1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_tim_ex.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L0xx_HAL_TIM_EX_H 38 #define __STM32L0xx_HAL_TIM_EX_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l0xx_hal_def.h" 46 47 /** @addtogroup STM32L0xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @defgroup TIMEx TIMEx 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup TIM_Exported_Types TIM Exported Types 57 * @{ 58 */ 59 /** 60 * @brief TIM Master configuration Structure definition 61 */ 62 typedef struct { 63 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 64 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 65 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 66 This parameter can be a value of @ref TIM_Master_Slave_Mode */ 67 }TIM_MasterConfigTypeDef; 68 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants 75 * @{ 76 */ 77 78 /** @defgroup TIMEx_Trigger_Selection Trigger selection 79 * @{ 80 */ 81 #define TIM_TRGO_RESET ((uint32_t)0x0000U) 82 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) 83 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) 84 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 85 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) 86 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) 87 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) 88 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 89 90 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 91 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 92 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 93 ((__SOURCE__) == TIM_TRGO_OC1) || \ 94 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 95 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 96 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 97 ((__SOURCE__) == TIM_TRGO_OC4REF)) 98 99 /** 100 * @} 101 */ 102 103 /** @defgroup TIMEx_Remap Remaping 104 * @{ 105 */ 106 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ 107 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 108 109 #define TIM2_ETR_GPIO ((uint32_t)0x0U) 110 #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 111 #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0) 112 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) 113 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) 114 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP 115 116 #elif defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) 117 118 #define TIM2_ETR_GPIO ((uint32_t)0x0U) 119 #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0) 120 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) 121 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) 122 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP 123 124 #else 125 126 #define TIM2_ETR_GPIO ((uint32_t)0x0U) 127 #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 128 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) 129 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) 130 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP 131 132 #endif 133 134 135 136 #define TIM2_TI4_GPIO ((uint32_t)0x0U) 137 #define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0 138 #define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1 139 140 #define TIM21_ETR_GPIO ((uint32_t)0x0U) 141 #define TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0 142 #define TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1 143 #define TIM21_ETR_LSE TIM21_OR_ETR_RMP 144 #define TIM21_TI1_GPIO ((uint32_t)0x0U) 145 #define TIM21_TI1_MCO TIM21_OR_TI1_RMP 146 #define TIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0 147 #define TIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1 148 #define TIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1) 149 #define TIM21_TI1_LSE TIM21_OR_TI1_RMP_2 150 #define TIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0) 151 #define TIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1) 152 #define TIM21_TI2_GPIO ((uint32_t)0x0U) 153 #define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP 154 155 #if !defined(STM32L011xx) && !defined(STM32L021xx) 156 #define TIM22_ETR_GPIO ((uint32_t)0x0U) 157 #define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0 158 #define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1 159 #define TIM22_ETR_LSE TIM22_OR_ETR_RMP 160 #define TIM22_TI1_GPIO1 ((uint32_t)0x0U) 161 #define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0 162 #define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1 163 #define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP 164 #endif 165 166 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ 167 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 168 169 #define TIM3_TI4_GPIO_DEF ((uint32_t)0x0U) 170 #define TIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP 171 #define TIM3_TI2_GPIO_DEF ((uint32_t)0x0U) 172 #define TIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP 173 #define TIM3_TI1_USB_SOF ((uint32_t)0x0U) 174 #define TIM3_TI1_GPIO TIM3_OR_TI1_RMP 175 #define TIM3_ETR_GPIO ((uint32_t)0x0U) 176 #define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1 177 178 #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ 179 180 181 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ 182 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 183 184 185 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ 186 ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \ 187 (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \ 188 (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || \ 189 (((__INSTANCE__) == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP)))) 190 191 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ 192 ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 193 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 194 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 195 ((__CHANNEL__) == TIM_CHANNEL_4))) || \ 196 (((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 197 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 198 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 199 ((__CHANNEL__) == TIM_CHANNEL_4))) || \ 200 (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 201 ((__CHANNEL__) == TIM_CHANNEL_2))) || \ 202 (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 203 ((__CHANNEL__) == TIM_CHANNEL_2)))) 204 205 #elif defined (STM32L011xx) || defined (STM32L021xx) 206 207 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ 208 ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \ 209 (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP)))) 210 211 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ 212 ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 213 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 214 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 215 ((__CHANNEL__) == TIM_CHANNEL_4))) || \ 216 (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 217 ((__CHANNEL__) == TIM_CHANNEL_2)))) 218 219 #else 220 221 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ 222 ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \ 223 (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \ 224 (((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP)))) 225 226 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ 227 ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 228 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 229 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 230 ((__CHANNEL__) == TIM_CHANNEL_4))) || \ 231 (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 232 ((__CHANNEL__) == TIM_CHANNEL_2))) || \ 233 (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ 234 ((__CHANNEL__) == TIM_CHANNEL_2)))) 235 236 #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ 237 238 239 /** 240 * @} 241 */ 242 243 /** 244 * @} 245 */ 246 247 248 /* Exported macro ------------------------------------------------------------*/ 249 /* Exported functions --------------------------------------------------------*/ 250 /* Control functions ***********************************************************/ 251 252 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions 253 * @{ 254 */ 255 256 /** @defgroup TIMEx_Exported_Functions_Group1 TIMEx Peripheral Control functions 257 * @{ 258 */ 259 260 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); 261 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); 262 263 /** 264 * @} 265 */ 266 267 /** 268 * @} 269 */ 270 271 /** 272 * @} 273 */ 274 275 /** 276 * @} 277 */ 278 #ifdef __cplusplus 279 } 280 #endif 281 282 #endif /* __STM32L0xx_HAL_TIM_EX_H */ 283 284 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 285 286
