1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L0xx_HAL_TIM_H 38 #define __STM32L0xx_HAL_TIM_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l0xx_hal_def.h" 46 47 /** @addtogroup STM32L0xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @defgroup TIM TIM (Timer) 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 57 /** @defgroup TIM_Exported_Types TIM Exported Types 58 * @{ 59 */ 60 61 /** @defgroup TIM_Base_Configuration TIM base configuration structure 62 * @{ 63 */ 64 /** 65 * @brief TIM Time base Configuration Structure definition 66 */ 67 typedef struct 68 { 69 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 70 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 71 72 uint32_t CounterMode; /*!< Specifies the counter mode. 73 This parameter can be a value of @ref TIM_Counter_Mode */ 74 75 uint32_t Period; /*!< Specifies the period value to be loaded into the active 76 Auto-Reload Register at the next update event. 77 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 78 79 uint32_t ClockDivision; /*!< Specifies the clock division. 80 This parameter can be a value of @ref TIM_ClockDivision */ 81 } TIM_Base_InitTypeDef; 82 /** 83 * @} 84 */ 85 86 /** @defgroup TIM_Output_Configuration TIM output compare configuration structure 87 * @{ 88 */ 89 90 /** 91 * @brief TIM Output Compare Configuration Structure definition 92 */ 93 94 typedef struct 95 { 96 uint32_t OCMode; /*!< Specifies the TIM mode. 97 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 98 99 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 100 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 101 102 uint32_t OCPolarity; /*!< Specifies the output polarity. 103 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 104 105 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 106 This parameter can be a value of @ref TIM_Output_Fast_State 107 @note This parameter is valid only in PWM1 and PWM2 mode. */ 108 109 } TIM_OC_InitTypeDef; 110 /** 111 * @} 112 */ 113 114 /** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure 115 * @{ 116 */ 117 /** 118 * @brief TIM One Pulse Mode Configuration Structure definition 119 */ 120 typedef struct 121 { 122 uint32_t OCMode; /*!< Specifies the TIM mode. 123 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 124 125 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 126 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 127 128 uint32_t OCPolarity; /*!< Specifies the output polarity. 129 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 130 131 132 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 133 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 134 135 uint32_t ICSelection; /*!< Specifies the input. 136 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 137 138 uint32_t ICFilter; /*!< Specifies the input capture filter. 139 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 140 } TIM_OnePulse_InitTypeDef; 141 /** 142 * @} 143 */ 144 145 /** @defgroup TIM_Input_Capture TIM input capture configuration structure 146 * @{ 147 */ 148 /** 149 * @brief TIM Input Capture Configuration Structure definition 150 */ 151 152 typedef struct 153 { 154 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 155 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 156 157 uint32_t ICSelection; /*!< Specifies the input. 158 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 159 160 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 161 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 162 163 uint32_t ICFilter; /*!< Specifies the input capture filter. 164 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 165 } TIM_IC_InitTypeDef; 166 /** 167 * @} 168 */ 169 170 /** @defgroup TIM_Encoder TIM encoder configuration structure 171 * @{ 172 */ 173 /** 174 * @brief TIM Encoder Configuration Structure definition 175 */ 176 177 typedef struct 178 { 179 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 180 This parameter can be a value of @ref TIM_Encoder_Mode */ 181 182 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 183 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 184 185 uint32_t IC1Selection; /*!< Specifies the input. 186 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 187 188 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 190 191 uint32_t IC1Filter; /*!< Specifies the input capture filter. 192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 193 194 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 195 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 196 197 uint32_t IC2Selection; /*!< Specifies the input. 198 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 199 200 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 201 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 202 203 uint32_t IC2Filter; /*!< Specifies the input capture filter. 204 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 205 } TIM_Encoder_InitTypeDef; 206 /** 207 * @} 208 */ 209 210 /** @defgroup TIM_Clock_Configuration TIM clock configuration structure 211 * @{ 212 */ 213 /** 214 * @brief Clock Configuration Handle Structure definition 215 */ 216 typedef struct 217 { 218 uint32_t ClockSource; /*!< TIM clock sources. 219 This parameter can be a value of @ref TIM_Clock_Source */ 220 uint32_t ClockPolarity; /*!< TIM clock polarity. 221 This parameter can be a value of @ref TIM_Clock_Polarity */ 222 uint32_t ClockPrescaler; /*!< TIM clock prescaler. 223 This parameter can be a value of @ref TIM_Clock_Prescaler */ 224 uint32_t ClockFilter; /*!< TIM clock filter. 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 226 }TIM_ClockConfigTypeDef; 227 /** 228 * @} 229 */ 230 231 /** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure 232 * @{ 233 */ 234 /** 235 * @brief Clear Input Configuration Handle Structure definition 236 */ 237 typedef struct 238 { 239 uint32_t ClearInputState; /*!< TIM clear Input state. 240 This parameter can be ENABLE or DISABLE */ 241 uint32_t ClearInputSource; /*!< TIM clear Input sources. 242 This parameter can be a value of @ref TIM_ClearInput_Source */ 243 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. 244 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 245 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. 246 This parameter can be a value of @ref TIM_ClearInput_Prescaler */ 247 uint32_t ClearInputFilter; /*!< TIM Clear Input filter. 248 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 249 }TIM_ClearInputConfigTypeDef; 250 /** 251 * @} 252 */ 253 254 /** @defgroup TIM_Slave_Configuratio TIM slave configuration structure 255 * @{ 256 */ 257 /** 258 * @brief TIM Slave configuration Structure definition 259 */ 260 typedef struct { 261 uint32_t SlaveMode; /*!< Slave mode selection. 262 This parameter can be a value of @ref TIM_Slave_Mode */ 263 uint32_t InputTrigger; /*!< Input Trigger source. 264 This parameter can be a value of @ref TIM_Trigger_Selection */ 265 uint32_t TriggerPolarity; /*!< Input Trigger polarity. 266 This parameter can be a value of @ref TIM_Trigger_Polarity */ 267 uint32_t TriggerPrescaler; /*!< Input trigger prescaler. 268 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 269 uint32_t TriggerFilter; /*!< Input trigger filter. 270 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 271 272 }TIM_SlaveConfigTypeDef; 273 /** 274 * @} 275 */ 276 277 /** @defgroup TIM_State_Definition TIM state definition 278 * @{ 279 */ 280 /** 281 * @brief HAL State structures definition 282 */ 283 typedef enum 284 { 285 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 286 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 287 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 288 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 289 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 290 }HAL_TIM_StateTypeDef; 291 /** 292 * @} 293 */ 294 295 /** @defgroup TIM_Active_Channel TIM active channel definition 296 * @{ 297 */ 298 /** 299 * @brief HAL Active channel structures definition 300 */ 301 typedef enum 302 { 303 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 304 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 305 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 306 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 307 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 308 }HAL_TIM_ActiveChannel; 309 /** 310 * @} 311 */ 312 313 /** @defgroup TIM_Handle TIM handler 314 * @{ 315 */ 316 /** 317 * @brief TIM Time Base Handle Structure definition 318 */ 319 typedef struct 320 { 321 TIM_TypeDef *Instance; /*!< Register base address */ 322 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 323 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 324 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 325 This array is accessed by a @ref DMA_Handle_index */ 326 HAL_LockTypeDef Lock; /*!< Locking object */ 327 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 328 }TIM_HandleTypeDef; 329 /** 330 * @} 331 */ 332 333 /** 334 * @} 335 */ 336 /* Exported constants --------------------------------------------------------*/ 337 /** @defgroup TIM_Exported_Constants TIM Exported Constants 338 * @{ 339 */ 340 341 342 #define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFFU) 343 344 #define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU) 345 346 347 /** @defgroup TIM_Input_Channel_Polarity Input channel polarity 348 * @{ 349 */ 350 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */ 351 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ 352 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup TIM_ETR_Polarity ETR polarity 358 * @{ 359 */ 360 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ 361 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */ 362 /** 363 * @} 364 */ 365 366 /** @defgroup TIM_ETR_Prescaler ETR prescaler 367 * @{ 368 */ 369 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */ 370 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ 371 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ 372 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup TIM_Counter_Mode Counter mode 378 * @{ 379 */ 380 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000U) 381 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR 382 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 383 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 384 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS 385 /** 386 * @} 387 */ 388 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 389 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 390 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 391 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 392 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 393 394 395 396 397 /** @defgroup TIM_ClockDivision Clock division 398 * @{ 399 */ 400 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U) 401 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) 402 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) 403 /** 404 * @} 405 */ 406 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 407 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 408 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 409 410 411 /** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes 412 * @{ 413 */ 414 #define TIM_OCMODE_TIMING ((uint32_t)0x0000U) 415 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) 416 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) 417 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) 418 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) 419 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) 420 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) 421 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) 422 /** 423 * @} 424 */ 425 426 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 427 ((__MODE__) == TIM_OCMODE_PWM2)) 428 429 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 430 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 431 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 432 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 433 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 434 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) 435 436 437 /** @defgroup TIM_Output_Compare_State Output compare state 438 * @{ 439 */ 440 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) 441 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) 442 /** 443 * @} 444 */ 445 446 /** @defgroup TIM_Output_Fast_State Output fast state 447 * @{ 448 */ 449 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000U) 450 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) 451 /** 452 * @} 453 */ 454 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 455 ((__STATE__) == TIM_OCFAST_ENABLE)) 456 457 /** @defgroup TIM_Output_Compare_N_State Output compare N state 458 * @{ 459 */ 460 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U) 461 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) 462 /** 463 * @} 464 */ 465 466 /** @defgroup TIM_Output_Compare_Polarity Output compare polarity 467 * @{ 468 */ 469 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U) 470 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) 471 /** 472 * @} 473 */ 474 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 475 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 476 477 /** @defgroup TIM_Channel TIM channels 478 * @{ 479 */ 480 #define TIM_CHANNEL_1 ((uint32_t)0x0000U) 481 #define TIM_CHANNEL_2 ((uint32_t)0x0004U) 482 #define TIM_CHANNEL_3 ((uint32_t)0x0008U) 483 #define TIM_CHANNEL_4 ((uint32_t)0x000CU) 484 #define TIM_CHANNEL_ALL ((uint32_t)0x0018U) 485 /** 486 * @} 487 */ 488 489 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 490 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 491 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 492 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 493 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 494 495 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 496 ((__CHANNEL__) == TIM_CHANNEL_2)) 497 498 499 /** @defgroup TIM_Input_Capture_Polarity Input capture polarity 500 * @{ 501 */ 502 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING 503 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING 504 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE 505 /** 506 * @} 507 */ 508 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 509 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 510 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 511 512 513 /** @defgroup TIM_Input_Capture_Selection Input capture selection 514 * @{ 515 */ 516 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be 517 connected to IC1, IC2, IC3 or IC4, respectively */ 518 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be 519 connected to IC2, IC1, IC4 or IC3, respectively */ 520 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 521 522 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 523 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 524 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 525 /** 526 * @} 527 */ 528 529 /** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler 530 * @{ 531 */ 532 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ 533 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ 534 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ 535 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ 536 /** 537 * @} 538 */ 539 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 540 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 541 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 542 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 543 544 /** @defgroup TIM_One_Pulse_Mode One pulse mode 545 * @{ 546 */ 547 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) 548 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U) 549 /** 550 * @} 551 */ 552 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 553 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 554 555 /** @defgroup TIM_Encoder_Mode Encoder_Mode 556 * @{ 557 */ 558 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) 559 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) 560 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) 561 /** 562 * @} 563 */ 564 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 565 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 566 ((__MODE__) == TIM_ENCODERMODE_TI12)) 567 568 /** @defgroup TIM_Interrupt_definition Interrupt definition 569 * @{ 570 */ 571 #define TIM_IT_UPDATE (TIM_DIER_UIE) 572 #define TIM_IT_CC1 (TIM_DIER_CC1IE) 573 #define TIM_IT_CC2 (TIM_DIER_CC2IE) 574 #define TIM_IT_CC3 (TIM_DIER_CC3IE) 575 #define TIM_IT_CC4 (TIM_DIER_CC4IE) 576 #define TIM_IT_TRIGGER (TIM_DIER_TIE) 577 /** 578 * @} 579 */ 580 581 /** @defgroup TIM_DMA_sources DMA sources 582 * @{ 583 */ 584 #define TIM_DMA_UPDATE (TIM_DIER_UDE) 585 #define TIM_DMA_CC1 (TIM_DIER_CC1DE) 586 #define TIM_DMA_CC2 (TIM_DIER_CC2DE) 587 #define TIM_DMA_CC3 (TIM_DIER_CC3DE) 588 #define TIM_DMA_CC4 (TIM_DIER_CC4DE) 589 #define TIM_DMA_TRIGGER (TIM_DIER_TDE) 590 /** 591 * @} 592 */ 593 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 594 595 596 597 /** @defgroup TIM_Event_Source Event sources 598 * @{ 599 */ 600 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG 601 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G 602 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G 603 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G 604 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G 605 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG 606 /** 607 * @} 608 */ 609 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 610 611 612 /** @defgroup TIM_Flag_definition Flag definition 613 * @{ 614 */ 615 #define TIM_FLAG_UPDATE (TIM_SR_UIF) 616 #define TIM_FLAG_CC1 (TIM_SR_CC1IF) 617 #define TIM_FLAG_CC2 (TIM_SR_CC2IF) 618 #define TIM_FLAG_CC3 (TIM_SR_CC3IF) 619 #define TIM_FLAG_CC4 (TIM_SR_CC4IF) 620 #define TIM_FLAG_TRIGGER (TIM_SR_TIF) 621 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) 622 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) 623 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) 624 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) 625 /** 626 * @} 627 */ 628 629 /** @defgroup TIM_Clock_Source Clock source 630 * @{ 631 */ 632 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) 633 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) 634 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U) 635 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) 636 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) 637 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) 638 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) 639 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) 640 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) 641 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) 642 /** 643 * @} 644 */ 645 646 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 647 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 648 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 649 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 650 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 651 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 652 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 653 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 654 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 655 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 656 657 658 /** @defgroup TIM_Clock_Polarity Clock polarity 659 * @{ 660 */ 661 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 662 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 663 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 664 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 665 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 666 /** 667 * @} 668 */ 669 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 670 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 671 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 672 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 673 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 674 675 /** @defgroup TIM_Clock_Prescaler Clock prescaler 676 * @{ 677 */ 678 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 679 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 680 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 681 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 682 /** 683 * @} 684 */ 685 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 686 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 687 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 688 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 689 690 691 /* Check clock filter */ 692 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 693 694 /** @defgroup TIM_ClearInput_Source Clear input source 695 * @{ 696 */ 697 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) 698 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) 699 /** 700 * @} 701 */ 702 703 #define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 704 ((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR)) 705 706 707 /** @defgroup TIM_ClearInput_Polarity Clear input polarity 708 * @{ 709 */ 710 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 711 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 712 /** 713 * @} 714 */ 715 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 716 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 717 718 719 /** @defgroup TIM_ClearInput_Prescaler Clear input prescaler 720 * @{ 721 */ 722 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 723 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 724 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 725 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 726 /** 727 * @} 728 */ 729 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 730 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 731 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 732 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 733 734 735 /* Check IC filter */ 736 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) 737 738 739 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 740 * @{ 741 */ 742 #define TIM_TRGO_RESET ((uint32_t)0x0000U) 743 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) 744 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) 745 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 746 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) 747 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) 748 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) 749 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 750 /** 751 * @} 752 */ 753 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 754 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 755 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 756 ((__SOURCE__) == TIM_TRGO_OC1) || \ 757 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 758 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 759 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 760 ((__SOURCE__) == TIM_TRGO_OC4REF)) 761 762 763 764 /** @defgroup TIM_Slave_Mode Slave mode 765 * @{ 766 */ 767 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U) 768 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004U) 769 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005U) 770 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006U) 771 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007U) 772 /** 773 * @} 774 */ 775 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 776 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 777 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 778 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 779 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) 780 781 /** @defgroup TIM_Master_Slave_Mode Master slave mode 782 * @{ 783 */ 784 785 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U) 786 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U) 787 /** 788 * @} 789 */ 790 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 791 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 792 793 /** @defgroup TIM_Trigger_Selection Trigger selection 794 * @{ 795 */ 796 #define TIM_TS_ITR0 ((uint32_t)0x0000U) 797 #define TIM_TS_ITR1 ((uint32_t)0x0010U) 798 #define TIM_TS_ITR2 ((uint32_t)0x0020U) 799 #define TIM_TS_ITR3 ((uint32_t)0x0030U) 800 #define TIM_TS_TI1F_ED ((uint32_t)0x0040U) 801 #define TIM_TS_TI1FP1 ((uint32_t)0x0050U) 802 #define TIM_TS_TI2FP2 ((uint32_t)0x0060U) 803 #define TIM_TS_ETRF ((uint32_t)0x0070U) 804 #define TIM_TS_NONE ((uint32_t)0xFFFFU) 805 /** 806 * @} 807 */ 808 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 809 ((__SELECTION__) == TIM_TS_ITR1) || \ 810 ((__SELECTION__) == TIM_TS_ITR2) || \ 811 ((__SELECTION__) == TIM_TS_ITR3) || \ 812 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 813 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 814 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 815 ((__SELECTION__) == TIM_TS_ETRF)) 816 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 817 ((__SELECTION__) == TIM_TS_ITR1) || \ 818 ((__SELECTION__) == TIM_TS_ITR2) || \ 819 ((__SELECTION__) == TIM_TS_ITR3) || \ 820 ((__SELECTION__) == TIM_TS_NONE)) 821 822 823 /** @defgroup TIM_Trigger_Polarity Trigger polarity 824 * @{ 825 */ 826 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 827 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 828 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 829 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 830 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 831 /** 832 * @} 833 */ 834 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 835 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 836 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 837 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 838 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 839 840 841 /** @defgroup TIM_Trigger_Prescaler Trigger prescaler 842 * @{ 843 */ 844 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 845 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 846 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 847 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 848 /** 849 * @} 850 */ 851 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 852 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 853 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 854 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 855 856 857 /* Check trigger filter */ 858 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 859 860 861 /** @defgroup TIM_TI1_Selection TI1 selection 862 * @{ 863 */ 864 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U) 865 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) 866 /** 867 * @} 868 */ 869 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 870 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 871 872 873 /** @defgroup TIM_DMA_Base_address DMA base address 874 * @{ 875 */ 876 #define TIM_DMABASE_CR1 (0x00000000U) 877 #define TIM_DMABASE_CR2 (0x00000001U) 878 #define TIM_DMABASE_SMCR (0x00000002U) 879 #define TIM_DMABASE_DIER (0x00000003U) 880 #define TIM_DMABASE_SR (0x00000004U) 881 #define TIM_DMABASE_EGR (0x00000005U) 882 #define TIM_DMABASE_CCMR1 (0x00000006U) 883 #define TIM_DMABASE_CCMR2 (0x00000007U) 884 #define TIM_DMABASE_CCER (0x00000008U) 885 #define TIM_DMABASE_CNT (0x00000009U) 886 #define TIM_DMABASE_PSC (0x0000000AU) 887 #define TIM_DMABASE_ARR (0x0000000BU) 888 #define TIM_DMABASE_CCR1 (0x0000000DU) 889 #define TIM_DMABASE_CCR2 (0x0000000EU) 890 #define TIM_DMABASE_CCR3 (0x0000000FU) 891 #define TIM_DMABASE_CCR4 (0x00000010U) 892 #define TIM_DMABASE_DCR (0x00000012U) 893 #define TIM_DMABASE_OR (0x00000013U) 894 /** 895 * @} 896 */ 897 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 898 ((__BASE__) == TIM_DMABASE_CR2) || \ 899 ((__BASE__) == TIM_DMABASE_SMCR) || \ 900 ((__BASE__) == TIM_DMABASE_DIER) || \ 901 ((__BASE__) == TIM_DMABASE_SR) || \ 902 ((__BASE__) == TIM_DMABASE_EGR) || \ 903 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 904 ((__BASE__) == TIM_DMABASE_CCMR2 ) || \ 905 ((__BASE__) == TIM_DMABASE_CCER) || \ 906 ((__BASE__) == TIM_DMABASE_CNT) || \ 907 ((__BASE__) == TIM_DMABASE_PSC) || \ 908 ((__BASE__) == TIM_DMABASE_ARR) || \ 909 ((__BASE__) == TIM_DMABASE_CCR1) || \ 910 ((__BASE__) == TIM_DMABASE_CCR2) || \ 911 ((__BASE__) == TIM_DMABASE_CCR3) || \ 912 ((__BASE__) == TIM_DMABASE_CCR4) || \ 913 ((__BASE__) == TIM_DMABASE_DCR) || \ 914 ((__BASE__) == TIM_DMABASE_OR)) 915 916 917 /** @defgroup TIM_DMA_Burst_Length DMA burst length 918 * @{ 919 */ 920 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) 921 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) 922 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) 923 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) 924 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) 925 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) 926 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) 927 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) 928 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) 929 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) 930 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) 931 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) 932 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) 933 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) 934 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) 935 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) 936 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) 937 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) 938 /** 939 * @} 940 */ 941 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) || \ 942 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 943 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 944 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 945 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 946 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 947 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 948 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 949 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) || \ 950 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 951 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) || \ 952 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 953 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 954 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 955 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 956 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 957 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 958 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS )) 959 960 961 /* Check IC filter */ 962 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 963 964 /** @defgroup DMA_Handle_index DMA handle index 965 * @{ 966 */ 967 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ 968 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 969 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 970 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 971 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 972 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Trigger DMA requests */ 973 /** 974 * @} 975 */ 976 977 /** @defgroup Channel_CC_State Channel state 978 * @{ 979 */ 980 #define TIM_CCx_ENABLE ((uint32_t)0x0001U) 981 #define TIM_CCx_DISABLE ((uint32_t)0x0000U) 982 /** 983 * @} 984 */ 985 986 /** 987 * @} 988 */ 989 990 /* Exported macro ------------------------------------------------------------*/ 991 /** @defgroup TIM_Exported_Macro TIM Exported Macro 992 * @{ 993 */ 994 995 /** @brief Reset UART handle state 996 * @param __HANDLE__ : TIM handle 997 * @retval None 998 */ 999 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 1000 1001 /** 1002 * @brief Enable the TIM peripheral. 1003 * @param __HANDLE__ : TIM handle 1004 * @retval None 1005 */ 1006 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1007 1008 /* The counter of a timer instance is disabled only if all the CCx channels have 1009 been disabled */ 1010 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1011 1012 /** 1013 * @brief Disable the TIM peripheral. 1014 * @param __HANDLE__ : TIM handle 1015 * @retval None 1016 */ 1017 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1018 do { \ 1019 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ 1020 { \ 1021 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1022 } \ 1023 } while(0) 1024 1025 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1026 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1027 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1028 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1029 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1030 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1031 1032 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 1033 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1034 1035 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1036 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1037 1038 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1039 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1040 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1041 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1042 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) 1043 1044 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1045 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ 1046 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ 1047 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ 1048 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) 1049 1050 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1051 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1052 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1053 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1054 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) 1055 1056 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1057 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1058 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1059 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1060 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) 1061 1062 /** 1063 * @brief Sets the TIM Capture Compare Register value on runtime without 1064 * calling another time ConfigChannel function. 1065 * @param __HANDLE__ : TIM handle. 1066 * @param __CHANNEL__ : TIM Channels to be configured. 1067 * This parameter can be one of the following values: 1068 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1069 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1070 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1071 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1072 * @param __COMPARE__: specifies the Capture Compare register new value. 1073 * @retval None 1074 */ 1075 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1076 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) 1077 1078 /** 1079 * @brief Gets the TIM Capture Compare Register value on runtime 1080 * @param __HANDLE__ : TIM handle. 1081 * @param __CHANNEL__ : TIM Channel associated with the capture compare register 1082 * This parameter can be one of the following values: 1083 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1084 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1085 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1086 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1087 * @retval None 1088 */ 1089 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1090 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) 1091 1092 /** 1093 * @brief Sets the TIM Counter Register value on runtime. 1094 * @param __HANDLE__ : TIM handle. 1095 * @param __COUNTER__: specifies the Counter register new value. 1096 * @retval None 1097 */ 1098 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1099 1100 /** 1101 * @brief Gets the TIM Counter Register value on runtime. 1102 * @param __HANDLE__ : TIM handle. 1103 * @retval None 1104 */ 1105 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1106 1107 /** 1108 * @brief Sets the TIM Autoreload Register value on runtime without calling 1109 * another time any Init function. 1110 * @param __HANDLE__ : TIM handle. 1111 * @param __AUTORELOAD__: specifies the Counter register new value. 1112 * @retval None 1113 */ 1114 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1115 do{ \ 1116 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1117 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1118 } while(0) 1119 /** 1120 * @brief Gets the TIM Autoreload Register value on runtime 1121 * @param __HANDLE__ : TIM handle. 1122 * @retval None 1123 */ 1124 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1125 1126 /** 1127 * @brief Sets the TIM Clock Division value on runtime without calling 1128 * another time any Init function. 1129 * @param __HANDLE__ : TIM handle. 1130 * @param __CKD__: specifies the clock division value. 1131 * This parameter can be one of the following value: 1132 * @arg TIM_CLOCKDIVISION_DIV1 1133 * @arg TIM_CLOCKDIVISION_DIV2 1134 * @arg TIM_CLOCKDIVISION_DIV4 1135 * @retval None 1136 */ 1137 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1138 do{ \ 1139 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ 1140 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1141 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1142 } while(0) 1143 /** 1144 * @brief Gets the TIM Clock Division value on runtime 1145 * @param __HANDLE__ : TIM handle. 1146 * @retval None 1147 */ 1148 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1149 1150 /** 1151 * @brief Sets the TIM Input Capture prescaler on runtime without calling 1152 * another time HAL_TIM_IC_ConfigChannel() function. 1153 * @param __HANDLE__ : TIM handle. 1154 * @param __CHANNEL__ : TIM Channels to be configured. 1155 * This parameter can be one of the following values: 1156 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1157 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1158 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1159 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1160 * @param __ICPSC__: specifies the Input Capture4 prescaler new value. 1161 * This parameter can be one of the following values: 1162 * @arg TIM_ICPSC_DIV1: no prescaler 1163 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1164 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1165 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1166 * @retval None 1167 */ 1168 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1169 do{ \ 1170 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1171 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1172 } while(0) 1173 1174 /** 1175 * @brief Gets the TIM Input Capture prescaler on runtime 1176 * @param __HANDLE__ : TIM handle. 1177 * @param __CHANNEL__ : TIM Channels to be configured. 1178 * This parameter can be one of the following values: 1179 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1180 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1181 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1182 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1183 * @retval None 1184 */ 1185 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1186 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1187 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ 1188 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1189 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1190 1191 1192 /** 1193 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register 1194 * @param __HANDLE__: TIM handle. 1195 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1196 * overflow/underflow generates an update interrupt or DMA request (if 1197 * enabled) 1198 * @retval None 1199 */ 1200 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ 1201 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) 1202 1203 /** 1204 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register 1205 * @param __HANDLE__: TIM handle. 1206 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1207 * following events generate an update interrupt or DMA request (if 1208 * enabled): 1209 * Counter overflow/underflow 1210 * Setting the UG bit 1211 * Update generation through the slave mode controller 1212 * @retval None 1213 */ 1214 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ 1215 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) 1216 1217 /** 1218 * @brief Sets the TIM Capture x input polarity on runtime. 1219 * @param __HANDLE__: TIM handle. 1220 * @param __CHANNEL__: TIM Channels to be configured. 1221 * This parameter can be one of the following values: 1222 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1223 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1224 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1225 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1226 * @param __POLARITY__: Polarity for TIx source 1227 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1228 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1229 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1230 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. 1231 * @retval None 1232 */ 1233 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1234 do{ \ 1235 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1236 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1237 }while(0) 1238 1239 /** 1240 * @} 1241 */ 1242 1243 /* Include TIM HAL Extension module */ 1244 #include "stm32l0xx_hal_tim_ex.h" 1245 1246 /* Exported functions --------------------------------------------------------*/ 1247 /** @defgroup TIM_Exported_Functions TIM Exported Functions 1248 * @{ 1249 */ 1250 1251 /* Exported functions --------------------------------------------------------*/ 1252 /* Time Base functions ********************************************************/ 1253 1254 /** @defgroup TIM_Exported_Functions_Group1 Timer Base functions 1255 * @brief Time Base functions 1256 * @{ 1257 */ 1258 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1259 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1260 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 1261 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 1262 /* Blocking mode: Polling */ 1263 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 1264 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 1265 /* Non-Blocking mode: Interrupt */ 1266 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 1267 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 1268 /* Non-Blocking mode: DMA */ 1269 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 1270 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 1271 1272 /** 1273 * @} 1274 */ 1275 1276 1277 /* Timer Output Compare functions **********************************************/ 1278 1279 /** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions 1280 * @brief Timer Output Compare functions 1281 * @{ 1282 */ 1283 1284 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 1285 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 1286 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 1287 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 1288 /* Blocking mode: Polling */ 1289 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1290 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1291 /* Non-Blocking mode: Interrupt */ 1292 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1293 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1294 /* Non-Blocking mode: DMA */ 1295 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1296 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1297 /** 1298 * @} 1299 */ 1300 1301 1302 /* Timer PWM functions *********************************************************/ 1303 1304 /** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions 1305 * @brief Timer PWM functions 1306 * @{ 1307 */ 1308 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 1309 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 1310 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 1311 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 1312 /* Blocking mode: Polling */ 1313 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1314 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1315 /* Non-Blocking mode: Interrupt */ 1316 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1317 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1318 /* Non-Blocking mode: DMA */ 1319 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1320 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1321 /** 1322 * @} 1323 */ 1324 1325 /* Timer Input Capture functions ***********************************************/ 1326 1327 /** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions 1328 * @brief Timer Input Capture functions 1329 * @{ 1330 */ 1331 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 1332 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 1333 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 1334 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 1335 /* Blocking mode: Polling */ 1336 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1337 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1338 /* Non-Blocking mode: Interrupt */ 1339 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1340 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1341 /* Non-Blocking mode: DMA */ 1342 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1343 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1344 /** 1345 * @} 1346 */ 1347 1348 /* Timer One Pulse functions ***************************************************/ 1349 1350 /** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions 1351 * @brief Timer One Pulse functions 1352 * @{ 1353 */ 1354 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 1355 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 1356 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 1357 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 1358 /* Blocking mode: Polling */ 1359 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1360 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1361 1362 /* Non-Blocking mode: Interrupt */ 1363 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1364 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1365 1366 /** 1367 * @} 1368 */ 1369 1370 /* Timer Encoder functions *****************************************************/ 1371 1372 /** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions 1373 * @brief Timer Encoder functions 1374 * @{ 1375 */ 1376 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); 1377 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 1378 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 1379 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 1380 /* Blocking mode: Polling */ 1381 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1382 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1383 /* Non-Blocking mode: Interrupt */ 1384 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1385 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1386 /* Non-Blocking mode: DMA */ 1387 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); 1388 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1389 1390 /** 1391 * @} 1392 */ 1393 1394 /* Interrupt Handler functions **********************************************/ 1395 1396 /** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management 1397 * @brief Interrupt Handler functions 1398 * @{ 1399 */ 1400 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 1401 /** 1402 * @} 1403 */ 1404 1405 /* Control functions *********************************************************/ 1406 1407 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions 1408 * @brief Control functions 1409 * @{ 1410 */ 1411 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); 1412 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); 1413 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); 1414 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); 1415 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); 1416 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); 1417 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 1418 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); 1419 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); 1420 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 1421 uint32_t *BurstBuffer, uint32_t BurstLength); 1422 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 1423 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 1424 uint32_t *BurstBuffer, uint32_t BurstLength); 1425 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 1426 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 1427 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 1428 1429 /** 1430 * @} 1431 */ 1432 1433 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 1434 1435 /** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions 1436 * @brief Callback functions 1437 * @{ 1438 */ 1439 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 1440 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 1441 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 1442 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 1443 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 1444 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 1445 /** 1446 * @} 1447 */ 1448 1449 1450 /* Peripheral State functions **************************************************/ 1451 1452 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 1453 * @brief Peripheral State functions 1454 * @{ 1455 */ 1456 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 1457 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 1458 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 1459 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 1460 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 1461 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 1462 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 1463 void TIM_DMAError(DMA_HandleTypeDef *hdma); 1464 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 1465 1466 /** 1467 * @} 1468 */ 1469 1470 /** 1471 * @} 1472 */ 1473 1474 /* Define the private group ***********************************/ 1475 /**************************************************************/ 1476 /** @defgroup TIM_Private TIM Private 1477 * @{ 1478 */ 1479 /** 1480 * @} 1481 */ 1482 /**************************************************************/ 1483 1484 /** 1485 * @} 1486 */ 1487 1488 /** 1489 * @} 1490 */ 1491 1492 #ifdef __cplusplus 1493 } 1494 #endif 1495 1496 #endif /* __STM32L0xx_HAL_TIM_H */ 1497 1498 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1499 1500
