1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_smbus.h 4 * @author MCD Application Team 5 * @brief Header file of SMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L0xx_HAL_SMBUS_H 38 #define __STM32L0xx_HAL_SMBUS_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l0xx_hal_def.h" 46 47 /** @addtogroup STM32L0xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup SMBUS 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types 57 * @{ 58 */ 59 60 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition 61 * @brief SMBUS Configuration Structure definition 62 * @{ 63 */ 64 typedef struct 65 { 66 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. 67 This parameter calculated by referring to SMBUS initialization 68 section in Reference manual */ 69 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 70 This parameter can be a value of @ref SMBUS_Analog_Filter */ 71 72 uint32_t OwnAddress1; /*!< Specifies the first device own address. 73 This parameter can be a 7-bit or 10-bit address. */ 74 75 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 76 This parameter can be a value of @ref SMBUS_addressing_mode */ 77 78 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 79 This parameter can be a value of @ref SMBUS_dual_addressing_mode */ 80 81 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 82 This parameter can be a 7-bit address. */ 83 84 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected 85 This parameter can be a value of @ref SMBUS_own_address2_masks. */ 86 87 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 88 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ 89 90 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 91 This parameter can be a value of @ref SMBUS_nostretch_mode */ 92 93 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 94 This parameter can be a value of @ref SMBUS_packet_error_check_mode */ 95 96 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 97 This parameter can be a value of @ref SMBUS_peripheral_mode */ 98 99 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. 100 (Enable bits and different timeout values) 101 This parameter calculated by referring to SMBUS initialization 102 section in Reference manual */ 103 } SMBUS_InitTypeDef; 104 /** 105 * @} 106 */ 107 108 /** @defgroup HAL_state_definition HAL state definition 109 * @brief HAL State definition 110 * @{ 111 */ 112 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ 113 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ 114 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ 115 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 116 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 117 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 118 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 119 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 120 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 121 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 122 /** 123 * @} 124 */ 125 126 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition 127 * @brief SMBUS Error Code definition 128 * @{ 129 */ 130 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 131 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 132 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 133 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 134 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 135 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 136 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 137 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 138 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 139 /** 140 * @} 141 */ 142 143 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 144 * @brief SMBUS handle Structure definition 145 * @{ 146 */ 147 typedef struct 148 { 149 I2C_TypeDef *Instance; /*!< SMBUS registers base address */ 150 151 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ 152 153 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ 154 155 uint16_t XferSize; /*!< SMBUS transfer size */ 156 157 __IO uint16_t XferCount; /*!< SMBUS transfer counter */ 158 159 __IO uint32_t XferOptions; /*!< SMBUS transfer options */ 160 161 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ 162 163 HAL_LockTypeDef Lock; /*!< SMBUS locking object */ 164 165 __IO uint32_t State; /*!< SMBUS communication state */ 166 167 __IO uint32_t ErrorCode; /*!< SMBUS Error code */ 168 169 } SMBUS_HandleTypeDef; 170 /** 171 * @} 172 */ 173 174 /** 175 * @} 176 */ 177 /* Exported constants --------------------------------------------------------*/ 178 179 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants 180 * @{ 181 */ 182 183 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter 184 * @{ 185 */ 186 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) 187 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 188 /** 189 * @} 190 */ 191 192 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode 193 * @{ 194 */ 195 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 196 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 197 /** 198 * @} 199 */ 200 201 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode 202 * @{ 203 */ 204 205 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) 206 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 207 /** 208 * @} 209 */ 210 211 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks 212 * @{ 213 */ 214 215 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) 216 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) 217 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) 218 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) 219 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) 220 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) 221 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) 222 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) 223 /** 224 * @} 225 */ 226 227 228 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode 229 * @{ 230 */ 231 #define SMBUS_GENERALCALL_DISABLE (0x00000000U) 232 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN 233 /** 234 * @} 235 */ 236 237 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode 238 * @{ 239 */ 240 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) 241 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 242 /** 243 * @} 244 */ 245 246 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode 247 * @{ 248 */ 249 #define SMBUS_PEC_DISABLE (0x00000000U) 250 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN 251 /** 252 * @} 253 */ 254 255 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode 256 * @{ 257 */ 258 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN 259 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) 260 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN 261 /** 262 * @} 263 */ 264 265 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition 266 * @{ 267 */ 268 269 #define SMBUS_SOFTEND_MODE (0x00000000U) 270 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD 271 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND 272 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE 273 /** 274 * @} 275 */ 276 277 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition 278 * @{ 279 */ 280 281 #define SMBUS_NO_STARTSTOP (0x00000000U) 282 #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) 283 #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 284 #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 285 /** 286 * @} 287 */ 288 289 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition 290 * @{ 291 */ 292 293 /* List of XferOptions in usage of : 294 * 1- Restart condition when direction change 295 * 2- No Restart condition in other use cases 296 */ 297 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE 298 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) 299 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 300 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 301 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 302 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 303 304 /* List of XferOptions in usage of : 305 * 1- Restart condition in all use cases (direction change or not) 306 */ 307 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 308 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 309 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 310 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 311 /** 312 * @} 313 */ 314 315 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition 316 * @brief SMBUS Interrupt definition 317 * Elements values convention: 0xXXXXXXXX 318 * - XXXXXXXX : Interrupt control mask 319 * @{ 320 */ 321 #define SMBUS_IT_ERRI I2C_CR1_ERRIE 322 #define SMBUS_IT_TCI I2C_CR1_TCIE 323 #define SMBUS_IT_STOPI I2C_CR1_STOPIE 324 #define SMBUS_IT_NACKI I2C_CR1_NACKIE 325 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE 326 #define SMBUS_IT_RXI I2C_CR1_RXIE 327 #define SMBUS_IT_TXI I2C_CR1_TXIE 328 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) 329 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) 330 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) 331 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) 332 /** 333 * @} 334 */ 335 336 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition 337 * @brief Flag definition 338 * Elements values convention: 0xXXXXYYYY 339 * - XXXXXXXX : Flag mask 340 * @{ 341 */ 342 343 #define SMBUS_FLAG_TXE I2C_ISR_TXE 344 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS 345 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE 346 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR 347 #define SMBUS_FLAG_AF I2C_ISR_NACKF 348 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF 349 #define SMBUS_FLAG_TC I2C_ISR_TC 350 #define SMBUS_FLAG_TCR I2C_ISR_TCR 351 #define SMBUS_FLAG_BERR I2C_ISR_BERR 352 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO 353 #define SMBUS_FLAG_OVR I2C_ISR_OVR 354 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR 355 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT 356 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT 357 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY 358 #define SMBUS_FLAG_DIR I2C_ISR_DIR 359 /** 360 * @} 361 */ 362 363 /** 364 * @} 365 */ 366 367 /* Exported macros ------------------------------------------------------------*/ 368 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros 369 * @{ 370 */ 371 372 /** @brief Reset SMBUS handle state. 373 * @param __HANDLE__ specifies the SMBUS Handle. 374 * @retval None 375 */ 376 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) 377 378 /** @brief Enable the specified SMBUS interrupts. 379 * @param __HANDLE__ specifies the SMBUS Handle. 380 * @param __INTERRUPT__ specifies the interrupt source to enable. 381 * This parameter can be one of the following values: 382 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 383 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 384 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 385 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 386 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 387 * @arg @ref SMBUS_IT_RXI RX interrupt enable 388 * @arg @ref SMBUS_IT_TXI TX interrupt enable 389 * 390 * @retval None 391 */ 392 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 393 394 /** @brief Disable the specified SMBUS interrupts. 395 * @param __HANDLE__ specifies the SMBUS Handle. 396 * @param __INTERRUPT__ specifies the interrupt source to disable. 397 * This parameter can be one of the following values: 398 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 399 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 400 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 401 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 402 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 403 * @arg @ref SMBUS_IT_RXI RX interrupt enable 404 * @arg @ref SMBUS_IT_TXI TX interrupt enable 405 * 406 * @retval None 407 */ 408 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 409 410 /** @brief Check whether the specified SMBUS interrupt source is enabled or not. 411 * @param __HANDLE__ specifies the SMBUS Handle. 412 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. 413 * This parameter can be one of the following values: 414 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 415 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 416 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 417 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 418 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 419 * @arg @ref SMBUS_IT_RXI RX interrupt enable 420 * @arg @ref SMBUS_IT_TXI TX interrupt enable 421 * 422 * @retval The new state of __IT__ (TRUE or FALSE). 423 */ 424 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 425 426 /** @brief Check whether the specified SMBUS flag is set or not. 427 * @param __HANDLE__ specifies the SMBUS Handle. 428 * @param __FLAG__ specifies the flag to check. 429 * This parameter can be one of the following values: 430 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 431 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status 432 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty 433 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 434 * @arg @ref SMBUS_FLAG_AF NACK received flag 435 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 436 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) 437 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload 438 * @arg @ref SMBUS_FLAG_BERR Bus error 439 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 440 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 441 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 442 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 443 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 444 * @arg @ref SMBUS_FLAG_BUSY Bus busy 445 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) 446 * 447 * @retval The new state of __FLAG__ (TRUE or FALSE). 448 */ 449 #define SMBUS_FLAG_MASK (0x0001FFFFU) 450 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) 451 452 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. 453 * @param __HANDLE__ specifies the SMBUS Handle. 454 * @param __FLAG__ specifies the flag to clear. 455 * This parameter can be any combination of the following values: 456 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 457 * @arg @ref SMBUS_FLAG_AF NACK received flag 458 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 459 * @arg @ref SMBUS_FLAG_BERR Bus error 460 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 461 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 462 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 463 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 464 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 465 * 466 * @retval None 467 */ 468 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 469 470 /** @brief Enable the specified SMBUS peripheral. 471 * @param __HANDLE__ specifies the SMBUS Handle. 472 * @retval None 473 */ 474 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 475 476 /** @brief Disable the specified SMBUS peripheral. 477 * @param __HANDLE__ specifies the SMBUS Handle. 478 * @retval None 479 */ 480 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 481 482 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. 483 * @param __HANDLE__ specifies the SMBUS Handle. 484 * @retval None 485 */ 486 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 487 488 /** 489 * @} 490 */ 491 492 493 /* Private constants ---------------------------------------------------------*/ 494 495 /* Private macros ------------------------------------------------------------*/ 496 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros 497 * @{ 498 */ 499 500 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ 501 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) 502 503 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 504 505 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ 506 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) 507 508 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ 509 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) 510 511 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ 512 ((MASK) == SMBUS_OA2_MASK01) || \ 513 ((MASK) == SMBUS_OA2_MASK02) || \ 514 ((MASK) == SMBUS_OA2_MASK03) || \ 515 ((MASK) == SMBUS_OA2_MASK04) || \ 516 ((MASK) == SMBUS_OA2_MASK05) || \ 517 ((MASK) == SMBUS_OA2_MASK06) || \ 518 ((MASK) == SMBUS_OA2_MASK07)) 519 520 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ 521 ((CALL) == SMBUS_GENERALCALL_ENABLE)) 522 523 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ 524 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) 525 526 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ 527 ((PEC) == SMBUS_PEC_ENABLE)) 528 529 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ 530 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ 531 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) 532 533 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ 534 ((MODE) == SMBUS_AUTOEND_MODE) || \ 535 ((MODE) == SMBUS_SOFTEND_MODE) || \ 536 ((MODE) == SMBUS_SENDPEC_MODE) || \ 537 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ 538 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ 539 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ 540 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) 541 542 543 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ 544 ((REQUEST) == SMBUS_GENERATE_START_READ) || \ 545 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ 546 ((REQUEST) == SMBUS_NO_STARTSTOP)) 547 548 549 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ 550 ((REQUEST) == SMBUS_NEXT_FRAME) || \ 551 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 552 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ 553 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 554 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ 555 IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) 556 557 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ 558 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 559 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ 560 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 561 562 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) 563 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) 564 565 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ 566 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 567 568 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) 569 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) 570 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 571 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) 572 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) 573 574 #define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) 575 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) 576 577 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 578 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 579 580 /** 581 * @} 582 */ 583 584 /* Exported functions --------------------------------------------------------*/ 585 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions 586 * @{ 587 */ 588 589 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 590 * @{ 591 */ 592 593 /* Initialization and de-initialization functions **********************************/ 594 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); 595 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); 596 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); 597 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); 598 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); 599 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); 600 601 /** 602 * @} 603 */ 604 605 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions 606 * @{ 607 */ 608 609 /* IO operation functions *****************************************************/ 610 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 611 * @{ 612 */ 613 /******* Blocking mode: Polling */ 614 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); 615 /** 616 * @} 617 */ 618 619 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 620 * @{ 621 */ 622 /******* Non-Blocking mode: Interrupt */ 623 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 624 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 625 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); 626 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 627 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 628 629 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 630 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 631 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); 632 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); 633 /** 634 * @} 635 */ 636 637 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 638 * @{ 639 */ 640 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 641 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 642 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 643 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 644 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 645 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 646 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 647 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 648 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); 649 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); 650 651 /** 652 * @} 653 */ 654 655 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 656 * @{ 657 */ 658 659 /* Peripheral State and Errors functions **************************************************/ 660 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); 661 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); 662 663 /** 664 * @} 665 */ 666 667 /** 668 * @} 669 */ 670 671 /* Private Functions ---------------------------------------------------------*/ 672 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions 673 * @{ 674 */ 675 /* Private functions are defined in stm32l0xx_hal_smbus.c file */ 676 /** 677 * @} 678 */ 679 680 /** 681 * @} 682 */ 683 684 /** 685 * @} 686 */ 687 688 /** 689 * @} 690 */ 691 692 #ifdef __cplusplus 693 } 694 #endif 695 696 697 #endif /* __STM32L0xx_HAL_SMBUS_H */ 698 699 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 700
