1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L0xx_HAL_RCC_H 38 #define __STM32L0xx_HAL_RCC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l0xx_hal_def.h" 46 47 /** @addtogroup STM32L0xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup RCC 52 * @{ 53 */ 54 55 /** @addtogroup RCC_Private_Constants 56 * @{ 57 */ 58 59 /** @defgroup RCC_Timeout RCC Timeout 60 * @{ 61 */ 62 63 /* Disable Backup domain write protection state change timeout */ 64 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ 65 /* LSE state change timeout */ 66 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 67 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ 68 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 69 #define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 70 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 71 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 72 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 73 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 74 #if defined(RCC_HSI48_SUPPORT) 75 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 76 #endif /* RCC_HSI48_SUPPORT */ 77 /** 78 * @} 79 */ 80 81 82 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion 83 * @brief RCC registers bit address in the alias region 84 * @{ 85 */ 86 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 87 /* --- CR Register ---*/ 88 /* Alias word address of HSION bit */ 89 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) 90 /* --- CFGR Register ---*/ 91 /* Alias word address of I2SSRC bit */ 92 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) 93 /* --- CSR Register ---*/ 94 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) 95 96 /* CR register byte 3 (Bits[23:16]) base address */ 97 #define RCC_CR_BYTE2_ADDRESS (0x40023802U) 98 99 /* CIER register byte 0 (Bits[0:8]) base address */ 100 #define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U)) 101 /** 102 * @} 103 */ 104 105 106 /* Defines used for Flags */ 107 #define CR_REG_INDEX ((uint8_t)1) 108 #define CSR_REG_INDEX ((uint8_t)2) 109 #define CRRCR_REG_INDEX ((uint8_t)3) 110 111 #define RCC_FLAG_MASK ((uint8_t)0x1F) 112 113 /** 114 * @} 115 */ 116 117 /** @addtogroup RCC_Private_Macros 118 * @{ 119 */ 120 #if defined(RCC_HSI48_SUPPORT) 121 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 122 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 123 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 124 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 125 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 126 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 127 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) 128 129 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 130 #else 131 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 132 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 133 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 134 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 135 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 136 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) 137 #endif /* RCC_HSI48_SUPPORT */ 138 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 139 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 140 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 141 ((__HSE__) == RCC_HSE_BYPASS)) 142 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 143 ((__LSE__) == RCC_LSE_BYPASS)) 144 #if defined(RCC_CR_HSIOUTEN) 145 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \ 146 ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN )) 147 #else 148 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \ 149 ((__HSI__) == RCC_HSI_DIV4)) 150 #endif /* RCC_CR_HSIOUTEN */ 151 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) 152 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF) 153 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 154 ((__RANGE__) == RCC_MSIRANGE_1) || \ 155 ((__RANGE__) == RCC_MSIRANGE_2) || \ 156 ((__RANGE__) == RCC_MSIRANGE_3) || \ 157 ((__RANGE__) == RCC_MSIRANGE_4) || \ 158 ((__RANGE__) == RCC_MSIRANGE_5) || \ 159 ((__RANGE__) == RCC_MSIRANGE_6)) 160 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 161 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 162 163 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 164 ((__PLL__) == RCC_PLL_ON)) 165 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ 166 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) 167 168 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ 169 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ 170 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ 171 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ 172 ((__MUL__) == RCC_PLL_MUL48)) 173 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 174 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 175 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 176 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) 177 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 178 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 179 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 180 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 181 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \ 182 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 183 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 184 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 185 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 186 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 187 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 188 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 189 ((__HCLK__) == RCC_SYSCLK_DIV512)) 190 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 191 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 192 ((__PCLK__) == RCC_HCLK_DIV16)) 193 #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) \ 194 || defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx) 195 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2) || ((__MCO__) == RCC_MCO3)) 196 #else 197 #define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO1) || ((__MCO__) == RCC_MCO2)) 198 199 #endif 200 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 201 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 202 ((__DIV__) == RCC_MCODIV_16)) 203 #if defined(RCC_CFGR_MCOSEL_HSI48) 204 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 205 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 206 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 207 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 208 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 209 #else 210 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 211 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 212 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 213 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 214 #endif /* RCC_CFGR_MCOSEL_HSI48 */ 215 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 216 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 217 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 218 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ 219 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ 220 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ 221 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16)) 222 223 /** 224 * @} 225 */ 226 227 /* Exported types ------------------------------------------------------------*/ 228 229 /** @defgroup RCC_Exported_Types RCC Exported Types 230 * @{ 231 */ 232 233 /** 234 * @brief RCC PLL configuration structure definition 235 */ 236 typedef struct 237 { 238 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 239 This parameter can be a value of @ref RCC_PLL_Config */ 240 241 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 242 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 243 244 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 245 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ 246 247 uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock 248 This parameter must be a value of @ref RCC_PLL_Division_Factor*/ 249 } RCC_PLLInitTypeDef; 250 251 /** 252 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 253 */ 254 typedef struct 255 { 256 uint32_t OscillatorType; /*!< The oscillators to be configured. 257 This parameter can be a value of @ref RCC_Oscillator_Type */ 258 259 uint32_t HSEState; /*!< The new state of the HSE. 260 This parameter can be a value of @ref RCC_HSE_Config */ 261 262 uint32_t LSEState; /*!< The new state of the LSE. 263 This parameter can be a value of @ref RCC_LSE_Config */ 264 265 uint32_t HSIState; /*!< The new state of the HSI. 266 This parameter can be a value of @ref RCC_HSI_Config */ 267 268 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 269 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 270 271 uint32_t LSIState; /*!< The new state of the LSI. 272 This parameter can be a value of @ref RCC_LSI_Config */ 273 274 #if defined(RCC_HSI48_SUPPORT) 275 uint32_t HSI48State; /*!< The new state of the HSI48. 276 This parameter can be a value of @ref RCC_HSI48_Config */ 277 278 #endif /* RCC_HSI48_SUPPORT */ 279 uint32_t MSIState; /*!< The new state of the MSI. 280 This parameter can be a value of @ref RCC_MSI_Config */ 281 282 uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT). 283 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 284 285 uint32_t MSIClockRange; /*!< The MSI frequency range. 286 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 287 288 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 289 290 } RCC_OscInitTypeDef; 291 292 /** 293 * @brief RCC System, AHB and APB busses clock configuration structure definition 294 */ 295 typedef struct 296 { 297 uint32_t ClockType; /*!< The clock to be configured. 298 This parameter can be a value of @ref RCC_System_Clock_Type */ 299 300 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 301 This parameter can be a value of @ref RCC_System_Clock_Source */ 302 303 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 304 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 305 306 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 307 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 308 309 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 310 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 311 } RCC_ClkInitTypeDef; 312 313 /** 314 * @} 315 */ 316 317 /* Exported constants --------------------------------------------------------*/ 318 /** @defgroup RCC_Exported_Constants RCC Exported Constants 319 * @{ 320 */ 321 322 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 323 * @{ 324 */ 325 326 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 327 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 328 329 /** 330 * @} 331 */ 332 333 /** @defgroup RCC_Oscillator_Type Oscillator Type 334 * @{ 335 */ 336 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) 337 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) 338 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) 339 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) 340 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) 341 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) 342 #if defined(RCC_HSI48_SUPPORT) 343 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) 344 #endif /* RCC_HSI48_SUPPORT */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup RCC_HSE_Config HSE Config 350 * @{ 351 */ 352 #define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */ 353 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 354 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 355 /** 356 * @} 357 */ 358 359 /** @defgroup RCC_LSE_Config LSE Config 360 * @{ 361 */ 362 #define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */ 363 #define RCC_LSE_ON RCC_CSR_LSEON /*!< LSE clock activation */ 364 #define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON)) /*!< External clock source for LSE clock */ 365 366 /** 367 * @} 368 */ 369 370 /** @defgroup RCC_HSI_Config HSI Config 371 * @{ 372 */ 373 #define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ 374 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 375 #define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */ 376 #if defined(RCC_CR_HSIOUTEN) 377 #define RCC_HSI_OUTEN RCC_CR_HSIOUTEN /*!< HSI_OUTEN clock activation */ 378 #endif /* RCC_CR_HSIOUTEN */ 379 380 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ 381 382 /** 383 * @} 384 */ 385 386 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 387 * @{ 388 */ 389 390 #define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ 391 #define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */ 392 #define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ 393 #define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ 394 #define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ 395 #define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ 396 #define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ 397 398 /** 399 * @} 400 */ 401 402 /** @defgroup RCC_LSI_Config LSI Config 403 * @{ 404 */ 405 #define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */ 406 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 407 408 /** 409 * @} 410 */ 411 412 /** @defgroup RCC_MSI_Config MSI Config 413 * @{ 414 */ 415 #define RCC_MSI_OFF ((uint32_t)0x00000000) 416 #define RCC_MSI_ON ((uint32_t)0x00000001) 417 418 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00000000U) /* Default MSI calibration trimming value */ 419 420 /** 421 * @} 422 */ 423 424 #if defined(RCC_HSI48_SUPPORT) 425 /** @defgroup RCC_HSI48_Config HSI48 Config 426 * @{ 427 */ 428 #define RCC_HSI48_OFF ((uint8_t)0x00) 429 #define RCC_HSI48_ON ((uint8_t)0x01) 430 431 /** 432 * @} 433 */ 434 #endif /* RCC_HSI48_SUPPORT */ 435 436 /** @defgroup RCC_PLL_Config PLL Config 437 * @{ 438 */ 439 #define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */ 440 #define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */ 441 #define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */ 442 443 /** 444 * @} 445 */ 446 447 /** @defgroup RCC_System_Clock_Type System Clock Type 448 * @{ 449 */ 450 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ 451 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ 452 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ 453 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */ 454 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCC_System_Clock_Source System Clock Source 460 * @{ 461 */ 462 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selected as system clock */ 463 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 464 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 465 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 466 467 /** 468 * @} 469 */ 470 471 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 472 * @{ 473 */ 474 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 475 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 476 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 477 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 478 479 /** 480 * @} 481 */ 482 483 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 484 * @{ 485 */ 486 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 487 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 488 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 489 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 490 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 491 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 492 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 493 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 494 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 495 496 /** 497 * @} 498 */ 499 500 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 501 * @{ 502 */ 503 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 504 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 505 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 506 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 507 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 508 509 /** 510 * @} 511 */ 512 513 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler 514 * @{ 515 */ 516 #define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock */ 517 #define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ 518 #define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ 519 #define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ 520 /** 521 * @} 522 */ 523 524 /** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source 525 * @{ 526 */ 527 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */ 528 #define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 529 #define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 530 #define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */ 531 #define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 2 used as RTC clock */ 532 #define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 4 used as RTC clock */ 533 #define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 8 used as RTC clock */ 534 #define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 16 used as RTC clock */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup RCC_PLL_Division_Factor PLL Division Factor 540 * @{ 541 */ 542 543 #define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 544 #define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 545 #define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 546 547 /** 548 * @} 549 */ 550 551 /** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor 552 * @{ 553 */ 554 555 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 556 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 557 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 558 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 559 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 560 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 561 #define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 562 #define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 563 #define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 564 565 /** 566 * @} 567 */ 568 569 /** @defgroup RCC_MCO_Index MCO Index 570 * @{ 571 */ 572 #define RCC_MCO1 ((uint32_t)0x00000000) 573 #define RCC_MCO2 ((uint32_t)0x00000001) 574 #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) \ 575 || defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx) 576 #define RCC_MCO3 ((uint32_t)0x00000002) 577 #endif 578 579 /** 580 * @} 581 */ 582 583 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 584 * @{ 585 */ 586 #define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1 587 #define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2 588 #define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4 589 #define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8 590 #define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16 591 592 /** 593 * @} 594 */ 595 596 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 597 * @{ 598 */ 599 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK 600 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK 601 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI 602 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI 603 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE 604 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI 605 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE 606 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL 607 #if defined(RCC_CFGR_MCOSEL_HSI48) 608 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 609 #endif /* RCC_CFGR_MCOSEL_HSI48 */ 610 611 /** 612 * @} 613 */ 614 /** @defgroup RCC_Interrupt Interrupts 615 * @{ 616 */ 617 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 618 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 619 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 620 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 621 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 622 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 623 #define RCC_IT_LSECSS RCC_CIFR_CSSLSEF /*!< LSE Clock Security System Interrupt flag */ 624 #if defined(RCC_HSECSS_SUPPORT) 625 #define RCC_IT_CSS RCC_CIFR_CSSHSEF /*!< Clock Security System Interrupt flag */ 626 #endif /* RCC_HSECSS_SUPPORT */ 627 #if defined(RCC_HSI48_SUPPORT) 628 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 629 #endif /* RCC_HSI48_SUPPORT */ 630 /** 631 * @} 632 */ 633 634 /** @defgroup RCC_Flag Flags 635 * Elements values convention: XXXYYYYYb 636 * - YYYYY : Flag position in the register 637 * - XXX : Register index 638 * - 001: CR register 639 * - 010: CSR register 640 * - 011: CRRCR register (*) 641 * (*) Applicable only for STM32L052xx, STM32L053xx, (...), STM32L073xx & STM32L082xx 642 * @{ 643 */ 644 /* Flags in the CR register */ 645 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | 2)) /*!< Internal High Speed clock ready flag */ 646 #define RCC_FLAG_HSIDIV ((uint8_t)((CR_REG_INDEX << 5) | 4)) /*!< HSI16 divider flag */ 647 #define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | 9)) /*!< MSI clock ready flag */ 648 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | 17)) /*!< External High Speed clock ready flag */ 649 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | 25)) /*!< PLL clock ready flag */ 650 /* Flags in the CSR register */ 651 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | 1)) /*!< Internal Low Speed oscillator Ready */ 652 #define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | 9)) /*!< External Low Speed oscillator Ready */ 653 #define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | 14)) /*!< CSS on LSE failure Detection */ 654 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | 25)) /*!< Options bytes loading reset flag */ 655 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | 26)) /*!< PIN reset flag */ 656 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | 27)) /*!< POR/PDR reset flag */ 657 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | 28)) /*!< Software Reset flag */ 658 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | 29)) /*!< Independent Watchdog reset flag */ 659 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | 30)) /*!< Window watchdog reset flag */ 660 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | 31)) /*!< Low-Power reset flag */ 661 #if defined(RCC_CSR_FWRSTF) 662 #define RCC_FLAG_FWRST ((uint8_t)((CSR_REG_INDEX << 5) | 8)) /*!< RCC flag FW reset */ 663 #endif /* RCC_CSR_FWRSTF */ 664 /* Flags in the CRRCR register */ 665 #if defined(RCC_HSI48_SUPPORT) 666 #define RCC_FLAG_HSI48RDY ((uint8_t)((CRRCR_REG_INDEX << 5) | 1)) /*!< HSI48 clock ready flag */ 667 #endif /* RCC_HSI48_SUPPORT */ 668 669 /** 670 * @} 671 */ 672 673 /** 674 * @} 675 */ 676 677 /* Exported macro ------------------------------------------------------------*/ 678 679 /** @defgroup RCC_Exported_Macros RCC Exported Macros 680 * @{ 681 */ 682 683 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable 684 * @brief Enable or disable the AHB peripheral clock. 685 * @note After reset, the peripheral clock (used for registers read/write access) 686 * is disabled and the application software has to enable this clock before 687 * using it. 688 * @{ 689 */ 690 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 691 __IO uint32_t tmpreg; \ 692 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 693 /* Delay after an RCC peripheral clock enabling */ \ 694 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 695 UNUSED(tmpreg); \ 696 } while(0) 697 698 #define __HAL_RCC_MIF_CLK_ENABLE() do { \ 699 __IO uint32_t tmpreg; \ 700 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\ 701 /* Delay after an RCC peripheral clock enabling */ \ 702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\ 703 UNUSED(tmpreg); \ 704 } while(0) 705 706 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 707 __IO uint32_t tmpreg; \ 708 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 709 /* Delay after an RCC peripheral clock enabling */ \ 710 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 711 UNUSED(tmpreg); \ 712 } while(0) 713 714 715 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) 716 #define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) 717 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) 718 719 /** 720 * @} 721 */ 722 723 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable 724 * @brief Enable or disable the IOPORT peripheral clock. 725 * @note After reset, the peripheral clock (used for registers read/write access) 726 * is disabled and the application software has to enable this clock before 727 * using it. 728 * @{ 729 */ 730 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 731 __IO uint32_t tmpreg; \ 732 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ 733 /* Delay after an RCC peripheral clock enabling */ \ 734 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ 735 UNUSED(tmpreg); \ 736 } while(0) 737 738 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 739 __IO uint32_t tmpreg; \ 740 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\ 741 /* Delay after an RCC peripheral clock enabling */ \ 742 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\ 743 UNUSED(tmpreg); \ 744 } while(0) 745 746 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 747 __IO uint32_t tmpreg; \ 748 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\ 749 /* Delay after an RCC peripheral clock enabling */ \ 750 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\ 751 UNUSED(tmpreg); \ 752 } while(0) 753 754 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 755 __IO uint32_t tmpreg; \ 756 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\ 757 /* Delay after an RCC peripheral clock enabling */ \ 758 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\ 759 UNUSED(tmpreg); \ 760 } while(0) 761 762 763 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) 764 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) 765 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) 766 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) 767 768 /** 769 * @} 770 */ 771 772 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 773 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 774 * @note After reset, the peripheral clock (used for registers read/write access) 775 * is disabled and the application software has to enable this clock before 776 * using it. 777 * @{ 778 */ 779 #define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN)) 780 #define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN)) 781 782 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN)) 783 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN)) 784 /** 785 * @} 786 */ 787 788 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 789 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 790 * @note After reset, the peripheral clock (used for registers read/write access) 791 * is disabled and the application software has to enable this clock before 792 * using it. 793 * @{ 794 */ 795 #define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN)) 796 #define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN)) 797 798 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN)) 799 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN)) 800 /** 801 * @} 802 */ 803 804 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status 805 * @brief Check whether the AHB peripheral clock is enabled or not. 806 * @note After reset, the peripheral clock (used for registers read/write access) 807 * is disabled and the application software has to enable this clock before 808 * using it. 809 * @{ 810 */ 811 812 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET) 813 #define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != RESET) 814 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET) 815 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET) 816 #define __HAL_RCC_MIF_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) == RESET) 817 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET) 818 819 /** 820 * @} 821 */ 822 823 /** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status 824 * @brief Check whether the IOPORT peripheral clock is enabled or not. 825 * @note After reset, the peripheral clock (used for registers read/write access) 826 * is disabled and the application software has to enable this clock before 827 * using it. 828 * @{ 829 */ 830 831 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET) 832 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET) 833 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET) 834 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != RESET) 835 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET) 836 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET) 837 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET) 838 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) == RESET) 839 840 /** 841 * @} 842 */ 843 844 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 845 * @brief Check whether the APB1 peripheral clock is enabled or not. 846 * @note After reset, the peripheral clock (used for registers read/write access) 847 * is disabled and the application software has to enable this clock before 848 * using it. 849 * @{ 850 */ 851 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != RESET) 852 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != RESET) 853 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == RESET) 854 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == RESET) 855 856 /** 857 * @} 858 */ 859 860 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 861 * @brief Check whether the APB2 peripheral clock is enabled or not. 862 * @note After reset, the peripheral clock (used for registers read/write access) 863 * is disabled and the application software has to enable this clock before 864 * using it. 865 * @{ 866 */ 867 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET) 868 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != RESET) 869 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) 870 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == RESET) 871 872 /** 873 * @} 874 */ 875 876 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset 877 * @brief Force or release AHB peripheral reset. 878 * @{ 879 */ 880 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 881 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST)) 882 #define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST)) 883 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST)) 884 885 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) 886 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST)) 887 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST)) 888 #define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST)) 889 /** 890 * @} 891 */ 892 893 /** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset 894 * @brief Force or release IOPORT peripheral reset. 895 * @{ 896 */ 897 #define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFFU) 898 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST)) 899 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST)) 900 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST)) 901 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST)) 902 903 #define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00000000U) 904 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST)) 905 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST)) 906 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST)) 907 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST)) 908 909 /** 910 * @} 911 */ 912 913 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 914 * @brief Force or release APB1 peripheral reset. 915 * @{ 916 */ 917 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 918 #define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST)) 919 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST)) 920 921 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) 922 #define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST)) 923 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST)) 924 925 /** 926 * @} 927 */ 928 929 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 930 * @brief Force or release APB2 peripheral reset. 931 * @{ 932 */ 933 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 934 #define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST)) 935 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST)) 936 937 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) 938 #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST)) 939 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST)) 940 /** 941 * @} 942 */ 943 944 945 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable 946 * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode. 947 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 948 * power consumption. 949 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 950 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. 951 * @{ 952 */ 953 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN)) 954 #define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN)) 955 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN)) 956 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN)) 957 958 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN)) 959 #define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN)) 960 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN)) 961 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN)) 962 /** 963 * @} 964 */ 965 966 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable 967 * @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode. 968 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 969 * power consumption. 970 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 971 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. 972 * @{ 973 */ 974 975 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN)) 976 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN)) 977 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN)) 978 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN)) 979 980 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN)) 981 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN)) 982 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN)) 983 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN)) 984 /** 985 * @} 986 */ 987 988 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 989 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 990 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 991 * power consumption. 992 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 993 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. 994 * @{ 995 */ 996 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN)) 997 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN)) 998 999 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN)) 1000 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN)) 1001 1002 /** 1003 * @} 1004 */ 1005 1006 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 1007 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1008 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1009 * power consumption. 1010 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1011 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. 1012 * @{ 1013 */ 1014 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN)) 1015 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN)) 1016 1017 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN)) 1018 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN)) 1019 1020 /** 1021 * @} 1022 */ 1023 1024 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status 1025 * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. 1026 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1027 * power consumption. 1028 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1029 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1030 * @{ 1031 */ 1032 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET) 1033 #define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != RESET) 1034 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET) 1035 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET) 1036 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET) 1037 #define __HAL_RCC_MIF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) == RESET) 1038 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET) 1039 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET) 1040 1041 /** 1042 * @} 1043 */ 1044 1045 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status 1046 * @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not. 1047 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1048 * power consumption. 1049 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1050 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1051 * @{ 1052 */ 1053 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != RESET) 1054 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != RESET) 1055 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != RESET) 1056 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != RESET) 1057 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET) 1058 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET) 1059 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET) 1060 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) == RESET) 1061 1062 /** 1063 * @} 1064 */ 1065 1066 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 1067 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 1068 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1069 * power consumption. 1070 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1071 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1072 * @{ 1073 */ 1074 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != RESET) 1075 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != RESET) 1076 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) == RESET) 1077 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) == RESET) 1078 1079 /** 1080 * @} 1081 */ 1082 1083 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 1084 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 1085 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1086 * power consumption. 1087 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1088 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1089 * @{ 1090 */ 1091 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) 1092 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != RESET) 1093 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) 1094 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) == RESET) 1095 1096 /** 1097 * @} 1098 */ 1099 /** @defgroup RCC_HSI_Configuration HSI Configuration 1100 * @{ 1101 */ 1102 1103 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). 1104 * @note After enabling the HSI, the application software should wait on 1105 * HSIRDY flag to be set indicating that HSI clock is stable and can 1106 * be used to clock the PLL and/or system clock. 1107 * @note HSI can not be stopped if it is used directly or through the PLL 1108 * as system clock. In this case, you have to select another source 1109 * of the system clock then stop the HSI. 1110 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1111 * @param __STATE__ specifies the new state of the HSI. 1112 * This parameter can be one of the following values: 1113 * @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator 1114 * @arg @ref RCC_HSI_ON turn ON the HSI oscillator 1115 * @arg @ref RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 1116 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1117 * clock cycles. 1118 */ 1119 #define __HAL_RCC_HSI_CONFIG(__STATE__) \ 1120 MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__)) 1121 1122 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 1123 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1124 * It is used (enabled by hardware) as system clock source after startup 1125 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1126 * of the HSE used directly or indirectly as system clock (if the Clock 1127 * Security System CSS is enabled). 1128 * @note HSI can not be stopped if it is used as system clock source. In this case, 1129 * you have to select another source of the system clock then stop the HSI. 1130 * @note After enabling the HSI, the application software should wait on HSIRDY 1131 * flag to be set indicating that HSI clock is stable and can be used as 1132 * system clock source. 1133 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1134 * clock cycles. 1135 */ 1136 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 1137 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 1138 1139 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 1140 * @note The calibration is used to compensate for the variations in voltage 1141 * and temperature that influence the frequency of the internal HSI RC. 1142 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 1143 * (default is RCC_HSICALIBRATION_DEFAULT). 1144 * This parameter must be a number between 0 and 0x1F. 1145 */ 1146 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 1147 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << 8)) 1148 1149 /** 1150 * @} 1151 */ 1152 1153 /** @defgroup RCC_LSI_Configuration LSI Configuration 1154 * @{ 1155 */ 1156 1157 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 1158 * @note After enabling the LSI, the application software should wait on 1159 * LSIRDY flag to be set indicating that LSI clock is stable and can 1160 * be used to clock the IWDG and/or the RTC. 1161 */ 1162 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 1163 1164 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 1165 * @note LSI can not be disabled if the IWDG is running. 1166 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1167 * clock cycles. 1168 */ 1169 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 1170 1171 /** 1172 * @} 1173 */ 1174 1175 /** @defgroup RCC_HSE_Configuration HSE Configuration 1176 * @{ 1177 */ 1178 1179 /** 1180 * @brief Macro to configure the External High Speed oscillator (HSE). 1181 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 1182 * supported by this macro. User should request a transition to HSE Off 1183 * first and then HSE On or HSE Bypass. 1184 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 1185 * software should wait on HSERDY flag to be set indicating that HSE clock 1186 * is stable and can be used to clock the PLL and/or system clock. 1187 * @note HSE state can not be changed if it is used directly or through the 1188 * PLL as system clock. In this case, you have to select another source 1189 * of the system clock then change the HSE state (ex. disable it). 1190 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1191 * @note This function reset the CSSON bit, so if the clock security system(CSS) 1192 * was previously enabled you have to enable it again after calling this 1193 * function. 1194 * @param __STATE__ specifies the new state of the HSE. 1195 * This parameter can be one of the following values: 1196 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 1197 * 6 HSE oscillator clock cycles. 1198 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 1199 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 1200 */ 1201 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 1202 do{ \ 1203 __IO uint32_t tmpreg; \ 1204 if ((__STATE__) == RCC_HSE_ON) \ 1205 { \ 1206 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1207 } \ 1208 else if ((__STATE__) == RCC_HSE_BYPASS) \ 1209 { \ 1210 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1211 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1212 } \ 1213 else \ 1214 { \ 1215 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1216 /* Delay after an RCC peripheral clock */ \ 1217 tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \ 1218 UNUSED(tmpreg); \ 1219 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1220 } \ 1221 }while(0) 1222 1223 /** 1224 * @} 1225 */ 1226 1227 /** @defgroup RCC_LSE_Configuration LSE Configuration 1228 * @{ 1229 */ 1230 1231 /** 1232 * @brief Macro to configure the External Low Speed oscillator (LSE). 1233 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 1234 * @note As the LSE is in the Backup domain and write access is denied to 1235 * this domain after reset, you have to enable write access using 1236 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 1237 * (to be done once after reset). 1238 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 1239 * software should wait on LSERDY flag to be set indicating that LSE clock 1240 * is stable and can be used to clock the RTC. 1241 * @param __STATE__ specifies the new state of the LSE. 1242 * This parameter can be one of the following values: 1243 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 1244 * 6 LSE oscillator clock cycles. 1245 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 1246 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 1247 */ 1248 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 1249 do{ \ 1250 if ((__STATE__) == RCC_LSE_ON) \ 1251 { \ 1252 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1253 } \ 1254 else if ((__STATE__) == RCC_LSE_OFF) \ 1255 { \ 1256 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1257 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1258 } \ 1259 else if ((__STATE__) == RCC_LSE_BYPASS) \ 1260 { \ 1261 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1262 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1263 } \ 1264 else \ 1265 { \ 1266 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ 1267 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ 1268 } \ 1269 }while(0) 1270 1271 /** 1272 * @} 1273 */ 1274 1275 /** @defgroup RCC_MSI_Configuration MSI Configuration 1276 * @{ 1277 */ 1278 1279 /** @brief Macro to enable Internal Multi Speed oscillator (MSI). 1280 * @note After enabling the MSI, the application software should wait on MSIRDY 1281 * flag to be set indicating that MSI clock is stable and can be used as 1282 * system clock source. 1283 */ 1284 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 1285 1286 /** @brief Macro to disable the Internal Multi Speed oscillator (MSI). 1287 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 1288 * It is used (enabled by hardware) as system clock source after startup 1289 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1290 * of the HSE used directly or indirectly as system clock (if the Clock 1291 * Security System CSS is enabled). 1292 * @note MSI can not be stopped if it is used as system clock source. In this case, 1293 * you have to select another source of the system clock then stop the MSI. 1294 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 1295 * clock cycles. 1296 */ 1297 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 1298 1299 /** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value. 1300 * @note The calibration is used to compensate for the variations in voltage 1301 * and temperature that influence the frequency of the internal MSI RC. 1302 * Refer to the Application Note AN3300 for more details on how to 1303 * calibrate the MSI. 1304 * @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value. 1305 * (default is RCC_MSICALIBRATION_DEFAULT). 1306 * This parameter must be a number between 0 and 0xFF. 1307 */ 1308 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \ 1309 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << 24)) 1310 1311 /* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. 1312 * @note After restart from Reset or wakeup from STANDBY, the MSI clock is 1313 * around 2.097 MHz. The MSI clock does not change after wake-up from 1314 * STOP mode. 1315 * @note The MSI clock range can be modified on the fly. 1316 * @param _MSIRANGEVALUE_ specifies the MSI Clock range. 1317 * This parameter must be one of the following values: 1318 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz 1319 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz 1320 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz 1321 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz 1322 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz 1323 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) 1324 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz 1325 */ 1326 #define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \ 1327 RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) 1328 1329 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 1330 * @retval MSI clock range. 1331 * This parameter must be one of the following values: 1332 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz 1333 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz 1334 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz 1335 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz 1336 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz 1337 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) 1338 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz 1339 */ 1340 #define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)) 1341 1342 /** 1343 * @} 1344 */ 1345 1346 /** @defgroup RCC_PLL_Configuration PLL Configuration 1347 * @{ 1348 */ 1349 1350 /** @brief Macro to enable the main PLL. 1351 * @note After enabling the main PLL, the application software should wait on 1352 * PLLRDY flag to be set indicating that PLL clock is stable and can 1353 * be used as system clock source. 1354 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 1355 */ 1356 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 1357 1358 /** @brief Macro to disable the main PLL. 1359 * @note The main PLL can not be disabled if it is used as system clock source 1360 */ 1361 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 1362 1363 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 1364 * @note This function must be used only when the main PLL is disabled. 1365 * 1366 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. 1367 * This parameter can be one of the following values: 1368 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 1369 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 1370 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock 1371 * This parameter can be one of the following values: 1372 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 1373 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 1374 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 1375 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 1376 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 1377 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 1378 * @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24 1379 * @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32 1380 * @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48 1381 * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in 1382 * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is 1383 * in Range 3. 1384 * 1385 * @param __PLLDIV__ specifies the division factor for PLL VCO input clock 1386 * This parameter can be one of the following values: 1387 * @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2 1388 * @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3 1389 * @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4 1390 * 1391 */ 1392 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ 1393 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) 1394 1395 /** @brief Get oscillator clock selected as PLL input clock 1396 * @retval The clock source used for PLL entry. The returned value can be one 1397 * of the following: 1398 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock 1399 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 1400 */ 1401 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 1402 1403 /** 1404 * @} 1405 */ 1406 1407 /** @defgroup RCC_Get_Clock_source Get Clock source 1408 * @{ 1409 */ 1410 1411 /** 1412 * @brief Macro to configure the system clock source. 1413 * @param __SYSCLKSOURCE__ specifies the system clock source. 1414 * This parameter can be one of the following values: 1415 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 1416 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 1417 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 1418 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 1419 */ 1420 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 1421 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 1422 1423 /** @brief Macro to get the clock source used as system clock. 1424 * @retval The clock source used as system clock. The returned value can be one 1425 * of the following: 1426 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock 1427 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 1428 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 1429 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 1430 */ 1431 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) 1432 1433 /** 1434 * @} 1435 */ 1436 1437 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 1438 * @{ 1439 */ 1440 1441 /** @brief Macro to configure the MCO clock. 1442 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1443 * This parameter can be one of the following values: 1444 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 1445 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock 1446 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock 1447 * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock 1448 * @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock 1449 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock 1450 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock 1451 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock 1452 @if STM32L052xx 1453 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1454 @elseif STM32L053xx 1455 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1456 @elseif STM32L062xx 1457 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1458 @elseif STM32L063xx 1459 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1460 @elseif STM32L072xx 1461 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1462 @elseif STM32L073xx 1463 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1464 @elseif STM32L082xx 1465 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1466 @elseif STM32L083xx 1467 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO clock 1468 @endif 1469 * @param __MCODIV__ specifies the MCO clock prescaler. 1470 * This parameter can be one of the following values: 1471 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 1472 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 1473 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 1474 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 1475 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 1476 */ 1477 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1478 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1479 1480 /** 1481 * @} 1482 */ 1483 1484 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 1485 * @{ 1486 */ 1487 1488 /** @brief Macro to configure the RTC clock (RTCCLK). 1489 * @note As the RTC clock configuration bits are in the Backup domain and write 1490 * access is denied to this domain after reset, you have to enable write 1491 * access using the Power Backup Access macro before to configure 1492 * the RTC clock source (to be done once after reset). 1493 * @note Once the RTC clock is configured it cannot be changed unless the 1494 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 1495 * a Power On Reset (POR). 1496 * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1). 1497 * 1498 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 1499 * This parameter can be one of the following values: 1500 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1501 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1502 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1503 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock 1504 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock 1505 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock 1506 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock 1507 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1508 * work in STOP and STANDBY modes, and can be used as wakeup source. 1509 * However, when the HSE clock is used as RTC clock source, the RTC 1510 * cannot be used in STOP and STANDBY modes. 1511 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 1512 * RTC clock source). 1513 */ 1514 #define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \ 1515 if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \ 1516 { \ 1517 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \ 1518 } \ 1519 } while (0) 1520 1521 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \ 1522 __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ 1523 RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \ 1524 } while (0) 1525 1526 /** @brief Macro to get the RTC clock source. 1527 * @retval The clock source can be one of the following values: 1528 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1529 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1530 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1531 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 1532 */ 1533 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)) 1534 1535 /** 1536 * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK). 1537 * 1538 * @retval Returned value can be one of the following values: 1539 * @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock 1540 * @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock 1541 * @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock 1542 * @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock 1543 * 1544 */ 1545 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE))) 1546 1547 /** @brief Macro to enable the the RTC clock. 1548 * @note These macros must be used only after the RTC clock source was selected. 1549 */ 1550 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN) 1551 1552 /** @brief Macro to disable the the RTC clock. 1553 * @note These macros must be used only after the RTC clock source was selected. 1554 */ 1555 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN) 1556 1557 /** @brief Macro to force the Backup domain reset. 1558 * @note This function resets the RTC peripheral (including the backup registers) 1559 * and the RTC clock source selection in RCC_CSR register. 1560 * @note The BKPSRAM is not affected by this reset. 1561 */ 1562 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST) 1563 1564 /** @brief Macros to release the Backup domain reset. 1565 */ 1566 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST) 1567 1568 /** 1569 * @} 1570 */ 1571 1572 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1573 * @brief macros to manage the specified RCC Flags and interrupts. 1574 * @{ 1575 */ 1576 1577 /** @brief Enable RCC interrupt. 1578 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled 1579 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is 1580 * automatically generated. The NMI will be executed indefinitely, and 1581 * since NMI has higher priority than any other IRQ (and main program) 1582 * the application will be stacked in the NMI ISR unless the CSS interrupt 1583 * pending bit is cleared. 1584 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1585 * This parameter can be any combination of the following values: 1586 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1587 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1588 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1589 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1590 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1591 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1592 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt 1593 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices) 1594 */ 1595 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 1596 1597 /** @brief Disable RCC interrupt. 1598 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled 1599 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is 1600 * automatically generated. The NMI will be executed indefinitely, and 1601 * since NMI has higher priority than any other IRQ (and main program) 1602 * the application will be stacked in the NMI ISR unless the CSS interrupt 1603 * pending bit is cleared. 1604 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1605 * This parameter can be any combination of the following values: 1606 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1607 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1608 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1609 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1610 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1611 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1612 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt 1613 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices) 1614 */ 1615 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 1616 1617 /** @brief Clear the RCC's interrupt pending bits. 1618 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1619 * This parameter can be any combination of the following values: 1620 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1621 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1622 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1623 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1624 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1625 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1626 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt 1627 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt (not available on all devices) 1628 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1629 */ 1630 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 1631 1632 /** @brief Check the RCC's interrupt has occurred or not. 1633 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1634 * This parameter can be one of the following values: 1635 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1636 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1637 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1638 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1639 * @arg @ref RCC_IT_PLLRDY PLL ready interrupt 1640 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 1641 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt 1642 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1643 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1644 */ 1645 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 1646 1647 1648 /** @brief Set RMVF bit to clear the reset flags. 1649 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 1650 * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 1651 */ 1652 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 1653 1654 /** @brief Check RCC flag is set or not. 1655 * @param __FLAG__ specifies the flag to check. 1656 * This parameter can be one of the following values: 1657 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 1658 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready (not available on all devices) 1659 * @arg @ref RCC_FLAG_HSIDIV HSI16 divider flag 1660 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 1661 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 1662 * @arg @ref RCC_FLAG_PLLRDY PLL clock ready 1663 * @arg @ref RCC_FLAG_LSECSS LSE oscillator clock CSS detected 1664 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 1665 * @arg @ref RCC_FLAG_FWRST Firewall reset 1666 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 1667 * @arg @ref RCC_FLAG_OBLRST Option Byte Loader (OBL) reset 1668 * @arg @ref RCC_FLAG_PINRST Pin reset 1669 * @arg @ref RCC_FLAG_PORRST POR/PDR reset 1670 * @arg @ref RCC_FLAG_SFTRST Software reset 1671 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 1672 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 1673 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 1674 * @retval The new state of __FLAG__ (TRUE or FALSE). 1675 */ 1676 #if defined(RCC_HSI48_SUPPORT) 1677 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == CSR_REG_INDEX) ? RCC->CSR :RCC->CRRCR)))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 ) 1678 #else 1679 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : RCC->CSR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 ) 1680 #endif /* RCC_HSI48_SUPPORT */ 1681 1682 /** 1683 * @} 1684 */ 1685 1686 /** 1687 * @} 1688 */ 1689 1690 /* Include RCC HAL Extension module */ 1691 #include "stm32l0xx_hal_rcc_ex.h" 1692 1693 /* Exported functions --------------------------------------------------------*/ 1694 /** @addtogroup RCC_Exported_Functions 1695 * @{ 1696 */ 1697 1698 /** @addtogroup RCC_Exported_Functions_Group1 1699 * @{ 1700 */ 1701 1702 /* Initialization and de-initialization functions ******************************/ 1703 void HAL_RCC_DeInit(void); 1704 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1705 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1706 1707 /** 1708 * @} 1709 */ 1710 1711 /** @addtogroup RCC_Exported_Functions_Group2 1712 * @{ 1713 */ 1714 1715 /* Peripheral Control functions ************************************************/ 1716 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1717 #if defined(RCC_HSECSS_SUPPORT) 1718 void HAL_RCC_EnableCSS(void); 1719 /* CSS NMI IRQ handler */ 1720 void HAL_RCC_NMI_IRQHandler(void); 1721 /* User Callbacks in non blocking mode (IT mode) */ 1722 void HAL_RCC_CSSCallback(void); 1723 #endif /* RCC_HSECSS_SUPPORT */ 1724 uint32_t HAL_RCC_GetSysClockFreq(void); 1725 uint32_t HAL_RCC_GetHCLKFreq(void); 1726 uint32_t HAL_RCC_GetPCLK1Freq(void); 1727 uint32_t HAL_RCC_GetPCLK2Freq(void); 1728 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1729 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1730 1731 /** 1732 * @} 1733 */ 1734 1735 /** 1736 * @} 1737 */ 1738 1739 /** 1740 * @} 1741 */ 1742 1743 /** 1744 * @} 1745 */ 1746 1747 #ifdef __cplusplus 1748 } 1749 #endif 1750 1751 #endif /* __STM32L0xx_HAL_RCC_H */ 1752 1753 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1754 1755
