1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L0xx_HAL_DMA_H 38 #define __STM32L0xx_HAL_DMA_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l0xx_hal_def.h" 46 47 /** @addtogroup STM32L0xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @defgroup DMA DMA 52 * @{ 53 */ 54 55 /** @defgroup DMA_Exported_Types DMA Exported Types 56 * @{ 57 */ 58 /* Exported types ------------------------------------------------------------*/ 59 60 /** 61 * @brief DMA Configuration Structure definition 62 */ 63 typedef struct 64 { 65 uint32_t Request; /*!< Specifies the request selected for the specified channel. 66 This parameter can be a value of @ref DMA_request */ 67 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 69 from memory to memory or from peripheral to memory. 70 This parameter can be a value of @ref DMA_Data_transfer_direction */ 71 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 73 When Memory to Memory transfer is used, this is the Source Increment mode 74 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 75 76 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 77 When Memory to Memory transfer is used, this is the Destination Increment mode 78 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 79 80 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 81 When Memory to Memory transfer is used, this is the Source Alignment format 82 This parameter can be a value of @ref DMA_Peripheral_data_size */ 83 84 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 85 When Memory to Memory transfer is used, this is the Destination Alignment format 86 This parameter can be a value of @ref DMA_Memory_data_size */ 87 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular). 89 This parameter can be a value of @ref DMA_mode 90 @note The circular buffer mode cannot be used if the memory-to-memory 91 data transfer is configured on the selected Channel */ 92 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 94 This parameter can be a value of @ref DMA_Priority_level */ 95 } DMA_InitTypeDef; 96 97 /** 98 * @brief DMA Configuration enumeration values definition 99 */ 100 typedef enum 101 { 102 DMA_MODE = 0U, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ 103 DMA_PRIORITY = 1U, /*!< Control related priority level Parameter in DMA_InitTypeDef */ 104 105 } DMA_ControlTypeDef; 106 107 /** 108 * @brief HAL DMA State structures definition 109 */ 110 typedef enum 111 { 112 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 113 HAL_DMA_STATE_READY = 0x01U, /*!< DMA process success and ready for use */ 114 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 115 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 116 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ 117 HAL_DMA_STATE_READY_HALF = 0x05U, /*!< DMA Half process success */ 118 }HAL_DMA_StateTypeDef; 119 120 /** 121 * @brief HAL DMA Error Code structure definition 122 */ 123 typedef enum 124 { 125 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 126 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ 127 128 }HAL_DMA_LevelCompleteTypeDef; 129 130 131 /** 132 * @brief DMA handle Structure definition 133 */ 134 typedef struct __DMA_HandleTypeDef 135 { 136 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 137 138 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 139 140 HAL_LockTypeDef Lock; /*!< DMA locking object */ 141 142 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 143 144 void *Parent; /*!< Parent object state */ 145 146 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 147 148 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 149 150 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 151 152 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 153 154 __IO uint32_t ErrorCode; /*!< DMA Error code */ 155 156 } DMA_HandleTypeDef; 157 158 /** 159 * @} 160 */ 161 162 /* Exported constants --------------------------------------------------------*/ 163 164 /** @defgroup DMA_Exported_Constants DMA Exported Constants 165 * @{ 166 */ 167 168 /** @defgroup DMA_Error_Code DMA Error Codes 169 * @{ 170 */ 171 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 172 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ 173 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< no ongoing transfer */ 174 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ 175 176 #if defined (STM32L011xx) || defined (STM32L021xx) 177 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 178 ((INSTANCE) == DMA1_Channel2) || \ 179 ((INSTANCE) == DMA1_Channel3) || \ 180 ((INSTANCE) == DMA1_Channel4) || \ 181 ((INSTANCE) == DMA1_Channel5)) 182 #else 183 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 184 ((INSTANCE) == DMA1_Channel2) || \ 185 ((INSTANCE) == DMA1_Channel3) || \ 186 ((INSTANCE) == DMA1_Channel4) || \ 187 ((INSTANCE) == DMA1_Channel5) || \ 188 ((INSTANCE) == DMA1_Channel6) || \ 189 ((INSTANCE) == DMA1_Channel7)) 190 191 #endif 192 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1)) 193 194 /** 195 * @} 196 */ 197 198 /** @defgroup DMA_request DMA request defintiions 199 * @{ 200 */ 201 202 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 203 204 #define DMA_REQUEST_0 ((uint32_t)0x00000000U) 205 #define DMA_REQUEST_1 ((uint32_t)0x00000001U) 206 #define DMA_REQUEST_2 ((uint32_t)0x00000002U) 207 #define DMA_REQUEST_3 ((uint32_t)0x00000003U) 208 #define DMA_REQUEST_4 ((uint32_t)0x00000004U) 209 #define DMA_REQUEST_5 ((uint32_t)0x00000005U) 210 #define DMA_REQUEST_6 ((uint32_t)0x00000006U) 211 #define DMA_REQUEST_7 ((uint32_t)0x00000007U) 212 #define DMA_REQUEST_8 ((uint32_t)0x00000008U) 213 #define DMA_REQUEST_9 ((uint32_t)0x00000009U) 214 #define DMA_REQUEST_10 ((uint32_t)0x0000000AU) 215 #define DMA_REQUEST_11 ((uint32_t)0x0000000BU) 216 #define DMA_REQUEST_12 ((uint32_t)0x0000000CU) 217 #define DMA_REQUEST_13 ((uint32_t)0x0000000DU) 218 #define DMA_REQUEST_14 ((uint32_t)0x0000000EU) 219 #define DMA_REQUEST_15 ((uint32_t)0x0000000FU) 220 221 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 222 ((REQUEST) == DMA_REQUEST_1) || \ 223 ((REQUEST) == DMA_REQUEST_2) || \ 224 ((REQUEST) == DMA_REQUEST_3) || \ 225 ((REQUEST) == DMA_REQUEST_4) || \ 226 ((REQUEST) == DMA_REQUEST_5) || \ 227 ((REQUEST) == DMA_REQUEST_6) || \ 228 ((REQUEST) == DMA_REQUEST_7) || \ 229 ((REQUEST) == DMA_REQUEST_8) || \ 230 ((REQUEST) == DMA_REQUEST_9) || \ 231 ((REQUEST) == DMA_REQUEST_10) || \ 232 ((REQUEST) == DMA_REQUEST_11) || \ 233 ((REQUEST) == DMA_REQUEST_12) || \ 234 ((REQUEST) == DMA_REQUEST_13) || \ 235 ((REQUEST) == DMA_REQUEST_14) || \ 236 ((REQUEST) == DMA_REQUEST_15)) 237 238 #else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ 239 240 #define DMA_REQUEST_0 ((uint32_t)0x00000000U) 241 #define DMA_REQUEST_1 ((uint32_t)0x00000001U) 242 #define DMA_REQUEST_2 ((uint32_t)0x00000002U) 243 #define DMA_REQUEST_3 ((uint32_t)0x00000003U) 244 #define DMA_REQUEST_4 ((uint32_t)0x00000004U) 245 #define DMA_REQUEST_5 ((uint32_t)0x00000005U) 246 #define DMA_REQUEST_6 ((uint32_t)0x00000006U) 247 #define DMA_REQUEST_7 ((uint32_t)0x00000007U) 248 #define DMA_REQUEST_8 ((uint32_t)0x00000008U) 249 #define DMA_REQUEST_9 ((uint32_t)0x00000009U) 250 #define DMA_REQUEST_11 ((uint32_t)0x0000000BU) 251 252 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 253 ((REQUEST) == DMA_REQUEST_1) || \ 254 ((REQUEST) == DMA_REQUEST_2) || \ 255 ((REQUEST) == DMA_REQUEST_3) || \ 256 ((REQUEST) == DMA_REQUEST_4) || \ 257 ((REQUEST) == DMA_REQUEST_5) || \ 258 ((REQUEST) == DMA_REQUEST_6) || \ 259 ((REQUEST) == DMA_REQUEST_7) || \ 260 ((REQUEST) == DMA_REQUEST_8) || \ 261 ((REQUEST) == DMA_REQUEST_9) || \ 262 ((REQUEST) == DMA_REQUEST_11)) 263 #endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ 264 265 /** 266 * @} 267 */ 268 269 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions 270 * @{ 271 */ 272 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ 273 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ 274 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ 275 276 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 277 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 278 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 279 /** 280 * @} 281 */ 282 283 /** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check 284 * @{ 285 */ 286 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 287 /** 288 * @} 289 */ 290 291 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode 292 * @{ 293 */ 294 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ 295 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ 296 297 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 298 ((STATE) == DMA_PINC_DISABLE)) 299 /** 300 * @} 301 */ 302 303 /** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode 304 * @{ 305 */ 306 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ 307 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ 308 309 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 310 ((STATE) == DMA_MINC_DISABLE)) 311 /** 312 * @} 313 */ 314 315 /** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment 316 * @{ 317 */ 318 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ 319 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ 320 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ 321 322 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 323 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 324 ((SIZE) == DMA_PDATAALIGN_WORD)) 325 /** 326 * @} 327 */ 328 329 330 /** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment 331 * @{ 332 */ 333 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ 334 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ 335 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ 336 337 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 338 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 339 ((SIZE) == DMA_MDATAALIGN_WORD )) 340 /** 341 * @} 342 */ 343 344 /** @defgroup DMA_mode DMA Mode 345 * @{ 346 */ 347 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ 348 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ 349 350 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 351 ((MODE) == DMA_CIRCULAR)) 352 /** 353 * @} 354 */ 355 356 /** @defgroup DMA_Priority_level DMA Priority Level 357 * @{ 358 */ 359 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ 360 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ 361 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ 362 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ 363 364 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 365 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 366 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 367 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 368 /** 369 * @} 370 */ 371 372 373 /** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions 374 * @{ 375 */ 376 377 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) 378 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) 379 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) 380 381 /** 382 * @} 383 */ 384 385 /** @defgroup DMA_flag_definitions DMA Flag Definitions 386 * @{ 387 */ 388 389 #define DMA_FLAG_GL1 ((uint32_t)0x00000001U) 390 #define DMA_FLAG_TC1 ((uint32_t)0x00000002U) 391 #define DMA_FLAG_HT1 ((uint32_t)0x00000004U) 392 #define DMA_FLAG_TE1 ((uint32_t)0x00000008U) 393 #define DMA_FLAG_GL2 ((uint32_t)0x00000010U) 394 #define DMA_FLAG_TC2 ((uint32_t)0x00000020U) 395 #define DMA_FLAG_HT2 ((uint32_t)0x00000040U) 396 #define DMA_FLAG_TE2 ((uint32_t)0x00000080U) 397 #define DMA_FLAG_GL3 ((uint32_t)0x00000100U) 398 #define DMA_FLAG_TC3 ((uint32_t)0x00000200U) 399 #define DMA_FLAG_HT3 ((uint32_t)0x00000400U) 400 #define DMA_FLAG_TE3 ((uint32_t)0x00000800U) 401 #define DMA_FLAG_GL4 ((uint32_t)0x00001000U) 402 #define DMA_FLAG_TC4 ((uint32_t)0x00002000U) 403 #define DMA_FLAG_HT4 ((uint32_t)0x00004000U) 404 #define DMA_FLAG_TE4 ((uint32_t)0x00008000U) 405 #define DMA_FLAG_GL5 ((uint32_t)0x00010000U) 406 #define DMA_FLAG_TC5 ((uint32_t)0x00020000U) 407 #define DMA_FLAG_HT5 ((uint32_t)0x00040000U) 408 #define DMA_FLAG_TE5 ((uint32_t)0x00080000U) 409 #define DMA_FLAG_GL6 ((uint32_t)0x00100000U) 410 #define DMA_FLAG_TC6 ((uint32_t)0x00200000U) 411 #define DMA_FLAG_HT6 ((uint32_t)0x00400000U) 412 #define DMA_FLAG_TE6 ((uint32_t)0x00800000U) 413 #define DMA_FLAG_GL7 ((uint32_t)0x01000000U) 414 #define DMA_FLAG_TC7 ((uint32_t)0x02000000U) 415 #define DMA_FLAG_HT7 ((uint32_t)0x04000000U) 416 #define DMA_FLAG_TE7 ((uint32_t)0x08000000U) 417 418 419 /** 420 * @} 421 */ 422 423 /** 424 * @} 425 */ 426 427 /* Exported macro ------------------------------------------------------------*/ 428 429 /** @defgroup DMA_Exported_Macros DMA Exported Macros 430 * @{ 431 */ 432 433 /** @brief Reset DMA handle state 434 * @param __HANDLE__: DMA handle 435 * @retval None 436 */ 437 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 438 439 /** 440 * @brief Enable the specified DMA Channel. 441 * @param __HANDLE__: DMA handle 442 * @retval None. 443 */ 444 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 445 446 /** 447 * @brief Disable the specified DMA Channel. 448 * @param __HANDLE__: DMA handle 449 * @retval None. 450 */ 451 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 452 453 454 /* Interrupt & Flag management */ 455 456 /** 457 * @brief Returns the current DMA Channel transfer complete flag. 458 * @param __HANDLE__: DMA handle 459 * @retval The specified transfer complete flag index. 460 */ 461 462 #if defined (STM32L011xx) || defined (STM32L021xx) 463 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 464 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 468 DMA_FLAG_TC5) 469 #else 470 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 477 DMA_FLAG_TC7) 478 #endif 479 /** 480 * @brief Returns the current DMA Channel half transfer complete flag. 481 * @param __HANDLE__: DMA handle 482 * @retval The specified half transfer complete flag index. 483 */ 484 #if defined (STM32L011xx) || defined (STM32L021xx) 485 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 486 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 490 DMA_FLAG_HT5) 491 #else 492 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 493 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 499 DMA_FLAG_HT7) 500 #endif 501 /** 502 * @brief Returns the current DMA Channel transfer error flag. 503 * @param __HANDLE__: DMA handle 504 * @retval The specified transfer error flag index. 505 */ 506 #if defined (STM32L011xx) || defined (STM32L021xx) 507 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 508 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 512 DMA_FLAG_TE5) 513 #else 514 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 515 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 521 DMA_FLAG_TE7) 522 #endif 523 /** 524 * @brief Returns the current DMA Channel Global interrupt flag. 525 * @param __HANDLE__: DMA handle 526 * @retval The specified transfer error flag index. 527 */ 528 #if defined (STM32L011xx) || defined (STM32L021xx) 529 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 530 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 534 DMA_ISR_GIF5) 535 #else 536 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 537 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 543 DMA_ISR_GIF7) 544 #endif 545 /** 546 * @brief Get the DMA Channel pending flags. 547 * @param __HANDLE__: DMA handle 548 * @param __FLAG__: Get the specified flag. 549 * This parameter can be any combination of the following values: 550 * @arg DMA_FLAG_TCIFx: Transfer complete flag 551 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 552 * @arg DMA_FLAG_TEIFx: Transfer error flag 553 * @arg DMA_ISR_GIFx: Global interrupt flag 554 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. 555 * @retval The state of FLAG (SET or RESET). 556 */ 557 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 558 559 /** 560 * @brief Clears the DMA Channel pending flags. 561 * @param __HANDLE__: DMA handle 562 * @param __FLAG__: specifies the flag to clear. 563 * This parameter can be any combination of the following values: 564 * @arg DMA_FLAG_TCIFx: Transfer complete flag 565 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 566 * @arg DMA_FLAG_TEIFx: Transfer error flag 567 * @arg DMA_ISR_GIFx: Global interrupt flag 568 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. 569 * @retval None 570 */ 571 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 572 573 /** 574 * @brief Enables the specified DMA Channel interrupts. 575 * @param __HANDLE__: DMA handle 576 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 577 * This parameter can be any combination of the following values: 578 * @arg DMA_IT_TC: Transfer complete interrupt mask 579 * @arg DMA_IT_HT: Half transfer complete interrupt mask 580 * @arg DMA_IT_TE: Transfer error interrupt mask 581 * @retval None 582 */ 583 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 584 585 /** 586 * @brief Disables the specified DMA Channel interrupts. 587 * @param __HANDLE__: DMA handle 588 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 589 * This parameter can be any combination of the following values: 590 * @arg DMA_IT_TC: Transfer complete interrupt mask 591 * @arg DMA_IT_HT: Half transfer complete interrupt mask 592 * @arg DMA_IT_TE: Transfer error interrupt mask 593 * @retval None 594 */ 595 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 596 597 /** 598 * @brief Checks whether the specified DMA Channel interrupt is enabled or not. 599 * @param __HANDLE__: DMA handle 600 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 601 * This parameter can be one of the following values: 602 * @arg DMA_IT_TC: Transfer complete interrupt mask 603 * @arg DMA_IT_HT: Half transfer complete interrupt mask 604 * @arg DMA_IT_TE: Transfer error interrupt mask 605 * @retval The state of DMA_IT (SET or RESET). 606 */ 607 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 608 609 /** 610 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. 611 * @param __HANDLE__: DMA handle 612 * 613 * @retval The number of remaining data units in the current DMA Channel transfer. 614 */ 615 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 616 617 /** 618 * @} 619 */ 620 621 /* Exported functions --------------------------------------------------------*/ 622 623 /** @defgroup DMA_Exported_Functions DMA Exported Functions 624 * @{ 625 */ 626 627 /** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions 628 * @{ 629 */ 630 631 /* Initialization and de-initialization functions *****************************/ 632 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 633 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 634 635 /** 636 * @} 637 */ 638 639 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 640 * @{ 641 */ 642 643 /* IO operation functions *****************************************************/ 644 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 645 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 646 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 647 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 648 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); 649 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 650 /** 651 * @} 652 */ 653 654 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 655 * @{ 656 */ 657 658 /* Peripheral State and Error functions ***************************************/ 659 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 660 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 661 662 /** 663 * @} 664 */ 665 666 /** 667 * @} 668 */ 669 /* Define the private group ***********************************/ 670 /**************************************************************/ 671 /** @defgroup DMA_Private DMA Private 672 * @{ 673 */ 674 /** 675 * @} 676 */ 677 /**************************************************************/ 678 679 /** 680 * @} 681 */ 682 683 /** 684 * @} 685 */ 686 687 #ifdef __cplusplus 688 } 689 #endif 690 691 #endif /* __STM32L0xx_HAL_DMA_H */ 692 693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 694 695
