1 /**
2 ******************************************************************************
3 * @file stm32l0xx_hal_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32L0xx_HAL_CORTEX_H
38 #define __STM32L0xx_HAL_CORTEX_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32l0xx_hal_def.h"
46
47 /** @addtogroup STM32L0xx_HAL_Driver
48 * @{
49 */
50
51 /** @defgroup CORTEX CORTEX
52 * @{
53 */
54 /* Exported types ------------------------------------------------------------*/
55
56 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
57 * @{
58 */
59
60 #if (__MPU_PRESENT == 1)
61 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
62 * @{
63 */
64 typedef struct
65 {
66 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
67
68 uint8_t Enable; /*!< Specifies the status of the region.
69 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
70 uint8_t Number; /*!< Specifies the number of the region to protect.
71 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
72
73 uint8_t Size; /*!< Specifies the size of the region to protect.
74 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
75 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
77 uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/
78
79 uint8_t AccessPermission; /*!< Specifies the region access permission type.
80 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
81 uint8_t DisableExec; /*!< Specifies the instruction access status.
82 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
83 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
84 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
85 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
86 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
87 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
88 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
89 }MPU_Region_InitTypeDef;
90 /**
91 * @}
92 */
93 #endif /* __MPU_PRESENT */
94
95 /**
96 * @}
97 */
98
99
100 /* Exported constants --------------------------------------------------------*/
101
102 /** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants
103 * @{
104 */
105
106
107 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4U)
108
109 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0)
110
111 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
112 * @{
113 */
114 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
115 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
116 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
117 ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
118 /**
119 * @}
120 */
121
122 #if (__MPU_PRESENT == 1)
123 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
124 * @{
125 */
126 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
127 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
128 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
129 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
130 /**
131 * @}
132 */
133
134 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
135 * @{
136 */
137 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
138 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
139 /**
140 * @}
141 */
142
143 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
144 * @{
145 */
146 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
147 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
148 /**
149 * @}
150 */
151
152 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
153 * @{
154 */
155 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
156 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
157 /**
158 * @}
159 */
160
161 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
162 * @{
163 */
164 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
165 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
166 /**
167 * @}
168 */
169
170 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
171 * @{
172 */
173 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
174 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
175 /**
176 * @}
177 */
178
179 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
180 * @{
181 */
182 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
183 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
184 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
185 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
186 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
187 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
188 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
189 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
190 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
191 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
192 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
193 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
194 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
195 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
196 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
197 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
198 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
199 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
200 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
201 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
202 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
203 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
204 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
205 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
206 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
207 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
208 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
209 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
210 /**
211 * @}
212 */
213
214 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
215 * @{
216 */
217 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
218 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
219 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
220 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
221 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
222 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
223 /**
224 * @}
225 */
226
227 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
228 * @{
229 */
230 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
231 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
232 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
233 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
234 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
235 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
236 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
237 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
238 /**
239 * @}
240 */
241 #endif /* __MPU_PRESENT */
242
243
244 /**
245 * @}
246 */
247
248 /* Exported functions --------------------------------------------------------*/
249 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
250 * @{
251 */
252
253 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
254 * @brief Initialization and Configuration functions
255 * @{
256 */
257 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
258 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
259 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
260 void HAL_NVIC_SystemReset(void);
261 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
262 #if (__MPU_PRESENT == 1)
263 /**
264 * @brief Disable the MPU.
265 * @retval None
266 */
HAL_MPU_Disable(void)267 __STATIC_INLINE void HAL_MPU_Disable(void)
268 {
269
270 /*Data Memory Barrier setup */
271 __DMB();
272 /* Disable the MPU */
273 MPU->CTRL = 0;
274 }
275
276 /**
277 * @brief Enable the MPU.
278 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
279 * NMI, FAULTMASK and privileged access to the default memory
280 * This parameter can be one of the following values:
281 * @arg MPU_HFNMI_PRIVDEF_NONE
282 * @arg MPU_HARDFAULT_NMI
283 * @arg MPU_PRIVILEGED_DEFAULT
284 * @arg MPU_HFNMI_PRIVDEF
285 * @retval None
286 */
287
HAL_MPU_Enable(uint32_t MPU_Control)288 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
289 {
290 /* Enable the MPU */
291 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
292 /* Data Synchronization Barrier setup */
293 __DSB();
294 /* Instruction Synchronization Barrier setup */
295 __ISB();
296
297 }
298 #endif /* __MPU_PRESENT */
299 /**
300 * @}
301 */
302
303 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
304 * @brief Cortex control functions
305 * @{
306 */
307
308 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
309 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
310 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
311 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
312 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
313 void HAL_SYSTICK_IRQHandler(void);
314 void HAL_SYSTICK_Callback(void);
315 #if (__MPU_PRESENT == 1)
316 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
317 #endif /* __MPU_PRESENT */
318 /**
319 * @}
320 */
321
322 /**
323 * @}
324 */
325
326 /* Private types -------------------------------------------------------------*/
327 /* Private variables ---------------------------------------------------------*/
328 /* Private constants ---------------------------------------------------------*/
329 /* Private macros ------------------------------------------------------------*/
330 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
331 * @{
332 */
333
334 #if (__MPU_PRESENT == 1)
335 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
336 ((STATE) == MPU_REGION_DISABLE))
337
338 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
339 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
340
341 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
342 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
343
344 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
345 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
346
347 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
348 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
349
350 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
351 ((TYPE) == MPU_REGION_PRIV_RW) || \
352 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
353 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
354 ((TYPE) == MPU_REGION_PRIV_RO) || \
355 ((TYPE) == MPU_REGION_PRIV_RO_URO))
356
357 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
358 ((NUMBER) == MPU_REGION_NUMBER1) || \
359 ((NUMBER) == MPU_REGION_NUMBER2) || \
360 ((NUMBER) == MPU_REGION_NUMBER3) || \
361 ((NUMBER) == MPU_REGION_NUMBER4) || \
362 ((NUMBER) == MPU_REGION_NUMBER5) || \
363 ((NUMBER) == MPU_REGION_NUMBER6) || \
364 ((NUMBER) == MPU_REGION_NUMBER7))
365
366 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \
367 ((SIZE) == MPU_REGION_SIZE_512B) || \
368 ((SIZE) == MPU_REGION_SIZE_1KB) || \
369 ((SIZE) == MPU_REGION_SIZE_2KB) || \
370 ((SIZE) == MPU_REGION_SIZE_4KB) || \
371 ((SIZE) == MPU_REGION_SIZE_8KB) || \
372 ((SIZE) == MPU_REGION_SIZE_16KB) || \
373 ((SIZE) == MPU_REGION_SIZE_32KB) || \
374 ((SIZE) == MPU_REGION_SIZE_64KB) || \
375 ((SIZE) == MPU_REGION_SIZE_128KB) || \
376 ((SIZE) == MPU_REGION_SIZE_256KB) || \
377 ((SIZE) == MPU_REGION_SIZE_512KB) || \
378 ((SIZE) == MPU_REGION_SIZE_1MB) || \
379 ((SIZE) == MPU_REGION_SIZE_2MB) || \
380 ((SIZE) == MPU_REGION_SIZE_4MB) || \
381 ((SIZE) == MPU_REGION_SIZE_8MB) || \
382 ((SIZE) == MPU_REGION_SIZE_16MB) || \
383 ((SIZE) == MPU_REGION_SIZE_32MB) || \
384 ((SIZE) == MPU_REGION_SIZE_64MB) || \
385 ((SIZE) == MPU_REGION_SIZE_128MB) || \
386 ((SIZE) == MPU_REGION_SIZE_256MB) || \
387 ((SIZE) == MPU_REGION_SIZE_512MB) || \
388 ((SIZE) == MPU_REGION_SIZE_1GB) || \
389 ((SIZE) == MPU_REGION_SIZE_2GB) || \
390 ((SIZE) == MPU_REGION_SIZE_4GB))
391
392 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
393 #endif /* __MPU_PRESENT */
394
395
396 /**
397 * @}
398 */
399
400 /**
401 * @}
402 */
403
404 /**
405 * @}
406 */
407
408 #ifdef __cplusplus
409 }
410 #endif
411
412 #endif /* __STM32L0xx_HAL_CORTEX_H */
413
414
415 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
416
417
