1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_LL_SDMMC_H 21 #define STM32H7xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 /** @addtogroup STM32H7xx_Driver 31 * @{ 32 */ 33 #if defined (SDMMC1) || defined (SDMMC2) 34 /** @addtogroup SDMMC_LL 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SDMMC Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change. 49 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 50 51 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 52 disabled when the bus is idle. 53 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 54 55 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 56 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 57 58 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 59 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 60 61 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 62 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 63 64 #if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U) 65 uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. 66 This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ 67 #endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */ 68 } SDMMC_InitTypeDef; 69 70 71 /** 72 * @brief SDMMC Command Control structure 73 */ 74 typedef struct 75 { 76 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 77 to a card as part of a command message. If a command 78 contains an argument, it must be loaded into this register 79 before writing the command to the command register. */ 80 81 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 82 Max_Data = 64 */ 83 84 uint32_t Response; /*!< Specifies the SDMMC response type. 85 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 86 87 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 88 enabled or disabled. 89 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 90 91 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 92 is enabled or disabled. 93 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 94 } SDMMC_CmdInitTypeDef; 95 96 97 /** 98 * @brief SDMMC Data Control structure 99 */ 100 typedef struct 101 { 102 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 103 104 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 105 106 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 107 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 108 109 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 110 is a read or write. 111 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 112 113 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 114 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 115 116 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 117 is enabled or disabled. 118 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 119 } SDMMC_DataInitTypeDef; 120 121 /** 122 * @} 123 */ 124 125 /* Exported constants --------------------------------------------------------*/ 126 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 127 * @{ 128 */ 129 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 130 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 131 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 132 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 133 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 134 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 135 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 136 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 137 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ 138 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 139 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 140 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 141 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ 142 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 143 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 144 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 145 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 146 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 147 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 148 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 149 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 150 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 151 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 152 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ 153 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 154 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 155 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 156 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 157 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 158 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 159 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 160 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 161 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 162 163 /** 164 * @brief Masks for R5 Response 165 */ 166 /** this is the reserved for future use in spec RFU */ 167 #define SDMMC_SDIO_R5_ERROR ((uint32_t)0x00000400U) 168 /** Out of range error */ 169 #define SDMMC_SDIO_R5_OUT_OF_RANGE ((uint32_t)0x00000100U) 170 /** Invalid function number */ 171 #define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER ((uint32_t)0x00000200U) 172 /** General or an unknown error */ 173 #define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00000800U) 174 /** SDIO Card current state 175 * 00=DIS (card not selected) 176 * 01=CMD (data line free) 177 * 10=TRN (transfer on data lines) */ 178 #define SDMMC_SDIO_R5_IO_CURRENT_STATE ((uint32_t)0x00003000U) 179 /** Illegal command error */ 180 #define SDMMC_SDIO_R5_ILLEGAL_CMD ((uint32_t)0x00004000U) 181 /** CRC check of previous cmd failed */ 182 #define SDMMC_SDIO_R5_COM_CRC_FAILED ((uint32_t)0x00008000U) 183 184 #define SDMMC_SDIO_R5_ERRORBITS (SDMMC_SDIO_R5_COM_CRC_FAILED | \ 185 SDMMC_SDIO_R5_ILLEGAL_CMD | \ 186 SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR | \ 187 SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \ 188 SDMMC_SDIO_R5_OUT_OF_RANGE) 189 /** 190 * @brief SDIO_CMD53_MODE 191 */ 192 #define SDMMC_SDIO_MODE_BYTE 0x00U /*!< Byte Mode */ 193 #define SDMMC_SDIO_MODE_BLOCK 0x01U /*!< Block Mode */ 194 195 /** 196 * @brief SDIO_CMD53_OP_CODE 197 */ 198 #define SDMMC_SDIO_NO_INC 0x00U /*!< No auto indentation */ 199 #define SDMMC_SDIO_AUTO_INC 0x01U /*!< Auto indentation */ 200 201 /** 202 * @brief SDIO_CMD53_RAW 203 */ 204 #define SDMMC_SDIO_WO 0x00U /*!< Write only Flag */ 205 #define SDMMC_SDIO_RAW 0x01U /*!< Read after write Flag */ 206 207 /** 208 * @brief SDMMC Commands Index 209 */ 210 #define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ 211 #define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ 212 #define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 213 #define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ 214 #define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ 215 #define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ 216 #define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 217 #define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ 218 #define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ 219 #define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 220 #define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ 221 #define SDMMC_CMD_VOLTAGE_SWITCH 11U /*!< SD card Voltage switch to 1.8V mode. */ 222 #define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ 223 #define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ 224 #define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ 225 #define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ 226 #define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ 227 /*!< for SDHS and SDXC. */ 228 #define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 229 #define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ 230 #define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 231 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ 232 #define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ 233 #define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 234 #define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 235 #define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ 236 #define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ 237 #define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ 238 #define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ 239 #define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ 240 #define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ 241 #define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ 242 #define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ 243 #define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ 244 #define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ 245 #define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ 246 #define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ 247 #define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ 248 #define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ 249 #define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ 250 #define SDMMC_CMD_NO_CMD 64U /*!< No command */ 251 252 /** 253 * @brief Following commands are SD Card Specific commands. 254 * SDMMC_APP_CMD should be sent before sending these commands. 255 */ 256 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ 257 #define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ 258 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ 259 #define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ 260 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 261 #define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ 262 #define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ 263 #define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ 264 265 /** 266 * @brief Following commands are MMC Specific commands. 267 */ 268 #define SDMMC_CMD_MMC_SLEEP_AWAKE 5U /*!< Toggle the device between Sleep state and Standby state. */ 269 270 /** 271 * @brief Following commands are SD Card Specific security commands. 272 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 273 */ 274 #define SDMMC_CMD_SD_APP_GET_MKB 43U 275 #define SDMMC_CMD_SD_APP_GET_MID 44U 276 #define SDMMC_CMD_SD_APP_SET_CER_RN1 45U 277 #define SDMMC_CMD_SD_APP_GET_CER_RN2 46U 278 #define SDMMC_CMD_SD_APP_SET_CER_RES2 47U 279 #define SDMMC_CMD_SD_APP_GET_CER_RES1 48U 280 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U 281 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U 282 #define SDMMC_CMD_SD_APP_SECURE_ERASE 38U 283 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U 284 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U 285 286 /** 287 * @brief Masks for errors Card Status R1 (OCR Register) 288 */ 289 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 290 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 291 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 292 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 293 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 294 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 295 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 296 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 297 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 298 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 299 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 300 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 301 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 302 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 303 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 304 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 305 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 306 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 307 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 308 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 309 310 /** 311 * @brief Masks for R6 Response 312 */ 313 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 314 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 315 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 316 317 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 318 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 319 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 320 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 321 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 322 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) 323 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 324 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 325 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 326 #define SDMMC_SDR12_SWITCH_PATTERN ((uint32_t)0x80FFFF00U) 327 328 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 329 330 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 331 332 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 333 334 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 335 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 336 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 337 338 #ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ 339 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 340 #endif /* SDMMC_DATATIMEOUT */ 341 342 #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ 343 #define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) 344 #endif /* SDMMC_SWDATATIMEOUT */ 345 346 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 347 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 348 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 349 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 350 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 351 352 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 353 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 354 355 /* SDMMC FIFO Size */ 356 #define SDMMC_FIFO_SIZE 32U 357 /** 358 * @brief Command Class supported 359 */ 360 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 361 362 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 363 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 364 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 365 366 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 367 * @{ 368 */ 369 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 370 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 371 372 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 373 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 374 /** 375 * @} 376 */ 377 378 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 379 * @{ 380 */ 381 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 382 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 383 384 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 385 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 386 /** 387 * @} 388 */ 389 390 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 391 * @{ 392 */ 393 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 394 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 395 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 396 397 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 398 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 399 ((WIDE) == SDMMC_BUS_WIDE_8B)) 400 /** 401 * @} 402 */ 403 404 /** @defgroup SDMMC_LL_Speed_Mode 405 * @{ 406 */ 407 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) 408 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) 409 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) 410 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) 411 #define SDMMC_SPEED_MODE_ULTRA_SDR104 SDMMC_SPEED_MODE_ULTRA 412 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) 413 #define SDMMC_SPEED_MODE_ULTRA_SDR50 ((uint32_t)0x00000005U) 414 415 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ 416 ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ 417 ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ 418 ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ 419 ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50) || \ 420 ((MODE) == SDMMC_SPEED_MODE_DDR)) 421 422 /** 423 * @} 424 */ 425 426 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 427 * @{ 428 */ 429 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 430 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 431 432 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 433 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 434 /** 435 * @} 436 */ 437 438 /** @defgroup SDMMC_LL_Clock_Division Clock Division 439 * @{ 440 */ 441 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 442 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 443 /** 444 * @} 445 */ 446 447 /** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present 448 * @{ 449 */ 450 #define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U) 451 #define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U) 452 #define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U) 453 454 /** 455 * @} 456 */ 457 458 /** @defgroup SDMMC_LL_Command_Index Command Index 459 * @{ 460 */ 461 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 462 /** 463 * @} 464 */ 465 466 /** @defgroup SDMMC_LL_Response_Type Response Type 467 * @{ 468 */ 469 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 470 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 471 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 472 473 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 474 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 475 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 476 /** 477 * @} 478 */ 479 480 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 481 * @{ 482 */ 483 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 484 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 485 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 486 487 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 488 ((WAIT) == SDMMC_WAIT_IT) || \ 489 ((WAIT) == SDMMC_WAIT_PEND)) 490 /** 491 * @} 492 */ 493 494 /** @defgroup SDMMC_LL_CPSM_State CPSM State 495 * @{ 496 */ 497 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 498 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 499 500 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 501 ((CPSM) == SDMMC_CPSM_ENABLE)) 502 /** 503 * @} 504 */ 505 506 /** @defgroup SDMMC_LL_Response_Registers Response Register 507 * @{ 508 */ 509 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 510 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 511 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 512 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 513 514 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 515 ((RESP) == SDMMC_RESP2) || \ 516 ((RESP) == SDMMC_RESP3) || \ 517 ((RESP) == SDMMC_RESP4)) 518 519 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 520 * @{ 521 */ 522 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 523 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 524 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 525 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 526 527 /** 528 * @} 529 */ 530 531 /** @defgroup SDMMC_LL_Data_Length Data Length 532 * @{ 533 */ 534 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 535 /** 536 * @} 537 */ 538 539 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 540 * @{ 541 */ 542 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 543 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 544 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 545 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 546 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 547 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 548 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 549 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 550 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 551 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 552 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 553 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 554 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 555 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 556 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 557 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 558 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 559 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \ 560 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 561 562 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 563 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 564 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 565 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 566 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 567 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 568 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 569 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 570 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 571 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 572 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 573 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 574 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 575 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 576 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 577 /** 578 * @} 579 */ 580 581 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 582 * @{ 583 */ 584 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 585 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 586 587 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 588 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 589 /** 590 * @} 591 */ 592 593 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 594 * @{ 595 */ 596 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 597 #define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0 598 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 599 600 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 601 ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \ 602 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 603 /** 604 * @} 605 */ 606 607 /** @defgroup SDMMC_LL_DPSM_State DPSM State 608 * @{ 609 */ 610 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 611 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 612 613 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 614 ((DPSM) == SDMMC_DPSM_ENABLE)) 615 /** 616 * @} 617 */ 618 619 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 620 * @{ 621 */ 622 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 623 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 624 625 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 626 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 627 /** 628 * @} 629 */ 630 631 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 632 * @{ 633 */ 634 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 635 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 636 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 637 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 638 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 639 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 640 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 641 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 642 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 643 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 644 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 645 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 646 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 647 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 648 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 649 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 650 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 651 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 652 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 653 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 654 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 655 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 656 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 657 /** 658 * @} 659 */ 660 661 /** @defgroup SDMMC_LL_Flags Flags 662 * @{ 663 */ 664 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 665 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 666 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 667 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 668 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 669 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 670 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 671 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 672 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 673 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 674 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 675 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 676 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 677 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 678 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 679 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 680 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 681 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 682 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 683 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 684 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 685 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 686 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 687 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 688 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 689 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 690 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 691 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 692 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 693 694 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 695 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 696 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 697 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 698 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 699 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 700 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 701 702 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 703 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 704 705 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 706 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 707 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 708 SDMMC_FLAG_IDMABTC)) 709 /** 710 * @} 711 */ 712 713 /** @defgroup SDMMC_SDIO_CCCR_Registers 714 * @{ 715 */ 716 /*-------------------------------- CCCR0 ----------------------------------*/ 717 #define SDMMC_SDIO_CCCR0 0x000U /*!< SDIOS Card Common Control Register 0 */ 718 #define SDMMC_SDIO_CCCR0_SD_BYTE0 0x000U /*!< SDIOS Card Common Control Register 0 Byte 0 */ 719 #define SDMMC_SDIO_CCCR0_SD_BYTE1 0x001U /*!< SDIOS Card Common Control Register 0 Byte 1 */ 720 #define SDMMC_SDIO_CCCR0_SD_BYTE2 0x002U /*!< SDIOS Card Common Control Register 0 Byte 2 */ 721 #define SDMMC_SDIO_CCCR0_SD_BYTE3 0x003U /*!< SDIOS Card Common Control Register 0 Byte 3 */ 722 723 /*-------------------------------- CCCR4 ----------------------------------*/ 724 #define SDMMC_SDIO_CCCR4 0x004U /*!< SDIOS Card Common Control Register 4 */ 725 #define SDMMC_SDIO_CCCR4_SD_BYTE0 0x004U /*!< SDIOS Card Common Control Register 4 Byte 0 */ 726 #define SDMMC_SDIO_CCCR4_SD_BYTE1 0x005U /*!< SDIOS Card Common Control Register 4 Byte 1 */ 727 #define SDMMC_SDIO_CCCR4_SD_BYTE2 0x006U /*!< SDIOS Card Common Control Register 4 Byte 2 */ 728 #define SDMMC_SDIO_CCCR4_SD_BYTE3 0x007U /*!< SDIOS Card Common Control Register 4 Byte 3 */ 729 730 /*-------------------------------- CCCR8 ----------------------------------*/ 731 #define SDMMC_SDIO_CCCR8 0x008U /*!< SDIOS Card Common Control Register 8 */ 732 #define SDMMC_SDIO_CCCR8_SD_BYTE0 0x008U /*!< SDIOS Card Common Control Register 8 Byte 0 */ 733 #define SDMMC_SDIO_CCCR8_SD_BYTE1 0x009U /*!< SDIOS Card Common Control Register 8 Byte 1 */ 734 #define SDMMC_SDIO_CCCR8_SD_BYTE2 0x00AU /*!< SDIOS Card Common Control Register 8 Byte 2 */ 735 #define SDMMC_SDIO_CCCR8_SD_BYTE3 0x00BU /*!< SDIOS Card Common Control Register 8 Byte 3 */ 736 737 /*-------------------------------- CCCR12 ---------------------------------*/ 738 #define SDMMC_SDIO_CCCR12 0x00CU /*!< SDIOS Card Common Control Register 12 */ 739 #define SDMMC_SDIO_CCCR12_SD_BYTE0 0x00CU /*!< SDIOS Card Common Control Register 12 Byte 0 */ 740 #define SDMMC_SDIO_CCCR12_SD_BYTE1 0x00DU /*!< SDIOS Card Common Control Register 12 Byte 1 */ 741 #define SDMMC_SDIO_CCCR12_SD_BYTE2 0x00EU /*!< SDIOS Card Common Control Register 12 Byte 2 */ 742 #define SDMMC_SDIO_CCCR12_SD_BYTE3 0x00FU /*!< SDIOS Card Common Control Register 12 Byte 3 */ 743 744 /*-------------------------------- CCCR16 ---------------------------------*/ 745 #define SDMMC_SDIO_CCCR16 0x010U /*!< SDIOS Card Common Control Register 16 */ 746 #define SDMMC_SDIO_CCCR16_SD_BYTE0 0x010U /*!< SDIOS Card Common Control Register 16 Byte 0 */ 747 #define SDMMC_SDIO_CCCR16_SD_BYTE1 0x011U /*!< SDIOS Card Common Control Register 16 Byte 1 */ 748 #define SDMMC_SDIO_CCCR16_SD_BYTE2 0x012U /*!< SDIOS Card Common Control Register 16 Byte 2 */ 749 #define SDMMC_SDIO_CCCR16_SD_BYTE3 0x013U /*!< SDIOS Card Common Control Register 16 Byte 3 */ 750 751 /*-------------------------------- CCCR20 ---------------------------------*/ 752 #define SDMMC_SDIO_CCCR20 0x014U /*!< SDIOS Card Common Control Register 20 */ 753 #define SDMMC_SDIO_CCCR20_SD_BYTE0 0x014U /*!< SDIOS Card Common Control Register 20 Byte 0 */ 754 #define SDMMC_SDIO_CCCR20_SD_BYTE1 0x015U /*!< SDIOS Card Common Control Register 20 Byte 1 */ 755 #define SDMMC_SDIO_CCCR20_SD_BYTE2 0x016U /*!< SDIOS Card Common Control Register 20 Byte 2 */ 756 #define SDMMC_SDIO_CCCR20_SD_BYTE3 0x017U /*!< SDIOS Card Common Control Register 20 Byte 3 */ 757 758 /*-------------------------------- F1BR0 ----------------------------------*/ 759 #define SDMMC_SDIO_F1BR0 0x100U /*!< SDIOS Function 1 Basic Register 0 */ 760 #define SDMMC_SDIO_F1BR0_SD_BYTE0 0x100U /*!< SDIOS Function 1 Basic Register 0 Byte 0 */ 761 #define SDMMC_SDIO_F1BR0_SD_BYTE1 0x101U /*!< SDIOS Function 1 Basic Register 0 Byte 1 */ 762 #define SDMMC_SDIO_F1BR0_SD_BYTE2 0x102U /*!< SDIOS Function 1 Basic Register 0 Byte 2 */ 763 #define SDMMC_SDIO_F1BR0_SD_BYTE3 0x103U /*!< SDIOS Function 1 Basic Register 0 Byte 3 */ 764 765 /*-------------------------------- F1BR8 ----------------------------------*/ 766 #define SDMMC_SDIO_F1BR8 0x108U /*!< SDIOS Function 1 Basic Register 8 */ 767 #define SDMMC_SDIO_F1BR8_SD_BYTE0 0x108U /*!< SDIOS Function 1 Basic Register 8 Byte 0 */ 768 #define SDMMC_SDIO_F1BR8_SD_BYTE1 0x109U /*!< SDIOS Function 1 Basic Register 8 Byte 1 */ 769 #define SDMMC_SDIO_F1BR8_SD_BYTE2 0x10AU /*!< SDIOS Function 1 Basic Register 8 Byte 2 */ 770 #define SDMMC_SDIO_F1BR8_SD_BYTE3 0x10BU /*!< SDIOS Function 1 Basic Register 8 Byte 3 */ 771 772 /*-------------------------------- F1BR12 ---------------------------------*/ 773 #define SDMMC_SDIO_F1BR12 0x10CU /*!< SDIOS Function 1 Basic Register 12 */ 774 #define SDMMC_SDIO_F1BR12_SD_BYTE0 0x10CU /*!< SDIOS Function 1 Basic Register 12 Byte 0 */ 775 #define SDMMC_SDIO_F1BR12_SD_BYTE1 0x10DU /*!< SDIOS Function 1 Basic Register 12 Byte 1 */ 776 #define SDMMC_SDIO_F1BR12_SD_BYTE2 0x10EU /*!< SDIOS Function 1 Basic Register 12 Byte 2 */ 777 #define SDMMC_SDIO_F1BR12_SD_BYTE3 0x10FU /*!< SDIOS Function 1 Basic Register 12 Byte 3 */ 778 779 /*-------------------------------- F1BR16 ---------------------------------*/ 780 #define SDMMC_SDIO_F1BR16 0x110U /*!< SDIOS Function 1 Basic Register 16 */ 781 #define SDMMC_SDIO_F1BR16_SD_BYTE0 0x110U /*!< SDIOS Function 1 Basic Register 16 Byte 0 */ 782 #define SDMMC_SDIO_F1BR16_SD_BYTE1 0x111U /*!< SDIOS Function 1 Basic Register 16 Byte 1 */ 783 #define SDMMC_SDIO_F1BR16_SD_BYTE2 0x112U /*!< SDIOS Function 1 Basic Register 16 Byte 2 */ 784 #define SDMMC_SDIO_F1BR16_SD_BYTE3 0x113U /*!< SDIOS Function 1 Basic Register 16 Byte 3 */ 785 /** 786 * @} 787 */ 788 789 /** 790 * @} 791 */ 792 793 /* Exported macro ------------------------------------------------------------*/ 794 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 795 * @{ 796 */ 797 798 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 799 * @brief SDMMC_LL registers bit address in the alias region 800 * @{ 801 */ 802 /* ---------------------- SDMMC registers bit mask --------------------------- */ 803 /* --- CLKCR Register ---*/ 804 /* CLKCR register clear mask */ 805 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 806 SDMMC_CLKCR_WIDBUS |\ 807 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ 808 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ 809 SDMMC_CLKCR_SELCLKRX)) 810 811 /* --- DCTRL Register ---*/ 812 /* SDMMC DCTRL Clear Mask */ 813 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 814 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 815 816 /* --- CMD Register ---*/ 817 /* CMD Register clear mask */ 818 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 819 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 820 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 821 822 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/ 823 #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA) 824 825 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/ 826 #define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4) 827 828 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/ 829 #define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2) 830 /** 831 * @} 832 */ 833 834 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 835 * @brief macros to handle interrupts and specific clock configurations 836 * @{ 837 */ 838 839 /** 840 * @brief Enable the SDMMC device interrupt. 841 * @param __INSTANCE__ Pointer to SDMMC register base 842 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. 843 * This parameter can be one or a combination of the following values: 844 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 845 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 846 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 847 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 848 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 849 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 850 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 851 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 852 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 853 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 854 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 855 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 856 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 857 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 858 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 859 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 860 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 861 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 862 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 863 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 864 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 865 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 866 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 867 * @retval None 868 */ 869 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 870 871 /** 872 * @brief Disable the SDMMC device interrupt. 873 * @param __INSTANCE__ Pointer to SDMMC register base 874 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. 875 * This parameter can be one or a combination of the following values: 876 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 877 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 878 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 879 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 880 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 881 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 882 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 883 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 884 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 885 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 886 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 887 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 888 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 889 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 890 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 891 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 892 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 893 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 894 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 895 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 896 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 897 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 898 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 899 * @retval None 900 */ 901 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 902 903 /** 904 * @brief Checks whether the specified SDMMC flag is set or not. 905 * @param __INSTANCE__ Pointer to SDMMC register base 906 * @param __FLAG__ specifies the flag to check. 907 * This parameter can be one of the following values: 908 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 909 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 910 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 911 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 912 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 913 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 914 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 915 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 916 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 917 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 918 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 919 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 920 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 921 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 922 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 923 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 924 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 925 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 926 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 927 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 928 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 929 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 930 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 931 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 932 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 933 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 934 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 935 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 936 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 937 * @retval The new state of SDMMC_FLAG (SET or RESET). 938 */ 939 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 940 941 942 /** 943 * @brief Clears the SDMMC pending flags. 944 * @param __INSTANCE__ Pointer to SDMMC register base 945 * @param __FLAG__ specifies the flag to clear. 946 * This parameter can be one or a combination of the following values: 947 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 948 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 949 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 950 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 951 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 952 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 953 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 954 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 955 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 956 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 957 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 958 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 959 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 960 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 961 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 962 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 963 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 964 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 965 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 966 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 967 * @retval None 968 */ 969 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 970 971 /** 972 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 973 * @param __INSTANCE__ Pointer to SDMMC register base 974 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 975 * This parameter can be one of the following values: 976 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 977 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 978 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 979 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 980 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 981 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 982 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 983 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 984 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 985 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 986 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 987 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 988 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 989 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 990 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 991 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 992 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 993 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 994 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 995 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 996 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 997 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 998 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 999 * @retval The new state of SDMMC_IT (SET or RESET). 1000 */ 1001 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 1002 1003 /** 1004 * @brief Checks the source of specified interrupt. 1005 * @param __INSTANCE__ Pointer to SDMMC register base 1006 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 1007 * This parameter can be one of the following values: 1008 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1009 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1010 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1011 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1012 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1013 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1014 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1015 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1016 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1017 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1018 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1019 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1020 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 1021 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 1022 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 1023 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 1024 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1025 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1026 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1027 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1028 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1029 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1030 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1031 * @retval The new state of SDMMC_IT (SET or RESET). 1032 */ 1033 #define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__))) 1034 1035 /** 1036 * @brief Clears the SDMMC's interrupt pending bits. 1037 * @param __INSTANCE__ Pointer to SDMMC register base 1038 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1039 * This parameter can be one or a combination of the following values: 1040 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1041 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1042 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1043 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1044 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1045 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1046 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1047 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1048 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1049 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1050 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1051 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1052 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1053 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1054 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1055 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1056 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1057 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1058 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1059 * @retval None 1060 */ 1061 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 1062 1063 /** 1064 * @brief Enable Start the SD I/O Read Wait operation. 1065 * @param __INSTANCE__ Pointer to SDMMC register base 1066 * @retval None 1067 */ 1068 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 1069 1070 /** 1071 * @brief Disable Start the SD I/O Read Wait operations. 1072 * @param __INSTANCE__ Pointer to SDMMC register base 1073 * @retval None 1074 */ 1075 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 1076 1077 /** 1078 * @brief Enable Start the SD I/O Read Wait operation. 1079 * @param __INSTANCE__ Pointer to SDMMC register base 1080 * @retval None 1081 */ 1082 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 1083 1084 /** 1085 * @brief Disable Stop the SD I/O Read Wait operations. 1086 * @param __INSTANCE__ Pointer to SDMMC register base 1087 * @retval None 1088 */ 1089 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 1090 1091 /** 1092 * @brief Enable the SD I/O Mode Operation. 1093 * @param __INSTANCE__ Pointer to SDMMC register base 1094 * @retval None 1095 */ 1096 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 1097 1098 /** 1099 * @brief Disable the SD I/O Mode Operation. 1100 * @param __INSTANCE__ Pointer to SDMMC register base 1101 * @retval None 1102 */ 1103 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 1104 1105 /** 1106 * @brief Enable the SD I/O Suspend command sending. 1107 * @param __INSTANCE__ Pointer to SDMMC register base 1108 * @retval None 1109 */ 1110 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 1111 1112 /** 1113 * @brief Disable the SD I/O Suspend command sending. 1114 * @param __INSTANCE__ Pointer to SDMMC register base 1115 * @retval None 1116 */ 1117 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 1118 1119 /** 1120 * @brief Enable the CMDTRANS mode. 1121 * @param __INSTANCE__ Pointer to SDMMC register base 1122 * @retval None 1123 */ 1124 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 1125 1126 /** 1127 * @brief Disable the CMDTRANS mode. 1128 * @param __INSTANCE__ Pointer to SDMMC register base 1129 * @retval None 1130 */ 1131 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 1132 1133 /** 1134 * @brief Enable the CMDSTOP mode. 1135 * @param __INSTANCE__ Pointer to SDMMC register base 1136 * @retval None 1137 */ 1138 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 1139 1140 /** 1141 * @brief Disable the CMDSTOP mode. 1142 * @param __INSTANCE__ Pointer to SDMMC register base 1143 * @retval None 1144 */ 1145 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 1146 1147 /** 1148 * @} 1149 */ 1150 1151 /** 1152 * @} 1153 */ 1154 1155 /* Exported functions --------------------------------------------------------*/ 1156 /** @addtogroup SDMMC_LL_Exported_Functions 1157 * @{ 1158 */ 1159 1160 /* Initialization/de-initialization functions **********************************/ 1161 /** @addtogroup HAL_SDMMC_LL_Group1 1162 * @{ 1163 */ 1164 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 1165 /** 1166 * @} 1167 */ 1168 1169 /* I/O operation functions *****************************************************/ 1170 /** @addtogroup HAL_SDMMC_LL_Group2 1171 * @{ 1172 */ 1173 uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx); 1174 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 1175 /** 1176 * @} 1177 */ 1178 1179 /* Peripheral Control functions ************************************************/ 1180 /** @addtogroup HAL_SDMMC_LL_Group3 1181 * @{ 1182 */ 1183 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 1184 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 1185 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1186 uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); 1187 1188 /* Command path state machine (CPSM) management functions */ 1189 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); 1190 uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); 1191 uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); 1192 1193 /* Data path state machine (DPSM) management functions */ 1194 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); 1195 uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); 1196 uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); 1197 1198 /* SDMMC Cards mode management functions */ 1199 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1200 /** 1201 * @} 1202 */ 1203 1204 /* SDMMC Commands management functions ******************************************/ 1205 /** @addtogroup HAL_SDMMC_LL_Group4 1206 * @{ 1207 */ 1208 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1209 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1210 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1211 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1212 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1213 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1214 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1215 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1216 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1217 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); 1218 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1219 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr); 1220 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1221 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1222 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1223 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1224 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1225 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1226 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1227 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1228 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1229 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); 1230 uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1231 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1232 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1233 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1234 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1235 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1236 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1237 uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); 1238 uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse); 1239 uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1240 uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp); 1241 /** 1242 * @} 1243 */ 1244 1245 /* SDMMC Responses management functions *****************************************/ 1246 /** @addtogroup HAL_SDMMC_LL_Group5 1247 * @{ 1248 */ 1249 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); 1250 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); 1251 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); 1252 uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp); 1253 uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData); 1254 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); 1255 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); 1256 /** 1257 * @} 1258 */ 1259 1260 1261 /** 1262 * @} 1263 */ 1264 1265 /** 1266 * @} 1267 */ 1268 1269 /** 1270 * @} 1271 */ 1272 1273 /** 1274 * @} 1275 */ 1276 #endif /* SDMMC1 || SDMMC2 */ 1277 /** 1278 * @} 1279 */ 1280 #ifdef __cplusplus 1281 } 1282 #endif 1283 1284 #endif /* STM32H7xx_LL_SDMMC_H */ 1285
