1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef STM32H7xx_LL_BUS_H
37 #define STM32H7xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32h7xx.h"
45
46 /** @addtogroup STM32H7xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private variables ---------------------------------------------------------*/
57
58 /* Private constants ---------------------------------------------------------*/
59
60 /* Private macros ------------------------------------------------------------*/
61
62 /* Exported types ------------------------------------------------------------*/
63
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN
73 #define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN
74
75 #if defined(JPEG)
76 #define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN
77 #endif /* JPEG */
78
79 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
80 #if defined(QUADSPI)
81 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
82 #endif /* QUADSPI */
83 #if defined(OCTOSPI1) || defined(OCTOSPI2)
84 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
85 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
86 #endif /*(OCTOSPI1) || (OCTOSPI2)*/
87 #if defined(OCTOSPIM)
88 #define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN
89 #endif /* OCTOSPIM */
90 #if defined(OTFDEC1) || defined(OTFDEC2)
91 #define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN
92 #define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN
93 #endif /* (OTFDEC1) || (OTFDEC2) */
94 #if defined(GFXMMU)
95 #define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN
96 #endif /* GFXMMU */
97 #define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN
98 #define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN
99 #define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN
100 #define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN
101 #define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN
102 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
103 #define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN
104 #else
105 #define LL_AHB3_GRP1_PERIPH_AXISRAM1 RCC_AHB3LPENR_AXISRAM1LPEN
106 #define LL_AHB3_GRP1_PERIPH_AXISRAM LL_AHB3_GRP1_PERIPH_AXISRAM1 /* for backward compatibility*/
107 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
108 #if defined(CD_AXISRAM2_BASE)
109 #define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN
110 #endif /* CD_AXISRAM2_BASE */
111 #if defined(CD_AXISRAM3_BASE)
112 #define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN
113 #endif /* CD_AXISRAM3_BASE */
114 /**
115 * @}
116 */
117
118
119 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
120 * @{
121 */
122 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
123 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
124 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
125 #if defined(DUAL_CORE)
126 #define LL_AHB1_GRP1_PERIPH_ART RCC_AHB1ENR_ARTEN
127 #endif /* DUAL_CORE */
128 #if defined(RCC_AHB1ENR_CRCEN)
129 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
130 #endif /* RCC_AHB1ENR_CRCEN */
131 #if defined(ETH)
132 #define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN
133 #define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN
134 #define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN
135 #endif /* ETH */
136 #define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN
137 #define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN
138 #if defined(USB2_OTG_FS)
139 #define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN
140 #define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN
141 #endif /* USB2_OTG_FS */
142 /**
143 * @}
144 */
145
146
147 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
148 * @{
149 */
150 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
151 #if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)
152 #define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN
153 #endif /* HSEM && RCC_AHB2ENR_HSEMEN */
154 #if defined(CRYP)
155 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
156 #endif /* CRYP */
157 #if defined(HASH)
158 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
159 #endif /* HASH */
160 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
161 #define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
162 #if defined(FMAC)
163 #define LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN
164 #endif /* FMAC */
165 #if defined(CORDIC)
166 #define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN
167 #endif /* CORDIC */
168 #if defined(BDMA1)
169 #define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN
170 #endif /* BDMA1 */
171 #if defined(RCC_AHB2ENR_D2SRAM1EN)
172 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN
173 #else
174 #define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN
175 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/
176 #endif /* RCC_AHB2ENR_D2SRAM1EN */
177 #if defined(RCC_AHB2ENR_D2SRAM2EN)
178 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN
179 #else
180 #define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN
181 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/
182 #endif /* RCC_AHB2ENR_D2SRAM2EN */
183 #if defined(RCC_AHB2ENR_D2SRAM3EN)
184 #define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN
185 #endif /* RCC_AHB2ENR_D2SRAM3EN */
186 /**
187 * @}
188 */
189
190
191 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
192 * @{
193 */
194 #define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
195 #define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
196 #define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
197 #define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
198 #define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
199 #define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
200 #define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
201 #define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
202 #if defined(GPIOI)
203 #define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN
204 #endif /* GPIOI */
205 #define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN
206 #define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN
207 #if defined(RCC_AHB4ENR_CRCEN)
208 #define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN
209 #endif /* RCC_AHB4ENR_CRCEN */
210 #if defined(BDMA2)
211 #define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN
212 #define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/
213 #else
214 #define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN
215 #endif /* BDMA2 */
216 #if defined(ADC3)
217 #define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN
218 #endif /* ADC3 */
219 #if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)
220 #define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN
221 #endif /* HSEM && RCC_AHB4ENR_HSEMEN*/
222 #define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN
223 #if defined(RCC_AHB4LPENR_SRAM4LPEN)
224 #define LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN
225 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4
226 #else
227 #define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN
228 #define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
229 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
230 #endif /* RCC_AHB4ENR_D3SRAM1EN */
231 /**
232 * @}
233 */
234
235
236 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
237 * @{
238 */
239 #if defined(LTDC)
240 #define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN
241 #endif /* LTDC */
242 #if defined(DSI)
243 #define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN
244 #endif /* DSI */
245 #define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN
246 #if defined(RCC_APB3ENR_WWDGEN)
247 #define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/
248 #endif /* RCC_APB3ENR_WWDGEN */
249 /**
250 * @}
251 */
252
253
254 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
255 * @{
256 */
257 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
258 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
259 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
260 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
261 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
262 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
263 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
264 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
265 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
266 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN
267 #if defined(DUAL_CORE)
268 #define LL_APB1_GRP1_PERIPH_WWDG2 RCC_APB1LENR_WWDG2EN
269 #endif /*DUAL_CORE*/
270 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
271 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
272 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN
273 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
274 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
275 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
276 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
277 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
278 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
279 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN
280 #if defined(I2C5)
281 #define LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN
282 #endif /* I2C5 */
283 #if defined(RCC_APB1LENR_CECEN)
284 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
285 #else
286 #define LL_APB1_GRP1_PERIPH_HDMICEC RCC_APB1LENR_HDMICECEN
287 #define LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_HDMICEC /* for backward compatibility*/
288 #endif /* RCC_APB1LENR_CECEN */
289 #define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN
290 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
291 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
292 /**
293 * @}
294 */
295
296
297 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
298 * @{
299 */
300 #define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN
301 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN
302 #define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN
303 #define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN
304 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
305 #if defined(TIM23)
306 #define LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN
307 #endif /* TIM23 */
308 #if defined(TIM24)
309 #define LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN
310 #endif /* TIM24 */
311 /**
312 * @}
313 */
314
315
316 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
317 * @{
318 */
319 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
320 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
321 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
322 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
323 #if defined(UART9)
324 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
325 #endif /* UART9 */
326 #if defined(USART10)
327 #define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN
328 #endif /* USART10 */
329 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
330 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
331 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
332 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
333 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
334 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
335 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
336 #if defined(SAI2)
337 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
338 #endif /* SAI2 */
339 #if defined(SAI3)
340 #define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN
341 #endif /* SAI3 */
342 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
343 #if defined(HRTIM1)
344 #define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN
345 #endif /* HRTIM1 */
346 /**
347 * @}
348 */
349
350
351 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH
352 * @{
353 */
354 #define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN
355 #define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN
356 #define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN
357 #define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN
358 #define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN
359 #define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN
360 #if defined(LPTIM4)
361 #define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN
362 #endif /* LPTIM4 */
363 #if defined(LPTIM5)
364 #define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN
365 #endif /* LPTIM5 */
366 #if defined(DAC2)
367 #define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN
368 #endif /* DAC2 */
369 #define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN
370 #define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN
371 #define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN
372 #if defined(SAI4)
373 #define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN
374 #endif /* SAI4 */
375 #if defined(DTS)
376 #define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN
377 #endif /*DTS*/
378 #if defined(DFSDM2_BASE)
379 #define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN
380 #endif /* DFSDM2_BASE */
381 /**
382 * @}
383 */
384
385 /** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH
386 * @{
387 */
388 #if defined(RCC_D3AMR_BDMAAMEN)
389 #define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN
390 #else
391 #define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN
392 #define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
393 #endif /* RCC_D3AMR_BDMAAMEN */
394 #if defined(RCC_SRDAMR_GPIOAMEN)
395 #define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN
396 #endif /* RCC_SRDAMR_GPIOAMEN */
397 #if defined(RCC_D3AMR_LPUART1AMEN)
398 #define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN
399 #else
400 #define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN
401 #endif /* RCC_D3AMR_LPUART1AMEN */
402 #if defined(RCC_D3AMR_SPI6AMEN)
403 #define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN
404 #else
405 #define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN
406 #endif /* RCC_D3AMR_SPI6AMEN */
407 #if defined(RCC_D3AMR_I2C4AMEN)
408 #define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN
409 #else
410 #define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN
411 #endif /* RCC_D3AMR_I2C4AMEN */
412 #if defined(RCC_D3AMR_LPTIM2AMEN)
413 #define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN
414 #else
415 #define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN
416 #endif /* RCC_D3AMR_LPTIM2AMEN */
417 #if defined(RCC_D3AMR_LPTIM3AMEN)
418 #define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN
419 #else
420 #define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN
421 #endif /* RCC_D3AMR_LPTIM3AMEN */
422 #if defined(RCC_D3AMR_LPTIM4AMEN)
423 #define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN
424 #endif /* RCC_D3AMR_LPTIM4AMEN */
425 #if defined(RCC_D3AMR_LPTIM5AMEN)
426 #define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN
427 #endif /* RCC_D3AMR_LPTIM5AMEN */
428 #if defined(DAC2)
429 #define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN
430 #endif /* DAC2 */
431 #if defined(RCC_D3AMR_COMP12AMEN)
432 #define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN
433 #else
434 #define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN
435 #endif /* RCC_D3AMR_COMP12AMEN */
436 #if defined(RCC_D3AMR_VREFAMEN)
437 #define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN
438 #else
439 #define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN
440 #endif /* RCC_D3AMR_VREFAMEN */
441 #if defined(RCC_D3AMR_RTCAMEN)
442 #define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN
443 #else
444 #define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN
445 #endif /* RCC_D3AMR_RTCAMEN */
446 #if defined(RCC_D3AMR_CRCAMEN)
447 #define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN
448 #endif /* RCC_D3AMR_CRCAMEN */
449 #if defined(SAI4)
450 #define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN
451 #endif /* SAI4 */
452 #if defined(ADC3)
453 #define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN
454 #endif /* ADC3 */
455 #if defined(RCC_SRDAMR_DTSAMEN)
456 #define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN
457 #endif /* RCC_SRDAMR_DTSAMEN */
458 #if defined(RCC_D3AMR_DTSAMEN)
459 #define LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN
460 #endif /* RCC_D3AMR_DTSAMEN */
461 #if defined(DFSDM2_BASE)
462 #define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN
463 #endif /* DFSDM2_BASE */
464 #if defined(RCC_D3AMR_BKPRAMAMEN)
465 #define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN
466 #else
467 #define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN
468 #endif /* RCC_D3AMR_BKPRAMAMEN */
469 #if defined(RCC_D3AMR_SRAM4AMEN)
470 #define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN
471 #else
472 #define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN
473 #define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM
474 #endif /* RCC_D3AMR_SRAM4AMEN */
475 /**
476 * @}
477 */
478
479 #if defined(RCC_CKGAENR_AXICKG)
480 /** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH
481 * @{
482 */
483 #define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG
484 #define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG
485 #define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG
486 #define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG
487 #define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG
488 #define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG
489 #define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG
490 #define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG
491 #define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG
492 #define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG
493 #define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG
494 #define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG
495 #define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG
496 #define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG
497 #define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG
498 #define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG
499 #define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG
500 #define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG
501 #define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG
502 #define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG
503 #define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG
504 /**
505 * @}
506 */
507 #endif /* RCC_CKGAENR_AXICKG */
508
509 /**
510 * @}
511 */
512
513 /* Exported macro ------------------------------------------------------------*/
514
515 /* Exported functions --------------------------------------------------------*/
516
517 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
518 * @{
519 */
520
521 /** @defgroup BUS_LL_EF_AHB3 AHB3
522 * @{
523 */
524
525 /**
526 * @brief Enable AHB3 peripherals clock.
527 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n
528 * AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n
529 * AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n
530 * AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
531 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n (*)
532 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n (*)
533 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock\n (*)
534 * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*)
535 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*)
536 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*)
537 * AHB3ENR GFXMMUEN LL_AHB3_GRP1_EnableClock\n (*)
538 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n
539 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*)
540 * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*)
541 * AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n (*)
542 * AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n (*)
543 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*)
544 * @param Periphs This parameter can be a combination of the following values:
545 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
546 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
547 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
548 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
549 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
550 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
551 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
552 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
553 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
554 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
555 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
556 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
557 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
558 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
559 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
560 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
561 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
562 *
563 * (*) value not defined in all devices.
564 * @retval None
565 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)566 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
567 {
568 __IO uint32_t tmpreg;
569 SET_BIT(RCC->AHB3ENR, Periphs);
570 /* Delay after an RCC peripheral clock enabling */
571 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
572 (void)tmpreg;
573 }
574
575 /**
576 * @brief Check if AHB3 peripheral clock is enabled or not
577 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n
578 * AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n
579 * AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n
580 * AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
581 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n (*)
582 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
583 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
584 * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*)
585 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
586 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
587 * AHB3ENR GFXMMUEN LL_AHB3_GRP1_IsEnabledClock\n (*)
588 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n
589 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*)
590 * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
591 * AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
592 * AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n (*)
593 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*)
594 * @param Periphs This parameter can be a combination of the following values:
595 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
596 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
597 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
598 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
599 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
600 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
601 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
602 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
603 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
604 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
605 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
606 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
607 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
608 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
609 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
610 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
611 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
612 *
613 * (*) value not defined in all devices.
614 * @retval uint32_t
615 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)616 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
617 {
618 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U);
619 }
620
621 /**
622 * @brief Disable AHB3 peripherals clock.
623 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n
624 * AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n
625 * AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n
626 * AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
627 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n (*)
628 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n (*)
629 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock\n (*)
630 * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*)
631 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*)
632 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*)
633 * AHB3ENR GFXMMUEN LL_AHB3_GRP1_DisableClock\n (*)
634 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*)
635 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*)
636 * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*)
637 * AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n (*)
638 * AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n (*)
639 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock
640 * @param Periphs This parameter can be a combination of the following values:
641 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
642 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
643 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
644 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
645 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
646 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
647 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
648 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
649 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
650 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
651 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
652 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
653 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
654 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
655 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
656 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
657 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
658 *
659 * (*) value not defined in all devices.
660 * @retval None
661 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)662 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
663 {
664 CLEAR_BIT(RCC->AHB3ENR, Periphs);
665 }
666
667 /**
668 * @brief Force AHB3 peripherals reset.
669 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n
670 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n
671 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n
672 * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
673 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*)
674 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*)
675 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*)
676 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset\n (*)
677 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset\n (*)
678 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset\n (*)
679 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset\n (*)
680 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset
681 * @param Periphs This parameter can be a combination of the following values:
682 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
683 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
684 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
685 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
686 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
687 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
688 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
689 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
690 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
691 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
692 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
693 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
694 *
695 * (*) value not defined in all devices.
696 * @retval None
697 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)698 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
699 {
700 SET_BIT(RCC->AHB3RSTR, Periphs);
701 }
702
703 /**
704 * @brief Release AHB3 peripherals reset.
705 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n
706 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n
707 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n
708 * AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
709 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
710 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n (*)
711 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset\n (*)
712 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset\n (*)
713 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset\n (*)
714 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset\n (*)
715 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset\n (*)
716 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset
717 * @param Periphs This parameter can be a combination of the following values:
718 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
719 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
720 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
721 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
722 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
723 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
724 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
725 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
726 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
727 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
728 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
729 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
730 *
731 * (*) value not defined in all devices.
732 * @retval None
733 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)734 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
735 {
736 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
737 }
738
739 /**
740 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode.
741 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n
742 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n
743 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n
744 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n
745 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
746 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
747 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
748 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
749 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
750 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
751 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
752 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n
753 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n
754 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n
755 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n
756 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n
757 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep
758 * @param Periphs This parameter can be a combination of the following values:
759 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
760 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
761 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
762 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
763 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
764 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
765 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
766 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
767 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
768 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
769 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
770 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
771 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
772 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
773 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
774 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
775 *
776 * (*) value not defined in all devices.
777 * @retval None
778 */
LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)779 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
780 {
781 __IO uint32_t tmpreg;
782 SET_BIT(RCC->AHB3LPENR, Periphs);
783 /* Delay after an RCC peripheral clock enabling */
784 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
785 (void)tmpreg;
786 }
787
788 /**
789 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode.
790 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n
791 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n
792 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n
793 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n
794 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n
795 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
796 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
797 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
798 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
799 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
800 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
801 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n
802 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n
803 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n
804 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n
805 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n
806 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep
807 * @param Periphs This parameter can be a combination of the following values:
808 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
809 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
810 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
811 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
812 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
813 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
814 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
815 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
816 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
817 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
818 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
819 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
820 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
821 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
822 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
823 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
824 *
825 * (*) value not defined in all devices.
826 * @retval None
827 */
LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)828 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
829 {
830 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
831 }
832
833 /**
834 * @}
835 */
836
837 /** @defgroup BUS_LL_EF_AHB1 AHB1
838 * @{
839 */
840
841 /**
842 * @brief Enable AHB1 peripherals clock.
843 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
844 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
845 * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n
846 * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n
847 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n (*)
848 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*)
849 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*)
850 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*)
851 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n
852 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n
853 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n (*)
854 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*)
855 * @param Periphs This parameter can be a combination of the following values:
856 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
857 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
858 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
859 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
860 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
861 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
862 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
863 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
864 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
865 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
866 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
867 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
868 *
869 * (*) value not defined in all devices.
870 * @retval None
871 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)872 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
873 {
874 __IO uint32_t tmpreg;
875 SET_BIT(RCC->AHB1ENR, Periphs);
876 /* Delay after an RCC peripheral clock enabling */
877 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
878 (void)tmpreg;
879 }
880
881 /**
882 * @brief Check if AHB1 peripheral clock is enabled or not
883 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
884 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
885 * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
886 * AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n (*)
887 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n (*)
888 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n (*)
889 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n (*)
890 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n (*)
891 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
892 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n
893 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n (*)
894 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*)
895 * @param Periphs This parameter can be a combination of the following values:
896 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
897 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
898 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
899 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
900 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
901 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
902 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
903 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
904 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
905 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
906 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
907 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
908 *
909 * (*) value not defined in all devices.
910 * @retval uint32_t
911 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)912 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
913 {
914 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U);
915 }
916
917 /**
918 * @brief Disable AHB1 peripherals clock.
919 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
920 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
921 * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n
922 * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*)
923 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n (*)
924 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*)
925 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*)
926 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*)
927 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n
928 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n
929 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n (*)
930 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*)
931 * @param Periphs This parameter can be a combination of the following values:
932 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
933 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
934 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
935 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
936 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
937 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
938 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
939 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
940 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
941 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
942 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
943 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
944 *
945 * (*) value not defined in all devices.
946 * @retval None
947 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)948 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
949 {
950 CLEAR_BIT(RCC->AHB1ENR, Periphs);
951 }
952
953 /**
954 * @brief Force AHB1 peripherals reset.
955 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
956 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
957 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
958 * AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n (*)
959 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n (*)
960 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n (*)
961 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n
962 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*)
963 * @param Periphs This parameter can be a combination of the following values:
964 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
965 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
966 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
967 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
968 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
969 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
970 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
971 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
972 *
973 * (*) value not defined in all devices.
974 * @retval None
975 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)976 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
977 {
978 SET_BIT(RCC->AHB1RSTR, Periphs);
979 }
980
981 /**
982 * @brief Release AHB1 peripherals reset.
983 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
984 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
985 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
986 * AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n (*)
987 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n (*)
988 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n (*)
989 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n
990 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*)
991 * @param Periphs This parameter can be a combination of the following values:
992 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
993 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
994 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
995 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
996 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
997 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
998 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
999 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
1000 *
1001 * (*) value not defined in all devices.
1002 * @retval None
1003 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)1004 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
1005 {
1006 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
1007 }
1008
1009 /**
1010 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
1011 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
1012 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
1013 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n
1014 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1015 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1016 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1017 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1018 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n
1019 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n
1020 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n
1021 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1022 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*)
1023 * @param Periphs This parameter can be a combination of the following values:
1024 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
1025 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
1026 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
1027 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
1028 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
1029 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
1030 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
1031 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
1032 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
1033 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
1034 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
1035 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
1036 *
1037 * (*) value not defined in all devices.
1038 * @retval None
1039 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)1040 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
1041 {
1042 __IO uint32_t tmpreg;
1043 SET_BIT(RCC->AHB1LPENR, Periphs);
1044 /* Delay after an RCC peripheral clock enabling */
1045 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
1046 (void)tmpreg;
1047 }
1048
1049 /**
1050 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
1051 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
1052 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
1053 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n
1054 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1055 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1056 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1057 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1058 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1059 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n
1060 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n
1061 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1062 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*)
1063 * @param Periphs This parameter can be a combination of the following values:
1064 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
1065 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
1066 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
1067 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
1068 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
1069 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
1070 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
1071 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
1072 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
1073 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
1074 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
1075 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
1076 *
1077 * (*) value not defined in all devices.
1078 * @retval None
1079 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)1080 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
1081 {
1082 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
1083 }
1084
1085 /**
1086 * @}
1087 */
1088
1089 /** @defgroup BUS_LL_EF_AHB2 AHB2
1090 * @{
1091 */
1092
1093 /**
1094 * @brief Enable AHB2 peripherals clock.
1095 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
1096 * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n (*)
1097 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n (*)
1098 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n (*)
1099 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
1100 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n
1101 * AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*)
1102 * AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock\n
1103 * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n
1104 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n
1105 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n
1106 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*)
1107 * @param Periphs This parameter can be a combination of the following values:
1108 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1109 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1110 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1111 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1112 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1113 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1114 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1115 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1116 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1117 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1118 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1119 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1120 *
1121 * (*) value not defined in all devices.
1122 * @retval None
1123 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)1124 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
1125 {
1126 __IO uint32_t tmpreg;
1127 SET_BIT(RCC->AHB2ENR, Periphs);
1128 /* Delay after an RCC peripheral clock enabling */
1129 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
1130 (void)tmpreg;
1131 }
1132
1133 /**
1134 * @brief Check if AHB2 peripheral clock is enabled or not
1135 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
1136 * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1137 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1138 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1139 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
1140 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
1141 * AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*)
1142 * AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock\n
1143 * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n
1144 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n
1145 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
1146 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*)
1147 * @param Periphs This parameter can be a combination of the following values:
1148 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1149 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1150 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1151 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1152 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1153 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1154 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1155 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1156 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1157 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1158 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1159 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1160 *
1161 * (*) value not defined in all devices.
1162 * @retval uint32_t
1163 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)1164 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
1165 {
1166 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U);
1167 }
1168
1169 /**
1170 * @brief Disable AHB2 peripherals clock.
1171 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
1172 * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n (*)
1173 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n (*)
1174 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n (*)
1175 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
1176 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n
1177 * AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*)
1178 * AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock\n
1179 * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n
1180 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n
1181 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n
1182 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*)
1183 * @param Periphs This parameter can be a combination of the following values:
1184 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1185 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1186 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1187 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1188 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1189 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1190 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1191 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1192 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1193 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1194 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1195 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1196 *
1197 * (*) value not defined in all devices.
1198 * @retval None
1199 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)1200 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
1201 {
1202 CLEAR_BIT(RCC->AHB2ENR, Periphs);
1203 }
1204
1205 /**
1206 * @brief Force AHB2 peripherals reset.
1207 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
1208 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n (*)
1209 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n (*)
1210 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*)
1211 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
1212 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n
1213 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset\n (*)
1214 * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n
1215 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset
1216 * @param Periphs This parameter can be a combination of the following values:
1217 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1218 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1219 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1220 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1221 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1222 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1223 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1224 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1225 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1226 *
1227 * (*) value not defined in all devices.
1228 * @retval None
1229 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)1230 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
1231 {
1232 SET_BIT(RCC->AHB2RSTR, Periphs);
1233 }
1234
1235 /**
1236 * @brief Release AHB2 peripherals reset.
1237 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
1238 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n (*)
1239 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n (*)
1240 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*)
1241 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
1242 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n
1243 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset\n (*)
1244 * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n
1245 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset
1246 * @param Periphs This parameter can be a combination of the following values:
1247 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1248 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1249 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1250 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1251 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1252 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1253 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1254 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1255 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1256 *
1257 * (*) value not defined in all devices.
1258 * @retval None
1259 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)1260 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
1261 {
1262 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
1263 }
1264
1265 /**
1266 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
1267 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n
1268 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1269 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1270 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n
1271 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n
1272 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1273 * AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep\n
1274 * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n
1275 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n
1276 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n
1277 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*)
1278 * @param Periphs This parameter can be a combination of the following values:
1279 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1280 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1281 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1282 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1283 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1284 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1285 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1286 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1287 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1288 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1289 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1290 *
1291 * (*) value not defined in all devices.
1292 * @retval None
1293 */
LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)1294 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
1295 {
1296 __IO uint32_t tmpreg;
1297 SET_BIT(RCC->AHB2LPENR, Periphs);
1298 /* Delay after an RCC peripheral clock enabling */
1299 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
1300 (void)tmpreg;
1301 }
1302
1303 /**
1304 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode.
1305 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n
1306 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1307 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1308 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n
1309 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n
1310 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1311 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n
1312 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n
1313 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*)
1314 * @param Periphs This parameter can be a combination of the following values:
1315 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1316 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1317 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1318 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1319 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1320 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1321 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1322 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1323 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1324 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1325 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1326 *
1327 * (*) value not defined in all devices.
1328 * @retval None
1329 */
LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)1330 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
1331 {
1332 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
1333 }
1334
1335 /**
1336 * @}
1337 */
1338
1339 /** @defgroup BUS_LL_EF_AHB4 AHB4
1340 * @{
1341 */
1342
1343 /**
1344 * @brief Enable AHB4 peripherals clock.
1345 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n
1346 * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n
1347 * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n
1348 * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n
1349 * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n
1350 * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n
1351 * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n
1352 * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n
1353 * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n (*)
1354 * AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n
1355 * AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n
1356 * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*)
1357 * AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n
1358 * AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n (*)
1359 * AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n (*)
1360 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n
1361 * AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock
1362 * @param Periphs This parameter can be a combination of the following values:
1363 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1364 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1365 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1366 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1367 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1368 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1369 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1370 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1371 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1372 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1373 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1374 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1375 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1376 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1377 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1378 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1379 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1380 *
1381 * (*) value not defined in all devices.
1382 * @retval None
1383 */
LL_AHB4_GRP1_EnableClock(uint32_t Periphs)1384 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
1385 {
1386 __IO uint32_t tmpreg;
1387 SET_BIT(RCC->AHB4ENR, Periphs);
1388 /* Delay after an RCC peripheral clock enabling */
1389 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
1390 (void)tmpreg;
1391 }
1392
1393 /**
1394 * @brief Check if AHB4 peripheral clock is enabled or not
1395 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n
1396 * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n
1397 * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n
1398 * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n
1399 * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n
1400 * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n
1401 * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n
1402 * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n
1403 * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n (*)
1404 * AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n
1405 * AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n
1406 * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*)
1407 * AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n
1408 * AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n (*)
1409 * AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n (*)
1410 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n
1411 * AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock
1412 * @param Periphs This parameter can be a combination of the following values:
1413 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1414 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1415 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1416 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1417 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1418 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1419 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1420 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1421 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1422 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1423 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1424 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1425 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1426 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1427 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1428 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1429 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1430 *
1431 * (*) value not defined in all devices.
1432 * @retval uint32_t
1433 */
LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)1434 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
1435 {
1436 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U);
1437 }
1438
1439 /**
1440 * @brief Disable AHB4 peripherals clock.
1441 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n
1442 * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n
1443 * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n
1444 * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n
1445 * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n
1446 * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n
1447 * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n
1448 * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n
1449 * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n (*)
1450 * AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n
1451 * AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n
1452 * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*)
1453 * AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n
1454 * AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n (*)
1455 * AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n (*)
1456 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n
1457 * AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock
1458 * @param Periphs This parameter can be a combination of the following values:
1459 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1460 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1461 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1462 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1463 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1464 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1465 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1466 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1467 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1468 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1469 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1470 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1471 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1472 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1473 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1474 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1475 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1476 *
1477 * (*) value not defined in all devices.
1478 * @retval None
1479 */
LL_AHB4_GRP1_DisableClock(uint32_t Periphs)1480 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
1481 {
1482 CLEAR_BIT(RCC->AHB4ENR, Periphs);
1483 }
1484
1485 /**
1486 * @brief Force AHB4 peripherals reset.
1487 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n
1488 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n
1489 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n
1490 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n
1491 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n
1492 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n
1493 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n
1494 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n
1495 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n (*)
1496 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n
1497 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n
1498 * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*)
1499 * AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n
1500 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n (*)
1501 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*)
1502 * @param Periphs This parameter can be a combination of the following values:
1503 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1504 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1505 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1506 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1507 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1508 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1509 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1510 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1511 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1512 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1513 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1514 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1515 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1516 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1517 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1518 *
1519 * (*) value not defined in all devices.
1520 * @retval None
1521 */
LL_AHB4_GRP1_ForceReset(uint32_t Periphs)1522 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
1523 {
1524 SET_BIT(RCC->AHB4RSTR, Periphs);
1525 }
1526
1527 /**
1528 * @brief Release AHB4 peripherals reset.
1529 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n
1530 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n
1531 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n
1532 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n
1533 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n
1534 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n
1535 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n
1536 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n
1537 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n (*)
1538 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n
1539 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n
1540 * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*)
1541 * AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n
1542 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n (*)
1543 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*)
1544 * @param Periphs This parameter can be a combination of the following values:
1545 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1546 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1547 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1548 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1549 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1550 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1551 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1552 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1553 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1554 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1555 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1556 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1557 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1558 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1559 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1560 *
1561 * (*) value not defined in all devices.
1562 * @retval None
1563 */
LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)1564 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
1565 {
1566 CLEAR_BIT(RCC->AHB4RSTR, Periphs);
1567 }
1568
1569 /**
1570 * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode.
1571 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n
1572 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n
1573 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n
1574 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n
1575 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n
1576 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n
1577 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n
1578 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n
1579 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
1580 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n
1581 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n
1582 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
1583 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n
1584 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
1585 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n
1586 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep
1587 * @param Periphs This parameter can be a combination of the following values:
1588 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1589 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1590 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1591 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1592 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1593 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1594 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1595 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1596 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1597 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1598 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1599 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1600 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1601 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1602 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1603 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1604 * @retval None
1605 */
LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)1606 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
1607 {
1608 __IO uint32_t tmpreg;
1609 SET_BIT(RCC->AHB4LPENR, Periphs);
1610 /* Delay after an RCC peripheral clock enabling */
1611 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
1612 (void)tmpreg;
1613 }
1614
1615 /**
1616 * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode.
1617 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n
1618 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n
1619 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n
1620 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n
1621 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n
1622 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n
1623 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n
1624 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n
1625 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
1626 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n
1627 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n
1628 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
1629 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n
1630 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
1631 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n
1632 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep
1633 * @param Periphs This parameter can be a combination of the following values:
1634 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1635 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1636 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1637 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1638 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1639 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1640 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1641 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1642 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1643 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1644 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1645 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1646 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1647 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1648 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1649 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1650 * @retval None
1651 */
LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)1652 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
1653 {
1654 CLEAR_BIT(RCC->AHB4LPENR, Periphs);
1655 }
1656
1657 /**
1658 * @}
1659 */
1660
1661 /** @defgroup BUS_LL_EF_APB3 APB3
1662 * @{
1663 */
1664
1665 /**
1666 * @brief Enable APB3 peripherals clock.
1667 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n (*)
1668 * APB3ENR DSIEN LL_APB3_GRP1_EnableClock\n (*)
1669 * APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock
1670 * @param Periphs This parameter can be a combination of the following values:
1671 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1672 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1673 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1674 *
1675 * (*) value not defined in all devices.
1676 * @retval None
1677 */
LL_APB3_GRP1_EnableClock(uint32_t Periphs)1678 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
1679 {
1680 __IO uint32_t tmpreg;
1681 SET_BIT(RCC->APB3ENR, Periphs);
1682 /* Delay after an RCC peripheral clock enabling */
1683 tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
1684 (void)tmpreg;
1685 }
1686
1687 /**
1688 * @brief Check if APB3 peripheral clock is enabled or not
1689 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n (*)
1690 * APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock\n (*)
1691 * APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock
1692 * @param Periphs This parameter can be a combination of the following values:
1693 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1694 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1695 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1696 *
1697 * (*) value not defined in all devices.
1698 * @retval uint32_t
1699 */
LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)1700 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
1701 {
1702 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1U : 0U);
1703 }
1704
1705 /**
1706 * @brief Disable APB3 peripherals clock.
1707 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n
1708 * APB3ENR DSIEN LL_APB3_GRP1_DisableClock\n
1709 * APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock
1710 * @param Periphs This parameter can be a combination of the following values:
1711 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1712 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1713 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1714 *
1715 * (*) value not defined in all devices.
1716 * @retval None
1717 */
LL_APB3_GRP1_DisableClock(uint32_t Periphs)1718 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
1719 {
1720 CLEAR_BIT(RCC->APB3ENR, Periphs);
1721 }
1722
1723 /**
1724 * @brief Force APB3 peripherals reset.
1725 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n (*)
1726 * APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*)
1727 * @param Periphs This parameter can be a combination of the following values:
1728 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1729 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1730 *
1731 * (*) value not defined in all devices.
1732 * @retval None
1733 */
LL_APB3_GRP1_ForceReset(uint32_t Periphs)1734 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
1735 {
1736 SET_BIT(RCC->APB3RSTR, Periphs);
1737 }
1738
1739 /**
1740 * @brief Release APB3 peripherals reset.
1741 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n
1742 * APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset
1743 * @param Periphs This parameter can be a combination of the following values:
1744 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1745 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1746 *
1747 * (*) value not defined in all devices.
1748 * @retval None
1749 */
LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)1750 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
1751 {
1752 CLEAR_BIT(RCC->APB3RSTR, Periphs);
1753 }
1754
1755 /**
1756 * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode.
1757 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n (*)
1758 * APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep\n (*)
1759 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep
1760 * @param Periphs This parameter can be a combination of the following values:
1761 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1762 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1763 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1764 *
1765 * (*) value not defined in all devices.
1766 * @retval None
1767 */
LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)1768 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
1769 {
1770 __IO uint32_t tmpreg;
1771 SET_BIT(RCC->APB3LPENR, Periphs);
1772 /* Delay after an RCC peripheral clock enabling */
1773 tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
1774 (void)tmpreg;
1775 }
1776
1777 /**
1778 * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode.
1779 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n (*)
1780 * APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep\n (*)
1781 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep
1782 * @param Periphs This parameter can be a combination of the following values:
1783 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1784 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1785 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1786 *
1787 * (*) value not defined in all devices.
1788 * @retval None
1789 */
LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)1790 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
1791 {
1792 CLEAR_BIT(RCC->APB3LPENR, Periphs);
1793 }
1794
1795 /**
1796 * @}
1797 */
1798
1799 /** @defgroup BUS_LL_EF_APB1 APB1
1800 * @{
1801 */
1802
1803 /**
1804 * @brief Enable APB1 peripherals clock.
1805 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n
1806 * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n
1807 * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n
1808 * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n
1809 * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n
1810 * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n
1811 * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n
1812 * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n
1813 * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n
1814 * APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1815 * APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n (*)
1816 * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n
1817 * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n
1818 * APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1819 * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n
1820 * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n
1821 * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n
1822 * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n
1823 * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n
1824 * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n
1825 * APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n
1826 * APB1LENR I2C5EN LL_APB1_GRP1_EnableClock\n (*)
1827 * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n
1828 * APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n
1829 * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n
1830 * APB1LENR UART8EN LL_APB1_GRP1_EnableClock
1831 * @param Periphs This parameter can be a combination of the following values:
1832 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1833 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1834 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1835 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1836 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1837 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1838 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1839 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1840 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1841 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1842 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1843 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1844 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1845 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1846 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1847 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1848 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1849 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1850 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1851 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1852 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1853 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
1854 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1855 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1856 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1857 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1858 *
1859 * (*) value not defined in all devices.
1860 * @retval None
1861 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1862 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1863 {
1864 __IO uint32_t tmpreg;
1865 SET_BIT(RCC->APB1LENR, Periphs);
1866 /* Delay after an RCC peripheral clock enabling */
1867 tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
1868 (void)tmpreg;
1869 }
1870
1871 /**
1872 * @brief Check if APB1 peripheral clock is enabled or not
1873 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1874 * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1875 * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1876 * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1877 * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1878 * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1879 * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1880 * APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1881 * APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1882 * APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1883 * APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n (*)
1884 * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1885 * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1886 * APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1887 * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1888 * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1889 * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1890 * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1891 * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1892 * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1893 * APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1894 * APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock\n (*)
1895 * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1896 * APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n
1897 * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1898 * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock
1899 * @param Periphs This parameter can be a combination of the following values:
1900 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1901 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1902 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1903 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1904 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1905 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1906 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1907 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1908 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1909 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1910 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1911 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1912 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1913 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1914 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1915 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1916 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1917 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1918 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1919 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1920 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1921 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
1922 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1923 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1924 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1925 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1926 *
1927 * (*) value not defined in all devices.
1928 * @retval uint32_t
1929 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1930 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1931 {
1932 return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1U : 0U);
1933 }
1934
1935 /**
1936 * @brief Disable APB1 peripherals clock.
1937 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n
1938 * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n
1939 * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n
1940 * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n
1941 * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n
1942 * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n
1943 * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n
1944 * APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n
1945 * APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n
1946 * APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1947 * APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n (*)
1948 * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n
1949 * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n
1950 * APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1951 * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n
1952 * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n
1953 * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n
1954 * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n
1955 * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n
1956 * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n
1957 * APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n
1958 * APB1LENR I2C5EN LL_APB1_GRP1_DisableClock\n (*)
1959 * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n
1960 * APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n
1961 * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n
1962 * APB1LENR UART8EN LL_APB1_GRP1_DisableClock
1963 * @param Periphs This parameter can be a combination of the following values:
1964 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1965 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1966 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1967 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1968 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1969 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1970 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1971 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1972 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1973 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1974 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1975 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1976 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1977 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1978 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1979 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1980 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1981 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1982 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1983 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1984 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1985 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
1986 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1987 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1988 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1989 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1990 *
1991 * (*) value not defined in all devices.
1992 * @retval None
1993 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1994 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1995 {
1996 CLEAR_BIT(RCC->APB1LENR, Periphs);
1997 }
1998
1999 /**
2000 * @brief Force APB1 peripherals reset.
2001 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n
2002 * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n
2003 * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n
2004 * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n
2005 * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n
2006 * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n
2007 * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n
2008 * APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n
2009 * APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n
2010 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
2011 * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n
2012 * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n
2013 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
2014 * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n
2015 * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n
2016 * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n
2017 * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n
2018 * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n
2019 * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n
2020 * APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n
2021 * APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset\n (*)
2022 * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n
2023 * APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n
2024 * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n
2025 * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset
2026 * @param Periphs This parameter can be a combination of the following values:
2027 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2028 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2029 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2030 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2031 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2033 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2034 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2035 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2036 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2037 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2038 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2039 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2040 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2041 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2042 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2043 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2044 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2045 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2046 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2047 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
2048 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2049 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2050 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2051 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2052 *
2053 * (*) value not defined in all devices.
2054 * @retval None
2055 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)2056 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
2057 {
2058 SET_BIT(RCC->APB1LRSTR, Periphs);
2059 }
2060
2061 /**
2062 * @brief Release APB1 peripherals reset.
2063 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
2064 * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
2065 * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
2066 * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
2067 * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
2068 * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
2069 * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
2070 * APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
2071 * APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
2072 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
2073 * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
2074 * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
2075 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
2076 * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
2077 * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
2078 * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
2079 * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
2080 * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
2081 * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
2082 * APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
2083 * APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset\n (*)
2084 * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n
2085 * APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n
2086 * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
2087 * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset
2088 * @param Periphs This parameter can be a combination of the following values:
2089 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2090 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2091 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2092 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2093 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2094 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2095 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2096 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2097 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2098 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2099 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2100 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2101 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2102 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2103 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2104 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2105 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2106 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2107 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2108 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2109 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
2110 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2111 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2112 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2113 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2114 *
2115 * (*) value not defined in all devices.
2116 * @retval None
2117 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)2118 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
2119 {
2120 CLEAR_BIT(RCC->APB1LRSTR, Periphs);
2121 }
2122
2123 /**
2124 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
2125 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
2126 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
2127 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
2128 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
2129 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
2130 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
2131 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n
2132 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n
2133 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n
2134 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n
2135 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n (*)
2136 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
2137 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
2138 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n
2139 * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
2140 * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
2141 * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
2142 * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
2143 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
2144 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
2145 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n
2146 * APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep\n (*)
2147 * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n
2148 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n
2149 * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n
2150 * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep
2151 * @param Periphs This parameter can be a combination of the following values:
2152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2155 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2158 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2160 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2161 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2162 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
2163 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2164 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2165 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2166 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2167 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2168 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2169 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2170 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2171 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2172 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2173 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
2174 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2175 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2176 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2177 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2178 *
2179 * (*) value not defined in all devices.
2180 * @retval None
2181 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)2182 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
2183 {
2184 __IO uint32_t tmpreg;
2185 SET_BIT(RCC->APB1LLPENR, Periphs);
2186 /* Delay after an RCC peripheral clock enabling */
2187 tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
2188 (void)tmpreg;
2189 }
2190
2191 /**
2192 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
2193 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
2194 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
2195 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
2196 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
2197 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
2198 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
2199 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n
2200 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n
2201 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n
2202 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n
2203 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n (*)
2204 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
2205 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
2206 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n
2207 * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
2208 * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
2209 * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
2210 * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
2211 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
2212 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
2213 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n
2214 * APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep\n (*)
2215 * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n
2216 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n
2217 * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n
2218 * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep
2219 * @param Periphs This parameter can be a combination of the following values:
2220 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2221 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2222 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2223 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2224 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2225 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2226 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2227 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2228 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2229 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2230 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
2231 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2232 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2233 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2234 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2235 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2236 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2237 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2238 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2239 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2240 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2241 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
2242 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2243 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2244 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2245 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2246 *
2247 * (*) value not defined in all devices.
2248 * @retval None
2249 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)2250 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
2251 {
2252 CLEAR_BIT(RCC->APB1LLPENR, Periphs);
2253 }
2254
2255 /**
2256 * @brief Enable APB1 peripherals clock.
2257 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n
2258 * APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n
2259 * APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n
2260 * APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n
2261 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock
2262 * @param Periphs This parameter can be a combination of the following values:
2263 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2264 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2265 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2266 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2267 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2268 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2269 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2270 *
2271 * (*) value not defined in all devices.
2272 * @retval None
2273 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)2274 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
2275 {
2276 __IO uint32_t tmpreg;
2277 SET_BIT(RCC->APB1HENR, Periphs);
2278 /* Delay after an RCC peripheral clock enabling */
2279 tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
2280 (void)tmpreg;
2281 }
2282
2283 /**
2284 * @brief Check if APB1 peripheral clock is enabled or not
2285 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n
2286 * APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n
2287 * APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n
2288 * APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n
2289 * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock
2290 * @param Periphs This parameter can be a combination of the following values:
2291 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2292 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2293 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2294 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2295 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2296 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2297 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2298 *
2299 * (*) value not defined in all devices.
2300 * @retval uint32_t
2301 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)2302 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
2303 {
2304 return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1U : 0U);
2305 }
2306
2307 /**
2308 * @brief Disable APB1 peripherals clock.
2309 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n
2310 * APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n
2311 * APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n
2312 * APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n
2313 * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock
2314 * @param Periphs This parameter can be a combination of the following values:
2315 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2316 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2317 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2318 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2319 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2320 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2321 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2322 *
2323 * (*) value not defined in all devices.
2324 * @retval None
2325 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)2326 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
2327 {
2328 CLEAR_BIT(RCC->APB1HENR, Periphs);
2329 }
2330
2331 /**
2332 * @brief Force APB1 peripherals reset.
2333 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n
2334 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n
2335 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n
2336 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n
2337 * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset
2338 * @param Periphs This parameter can be a combination of the following values:
2339 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2340 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2341 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2342 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2343 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2344 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2345 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2346 *
2347 * (*) value not defined in all devices.
2348 * @retval None
2349 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)2350 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
2351 {
2352 SET_BIT(RCC->APB1HRSTR, Periphs);
2353 }
2354
2355 /**
2356 * @brief Release APB1 peripherals reset.
2357 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n
2358 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n
2359 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n
2360 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n
2361 * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset
2362 * @param Periphs This parameter can be a combination of the following values:
2363 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2364 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2365 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2366 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2367 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2368 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2369 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2370 *
2371 * (*) value not defined in all devices.
2372 * @retval None
2373 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)2374 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
2375 {
2376 CLEAR_BIT(RCC->APB1HRSTR, Periphs);
2377 }
2378
2379 /**
2380 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
2381 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n
2382 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n
2383 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n
2384 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n
2385 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep
2386 * @param Periphs This parameter can be a combination of the following values:
2387 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2388 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2389 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2390 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2391 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2392 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2393 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2394 *
2395 * (*) value not defined in all devices.
2396 * @retval None
2397 */
LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)2398 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
2399 {
2400 __IO uint32_t tmpreg;
2401 SET_BIT(RCC->APB1HLPENR, Periphs);
2402 /* Delay after an RCC peripheral clock enabling */
2403 tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
2404 (void)tmpreg;
2405 }
2406
2407 /**
2408 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
2409 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n
2410 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n
2411 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n
2412 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n
2413 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep
2414 * @param Periphs This parameter can be a combination of the following values:
2415 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2416 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2417 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2418 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2419 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2420 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2421 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2422 *
2423 * (*) value not defined in all devices.
2424 * @retval None
2425 */
LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)2426 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
2427 {
2428 CLEAR_BIT(RCC->APB1HLPENR, Periphs);
2429 }
2430
2431 /**
2432 * @}
2433 */
2434
2435 /** @defgroup BUS_LL_EF_APB2 APB2
2436 * @{
2437 */
2438
2439 /**
2440 * @brief Enable APB2 peripherals clock.
2441 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
2442 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
2443 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
2444 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
2445 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n (*)
2446 * APB2ENR USART10EN LL_APB2_GRP1_EnableClock\n (*)
2447 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
2448 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
2449 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
2450 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
2451 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
2452 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
2453 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
2454 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
2455 * APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n (*)
2456 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
2457 * APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*)
2458 * @param Periphs This parameter can be a combination of the following values:
2459 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2460 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2461 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2462 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2463 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2464 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2465 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2466 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2467 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2468 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2469 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2470 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2471 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2472 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2473 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2474 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2475 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2476 *
2477 * (*) value not defined in all devices.
2478 * @retval None
2479 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)2480 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
2481 {
2482 __IO uint32_t tmpreg;
2483 SET_BIT(RCC->APB2ENR, Periphs);
2484 /* Delay after an RCC peripheral clock enabling */
2485 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
2486 (void)tmpreg;
2487 }
2488
2489 /**
2490 * @brief Check if APB2 peripheral clock is enabled or not
2491 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
2492 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
2493 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
2494 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
2495 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n (*)
2496 * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n (*)
2497 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
2498 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
2499 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
2500 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
2501 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
2502 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
2503 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
2504 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
2505 * APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n
2506 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
2507 * APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock
2508 * @param Periphs This parameter can be a combination of the following values:
2509 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2510 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2511 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2512 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2513 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2514 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2515 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2516 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2517 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2518 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2519 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2520 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2521 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2522 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2523 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2524 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2525 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2526 *
2527 * (*) value not defined in all devices.
2528 * @retval uint32_t
2529 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2530 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2531 {
2532 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U);
2533 }
2534
2535 /**
2536 * @brief Disable APB2 peripherals clock.
2537 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
2538 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
2539 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
2540 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
2541 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n (*)
2542 * APB2ENR USART10EN LL_APB2_GRP1_DisableClock\n (*)
2543 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
2544 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
2545 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
2546 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
2547 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
2548 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
2549 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
2550 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
2551 * APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n (*)
2552 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
2553 * APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*)
2554 * @param Periphs This parameter can be a combination of the following values:
2555 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2556 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2557 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2558 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2559 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2560 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2561 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2562 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2563 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2564 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2565 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2566 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2567 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2568 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2569 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2570 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2571 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2572 *
2573 * (*) value not defined in all devices.
2574 * @retval None
2575 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)2576 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2577 {
2578 CLEAR_BIT(RCC->APB2ENR, Periphs);
2579 }
2580
2581 /**
2582 * @brief Force APB2 peripherals reset.
2583 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
2584 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
2585 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
2586 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
2587 * APB2ENR UART9RST LL_APB2_GRP1_ForceReset\n (*)
2588 * APB2ENR USART10RST LL_APB2_GRP1_ForceReset\n (*)
2589 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
2590 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
2591 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
2592 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
2593 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
2594 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
2595 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
2596 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
2597 * APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n (*)
2598 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
2599 * APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*)
2600 * @param Periphs This parameter can be a combination of the following values:
2601 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2602 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2603 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2604 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2605 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2606 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2607 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2608 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2609 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2610 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2611 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2612 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2613 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2614 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2615 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2616 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2617 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2618 *
2619 * (*) value not defined in all devices.
2620 * @retval None
2621 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)2622 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
2623 {
2624 SET_BIT(RCC->APB2RSTR, Periphs);
2625 }
2626
2627 /**
2628 * @brief Release APB2 peripherals reset.
2629 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
2630 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
2631 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
2632 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
2633 * APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset\n (*)
2634 * APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset\n (*)
2635 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
2636 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
2637 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
2638 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
2639 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
2640 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
2641 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
2642 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
2643 * APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n (*)
2644 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
2645 * APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*)
2646 * @param Periphs This parameter can be a combination of the following values:
2647 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2648 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2649 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2650 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2651 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2652 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2653 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2654 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2655 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2656 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2657 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2658 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2659 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2660 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2661 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2662 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2663 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2664 *
2665 * (*) value not defined in all devices.
2666 * @retval None
2667 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)2668 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
2669 {
2670 CLEAR_BIT(RCC->APB2RSTR, Periphs);
2671 }
2672
2673 /**
2674 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
2675 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2676 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n
2677 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n
2678 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n
2679 * APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2680 * APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2681 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2682 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n
2683 * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n
2684 * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n
2685 * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n
2686 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n
2687 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2688 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n
2689 * APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2690 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2691 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*)
2692 * @param Periphs This parameter can be a combination of the following values:
2693 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2694 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2695 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2696 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2697 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2698 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2699 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2700 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2701 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2702 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2703 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2704 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2705 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2706 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2707 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2708 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2709 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2710 *
2711 * (*) value not defined in all devices.
2712 * @retval None
2713 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)2714 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2715 {
2716 __IO uint32_t tmpreg;
2717 SET_BIT(RCC->APB2LPENR, Periphs);
2718 /* Delay after an RCC peripheral clock enabling */
2719 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2720 (void)tmpreg;
2721 }
2722
2723 /**
2724 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
2725 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2726 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n
2727 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n
2728 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n
2729 * APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2730 * APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2731 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2732 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n
2733 * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n
2734 * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n
2735 * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n
2736 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n
2737 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2738 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n
2739 * APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2740 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2741 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*)
2742 * @param Periphs This parameter can be a combination of the following values:
2743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2744 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2745 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2746 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2747 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2748 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2749 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2750 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2751 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2752 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2753 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2754 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2755 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2756 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2757 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2758 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2759 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2760 *
2761 * (*) value not defined in all devices.
2762 * @retval None
2763 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)2764 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2765 {
2766 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2767 }
2768
2769 /**
2770 * @}
2771 */
2772
2773 /** @defgroup BUS_LL_EF_APB4 APB4
2774 * @{
2775 */
2776
2777 /**
2778 * @brief Enable APB4 peripherals clock.
2779 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n
2780 * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n
2781 * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n
2782 * APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n
2783 * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n
2784 * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n
2785 * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n (*)
2786 * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n (*)
2787 * APB4ENR DAC2EN LL_APB4_GRP1_EnableClock\n (*)
2788 * APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n
2789 * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n
2790 * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n
2791 * APB4ENR SAI4EN LL_APB4_GRP1_EnableClock\n (*)
2792 * APB4ENR DTSEN LL_APB4_GRP1_EnableClock\n (*)
2793 * APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*)
2794 * @param Periphs This parameter can be a combination of the following values:
2795 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2796 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2797 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2798 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2799 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2800 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2801 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2802 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2803 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2804 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2805 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2806 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2807 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2808 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2809 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2810 *
2811 * (*) value not defined in all devices.
2812 * @retval None
2813 */
LL_APB4_GRP1_EnableClock(uint32_t Periphs)2814 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
2815 {
2816 __IO uint32_t tmpreg;
2817 SET_BIT(RCC->APB4ENR, Periphs);
2818 /* Delay after an RCC peripheral clock enabling */
2819 tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
2820 (void)tmpreg;
2821 }
2822
2823 /**
2824 * @brief Check if APB4 peripheral clock is enabled or not
2825 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n
2826 * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n
2827 * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n
2828 * APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n
2829 * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n
2830 * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n
2831 * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n (*)
2832 * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n (*)
2833 * APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock\n (*)
2834 * APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n
2835 * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n
2836 * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n
2837 * APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock\n (*)
2838 * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock\n (*)
2839 * APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*)
2840 * @param Periphs This parameter can be a combination of the following values:
2841 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2842 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2843 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2844 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2845 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2846 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2847 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2848 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2849 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2850 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2851 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2852 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2853 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2854 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2855 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2856 *
2857 * (*) value not defined in all devices.
2858 * @retval uint32_t
2859 */
LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)2860 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
2861 {
2862 return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U);
2863 }
2864
2865 /**
2866 * @brief Disable APB4 peripherals clock.
2867 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n
2868 * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n
2869 * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n
2870 * APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n
2871 * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n
2872 * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n
2873 * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n (*)
2874 * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n (*)
2875 * APB4ENR DAC2EN LL_APB4_GRP1_DisableClock\n (*)
2876 * APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n
2877 * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n
2878 * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n
2879 * APB4ENR SAI4EN LL_APB4_GRP1_DisableClock\n (*)
2880 * APB4ENR DTSEN LL_APB4_GRP1_DisableClock\n (*)
2881 * APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*)
2882 * @param Periphs This parameter can be a combination of the following values:
2883 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2884 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2885 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2886 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2887 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2888 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2889 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2890 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2891 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2892 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2893 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2894 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2895 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2896 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2897 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2898 *
2899 * (*) value not defined in all devices.
2900 * @retval None
2901 */
LL_APB4_GRP1_DisableClock(uint32_t Periphs)2902 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
2903 {
2904 CLEAR_BIT(RCC->APB4ENR, Periphs);
2905 }
2906
2907 /**
2908 * @brief Force APB4 peripherals reset.
2909 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n
2910 * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n
2911 * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n
2912 * APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n
2913 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n
2914 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n
2915 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n (*)
2916 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n (*)
2917 * APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset\n (*)
2918 * APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n
2919 * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n
2920 * APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*)
2921 * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*)
2922 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*)
2923 * @param Periphs This parameter can be a combination of the following values:
2924 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2925 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2926 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2927 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2928 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2929 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2930 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2931 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2932 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2933 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2934 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2935 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2936 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2937 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2938 *
2939 * (*) value not defined in all devices.
2940 * @retval None
2941 */
LL_APB4_GRP1_ForceReset(uint32_t Periphs)2942 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
2943 {
2944 SET_BIT(RCC->APB4RSTR, Periphs);
2945 }
2946
2947 /**
2948 * @brief Release APB4 peripherals reset.
2949 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n
2950 * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n
2951 * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n
2952 * APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n
2953 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n
2954 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n
2955 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n (*)
2956 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n (*)
2957 * APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset\n (*)
2958 * APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n
2959 * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n
2960 * APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset\n
2961 * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset\n (*)
2962 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*)
2963 * @param Periphs This parameter can be a combination of the following values:
2964 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2965 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2966 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2967 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2968 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2969 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2970 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2971 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2972 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2973 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2974 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2975 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2976 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2977 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2978 *
2979 * (*) value not defined in all devices.
2980 * @retval None
2981 */
LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)2982 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
2983 {
2984 CLEAR_BIT(RCC->APB4RSTR, Periphs);
2985 }
2986
2987 /**
2988 * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode.
2989 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n
2990 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n
2991 * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n
2992 * APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n
2993 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n
2994 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n
2995 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2996 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2997 * APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2998 * APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n
2999 * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n
3000 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n
3001 * APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
3002 * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep\n (*)
3003 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*)
3004 * @param Periphs This parameter can be a combination of the following values:
3005 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
3006 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3007 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3008 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3009 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3010 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3011 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
3012 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
3013 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
3014 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
3015 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
3016 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3017 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
3018 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
3019 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
3020 *
3021 * (*) value not defined in all devices.
3022 * @retval None
3023 */
LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)3024 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
3025 {
3026 __IO uint32_t tmpreg;
3027 SET_BIT(RCC->APB4LPENR, Periphs);
3028 /* Delay after an RCC peripheral clock enabling */
3029 tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
3030 (void)tmpreg;
3031 }
3032
3033 /**
3034 * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode.
3035 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n
3036 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n
3037 * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n
3038 * APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n
3039 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n
3040 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n
3041 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3042 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3043 * APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3044 * APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n
3045 * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n
3046 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n
3047 * APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3048 * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3049 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*)
3050 * @param Periphs This parameter can be a combination of the following values:
3051 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
3052 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3053 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3054 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3055 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3056 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3057 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
3058 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
3059 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
3060 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
3061 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
3062 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3063 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
3064 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
3065 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
3066 *
3067 * (*) value not defined in all devices.
3068 * @retval None
3069 */
LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)3070 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
3071 {
3072 CLEAR_BIT(RCC->APB4LPENR, Periphs);
3073 }
3074
3075 /**
3076 * @}
3077 */
3078
3079 /** @defgroup BUS_LL_EF_CLKAM CLKAM
3080 * @{
3081 */
3082
3083 /**
3084 * @brief Enable peripherals clock for CLKAM Mode.
3085 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Enable\n
3086 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable\n
3087 * D3AMR / SRDAMR SPI6 LL_CLKAM_Enable\n
3088 * D3AMR / SRDAMR I2C4 LL_CLKAM_Enable\n
3089 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable\n
3090 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable\n
3091 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable\n (*)
3092 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable\n (*)
3093 * D3AMR / SRDAMR DAC2 LL_CLKAM_Enable\n (*)
3094 * D3AMR / SRDAMR COMP12 LL_CLKAM_Enable\n
3095 * D3AMR / SRDAMR VREF LL_CLKAM_Enable\n
3096 * D3AMR / SRDAMR RTC LL_CLKAM_Enable\n
3097 * D3AMR / SRDAMR CRC LL_CLKAM_Enable\n
3098 * D3AMR / SRDAMR SAI4 LL_CLKAM_Enable\n (*)
3099 * D3AMR / SRDAMR ADC3 LL_CLKAM_Enable\n (*)
3100 * D3AMR / SRDAMR DTS LL_CLKAM_Enable\n (*)
3101 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable\n (*)
3102 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable\n
3103 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable
3104 * @param Periphs This parameter can be a combination of the following values:
3105 * @arg @ref LL_CLKAM_PERIPH_BDMA
3106 * @arg @ref LL_CLKAM_PERIPH_GPIO (*)
3107 * @arg @ref LL_CLKAM_PERIPH_LPUART1
3108 * @arg @ref LL_CLKAM_PERIPH_SPI6
3109 * @arg @ref LL_CLKAM_PERIPH_I2C4
3110 * @arg @ref LL_CLKAM_PERIPH_LPTIM2
3111 * @arg @ref LL_CLKAM_PERIPH_LPTIM3
3112 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
3113 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
3114 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*)
3115 * @arg @ref LL_CLKAM_PERIPH_COMP12
3116 * @arg @ref LL_CLKAM_PERIPH_VREF
3117 * @arg @ref LL_CLKAM_PERIPH_RTC
3118 * @arg @ref LL_CLKAM_PERIPH_CRC (*)
3119 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
3120 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
3121 * @arg @ref LL_CLKAM_PERIPH_DTS (*)
3122 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
3123 * @arg @ref LL_CLKAM_PERIPH_BKPRAM
3124 * @arg @ref LL_CLKAM_PERIPH_SRAM4
3125 *
3126 * (*) value not defined in all devices.
3127 * @retval None
3128 */
LL_CLKAM_Enable(uint32_t Periphs)3129 __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
3130 {
3131 __IO uint32_t tmpreg;
3132
3133 #if defined(RCC_D3AMR_BDMAAMEN)
3134 SET_BIT(RCC->D3AMR, Periphs);
3135 /* Delay after an RCC peripheral clock enabling */
3136 tmpreg = READ_BIT(RCC->D3AMR, Periphs);
3137 #else
3138 SET_BIT(RCC->SRDAMR, Periphs);
3139 /* Delay after an RCC peripheral clock enabling */
3140 tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
3141 #endif /* RCC_D3AMR_BDMAAMEN */
3142 (void)tmpreg;
3143 }
3144
3145 /**
3146 * @brief Disable peripherals clock for CLKAM Mode.
3147 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Disable\n
3148 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable\n
3149 * D3AMR / SRDAMR SPI6 LL_CLKAM_Disable\n
3150 * D3AMR / SRDAMR I2C4 LL_CLKAM_Disable\n
3151 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable\n
3152 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable\n
3153 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable\n (*)
3154 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable\n (*)
3155 * D3AMR / SRDAMR DAC2 LL_CLKAM_Disable\n (*)
3156 * D3AMR / SRDAMR COMP12 LL_CLKAM_Disable\n
3157 * D3AMR / SRDAMR VREF LL_CLKAM_Disable\n
3158 * D3AMR / SRDAMR RTC LL_CLKAM_Disable\n
3159 * D3AMR / SRDAMR CRC LL_CLKAM_Disable\n
3160 * D3AMR / SRDAMR SAI4 LL_CLKAM_Disable\n (*)
3161 * D3AMR / SRDAMR ADC3 LL_CLKAM_Disable\n (*)
3162 * D3AMR / SRDAMR DTS LL_CLKAM_Disable\n (*)
3163 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable\n (*)
3164 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable\n
3165 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable
3166 * @param Periphs This parameter can be a combination of the following values:
3167 * @arg @ref LL_CLKAM_PERIPH_BDMA
3168 * @arg @ref LL_CLKAM_PERIPH_GPIO (*)
3169 * @arg @ref LL_CLKAM_PERIPH_LPUART1
3170 * @arg @ref LL_CLKAM_PERIPH_SPI6
3171 * @arg @ref LL_CLKAM_PERIPH_I2C4
3172 * @arg @ref LL_CLKAM_PERIPH_LPTIM2
3173 * @arg @ref LL_CLKAM_PERIPH_LPTIM3
3174 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
3175 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
3176 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*)
3177 * @arg @ref LL_CLKAM_PERIPH_COMP12
3178 * @arg @ref LL_CLKAM_PERIPH_VREF
3179 * @arg @ref LL_CLKAM_PERIPH_RTC
3180 * @arg @ref LL_CLKAM_PERIPH_CRC (*)
3181 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
3182 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
3183 * @arg @ref LL_CLKAM_PERIPH_DTS (*)
3184 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
3185 * @arg @ref LL_CLKAM_PERIPH_BKPRAM
3186 * @arg @ref LL_CLKAM_PERIPH_SRAM4
3187 *
3188 * (*) value not defined in all devices.
3189 * @retval None
3190 */
LL_CLKAM_Disable(uint32_t Periphs)3191 __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
3192 {
3193 #if defined(RCC_D3AMR_BDMAAMEN)
3194 CLEAR_BIT(RCC->D3AMR, Periphs);
3195 #else
3196 CLEAR_BIT(RCC->SRDAMR, Periphs);
3197 #endif /* RCC_D3AMR_BDMAAMEN */
3198 }
3199
3200 /**
3201 * @}
3202 */
3203
3204 /** @defgroup BUS_LL_EF_CKGA CKGA
3205 * @{
3206 */
3207
3208 #if defined(RCC_CKGAENR_AXICKG)
3209
3210
3211 /**
3212 * @brief Enable clock gating for AXI bus peripherals.
3213 * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n
3214 * CKGAENR AHBCKG LL_CKGA_Enable\n
3215 * CKGAENR CPUCKG LL_CKGA_Enable\n
3216 * CKGAENR SDMMCCKG LL_CKGA_Enable\n
3217 * CKGAENR MDMACKG LL_CKGA_Enable\n
3218 * CKGAENR DMA2DCKG LL_CKGA_Enable\n
3219 * CKGAENR LTDCCKG LL_CKGA_Enable\n
3220 * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n
3221 * CKGAENR AHB12CKG LL_CKGA_Enable\n
3222 * CKGAENR AHB34CKG LL_CKGA_Enable\n
3223 * CKGAENR FLIFTCKG LL_CKGA_Enable\n
3224 * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n
3225 * CKGAENR FMCCKG LL_CKGA_Enable\n
3226 * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n
3227 * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n
3228 * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n
3229 * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n
3230 * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n
3231 * CKGAENR ECCRAMCKG LL_CKGA_Enable\n
3232 * CKGAENR EXTICKG LL_CKGA_Enable\n
3233 * CKGAENR JTAGCKG LL_CKGA_Enable
3234 * @param Periphs This parameter can be a combination of the following values:
3235 * @arg @ref LL_CKGA_PERIPH_AXI
3236 * @arg @ref LL_CKGA_PERIPH_AHB
3237 * @arg @ref LL_CKGA_PERIPH_CPU
3238 * @arg @ref LL_CKGA_PERIPH_SDMMC
3239 * @arg @ref LL_CKGA_PERIPH_MDMA
3240 * @arg @ref LL_CKGA_PERIPH_DMA2D
3241 * @arg @ref LL_CKGA_PERIPH_LTDC
3242 * @arg @ref LL_CKGA_PERIPH_GFXMMUM
3243 * @arg @ref LL_CKGA_PERIPH_AHB12
3244 * @arg @ref LL_CKGA_PERIPH_AHB34
3245 * @arg @ref LL_CKGA_PERIPH_FLIFT
3246 * @arg @ref LL_CKGA_PERIPH_OCTOSPI2
3247 * @arg @ref LL_CKGA_PERIPH_FMC
3248 * @arg @ref LL_CKGA_PERIPH_OCTOSPI1
3249 * @arg @ref LL_CKGA_PERIPH_AXIRAM1
3250 * @arg @ref LL_CKGA_PERIPH_AXIRAM2
3251 * @arg @ref LL_CKGA_PERIPH_AXIRAM3
3252 * @arg @ref LL_CKGA_PERIPH_GFXMMUS
3253 * @arg @ref LL_CKGA_PERIPH_ECCRAM
3254 * @arg @ref LL_CKGA_PERIPH_EXTI
3255 * @arg @ref LL_CKGA_PERIPH_JTAG
3256 * @retval None
3257 */
LL_CKGA_Enable(uint32_t Periphs)3258 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
3259 {
3260 __IO uint32_t tmpreg;
3261 SET_BIT(RCC->CKGAENR, Periphs);
3262 /* Delay after an RCC peripheral clock enabling */
3263 tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
3264 (void)tmpreg;
3265 }
3266
3267 #endif /* RCC_CKGAENR_AXICKG */
3268
3269 #if defined(RCC_CKGAENR_AXICKG)
3270
3271 /**
3272 * @brief Disable clock gating for AXI bus peripherals.
3273 * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n
3274 * CKGAENR AHBCKG LL_CKGA_Enable\n
3275 * CKGAENR CPUCKG LL_CKGA_Enable\n
3276 * CKGAENR SDMMCCKG LL_CKGA_Enable\n
3277 * CKGAENR MDMACKG LL_CKGA_Enable\n
3278 * CKGAENR DMA2DCKG LL_CKGA_Enable\n
3279 * CKGAENR LTDCCKG LL_CKGA_Enable\n
3280 * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n
3281 * CKGAENR AHB12CKG LL_CKGA_Enable\n
3282 * CKGAENR AHB34CKG LL_CKGA_Enable\n
3283 * CKGAENR FLIFTCKG LL_CKGA_Enable\n
3284 * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n
3285 * CKGAENR FMCCKG LL_CKGA_Enable\n
3286 * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n
3287 * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n
3288 * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n
3289 * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n
3290 * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n
3291 * CKGAENR ECCRAMCKG LL_CKGA_Enable\n
3292 * CKGAENR EXTICKG LL_CKGA_Enable\n
3293 * CKGAENR JTAGCKG LL_CKGA_Enable
3294 * @param Periphs This parameter can be a combination of the following values:
3295 * @arg @ref LL_CKGA_PERIPH_AXI
3296 * @arg @ref LL_CKGA_PERIPH_AHB
3297 * @arg @ref LL_CKGA_PERIPH_CPU
3298 * @arg @ref LL_CKGA_PERIPH_SDMMC
3299 * @arg @ref LL_CKGA_PERIPH_MDMA
3300 * @arg @ref LL_CKGA_PERIPH_DMA2D
3301 * @arg @ref LL_CKGA_PERIPH_LTDC
3302 * @arg @ref LL_CKGA_PERIPH_GFXMMUM
3303 * @arg @ref LL_CKGA_PERIPH_AHB12
3304 * @arg @ref LL_CKGA_PERIPH_AHB34
3305 * @arg @ref LL_CKGA_PERIPH_FLIFT
3306 * @arg @ref LL_CKGA_PERIPH_OCTOSPI2
3307 * @arg @ref LL_CKGA_PERIPH_FMC
3308 * @arg @ref LL_CKGA_PERIPH_OCTOSPI1
3309 * @arg @ref LL_CKGA_PERIPH_AXIRAM1
3310 * @arg @ref LL_CKGA_PERIPH_AXIRAM2
3311 * @arg @ref LL_CKGA_PERIPH_AXIRAM3
3312 * @arg @ref LL_CKGA_PERIPH_GFXMMUS
3313 * @arg @ref LL_CKGA_PERIPH_ECCRAM
3314 * @arg @ref LL_CKGA_PERIPH_EXTI
3315 * @arg @ref LL_CKGA_PERIPH_JTAG
3316 * @retval None
3317 */
LL_CKGA_Disable(uint32_t Periphs)3318 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
3319 {
3320 CLEAR_BIT(RCC->CKGAENR, Periphs);
3321 }
3322
3323 #endif /* RCC_CKGAENR_AXICKG */
3324
3325 /**
3326 * @}
3327 */
3328
3329 #if defined(DUAL_CORE)
3330 /** @addtogroup BUS_LL_EF_AHB3 AHB3
3331 * @{
3332 */
3333
3334 /**
3335 * @brief Enable C1 AHB3 peripherals clock.
3336 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_EnableClock\n
3337 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_EnableClock\n
3338 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_EnableClock\n
3339 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_EnableClock\n
3340 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_EnableClock\n (*)
3341 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3342 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3343 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*)
3344 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3345 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3346 * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_EnableClock\n (*)
3347 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock
3348 * @param Periphs This parameter can be a combination of the following values:
3349 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3350 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3351 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3352 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3353 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3354 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3355 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3356 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3357 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3358 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3359 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3360 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3361 *
3362 * (*) value not defined in all devices.
3363 * @retval None
3364 */
LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)3365 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
3366 {
3367 __IO uint32_t tmpreg;
3368 SET_BIT(RCC_C1->AHB3ENR, Periphs);
3369 /* Delay after an RCC peripheral clock enabling */
3370 tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);
3371 (void)tmpreg;
3372 }
3373
3374 /**
3375 * @brief Check if C1 AHB3 peripheral clock is enabled or not
3376 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3377 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3378 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3379 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3380 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3381 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3382 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3383 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3384 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3385 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3386 * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3387 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock
3388 * @param Periphs This parameter can be a combination of the following values:
3389 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3390 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3391 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3392 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3393 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3394 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3395 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3396 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3397 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3398 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3399 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3400 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3401 *
3402 * (*) value not defined in all devices.
3403 * @retval uint32_t
3404 */
LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)3405 __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
3406 {
3407 return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U);
3408 }
3409
3410 /**
3411 * @brief Disable C1 AHB3 peripherals clock.
3412 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_DisableClock\n
3413 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_DisableClock\n
3414 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_DisableClock\n
3415 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_DisableClock\n
3416 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_DisableClock\n (*)
3417 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3418 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3419 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*)
3420 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3421 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3422 * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_DisableClock\n (*)
3423 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock
3424 * @param Periphs This parameter can be a combination of the following values:
3425 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3426 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3427 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
3428 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3429 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3430 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3431 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3432 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3433 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3434 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3435 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3436 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3437 *
3438 * (*) value not defined in all devices.
3439 * @retval None
3440 */
LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)3441 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)
3442 {
3443 CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);
3444 }
3445
3446 /**
3447 * @brief Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
3448 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3449 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3450 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3451 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3452 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3453 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3454 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3455 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3456 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3457 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3458 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3459 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3460 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3461 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3462 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3463 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3464 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep
3465 * @param Periphs This parameter can be a combination of the following values:
3466 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3467 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
3468 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3469 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3470 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3471 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3472 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3473 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3474 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3475 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3476 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3477 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
3478 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
3479 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
3480 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
3481 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
3482 *
3483 * (*) value not defined in all devices.
3484 * @retval None
3485 */
LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)3486 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
3487 {
3488 __IO uint32_t tmpreg;
3489 SET_BIT(RCC_C1->AHB3LPENR, Periphs);
3490 /* Delay after an RCC peripheral clock enabling */
3491 tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);
3492 (void)tmpreg;
3493 }
3494
3495 /**
3496 * @brief Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
3497 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3498 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3499 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3500 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3501 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3502 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3503 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3504 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3505 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3506 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3507 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3508 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3509 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3510 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3511 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3512 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3513 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep
3514 * @param Periphs This parameter can be a combination of the following values:
3515 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3516 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
3517 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3518 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3519 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3520 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3521 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3522 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3523 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3524 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3525 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3526 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
3527 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
3528 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
3529 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
3530 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
3531 *
3532 * (*) value not defined in all devices.
3533 * @retval None
3534 */
LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)3535 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
3536 {
3537 CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);
3538 }
3539
3540 /**
3541 * @}
3542 */
3543
3544 /** @addtogroup BUS_LL_EF_AHB1 AHB1
3545 * @{
3546 */
3547
3548 /**
3549 * @brief Enable C1 AHB1 peripherals clock.
3550 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_EnableClock\n
3551 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_EnableClock\n
3552 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_EnableClock\n
3553 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3554 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3555 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3556 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3557 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3558 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n
3559 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock\n
3560 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3561 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock (*)
3562 * @param Periphs This parameter can be a combination of the following values:
3563 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3564 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3565 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3566 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3567 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3568 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3569 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3570 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3571 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3572 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3573 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3574 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3575 *
3576 * (*) value not defined in all devices.
3577 * @retval None
3578 */
LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)3579 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
3580 {
3581 __IO uint32_t tmpreg;
3582 SET_BIT(RCC_C1->AHB1ENR, Periphs);
3583 /* Delay after an RCC peripheral clock enabling */
3584 tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);
3585 (void)tmpreg;
3586 }
3587
3588 /**
3589 * @brief Check if C1 AHB1 peripheral clock is enabled or not
3590 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3591 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3592 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3593 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3594 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3595 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3596 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3597 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3598 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n
3599 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock\n
3600 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3601 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock (*)
3602 * @param Periphs This parameter can be a combination of the following values:
3603 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3604 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3605 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3606 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3607 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3608 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3609 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3610 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3611 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3612 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3613 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3614 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3615 *
3616 * (*) value not defined in all devices.
3617 * @retval uint32_t
3618 */
LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)3619 __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
3620 {
3621 return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U);
3622 }
3623
3624 /**
3625 * @brief Disable C1 AHB1 peripherals clock.
3626 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_DisableClock\n
3627 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_DisableClock\n
3628 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_DisableClock\n
3629 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3630 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3631 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3632 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3633 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3634 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n
3635 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock\n
3636 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3637 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock (*)
3638 * @param Periphs This parameter can be a combination of the following values:
3639 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3640 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3641 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3642 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3643 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3644 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3645 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3646 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3647 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3648 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3649 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3650 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3651 *
3652 * (*) value not defined in all devices.
3653 * @retval None
3654 */
LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)3655 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)
3656 {
3657 CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);
3658 }
3659
3660 /**
3661 * @brief Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
3662 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3663 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3664 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3665 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3666 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3667 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3668 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3669 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3670 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3671 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3672 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3673 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep (*)
3674 * @param Periphs This parameter can be a combination of the following values:
3675 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3676 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3677 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3678 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3679 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3680 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3681 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3682 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3683 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3684 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3685 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3686 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3687 *
3688 * (*) value not defined in all devices.
3689 * @retval None
3690 */
LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)3691 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
3692 {
3693 __IO uint32_t tmpreg;
3694 SET_BIT(RCC_C1->AHB1LPENR, Periphs);
3695 /* Delay after an RCC peripheral clock enabling */
3696 tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);
3697 (void)tmpreg;
3698 }
3699
3700 /**
3701 * @brief Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
3702 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3703 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3704 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3705 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3706 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3707 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3708 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3709 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3710 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3711 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3712 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3713 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep (*)
3714 * @param Periphs This parameter can be a combination of the following values:
3715 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3716 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3717 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3718 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3719 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3720 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3721 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3722 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3723 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3724 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3725 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3726 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3727 *
3728 * (*) value not defined in all devices.
3729 * @retval None
3730 */
LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)3731 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
3732 {
3733 CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);
3734 }
3735
3736 /**
3737 * @}
3738 */
3739
3740 /** @addtogroup BUS_LL_EF_AHB2 AHB2
3741 * @{
3742 */
3743
3744 /**
3745 * @brief Enable C1 AHB2 peripherals clock.
3746 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_EnableClock\n
3747 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3748 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3749 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3750 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_EnableClock\n
3751 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_EnableClock\n
3752 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_EnableClock\n (*)
3753 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_EnableClock\n
3754 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_EnableClock\n
3755 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_EnableClock (*)
3756 * @param Periphs This parameter can be a combination of the following values:
3757 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3758 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3759 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3760 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3761 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3762 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3763 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3764 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3765 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3766 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3767 *
3768 * (*) value not defined in all devices.
3769 * @retval None
3770 */
LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)3771 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
3772 {
3773 __IO uint32_t tmpreg;
3774 SET_BIT(RCC_C1->AHB2ENR, Periphs);
3775 /* Delay after an RCC peripheral clock enabling */
3776 tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);
3777 (void)tmpreg;
3778 }
3779
3780 /**
3781 * @brief Check if C1 AHB2 peripheral clock is enabled or not
3782 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_IsEnabledClock\n
3783 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3784 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3785 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3786 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_IsEnabledClock\n
3787 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3788 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3789 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3790 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3791 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_IsEnabledClock (*)
3792 * @param Periphs This parameter can be a combination of the following values:
3793 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3794 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3795 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3796 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3797 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3798 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3799 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3800 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3801 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3802 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3803 *
3804 * (*) value not defined in all devices.
3805 * @retval uint32_t
3806 */
LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)3807 __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
3808 {
3809 return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U);
3810 }
3811
3812 /**
3813 * @brief Disable C1 AHB2 peripherals clock.
3814 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_DisableClock\n
3815 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3816 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3817 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3818 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_DisableClock\n
3819 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_DisableClock\n
3820 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_DisableClock\n (*)
3821 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_DisableClock\n
3822 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_DisableClock\n
3823 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_DisableClock (*)
3824 * @param Periphs This parameter can be a combination of the following values:
3825 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3826 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3827 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3828 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3829 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3830 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3831 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3832 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3833 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3834 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3835 *
3836 * (*) value not defined in all devices.
3837 * @retval None
3838 */
LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)3839 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)
3840 {
3841 CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);
3842 }
3843
3844 /**
3845 * @brief Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
3846 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3847 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3848 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3849 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3850 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3851 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3852 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3853 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3854 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*)
3855 * @param Periphs This parameter can be a combination of the following values:
3856 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3857 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3858 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3859 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3860 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3861 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3862 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3863 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3864 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3865 *
3866 * (*) value not defined in all devices.
3867 * @retval None
3868 */
LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)3869 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
3870 {
3871 __IO uint32_t tmpreg;
3872 SET_BIT(RCC_C1->AHB2LPENR, Periphs);
3873 /* Delay after an RCC peripheral clock enabling */
3874 tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);
3875 (void)tmpreg;
3876 }
3877
3878 /**
3879 * @brief Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
3880 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3881 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3882 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3883 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3884 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3885 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3886 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3887 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3888 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_DisableClockSleep
3889 * @param Periphs This parameter can be a combination of the following values:
3890 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3891 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3892 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3893 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3894 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3895 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3896 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3897 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3898 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3899 *
3900 * (*) value not defined in all devices.
3901 * @retval None
3902 */
LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)3903 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
3904 {
3905 CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);
3906 }
3907
3908 /**
3909 * @}
3910 */
3911
3912 /** @addtogroup BUS_LL_EF_AHB4 AHB4
3913 * @{
3914 */
3915
3916 /**
3917 * @brief Enable C1 AHB4 peripherals clock.
3918 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_EnableClock\n
3919 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_EnableClock\n
3920 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_EnableClock\n
3921 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_EnableClock\n
3922 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_EnableClock\n
3923 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_EnableClock\n
3924 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_EnableClock\n
3925 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_EnableClock\n
3926 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_EnableClock\n
3927 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_EnableClock\n
3928 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_EnableClock\n
3929 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_EnableClock\n (*)
3930 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_EnableClock\n
3931 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_EnableClock\n (*)
3932 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_EnableClock\n (*)
3933 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_EnableClock\n
3934 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_EnableClock
3935 * @param Periphs This parameter can be a combination of the following values:
3936 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3937 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3938 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3939 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3940 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3941 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3942 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3943 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3944 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
3945 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3946 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3947 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3948 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3949 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3950 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
3951 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3952 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3953 *
3954 * (*) value not defined in all devices.
3955 * @retval None
3956 */
LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)3957 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
3958 {
3959 __IO uint32_t tmpreg;
3960 SET_BIT(RCC_C1->AHB4ENR, Periphs);
3961 /* Delay after an RCC peripheral clock enabling */
3962 tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);
3963 (void)tmpreg;
3964 }
3965
3966 /**
3967 * @brief Check if C1 AHB4 peripheral clock is enabled or not
3968 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3969 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3970 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3971 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3972 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3973 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3974 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3975 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3976 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3977 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3978 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3979 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3980 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3981 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3982 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3983 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3984 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_IsEnabledClock
3985 * @param Periphs This parameter can be a combination of the following values:
3986 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3987 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3988 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3989 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3990 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3991 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3992 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3993 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3994 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
3995 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3996 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3997 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3998 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3999 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
4000 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
4001 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
4002 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
4003 *
4004 * (*) value not defined in all devices.
4005 * @retval uint32_t
4006 */
LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)4007 __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
4008 {
4009 return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs) ? 1U : 0U);
4010 }
4011
4012 /**
4013 * @brief Disable C1 AHB4 peripherals clock.
4014 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_DisableClock\n
4015 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_DisableClock\n
4016 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_DisableClock\n
4017 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_DisableClock\n
4018 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_DisableClock\n
4019 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_DisableClock\n
4020 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_DisableClock\n
4021 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_DisableClock\n
4022 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_DisableClock\n
4023 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_DisableClock\n
4024 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_DisableClock\n
4025 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_DisableClock\n (*)
4026 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_DisableClock\n
4027 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_DisableClock\n (*)
4028 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_DisableClock\n (*)
4029 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_DisableClock\n
4030 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_DisableClock
4031 * @param Periphs This parameter can be a combination of the following values:
4032 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
4033 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
4034 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
4035 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
4036 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
4037 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
4038 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
4039 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
4040 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
4041 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
4042 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
4043 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
4044 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
4045 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
4046 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
4047 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
4048 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
4049 *
4050 * (*) value not defined in all devices.
4051 * @retval None
4052 */
LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)4053 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)
4054 {
4055 CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);
4056 }
4057
4058 /**
4059 * @brief Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
4060 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4061 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4062 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4063 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4064 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4065 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4066 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4067 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4068 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4069 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4070 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4071 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
4072 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4073 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
4074 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
4075 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_EnableClockSleep
4076 * @param Periphs This parameter can be a combination of the following values:
4077 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
4078 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
4079 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
4080 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
4081 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
4082 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
4083 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
4084 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
4085 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
4086 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
4087 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
4088 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
4089 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
4090 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
4091 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
4092 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
4093 * @retval None
4094 */
LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)4095 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
4096 {
4097 __IO uint32_t tmpreg;
4098 SET_BIT(RCC_C1->AHB4LPENR, Periphs);
4099 /* Delay after an RCC peripheral clock enabling */
4100 tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);
4101 (void)tmpreg;
4102 }
4103
4104 /**
4105 * @brief Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
4106 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4107 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4108 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4109 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4110 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4111 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4112 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4113 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4114 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4115 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4116 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4117 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
4118 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4119 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
4120 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4121 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_DisableClockSleep
4122 * @param Periphs This parameter can be a combination of the following values:
4123 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
4124 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
4125 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
4126 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
4127 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
4128 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
4129 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
4130 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
4131 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
4132 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
4133 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
4134 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
4135 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
4136 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
4137 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
4138 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
4139 * @retval None
4140 */
LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)4141 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
4142 {
4143 CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);
4144 }
4145
4146 /**
4147 * @}
4148 */
4149
4150 /** @addtogroup BUS_LL_EF_APB3 APB3
4151 * @{
4152 */
4153
4154 /**
4155 * @brief Enable C1 APB3 peripherals clock.
4156 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_EnableClock\n (*)
4157 * APB3ENR DSIEN LL_C1_APB3_GRP1_EnableClock\n (*)
4158 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock
4159 * @param Periphs This parameter can be a combination of the following values:
4160 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4161 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4162 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4163 *
4164 * (*) value not defined in all devices.
4165 * @retval None
4166 */
LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)4167 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
4168 {
4169 __IO uint32_t tmpreg;
4170 SET_BIT(RCC_C1->APB3ENR, Periphs);
4171 /* Delay after an RCC peripheral clock enabling */
4172 tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);
4173 (void)tmpreg;
4174 }
4175
4176 /**
4177 * @brief Check if C1 APB3 peripheral clock is enabled or not
4178 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_IsEnabledClock\n (*)
4179 * APB3ENR DSIEN LL_C1_APB3_GRP1_IsEnabledClock\n (*)
4180 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock
4181 * @param Periphs This parameter can be a combination of the following values:
4182 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4183 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4184 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4185 *
4186 * (*) value not defined in all devices.
4187 * @retval uint32_t
4188 */
LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)4189 __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
4190 {
4191 return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs) ? 1U : 0U);
4192 }
4193
4194 /**
4195 * @brief Disable C1 APB3 peripherals clock.
4196 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_DisableClock\n (*)
4197 * APB3ENR DSIEN LL_C1_APB3_GRP1_DisableClock\n (*)
4198 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock
4199 * @param Periphs This parameter can be a combination of the following values:
4200 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4201
4202 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4203 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4204 *
4205 * (*) value not defined in all devices.
4206 * @retval None
4207 */
LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)4208 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)
4209 {
4210 CLEAR_BIT(RCC_C1->APB3ENR, Periphs);
4211 }
4212
4213 /**
4214 * @brief Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.
4215 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*)
4216 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*)
4217 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep
4218 * @param Periphs This parameter can be a combination of the following values:
4219 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4220 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4221 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4222 *
4223 * (*) value not defined in all devices.
4224 * @retval None
4225 */
LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)4226 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
4227 {
4228 __IO uint32_t tmpreg;
4229 SET_BIT(RCC_C1->APB3LPENR, Periphs);
4230 /* Delay after an RCC peripheral clock enabling */
4231 tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);
4232 (void)tmpreg;
4233 }
4234
4235 /**
4236 * @brief Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.
4237 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*)
4238 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*)
4239 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep
4240 * @param Periphs This parameter can be a combination of the following values:
4241 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4242 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4243 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4244 *
4245 * (*) value not defined in all devices.
4246 * @retval None
4247 */
LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)4248 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
4249 {
4250 CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);
4251 }
4252
4253 /**
4254 * @}
4255 */
4256
4257 /** @addtogroup BUS_LL_EF_APB1 APB1
4258 * @{
4259 */
4260
4261 /**
4262 * @brief Enable C1 APB1 peripherals clock.
4263 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_EnableClock\n
4264 * APB1LENR TIM3EN LL_C1_APB1_GRP1_EnableClock\n
4265 * APB1LENR TIM4EN LL_C1_APB1_GRP1_EnableClock\n
4266 * APB1LENR TIM5EN LL_C1_APB1_GRP1_EnableClock\n
4267 * APB1LENR TIM6EN LL_C1_APB1_GRP1_EnableClock\n
4268 * APB1LENR TIM7EN LL_C1_APB1_GRP1_EnableClock\n
4269 * APB1LENR TIM12EN LL_C1_APB1_GRP1_EnableClock\n
4270 * APB1LENR TIM13EN LL_C1_APB1_GRP1_EnableClock\n
4271 * APB1LENR TIM14EN LL_C1_APB1_GRP1_EnableClock\n
4272 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_EnableClock\n
4273 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_EnableClock\n (*)
4274 * APB1LENR SPI2EN LL_C1_APB1_GRP1_EnableClock\n
4275 * APB1LENR SPI3EN LL_C1_APB1_GRP1_EnableClock\n
4276 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_EnableClock\n
4277 * APB1LENR USART2EN LL_C1_APB1_GRP1_EnableClock\n
4278 * APB1LENR USART3EN LL_C1_APB1_GRP1_EnableClock\n
4279 * APB1LENR UART4EN LL_C1_APB1_GRP1_EnableClock\n
4280 * APB1LENR UART5EN LL_C1_APB1_GRP1_EnableClock\n
4281 * APB1LENR I2C1EN LL_C1_APB1_GRP1_EnableClock\n
4282 * APB1LENR I2C2EN LL_C1_APB1_GRP1_EnableClock\n
4283 * APB1LENR I2C3EN LL_C1_APB1_GRP1_EnableClock\n
4284 * APB1LENR CECEN LL_C1_APB1_GRP1_EnableClock\n
4285 * APB1LENR DAC12EN LL_C1_APB1_GRP1_EnableClock\n
4286 * APB1LENR UART7EN LL_C1_APB1_GRP1_EnableClock\n
4287 * APB1LENR UART8EN LL_C1_APB1_GRP1_EnableClock
4288 * @param Periphs This parameter can be a combination of the following values:
4289 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4290 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4291 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4292 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4293 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4294 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4295 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4296 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4297 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4298 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4299 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4300 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4301 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4302 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4303 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4304 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4305 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4306 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4307 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4308 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4309 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4310 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4311 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4312 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4313 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4314 *
4315 * (*) value not defined in all devices.
4316 * @retval None
4317 */
LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)4318 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
4319 {
4320 __IO uint32_t tmpreg;
4321 SET_BIT(RCC_C1->APB1LENR, Periphs);
4322 /* Delay after an RCC peripheral clock enabling */
4323 tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);
4324 (void)tmpreg;
4325 }
4326
4327 /**
4328 * @brief Check if C1 APB1 peripheral clock is enabled or not
4329 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4330 * APB1LENR TIM3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4331 * APB1LENR TIM4EN LL_C1_APB1_GRP1_IsEnabledClock\n
4332 * APB1LENR TIM5EN LL_C1_APB1_GRP1_IsEnabledClock\n
4333 * APB1LENR TIM6EN LL_C1_APB1_GRP1_IsEnabledClock\n
4334 * APB1LENR TIM7EN LL_C1_APB1_GRP1_IsEnabledClock\n
4335 * APB1LENR TIM12EN LL_C1_APB1_GRP1_IsEnabledClock\n
4336 * APB1LENR TIM13EN LL_C1_APB1_GRP1_IsEnabledClock\n
4337 * APB1LENR TIM14EN LL_C1_APB1_GRP1_IsEnabledClock\n
4338 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_IsEnabledClock\n
4339 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_IsEnabledClock\n (*)
4340 * APB1LENR SPI2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4341 * APB1LENR SPI3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4342 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_IsEnabledClock\n
4343 * APB1LENR USART2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4344 * APB1LENR USART3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4345 * APB1LENR UART4EN LL_C1_APB1_GRP1_IsEnabledClock\n
4346 * APB1LENR UART5EN LL_C1_APB1_GRP1_IsEnabledClock\n
4347 * APB1LENR I2C1EN LL_C1_APB1_GRP1_IsEnabledClock\n
4348 * APB1LENR I2C2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4349 * APB1LENR I2C3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4350 * APB1LENR CECEN LL_C1_APB1_GRP1_IsEnabledClock\n
4351 * APB1LENR DAC12EN LL_C1_APB1_GRP1_IsEnabledClock\n
4352 * APB1LENR UART7EN LL_C1_APB1_GRP1_IsEnabledClock\n
4353 * APB1LENR UART8EN LL_C1_APB1_GRP1_IsEnabledClock
4354 * @param Periphs This parameter can be a combination of the following values:
4355 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4356 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4357 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4358 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4359 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4360 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4361 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4362 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4363 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4364 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4365 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4366 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4367 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4368 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4369 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4370 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4371 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4372 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4373 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4374 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4375 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4376 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4377 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4378 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4379 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4380 *
4381 * (*) value not defined in all devices.
4382 * @retval uint32_t
4383 */
LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)4384 __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
4385 {
4386 return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs) ? 1U : 0U);
4387 }
4388
4389 /**
4390 * @brief Disable C1 APB1 peripherals clock.
4391 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_DisableClock\n
4392 * APB1LENR TIM3EN LL_C1_APB1_GRP1_DisableClock\n
4393 * APB1LENR TIM4EN LL_C1_APB1_GRP1_DisableClock\n
4394 * APB1LENR TIM5EN LL_C1_APB1_GRP1_DisableClock\n
4395 * APB1LENR TIM6EN LL_C1_APB1_GRP1_DisableClock\n
4396 * APB1LENR TIM7EN LL_C1_APB1_GRP1_DisableClock\n
4397 * APB1LENR TIM12EN LL_C1_APB1_GRP1_DisableClock\n
4398 * APB1LENR TIM13EN LL_C1_APB1_GRP1_DisableClock\n
4399 * APB1LENR TIM14EN LL_C1_APB1_GRP1_DisableClock\n
4400 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_DisableClock\n
4401 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_DisableClock\n (*)
4402 * APB1LENR SPI2EN LL_C1_APB1_GRP1_DisableClock\n
4403 * APB1LENR SPI3EN LL_C1_APB1_GRP1_DisableClock\n
4404 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_DisableClock\n
4405 * APB1LENR USART2EN LL_C1_APB1_GRP1_DisableClock\n
4406 * APB1LENR USART3EN LL_C1_APB1_GRP1_DisableClock\n
4407 * APB1LENR UART4EN LL_C1_APB1_GRP1_DisableClock\n
4408 * APB1LENR UART5EN LL_C1_APB1_GRP1_DisableClock\n
4409 * APB1LENR I2C1EN LL_C1_APB1_GRP1_DisableClock\n
4410 * APB1LENR I2C2EN LL_C1_APB1_GRP1_DisableClock\n
4411 * APB1LENR I2C3EN LL_C1_APB1_GRP1_DisableClock\n
4412 * APB1LENR CECEN LL_C1_APB1_GRP1_DisableClock\n
4413 * APB1LENR DAC12EN LL_C1_APB1_GRP1_DisableClock\n
4414 * APB1LENR UART7EN LL_C1_APB1_GRP1_DisableClock\n
4415 * APB1LENR UART8EN LL_C1_APB1_GRP1_DisableClock
4416 * @param Periphs This parameter can be a combination of the following values:
4417 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4418 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4419 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4420 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4421 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4422 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4423 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4424 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4425 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4426 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4427 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4428 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4429 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4430 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4431 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4432 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4433 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4434 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4435 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4436 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4437 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4438 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4439 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4440 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4441 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4442 *
4443 * (*) value not defined in all devices.
4444 * @retval uint32_t
4445 */
LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)4446 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)
4447 {
4448 CLEAR_BIT(RCC_C1->APB1LENR, Periphs);
4449 }
4450
4451 /**
4452 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4453 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4454 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4455 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4456 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4457 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4458 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4459 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4460 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4461 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4462 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4463 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n (*)
4464 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4465 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4466 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4467 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4468 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4469 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4470 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4471 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4472 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4473 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4474 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4475 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4476 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4477 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_EnableClockSleep
4478 * @param Periphs This parameter can be a combination of the following values:
4479 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4480 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4481 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4482 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4483 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4484 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4485 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4486 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4487 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4488 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4489 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4490 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4491 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4492 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4493 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4494 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4495 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4496 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4497 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4498 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4499 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4500 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4501 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4502 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4503 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4504 *
4505 * (*) value not defined in all devices.
4506 * @retval None
4507 */
LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)4508 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
4509 {
4510 __IO uint32_t tmpreg;
4511 SET_BIT(RCC_C1->APB1LLPENR, Periphs);
4512 /* Delay after an RCC peripheral clock enabling */
4513 tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);
4514 (void)tmpreg;
4515 }
4516
4517 /**
4518 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4519 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4520 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4521 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4522 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4523 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4524 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4525 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4526 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4527 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4528 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4529 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n (*)
4530 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4531 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4532 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4533 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4534 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4535 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4536 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4537 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4538 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4539 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4540 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4541 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4542 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4543 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_DisableClockSleep
4544 * @param Periphs This parameter can be a combination of the following values:
4545 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4546 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4547 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4548 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4549 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4550 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4551 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4552 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4553 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4554 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4555 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4556 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4557 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4558 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4559 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4560 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4561 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4562 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4563 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4564 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4565 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4566 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4567 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4568 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4569 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4570 *
4571 * (*) value not defined in all devices.
4572 * @retval None
4573 */
LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)4574 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
4575 {
4576 CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);
4577 }
4578
4579 /**
4580 * @brief Enable C1 APB1 peripherals clock.
4581 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_EnableClock\n
4582 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_EnableClock\n
4583 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_EnableClock\n
4584 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_EnableClock\n
4585 * APB1HENR FDCANEN LL_C1_APB1_GRP2_EnableClock
4586 * @param Periphs This parameter can be a combination of the following values:
4587 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4588 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4589 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4590 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4591 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4592 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4593 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4594 *
4595 * (*) value not defined in all devices.
4596 * @retval None
4597 */
LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)4598 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
4599 {
4600 __IO uint32_t tmpreg;
4601 SET_BIT(RCC_C1->APB1HENR, Periphs);
4602 /* Delay after an RCC peripheral clock enabling */
4603 tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);
4604 (void)tmpreg;
4605 }
4606
4607 /**
4608 * @brief Check if C1 APB1 peripheral clock is enabled or not
4609 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_IsEnabledClock\n
4610 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_IsEnabledClock\n
4611 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_IsEnabledClock\n
4612 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_IsEnabledClock\n
4613 * APB1HENR FDCANEN LL_C1_APB1_GRP2_IsEnabledClock
4614 * @param Periphs This parameter can be a combination of the following values:
4615 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4616 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4617 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4618 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4619 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4620 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4621 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4622 *
4623 * (*) value not defined in all devices.
4624 * @retval uint32_t
4625 */
LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)4626 __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
4627 {
4628 return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs) ? 1U : 0U);
4629 }
4630
4631 /**
4632 * @brief Disable C1 APB1 peripherals clock.
4633 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_DisableClock\n
4634 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_DisableClock\n
4635 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_DisableClock\n
4636 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_DisableClock\n
4637 * APB1HENR FDCANEN LL_C1_APB1_GRP2_DisableClock
4638 * @param Periphs This parameter can be a combination of the following values:
4639 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4640 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4641 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4642 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4643 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4644 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4645 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4646 *
4647 * (*) value not defined in all devices.
4648 * @retval None
4649 */
LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)4650 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
4651 {
4652 CLEAR_BIT(RCC_C1->APB1HENR, Periphs);
4653 }
4654
4655 /**
4656 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4657 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4658 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4659 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4660 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4661 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_EnableClockSleep
4662 * @param Periphs This parameter can be a combination of the following values:
4663 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4664 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4665 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4666 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4667 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4668 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4669 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4670 *
4671 * (*) value not defined in all devices.
4672 * @retval None
4673 */
LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)4674 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
4675 {
4676 __IO uint32_t tmpreg;
4677 SET_BIT(RCC_C1->APB1HLPENR, Periphs);
4678 /* Delay after an RCC peripheral clock enabling */
4679 tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);
4680 (void)tmpreg;
4681 }
4682
4683 /**
4684 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4685 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4686 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4687 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4688 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4689 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_DisableClockSleep
4690 * @param Periphs This parameter can be a combination of the following values:
4691 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4692 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4693 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4694 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4695 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4696 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4697 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4698 *
4699 * (*) value not defined in all devices.
4700 * @retval None
4701 */
LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)4702 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
4703 {
4704 CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);
4705 }
4706
4707 /**
4708 * @}
4709 */
4710
4711 /** @addtogroup BUS_LL_EF_APB2 APB2
4712 * @{
4713 */
4714
4715 /**
4716 * @brief Enable C1 APB2 peripherals clock.
4717 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_EnableClock\n
4718 * APB2ENR TIM8EN LL_C1_APB2_GRP1_EnableClock\n
4719 * APB2ENR USART1EN LL_C1_APB2_GRP1_EnableClock\n
4720 * APB2ENR USART6EN LL_C1_APB2_GRP1_EnableClock\n
4721 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClock\n (*)
4722 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClock\n (*)
4723 * APB2ENR SPI1EN LL_C1_APB2_GRP1_EnableClock\n
4724 * APB2ENR SPI4EN LL_C1_APB2_GRP1_EnableClock\n
4725 * APB2ENR TIM15EN LL_C1_APB2_GRP1_EnableClock\n
4726 * APB2ENR TIM16EN LL_C1_APB2_GRP1_EnableClock\n
4727 * APB2ENR TIM17EN LL_C1_APB2_GRP1_EnableClock\n
4728 * APB2ENR SPI5EN LL_C1_APB2_GRP1_EnableClock\n
4729 * APB2ENR SAI1EN LL_C1_APB2_GRP1_EnableClock\n
4730 * APB2ENR SAI2EN LL_C1_APB2_GRP1_EnableClock\n
4731 * APB2ENR SAI3EN LL_C1_APB2_GRP1_EnableClock\n (*)
4732 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_EnableClock\n
4733 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_EnableClock (*)
4734 * @param Periphs This parameter can be a combination of the following values:
4735 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4736 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4737 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4738 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4739 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4740 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4741 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4742 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4744 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4745 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4746 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4747 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4748 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4749 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4750 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4751 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4752 *
4753 * (*) value not defined in all devices.
4754 * @retval None
4755 */
LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)4756 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
4757 {
4758 __IO uint32_t tmpreg;
4759 SET_BIT(RCC_C1->APB2ENR, Periphs);
4760 /* Delay after an RCC peripheral clock enabling */
4761 tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);
4762 (void)tmpreg;
4763 }
4764
4765 /**
4766 * @brief Check if C1 APB2 peripheral clock is enabled or not
4767 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4768 * APB2ENR TIM8EN LL_C1_APB2_GRP1_IsEnabledClock\n
4769 * APB2ENR USART1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4770 * APB2ENR USART6EN LL_C1_APB2_GRP1_IsEnabledClock\n
4771 * APB2ENR UART9EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4772 * APB2ENR USART10EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4773 * APB2ENR SPI1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4774 * APB2ENR SPI4EN LL_C1_APB2_GRP1_IsEnabledClock\n
4775 * APB2ENR TIM15EN LL_C1_APB2_GRP1_IsEnabledClock\n
4776 * APB2ENR TIM16EN LL_C1_APB2_GRP1_IsEnabledClock\n
4777 * APB2ENR TIM17EN LL_C1_APB2_GRP1_IsEnabledClock\n
4778 * APB2ENR SPI5EN LL_C1_APB2_GRP1_IsEnabledClock\n
4779 * APB2ENR SAI1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4780 * APB2ENR SAI2EN LL_C1_APB2_GRP1_IsEnabledClock\n
4781 * APB2ENR SAI3EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4782 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4783 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_IsEnabledClock (*)
4784 * @param Periphs This parameter can be a combination of the following values:
4785 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4786 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4787 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4788 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4789 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4790 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4791 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4792 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4793 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4794 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4795 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4796 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4797 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4798 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4799 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4800 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4801 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4802 *
4803 * (*) value not defined in all devices.
4804 * @retval None
4805 */
LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)4806 __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
4807 {
4808 return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs) ? 1U : 0U);
4809 }
4810
4811 /**
4812 * @brief Disable C1 APB2 peripherals clock.
4813 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_DisableClock\n
4814 * APB2ENR TIM8EN LL_C1_APB2_GRP1_DisableClock\n
4815 * APB2ENR USART1EN LL_C1_APB2_GRP1_DisableClock\n
4816 * APB2ENR USART6EN LL_C1_APB2_GRP1_DisableClock\n
4817 * APB2ENR UART9EN LL_C1_APB2_GRP1_DisableClock\n (*)
4818 * APB2ENR USART10EN LL_C1_APB2_GRP1_DisableClock\n (*)
4819 * APB2ENR SPI1EN LL_C1_APB2_GRP1_DisableClock\n
4820 * APB2ENR SPI4EN LL_C1_APB2_GRP1_DisableClock\n
4821 * APB2ENR TIM15EN LL_C1_APB2_GRP1_DisableClock\n
4822 * APB2ENR TIM16EN LL_C1_APB2_GRP1_DisableClock\n
4823 * APB2ENR TIM17EN LL_C1_APB2_GRP1_DisableClock\n
4824 * APB2ENR SPI5EN LL_C1_APB2_GRP1_DisableClock\n
4825 * APB2ENR SAI1EN LL_C1_APB2_GRP1_DisableClock\n
4826 * APB2ENR SAI2EN LL_C1_APB2_GRP1_DisableClock\n
4827 * APB2ENR SAI3EN LL_C1_APB2_GRP1_DisableClock\n (*)
4828 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_DisableClock\n
4829 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_DisableClock (*)
4830 * @param Periphs This parameter can be a combination of the following values:
4831 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4832 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4833 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4834 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4835 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4836 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4837 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4838 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4839 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4840 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4841 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4842 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4843 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4844 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4845 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4846 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4847 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4848 *
4849 * (*) value not defined in all devices.
4850 * @retval None
4851 */
LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)4852 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)
4853 {
4854 CLEAR_BIT(RCC_C1->APB2ENR, Periphs);
4855 }
4856
4857 /**
4858 * @brief Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.
4859 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4860 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4861 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4862 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4863 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4864 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4865 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4866 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4867 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4868 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4869 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4870 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4871 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4872 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4873 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4874 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4875 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_EnableClockSleep (*)
4876 * @param Periphs This parameter can be a combination of the following values:
4877 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4878 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4879 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4880 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4881 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4882 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4883 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4884 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4885 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4886 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4887 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4888 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4889 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4890 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4891 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4892 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4893 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4894 *
4895 * (*) value not defined in all devices.
4896 * @retval None
4897 */
LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)4898 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
4899 {
4900 __IO uint32_t tmpreg;
4901 SET_BIT(RCC_C1->APB2LPENR, Periphs);
4902 /* Delay after an RCC peripheral clock enabling */
4903 tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);
4904 (void)tmpreg;
4905 }
4906
4907 /**
4908 * @brief Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.
4909 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4910 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4911 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4912 * APB2LPENR UART9LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4913 * APB2LPENR USART10LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4914 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4915 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4916 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4917 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4918 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4919 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4920 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4921 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4922 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4923 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4924 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4925 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_DisableClockSleep (*)
4926 * @param Periphs This parameter can be a combination of the following values:
4927 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4928 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4929 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4930 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4931 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4932 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4933 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4934 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4935 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4936 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4937 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4938 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4939 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4940 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4941 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4942 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4943 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4944 *
4945 * (*) value not defined in all devices.
4946 * @retval None
4947 */
LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)4948 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
4949 {
4950 CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);
4951 }
4952
4953 /**
4954 * @}
4955 */
4956
4957 /** @addtogroup BUS_LL_EF_APB4 APB4
4958 * @{
4959 */
4960
4961 /**
4962 * @brief Enable C1 APB4 peripherals clock.
4963 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_EnableClock\n
4964 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_EnableClock\n
4965 * APB4ENR SPI6EN LL_C1_APB4_GRP1_EnableClock\n
4966 * APB4ENR I2C4EN LL_C1_APB4_GRP1_EnableClock\n
4967 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_EnableClock\n
4968 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_EnableClock\n
4969 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_EnableClock\n (*)
4970 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_EnableClock\n (*)
4971 * APB4ENR DAC2EN LL_C1_APB4_GRP1_EnableClock\n (*)
4972 * APB4ENR COMP12EN LL_C1_APB4_GRP1_EnableClock\n
4973 * APB4ENR VREFEN LL_C1_APB4_GRP1_EnableClock\n
4974 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_EnableClock\n
4975 * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClock\n (*)
4976 * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClock\n (*)
4977 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClock (*)
4978 * @param Periphs This parameter can be a combination of the following values:
4979 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4980 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4981 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4982 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4983 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4984 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4985 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4986 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4987 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4988 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4989 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
4990 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4991 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4992 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4993 *
4994 * (*) value not defined in all devices.
4995 * @retval None
4996 */
LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)4997 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
4998 {
4999 __IO uint32_t tmpreg;
5000 SET_BIT(RCC_C1->APB4ENR, Periphs);
5001 /* Delay after an RCC peripheral clock enabling */
5002 tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);
5003 (void)tmpreg;
5004 }
5005
5006 /**
5007 * @brief Check if C1 APB4 peripheral clock is enabled or not
5008 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_IsEnabledClock\n
5009 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_IsEnabledClock\n
5010 * APB4ENR SPI6EN LL_C1_APB4_GRP1_IsEnabledClock\n
5011 * APB4ENR I2C4EN LL_C1_APB4_GRP1_IsEnabledClock\n
5012 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_IsEnabledClock\n
5013 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_IsEnabledClock\n
5014 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
5015 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
5016 * APB4ENR COMP12EN LL_C1_APB4_GRP1_IsEnabledClock\n
5017 * APB4ENR VREFEN LL_C1_APB4_GRP1_IsEnabledClock\n
5018 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_IsEnabledClock\n
5019 * APB4ENR SAI4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
5020 * APB4ENR DTSEN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
5021 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_IsEnabledClock (*)
5022 * @param Periphs This parameter can be a combination of the following values:
5023 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
5024 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
5025 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
5026 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
5027 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
5028 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
5029 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
5030 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
5031 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
5032 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
5033 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
5034 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
5035 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
5036 *
5037 * (*) value not defined in all devices.
5038 * @retval uint32_t
5039 */
LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)5040 __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
5041 {
5042 return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs) ? 1U : 0U);
5043 }
5044
5045 /**
5046 * @brief Disable C1 APB4 peripherals clock.
5047 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_DisableClock\n
5048 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_DisableClock\n
5049 * APB4ENR SPI6EN LL_C1_APB4_GRP1_DisableClock\n
5050 * APB4ENR I2C4EN LL_C1_APB4_GRP1_DisableClock\n
5051 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_DisableClock\n
5052 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_DisableClock\n
5053 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_DisableClock\n (*)
5054 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_DisableClock\n (*)
5055 * APB4ENR COMP12EN LL_C1_APB4_GRP1_DisableClock\n
5056 * APB4ENR VREFEN LL_C1_APB4_GRP1_DisableClock\n
5057 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_DisableClock\n
5058 * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClock\n (*)
5059 * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClock\n (*)
5060 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClock (*)
5061 * @param Periphs This parameter can be a combination of the following values:
5062 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
5063 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
5064 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
5065 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
5066 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
5067 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
5068 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
5069 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
5070 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
5071 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
5072 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
5073 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
5074 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
5075 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
5076 *
5077 * (*) value not defined in all devices.
5078 * @retval None
5079 */
LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)5080 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)
5081 {
5082 CLEAR_BIT(RCC_C1->APB4ENR, Periphs);
5083 }
5084
5085 /**
5086 * @brief Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.
5087 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5088 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5089 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5090 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5091 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5092 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
5093 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
5094 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5095 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5096 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5097 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5098 * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
5099 * APB4ENR DTSLPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
5100 * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_EnableClockSleep (*)
5101 * @param Periphs This parameter can be a combination of the following values:
5102 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
5103 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
5104 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
5105 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
5106 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
5107 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
5108 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
5109 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
5110 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
5111 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
5112 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
5113 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
5114 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
5115 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
5116 *
5117 * (*) value not defined in all devices.
5118 * @retval None
5119 */
LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)5120 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
5121 {
5122 __IO uint32_t tmpreg;
5123 SET_BIT(RCC_C1->APB4LPENR, Periphs);
5124 /* Delay after an RCC peripheral clock enabling */
5125 tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);
5126 (void)tmpreg;
5127 }
5128
5129 /**
5130 * @brief Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.
5131 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5132 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5133 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5134 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5135 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5136 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5137 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5138 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5139 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5140 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5141 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5142 * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
5143 * APB4ENR DTSLPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
5144 * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_DisableClockSleep (*)
5145 * @param Periphs This parameter can be a combination of the following values:
5146 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
5147 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
5148 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
5149 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
5150 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
5151 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
5152 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
5153 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
5154 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
5155 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
5156 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
5157 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
5158 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
5159 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
5160 *
5161 * (*) value not defined in all devices.
5162 * @retval None
5163 */
LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)5164 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
5165 {
5166 CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);
5167 }
5168
5169 /**
5170 * @}
5171 */
5172
5173 /** @addtogroup BUS_LL_EF_AHB3 AHB3
5174 * @{
5175 */
5176
5177 /**
5178 * @brief Enable C2 AHB3 peripherals clock.
5179 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_EnableClock\n
5180 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_EnableClock\n
5181 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_EnableClock\n
5182 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_EnableClock\n
5183 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_EnableClock\n
5184 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_EnableClock\n
5185 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock\n
5186 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_EnableClock\n
5187 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_EnableClock\n
5188 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_EnableClock\n
5189 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_EnableClock
5190 * @param Periphs This parameter can be a combination of the following values:
5191 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
5192 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5193 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5194 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5195 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5196 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5197 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5198 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5199 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5200 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5201 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5202 * @retval None
5203 */
LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)5204 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
5205 {
5206 __IO uint32_t tmpreg;
5207 SET_BIT(RCC_C2->AHB3ENR, Periphs);
5208 /* Delay after an RCC peripheral clock enabling */
5209 tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);
5210 (void)tmpreg;
5211 }
5212
5213 /**
5214 * @brief Check if C2 AHB3 peripheral clock is enabled or not
5215 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5216 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5217 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5218 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5219 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5220 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5221 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5222 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5223 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5224 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5225 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_IsEnabledClock
5226 * @param Periphs This parameter can be a combination of the following values:
5227 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
5228 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5229 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5230 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5231 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5232 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5233 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5234 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5235 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5236 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5237 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5238 * @retval uint32_t
5239 */
LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)5240 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
5241 {
5242 return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs) ? 1U : 0U);
5243 }
5244
5245 /**
5246 * @brief Disable C2 AHB3 peripherals clock.
5247 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_DisableClock\n
5248 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_DisableClock\n
5249 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_DisableClock\n
5250 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_DisableClock\n
5251 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_DisableClock\n
5252 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_DisableClock\n
5253 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock\n
5254 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_DisableClock\n
5255 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_DisableClock\n
5256 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_DisableClock\n
5257 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_DisableClock
5258 * @param Periphs This parameter can be a combination of the following values:
5259 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
5260 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5261 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5262 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5263 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5264 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5265 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5266 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5267 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5268 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5269 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5270 * @retval None
5271 */
LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)5272 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
5273 {
5274 CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);
5275 }
5276
5277 /**
5278 * @brief Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
5279 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5280 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5281 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5282 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5283 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5284 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5285 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5286 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5287 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5288 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5289 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep
5290 * @param Periphs This parameter can be a combination of the following values:
5291 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5292 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5293 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5294 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5295 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5296 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5297 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5298 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5299 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5300 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5301 * @retval None
5302 */
LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)5303 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
5304 {
5305 __IO uint32_t tmpreg;
5306 SET_BIT(RCC_C2->AHB3LPENR, Periphs);
5307 /* Delay after an RCC peripheral clock enabling */
5308 tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);
5309 (void)tmpreg;
5310 }
5311
5312 /**
5313 * @brief Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
5314 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5315 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5316 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5317 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5318 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5319 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5320 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5321 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5322 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5323 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5324 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep
5325 * @param Periphs This parameter can be a combination of the following values:
5326 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5327 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5328 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5329 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5330 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5331 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5332 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5333 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5334 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5335 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5336 * @retval None
5337 */
LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)5338 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
5339 {
5340 CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);
5341 }
5342
5343 /**
5344 * @}
5345 */
5346
5347 /** @addtogroup BUS_LL_EF_AHB1 AHB1
5348 * @{
5349 */
5350
5351 /**
5352 * @brief Enable C2 AHB1 peripherals clock.
5353 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n
5354 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n
5355 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_EnableClock\n
5356 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_EnableClock\n
5357 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_EnableClock\n
5358 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_EnableClock\n
5359 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_EnableClock\n
5360 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n
5361 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock\n
5362 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n
5363 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock
5364 * @param Periphs This parameter can be a combination of the following values:
5365 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5366 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5367 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5368 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5369 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5370 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5371 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5372 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5373 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5374 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5375 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5376 *
5377 * (*) value not defined in all devices.
5378 * @retval None
5379 */
LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)5380 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
5381 {
5382 __IO uint32_t tmpreg;
5383 SET_BIT(RCC_C2->AHB1ENR, Periphs);
5384 /* Delay after an RCC peripheral clock enabling */
5385 tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);
5386 (void)tmpreg;
5387 }
5388
5389 /**
5390 * @brief Check if C2 AHB1 peripheral clock is enabled or not
5391 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5392 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5393 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5394 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5395 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5396 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5397 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5398 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5399 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5400 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5401 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock
5402 * @param Periphs This parameter can be a combination of the following values:
5403 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5404 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5405 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5406 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5407 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5408 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5409 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5410 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5411 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5412 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5413 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5414 *
5415 * (*) value not defined in all devices.
5416 * @retval uint32_t
5417 */
LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)5418 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
5419 {
5420 return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs) ? 1U : 0U);
5421 }
5422
5423 /**
5424 * @brief Disable C2 AHB1 peripherals clock.
5425 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n
5426 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n
5427 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_DisableClock\n
5428 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_DisableClock\n
5429 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_DisableClock\n
5430 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_DisableClock\n
5431 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_DisableClock\n
5432 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n
5433 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock\n
5434 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n
5435 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock
5436 * @param Periphs This parameter can be a combination of the following values:
5437 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5438 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5439 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5440 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5441 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5442 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5443 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5444 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5445 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5446 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5447 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5448 *
5449 * (*) value not defined in all devices.
5450 * @retval None
5451 */
LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)5452 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
5453 {
5454 CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);
5455 }
5456
5457 /**
5458 * @brief Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
5459 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5460 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5461 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5462 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5463 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5464 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5465 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5466 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5467 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5468 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5469 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep
5470 * @param Periphs This parameter can be a combination of the following values:
5471 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5472 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5473 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5474 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5475 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5476 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5477 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5478 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5479 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5480 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5481 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5482 *
5483 * (*) value not defined in all devices.
5484 * @retval None
5485 */
LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)5486 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
5487 {
5488 __IO uint32_t tmpreg;
5489 SET_BIT(RCC_C2->AHB1LPENR, Periphs);
5490 /* Delay after an RCC peripheral clock enabling */
5491 tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);
5492 (void)tmpreg;
5493 }
5494
5495 /**
5496 * @brief Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
5497 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5498 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5499 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5500 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5501 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5502 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5503 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5504 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5505 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5506 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5507 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep
5508 * @param Periphs This parameter can be a combination of the following values:
5509 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5510 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5511 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5512 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5513 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5514 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5515 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5516 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5517 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5518 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5519 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5520 *
5521 * (*) value not defined in all devices.
5522 * @retval None
5523 */
LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)5524 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
5525 {
5526 CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);
5527 }
5528
5529 /**
5530 * @}
5531 */
5532
5533 /** @addtogroup BUS_LL_EF_AHB2 AHB2
5534 * @{
5535 */
5536
5537 /**
5538 * @brief Enable C2 AHB2 peripherals clock.
5539 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_EnableClock\n
5540 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_EnableClock\n
5541 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_EnableClock\n
5542 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_EnableClock\n
5543 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_EnableClock
5544 * @param Periphs This parameter can be a combination of the following values:
5545 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5546 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5547 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5548 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5549 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5550 *
5551 * (*) value not defined in all devices.
5552 * @retval None
5553 */
LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)5554 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
5555 {
5556 __IO uint32_t tmpreg;
5557 SET_BIT(RCC_C2->AHB2ENR, Periphs);
5558 /* Delay after an RCC peripheral clock enabling */
5559 tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);
5560 (void)tmpreg;
5561 }
5562
5563 /**
5564 * @brief Check if C2 AHB2 peripheral clock is enabled or not
5565 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5566 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5567 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5568 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5569 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_IsEnabledClock
5570 * @param Periphs This parameter can be a combination of the following values:
5571 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5572 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5573 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5574 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5575 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5576 *
5577 * (*) value not defined in all devices.
5578 * @retval uint32_t
5579 */
LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)5580 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
5581 {
5582 return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs) ? 1U : 0U);
5583 }
5584
5585 /**
5586 * @brief Disable C2 AHB2 peripherals clock.
5587 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_DisableClock\n
5588 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_DisableClock\n
5589 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_DisableClock\n
5590 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_DisableClock\n
5591 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_DisableClock
5592 * @param Periphs This parameter can be a combination of the following values:
5593 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5594 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5595 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5596 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5597 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5598 *
5599 * (*) value not defined in all devices.
5600 * @retval None
5601 */
LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)5602 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
5603 {
5604 CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);
5605 }
5606
5607 /**
5608 * @brief Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
5609 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5610 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5611 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5612 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5613 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5614 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5615 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5616 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_EnableClockSleep
5617 * @param Periphs This parameter can be a combination of the following values:
5618 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5619 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5620 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5621 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5622 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5623 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
5624 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
5625 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
5626 *
5627 * (*) value not defined in all devices.
5628 * @retval None
5629 */
LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)5630 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
5631 {
5632 __IO uint32_t tmpreg;
5633 SET_BIT(RCC_C2->AHB2LPENR, Periphs);
5634 /* Delay after an RCC peripheral clock enabling */
5635 tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);
5636 (void)tmpreg;
5637 }
5638
5639 /**
5640 * @brief Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
5641 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5642 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5643 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5644 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5645 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5646 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5647 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5648 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_DisableClockSleep
5649 * @param Periphs This parameter can be a combination of the following values:
5650 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5651 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5652 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5653 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5654 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5655 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
5656 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
5657 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
5658 *
5659 * (*) value not defined in all devices.
5660 * @retval None
5661 */
LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)5662 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
5663 {
5664 CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);
5665 }
5666
5667 /**
5668 * @}
5669 */
5670
5671 /** @addtogroup BUS_LL_EF_AHB4 AHB4
5672 * @{
5673 */
5674
5675 /**
5676 * @brief Enable C2 AHB4 peripherals clock.
5677 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_EnableClock\n
5678 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_EnableClock\n
5679 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_EnableClock\n
5680 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_EnableClock\n
5681 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_EnableClock\n
5682 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_EnableClock\n
5683 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_EnableClock\n
5684 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_EnableClock\n
5685 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_EnableClock\n
5686 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_EnableClock\n
5687 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_EnableClock\n
5688 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_EnableClock\n
5689 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_EnableClock\n
5690 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_EnableClock\n
5691 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_EnableClock\n
5692 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_EnableClock\n
5693 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_EnableClock
5694 * @param Periphs This parameter can be a combination of the following values:
5695 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5696 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5697 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5698 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5699 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5700 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5701 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5702 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5703 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5704 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5705 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5706 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5707 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5708 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5709 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5710 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5711 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5712 *
5713 * (*) value not defined in all devices.
5714 * @retval None
5715 */
LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)5716 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
5717 {
5718 __IO uint32_t tmpreg;
5719 SET_BIT(RCC_C2->AHB4ENR, Periphs);
5720 /* Delay after an RCC peripheral clock enabling */
5721 tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);
5722 (void)tmpreg;
5723 }
5724
5725 /**
5726 * @brief Check if C2 AHB4 peripheral clock is enabled or not
5727 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5728 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5729 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5730 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5731 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5732 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5733 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5734 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5735 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5736 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5737 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5738 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5739 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5740 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_IsEnabledClock\n
5741 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5742 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5743 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_IsEnabledClock
5744 * @param Periphs This parameter can be a combination of the following values:
5745 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5746 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5747 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5748 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5749 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5750 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5751 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5752 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5753 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5754 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5755 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5756 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5757 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5758 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5759 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5760 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5761 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5762 *
5763 * (*) value not defined in all devices.
5764 * @retval uint32_t
5765 */
LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)5766 __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
5767 {
5768 return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs) ? 1U : 0U);
5769 }
5770
5771 /**
5772 * @brief Disable C2 AHB4 peripherals clock.
5773 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_DisableClock\n
5774 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_DisableClock\n
5775 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_DisableClock\n
5776 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_DisableClock\n
5777 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_DisableClock\n
5778 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_DisableClock\n
5779 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_DisableClock\n
5780 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_DisableClock\n
5781 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_DisableClock\n
5782 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_DisableClock\n
5783 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_DisableClock\n
5784 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_DisableClock\n
5785 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_DisableClock\n
5786 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_DisableClock\n
5787 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_DisableClock\n
5788 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_DisableClock\n
5789 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_DisableClock
5790 * @param Periphs This parameter can be a combination of the following values:
5791 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5792 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5793 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5794 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5795 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5796 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5797 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5798 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5799 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5800 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5801 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5802 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5803 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5804 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5805 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5806 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5807 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5808 *
5809 * (*) value not defined in all devices.
5810 * @retval None
5811 */
LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)5812 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)
5813 {
5814 CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);
5815 }
5816
5817 /**
5818 * @brief Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
5819 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5820 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5821 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5822 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5823 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5824 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5825 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5826 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5827 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5828 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5829 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5830 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5831 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5832 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5833 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5834 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_EnableClockSleep
5835 * @param Periphs This parameter can be a combination of the following values:
5836 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5837 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5838 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5839 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5840 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5841 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5842 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5843 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5844 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5845 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5846 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5847 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5848 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5849 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5850 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5851 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5852 * @retval None
5853 */
LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)5854 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
5855 {
5856 __IO uint32_t tmpreg;
5857 SET_BIT(RCC_C2->AHB4LPENR, Periphs);
5858 /* Delay after an RCC peripheral clock enabling */
5859 tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);
5860 (void)tmpreg;
5861 }
5862
5863 /**
5864 * @brief Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
5865 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5866 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5867 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5868 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5869 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5870 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5871 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5872 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5873 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5874 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5875 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5876 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5877 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5878 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5879 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5880 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_DisableClockSleep
5881 * @param Periphs This parameter can be a combination of the following values:
5882 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5883 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5884 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5885 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5886 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5887 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5888 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5889 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5890 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5891 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5892 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5893 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5894 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5895 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5896 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5897 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5898 * @retval None
5899 */
LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)5900 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
5901 {
5902 CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);
5903 }
5904
5905 /**
5906 * @}
5907 */
5908
5909 /** @addtogroup BUS_LL_EF_APB3 APB3
5910 * @{
5911 */
5912
5913 /**
5914 * @brief Enable C2 APB3 peripherals clock.
5915 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_EnableClock\n
5916 * APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n
5917 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock
5918 * @param Periphs This parameter can be a combination of the following values:
5919 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5920 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5921 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5922 *
5923 * (*) value not defined in all devices.
5924 * @retval None
5925 */
LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)5926 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
5927 {
5928 __IO uint32_t tmpreg;
5929 SET_BIT(RCC_C2->APB3ENR, Periphs);
5930 /* Delay after an RCC peripheral clock enabling */
5931 tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);
5932 (void)tmpreg;
5933 }
5934
5935 /**
5936 * @brief Check if C2 APB3 peripheral clock is enabled or not
5937 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_IsEnabledClock\n
5938 * APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n
5939 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock
5940 * @param Periphs This parameter can be a combination of the following values:
5941 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5942 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5943 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5944 *
5945 * (*) value not defined in all devices.
5946 * @retval uint32_t
5947 */
LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)5948 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
5949 {
5950 return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs) ? 1U : 0U);
5951 }
5952
5953 /**
5954 * @brief Disable C2 APB3 peripherals clock.
5955 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_DisableClock\n
5956 * APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n
5957 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock
5958 * @param Periphs This parameter can be a combination of the following values:
5959 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5960 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5961 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5962 *
5963 * (*) value not defined in all devices.
5964 * @retval None
5965 */
LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)5966 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
5967 {
5968 CLEAR_BIT(RCC_C2->APB3ENR, Periphs);
5969 }
5970
5971 /**
5972 * @brief Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.
5973 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_EnableClockSleep\n
5974 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n
5975 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep
5976 * @param Periphs This parameter can be a combination of the following values:
5977 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5978 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5979 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5980 *
5981 * (*) value not defined in all devices.
5982 * @retval None
5983 */
LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)5984 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
5985 {
5986 __IO uint32_t tmpreg;
5987 SET_BIT(RCC_C2->APB3LPENR, Periphs);
5988 /* Delay after an RCC peripheral clock enabling */
5989 tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);
5990 (void)tmpreg;
5991 }
5992
5993 /**
5994 * @brief Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.
5995 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_DisableClockSleep\n
5996 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n
5997 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep
5998 * @param Periphs This parameter can be a combination of the following values:
5999 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
6000 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
6001 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
6002 *
6003 * (*) value not defined in all devices.
6004 * @retval None
6005 */
LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)6006 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
6007 {
6008 CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);
6009 }
6010
6011 /**
6012 * @}
6013 */
6014
6015 /** @addtogroup BUS_LL_EF_APB1 APB1
6016 * @{
6017 */
6018
6019 /**
6020 * @brief Enable C2 APB1 peripherals clock.
6021 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_EnableClock\n
6022 * APB1LENR TIM3EN LL_C2_APB1_GRP1_EnableClock\n
6023 * APB1LENR TIM4EN LL_C2_APB1_GRP1_EnableClock\n
6024 * APB1LENR TIM5EN LL_C2_APB1_GRP1_EnableClock\n
6025 * APB1LENR TIM6EN LL_C2_APB1_GRP1_EnableClock\n
6026 * APB1LENR TIM7EN LL_C2_APB1_GRP1_EnableClock\n
6027 * APB1LENR TIM12EN LL_C2_APB1_GRP1_EnableClock\n
6028 * APB1LENR TIM13EN LL_C2_APB1_GRP1_EnableClock\n
6029 * APB1LENR TIM14EN LL_C2_APB1_GRP1_EnableClock\n
6030 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_EnableClock\n
6031 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_EnableClock\n
6032 * APB1LENR SPI2EN LL_C2_APB1_GRP1_EnableClock\n
6033 * APB1LENR SPI3EN LL_C2_APB1_GRP1_EnableClock\n
6034 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_EnableClock\n
6035 * APB1LENR USART2EN LL_C2_APB1_GRP1_EnableClock\n
6036 * APB1LENR USART3EN LL_C2_APB1_GRP1_EnableClock\n
6037 * APB1LENR UART4EN LL_C2_APB1_GRP1_EnableClock\n
6038 * APB1LENR UART5EN LL_C2_APB1_GRP1_EnableClock\n
6039 * APB1LENR I2C1EN LL_C2_APB1_GRP1_EnableClock\n
6040 * APB1LENR I2C2EN LL_C2_APB1_GRP1_EnableClock\n
6041 * APB1LENR I2C3EN LL_C2_APB1_GRP1_EnableClock\n
6042 * APB1LENR CECEN LL_C2_APB1_GRP1_EnableClock\n
6043 * APB1LENR DAC12EN LL_C2_APB1_GRP1_EnableClock\n
6044 * APB1LENR UART7EN LL_C2_APB1_GRP1_EnableClock\n
6045 * APB1LENR UART8EN LL_C2_APB1_GRP1_EnableClock
6046 * @param Periphs This parameter can be a combination of the following values:
6047 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6048 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6049 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6050 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6051 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6052 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6053 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6054 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6055 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6056 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6057 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6058 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6059 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6060 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6061 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6062 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6063 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6064 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6065 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6066 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6067 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6068 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6069 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6070 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6071 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6072 *
6073 * (*) value not defined in all devices.
6074 * @retval None
6075 */
LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)6076 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
6077 {
6078 __IO uint32_t tmpreg;
6079 SET_BIT(RCC_C2->APB1LENR, Periphs);
6080 /* Delay after an RCC peripheral clock enabling */
6081 tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);
6082 (void)tmpreg;
6083 }
6084
6085 /**
6086 * @brief Check if C2 APB1 peripheral clock is enabled or not
6087 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6088 * APB1LENR TIM3EN LL_C2_APB1_GRP1_IsEnabledClock\n
6089 * APB1LENR TIM4EN LL_C2_APB1_GRP1_IsEnabledClock\n
6090 * APB1LENR TIM5EN LL_C2_APB1_GRP1_IsEnabledClock\n
6091 * APB1LENR TIM6EN LL_C2_APB1_GRP1_IsEnabledClock\n
6092 * APB1LENR TIM7EN LL_C2_APB1_GRP1_IsEnabledClock\n
6093 * APB1LENR TIM12EN LL_C2_APB1_GRP1_IsEnabledClock\n
6094 * APB1LENR TIM13EN LL_C2_APB1_GRP1_IsEnabledClock\n
6095 * APB1LENR TIM14EN LL_C2_APB1_GRP1_IsEnabledClock\n
6096 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock\n
6097 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6098 * APB1LENR SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6099 * APB1LENR SPI3EN LL_C2_APB1_GRP1_IsEnabledClock\n
6100 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_IsEnabledClock\n
6101 * APB1LENR USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6102 * APB1LENR USART3EN LL_C2_APB1_GRP1_IsEnabledClock\n
6103 * APB1LENR UART4EN LL_C2_APB1_GRP1_IsEnabledClock\n
6104 * APB1LENR UART5EN LL_C2_APB1_GRP1_IsEnabledClock\n
6105 * APB1LENR I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n
6106 * APB1LENR I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6107 * APB1LENR I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n
6108 * APB1LENR CECEN LL_C2_APB1_GRP1_IsEnabledClock\n
6109 * APB1LENR DAC12EN LL_C2_APB1_GRP1_IsEnabledClock\n
6110 * APB1LENR UART7EN LL_C2_APB1_GRP1_IsEnabledClock\n
6111 * APB1LENR UART8EN LL_C2_APB1_GRP1_IsEnabledClock
6112 * @param Periphs This parameter can be a combination of the following values:
6113 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6114 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6115 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6116 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6117 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6118 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6119 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6120 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6121 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6122 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6123 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6124 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6125 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6126 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6127 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6128 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6129 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6130 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6131 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6132 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6133 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6134 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6135 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6136 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6137 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6138 *
6139 * (*) value not defined in all devices.
6140 * @retval uint32_t
6141 */
LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)6142 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
6143 {
6144 return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs) ? 1U : 0U);
6145 }
6146
6147 /**
6148 * @brief Disable C2 APB1 peripherals clock.
6149 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_DisableClock\n
6150 * APB1LENR TIM3EN LL_C2_APB1_GRP1_DisableClock\n
6151 * APB1LENR TIM4EN LL_C2_APB1_GRP1_DisableClock\n
6152 * APB1LENR TIM5EN LL_C2_APB1_GRP1_DisableClock\n
6153 * APB1LENR TIM6EN LL_C2_APB1_GRP1_DisableClock\n
6154 * APB1LENR TIM7EN LL_C2_APB1_GRP1_DisableClock\n
6155 * APB1LENR TIM12EN LL_C2_APB1_GRP1_DisableClock\n
6156 * APB1LENR TIM13EN LL_C2_APB1_GRP1_DisableClock\n
6157 * APB1LENR TIM14EN LL_C2_APB1_GRP1_DisableClock\n
6158 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_DisableClock\n
6159 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_DisableClock\n
6160 * APB1LENR SPI2EN LL_C2_APB1_GRP1_DisableClock\n
6161 * APB1LENR SPI3EN LL_C2_APB1_GRP1_DisableClock\n
6162 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_DisableClock\n
6163 * APB1LENR USART2EN LL_C2_APB1_GRP1_DisableClock\n
6164 * APB1LENR USART3EN LL_C2_APB1_GRP1_DisableClock\n
6165 * APB1LENR UART4EN LL_C2_APB1_GRP1_DisableClock\n
6166 * APB1LENR UART5EN LL_C2_APB1_GRP1_DisableClock\n
6167 * APB1LENR I2C1EN LL_C2_APB1_GRP1_DisableClock\n
6168 * APB1LENR I2C2EN LL_C2_APB1_GRP1_DisableClock\n
6169 * APB1LENR I2C3EN LL_C2_APB1_GRP1_DisableClock\n
6170 * APB1LENR CECEN LL_C2_APB1_GRP1_DisableClock\n
6171 * APB1LENR DAC12EN LL_C2_APB1_GRP1_DisableClock\n
6172 * APB1LENR UART7EN LL_C2_APB1_GRP1_DisableClock\n
6173 * APB1LENR UART8EN LL_C2_APB1_GRP1_DisableClock
6174 * @param Periphs This parameter can be a combination of the following values:
6175 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6176 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6177 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6178 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6179 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6180 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6181 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6182 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6183 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6184 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6185 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6186 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6187 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6188 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6189 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6190 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6191 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6192 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6193 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6194 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6195 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6196 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6197 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6198 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6199 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6200 *
6201 * (*) value not defined in all devices.
6202 * @retval None
6203 */
LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)6204 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
6205 {
6206 CLEAR_BIT(RCC_C2->APB1LENR, Periphs);
6207 }
6208
6209 /**
6210 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6211 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6212 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6213 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6214 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6215 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6216 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6217 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6218 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6219 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6220 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6221 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6222 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6223 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6224 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6225 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6226 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6227 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6228 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6229 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6230 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6231 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6232 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6233 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6234 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6235 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_EnableClockSleep
6236 * @param Periphs This parameter can be a combination of the following values:
6237 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6238 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6239 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6240 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6241 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6242 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6243 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6244 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6245 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6246 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6247 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6248 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6249 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6250 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6251 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6252 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6253 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6254 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6255 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6256 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6257 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6258 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6259 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6260 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6261 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6262 *
6263 * (*) value not defined in all devices.
6264 * @retval None
6265 */
LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)6266 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
6267 {
6268 __IO uint32_t tmpreg;
6269 SET_BIT(RCC_C2->APB1LLPENR, Periphs);
6270 /* Delay after an RCC peripheral clock enabling */
6271 tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);
6272 (void)tmpreg;
6273 }
6274
6275 /**
6276 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6277 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6278 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6279 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6280 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6281 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6282 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6283 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6284 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6285 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6286 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6287 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6288 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6289 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6290 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6291 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6292 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6293 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6294 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6295 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6296 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6297 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6298 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6299 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6300 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6301 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_DisableClockSleep
6302 * @param Periphs This parameter can be a combination of the following values:
6303 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6304 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6305 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6306 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6307 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6308 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6309 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6310 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6311 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6312 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6313 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6314 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6315 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6316 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6317 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6318 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6319 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6320 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6321 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6322 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6323 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6324 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6325 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6326 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6327 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6328 *
6329 * (*) value not defined in all devices.
6330 * @retval None
6331 */
LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)6332 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
6333 {
6334 CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);
6335 }
6336
6337 /**
6338 * @brief Enable C2 APB1 peripherals clock.
6339 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_EnableClock\n
6340 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_EnableClock\n
6341 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_EnableClock\n
6342 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_EnableClock\n
6343 * APB1HENR FDCANEN LL_C2_APB1_GRP2_EnableClock
6344 * @param Periphs This parameter can be a combination of the following values:
6345 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6346 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6347 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6348 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6349 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6350 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6351 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6352 *
6353 * (*) value not defined in all devices.
6354 * @retval None
6355 */
LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)6356 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
6357 {
6358 __IO uint32_t tmpreg;
6359 SET_BIT(RCC_C2->APB1HENR, Periphs);
6360 /* Delay after an RCC peripheral clock enabling */
6361 tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);
6362 (void)tmpreg;
6363 }
6364
6365 /**
6366 * @brief Check if C2 APB1 peripheral clock is enabled or not
6367 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_IsEnabledClock\n
6368 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_IsEnabledClock\n
6369 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_IsEnabledClock\n
6370 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_IsEnabledClock\n
6371 * APB1HENR FDCANEN LL_C2_APB1_GRP2_IsEnabledClock
6372 * @param Periphs This parameter can be a combination of the following values:
6373 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6374 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6375 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6376 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6377 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6378 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6379 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6380 *
6381 * (*) value not defined in all devices.
6382 * @retval uint32_t
6383 */
LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)6384 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
6385 {
6386 return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs) ? 1U : 0U);
6387 }
6388
6389 /**
6390 * @brief Disable C2 APB1 peripherals clock.
6391 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_DisableClock\n
6392 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_DisableClock\n
6393 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_DisableClock\n
6394 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_DisableClock\n
6395 * APB1HENR FDCANEN LL_C2_APB1_GRP2_DisableClock
6396 * @param Periphs This parameter can be a combination of the following values:
6397 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6398 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6399 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6400 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6401 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6402 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6403 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6404 *
6405 * (*) value not defined in all devices.
6406 * @retval None
6407 */
LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)6408 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
6409 {
6410 CLEAR_BIT(RCC_C2->APB1HENR, Periphs);
6411 }
6412
6413 /**
6414 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6415 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6416 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6417 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6418 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6419 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_EnableClockSleep
6420 * @param Periphs This parameter can be a combination of the following values:
6421 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6422 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6423 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6424 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6425 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6426 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6427 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6428 *
6429 * (*) value not defined in all devices.
6430 * @retval None
6431 */
LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)6432 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
6433 {
6434 __IO uint32_t tmpreg;
6435 SET_BIT(RCC_C2->APB1HLPENR, Periphs);
6436 /* Delay after an RCC peripheral clock enabling */
6437 tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);
6438 (void)tmpreg;
6439 }
6440
6441 /**
6442 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6443 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6444 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6445 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6446 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6447 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_DisableClockSleep
6448 * @param Periphs This parameter can be a combination of the following values:
6449 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6450 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6451 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6452 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6453 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6454 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6455 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6456 *
6457 * (*) value not defined in all devices.
6458 * @retval None
6459 */
LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)6460 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
6461 {
6462 CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);
6463 }
6464
6465 /**
6466 * @}
6467 */
6468
6469 /** @addtogroup BUS_LL_EF_APB2 APB2
6470 * @{
6471 */
6472
6473 /**
6474 * @brief Enable C2 APB2 peripherals clock.
6475 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n
6476 * APB2ENR TIM8EN LL_C2_APB2_GRP1_EnableClock\n
6477 * APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n
6478 * APB2ENR USART6EN LL_C2_APB2_GRP1_EnableClock\n
6479 * APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n
6480 * APB2ENR SPI4EN LL_C2_APB2_GRP1_EnableClock\n
6481 * APB2ENR TIM15EN LL_C2_APB2_GRP1_EnableClock\n
6482 * APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n
6483 * APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n
6484 * APB2ENR SPI5EN LL_C2_APB2_GRP1_EnableClock\n
6485 * APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock\n
6486 * APB2ENR SAI2EN LL_C2_APB2_GRP1_EnableClock\n
6487 * APB2ENR SAI3EN LL_C2_APB2_GRP1_EnableClock\n
6488 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_EnableClock\n
6489 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_EnableClock
6490 * @param Periphs This parameter can be a combination of the following values:
6491 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6492 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6493 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6494 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6495 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6496 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6497 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6498 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6499 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6500 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6501 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6502 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6503 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6504 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6505 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6506 *
6507 * (*) value not defined in all devices.
6508
6509 * @retval None
6510 */
LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)6511 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
6512 {
6513 __IO uint32_t tmpreg;
6514 SET_BIT(RCC_C2->APB2ENR, Periphs);
6515 /* Delay after an RCC peripheral clock enabling */
6516 tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);
6517 (void)tmpreg;
6518 }
6519
6520 /**
6521 * @brief Check if C2 APB2 peripheral clock is enabled or not
6522 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6523 * APB2ENR TIM8EN LL_C2_APB2_GRP1_IsEnabledClock\n
6524 * APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6525 * APB2ENR USART6EN LL_C2_APB2_GRP1_IsEnabledClock\n
6526 * APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6527 * APB2ENR SPI4EN LL_C2_APB2_GRP1_IsEnabledClock\n
6528 * APB2ENR TIM15EN LL_C2_APB2_GRP1_IsEnabledClock\n
6529 * APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n
6530 * APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n
6531 * APB2ENR SPI5EN LL_C2_APB2_GRP1_IsEnabledClock\n
6532 * APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6533 * APB2ENR SAI2EN LL_C2_APB2_GRP1_IsEnabledClock\n
6534 * APB2ENR SAI3EN LL_C2_APB2_GRP1_IsEnabledClock\n
6535 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6536 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_IsEnabledClock
6537 * @param Periphs This parameter can be a combination of the following values:
6538 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6539 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6540 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6541 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6542 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6543 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6544 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6545 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6546 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6547 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6548 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6549 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6550 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6551 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6552 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6553 *
6554 * (*) value not defined in all devices.
6555 * @retval uint32_t
6556 */
LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)6557 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
6558 {
6559 return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs) ? 1U : 0U);
6560 }
6561
6562 /**
6563 * @brief Disable C2 APB2 peripherals clock.
6564 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n
6565 * APB2ENR TIM8EN LL_C2_APB2_GRP1_DisableClock\n
6566 * APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n
6567 * APB2ENR USART6EN LL_C2_APB2_GRP1_DisableClock\n
6568 * APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n
6569 * APB2ENR SPI4EN LL_C2_APB2_GRP1_DisableClock\n
6570 * APB2ENR TIM15EN LL_C2_APB2_GRP1_DisableClock\n
6571 * APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n
6572 * APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n
6573 * APB2ENR SPI5EN LL_C2_APB2_GRP1_DisableClock\n
6574 * APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock\n
6575 * APB2ENR SAI2EN LL_C2_APB2_GRP1_DisableClock\n
6576 * APB2ENR SAI3EN LL_C2_APB2_GRP1_DisableClock\n
6577 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_DisableClock\n
6578 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_DisableClock
6579 * @param Periphs This parameter can be a combination of the following values:
6580 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6581 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6582 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6583 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6584 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6585 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6586 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6587 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6588 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6589 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6590 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6591 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6592 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6593 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6594 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6595 *
6596 * (*) value not defined in all devices.
6597 * @retval None
6598 */
LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)6599 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
6600 {
6601 CLEAR_BIT(RCC_C2->APB2ENR, Periphs);
6602 }
6603
6604 /**
6605 * @brief Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.
6606 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6607 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6608 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6609 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6610 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6611 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6612 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6613 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6614 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6615 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6616 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6617 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6618 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6619 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6620 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_EnableClockSleep
6621 * @param Periphs This parameter can be a combination of the following values:
6622 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6623 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6624 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6625 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6626 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6627 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6628 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6629 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6630 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6631 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6632 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6633 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6634 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6635 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6636 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6637 *
6638 * (*) value not defined in all devices.
6639 * @retval None
6640 */
LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)6641 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
6642 {
6643 __IO uint32_t tmpreg;
6644 SET_BIT(RCC_C2->APB2LPENR, Periphs);
6645 /* Delay after an RCC peripheral clock enabling */
6646 tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);
6647 (void)tmpreg;
6648 }
6649
6650 /**
6651 * @brief Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.
6652 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6653 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6654 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6655 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6656 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6657 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6658 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6659 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6660 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6661 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6662 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6663 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6664 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6665 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6666 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_DisableClockSleep
6667 * @param Periphs This parameter can be a combination of the following values:
6668 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6669 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6670 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6671 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6672 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6673 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6674 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6675 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6676 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6677 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6678 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6679 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6680 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6681 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6682 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6683 *
6684 * (*) value not defined in all devices.
6685 * @retval None
6686 */
LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)6687 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
6688 {
6689 CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);
6690 }
6691
6692 /**
6693 * @}
6694 */
6695
6696 /** @addtogroup BUS_LL_EF_APB4 APB4
6697 * @{
6698 */
6699
6700 /**
6701 * @brief Enable C2 APB4 peripherals clock.
6702 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_EnableClock\n
6703 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_EnableClock\n
6704 * APB4ENR SPI6EN LL_C2_APB4_GRP1_EnableClock\n
6705 * APB4ENR I2C4EN LL_C2_APB4_GRP1_EnableClock\n
6706 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_EnableClock\n
6707 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_EnableClock\n
6708 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_EnableClock\n
6709 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_EnableClock\n
6710 * APB4ENR COMP12EN LL_C2_APB4_GRP1_EnableClock\n
6711 * APB4ENR VREFEN LL_C2_APB4_GRP1_EnableClock\n
6712 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_EnableClock\n
6713 * APB4ENR SAI4EN LL_C2_APB4_GRP1_EnableClock
6714 * @param Periphs This parameter can be a combination of the following values:
6715 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6716 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6717 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6718 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6719 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6720 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6721 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6722 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6723 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6724 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6725 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6726 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6727 *
6728 * (*) value not defined in all devices
6729 * @retval None
6730 */
LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)6731 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
6732 {
6733 __IO uint32_t tmpreg;
6734 SET_BIT(RCC_C2->APB4ENR, Periphs);
6735 /* Delay after an RCC peripheral clock enabling */
6736 tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);
6737 (void)tmpreg;
6738 }
6739
6740 /**
6741 * @brief Check if C2 APB4 peripheral clock is enabled or not
6742 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_IsEnabledClock\n
6743 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_IsEnabledClock\n
6744 * APB4ENR SPI6EN LL_C2_APB4_GRP1_IsEnabledClock\n
6745 * APB4ENR I2C4EN LL_C2_APB4_GRP1_IsEnabledClock\n
6746 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_IsEnabledClock\n
6747 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_IsEnabledClock\n
6748 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_IsEnabledClock\n
6749 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_IsEnabledClock\n
6750 * APB4ENR COMP12EN LL_C2_APB4_GRP1_IsEnabledClock\n
6751 * APB4ENR VREFEN LL_C2_APB4_GRP1_IsEnabledClock\n
6752 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_IsEnabledClock\n
6753 * APB4ENR SAI4EN LL_C2_APB4_GRP1_IsEnabledClock
6754 * @param Periphs This parameter can be a combination of the following values:
6755 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6756 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6757 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6758 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6759 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6760 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6761 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6762 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6763 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6764 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6765 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6766 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6767 *
6768 * (*) value not defined in all devices
6769 * @retval uint32_t
6770 */
LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)6771 __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
6772 {
6773 return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs) ? 1U : 0U);
6774 }
6775
6776 /**
6777 * @brief Disable C2 APB4 peripherals clock.
6778 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_DisableClock\n
6779 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_DisableClock\n
6780 * APB4ENR SPI6EN LL_C2_APB4_GRP1_DisableClock\n
6781 * APB4ENR I2C4EN LL_C2_APB4_GRP1_DisableClock\n
6782 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_DisableClock\n
6783 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_DisableClock\n
6784 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_DisableClock\n
6785 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_DisableClock\n
6786 * APB4ENR COMP12EN LL_C2_APB4_GRP1_DisableClock\n
6787 * APB4ENR VREFEN LL_C2_APB4_GRP1_DisableClock\n
6788 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_DisableClock\n
6789 * APB4ENR SAI4EN LL_C2_APB4_GRP1_DisableClock
6790 * @param Periphs This parameter can be a combination of the following values:
6791 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6792 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6793 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6794 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6795 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6796 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6797 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6798 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6799 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6800 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6801 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6802 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6803 *
6804 * (*) value not defined in all devices
6805 * @retval None
6806 */
LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)6807 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
6808 {
6809 CLEAR_BIT(RCC_C2->APB4ENR, Periphs);
6810 }
6811
6812 /**
6813 * @brief Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.
6814 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6815 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6816 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6817 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6818 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6819 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6820 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6821 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6822 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6823 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6824 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6825 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_EnableClockSleep
6826 * @param Periphs This parameter can be a combination of the following values:
6827 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6828 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6829 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6830 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6831 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6832 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6833 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6834 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6835 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6836 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6837 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6838 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6839 *
6840 * (*) value not defined in all devices
6841 * @retval None
6842 */
LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)6843 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
6844 {
6845 __IO uint32_t tmpreg;
6846 SET_BIT(RCC_C2->APB4LPENR, Periphs);
6847 /* Delay after an RCC peripheral clock enabling */
6848 tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);
6849 (void)tmpreg;
6850 }
6851
6852 /**
6853 * @brief Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.
6854 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6855 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6856 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6857 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6858 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6859 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6860 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6861 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6862 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6863 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6864 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6865 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_DisableClockSleep
6866 * @param Periphs This parameter can be a combination of the following values:
6867 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6868 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6869 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6870 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6871 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6872 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6873 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6874 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6875 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6876 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6877 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6878 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6879 *
6880 * (*) value not defined in all devices
6881 * @retval None
6882 */
LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)6883 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
6884 {
6885 CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);
6886 }
6887
6888 /**
6889 * @}
6890 */
6891
6892 #endif /*DUAL_CORE*/
6893
6894 /**
6895 * @}
6896 */
6897
6898 /**
6899 * @}
6900 */
6901
6902 #endif /* defined(RCC) */
6903
6904 /**
6905 * @}
6906 */
6907
6908 #ifdef __cplusplus
6909 }
6910 #endif
6911
6912 #endif /* STM32H7xx_LL_BUS_H */
6913
6914
