1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_qspi.h 4 * @author MCD Application Team 5 * @brief Header file of QSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_QSPI_H 21 #define STM32H7xx_HAL_QSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 #if defined (DLYB_QUADSPI) 30 #include "stm32h7xx_ll_delayblock.h" 31 #endif /* DLYB_QUADSPI */ 32 33 #if defined(QUADSPI) 34 35 /** @addtogroup STM32H7xx_HAL_Driver 36 * @{ 37 */ 38 39 /** @addtogroup QSPI 40 * @{ 41 */ 42 43 /* Exported types ------------------------------------------------------------*/ 44 /** @defgroup QSPI_Exported_Types QSPI Exported Types 45 * @{ 46 */ 47 48 /** 49 * @brief QSPI Init structure definition 50 */ 51 typedef struct 52 { 53 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 54 This parameter can be a number between 0 and 255 */ 55 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 56 This parameter can be a value between 1 and 32 */ 57 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 58 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 59 This parameter can be a value of @ref QSPI_SampleShifting */ 60 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 61 required to address the flash memory. The flash capacity can be up to 4GB 62 (addressed using 32 bits) in indirect mode, but the addressable space in 63 memory-mapped mode is limited to 256MB 64 This parameter can be a number between 0 and 31 */ 65 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 66 of clock cycles which the chip select must remain high between commands. 67 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 68 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 69 This parameter can be a value of @ref QSPI_ClockMode */ 70 uint32_t FlashID; /* Specifies the Flash which will be used, 71 This parameter can be a value of @ref QSPI_Flash_Select */ 72 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 73 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 74 }QSPI_InitTypeDef; 75 76 /** 77 * @brief HAL QSPI State structures definition 78 */ 79 typedef enum 80 { 81 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 82 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 83 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 84 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 85 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 86 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 87 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 88 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 89 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 90 }HAL_QSPI_StateTypeDef; 91 92 /** 93 * @brief QSPI Handle Structure definition 94 */ 95 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 96 typedef struct __QSPI_HandleTypeDef 97 #else 98 typedef struct 99 #endif 100 { 101 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 102 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 103 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 104 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 105 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 106 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 107 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 108 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 109 MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ 110 __IO HAL_LockTypeDef Lock; /* Locking object */ 111 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 112 __IO uint32_t ErrorCode; /* QSPI Error code */ 113 uint32_t Timeout; /* Timeout for the QSPI memory access */ 114 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 115 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 116 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 117 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 118 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 119 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 120 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 121 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 122 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 123 124 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 125 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 126 #endif 127 }QSPI_HandleTypeDef; 128 129 /** 130 * @brief QSPI Command structure definition 131 */ 132 typedef struct 133 { 134 uint32_t Instruction; /* Specifies the Instruction to be sent 135 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 136 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 137 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 138 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 139 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 140 uint32_t AddressSize; /* Specifies the Address Size 141 This parameter can be a value of @ref QSPI_AddressSize */ 142 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 143 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 144 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 145 This parameter can be a number between 0 and 31 */ 146 uint32_t InstructionMode; /* Specifies the Instruction Mode 147 This parameter can be a value of @ref QSPI_InstructionMode */ 148 uint32_t AddressMode; /* Specifies the Address Mode 149 This parameter can be a value of @ref QSPI_AddressMode */ 150 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 151 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 152 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 153 This parameter can be a value of @ref QSPI_DataMode */ 154 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 155 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 156 until end of memory)*/ 157 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 158 This parameter can be a value of @ref QSPI_DdrMode */ 159 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 160 output by one half of system clock in DDR mode. 161 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 162 uint32_t SIOOMode; /* Specifies the send instruction only once mode 163 This parameter can be a value of @ref QSPI_SIOOMode */ 164 }QSPI_CommandTypeDef; 165 166 /** 167 * @brief QSPI Auto Polling mode configuration structure definition 168 */ 169 typedef struct 170 { 171 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 172 This parameter can be any value between 0 and 0xFFFFFFFF */ 173 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 174 This parameter can be any value between 0 and 0xFFFFFFFF */ 175 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 176 This parameter can be any value between 0 and 0xFFFF */ 177 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 178 This parameter can be any value between 1 and 4 */ 179 uint32_t MatchMode; /* Specifies the method used for determining a match. 180 This parameter can be a value of @ref QSPI_MatchMode */ 181 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 182 This parameter can be a value of @ref QSPI_AutomaticStop */ 183 }QSPI_AutoPollingTypeDef; 184 185 /** 186 * @brief QSPI Memory Mapped mode configuration structure definition 187 */ 188 typedef struct 189 { 190 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 191 This parameter can be any value between 0 and 0xFFFF */ 192 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 193 This parameter can be a value of @ref QSPI_TimeOutActivation */ 194 }QSPI_MemoryMappedTypeDef; 195 196 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 197 /** 198 * @brief HAL QSPI Callback ID enumeration definition 199 */ 200 typedef enum 201 { 202 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 203 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 204 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 205 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 206 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 207 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 208 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 209 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 210 211 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 212 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 213 }HAL_QSPI_CallbackIDTypeDef; 214 215 /** 216 * @brief HAL QSPI Callback pointer definition 217 */ 218 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 219 #endif 220 /** 221 * @} 222 */ 223 224 /* Exported constants --------------------------------------------------------*/ 225 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 226 * @{ 227 */ 228 229 /** @defgroup QSPI_ErrorCode QSPI Error Code 230 * @{ 231 */ 232 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 233 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 234 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 235 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 236 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 237 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 238 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 239 #endif 240 /** 241 * @} 242 */ 243 244 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 245 * @{ 246 */ 247 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 248 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 249 /** 250 * @} 251 */ 252 253 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 254 * @{ 255 */ 256 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 257 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 258 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 259 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 260 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 261 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 262 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 263 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 264 /** 265 * @} 266 */ 267 268 /** @defgroup QSPI_ClockMode QSPI Clock Mode 269 * @{ 270 */ 271 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 272 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 273 /** 274 * @} 275 */ 276 277 /** @defgroup QSPI_Flash_Select QSPI Flash Select 278 * @{ 279 */ 280 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 281 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 282 /** 283 * @} 284 */ 285 286 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 287 * @{ 288 */ 289 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 290 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 291 /** 292 * @} 293 */ 294 295 /** @defgroup QSPI_AddressSize QSPI Address Size 296 * @{ 297 */ 298 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 299 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 300 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 301 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 302 /** 303 * @} 304 */ 305 306 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 307 * @{ 308 */ 309 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 310 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 311 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 312 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 313 /** 314 * @} 315 */ 316 317 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 318 * @{ 319 */ 320 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 321 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 322 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 323 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 324 /** 325 * @} 326 */ 327 328 /** @defgroup QSPI_AddressMode QSPI Address Mode 329 * @{ 330 */ 331 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 332 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 333 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 334 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 335 /** 336 * @} 337 */ 338 339 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 340 * @{ 341 */ 342 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 343 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 344 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 345 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 346 /** 347 * @} 348 */ 349 350 /** @defgroup QSPI_DataMode QSPI Data Mode 351 * @{ 352 */ 353 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 354 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 355 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 356 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 357 /** 358 * @} 359 */ 360 361 /** @defgroup QSPI_DdrMode QSPI DDR Mode 362 * @{ 363 */ 364 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 365 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 366 /** 367 * @} 368 */ 369 370 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 371 * @{ 372 */ 373 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 374 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 375 /** 376 * @} 377 */ 378 379 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 380 * @{ 381 */ 382 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 383 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 384 /** 385 * @} 386 */ 387 388 /** @defgroup QSPI_MatchMode QSPI Match Mode 389 * @{ 390 */ 391 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 392 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 393 /** 394 * @} 395 */ 396 397 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 398 * @{ 399 */ 400 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 401 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 402 /** 403 * @} 404 */ 405 406 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 407 * @{ 408 */ 409 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 410 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 411 /** 412 * @} 413 */ 414 415 /** @defgroup QSPI_Flags QSPI Flags 416 * @{ 417 */ 418 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 419 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 420 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 421 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 422 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 423 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 424 /** 425 * @} 426 */ 427 428 /** @defgroup QSPI_Interrupts QSPI Interrupts 429 * @{ 430 */ 431 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 432 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 433 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 434 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 435 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 436 /** 437 * @} 438 */ 439 440 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 441 * @brief QSPI Timeout definition 442 * @{ 443 */ 444 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 445 /** 446 * @} 447 */ 448 449 /** 450 * @} 451 */ 452 453 /* Exported macros -----------------------------------------------------------*/ 454 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 455 * @{ 456 */ 457 /** @brief Reset QSPI handle state. 458 * @param __HANDLE__ QSPI handle. 459 * @retval None 460 */ 461 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 462 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 463 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 464 (__HANDLE__)->MspInitCallback = NULL; \ 465 (__HANDLE__)->MspDeInitCallback = NULL; \ 466 } while(0) 467 #else 468 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 469 #endif 470 471 /** @brief Enable the QSPI peripheral. 472 * @param __HANDLE__ specifies the QSPI Handle. 473 * @retval None 474 */ 475 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 476 477 /** @brief Disable the QSPI peripheral. 478 * @param __HANDLE__ specifies the QSPI Handle. 479 * @retval None 480 */ 481 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 482 483 /** @brief Enable the specified QSPI interrupt. 484 * @param __HANDLE__ specifies the QSPI Handle. 485 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. 486 * This parameter can be one of the following values: 487 * @arg QSPI_IT_TO: QSPI Timeout interrupt 488 * @arg QSPI_IT_SM: QSPI Status match interrupt 489 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 490 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 491 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 492 * @retval None 493 */ 494 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 495 496 497 /** @brief Disable the specified QSPI interrupt. 498 * @param __HANDLE__ specifies the QSPI Handle. 499 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. 500 * This parameter can be one of the following values: 501 * @arg QSPI_IT_TO: QSPI Timeout interrupt 502 * @arg QSPI_IT_SM: QSPI Status match interrupt 503 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 504 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 505 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 506 * @retval None 507 */ 508 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 509 510 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 511 * @param __HANDLE__ specifies the QSPI Handle. 512 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. 513 * This parameter can be one of the following values: 514 * @arg QSPI_IT_TO: QSPI Timeout interrupt 515 * @arg QSPI_IT_SM: QSPI Status match interrupt 516 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 517 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 518 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 519 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 520 */ 521 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 522 523 /** 524 * @brief Check whether the selected QSPI flag is set or not. 525 * @param __HANDLE__ specifies the QSPI Handle. 526 * @param __FLAG__ specifies the QSPI flag to check. 527 * This parameter can be one of the following values: 528 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 529 * @arg QSPI_FLAG_TO: QSPI Timeout flag 530 * @arg QSPI_FLAG_SM: QSPI Status match flag 531 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 532 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 533 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 534 * @retval None 535 */ 536 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 537 538 /** @brief Clears the specified QSPI's flag status. 539 * @param __HANDLE__ specifies the QSPI Handle. 540 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set 541 * This parameter can be one of the following values: 542 * @arg QSPI_FLAG_TO: QSPI Timeout flag 543 * @arg QSPI_FLAG_SM: QSPI Status match flag 544 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 545 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 546 * @retval None 547 */ 548 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 549 /** 550 * @} 551 */ 552 553 /* Exported functions --------------------------------------------------------*/ 554 /** @addtogroup QSPI_Exported_Functions 555 * @{ 556 */ 557 558 /** @addtogroup QSPI_Exported_Functions_Group1 559 * @{ 560 */ 561 /* Initialization/de-initialization functions ********************************/ 562 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 563 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 564 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 565 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 566 /** 567 * @} 568 */ 569 570 /** @addtogroup QSPI_Exported_Functions_Group2 571 * @{ 572 */ 573 /* IO operation functions *****************************************************/ 574 /* QSPI IRQ handler method */ 575 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 576 577 /* QSPI indirect mode */ 578 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 579 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 580 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 581 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 582 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 583 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 584 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 585 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 586 587 /* QSPI status flag polling mode */ 588 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 589 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 590 591 /* QSPI memory-mapped mode */ 592 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 593 594 /* Callback functions in non-blocking modes ***********************************/ 595 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 596 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 597 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 598 599 /* QSPI indirect mode */ 600 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 601 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 602 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 603 604 /* QSPI status flag polling mode */ 605 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 606 607 /* QSPI memory-mapped mode */ 608 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 609 610 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 611 /* QSPI callback registering/unregistering */ 612 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 613 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 614 #endif 615 /** 616 * @} 617 */ 618 619 /** @addtogroup QSPI_Exported_Functions_Group3 620 * @{ 621 */ 622 /* Peripheral Control and State functions ************************************/ 623 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi); 624 uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi); 625 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 626 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 627 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 628 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 629 uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi); 630 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 631 /** 632 * @} 633 */ 634 635 /** 636 * @} 637 */ 638 /* End of exported functions -------------------------------------------------*/ 639 640 /* Private macros ------------------------------------------------------------*/ 641 /** @defgroup QSPI_Private_Macros QSPI Private Macros 642 * @{ 643 */ 644 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 645 646 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) 647 648 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 649 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 650 651 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 652 653 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 654 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 655 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 656 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 657 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 658 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 659 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 660 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 661 662 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 663 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 664 665 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 666 ((FLASH_ID) == QSPI_FLASH_ID_2)) 667 668 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 669 ((MODE) == QSPI_DUALFLASH_DISABLE)) 670 671 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 672 673 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 674 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 675 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 676 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 677 678 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 679 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 680 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 681 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 682 683 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 684 685 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 686 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 687 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 688 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 689 690 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 691 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 692 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 693 ((MODE) == QSPI_ADDRESS_4_LINES)) 694 695 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 696 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 697 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 698 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 699 700 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 701 ((MODE) == QSPI_DATA_1_LINE) || \ 702 ((MODE) == QSPI_DATA_2_LINES) || \ 703 ((MODE) == QSPI_DATA_4_LINES)) 704 705 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 706 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 707 708 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 709 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 710 711 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 712 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 713 714 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 715 716 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 717 718 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 719 ((MODE) == QSPI_MATCH_MODE_OR)) 720 721 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 722 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 723 724 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 725 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 726 727 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 728 /** 729 * @} 730 */ 731 /* End of private macros -----------------------------------------------------*/ 732 733 /** 734 * @} 735 */ 736 737 /** 738 * @} 739 */ 740 741 #endif /* defined(QUADSPI) */ 742 743 #ifdef __cplusplus 744 } 745 #endif 746 747 #endif /* STM32H7xx_HAL_QSPI_H */ 748
