1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h7rsxx_ll_tim.h"
22 #include "stm32h7rsxx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32H7RSxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM9) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \
71 || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
72 || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
73
74 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
75 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
76
77 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
78 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
79
80 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
81 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
82
83 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
84 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
85 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
86
87 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
89 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
90 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
91
92 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
108
109 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
111 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
112
113 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
114 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
115 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
116 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
117 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
118 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
119 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
120 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
121 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
122
123 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
124 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
125
126 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
127 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
128
129 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
130 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
131
132 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
133 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
134 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
135 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
136
137 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
138 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
139
140 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
141 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
142
143 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
152 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
153 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
154 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
159
160 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
161 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
162
163 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
164 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
165
166 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
167 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
168
169 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
185
186 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
187 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
188
189 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
190 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
191 /**
192 * @}
193 */
194
195
196 /* Private function prototypes -----------------------------------------------*/
197 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
198 * @{
199 */
200 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
201 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
202 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
203 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
204 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
205 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
206 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
207 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
208 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
209 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
210 /**
211 * @}
212 */
213
214 /* Exported functions --------------------------------------------------------*/
215 /** @addtogroup TIM_LL_Exported_Functions
216 * @{
217 */
218
219 /** @addtogroup TIM_LL_EF_Init
220 * @{
221 */
222
223 /**
224 * @brief Set TIMx registers to their reset values.
225 * @param TIMx Timer instance
226 * @retval An ErrorStatus enumeration value:
227 * - SUCCESS: TIMx registers are de-initialized
228 * - ERROR: invalid TIMx instance
229 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)230 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
231 {
232 ErrorStatus result = SUCCESS;
233
234 /* Check the parameters */
235 assert_param(IS_TIM_INSTANCE(TIMx));
236
237 if (TIMx == TIM1)
238 {
239 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
240 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
241 }
242 else if (TIMx == TIM2)
243 {
244 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
245 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
246 }
247 else if (TIMx == TIM3)
248 {
249 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
250 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
251 }
252 else if (TIMx == TIM4)
253 {
254 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
255 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
256 }
257 else if (TIMx == TIM5)
258 {
259 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
260 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
261 }
262 else if (TIMx == TIM6)
263 {
264 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
265 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
266 }
267 else if (TIMx == TIM7)
268 {
269 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
270 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
271 }
272 else if (TIMx == TIM9)
273 {
274 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
275 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
276 }
277 else if (TIMx == TIM12)
278 {
279 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
280 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
281 }
282 else if (TIMx == TIM13)
283 {
284 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
285 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
286 }
287 else if (TIMx == TIM14)
288 {
289 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
290 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
291 }
292 else if (TIMx == TIM15)
293 {
294 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
295 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
296 }
297 else if (TIMx == TIM16)
298 {
299 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
300 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
301 }
302 else if (TIMx == TIM17)
303 {
304 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
305 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
306 }
307 else
308 {
309 result = ERROR;
310 }
311
312 return result;
313 }
314
315 /**
316 * @brief Set the fields of the time base unit configuration data structure
317 * to their default values.
318 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
319 * @retval None
320 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)321 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
322 {
323 /* Set the default configuration */
324 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
325 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
326 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
327 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
328 TIM_InitStruct->RepetitionCounter = 0x00000000U;
329 }
330
331 /**
332 * @brief Configure the TIMx time base unit.
333 * @param TIMx Timer Instance
334 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
335 * (TIMx time base unit configuration data structure)
336 * @retval An ErrorStatus enumeration value:
337 * - SUCCESS: TIMx registers are de-initialized
338 * - ERROR: not applicable
339 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)340 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
341 {
342 uint32_t tmpcr1;
343
344 /* Check the parameters */
345 assert_param(IS_TIM_INSTANCE(TIMx));
346 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
347 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
348
349 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
350
351 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
352 {
353 /* Select the Counter Mode */
354 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
355 }
356
357 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
358 {
359 /* Set the clock division */
360 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
361 }
362
363 /* Write to TIMx CR1 */
364 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
365
366 /* Set the Autoreload value */
367 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
368
369 /* Set the Prescaler value */
370 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
371
372 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
373 {
374 /* Set the Repetition Counter value */
375 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
376 }
377
378 /* Generate an update event to reload the Prescaler
379 and the repetition counter value (if applicable) immediately */
380 LL_TIM_GenerateEvent_UPDATE(TIMx);
381
382 return SUCCESS;
383 }
384
385 /**
386 * @brief Set the fields of the TIMx output channel configuration data
387 * structure to their default values.
388 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
389 * (the output channel configuration data structure)
390 * @retval None
391 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)392 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
393 {
394 /* Set the default configuration */
395 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
396 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
397 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
398 TIM_OC_InitStruct->CompareValue = 0x00000000U;
399 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
400 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
401 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
402 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
403 }
404
405 /**
406 * @brief Configure the TIMx output channel.
407 * @param TIMx Timer Instance
408 * @param Channel This parameter can be one of the following values:
409 * @arg @ref LL_TIM_CHANNEL_CH1
410 * @arg @ref LL_TIM_CHANNEL_CH2
411 * @arg @ref LL_TIM_CHANNEL_CH3
412 * @arg @ref LL_TIM_CHANNEL_CH4
413 * @arg @ref LL_TIM_CHANNEL_CH5
414 * @arg @ref LL_TIM_CHANNEL_CH6
415 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
416 * data structure)
417 * @retval An ErrorStatus enumeration value:
418 * - SUCCESS: TIMx output channel is initialized
419 * - ERROR: TIMx output channel is not initialized
420 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)421 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
422 {
423 ErrorStatus result = ERROR;
424
425 switch (Channel)
426 {
427 case LL_TIM_CHANNEL_CH1:
428 result = OC1Config(TIMx, TIM_OC_InitStruct);
429 break;
430 case LL_TIM_CHANNEL_CH2:
431 result = OC2Config(TIMx, TIM_OC_InitStruct);
432 break;
433 case LL_TIM_CHANNEL_CH3:
434 result = OC3Config(TIMx, TIM_OC_InitStruct);
435 break;
436 case LL_TIM_CHANNEL_CH4:
437 result = OC4Config(TIMx, TIM_OC_InitStruct);
438 break;
439 case LL_TIM_CHANNEL_CH5:
440 result = OC5Config(TIMx, TIM_OC_InitStruct);
441 break;
442 case LL_TIM_CHANNEL_CH6:
443 result = OC6Config(TIMx, TIM_OC_InitStruct);
444 break;
445 default:
446 break;
447 }
448
449 return result;
450 }
451
452 /**
453 * @brief Set the fields of the TIMx input channel configuration data
454 * structure to their default values.
455 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
456 * data structure)
457 * @retval None
458 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)459 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
460 {
461 /* Set the default configuration */
462 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
463 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
464 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
465 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
466 }
467
468 /**
469 * @brief Configure the TIMx input channel.
470 * @param TIMx Timer Instance
471 * @param Channel This parameter can be one of the following values:
472 * @arg @ref LL_TIM_CHANNEL_CH1
473 * @arg @ref LL_TIM_CHANNEL_CH2
474 * @arg @ref LL_TIM_CHANNEL_CH3
475 * @arg @ref LL_TIM_CHANNEL_CH4
476 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
477 * structure)
478 * @retval An ErrorStatus enumeration value:
479 * - SUCCESS: TIMx output channel is initialized
480 * - ERROR: TIMx output channel is not initialized
481 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)482 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
483 {
484 ErrorStatus result = ERROR;
485
486 switch (Channel)
487 {
488 case LL_TIM_CHANNEL_CH1:
489 result = IC1Config(TIMx, TIM_IC_InitStruct);
490 break;
491 case LL_TIM_CHANNEL_CH2:
492 result = IC2Config(TIMx, TIM_IC_InitStruct);
493 break;
494 case LL_TIM_CHANNEL_CH3:
495 result = IC3Config(TIMx, TIM_IC_InitStruct);
496 break;
497 case LL_TIM_CHANNEL_CH4:
498 result = IC4Config(TIMx, TIM_IC_InitStruct);
499 break;
500 default:
501 break;
502 }
503
504 return result;
505 }
506
507 /**
508 * @brief Fills each TIM_EncoderInitStruct field with its default value
509 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
510 * configuration data structure)
511 * @retval None
512 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)513 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
514 {
515 /* Set the default configuration */
516 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
517 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
518 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
519 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
520 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
521 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
522 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
523 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
524 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
525 }
526
527 /**
528 * @brief Configure the encoder interface of the timer instance.
529 * @param TIMx Timer Instance
530 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
531 * configuration data structure)
532 * @retval An ErrorStatus enumeration value:
533 * - SUCCESS: TIMx registers are de-initialized
534 * - ERROR: not applicable
535 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)536 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
537 {
538 uint32_t tmpccmr1;
539 uint32_t tmpccer;
540
541 /* Check the parameters */
542 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
543 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
544 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
545 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
546 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
547 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
548 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
549 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
550 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
551 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
552
553 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
554 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
555
556 /* Get the TIMx CCMR1 register value */
557 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
558
559 /* Get the TIMx CCER register value */
560 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
561
562 /* Configure TI1 */
563 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
564 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
565 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
566 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
567
568 /* Configure TI2 */
569 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
570 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
571 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
572 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
573
574 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
575 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
576 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
577 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
578 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
579
580 /* Set encoder mode */
581 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
582
583 /* Write to TIMx CCMR1 */
584 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
585
586 /* Write to TIMx CCER */
587 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
588
589 return SUCCESS;
590 }
591
592 /**
593 * @brief Set the fields of the TIMx Hall sensor interface configuration data
594 * structure to their default values.
595 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
596 * configuration data structure)
597 * @retval None
598 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)599 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
600 {
601 /* Set the default configuration */
602 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
603 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
604 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
605 TIM_HallSensorInitStruct->CommutationDelay = 0U;
606 }
607
608 /**
609 * @brief Configure the Hall sensor interface of the timer instance.
610 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
611 * to the TI1 input channel
612 * @note TIMx slave mode controller is configured in reset mode.
613 Selected internal trigger is TI1F_ED.
614 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
615 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
616 * between 2 changes on the inputs. It gives information about motor speed.
617 * @note Channel 2 is configured in output PWM 2 mode.
618 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
619 * @note OC2REF is selected as trigger output on TRGO.
620 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
621 * when TIMx operates in Hall sensor interface mode.
622 * @param TIMx Timer Instance
623 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
624 * interface configuration data structure)
625 * @retval An ErrorStatus enumeration value:
626 * - SUCCESS: TIMx registers are de-initialized
627 * - ERROR: not applicable
628 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)629 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
630 {
631 uint32_t tmpcr2;
632 uint32_t tmpccmr1;
633 uint32_t tmpccer;
634 uint32_t tmpsmcr;
635
636 /* Check the parameters */
637 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
638 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
639 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
640 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
641
642 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
643 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
644
645 /* Get the TIMx CR2 register value */
646 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
647
648 /* Get the TIMx CCMR1 register value */
649 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
650
651 /* Get the TIMx CCER register value */
652 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
653
654 /* Get the TIMx SMCR register value */
655 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
656
657 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
658 tmpcr2 |= TIM_CR2_TI1S;
659
660 /* OC2REF signal is used as trigger output (TRGO) */
661 tmpcr2 |= LL_TIM_TRGO_OC2REF;
662
663 /* Configure the slave mode controller */
664 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
665 tmpsmcr |= LL_TIM_TS_TI1F_ED;
666 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
667
668 /* Configure input channel 1 */
669 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
670 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
671 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
672 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
673
674 /* Configure input channel 2 */
675 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
676 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
677
678 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
679 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
680 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
681 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
682
683 /* Write to TIMx CR2 */
684 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
685
686 /* Write to TIMx SMCR */
687 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
688
689 /* Write to TIMx CCMR1 */
690 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
691
692 /* Write to TIMx CCER */
693 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
694
695 /* Write to TIMx CCR2 */
696 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
697
698 return SUCCESS;
699 }
700
701 /**
702 * @brief Set the fields of the Break and Dead Time configuration data structure
703 * to their default values.
704 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
705 * data structure)
706 * @retval None
707 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)708 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
709 {
710 /* Set the default configuration */
711 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
712 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
713 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
714 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
715 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
716 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
717 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
718 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
719 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
720 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
721 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
722 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
723 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
724 }
725
726 /**
727 * @brief Configure the Break and Dead Time feature of the timer instance.
728 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
729 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
730 * can be necessary to configure all of them during the first write access to
731 * the TIMx_BDTR register.
732 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
733 * a timer instance provides a break input.
734 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
735 * a timer instance provides a second break input.
736 * @param TIMx Timer Instance
737 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
738 * data structure)
739 * @retval An ErrorStatus enumeration value:
740 * - SUCCESS: Break and Dead Time is initialized
741 * - ERROR: not applicable
742 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)743 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
744 {
745 uint32_t tmpbdtr = 0;
746
747 /* Check the parameters */
748 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
749 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
750 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
751 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
752 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
753 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
754 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
755 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
756 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
757
758 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
759 the OSSI State, the dead time value and the Automatic Output Enable Bit */
760
761 /* Set the BDTR bits */
762 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
763 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
764 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
765 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
766 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
767 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
768 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
769 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
770 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
771
772 if (IS_TIM_BKIN2_INSTANCE(TIMx))
773 {
774 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
775 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
776 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
777 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
778
779 /* Set the BREAK2 input related BDTR bit-fields */
780 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
781 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
782 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
783 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
784 }
785
786 /* Set TIMx_BDTR */
787 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
788
789 return SUCCESS;
790 }
791 /**
792 * @}
793 */
794
795 /**
796 * @}
797 */
798
799 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
800 * @brief Private functions
801 * @{
802 */
803 /**
804 * @brief Configure the TIMx output channel 1.
805 * @param TIMx Timer Instance
806 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
807 * @retval An ErrorStatus enumeration value:
808 * - SUCCESS: TIMx registers are de-initialized
809 * - ERROR: not applicable
810 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)811 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
812 {
813 uint32_t tmpccmr1;
814 uint32_t tmpccer;
815 uint32_t tmpcr2;
816
817 /* Check the parameters */
818 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
819 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
820 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
821 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
822
823 /* Disable the Channel 1: Reset the CC1E Bit */
824 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
825
826 /* Get the TIMx CCER register value */
827 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
828
829 /* Get the TIMx CR2 register value */
830 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
831
832 /* Get the TIMx CCMR1 register value */
833 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
834
835 /* Reset Capture/Compare selection Bits */
836 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
837
838 /* Set the Output Compare Mode */
839 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
840
841 /* Set the Output Compare Polarity */
842 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
843
844 /* Set the Output State */
845 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
846
847 if (IS_TIM_BREAK_INSTANCE(TIMx))
848 {
849 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
850 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
851 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
852 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
853
854 /* Set the complementary output Polarity */
855 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
856
857 /* Set the complementary output State */
858 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
859
860 /* Set the Output Idle state */
861 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
862
863 /* Set the complementary output Idle state */
864 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
865 }
866
867 /* Write to TIMx CR2 */
868 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
869
870 /* Write to TIMx CCMR1 */
871 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
872
873 /* Set the Capture Compare Register value */
874 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
875
876 /* Write to TIMx CCER */
877 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
878
879 return SUCCESS;
880 }
881
882 /**
883 * @brief Configure the TIMx output channel 2.
884 * @param TIMx Timer Instance
885 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
886 * @retval An ErrorStatus enumeration value:
887 * - SUCCESS: TIMx registers are de-initialized
888 * - ERROR: not applicable
889 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)890 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
891 {
892 uint32_t tmpccmr1;
893 uint32_t tmpccer;
894 uint32_t tmpcr2;
895
896 /* Check the parameters */
897 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
898 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
899 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
900 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
901
902 /* Disable the Channel 2: Reset the CC2E Bit */
903 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
904
905 /* Get the TIMx CCER register value */
906 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
907
908 /* Get the TIMx CR2 register value */
909 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
910
911 /* Get the TIMx CCMR1 register value */
912 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
913
914 /* Reset Capture/Compare selection Bits */
915 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
916
917 /* Select the Output Compare Mode */
918 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
919
920 /* Set the Output Compare Polarity */
921 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
922
923 /* Set the Output State */
924 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
925
926 if (IS_TIM_BREAK_INSTANCE(TIMx))
927 {
928 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
929 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
930 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
931 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
932
933 /* Set the complementary output Polarity */
934 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
935
936 /* Set the complementary output State */
937 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
938
939 /* Set the Output Idle state */
940 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
941
942 /* Set the complementary output Idle state */
943 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
944 }
945
946 /* Write to TIMx CR2 */
947 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
948
949 /* Write to TIMx CCMR1 */
950 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
951
952 /* Set the Capture Compare Register value */
953 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
954
955 /* Write to TIMx CCER */
956 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
957
958 return SUCCESS;
959 }
960
961 /**
962 * @brief Configure the TIMx output channel 3.
963 * @param TIMx Timer Instance
964 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
965 * @retval An ErrorStatus enumeration value:
966 * - SUCCESS: TIMx registers are de-initialized
967 * - ERROR: not applicable
968 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)969 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
970 {
971 uint32_t tmpccmr2;
972 uint32_t tmpccer;
973 uint32_t tmpcr2;
974
975 /* Check the parameters */
976 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
977 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
978 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
979 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
980
981 /* Disable the Channel 3: Reset the CC3E Bit */
982 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
983
984 /* Get the TIMx CCER register value */
985 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
986
987 /* Get the TIMx CR2 register value */
988 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
989
990 /* Get the TIMx CCMR2 register value */
991 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
992
993 /* Reset Capture/Compare selection Bits */
994 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
995
996 /* Select the Output Compare Mode */
997 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
998
999 /* Set the Output Compare Polarity */
1000 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1001
1002 /* Set the Output State */
1003 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1004
1005 if (IS_TIM_BREAK_INSTANCE(TIMx))
1006 {
1007 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1008 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1009 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1010 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1011
1012 /* Set the complementary output Polarity */
1013 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1014
1015 /* Set the complementary output State */
1016 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1017
1018 /* Set the Output Idle state */
1019 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1020
1021 /* Set the complementary output Idle state */
1022 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1023 }
1024
1025 /* Write to TIMx CR2 */
1026 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1027
1028 /* Write to TIMx CCMR2 */
1029 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1030
1031 /* Set the Capture Compare Register value */
1032 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1033
1034 /* Write to TIMx CCER */
1035 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1036
1037 return SUCCESS;
1038 }
1039
1040 /**
1041 * @brief Configure the TIMx output channel 4.
1042 * @param TIMx Timer Instance
1043 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1044 * @retval An ErrorStatus enumeration value:
1045 * - SUCCESS: TIMx registers are de-initialized
1046 * - ERROR: not applicable
1047 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1048 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1049 {
1050 uint32_t tmpccmr2;
1051 uint32_t tmpccer;
1052 uint32_t tmpcr2;
1053
1054 /* Check the parameters */
1055 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1056 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1057 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1058 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1059
1060 /* Disable the Channel 4: Reset the CC4E Bit */
1061 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1062
1063 /* Get the TIMx CCER register value */
1064 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1065
1066 /* Get the TIMx CR2 register value */
1067 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1068
1069 /* Get the TIMx CCMR2 register value */
1070 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1071
1072 /* Reset Capture/Compare selection Bits */
1073 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1074
1075 /* Select the Output Compare Mode */
1076 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1077
1078 /* Set the Output Compare Polarity */
1079 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1080
1081 /* Set the Output State */
1082 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1083
1084 if (IS_TIM_BREAK_INSTANCE(TIMx))
1085 {
1086 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1087 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1088 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1089 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1090
1091 /* Set the complementary output Polarity */
1092 MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
1093
1094 /* Set the complementary output State */
1095 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
1096
1097 /* Set the Output Idle state */
1098 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1099
1100 /* Set the complementary output Idle state */
1101 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
1102 }
1103
1104 /* Write to TIMx CR2 */
1105 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1106
1107 /* Write to TIMx CCMR2 */
1108 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1109
1110 /* Set the Capture Compare Register value */
1111 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1112
1113 /* Write to TIMx CCER */
1114 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1115
1116 return SUCCESS;
1117 }
1118
1119 /**
1120 * @brief Configure the TIMx output channel 5.
1121 * @param TIMx Timer Instance
1122 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1123 * @retval An ErrorStatus enumeration value:
1124 * - SUCCESS: TIMx registers are de-initialized
1125 * - ERROR: not applicable
1126 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1127 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1128 {
1129 uint32_t tmpccmr3;
1130 uint32_t tmpccer;
1131
1132 /* Check the parameters */
1133 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1134 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1135 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1136 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1137 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1138 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1139
1140 /* Disable the Channel 5: Reset the CC5E Bit */
1141 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1142
1143 /* Get the TIMx CCER register value */
1144 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1145
1146 /* Get the TIMx CCMR3 register value */
1147 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1148
1149 /* Select the Output Compare Mode */
1150 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1151
1152 /* Set the Output Compare Polarity */
1153 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1154
1155 /* Set the Output State */
1156 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1157
1158 if (IS_TIM_BREAK_INSTANCE(TIMx))
1159 {
1160 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1161 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1162
1163 /* Set the Output Idle state */
1164 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1165
1166 }
1167
1168 /* Write to TIMx CCMR3 */
1169 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1170
1171 /* Set the Capture Compare Register value */
1172 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1173
1174 /* Write to TIMx CCER */
1175 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1176
1177 return SUCCESS;
1178 }
1179
1180 /**
1181 * @brief Configure the TIMx output channel 6.
1182 * @param TIMx Timer Instance
1183 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1184 * @retval An ErrorStatus enumeration value:
1185 * - SUCCESS: TIMx registers are de-initialized
1186 * - ERROR: not applicable
1187 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1188 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1189 {
1190 uint32_t tmpccmr3;
1191 uint32_t tmpccer;
1192
1193 /* Check the parameters */
1194 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1195 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1196 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1197 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1198 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1199 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1200
1201 /* Disable the Channel 5: Reset the CC6E Bit */
1202 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1203
1204 /* Get the TIMx CCER register value */
1205 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1206
1207 /* Get the TIMx CCMR3 register value */
1208 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1209
1210 /* Select the Output Compare Mode */
1211 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1212
1213 /* Set the Output Compare Polarity */
1214 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1215
1216 /* Set the Output State */
1217 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1218
1219 if (IS_TIM_BREAK_INSTANCE(TIMx))
1220 {
1221 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1222 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1223
1224 /* Set the Output Idle state */
1225 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1226 }
1227
1228 /* Write to TIMx CCMR3 */
1229 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1230
1231 /* Set the Capture Compare Register value */
1232 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1233
1234 /* Write to TIMx CCER */
1235 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1236
1237 return SUCCESS;
1238 }
1239
1240 /**
1241 * @brief Configure the TIMx input channel 1.
1242 * @param TIMx Timer Instance
1243 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1244 * @retval An ErrorStatus enumeration value:
1245 * - SUCCESS: TIMx registers are de-initialized
1246 * - ERROR: not applicable
1247 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1248 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1249 {
1250 /* Check the parameters */
1251 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1252 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1253 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1254 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1255 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1256
1257 /* Disable the Channel 1: Reset the CC1E Bit */
1258 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1259
1260 /* Select the Input and set the filter and the prescaler value */
1261 MODIFY_REG(TIMx->CCMR1,
1262 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1263 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1264
1265 /* Select the Polarity and set the CC1E Bit */
1266 MODIFY_REG(TIMx->CCER,
1267 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1268 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1269
1270 return SUCCESS;
1271 }
1272
1273 /**
1274 * @brief Configure the TIMx input channel 2.
1275 * @param TIMx Timer Instance
1276 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1277 * @retval An ErrorStatus enumeration value:
1278 * - SUCCESS: TIMx registers are de-initialized
1279 * - ERROR: not applicable
1280 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1281 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1282 {
1283 /* Check the parameters */
1284 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1285 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1286 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1287 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1288 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1289
1290 /* Disable the Channel 2: Reset the CC2E Bit */
1291 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1292
1293 /* Select the Input and set the filter and the prescaler value */
1294 MODIFY_REG(TIMx->CCMR1,
1295 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1296 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1297
1298 /* Select the Polarity and set the CC2E Bit */
1299 MODIFY_REG(TIMx->CCER,
1300 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1301 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1302
1303 return SUCCESS;
1304 }
1305
1306 /**
1307 * @brief Configure the TIMx input channel 3.
1308 * @param TIMx Timer Instance
1309 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1310 * @retval An ErrorStatus enumeration value:
1311 * - SUCCESS: TIMx registers are de-initialized
1312 * - ERROR: not applicable
1313 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1314 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1315 {
1316 /* Check the parameters */
1317 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1318 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1319 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1320 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1321 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1322
1323 /* Disable the Channel 3: Reset the CC3E Bit */
1324 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1325
1326 /* Select the Input and set the filter and the prescaler value */
1327 MODIFY_REG(TIMx->CCMR2,
1328 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1329 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1330
1331 /* Select the Polarity and set the CC3E Bit */
1332 MODIFY_REG(TIMx->CCER,
1333 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1334 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1335
1336 return SUCCESS;
1337 }
1338
1339 /**
1340 * @brief Configure the TIMx input channel 4.
1341 * @param TIMx Timer Instance
1342 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1343 * @retval An ErrorStatus enumeration value:
1344 * - SUCCESS: TIMx registers are de-initialized
1345 * - ERROR: not applicable
1346 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1347 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1348 {
1349 /* Check the parameters */
1350 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1351 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1352 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1353 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1354 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1355
1356 /* Disable the Channel 4: Reset the CC4E Bit */
1357 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1358
1359 /* Select the Input and set the filter and the prescaler value */
1360 MODIFY_REG(TIMx->CCMR2,
1361 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1362 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1363
1364 /* Select the Polarity and set the CC4E Bit */
1365 MODIFY_REG(TIMx->CCER,
1366 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1367 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1368
1369 return SUCCESS;
1370 }
1371
1372
1373 /**
1374 * @}
1375 */
1376
1377 /**
1378 * @}
1379 */
1380
1381 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM9 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
1382
1383 /**
1384 * @}
1385 */
1386
1387 #endif /* USE_FULL_LL_DRIVER */
1388
