1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) API to access to MCU info (CPUID register)
28 (+) API to enable fault handler (SHCSR accesses)
29 (+) API to enable and disable the MPU
30 (+) API to configure the region of MPU
31 (+) API to configure the attributes region of MPU
32
33 @endverbatim
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32H7RSxx_LL_CORTEX_H
38 #define STM32H7RSxx_LL_CORTEX_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32h7rsxx.h"
46
47 /** @addtogroup STM32H7RSxx_LL_Driver
48 * @{
49 */
50
51 /** @defgroup CORTEX_LL CORTEX
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57 /* Private constants ---------------------------------------------------------*/
58 /* Private macros ------------------------------------------------------------*/
59 /* Exported types ------------------------------------------------------------*/
60 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
62 * @{
63 */
64
65 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK CORTEX LL SYSTICK Clock Source
66 * @{
67 */
68 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0U /*!< AHB clock divided by 8 selected as SysTick
69 clock source */
70 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
71 clock source */
72 /**
73 * @}
74 */
75
76 /** @defgroup CORTEX_LL_EC_FAULT CORTEX LL Handler Fault type
77 * @{
78 */
79 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
80 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
81 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
82 /**
83 * @}
84 */
85
86 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF CORTEX LL MPU HFNMI and PRIVILEGED Access control
87 * @{
88 */
89 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Disable NMI and privileged SW access */
90 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
91 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
92 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
93 /**
94 * @}
95 */
96
97 /** @defgroup CORTEX_LL_EC_REGION CORTEX LL MPU Region Number
98 * @{
99 */
100 #define LL_MPU_REGION_NUMBER0 0U /*!< REGION Number 0 */
101 #define LL_MPU_REGION_NUMBER1 1U /*!< REGION Number 1 */
102 #define LL_MPU_REGION_NUMBER2 2U /*!< REGION Number 2 */
103 #define LL_MPU_REGION_NUMBER3 3U /*!< REGION Number 3 */
104 #define LL_MPU_REGION_NUMBER4 4U /*!< REGION Number 4 */
105 #define LL_MPU_REGION_NUMBER5 5U /*!< REGION Number 5 */
106 #define LL_MPU_REGION_NUMBER6 6U /*!< REGION Number 6 */
107 #define LL_MPU_REGION_NUMBER7 7U /*!< REGION Number 7 */
108 #define LL_MPU_REGION_NUMBER8 8U /*!< REGION Number 8 */
109 #define LL_MPU_REGION_NUMBER9 9U /*!< REGION Number 9 */
110 #define LL_MPU_REGION_NUMBER10 10U /*!< REGION Number 10 */
111 #define LL_MPU_REGION_NUMBER11 11U /*!< REGION Number 11 */
112 #define LL_MPU_REGION_NUMBER12 12U /*!< REGION Number 12 */
113 #define LL_MPU_REGION_NUMBER13 13U /*!< REGION Number 13 */
114 #define LL_MPU_REGION_NUMBER14 14U /*!< REGION Number 14 */
115 #define LL_MPU_REGION_NUMBER15 15U /*!< REGION Number 15 */
116 /**
117 * @}
118 */
119
120 /** @defgroup CORTEX_LL_EC_REGION_SIZE CORTEX LL MPU Region Size
121 * @{
122 */
123 #define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
124 #define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
125 #define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
126 #define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
130 #define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
131 #define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
132 #define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
133 #define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
134 #define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
135 #define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
136 #define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
137 #define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
138 #define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
139 #define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
140 #define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
141 #define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
142 #define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
143 #define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
144 #define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
145 #define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
146 #define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
147 #define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
148 #define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
149 #define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
150 #define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
151 /**
152 * @}
153 */
154
155 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES CORTEX LL MPU Region Privileges
156 * @{
157 */
158 #define LL_MPU_REGION_NO_ACCESS (0U << MPU_RASR_AP_Pos) /*!< No access*/
159 #define LL_MPU_REGION_PRIV_RW (1U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
160 #define LL_MPU_REGION_PRIV_RW_URO (2U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
161 #define LL_MPU_REGION_FULL_ACCESS (3U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
162 #define LL_MPU_REGION_PRIV_RO (5U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
163 #define LL_MPU_REGION_PRIV_RO_URO (6U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
164 /**
165 * @}
166 */
167
168 /** @defgroup CORTEX_LL_EC_TEX CORTEX LL MPU TEX Level
169 * @{
170 */
171 #define LL_MPU_TEX_LEVEL0 (0U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
172 #define LL_MPU_TEX_LEVEL1 (1U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
173 #define LL_MPU_TEX_LEVEL2 (2U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
174 #define LL_MPU_TEX_LEVEL4 (4U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
175 /**
176 * @}
177 */
178
179 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS CORTEX LL MPU Instruction Access
180 * @{
181 */
182 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Instruction fetches enabled */
183 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
184 /**
185 * @}
186 */
187
188 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS CORTEX LL MPU Shareable Access
189 * @{
190 */
191 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
192 #define LL_MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not Shareable memory attribute */
193 /**
194 * @}
195 */
196
197 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS CORTEX LL MPU Cacheable Access
198 * @{
199 */
200 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
201 #define LL_MPU_ACCESS_NOT_CACHEABLE 0U /*!< Not Cacheable memory attribute */
202 /**
203 * @}
204 */
205
206 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS CORTEX LL MPU Bufferable Access
207 * @{
208 */
209 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
210 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0U /*!< Not Bufferable memory attribute */
211 /**
212 * @}
213 */
214 /**
215 * @}
216 */
217
218 /* Exported macro ------------------------------------------------------------*/
219
220 /* Exported functions --------------------------------------------------------*/
221 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
222 * @{
223 */
224
225 /** @defgroup CORTEX_LL_EF_SYSTICK CORTEX LL SYSTICK
226 * @brief CORTEX SYSTICK LL module driver
227 * @{
228 */
229
230 /**
231 * @brief This function checks if the Systick counter flag is active or not.
232 * @note It can be used in timeout function on application side.
233 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
234 * @retval State of bit (1 or 0).
235 */
LL_SYSTICK_IsActiveCounterFlag(void)236 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
237 {
238 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
239 }
240
241 /**
242 * @brief Configures the SysTick clock source
243 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
244 * @param Source This parameter can be one of the following values:
245 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
246 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
247 * @retval None
248 */
LL_SYSTICK_SetClkSource(uint32_t Source)249 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
250 {
251 MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
252 }
253
254 /**
255 * @brief Get the SysTick clock source
256 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
257 * @retval Returned value can be one of the following values:
258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
259 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
260 */
LL_SYSTICK_GetClkSource(void)261 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
262 {
263 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
264 }
265
266 /**
267 * @brief Enable SysTick exception request
268 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
269 * @retval None
270 */
LL_SYSTICK_EnableIT(void)271 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
272 {
273 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
274 }
275
276 /**
277 * @brief Disable SysTick exception request
278 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
279 * @retval None
280 */
LL_SYSTICK_DisableIT(void)281 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
282 {
283 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
284 }
285
286 /**
287 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
288 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
289 * @retval State of bit (1 or 0).
290 */
LL_SYSTICK_IsEnabledIT(void)291 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
292 {
293 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
294 }
295
296 /**
297 * @}
298 */
299
300 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
301 * @{
302 */
303
304 /**
305 * @brief Processor uses sleep as its low power mode
306 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
307 * @retval None
308 */
LL_LPM_EnableSleep(void)309 __STATIC_INLINE void LL_LPM_EnableSleep(void)
310 {
311 /* Clear SLEEPDEEP bit of Cortex System Control Register */
312 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
313 }
314
315 /**
316 * @brief Processor uses deep sleep as its low power mode
317 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
318 * @retval None
319 */
LL_LPM_EnableDeepSleep(void)320 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
321 {
322 /* Set SLEEPDEEP bit of Cortex System Control Register */
323 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
324 }
325
326 /**
327 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
328 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
329 * empty main application.
330 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
331 * @retval None
332 */
LL_LPM_EnableSleepOnExit(void)333 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
334 {
335 /* Set SLEEPONEXIT bit of Cortex System Control Register */
336 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
337 }
338
339 /**
340 * @brief Do not sleep when returning to Thread mode.
341 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
342 * @retval None
343 */
LL_LPM_DisableSleepOnExit(void)344 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
345 {
346 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
347 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
348 }
349
350 /**
351 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
352 * processor.
353 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
354 * @retval None
355 */
LL_LPM_EnableEventOnPend(void)356 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
357 {
358 /* Set SEVEONPEND bit of Cortex System Control Register */
359 SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
360 }
361
362 /**
363 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
364 * excluded
365 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
366 * @retval None
367 */
LL_LPM_DisableEventOnPend(void)368 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
369 {
370 /* Clear SEVEONPEND bit of Cortex System Control Register */
371 CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
372 }
373
374 /**
375 * @brief Clear pending events.
376 * @retval None
377 */
LL_LPM_ClearEvent(void)378 __STATIC_INLINE void LL_LPM_ClearEvent(void)
379 {
380 __SEV();
381 __WFE();
382 }
383 /**
384 * @}
385 */
386
387 /** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
388 * @{
389 */
390
391 /**
392 * @brief Enable a fault in System handler control register (SHCSR)
393 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
394 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
395 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
396 * @param Fault This parameter can be a combination of the following values:
397 * @arg @ref LL_HANDLER_FAULT_USG
398 * @arg @ref LL_HANDLER_FAULT_BUS
399 * @arg @ref LL_HANDLER_FAULT_MEM
400 * @retval None
401 */
LL_HANDLER_EnableFault(uint32_t Fault)402 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
403 {
404 /* Enable the system handler fault */
405 SET_BIT(SCB->SHCSR, Fault);
406 }
407
408 /**
409 * @brief Disable a fault in System handler control register (SHCSR)
410 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
411 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
412 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
413 * @param Fault This parameter can be a combination of the following values:
414 * @arg @ref LL_HANDLER_FAULT_USG
415 * @arg @ref LL_HANDLER_FAULT_BUS
416 * @arg @ref LL_HANDLER_FAULT_MEM
417 * @retval None
418 */
LL_HANDLER_DisableFault(uint32_t Fault)419 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
420 {
421 /* Disable the system handler fault */
422 CLEAR_BIT(SCB->SHCSR, Fault);
423 }
424
425 /**
426 * @}
427 */
428
429 /** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
430 * @{
431 */
432
433 /**
434 * @brief Get Implementer code
435 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
436 * @retval Value should be equal to 0x41 for ARM
437 */
LL_CPUID_GetImplementer(void)438 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
439 {
440 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
441 }
442
443 /**
444 * @brief Get Variant number (The r value in the rnpn product revision identifier)
445 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
446 * @retval Value between 0 and 255 (0x0: revision 0)
447 */
LL_CPUID_GetVariant(void)448 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
449 {
450 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
451 }
452
453 /**
454 * @brief Get Architecture version
455 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
456 * @retval Value should be equal to 0xF for Cortex-M7
457 */
LL_CPUID_GetArchitecture(void)458 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
459 {
460 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
461 }
462
463 /**
464 * @brief Get Part number
465 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
466 * @retval Value should be equal to 0xC27 for Cortex-M7
467 */
LL_CPUID_GetParNo(void)468 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
469 {
470 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
471 }
472
473 /**
474 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
475 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
476 * @retval Value between 0 and 255 (0x1: patch 1)
477 */
LL_CPUID_GetRevision(void)478 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
479 {
480 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
481 }
482
483 /**
484 * @}
485 */
486
487 /** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
488 * @{
489 */
490
491 /**
492 * @brief Enable MPU with input options
493 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
494 * @param MPU_Control This parameter can be one of the following values:
495 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
496 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
497 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
498 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
499 * @retval None
500 */
LL_MPU_Enable(uint32_t MPU_Control)501 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
502 {
503 __DMB(); /* Force any outstanding transfers to complete before enabling MPU */
504
505 /* Enable the MPU*/
506 WRITE_REG(MPU->CTRL, (MPU_Control | MPU_CTRL_ENABLE_Msk));
507
508 /* Ensure MPU settings take effects */
509 __DSB();
510 __ISB();
511 }
512
513 /**
514 * @brief Disable MPU
515 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
516 * @retval None
517 */
LL_MPU_Disable(void)518 __STATIC_INLINE void LL_MPU_Disable(void)
519 {
520 /* Make sure outstanding transfers are done */
521 __DMB();
522
523 /* Disable the MPU and clear the control register */
524 WRITE_REG(MPU->CTRL, 0U);
525 }
526
527 /**
528 * @brief Check if MPU is enabled or not
529 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
530 * @retval State of bit (1 or 0).
531 */
LL_MPU_IsEnabled(void)532 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
533 {
534 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
535 }
536
537 /**
538 * @brief Enable a MPU region
539 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
540 * @param Region This parameter can be one of the following values:
541 * @arg @ref LL_MPU_REGION_NUMBER0
542 * @arg @ref LL_MPU_REGION_NUMBER1
543 * @arg @ref LL_MPU_REGION_NUMBER2
544 * @arg @ref LL_MPU_REGION_NUMBER3
545 * @arg @ref LL_MPU_REGION_NUMBER4
546 * @arg @ref LL_MPU_REGION_NUMBER5
547 * @arg @ref LL_MPU_REGION_NUMBER6
548 * @arg @ref LL_MPU_REGION_NUMBER7
549 * @arg @ref LL_MPU_REGION_NUMBER8
550 * @arg @ref LL_MPU_REGION_NUMBER9
551 * @arg @ref LL_MPU_REGION_NUMBER10
552 * @arg @ref LL_MPU_REGION_NUMBER11
553 * @arg @ref LL_MPU_REGION_NUMBER12
554 * @arg @ref LL_MPU_REGION_NUMBER13
555 * @arg @ref LL_MPU_REGION_NUMBER14
556 * @arg @ref LL_MPU_REGION_NUMBER15
557 * @retval None
558 */
LL_MPU_EnableRegion(uint32_t Region)559 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
560 {
561 /* Set Region number */
562 WRITE_REG(MPU->RNR, Region);
563
564 /* Enable the MPU region */
565 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
566 }
567
568 /**
569 * @brief Check if MPU region is enabled or not
570 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region
571 * @param Region This parameter can be one of the following values:
572 * @arg @ref LL_MPU_REGION_NUMBER0
573 * @arg @ref LL_MPU_REGION_NUMBER1
574 * @arg @ref LL_MPU_REGION_NUMBER2
575 * @arg @ref LL_MPU_REGION_NUMBER3
576 * @arg @ref LL_MPU_REGION_NUMBER4
577 * @arg @ref LL_MPU_REGION_NUMBER5
578 * @arg @ref LL_MPU_REGION_NUMBER6
579 * @arg @ref LL_MPU_REGION_NUMBER7
580 * @arg @ref LL_MPU_REGION_NUMBER8
581 * @arg @ref LL_MPU_REGION_NUMBER9
582 * @arg @ref LL_MPU_REGION_NUMBER10
583 * @arg @ref LL_MPU_REGION_NUMBER11
584 * @arg @ref LL_MPU_REGION_NUMBER12
585 * @arg @ref LL_MPU_REGION_NUMBER13
586 * @arg @ref LL_MPU_REGION_NUMBER14
587 * @arg @ref LL_MPU_REGION_NUMBER15
588 * @retval State of bit (1 or 0).
589 */
LL_MPU_IsEnabled_Region(uint32_t Region)590 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
591 {
592 /* Set region index */
593 WRITE_REG(MPU->RNR, Region);
594
595 /* Return MPU region status */
596 return ((READ_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk) == (MPU_RASR_ENABLE_Msk)) ? 1UL : 0UL);
597 }
598
599 /**
600 * @brief Configure and enable a MPU region
601 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
602 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
603 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
604 * MPU_RASR XN LL_MPU_ConfigRegion\n
605 * MPU_RASR AP LL_MPU_ConfigRegion\n
606 * MPU_RASR S LL_MPU_ConfigRegion\n
607 * MPU_RASR C LL_MPU_ConfigRegion\n
608 * MPU_RASR B LL_MPU_ConfigRegion\n
609 * MPU_RASR SIZE LL_MPU_ConfigRegion
610 * @param Region This parameter can be one of the following values:
611 * @arg @ref LL_MPU_REGION_NUMBER0
612 * @arg @ref LL_MPU_REGION_NUMBER1
613 * @arg @ref LL_MPU_REGION_NUMBER2
614 * @arg @ref LL_MPU_REGION_NUMBER3
615 * @arg @ref LL_MPU_REGION_NUMBER4
616 * @arg @ref LL_MPU_REGION_NUMBER5
617 * @arg @ref LL_MPU_REGION_NUMBER6
618 * @arg @ref LL_MPU_REGION_NUMBER7
619 * @arg @ref LL_MPU_REGION_NUMBER8
620 * @arg @ref LL_MPU_REGION_NUMBER9
621 * @arg @ref LL_MPU_REGION_NUMBER10
622 * @arg @ref LL_MPU_REGION_NUMBER11
623 * @arg @ref LL_MPU_REGION_NUMBER12
624 * @arg @ref LL_MPU_REGION_NUMBER13
625 * @arg @ref LL_MPU_REGION_NUMBER14
626 * @arg @ref LL_MPU_REGION_NUMBER15
627 * @param Address Value of region base address
628 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
629 * @param Attributes This parameter can be a combination of the following values:
630 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B
631 * or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
632 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB
633 * or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
634 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB
635 * or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
636 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB
637 * or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
638 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB
639 * or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
640 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
641 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO
642 * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
643 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
644 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
645 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
646 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
647 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
648 * @retval None
649 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)650 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address,
651 uint32_t Attributes)
652 {
653 /* Set Region number */
654 WRITE_REG(MPU->RNR, Region);
655
656 /* Set base address */
657 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
658
659 /* Configure MPU */
660 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
661 }
662
663 /**
664 * @brief Disable a MPU region
665 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
666 * MPU_RASR ENABLE LL_MPU_DisableRegion
667 * @param Region This parameter can be one of the following values:
668 * @arg @ref LL_MPU_REGION_NUMBER0
669 * @arg @ref LL_MPU_REGION_NUMBER1
670 * @arg @ref LL_MPU_REGION_NUMBER2
671 * @arg @ref LL_MPU_REGION_NUMBER3
672 * @arg @ref LL_MPU_REGION_NUMBER4
673 * @arg @ref LL_MPU_REGION_NUMBER5
674 * @arg @ref LL_MPU_REGION_NUMBER6
675 * @arg @ref LL_MPU_REGION_NUMBER7
676 * @arg @ref LL_MPU_REGION_NUMBER8
677 * @arg @ref LL_MPU_REGION_NUMBER9
678 * @arg @ref LL_MPU_REGION_NUMBER10
679 * @arg @ref LL_MPU_REGION_NUMBER11
680 * @arg @ref LL_MPU_REGION_NUMBER12
681 * @arg @ref LL_MPU_REGION_NUMBER13
682 * @arg @ref LL_MPU_REGION_NUMBER14
683 * @arg @ref LL_MPU_REGION_NUMBER15
684 * @retval None
685 */
LL_MPU_DisableRegion(uint32_t Region)686 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
687 {
688 /* Set Region number */
689 WRITE_REG(MPU->RNR, Region);
690
691 /* Disable the MPU region */
692 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
693 }
694
695 /**
696 * @}
697 */
698
699 /**
700 * @}
701 */
702
703 /**
704 * @}
705 */
706
707 /**
708 * @}
709 */
710
711 #ifdef __cplusplus
712 }
713 #endif
714
715 #endif /* STM32H7RSxx_LL_CORTEX_H */
716
