1 /** 2 ****************************************************************************** 3 * @file stm32h7rsxx_hal_smbus.h 4 * @author MCD Application Team 5 * @brief Header file of SMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7RSxx_HAL_SMBUS_H 21 #define STM32H7RSxx_HAL_SMBUS_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7rsxx_hal_def.h" 29 30 /** @addtogroup STM32H7RSxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SMBUS 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types 40 * @{ 41 */ 42 43 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition 44 * @brief SMBUS Configuration Structure definition 45 * @{ 46 */ 47 typedef struct 48 { 49 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. 50 This parameter calculated by referring to SMBUS initialization section 51 in Reference manual */ 52 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 53 This parameter can be a value of @ref SMBUS_Analog_Filter */ 54 55 uint32_t OwnAddress1; /*!< Specifies the first device own address. 56 This parameter can be a 7-bit address. */ 57 58 uint32_t AddressingMode; /*!< Specifies addressing mode selected. 59 This parameter can be a value of @ref SMBUS_addressing_mode */ 60 61 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 62 This parameter can be a value of @ref SMBUS_dual_addressing_mode */ 63 64 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 65 This parameter can be a 7-bit address. */ 66 67 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address 68 if dual addressing mode is selected 69 This parameter can be a value of @ref SMBUS_own_address2_masks. */ 70 71 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 72 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ 73 74 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 75 This parameter can be a value of @ref SMBUS_nostretch_mode */ 76 77 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 78 This parameter can be a value of @ref SMBUS_packet_error_check_mode */ 79 80 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 81 This parameter can be a value of @ref SMBUS_peripheral_mode */ 82 83 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. 84 (Enable bits and different timeout values) 85 This parameter calculated by referring to SMBUS initialization section 86 in Reference manual */ 87 } SMBUS_InitTypeDef; 88 /** 89 * @} 90 */ 91 92 /** @defgroup HAL_state_definition HAL state definition 93 * @brief HAL State definition 94 * @{ 95 */ 96 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ 97 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ 98 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ 99 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 103 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 104 /** 105 * @} 106 */ 107 108 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition 109 * @brief SMBUS Error Code definition 110 * @{ 111 */ 112 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 113 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 114 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 115 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 116 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 117 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 118 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 119 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 120 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 121 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 122 #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 123 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 124 #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 125 /** 126 * @} 127 */ 128 129 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 130 * @brief SMBUS handle Structure definition 131 * @{ 132 */ 133 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 134 typedef struct __SMBUS_HandleTypeDef 135 #else 136 typedef struct 137 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 138 { 139 I2C_TypeDef *Instance; /*!< SMBUS registers base address */ 140 141 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ 142 143 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ 144 145 uint16_t XferSize; /*!< SMBUS transfer size */ 146 147 __IO uint16_t XferCount; /*!< SMBUS transfer counter */ 148 149 __IO uint32_t XferOptions; /*!< SMBUS transfer options */ 150 151 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ 152 153 HAL_LockTypeDef Lock; /*!< SMBUS locking object */ 154 155 __IO uint32_t State; /*!< SMBUS communication state */ 156 157 __IO uint32_t ErrorCode; /*!< SMBUS Error code */ 158 159 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 160 void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 161 /*!< SMBUS Master Tx Transfer completed callback */ 162 void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 163 /*!< SMBUS Master Rx Transfer completed callback */ 164 void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 165 /*!< SMBUS Slave Tx Transfer completed callback */ 166 void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 167 /*!< SMBUS Slave Rx Transfer completed callback */ 168 void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 169 /*!< SMBUS Listen Complete callback */ 170 void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 171 /*!< SMBUS Error callback */ 172 173 void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 174 /*!< SMBUS Slave Address Match callback */ 175 176 void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 177 /*!< SMBUS Msp Init callback */ 178 void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 179 /*!< SMBUS Msp DeInit callback */ 180 181 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 182 } SMBUS_HandleTypeDef; 183 184 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 185 /** 186 * @brief HAL SMBUS Callback ID enumeration definition 187 */ 188 typedef enum 189 { 190 HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ 191 HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ 192 HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ 193 HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ 194 HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ 195 HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ 196 197 HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ 198 HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ 199 200 } HAL_SMBUS_CallbackIDTypeDef; 201 202 /** 203 * @brief HAL SMBUS Callback pointer definition 204 */ 205 typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); 206 /*!< pointer to an SMBUS callback function */ 207 typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, 208 uint16_t AddrMatchCode); 209 /*!< pointer to an SMBUS Address Match callback function */ 210 211 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 212 /** 213 * @} 214 */ 215 216 /** 217 * @} 218 */ 219 /* Exported constants --------------------------------------------------------*/ 220 221 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants 222 * @{ 223 */ 224 225 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter 226 * @{ 227 */ 228 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) 229 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 230 /** 231 * @} 232 */ 233 234 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode 235 * @{ 236 */ 237 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 238 /** 239 * @} 240 */ 241 242 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode 243 * @{ 244 */ 245 246 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) 247 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 248 /** 249 * @} 250 */ 251 252 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks 253 * @{ 254 */ 255 256 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) 257 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) 258 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) 259 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) 260 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) 261 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) 262 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) 263 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) 264 /** 265 * @} 266 */ 267 268 269 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode 270 * @{ 271 */ 272 #define SMBUS_GENERALCALL_DISABLE (0x00000000U) 273 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN 274 /** 275 * @} 276 */ 277 278 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode 279 * @{ 280 */ 281 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) 282 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 283 /** 284 * @} 285 */ 286 287 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode 288 * @{ 289 */ 290 #define SMBUS_PEC_DISABLE (0x00000000U) 291 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN 292 /** 293 * @} 294 */ 295 296 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode 297 * @{ 298 */ 299 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN 300 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) 301 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN 302 /** 303 * @} 304 */ 305 306 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition 307 * @{ 308 */ 309 310 #define SMBUS_SOFTEND_MODE (0x00000000U) 311 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD 312 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND 313 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE 314 /** 315 * @} 316 */ 317 318 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition 319 * @{ 320 */ 321 322 #define SMBUS_NO_STARTSTOP (0x00000000U) 323 #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) 324 #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 325 #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 326 /** 327 * @} 328 */ 329 330 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition 331 * @{ 332 */ 333 334 /* List of XferOptions in usage of : 335 * 1- Restart condition when direction change 336 * 2- No Restart condition in other use cases 337 */ 338 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE 339 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) 340 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 341 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 342 #define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) 343 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 344 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 345 346 /* List of XferOptions in usage of : 347 * 1- Restart condition in all use cases (direction change or not) 348 */ 349 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 350 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 351 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 352 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 353 /** 354 * @} 355 */ 356 357 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition 358 * @brief SMBUS Interrupt definition 359 * Elements values convention: 0xXXXXXXXX 360 * - XXXXXXXX : Interrupt control mask 361 * @{ 362 */ 363 #define SMBUS_IT_ERRI I2C_CR1_ERRIE 364 #define SMBUS_IT_TCI I2C_CR1_TCIE 365 #define SMBUS_IT_STOPI I2C_CR1_STOPIE 366 #define SMBUS_IT_NACKI I2C_CR1_NACKIE 367 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE 368 #define SMBUS_IT_RXI I2C_CR1_RXIE 369 #define SMBUS_IT_TXI I2C_CR1_TXIE 370 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ 371 SMBUS_IT_NACKI | SMBUS_IT_TXI) 372 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ 373 SMBUS_IT_RXI) 374 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) 375 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) 376 /** 377 * @} 378 */ 379 380 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition 381 * @brief Flag definition 382 * Elements values convention: 0xXXXXYYYY 383 * - XXXXXXXX : Flag mask 384 * @{ 385 */ 386 387 #define SMBUS_FLAG_TXE I2C_ISR_TXE 388 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS 389 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE 390 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR 391 #define SMBUS_FLAG_AF I2C_ISR_NACKF 392 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF 393 #define SMBUS_FLAG_TC I2C_ISR_TC 394 #define SMBUS_FLAG_TCR I2C_ISR_TCR 395 #define SMBUS_FLAG_BERR I2C_ISR_BERR 396 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO 397 #define SMBUS_FLAG_OVR I2C_ISR_OVR 398 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR 399 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT 400 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT 401 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY 402 #define SMBUS_FLAG_DIR I2C_ISR_DIR 403 /** 404 * @} 405 */ 406 407 /** 408 * @} 409 */ 410 411 /* Exported macros ------------------------------------------------------------*/ 412 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros 413 * @{ 414 */ 415 416 /** @brief Reset SMBUS handle state. 417 * @param __HANDLE__ specifies the SMBUS Handle. 418 * @retval None 419 */ 420 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 421 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 422 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ 423 (__HANDLE__)->MspInitCallback = NULL; \ 424 (__HANDLE__)->MspDeInitCallback = NULL; \ 425 } while(0) 426 #else 427 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) 428 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 429 430 /** @brief Enable the specified SMBUS interrupts. 431 * @param __HANDLE__ specifies the SMBUS Handle. 432 * @param __INTERRUPT__ specifies the interrupt source to enable. 433 * This parameter can be one of the following values: 434 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 435 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 436 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 437 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 438 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 439 * @arg @ref SMBUS_IT_RXI RX interrupt enable 440 * @arg @ref SMBUS_IT_TXI TX interrupt enable 441 * 442 * @retval None 443 */ 444 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 445 446 /** @brief Disable the specified SMBUS interrupts. 447 * @param __HANDLE__ specifies the SMBUS Handle. 448 * @param __INTERRUPT__ specifies the interrupt source to disable. 449 * This parameter can be one of the following values: 450 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 451 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 452 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 453 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 454 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 455 * @arg @ref SMBUS_IT_RXI RX interrupt enable 456 * @arg @ref SMBUS_IT_TXI TX interrupt enable 457 * 458 * @retval None 459 */ 460 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 461 462 /** @brief Check whether the specified SMBUS interrupt source is enabled or not. 463 * @param __HANDLE__ specifies the SMBUS Handle. 464 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. 465 * This parameter can be one of the following values: 466 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 467 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 468 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 469 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 470 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 471 * @arg @ref SMBUS_IT_RXI RX interrupt enable 472 * @arg @ref SMBUS_IT_TXI TX interrupt enable 473 * 474 * @retval The new state of __IT__ (SET or RESET). 475 */ 476 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 477 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 478 479 /** @brief Check whether the specified SMBUS flag is set or not. 480 * @param __HANDLE__ specifies the SMBUS Handle. 481 * @param __FLAG__ specifies the flag to check. 482 * This parameter can be one of the following values: 483 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 484 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status 485 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty 486 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 487 * @arg @ref SMBUS_FLAG_AF NACK received flag 488 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 489 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) 490 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload 491 * @arg @ref SMBUS_FLAG_BERR Bus error 492 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 493 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 494 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 495 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 496 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 497 * @arg @ref SMBUS_FLAG_BUSY Bus busy 498 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) 499 * 500 * @retval The new state of __FLAG__ (SET or RESET). 501 */ 502 #define SMBUS_FLAG_MASK (0x0001FFFFU) 503 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ 504 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ 505 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 506 507 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. 508 * @param __HANDLE__ specifies the SMBUS Handle. 509 * @param __FLAG__ specifies the flag to clear. 510 * This parameter can be any combination of the following values: 511 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 512 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 513 * @arg @ref SMBUS_FLAG_AF NACK received flag 514 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 515 * @arg @ref SMBUS_FLAG_BERR Bus error 516 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 517 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 518 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 519 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 520 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 521 * 522 * @retval None 523 */ 524 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ 525 ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ 526 ((__HANDLE__)->Instance->ICR = (__FLAG__))) 527 528 /** @brief Enable the specified SMBUS peripheral. 529 * @param __HANDLE__ specifies the SMBUS Handle. 530 * @retval None 531 */ 532 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 533 534 /** @brief Disable the specified SMBUS peripheral. 535 * @param __HANDLE__ specifies the SMBUS Handle. 536 * @retval None 537 */ 538 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 539 540 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. 541 * @param __HANDLE__ specifies the SMBUS Handle. 542 * @retval None 543 */ 544 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 545 546 /** 547 * @} 548 */ 549 550 551 /* Private constants ---------------------------------------------------------*/ 552 553 /* Private macros ------------------------------------------------------------*/ 554 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros 555 * @{ 556 */ 557 558 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ 559 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) 560 561 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 562 563 #define IS_SMBUS_ADDRESSING_MODE(MODE) ((MODE) == SMBUS_ADDRESSINGMODE_7BIT) 564 565 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ 566 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) 567 568 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ 569 ((MASK) == SMBUS_OA2_MASK01) || \ 570 ((MASK) == SMBUS_OA2_MASK02) || \ 571 ((MASK) == SMBUS_OA2_MASK03) || \ 572 ((MASK) == SMBUS_OA2_MASK04) || \ 573 ((MASK) == SMBUS_OA2_MASK05) || \ 574 ((MASK) == SMBUS_OA2_MASK06) || \ 575 ((MASK) == SMBUS_OA2_MASK07)) 576 577 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ 578 ((CALL) == SMBUS_GENERALCALL_ENABLE)) 579 580 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ 581 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) 582 583 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ 584 ((PEC) == SMBUS_PEC_ENABLE)) 585 586 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ 587 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ 588 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) 589 590 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ 591 ((MODE) == SMBUS_AUTOEND_MODE) || \ 592 ((MODE) == SMBUS_SOFTEND_MODE) || \ 593 ((MODE) == SMBUS_SENDPEC_MODE) || \ 594 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ 595 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ 596 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ 597 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ 598 SMBUS_RELOAD_MODE ))) 599 600 601 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ 602 ((REQUEST) == SMBUS_GENERATE_START_READ) || \ 603 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ 604 ((REQUEST) == SMBUS_NO_STARTSTOP)) 605 606 607 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 608 ((REQUEST) == SMBUS_FIRST_FRAME) || \ 609 ((REQUEST) == SMBUS_NEXT_FRAME) || \ 610 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 611 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ 612 ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ 613 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 614 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) 615 616 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ 617 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 618 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ 619 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 620 621 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ 622 (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ 623 I2C_CR1_PECEN))) 624 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ 625 (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 626 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 627 I2C_CR2_RD_WRN))) 628 629 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ 630 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ 631 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ 632 (~I2C_CR2_RD_WRN)) : \ 633 (uint32_t)((((uint32_t)(__ADDRESS__) & \ 634 (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ 635 (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 636 637 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) 638 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) 639 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 640 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) 641 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) 642 643 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ 644 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 645 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 646 647 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 648 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 649 650 /** 651 * @} 652 */ 653 654 /* Include SMBUS HAL Extended module */ 655 #include "stm32h7rsxx_hal_smbus_ex.h" 656 657 /* Exported functions --------------------------------------------------------*/ 658 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions 659 * @{ 660 */ 661 662 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 663 * @{ 664 */ 665 666 /* Initialization and de-initialization functions ****************************/ 667 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); 668 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); 669 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); 670 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); 671 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); 672 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); 673 674 /* Callbacks Register/UnRegister functions ***********************************/ 675 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 676 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, 677 HAL_SMBUS_CallbackIDTypeDef CallbackID, 678 pSMBUS_CallbackTypeDef pCallback); 679 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, 680 HAL_SMBUS_CallbackIDTypeDef CallbackID); 681 682 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, 683 pSMBUS_AddrCallbackTypeDef pCallback); 684 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); 685 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 686 /** 687 * @} 688 */ 689 690 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions 691 * @{ 692 */ 693 694 /* IO operation functions *****************************************************/ 695 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 696 * @{ 697 */ 698 /******* Blocking mode: Polling */ 699 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, 700 uint32_t Timeout); 701 /** 702 * @} 703 */ 704 705 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 706 * @{ 707 */ 708 /******* Non-Blocking mode: Interrupt */ 709 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, 710 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 711 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, 712 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 713 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); 714 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, 715 uint32_t XferOptions); 716 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, 717 uint32_t XferOptions); 718 719 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 720 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 721 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); 722 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); 723 /** 724 * @} 725 */ 726 727 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 728 * @{ 729 */ 730 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 731 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 732 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 733 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 734 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 735 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 736 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 737 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 738 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); 739 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); 740 741 /** 742 * @} 743 */ 744 745 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 746 * @{ 747 */ 748 749 /* Peripheral State and Errors functions **************************************************/ 750 uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); 751 uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); 752 753 /** 754 * @} 755 */ 756 757 /** 758 * @} 759 */ 760 761 /* Private Functions ---------------------------------------------------------*/ 762 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions 763 * @{ 764 */ 765 /* Private functions are defined in stm32h7rsxx_hal_smbus.c file */ 766 /** 767 * @} 768 */ 769 770 /** 771 * @} 772 */ 773 774 /** 775 * @} 776 */ 777 778 /** 779 * @} 780 */ 781 782 #ifdef __cplusplus 783 } 784 #endif 785 786 787 #endif /* STM32H7RSxx_HAL_SMBUS_H */ 788
