1 /** 2 ****************************************************************************** 3 * @file stm32h7rsxx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7RSxx_HAL_CORTEX_H 21 #define STM32H7RSxx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7rsxx_hal_def.h" 29 30 /** @addtogroup STM32H7RSxx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @brief CORTEX HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 45 * @brief MPU Region initialization structure 46 * @{ 47 */ 48 typedef struct 49 { 50 uint8_t Enable; /*!< Specifies the status of the region. 51 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 52 uint8_t Number; /*!< Specifies the number of the region to protect. 53 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 54 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. 55 */ 56 uint8_t Size; /*!< Specifies the size of the region to protect. 57 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 58 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 59 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 60 uint8_t TypeExtField; /*!< Specifies the TEX field level. 61 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 62 uint8_t AccessPermission; /*!< Specifies the region access permission type. 63 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 64 uint8_t DisableExec; /*!< Specifies the instruction access status. 65 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 66 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 67 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 68 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 69 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 70 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 71 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 72 } MPU_Region_InitTypeDef; 73 /** 74 * @} 75 */ 76 77 /** 78 * @} 79 */ 80 81 /* Exported constants --------------------------------------------------------*/ 82 83 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 84 * @{ 85 */ 86 87 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 88 * @{ 89 */ 90 #define NVIC_PRIORITYGROUP_0 7U /*!< 0 bit for pre-emption priority, 91 4 bits for subpriority */ 92 #define NVIC_PRIORITYGROUP_1 6U /*!< 1 bit for pre-emption priority, 93 3 bits for subpriority */ 94 #define NVIC_PRIORITYGROUP_2 5U /*!< 2 bits for pre-emption priority, 95 2 bits for subpriority */ 96 #define NVIC_PRIORITYGROUP_3 4U /*!< 3 bits for pre-emption priority, 97 1 bit for subpriority */ 98 #define NVIC_PRIORITYGROUP_4 3U /*!< 4 bits for pre-emption priority, 99 0 bit for subpriority */ 100 /** 101 * @} 102 */ 103 104 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 105 * @{ 106 */ 107 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0U 108 #define SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk 109 110 /** 111 * @} 112 */ 113 114 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 115 * @{ 116 */ 117 #define MPU_HFNMI_PRIVDEF_NONE 0U 118 #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk 119 #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk 120 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 121 /** 122 * @} 123 */ 124 125 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 126 * @{ 127 */ 128 #define MPU_REGION_ENABLE 1U 129 #define MPU_REGION_DISABLE 0U 130 /** 131 * @} 132 */ 133 134 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 135 * @{ 136 */ 137 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U 138 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U 139 /** 140 * @} 141 */ 142 143 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 144 * @{ 145 */ 146 #define MPU_ACCESS_NOT_SHAREABLE 0U 147 #define MPU_ACCESS_SHAREABLE 1U 148 /** 149 * @} 150 */ 151 152 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 153 * @{ 154 */ 155 #define MPU_ACCESS_CACHEABLE 1U 156 #define MPU_ACCESS_NOT_CACHEABLE 0U 157 /** 158 * @} 159 */ 160 161 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 162 * @{ 163 */ 164 #define MPU_ACCESS_BUFFERABLE 1U 165 #define MPU_ACCESS_NOT_BUFFERABLE 0U 166 /** 167 * @} 168 */ 169 170 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 171 * @{ 172 */ 173 #define MPU_TEX_LEVEL0 0U 174 #define MPU_TEX_LEVEL1 1U 175 #define MPU_TEX_LEVEL2 2U 176 /** 177 * @} 178 */ 179 180 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 181 * @{ 182 */ 183 #define MPU_REGION_SIZE_32B 0x04U 184 #define MPU_REGION_SIZE_64B 0x05U 185 #define MPU_REGION_SIZE_128B 0x06U 186 #define MPU_REGION_SIZE_256B 0x07U 187 #define MPU_REGION_SIZE_512B 0x08U 188 #define MPU_REGION_SIZE_1KB 0x09U 189 #define MPU_REGION_SIZE_2KB 0x0AU 190 #define MPU_REGION_SIZE_4KB 0x0BU 191 #define MPU_REGION_SIZE_8KB 0x0CU 192 #define MPU_REGION_SIZE_16KB 0x0DU 193 #define MPU_REGION_SIZE_32KB 0x0EU 194 #define MPU_REGION_SIZE_64KB 0x0FU 195 #define MPU_REGION_SIZE_128KB 0x10U 196 #define MPU_REGION_SIZE_256KB 0x11U 197 #define MPU_REGION_SIZE_512KB 0x12U 198 #define MPU_REGION_SIZE_1MB 0x13U 199 #define MPU_REGION_SIZE_2MB 0x14U 200 #define MPU_REGION_SIZE_4MB 0x15U 201 #define MPU_REGION_SIZE_8MB 0x16U 202 #define MPU_REGION_SIZE_16MB 0x17U 203 #define MPU_REGION_SIZE_32MB 0x18U 204 #define MPU_REGION_SIZE_64MB 0x19U 205 #define MPU_REGION_SIZE_128MB 0x1AU 206 #define MPU_REGION_SIZE_256MB 0x1BU 207 #define MPU_REGION_SIZE_512MB 0x1CU 208 #define MPU_REGION_SIZE_1GB 0x1DU 209 #define MPU_REGION_SIZE_2GB 0x1EU 210 #define MPU_REGION_SIZE_4GB 0x1FU 211 /** 212 * @} 213 */ 214 215 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 216 * @{ 217 */ 218 #define MPU_REGION_NO_ACCESS 0U 219 #define MPU_REGION_PRIV_RW 1U 220 #define MPU_REGION_PRIV_RW_URO 2U 221 #define MPU_REGION_FULL_ACCESS 3U 222 #define MPU_REGION_PRIV_RO 5U 223 #define MPU_REGION_PRIV_RO_URO 6U 224 /** 225 * @} 226 */ 227 228 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 229 * @{ 230 */ 231 #define MPU_REGION_NUMBER0 0U 232 #define MPU_REGION_NUMBER1 1U 233 #define MPU_REGION_NUMBER2 2U 234 #define MPU_REGION_NUMBER3 3U 235 #define MPU_REGION_NUMBER4 4U 236 #define MPU_REGION_NUMBER5 5U 237 #define MPU_REGION_NUMBER6 6U 238 #define MPU_REGION_NUMBER7 7U 239 #define MPU_REGION_NUMBER8 8U 240 #define MPU_REGION_NUMBER9 9U 241 #define MPU_REGION_NUMBER10 10U 242 #define MPU_REGION_NUMBER11 11U 243 #define MPU_REGION_NUMBER12 12U 244 #define MPU_REGION_NUMBER13 13U 245 #define MPU_REGION_NUMBER14 14U 246 #define MPU_REGION_NUMBER15 15U 247 /** 248 * @} 249 */ 250 251 /** 252 * @} 253 */ 254 255 /* Exported macros -----------------------------------------------------------*/ 256 /* Exported functions --------------------------------------------------------*/ 257 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 258 * @{ 259 */ 260 261 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 262 * @brief Initialization and Configuration functions 263 * @{ 264 */ 265 /* Initialization and Configuration functions *****************************/ 266 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 267 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 268 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 269 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 270 void HAL_NVIC_SystemReset(void); 271 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 272 /** 273 * @} 274 */ 275 276 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 277 * @brief Cortex control functions 278 * @{ 279 */ 280 /* Peripheral Control functions ***********************************************/ 281 uint32_t HAL_NVIC_GetPriorityGrouping(void); 282 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); 283 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 284 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 285 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 286 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 287 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 288 void HAL_SYSTICK_IRQHandler(void); 289 void HAL_SYSTICK_Callback(void); 290 void HAL_MPU_Enable(uint32_t MPU_Control); 291 void HAL_MPU_Disable(void); 292 void HAL_MPU_EnableRegion(uint32_t RegionNumber); 293 void HAL_MPU_DisableRegion(uint32_t RegionNumber); 294 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit); 295 void HAL_CORTEX_ClearEvent(void); 296 /** 297 * @} 298 */ 299 300 /** 301 * @} 302 */ 303 304 /* Private types -------------------------------------------------------------*/ 305 /* Private variables ---------------------------------------------------------*/ 306 /* Private constants ---------------------------------------------------------*/ 307 /* Private macros ------------------------------------------------------------*/ 308 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 309 * @{ 310 */ 311 #define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \ 312 ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \ 313 ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \ 314 ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \ 315 ((__GROUP__) == NVIC_PRIORITYGROUP_4)) 316 317 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIO__) < (1uL << __NVIC_PRIO_BITS)) && \ 318 ((__PRIO__) < (0x1uL << (0x07u - __PRIOGRP__)))) 319 320 #define IS_NVIC_SUB_PRIORITY(__PRIO__, __PRIOGRP__) \ 321 ((__PRIOGRP__ < (0x07u - __NVIC_PRIO_BITS)) ?\ 322 ((__PRIO__) < (1u)): \ 323 ((__PRIO__) < (0x1uL << (__PRIOGRP__ - (0x07u - __NVIC_PRIO_BITS))))) 324 325 #define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) > SysTick_IRQn) 326 327 #define IS_NVIC_PRIO_INTERRUPT(__IT__) (((__IT__) > HardFault_IRQn) && ((__IT__) != DebugMonitor_IRQn)) 328 329 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ 330 ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 331 332 #define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \ 333 ((__STATE__) == MPU_REGION_DISABLE)) 334 335 #define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 336 ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE)) 337 338 #define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_SHAREABLE) || \ 339 ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE)) 340 341 #define IS_MPU_ACCESS_CACHEABLE(__STATE__) (((__STATE__) == MPU_ACCESS_CACHEABLE) || \ 342 ((__STATE__) == MPU_ACCESS_NOT_CACHEABLE)) 343 344 #define IS_MPU_ACCESS_BUFFERABLE(__STATE__) (((__STATE__) == MPU_ACCESS_BUFFERABLE) || \ 345 ((__STATE__) == MPU_ACCESS_NOT_BUFFERABLE)) 346 347 #define IS_MPU_TEX_LEVEL(__TYPE__) (((__TYPE__) == MPU_TEX_LEVEL0) || \ 348 ((__TYPE__) == MPU_TEX_LEVEL1) || \ 349 ((__TYPE__) == MPU_TEX_LEVEL2)) 350 351 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_NO_ACCESS) || \ 352 ((__TYPE__) == MPU_REGION_PRIV_RW) || \ 353 ((__TYPE__) == MPU_REGION_PRIV_RW_URO) || \ 354 ((__TYPE__) == MPU_REGION_FULL_ACCESS) || \ 355 ((__TYPE__) == MPU_REGION_PRIV_RO) || \ 356 ((__TYPE__) == MPU_REGION_PRIV_RO_URO)) 357 358 #define IS_MPU_REGION_NUMBER(__NUMBER__) ((__NUMBER__) <= MPU_REGION_NUMBER15) 359 360 #define IS_MPU_REGION_SIZE(__SIZE__) (((__SIZE__) == MPU_REGION_SIZE_32B) || \ 361 ((__SIZE__) == MPU_REGION_SIZE_64B) || \ 362 ((__SIZE__) == MPU_REGION_SIZE_128B) || \ 363 ((__SIZE__) == MPU_REGION_SIZE_256B) || \ 364 ((__SIZE__) == MPU_REGION_SIZE_512B) || \ 365 ((__SIZE__) == MPU_REGION_SIZE_1KB) || \ 366 ((__SIZE__) == MPU_REGION_SIZE_2KB) || \ 367 ((__SIZE__) == MPU_REGION_SIZE_4KB) || \ 368 ((__SIZE__) == MPU_REGION_SIZE_8KB) || \ 369 ((__SIZE__) == MPU_REGION_SIZE_16KB) || \ 370 ((__SIZE__) == MPU_REGION_SIZE_32KB) || \ 371 ((__SIZE__) == MPU_REGION_SIZE_64KB) || \ 372 ((__SIZE__) == MPU_REGION_SIZE_128KB) || \ 373 ((__SIZE__) == MPU_REGION_SIZE_256KB) || \ 374 ((__SIZE__) == MPU_REGION_SIZE_512KB) || \ 375 ((__SIZE__) == MPU_REGION_SIZE_1MB) || \ 376 ((__SIZE__) == MPU_REGION_SIZE_2MB) || \ 377 ((__SIZE__) == MPU_REGION_SIZE_4MB) || \ 378 ((__SIZE__) == MPU_REGION_SIZE_8MB) || \ 379 ((__SIZE__) == MPU_REGION_SIZE_16MB) || \ 380 ((__SIZE__) == MPU_REGION_SIZE_32MB) || \ 381 ((__SIZE__) == MPU_REGION_SIZE_64MB) || \ 382 ((__SIZE__) == MPU_REGION_SIZE_128MB) || \ 383 ((__SIZE__) == MPU_REGION_SIZE_256MB) || \ 384 ((__SIZE__) == MPU_REGION_SIZE_512MB) || \ 385 ((__SIZE__) == MPU_REGION_SIZE_1GB) || \ 386 ((__SIZE__) == MPU_REGION_SIZE_2GB) || \ 387 ((__SIZE__) == MPU_REGION_SIZE_4GB)) 388 389 #define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU) 390 391 #define IS_MPU_ADDRESS_MULTIPLE_SIZE(__ADDRESS__, __SIZE__) (((__ADDRESS__) & (1<<(__SIZE__+1U))- 1U) == 0U) 392 393 /** 394 * @} 395 */ 396 397 /** 398 * @} 399 */ 400 401 /** 402 * @} 403 */ 404 405 #ifdef __cplusplus 406 } 407 #endif 408 409 #endif /* STM32H7RSxx_HAL_CORTEX_H */ 410
