1 /**
2   ******************************************************************************
3   * @file    stm32h7b3xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32H7B3xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2019 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32h7b3xx
30   * @{
31   */
32 
33 #ifndef STM32H7B3xx_H
34 #define STM32H7B3xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Peripheral_interrupt_number_definition
41   * @{
42   */
43 
44 /**
45  * @brief STM32H7XX Interrupt Number Definition, according to the selected device
46  *        in @ref Library_configuration_section
47  */
48 typedef enum
49 {
50 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
51   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
52   HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
53   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
54   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
55   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
56   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
57   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */
58   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
59   SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
60 /******  STM32 specific Interrupt Numbers **********************************************************************/
61   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */
62   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM through EXTI Line detection Interrupt                     */
63   RTC_TAMP_STAMP_CSS_LSE_IRQn = 2,      /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line   */
64   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
65   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
66   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
67   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
68   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
69   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
70   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
71   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
72   DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
73   DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
74   DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
75   DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
76   DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
77   DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
78   DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
79   ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */
80   FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */
81   FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */
82   FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */
83   FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */
84   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
85   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */
86   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
87   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
88   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
89   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
90   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
91   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
92   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
93   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
94   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
95   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
96   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
97   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
98   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
99   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
100   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
101   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
102   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
103   DFSDM2_IRQn                 = 42,     /*!< DFSDM2 global Interrupt                                           */
104   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
105   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
106   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
107   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
108   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
109   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
110   SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
111   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
112   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
113   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
114   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
115   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
116   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
117   DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */
118   DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */
119   DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */
120   DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */
121   DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */
122   FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */
123   DFSDM1_FLT4_IRQn            = 64,     /*!< DFSDM Filter4 Interrupt                                           */
124   DFSDM1_FLT5_IRQn            = 65,     /*!< DFSDM Filter5 Interrupt                                           */
125   DFSDM1_FLT6_IRQn            = 66,     /*!< DFSDM Filter6 Interrupt                                           */
126   DFSDM1_FLT7_IRQn            = 67,     /*!< DFSDM Filter7 Interrupt                                           */
127   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
128   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
129   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
130   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
131   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
132   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
133   OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
134   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
135   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
136   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
137   DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */
138   CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
139   HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */
140   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
141   UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
142   UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
143   SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
144   SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
145   SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
146   SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
147   LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
148   LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
149   DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
150   SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
151   OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */
152   LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
153   CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
154   I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
155   I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
156   SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
157   DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */
158   DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */
159   DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */
160   DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */
161   DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */
162   SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */
163   TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */
164   TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */
165   TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */
166   MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */
167   MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */
168   JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */
169   MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */
170   SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */
171   HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */
172   DAC2_IRQn                   = 127,    /*!< DAC2 global Interrupt                                             */
173   DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */
174   BDMA2_Channel0_IRQn         = 129,    /*!< BDMA2 Channel 0 global Interrupt                                  */
175   BDMA2_Channel1_IRQn         = 130,    /*!< BDMA2 Channel 1 global Interrupt                                  */
176   BDMA2_Channel2_IRQn         = 131,    /*!< BDMA2 Channel 2 global Interrupt                                  */
177   BDMA2_Channel3_IRQn         = 132,    /*!< BDMA2 Channel 3 global Interrupt                                  */
178   BDMA2_Channel4_IRQn         = 133,    /*!< BDMA2 Channel 4 global Interrupt                                  */
179   BDMA2_Channel5_IRQn         = 134,    /*!< BDMA2 Channel 5 global Interrupt                                  */
180   BDMA2_Channel6_IRQn         = 135,    /*!< BDMA2 Channel 6 global Interrupt                                  */
181   BDMA2_Channel7_IRQn         = 136,    /*!< BDMA2 Channel 7 global Interrupt                                  */
182   COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */
183   LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */
184   LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */
185   UART9_IRQn                  = 140,    /*!< UART9 global interrupt                                            */
186   USART10_IRQn                = 141,    /*!< USART10 global interrupt                                          */
187   LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */
188   WWDG_RST_IRQn               = 143,    /*!<Window Watchdog Event interrupt                                    */
189   CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */
190   ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */
191   DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */
192   WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */
193   OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */
194   OTFDEC1_IRQn                = 151,    /*!< OTFDEC1 global interrupt                                          */
195   OTFDEC2_IRQn                = 152,    /*!< OTFDEC2 global interrupt                                          */
196   GFXMMU_IRQn                 = 153,    /*!< GFXMMU global interrupt                                           */
197   BDMA1_IRQn                  = 154,    /*!< BDMA1 for DFSM global interrupt                                   */
198 } IRQn_Type;
199 
200 /**
201   * @}
202   */
203 
204 /** @addtogroup Configuration_section_for_CMSIS
205   * @{
206   */
207 
208 
209 
210 
211 /**
212   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
213    */
214 #define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
215 #define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
216 #define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
217 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
218 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
219 #define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
220 #define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
221 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
222 
223 /**
224   * @}
225   */
226 
227 
228 
229 
230 #include "system_stm32h7xx.h"
231 #include <stdint.h>
232 
233 /** @addtogroup Peripheral_registers_structures
234   * @{
235   */
236 
237 /**
238   * @brief Analog to Digital Converter
239   */
240 
241 typedef struct
242 {
243   __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */
244   __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */
245   __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */
246   __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */
247   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
248   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
249   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
250   __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */
251   __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
252   __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
253   uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */
254   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
255   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
256   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
257   __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */
258   __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */
259   __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */
260   uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */
261   uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */
262   __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */
263   uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */
264   __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */
265   __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */
266   __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */
267   __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */
268   uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */
269   __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */
270   __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */
271   __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */
272   __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */
273   uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */
274   __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */
275   __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */
276   uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */
277   uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */
278   __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */
279   __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */
280   __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */
281   __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */
282   __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */
283   __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */
284   __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */
285 } ADC_TypeDef;
286 
287 
288 typedef struct
289 {
290 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
291 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
292 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
293 __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
294 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
295 
296 } ADC_Common_TypeDef;
297 
298 
299 /**
300   * @brief VREFBUF
301   */
302 
303 typedef struct
304 {
305   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
306   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
307 } VREFBUF_TypeDef;
308 
309 
310 /**
311   * @brief FD Controller Area Network
312   */
313 
314 typedef struct
315 {
316   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
317   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
318   __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
319   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
320   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
321   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
322   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
323   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
324   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
325   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
326   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
327   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
328   __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
329   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
330   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
331   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
332   __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
333   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
334   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
335   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
336   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
337   __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
338   __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
339   __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
340   __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
341   __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
342   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
343   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
344   __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
345   __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
346   __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
347   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
348   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
349   __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
350   __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
351   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
352   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
353   __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
354   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
355   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
356   __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
357   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
358   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
359   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
360   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
361   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
362   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
363   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
364   __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */
365   __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
366   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
367   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
368   __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */
369 } FDCAN_GlobalTypeDef;
370 
371 /**
372   * @brief TTFD Controller Area Network
373   */
374 
375 typedef struct
376 {
377   __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */
378   __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */
379   __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */
380   __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */
381   __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */
382   __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */
383   __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */
384   __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */
385   __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */
386   __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */
387   __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */
388   __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */
389   __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */
390   __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */
391   __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */
392   __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */
393   __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */
394   __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */
395   __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */
396 } TTCAN_TypeDef;
397 
398 /**
399   * @brief FD Controller Area Network
400   */
401 
402 typedef struct
403 {
404   __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
405   __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */
406   __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */
407   __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */
408   __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */
409   __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */
410 } FDCAN_ClockCalibrationUnit_TypeDef;
411 
412 
413 /**
414   * @brief Consumer Electronics Control
415   */
416 
417 typedef struct
418 {
419   __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
420   __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
421   __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
422   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
423   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
424   __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
425 }CEC_TypeDef;
426 
427 /**
428   * @brief CRC calculation unit
429   */
430 
431 typedef struct
432 {
433   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
434   __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
435   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
436   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
437   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
438   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
439 } CRC_TypeDef;
440 
441 
442 /**
443   * @brief Clock Recovery System
444   */
445 typedef struct
446 {
447 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
448 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
449 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
450 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
451 } CRS_TypeDef;
452 
453 
454 /**
455   * @brief Digital to Analog Converter
456   */
457 
458 typedef struct
459 {
460   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
461   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
462   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
463   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
464   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
465   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
466   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
467   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
468   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
469   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
470   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
471   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
472   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
473   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
474   __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
475   __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
476   __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
477   __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
478   __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
479   __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
480 } DAC_TypeDef;
481 
482 /**
483   * @brief DFSDM module registers
484   */
485 typedef struct
486 {
487   __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */
488   __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */
489   __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
490   __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
491   __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
492   __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */
493   __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */
494   __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */
495   __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
496   __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
497   __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
498   __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
499   __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
500   __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
501   __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */
502 } DFSDM_Filter_TypeDef;
503 
504 /**
505   * @brief DFSDM channel configuration registers
506   */
507 typedef struct
508 {
509   __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
510   __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
511   __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and
512                                    short circuit detector register,                  Address offset: 0x08 */
513   __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
514   __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */
515   __IO uint32_t CHDLYR;       /*!< DFSDM channel delay register,                     Address offset: 0x14 */
516 } DFSDM_Channel_TypeDef;
517 
518 /**
519   * @brief Debug MCU
520   */
521 typedef struct
522 {
523   __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */
524   __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */
525   uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */
526   __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */
527   uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */
528   __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */
529   uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */
530   __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */
531   uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */
532   __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */
533   uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */
534   __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */
535 }DBGMCU_TypeDef;
536 /**
537   * @brief DCMI
538   */
539 
540 typedef struct
541 {
542   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
543   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
544   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
545   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
546   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
547   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
548   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
549   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
550   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
551   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
552   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
553 } DCMI_TypeDef;
554 
555 /**
556   * @brief PSSI
557   */
558 
559 typedef struct
560 {
561   __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */
562   __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */
563   __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
564   __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */
565   __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */
566   __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */
567   __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */
568   __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */
569   __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */
570   __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */
571   __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */
572   __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */
573   __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */
574 } PSSI_TypeDef;
575 
576 /**
577   * @brief DMA Controller
578   */
579 
580 typedef struct
581 {
582   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
583   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
584   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
585   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
586   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
587   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
588 } DMA_Stream_TypeDef;
589 
590 typedef struct
591 {
592   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
593   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
594   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
595   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
596 } DMA_TypeDef;
597 
598 typedef struct
599 {
600   __IO uint32_t CCR;          /*!< DMA channel x configuration register          */
601   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */
602   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */
603   __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */
604   __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */
605 } BDMA_Channel_TypeDef;
606 
607 typedef struct
608 {
609   __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
610   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
611 } BDMA_TypeDef;
612 
613 typedef struct
614 {
615   __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */
616 }DMAMUX_Channel_TypeDef;
617 
618 typedef struct
619 {
620   __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */
621   __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */
622 }DMAMUX_ChannelStatus_TypeDef;
623 
624 typedef struct
625 {
626   __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */
627 }DMAMUX_RequestGen_TypeDef;
628 
629 typedef struct
630 {
631   __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */
632   __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */
633 }DMAMUX_RequestGenStatus_TypeDef;
634 
635 /**
636   * @brief MDMA Controller
637   */
638 typedef struct
639 {
640   __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */
641 }MDMA_TypeDef;
642 
643 typedef struct
644 {
645   __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */
646   __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */
647   __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */
648   __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */
649   __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */
650   __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */
651   __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */
652   __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */
653   __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */
654   __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */
655   __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */
656   uint32_t       RESERVED0; /*!< Reserved, 0x6C                                                             */
657   __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */
658   __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */
659 }MDMA_Channel_TypeDef;
660 
661 /**
662   * @brief DMA2D Controller
663   */
664 
665 typedef struct
666 {
667   __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
668   __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
669   __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
670   __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
671   __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
672   __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
673   __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
674   __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
675   __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
676   __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
677   __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
678   __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
679   __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
680   __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
681   __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
682   __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
683   __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
684   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
685   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
686   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
687   uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
688   __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
689   __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
690 } DMA2D_TypeDef;
691 
692 
693 /**
694   * @brief External Interrupt/Event Controller
695   */
696 
697 typedef struct
698 {
699 __IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */
700 __IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */
701 __IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */
702 __IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
703 __IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */
704 __IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */
705 uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */
706 __IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */
707 __IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */
708 __IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */
709 __IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
710 __IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */
711 __IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
712 uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */
713 __IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */
714 __IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */
715 __IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */
716 __IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
717 __IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
718 __IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
719 uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */
720 __IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */
721 __IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */
722 __IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */
723 uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */
724 __IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */
725 __IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */
726 __IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */
727 uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */
728 __IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */
729 __IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */
730 __IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */
731 }EXTI_TypeDef;
732 
733 /**
734   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
735   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
736   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
737   *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
738   *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
739   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
740   */
741 
742 typedef struct
743 {
744 __IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
745 __IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */
746 __IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */
747 uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */
748 __IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */
749 __IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */
750 __IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */
751 uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */
752 __IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
753 __IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */
754 __IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */
755 }EXTI_Core_TypeDef;
756 
757 
758 /**
759   * @brief FLASH Registers
760   */
761 
762 typedef struct
763 {
764   __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */
765   __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */
766   __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */
767   __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */
768   __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */
769   __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */
770   __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */
771   __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */
772   __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */
773   __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */
774   __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */
775   __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */
776   __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */
777   __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */
778   __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */
779   __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */
780   __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */
781   __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */
782   uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */
783   __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */
784   __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */
785   __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */
786   __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */
787   __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */
788   uint32_t      RESERVED;        /*!< Reserved, 0x64                                                                  */
789   __IO uint32_t OTPBL_CUR;       /*!< Flash Current OTP Block Lock Register,                    Address offset: 0x68  */
790   __IO uint32_t OTPBL_PRG;       /*!< Flash OTP Block Lock to Program Register,                 Address offset: 0x6C  */
791   uint32_t      RESERVED1[37];   /*!< Reserved, 0x70 to 0x100                                                         */
792   __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */
793   uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */
794   __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */
795   __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */
796   __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */
797   uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */
798   __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */
799   __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */
800   __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */
801   __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */
802   __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */
803   __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */
804   uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */
805   __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */
806   __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */
807   __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */
808   __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */
809   __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */
810 } FLASH_TypeDef;
811 
812 /**
813   * @brief Flexible Memory Controller
814   */
815 
816 typedef struct
817 {
818   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
819 } FMC_Bank1_TypeDef;
820 
821 /**
822   * @brief Flexible Memory Controller Bank1E
823   */
824 
825 typedef struct
826 {
827   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
828 } FMC_Bank1E_TypeDef;
829 
830 /**
831   * @brief Flexible Memory Controller Bank2
832   */
833 
834 typedef struct
835 {
836   __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
837   __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
838   __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
839   __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
840   uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
841   __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
842 } FMC_Bank2_TypeDef;
843 
844 /**
845   * @brief Flexible Memory Controller Bank3
846   */
847 
848 typedef struct
849 {
850   __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
851   __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
852   __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
853   __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
854   uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */
855   __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
856 } FMC_Bank3_TypeDef;
857 
858 /**
859   * @brief Flexible Memory Controller Bank5 and 6
860   */
861 
862 
863 typedef struct
864 {
865   __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
866   __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
867   __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
868   __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
869   __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
870 } FMC_Bank5_6_TypeDef;
871 
872 /**
873   * @brief GFXMMU registers
874   */
875 
876 typedef struct
877 {
878   __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */
879   __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */
880   __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */
881   __IO uint32_t CCR;             /*!< GFXMMU Cache Control Register,                     Address offset: 0x0C */
882   __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */
883        uint32_t RESERVED1[3];    /*!< Reserved1,                                         Address offset: 0x14 to 0x1C */
884   __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */
885   __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */
886   __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */
887   __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */
888        uint32_t RESERVED2[1012]; /*!< Reserved2,                                         Address offset: 0x30 to 0xFFC */
889   __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                              Address offset: 0x1000 to 0x2FFC
890                                       For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
891 } GFXMMU_TypeDef;
892 /**
893   * @brief General Purpose I/O
894   */
895 
896 typedef struct
897 {
898   __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
899   __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
900   __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
901   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
902   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
903   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
904   __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */
905   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
906   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
907 } GPIO_TypeDef;
908 
909 /**
910   * @brief Operational Amplifier (OPAMP)
911   */
912 
913 typedef struct
914 {
915   __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
916   __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
917   __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
918 } OPAMP_TypeDef;
919 
920 /**
921   * @brief System configuration controller
922   */
923 
924 typedef struct
925 {
926  uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */
927  __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */
928  __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */
929  __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */
930  uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */
931  __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */
932  __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */
933  __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */
934 
935 } SYSCFG_TypeDef;
936 
937 /**
938   * @brief Inter-integrated Circuit Interface
939   */
940 
941 typedef struct
942 {
943   __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
944   __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
945   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
946   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
947   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
948   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
949   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
950   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
951   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
952   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
953   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
954 } I2C_TypeDef;
955 
956 /**
957   * @brief Independent WATCHDOG
958   */
959 
960 typedef struct
961 {
962   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
963   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
964   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
965   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
966   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
967 } IWDG_TypeDef;
968 
969 
970 /**
971   * @brief JPEG Codec
972   */
973 typedef struct
974 {
975   __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
976   __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
977   __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
978   __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
979   __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
980   __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
981   __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
982   __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
983   uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
984   __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
985   __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
986   __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
987   uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
988   __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
989   __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
990   uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
991   __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
992   __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
993   __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
994   __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
995   __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
996   __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
997   __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
998   __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
999   uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
1000   __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
1001   __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
1002   __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
1003   __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
1004 
1005 } JPEG_TypeDef;
1006 
1007 /**
1008   * @brief LCD-TFT Display Controller
1009   */
1010 
1011 typedef struct
1012 {
1013   uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
1014   __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
1015   __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
1016   __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
1017   __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
1018   __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
1019   uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
1020   __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
1021   uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
1022   __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
1023   uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
1024   __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
1025   __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
1026   __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
1027   __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1028   __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
1029   __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
1030 } LTDC_TypeDef;
1031 
1032 /**
1033   * @brief LCD-TFT Display layer x Controller
1034   */
1035 
1036 typedef struct
1037 {
1038   __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
1039   __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1040   __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
1041   __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
1042   __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
1043   __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
1044   __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
1045   __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
1046   uint32_t      RESERVED0[2];  /*!< Reserved */
1047   __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
1048   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
1049   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
1050   uint32_t      RESERVED1[3];  /*!< Reserved */
1051   __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
1052 
1053 } LTDC_Layer_TypeDef;
1054 
1055 /**
1056   * @brief Power Control
1057   */
1058 
1059 typedef struct
1060 {
1061   __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */
1062   __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */
1063   __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */
1064   __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */
1065   __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */
1066        uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */
1067   __IO uint32_t SRDCR;     /*!< PWR SRD domain control register,         Address offset: 0x18 */
1068        uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */
1069   __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */
1070   __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */
1071   __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1072 } PWR_TypeDef;
1073 
1074 /**
1075   * @brief Reset and Clock Control
1076   */
1077 
1078 typedef struct
1079 {
1080  __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */
1081  __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */
1082  __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */
1083  __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */
1084  __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */
1085  uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */
1086  __IO uint32_t CDCFGR1;         /*!< RCC Domain 1 configuration register,                                    Address offset: 0x18  */
1087  __IO uint32_t CDCFGR2;         /*!< RCC Domain 2 configuration register,                                    Address offset: 0x1C  */
1088  __IO uint32_t SRDCFGR;         /*!< RCC Domain 3 configuration register,                                    Address offset: 0x20  */
1089  uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */
1090  __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */
1091  __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */
1092  __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */
1093  __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */
1094  __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */
1095  __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */
1096  __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */
1097  __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */
1098  uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */
1099  __IO uint32_t  CDCCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */
1100  __IO uint32_t  CDCCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */
1101  __IO uint32_t  CDCCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */
1102  __IO uint32_t  SRDCCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */
1103  uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */
1104  __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */
1105  __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */
1106  __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */
1107  uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */
1108  __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */
1109  __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */
1110  uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */
1111  __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */
1112  __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */
1113  __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */
1114  __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */
1115  __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */
1116  __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */
1117  __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */
1118  __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */
1119  __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */
1120  uint32_t     RESERVED7;       /*!< Reserved,                                                                Address offset: 0xA0  */
1121  uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */
1122  __IO uint32_t SRDAMR;         /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */
1123   uint32_t     RESERVED9;      /*!< Reserved, 0xAC-0xAF                                                      Address offset: 0xAC  */
1124  __IO uint32_t CKGAENR;        /*!< AXI Clocks Gating Enable Register,                                       Address offset: 0xB0  */
1125   uint32_t     RESERVED10[31];   /*!< Reserved, 0xAC-0xAF                                                    Address offset: 0xAC  */
1126  __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */
1127  __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */
1128  __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */
1129  __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */
1130  __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */
1131  __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */
1132  __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */
1133  __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */
1134  __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */
1135  __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */
1136  uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */
1137  __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */
1138  __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */
1139  __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */
1140  __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */
1141  __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */
1142  __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */
1143  __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */
1144  __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */
1145  __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */
1146  uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */
1147 
1148 } RCC_TypeDef;
1149 
1150 
1151 /**
1152   * @brief Real-Time Clock
1153   */
1154 typedef struct
1155 {
1156   __IO uint32_t TR;             /*!< RTC time register,                              Address offset: 0x00 */
1157   __IO uint32_t DR;             /*!< RTC date register,                              Address offset: 0x04 */
1158   __IO uint32_t SSR;            /*!< RTC sub second register,                        Address offset: 0x08 */
1159   __IO uint32_t ICSR;           /*!< RTC initialization control and status register, Address offset: 0x0C */
1160   __IO uint32_t PRER;           /*!< RTC prescaler register,                         Address offset: 0x10 */
1161   __IO uint32_t WUTR;           /*!< RTC wakeup timer register,                      Address offset: 0x14 */
1162   __IO uint32_t CR;             /*!< RTC control register,                           Address offset: 0x18 */
1163        uint32_t RESERVED0;      /*!< Reserved,                                       Address offset: 0x1C */
1164        uint32_t RESERVED1;      /*!< Reserved,                                       Address offset: 0x20 */
1165   __IO uint32_t WPR;            /*!< RTC write protection register,                  Address offset: 0x24 */
1166   __IO uint32_t CALR;           /*!< RTC calibration register,                       Address offset: 0x28 */
1167   __IO uint32_t SHIFTR;         /*!< RTC shift control register,                     Address offset: 0x2C */
1168   __IO uint32_t TSTR;           /*!< RTC time stamp time register,                   Address offset: 0x30 */
1169   __IO uint32_t TSDR;           /*!< RTC time stamp date register,                   Address offset: 0x34 */
1170   __IO uint32_t TSSSR;          /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
1171        uint32_t RESERVED2;      /*!< Reserved,                                       Address offset: 0x3C */
1172   __IO uint32_t ALRMAR;         /*!< RTC alarm A register,                           Address offset: 0x40 */
1173   __IO uint32_t ALRMASSR;       /*!< RTC alarm A sub second register,                Address offset: 0x44 */
1174   __IO uint32_t ALRMBR;         /*!< RTC alarm B register,                           Address offset: 0x48 */
1175   __IO uint32_t ALRMBSSR;       /*!< RTC alarm B sub second register,                Address offset: 0x4C */
1176   __IO uint32_t SR;             /*!< RTC Status register,                            Address offset: 0x50 */
1177   __IO uint32_t MISR;           /*!< RTC masked interrupt status register,           Address offset: 0x54 */
1178        uint32_t RESERVED3;      /*!< Reserved,                                       Address offset: 0x58 */
1179   __IO uint32_t SCR;            /*!< RTC status Clear register,                      Address offset: 0x5C */
1180   __IO uint32_t CFGR;           /*!< RTC configuration register,                     Address offset: 0x60 */
1181 } RTC_TypeDef;
1182 
1183 /**
1184   * @brief Tamper and backup registers
1185   */
1186 typedef struct
1187 {
1188   __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */
1189   __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */
1190        uint32_t RESERVED0;      /*!< Reserved,                                 Address offset: 0x08 */
1191   __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */
1192   __IO uint32_t ATCR1;          /*!< TAMP active tamper control register,      Address offset: 0x10 */
1193   __IO uint32_t ATSEEDR;        /*!< TAMP active tamper seed register,         Address offset: 0x14 */
1194   __IO uint32_t ATOR;           /*!< TAMP active tamper output register,       Address offset: 0x18 */
1195        uint32_t RESERVED1[4];   /*!< Reserved,                                 Address offset: 0x1C -- 0x28 */
1196   __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */
1197   __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */
1198   __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
1199        uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */
1200   __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */
1201   __IO uint32_t COUNTR;         /*!< TAMP monotonic counter register,          Address offset: 0x40 */
1202        uint32_t RESERVED3[3];   /*!< Reserved,                                 Address offset: 0x44 -- 0x4C */
1203   __IO uint32_t CFGR;           /*!< TAMP configuration register,              Address offset: 0x50 */
1204        uint32_t RESERVED4[43];  /*!< Reserved,                                 Address offset: 0x54 -- 0xFC */
1205   __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */
1206   __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */
1207   __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */
1208   __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */
1209   __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */
1210   __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */
1211   __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */
1212   __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */
1213   __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */
1214   __IO uint32_t BKP9R;          /*!< TAMP backup register 9,                   Address offset: 0x124 */
1215   __IO uint32_t BKP10R;         /*!< TAMP backup register 10,                  Address offset: 0x128 */
1216   __IO uint32_t BKP11R;         /*!< TAMP backup register 11,                  Address offset: 0x12C */
1217   __IO uint32_t BKP12R;         /*!< TAMP backup register 12,                  Address offset: 0x130 */
1218   __IO uint32_t BKP13R;         /*!< TAMP backup register 13,                  Address offset: 0x134 */
1219   __IO uint32_t BKP14R;         /*!< TAMP backup register 14,                  Address offset: 0x138 */
1220   __IO uint32_t BKP15R;         /*!< TAMP backup register 15,                  Address offset: 0x13C */
1221   __IO uint32_t BKP16R;         /*!< TAMP backup register 16,                  Address offset: 0x140 */
1222   __IO uint32_t BKP17R;         /*!< TAMP backup register 17,                  Address offset: 0x144 */
1223   __IO uint32_t BKP18R;         /*!< TAMP backup register 18,                  Address offset: 0x148 */
1224   __IO uint32_t BKP19R;         /*!< TAMP backup register 19,                  Address offset: 0x14C */
1225   __IO uint32_t BKP20R;         /*!< TAMP backup register 20,                  Address offset: 0x150 */
1226   __IO uint32_t BKP21R;         /*!< TAMP backup register 21,                  Address offset: 0x154 */
1227   __IO uint32_t BKP22R;         /*!< TAMP backup register 22,                  Address offset: 0x158 */
1228   __IO uint32_t BKP23R;         /*!< TAMP backup register 23,                  Address offset: 0x15C */
1229   __IO uint32_t BKP24R;         /*!< TAMP backup register 24,                  Address offset: 0x160 */
1230   __IO uint32_t BKP25R;         /*!< TAMP backup register 25,                  Address offset: 0x164 */
1231   __IO uint32_t BKP26R;         /*!< TAMP backup register 26,                  Address offset: 0x168 */
1232   __IO uint32_t BKP27R;         /*!< TAMP backup register 27,                  Address offset: 0x16C */
1233   __IO uint32_t BKP28R;         /*!< TAMP backup register 28,                  Address offset: 0x170 */
1234   __IO uint32_t BKP29R;         /*!< TAMP backup register 29,                  Address offset: 0x174 */
1235   __IO uint32_t BKP30R;         /*!< TAMP backup register 30,                  Address offset: 0x178 */
1236   __IO uint32_t BKP31R;         /*!< TAMP backup register 31,                  Address offset: 0x17C */
1237 } TAMP_TypeDef;
1238 
1239 /**
1240   * @brief Serial Audio Interface
1241   */
1242 
1243 typedef struct
1244 {
1245   __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */
1246   uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */
1247   __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */
1248   __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */
1249 } SAI_TypeDef;
1250 
1251 typedef struct
1252 {
1253   __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
1254   __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
1255   __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
1256   __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
1257   __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
1258   __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
1259   __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
1260   __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
1261 } SAI_Block_TypeDef;
1262 
1263 /**
1264   * @brief SPDIF-RX Interface
1265   */
1266 
1267 typedef struct
1268 {
1269   __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
1270   __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
1271   __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
1272   __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
1273   __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
1274   __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
1275   __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
1276   uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */
1277 } SPDIFRX_TypeDef;
1278 
1279 
1280 /**
1281   * @brief Secure digital input/output Interface
1282   */
1283 
1284 typedef struct
1285 {
1286   __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
1287   __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
1288   __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
1289   __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
1290   __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
1291   __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
1292   __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
1293   __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
1294   __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
1295   __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
1296   __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
1297   __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
1298   __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
1299   __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
1300   __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
1301   __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
1302   __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
1303   uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
1304   __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
1305   __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
1306   __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */
1307   __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */
1308   uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */
1309   __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
1310   uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */
1311   __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */
1312 } SDMMC_TypeDef;
1313 
1314 
1315 /**
1316   * @brief Delay Block DLYB
1317   */
1318 
1319 typedef struct
1320 {
1321   __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
1322   __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
1323 } DLYB_TypeDef;
1324 
1325 /**
1326   * @brief HW Semaphore HSEM
1327   */
1328 
1329 typedef struct
1330 {
1331   __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */
1332   __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */
1333   __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */
1334   __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */
1335   __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */
1336   __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */
1337   uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */
1338   __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */
1339   __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */
1340 
1341 } HSEM_TypeDef;
1342 
1343 typedef struct
1344 {
1345   __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
1346   __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
1347   __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
1348   __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
1349 } HSEM_Common_TypeDef;
1350 
1351 /**
1352   * @brief Serial Peripheral Interface
1353   */
1354 
1355 typedef struct
1356 {
1357   __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
1358   __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
1359   __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
1360   __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
1361   __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
1362   __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
1363   __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
1364   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
1365   __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
1366   uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
1367   __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
1368   uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
1369   __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
1370   __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
1371   __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
1372   __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
1373   __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
1374 
1375 } SPI_TypeDef;
1376 
1377 /**
1378   * @brief DTS
1379   */
1380 typedef struct
1381 {
1382   __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */
1383   uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */
1384   __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */
1385   uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */
1386   __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */
1387   __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */
1388   uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */
1389   __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */
1390   __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */
1391   __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */
1392   __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */
1393   __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */
1394 }
1395 DTS_TypeDef;
1396 
1397 /**
1398   * @brief TIM
1399   */
1400 
1401 typedef struct
1402 {
1403   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
1404   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
1405   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
1406   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
1407   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
1408   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
1409   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
1410   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
1411   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
1412   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
1413   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
1414   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
1415   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
1416   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
1417   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
1418   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
1419   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
1420   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
1421   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
1422   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
1423   uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */
1424   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
1425   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
1426   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
1427   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
1428   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
1429   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
1430 } TIM_TypeDef;
1431 
1432 /**
1433   * @brief LPTIMIMER
1434   */
1435 typedef struct
1436 {
1437   __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */
1438   __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */
1439   __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */
1440   __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */
1441   __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */
1442   __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */
1443   __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */
1444   __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */
1445   uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */
1446   __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */
1447 } LPTIM_TypeDef;
1448 
1449 /**
1450   * @brief Comparator
1451   */
1452 typedef struct
1453 {
1454   __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
1455   __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */
1456   __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */
1457 } COMPOPT_TypeDef;
1458 
1459 typedef struct
1460 {
1461   __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */
1462 } COMP_TypeDef;
1463 
1464 typedef struct
1465 {
1466   __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1467 } COMP_Common_TypeDef;
1468 /**
1469   * @brief Universal Synchronous Asynchronous Receiver Transmitter
1470   */
1471 
1472 typedef struct
1473 {
1474   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
1475   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
1476   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
1477   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
1478   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
1479   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
1480   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
1481   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
1482   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
1483   __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
1484   __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
1485   __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
1486 } USART_TypeDef;
1487 
1488 /**
1489   * @brief Single Wire Protocol Master Interface SPWMI
1490   */
1491 typedef struct
1492 {
1493   __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
1494   __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
1495     uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
1496   __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
1497   __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
1498   __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
1499   __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
1500   __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
1501   __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
1502   __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
1503 } SWPMI_TypeDef;
1504 
1505 /**
1506   * @brief Window WATCHDOG
1507   */
1508 
1509 typedef struct
1510 {
1511   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
1512   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
1513   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
1514 } WWDG_TypeDef;
1515 
1516 
1517 /**
1518   * @brief RAM_ECC_Specific_Registers
1519   */
1520 typedef struct
1521 {
1522   __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */
1523   __IO uint32_t SR;           /*!< RAMECC monitor status register                 */
1524   __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */
1525   __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */
1526   __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */
1527   __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */
1528 } RAMECC_MonitorTypeDef;
1529 
1530 typedef struct
1531 {
1532   __IO uint32_t IER;          /*!< RAMECC interrupt enable register */
1533 } RAMECC_TypeDef;
1534 /**
1535   * @}
1536   */
1537 
1538 
1539 /**
1540   * @brief Crypto Processor
1541   */
1542 
1543 typedef struct
1544 {
1545   __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
1546   __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
1547   __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */
1548   __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
1549   __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
1550   __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
1551   __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
1552   __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
1553   __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
1554   __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
1555   __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
1556   __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
1557   __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
1558   __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
1559   __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
1560   __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
1561   __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
1562   __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
1563   __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
1564   __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
1565   __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
1566   __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
1567   __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
1568   __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
1569   __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
1570   __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
1571   __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
1572   __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
1573   __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
1574   __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
1575   __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
1576   __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
1577   __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
1578   __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
1579   __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
1580   __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
1581 } CRYP_TypeDef;
1582 
1583 /**
1584   * @brief HASH
1585   */
1586 
1587 typedef struct
1588 {
1589   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
1590   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
1591   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
1592   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
1593   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
1594   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
1595        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
1596   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
1597 } HASH_TypeDef;
1598 
1599 /**
1600   * @brief HASH_DIGEST
1601   */
1602 
1603 typedef struct
1604 {
1605   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
1606 } HASH_DIGEST_TypeDef;
1607 
1608 
1609 /**
1610   * @brief RNG
1611   */
1612 
1613 typedef struct
1614 {
1615   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
1616   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
1617   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
1618   uint32_t RESERVED;
1619   __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
1620 } RNG_TypeDef;
1621 
1622 /**
1623   * @brief MDIOS
1624   */
1625 
1626 typedef struct
1627 {
1628   __IO uint32_t CR;
1629   __IO uint32_t WRFR;
1630   __IO uint32_t CWRFR;
1631   __IO uint32_t RDFR;
1632   __IO uint32_t CRDFR;
1633   __IO uint32_t SR;
1634   __IO uint32_t CLRFR;
1635   uint32_t RESERVED[57];
1636   __IO uint32_t DINR0;
1637   __IO uint32_t DINR1;
1638   __IO uint32_t DINR2;
1639   __IO uint32_t DINR3;
1640   __IO uint32_t DINR4;
1641   __IO uint32_t DINR5;
1642   __IO uint32_t DINR6;
1643   __IO uint32_t DINR7;
1644   __IO uint32_t DINR8;
1645   __IO uint32_t DINR9;
1646   __IO uint32_t DINR10;
1647   __IO uint32_t DINR11;
1648   __IO uint32_t DINR12;
1649   __IO uint32_t DINR13;
1650   __IO uint32_t DINR14;
1651   __IO uint32_t DINR15;
1652   __IO uint32_t DINR16;
1653   __IO uint32_t DINR17;
1654   __IO uint32_t DINR18;
1655   __IO uint32_t DINR19;
1656   __IO uint32_t DINR20;
1657   __IO uint32_t DINR21;
1658   __IO uint32_t DINR22;
1659   __IO uint32_t DINR23;
1660   __IO uint32_t DINR24;
1661   __IO uint32_t DINR25;
1662   __IO uint32_t DINR26;
1663   __IO uint32_t DINR27;
1664   __IO uint32_t DINR28;
1665   __IO uint32_t DINR29;
1666   __IO uint32_t DINR30;
1667   __IO uint32_t DINR31;
1668   __IO uint32_t DOUTR0;
1669   __IO uint32_t DOUTR1;
1670   __IO uint32_t DOUTR2;
1671   __IO uint32_t DOUTR3;
1672   __IO uint32_t DOUTR4;
1673   __IO uint32_t DOUTR5;
1674   __IO uint32_t DOUTR6;
1675   __IO uint32_t DOUTR7;
1676   __IO uint32_t DOUTR8;
1677   __IO uint32_t DOUTR9;
1678   __IO uint32_t DOUTR10;
1679   __IO uint32_t DOUTR11;
1680   __IO uint32_t DOUTR12;
1681   __IO uint32_t DOUTR13;
1682   __IO uint32_t DOUTR14;
1683   __IO uint32_t DOUTR15;
1684   __IO uint32_t DOUTR16;
1685   __IO uint32_t DOUTR17;
1686   __IO uint32_t DOUTR18;
1687   __IO uint32_t DOUTR19;
1688   __IO uint32_t DOUTR20;
1689   __IO uint32_t DOUTR21;
1690   __IO uint32_t DOUTR22;
1691   __IO uint32_t DOUTR23;
1692   __IO uint32_t DOUTR24;
1693   __IO uint32_t DOUTR25;
1694   __IO uint32_t DOUTR26;
1695   __IO uint32_t DOUTR27;
1696   __IO uint32_t DOUTR28;
1697   __IO uint32_t DOUTR29;
1698   __IO uint32_t DOUTR30;
1699   __IO uint32_t DOUTR31;
1700 } MDIOS_TypeDef;
1701 
1702 
1703 /**
1704   * @brief USB_OTG_Core_Registers
1705   */
1706 typedef struct
1707 {
1708  __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
1709   __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
1710   __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
1711   __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
1712   __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
1713   __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
1714   __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
1715   __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
1716   __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
1717   __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
1718   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
1719   __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
1720   uint32_t Reserved30[2];             /*!< Reserved                                     030h */
1721   __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
1722   __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
1723   __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
1724   __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
1725   __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
1726   __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
1727   uint32_t  Reserved6;                /*!< Reserved                                     050h */
1728   __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
1729   __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
1730   __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
1731    __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
1732     uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
1733   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
1734   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
1735 } USB_OTG_GlobalTypeDef;
1736 
1737 
1738 /**
1739   * @brief USB_OTG_device_Registers
1740   */
1741 typedef struct
1742 {
1743   __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
1744   __IO uint32_t DCTL;            /*!< dev Control Register         804h */
1745   __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
1746   uint32_t Reserved0C;           /*!< Reserved                     80Ch */
1747   __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
1748   __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
1749   __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
1750   __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
1751   uint32_t  Reserved20;          /*!< Reserved                     820h */
1752   uint32_t Reserved9;            /*!< Reserved                     824h */
1753   __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
1754   __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
1755   __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
1756   __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
1757   __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
1758   __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
1759   uint32_t Reserved40;           /*!< dedicated EP mask            840h */
1760   __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
1761   uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
1762   __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
1763 } USB_OTG_DeviceTypeDef;
1764 
1765 
1766 /**
1767   * @brief USB_OTG_IN_Endpoint-Specific_Register
1768   */
1769 typedef struct
1770 {
1771   __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
1772   uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
1773   __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
1774   uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
1775   __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
1776   __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
1777   __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1778   uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1779 } USB_OTG_INEndpointTypeDef;
1780 
1781 
1782 /**
1783   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1784   */
1785 typedef struct
1786 {
1787   __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
1788   uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
1789   __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
1790   uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
1791   __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
1792   __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
1793   uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1794 } USB_OTG_OUTEndpointTypeDef;
1795 
1796 
1797 /**
1798   * @brief USB_OTG_Host_Mode_Register_Structures
1799   */
1800 typedef struct
1801 {
1802   __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
1803   __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
1804   __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
1805   uint32_t Reserved40C;           /*!< Reserved                             40Ch */
1806   __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
1807   __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
1808   __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
1809 } USB_OTG_HostTypeDef;
1810 
1811 /**
1812   * @brief USB_OTG_Host_Channel_Specific_Registers
1813   */
1814 typedef struct
1815 {
1816   __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
1817   __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
1818   __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
1819   __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
1820   __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
1821   __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
1822   uint32_t Reserved[2];           /*!< Reserved                                      */
1823 } USB_OTG_HostChannelTypeDef;
1824 /**
1825   * @}
1826   */
1827 
1828 /**
1829   * @brief OCTO Serial Peripheral Interface
1830   */
1831 
1832 typedef struct
1833 {
1834   __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */
1835   uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */
1836   __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */
1837   __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */
1838   __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */
1839   __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */
1840   uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */
1841   __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */
1842   __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */
1843   uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */
1844   __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */
1845   uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */
1846   __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */
1847   uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */
1848   __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */
1849   uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */
1850   __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */
1851   uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */
1852   __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */
1853   uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */
1854   __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */
1855   uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */
1856   __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */
1857   uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */
1858   __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */
1859   uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */
1860   __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */
1861   uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */
1862   __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */
1863   uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */
1864   __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */
1865   uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */
1866   __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */
1867   uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */
1868   __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */
1869   uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */
1870   __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */
1871   uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */
1872   __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */
1873   uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */
1874   __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
1875   uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */
1876   __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */
1877   uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */
1878   __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */
1879   uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */
1880   __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */
1881   uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */
1882   __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */
1883   uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */
1884   __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */
1885   __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */
1886   __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */
1887   __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */
1888 } OCTOSPI_TypeDef;
1889 
1890 /**
1891   * @}
1892   */
1893 /**
1894   * @brief OCTO Serial Peripheral Interface IO Manager
1895   */
1896 
1897 typedef struct
1898 {
1899   __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */
1900   __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */
1901 } OCTOSPIM_TypeDef;
1902 
1903 /**
1904   * @}
1905   */
1906 
1907 /**
1908   * @brief OTFD register
1909   */
1910 typedef struct
1911 {
1912   __IO uint32_t REG_CONFIGR;
1913   __IO uint32_t REG_START_ADDR;
1914   __IO uint32_t REG_END_ADDR;
1915   __IO uint32_t REG_NONCER0;
1916   __IO uint32_t REG_NONCER1;
1917   __IO uint32_t REG_KEYR0;
1918   __IO uint32_t REG_KEYR1;
1919   __IO uint32_t REG_KEYR2;
1920   __IO uint32_t REG_KEYR3;
1921 } OTFDEC_Region_TypeDef;
1922 
1923 typedef struct
1924 {
1925   __IO uint32_t CR;
1926   uint32_t RESERVED1[191];
1927   __IO uint32_t ISR;
1928   __IO uint32_t ICR;
1929   __IO uint32_t IER;
1930   uint32_t RESERVED2[56];
1931   __IO uint32_t HWCFGR2;
1932   __IO uint32_t HWCFGR1;
1933   __IO uint32_t VERR;
1934   __IO uint32_t IPIDR;
1935   __IO uint32_t SIDR;
1936 } OTFDEC_TypeDef;
1937 /**
1938   * @}
1939   */
1940 
1941 /**
1942   * @brief Global Programmer View
1943   */
1944 
1945 typedef struct
1946 {
1947   uint32_t      RESERVED0[2036];     /*!< Reserved,                                                                           Address offset: 0x00-0x1FCC     */
1948   __IO uint32_t AXI_PERIPH_ID_4;     /*!< AXI interconnect - peripheral ID4 register,                                         Address offset: 0x1FD0          */
1949   uint32_t      AXI_PERIPH_ID_5;     /*!< Reserved,                                                                           Address offset: 0x1FD4          */
1950   uint32_t      AXI_PERIPH_ID_6;     /*!< Reserved,                                                                           Address offset: 0x1FD8          */
1951   uint32_t      AXI_PERIPH_ID_7;     /*!< Reserved,                                                                           Address offset: 0x1FDC          */
1952   __IO uint32_t AXI_PERIPH_ID_0;     /*!< AXI interconnect - peripheral ID0 register,                                         Address offset: 0x1FE0          */
1953   __IO uint32_t AXI_PERIPH_ID_1;     /*!< AXI interconnect - peripheral ID1 register,                                         Address offset: 0x1FE4          */
1954   __IO uint32_t AXI_PERIPH_ID_2;     /*!< AXI interconnect - peripheral ID2 register,                                         Address offset: 0x1FE8          */
1955   __IO uint32_t AXI_PERIPH_ID_3;     /*!< AXI interconnect - peripheral ID3 register,                                         Address offset: 0x1FEC          */
1956   __IO uint32_t AXI_COMP_ID_0;       /*!< AXI interconnect - component ID0 register,                                          Address offset: 0x1FF0          */
1957   __IO uint32_t AXI_COMP_ID_1;       /*!< AXI interconnect - component ID1 register,                                          Address offset: 0x1FF4          */
1958   __IO uint32_t AXI_COMP_ID_2;       /*!< AXI interconnect - component ID2 register,                                          Address offset: 0x1FF8          */
1959   __IO uint32_t AXI_COMP_ID_3;       /*!< AXI interconnect - component ID3 register,                                          Address offset: 0x1FFC          */
1960   uint32_t      RESERVED1[2];        /*!< Reserved,                                                                           Address offset: 0x2000-0x2004   */
1961   __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register,           Address offset: 0x2008          */
1962   uint32_t      RESERVED2[6];        /*!< Reserved,                                                                           Address offset: 0x200C-0x2020   */
1963   __IO uint32_t AXI_TARG1_FN_MOD2;   /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register,                      Address offset: 0x2024          */
1964   uint32_t      RESERVED3;           /*!< Reserved,                                                                           Address offset: 0x2028          */
1965   __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register,           Address offset: 0x202C          */
1966   uint32_t      RESERVED4[54];       /*!< Reserved,                                                                           Address offset: 0x2030-0x2104   */
1967   __IO uint32_t AXI_TARG1_FN_MOD;    /*!< AXI interconnect - TARG 1 issuing functionality modification register,              Address offset: 0x2108          */
1968   uint32_t      RESERVED5[959];      /*!< Reserved,                                                                           Address offset: 0x210C-0x3004   */
1969   __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register,           Address offset: 0x3008          */
1970   uint32_t      RESERVED6[6];        /*!< Reserved,                                                                           Address offset: 0x300C-0x3020   */
1971   __IO uint32_t AXI_TARG2_FN_MOD2;   /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register,                      Address offset: 0x3024          */
1972   uint32_t      RESERVED7;           /*!< Reserved,                                                                           Address offset: 0x3028          */
1973   __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register,           Address offset: 0x302C          */
1974   uint32_t      RESERVED8[54];       /*!< Reserved,                                                                           Address offset: 0x3030-0x3104   */
1975   __IO uint32_t AXI_TARG2_FN_MOD;    /*!< AXI interconnect - TARG 2 issuing functionality modification register,              Address offset: 0x3108          */
1976   uint32_t      RESERVED9[959];      /*!< Reserved,                                                                           Address offset: 0x310C-0x4004   */
1977   __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;   /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register,          Address offset: 0x4008          */
1978   uint32_t      RESERVED10[1023];    /*!< Reserved,                                                                           Address offset: 0x400C-0x5004   */
1979   __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register,           Address offset: 0x5008          */
1980   uint32_t      RESERVED11[1023];    /*!< Reserved,                                                                           Address offset: 0x500C-0x6004   */
1981   __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register,           Address offset: 0x6008          */
1982   uint32_t      RESERVED12[1023];    /*!< Reserved,                                                                           Address offset: 0x600C-0x7004   */
1983   __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register,           Address offset: 0x7008          */
1984   uint32_t      RESERVED13[1023];    /*!< Reserved,                                                                           Address offset: 0x700C-0x8004   */
1985   __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register,           Address offset: 0x8008          */
1986   uint32_t      RESERVED14[6];       /*!< Reserved,                                                                           Address offset: 0x800C-0x8020   */
1987   __IO uint32_t AXI_TARG7_FN_MOD2;   /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register,                      Address offset: 0x8024          */
1988   uint32_t      RESERVED15;          /*!< Reserved,                                                                           Address offset: 0x8028          */
1989   __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register,           Address offset: 0x802C          */
1990   uint32_t      RESERVED16[54];      /*!< Reserved,                                                                           Address offset: 0x8030-0x8104   */
1991   __IO uint32_t AXI_TARG7_FN_MOD;    /*!< AXI interconnect - TARG 7 issuing functionality modification register,              Address offset: 0x8108          */
1992   uint32_t      RESERVED17[959];     /*!< Reserved,                                                                           Address offset: 0x810C-0x9004   */
1993   __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register,           Address offset: 0x9008          */
1994   uint32_t      RESERVED117[6];      /*!< Reserved,                                                                           Address offset: 0x900C-0x9020   */
1995   __IO uint32_t AXI_TARG8_FN_MOD2;   /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register,                      Address offset: 0x9024          */
1996   uint32_t      RESERVED118[56];     /*!< Reserved,                                                                           Address offset: 0x9028-0x9104   */
1997   __IO uint32_t AXI_TARG8_FN_MOD;    /*!< AXI interconnect - TARG 8 issuing functionality modification register,              Address offset: 0x9108          */
1998   uint32_t      RESERVED119[959];    /*!< Reserved,                                                                           Address offset: 0x910C-0xA004   */
1999   __IO uint32_t AXI_TARG9_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 9 bus matrix issuing functionality register,            Address offset: 0xA008          */
2000   uint32_t      RESERVED120[6];      /*!< Reserved,                                                                           Address offset: 0xA00C-0xA020   */
2001   __IO uint32_t AXI_TARG9_FN_MOD2;   /*!< AXI interconnect - TARG 9 bus matrix functionality 2 register,                      Address offset: 0xA024          */
2002   uint32_t      RESERVED121[56];     /*!< Reserved,                                                                           Address offset: 0xA028-0xA104   */
2003   __IO uint32_t AXI_TARG9_FN_MOD;    /*!< AXI interconnect - TARG 9 issuing functionality modification register,              Address offset: 0xA108          */
2004   uint32_t      RESERVED122[959];    /*!< Reserved,                                                                           Address offset: 0xA10C-0xB004   */
2005   __IO uint32_t AXI_TARG10_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 10 bus matrix issuing functionality register,          Address offset: 0xB008          */
2006   uint32_t      RESERVED123[6];      /*!< Reserved,                                                                           Address offset: 0xB00C-0xB020   */
2007   __IO uint32_t AXI_TARG10_FN_MOD2;  /*!< AXI interconnect - TARG 10 bus matrix functionality 2 register,                     Address offset: 0xB024          */
2008   uint32_t      RESERVED124[56];     /*!< Reserved,                                                                           Address offset: 0xB028-0xB104   */
2009   __IO uint32_t AXI_TARG10_FN_MOD;   /*!< AXI interconnect - TARG 10 issuing functionality modification register,             Address offset: 0xB108          */
2010   uint32_t      RESERVED125[968];    /*!< Reserved,                                                                           Address offset: 0xB10C-0xC028   */
2011   __IO uint32_t AXI_TARG10_FN_MOD_LB; /*!< AXI interconnect - TARG 10 long burst functionality modification register,         Address offset: 0xC02C          */
2012   uint32_t      RESERVED126[55293];  /*!< Reserved,                                                                           Address offset: 0xC030-0xC104   */
2013   __IO uint32_t AXI_INI1_FN_MOD2;    /*!< AXI interconnect - INI 1 functionality modification 2 register,                     Address offset: 0x42024         */
2014   __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register,                   Address offset: 0x42028         */
2015   uint32_t      RESERVED18[53];      /*!< Reserved,                                                                           Address offset: 0x4202C-0x420FC */
2016   __IO uint32_t AXI_INI1_READ_QOS;   /*!< AXI interconnect - INI 1 read QoS register,                                         Address offset: 0x42100         */
2017   __IO uint32_t AXI_INI1_WRITE_QOS;  /*!< AXI interconnect - INI 1 write QoS register,                                        Address offset: 0x42104         */
2018   __IO uint32_t AXI_INI1_FN_MOD;     /*!< AXI interconnect - INI 1 issuing functionality modification register,               Address offset: 0x42108         */
2019   uint32_t      RESERVED19[1021];    /*!< Reserved,                                                                           Address offset: 0x4210C-0x430FC */
2020   __IO uint32_t AXI_INI2_READ_QOS;   /*!< AXI interconnect - INI 2 read QoS register,                                         Address offset: 0x43100         */
2021   __IO uint32_t AXI_INI2_WRITE_QOS;  /*!< AXI interconnect - INI 2 write QoS register,                                        Address offset: 0x43104         */
2022   __IO uint32_t AXI_INI2_FN_MOD;     /*!< AXI interconnect - INI 2 issuing functionality modification register,               Address offset: 0x43108         */
2023   uint32_t      RESERVED20[966];     /*!< Reserved,                                                                           Address offset: 0x4310C-0x44020 */
2024   __IO uint32_t AXI_INI3_FN_MOD2;    /*!< AXI interconnect - INI 3 functionality modification 2 register,                     Address offset: 0x44024         */
2025   __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register,                   Address offset: 0x44028         */
2026   uint32_t      RESERVED21[53];      /*!< Reserved,                                                                           Address offset: 0x4402C-0x440FC */
2027   __IO uint32_t AXI_INI3_READ_QOS;   /*!< AXI interconnect - INI 3 read QoS register,                                         Address offset: 0x44100         */
2028   __IO uint32_t AXI_INI3_WRITE_QOS;  /*!< AXI interconnect - INI 3 write QoS register,                                        Address offset: 0x44104         */
2029   __IO uint32_t AXI_INI3_FN_MOD;     /*!< AXI interconnect - INI 3 issuing functionality modification register,               Address offset: 0x44108         */
2030   uint32_t      RESERVED22[1021];    /*!< Reserved,                                                                           Address offset: 0x4410C-0x450FC */
2031   __IO uint32_t AXI_INI4_READ_QOS;   /*!< AXI interconnect - INI 4 read QoS register,                                         Address offset: 0x45100         */
2032   __IO uint32_t AXI_INI4_WRITE_QOS;  /*!< AXI interconnect - INI 4 write QoS register,                                        Address offset: 0x45104         */
2033   __IO uint32_t AXI_INI4_FN_MOD;     /*!< AXI interconnect - INI 4 issuing functionality modification register,               Address offset: 0x45108         */
2034   uint32_t      RESERVED23[1021];    /*!< Reserved,                                                                           Address offset: 0x4510C-0x460FC */
2035   __IO uint32_t AXI_INI5_READ_QOS;   /*!< AXI interconnect - INI 5 read QoS register,                                         Address offset: 0x46100         */
2036   __IO uint32_t AXI_INI5_WRITE_QOS;  /*!< AXI interconnect - INI 5 write QoS register,                                        Address offset: 0x46104         */
2037   __IO uint32_t AXI_INI5_FN_MOD;     /*!< AXI interconnect - INI 5 issuing functionality modification register,               Address offset: 0x46108         */
2038   uint32_t      RESERVED24[1021];    /*!< Reserved,                                                                           Address offset: 0x4610C-0x470FC */
2039   __IO uint32_t AXI_INI6_READ_QOS;   /*!< AXI interconnect - INI 6 read QoS register,                                         Address offset: 0x47100         */
2040   __IO uint32_t AXI_INI6_WRITE_QOS;  /*!< AXI interconnect - INI 6 write QoS register,                                        Address offset: 0x47104         */
2041   __IO uint32_t AXI_INI6_FN_MOD;     /*!< AXI interconnect - INI 6 issuing functionality modification register,               Address offset: 0x47108         */
2042   uint32_t      RESERVED25[966];     /*!< Reserved,                                                                           Address offset: 0x4710C-0x48020 */
2043   __IO uint32_t AXI_INI7_FN_MOD2;    /*!< AXI interconnect - INI 7 functionality modification 2 register,                     Address offset: 0x48024         */
2044   __IO uint32_t AXI_INI7_FN_MOD_AHB; /*!< AXI interconnect - INI 7 AHB functionality modification register,                   Address offset: 0x48028         */
2045   uint32_t      RESERVED26[53];      /*!< Reserved,                                                                           Address offset: 0x4802C-0x480FC */
2046   __IO uint32_t AXI_INI7_READ_QOS;   /*!< AXI interconnect - INI 7 read QoS register,                                         Address offset: 0x48100         */
2047   __IO uint32_t AXI_INI7_WRITE_QOS;  /*!< AXI interconnect - INI 7 write QoS register,                                        Address offset: 0x48104         */
2048   __IO uint32_t AXI_INI7_FN_MOD;     /*!< AXI interconnect - INI 7 issuing functionality modification register,               Address offset: 0x48108         */
2049 
2050 } GPV_TypeDef;
2051 
2052 /** @addtogroup Peripheral_memory_map
2053   * @{
2054   */
2055 #define CD_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */
2056 #define CD_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM                   */
2057 #define CD_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
2058 
2059 #define CD_AXISRAM1_BASE          (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI                */
2060 #define CD_AXISRAM2_BASE          (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI                */
2061 #define CD_AXISRAM3_BASE          (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI                */
2062 #define CD_AHBSRAM1_BASE          (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge     */
2063 #define CD_AHBSRAM2_BASE          (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge     */
2064 
2065 #define SRD_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */
2066 #define SRD_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge                               */
2067 
2068 #define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */
2069 #define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */
2070 
2071 #define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */
2072 #define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */
2073 #define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */
2074 
2075 /* Legacy define */
2076 #define FLASH_BASE                FLASH_BANK1_BASE
2077 #define D1_AXISRAM_BASE           CD_AXISRAM1_BASE
2078 
2079 #define FLASH_OTP_BASE            (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area                           */
2080 #define FLASH_OTP_END             (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area                            */
2081 
2082 
2083 /*!< Device electronic signature memory map */
2084 #define UID_BASE                  (0x08FFF800UL)            /*!< Unique device ID register base address */
2085 #define FLASHSIZE_BASE            (0x08FFF80CUL)            /*!< FLASH Size register base address */
2086 #define PACKAGE_BASE              (0x08FFF80EUL)            /*!< Package Data register base address */
2087 
2088 #define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals                                                    */
2089 /*!< Peripheral memory map */
2090 #define CD_APB1PERIPH_BASE        PERIPH_BASE                   /*!<  D2_APB1PERIPH_BASE        PERIPH_BASE                                    */
2091 #define CD_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)   /*!<  D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)                    */
2092 #define CD_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)   /*!<  D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)                    */
2093 #define CD_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)   /*!<  D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)                    */
2094 
2095 #define CD_APB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)   /*!<  D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)                    */
2096 #define CD_AHB3PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)   /*!<  D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)                    */
2097 
2098 #define SRD_APB4PERIPH_BASE      (PERIPH_BASE + 0x18000000UL)   /*!<  D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)                    */
2099 #define SRD_AHB4PERIPH_BASE      (PERIPH_BASE + 0x18020000UL)   /*!<  D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)                    */
2100 
2101 /*!< Legacy Peripheral memory map */
2102 #define APB1PERIPH_BASE        PERIPH_BASE
2103 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
2104 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
2105 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)
2106 
2107 /*!< CD_AHB3PERIPH peripherals */
2108 #define MDMA_BASE             (CD_AHB3PERIPH_BASE + 0x0000UL)
2109 #define DMA2D_BASE            (CD_AHB3PERIPH_BASE + 0x1000UL)
2110 #define FLASH_R_BASE          (CD_AHB3PERIPH_BASE + 0x2000UL)
2111 #define JPGDEC_BASE           (CD_AHB3PERIPH_BASE + 0x3000UL)
2112 #define FMC_R_BASE            (CD_AHB3PERIPH_BASE + 0x4000UL)
2113 #define OCTOSPI1_R_BASE       (CD_AHB3PERIPH_BASE + 0x5000UL)
2114 #define DLYB_OCTOSPI1_BASE    (CD_AHB3PERIPH_BASE + 0x6000UL)
2115 #define SDMMC1_BASE           (CD_AHB3PERIPH_BASE + 0x7000UL)
2116 #define DLYB_SDMMC1_BASE      (CD_AHB3PERIPH_BASE + 0x8000UL)
2117 #define RAMECC_BASE           (CD_AHB3PERIPH_BASE + 0x9000UL)
2118 #define OCTOSPI2_R_BASE       (CD_AHB3PERIPH_BASE + 0xA000UL)
2119 #define DLYB_OCTOSPI2_BASE    (CD_AHB3PERIPH_BASE + 0xB000UL)
2120 #define OCTOSPIM_BASE         (CD_AHB3PERIPH_BASE + 0xB400UL)
2121 
2122 /*!< CD_AHB1PERIPH peripherals */
2123 
2124 #define DMA1_BASE               (CD_AHB1PERIPH_BASE + 0x0000UL)
2125 #define DMA2_BASE               (CD_AHB1PERIPH_BASE + 0x0400UL)
2126 #define DMAMUX1_BASE            (CD_AHB1PERIPH_BASE + 0x0800UL)
2127 #define ADC1_BASE               (CD_AHB1PERIPH_BASE + 0x2000UL)
2128 #define ADC2_BASE               (CD_AHB1PERIPH_BASE + 0x2100UL)
2129 #define ADC12_COMMON_BASE       (CD_AHB1PERIPH_BASE + 0x2300UL)
2130 #define CRC_BASE                (CD_AHB1PERIPH_BASE + 0x3000UL)
2131 
2132 /*!< USB registers base address */
2133 #define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)
2134 #define USB_OTG_GLOBAL_BASE                  (0x000UL)
2135 #define USB_OTG_DEVICE_BASE                  (0x800UL)
2136 #define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)
2137 #define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)
2138 #define USB_OTG_EP_REG_SIZE                  (0x20UL)
2139 #define USB_OTG_HOST_BASE                    (0x400UL)
2140 #define USB_OTG_HOST_PORT_BASE               (0x440UL)
2141 #define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)
2142 #define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)
2143 #define USB_OTG_PCGCCTL_BASE                 (0xE00UL)
2144 #define USB_OTG_FIFO_BASE                    (0x1000UL)
2145 #define USB_OTG_FIFO_SIZE                    (0x1000UL)
2146 
2147 /*!< CD_AHB2PERIPH peripherals */
2148 
2149 #define DCMI_BASE              (CD_AHB2PERIPH_BASE + 0x0000UL)
2150 #define PSSI_BASE              (CD_AHB2PERIPH_BASE + 0x0400UL)
2151 #define HSEM_BASE              (CD_AHB2PERIPH_BASE + 0x0800UL)
2152 #define CRYP_BASE              (CD_AHB2PERIPH_BASE + 0x1000UL)
2153 #define HASH_BASE              (CD_AHB2PERIPH_BASE + 0x1400UL)
2154 #define HASH_DIGEST_BASE       (CD_AHB2PERIPH_BASE + 0x1710UL)
2155 #define RNG_BASE               (CD_AHB2PERIPH_BASE + 0x1800UL)
2156 #define SDMMC2_BASE            (CD_AHB2PERIPH_BASE + 0x2400UL)
2157 #define DLYB_SDMMC2_BASE       (CD_AHB2PERIPH_BASE + 0x2800UL)
2158 #define BDMA1_BASE             (CD_AHB2PERIPH_BASE + 0x2C00UL)
2159 
2160 /*!< SRD_AHB4PERIPH peripherals */
2161 #define GPIOA_BASE            (SRD_AHB4PERIPH_BASE + 0x0000UL)
2162 #define GPIOB_BASE            (SRD_AHB4PERIPH_BASE + 0x0400UL)
2163 #define GPIOC_BASE            (SRD_AHB4PERIPH_BASE + 0x0800UL)
2164 #define GPIOD_BASE            (SRD_AHB4PERIPH_BASE + 0x0C00UL)
2165 #define GPIOE_BASE            (SRD_AHB4PERIPH_BASE + 0x1000UL)
2166 #define GPIOF_BASE            (SRD_AHB4PERIPH_BASE + 0x1400UL)
2167 #define GPIOG_BASE            (SRD_AHB4PERIPH_BASE + 0x1800UL)
2168 #define GPIOH_BASE            (SRD_AHB4PERIPH_BASE + 0x1C00UL)
2169 #define GPIOI_BASE            (SRD_AHB4PERIPH_BASE + 0x2000UL)
2170 #define GPIOJ_BASE            (SRD_AHB4PERIPH_BASE + 0x2400UL)
2171 #define GPIOK_BASE            (SRD_AHB4PERIPH_BASE + 0x2800UL)
2172 #define RCC_BASE              (SRD_AHB4PERIPH_BASE + 0x4400UL)
2173 #define PWR_BASE              (SRD_AHB4PERIPH_BASE + 0x4800UL)
2174 #define BDMA2_BASE            (SRD_AHB4PERIPH_BASE + 0x5400UL)
2175 #define DMAMUX2_BASE          (SRD_AHB4PERIPH_BASE + 0x5800UL)
2176 
2177 /*!< CD_APB3PERIPH peripherals */
2178 #define LTDC_BASE             (CD_APB3PERIPH_BASE + 0x1000UL)
2179 #define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
2180 #define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
2181 #define WWDG1_BASE            (CD_APB3PERIPH_BASE + 0x3000UL)
2182 
2183 /*!< CD_APB1PERIPH peripherals */
2184 #define TIM2_BASE             (CD_APB1PERIPH_BASE + 0x0000UL)
2185 #define TIM3_BASE             (CD_APB1PERIPH_BASE + 0x0400UL)
2186 #define TIM4_BASE             (CD_APB1PERIPH_BASE + 0x0800UL)
2187 #define TIM5_BASE             (CD_APB1PERIPH_BASE + 0x0C00UL)
2188 #define TIM6_BASE             (CD_APB1PERIPH_BASE + 0x1000UL)
2189 #define TIM7_BASE             (CD_APB1PERIPH_BASE + 0x1400UL)
2190 #define TIM12_BASE            (CD_APB1PERIPH_BASE + 0x1800UL)
2191 #define TIM13_BASE            (CD_APB1PERIPH_BASE + 0x1C00UL)
2192 #define TIM14_BASE            (CD_APB1PERIPH_BASE + 0x2000UL)
2193 #define LPTIM1_BASE           (CD_APB1PERIPH_BASE + 0x2400UL)
2194 
2195 #define SPI2_BASE             (CD_APB1PERIPH_BASE + 0x3800UL)
2196 #define SPI3_BASE             (CD_APB1PERIPH_BASE + 0x3C00UL)
2197 #define SPDIFRX_BASE          (CD_APB1PERIPH_BASE + 0x4000UL)
2198 #define USART2_BASE           (CD_APB1PERIPH_BASE + 0x4400UL)
2199 #define USART3_BASE           (CD_APB1PERIPH_BASE + 0x4800UL)
2200 #define UART4_BASE            (CD_APB1PERIPH_BASE + 0x4C00UL)
2201 #define UART5_BASE            (CD_APB1PERIPH_BASE + 0x5000UL)
2202 #define I2C1_BASE             (CD_APB1PERIPH_BASE + 0x5400UL)
2203 #define I2C2_BASE             (CD_APB1PERIPH_BASE + 0x5800UL)
2204 #define I2C3_BASE             (CD_APB1PERIPH_BASE + 0x5C00UL)
2205 #define CEC_BASE              (CD_APB1PERIPH_BASE + 0x6C00UL)
2206 #define DAC1_BASE             (CD_APB1PERIPH_BASE + 0x7400UL)
2207 #define UART7_BASE            (CD_APB1PERIPH_BASE + 0x7800UL)
2208 #define UART8_BASE            (CD_APB1PERIPH_BASE + 0x7C00UL)
2209 #define CRS_BASE              (CD_APB1PERIPH_BASE + 0x8400UL)
2210 #define SWPMI1_BASE           (CD_APB1PERIPH_BASE + 0x8800UL)
2211 #define OPAMP_BASE            (CD_APB1PERIPH_BASE + 0x9000UL)
2212 #define OPAMP1_BASE           (CD_APB1PERIPH_BASE + 0x9000UL)
2213 #define OPAMP2_BASE           (CD_APB1PERIPH_BASE + 0x9010UL)
2214 #define MDIOS_BASE            (CD_APB1PERIPH_BASE + 0x9400UL)
2215 #define FDCAN1_BASE           (CD_APB1PERIPH_BASE + 0xA000UL)
2216 #define FDCAN2_BASE           (CD_APB1PERIPH_BASE + 0xA400UL)
2217 #define FDCAN_CCU_BASE        (CD_APB1PERIPH_BASE + 0xA800UL)
2218 #define SRAMCAN_BASE          (CD_APB1PERIPH_BASE + 0xAC00UL)
2219 
2220 /*!< CD_APB2PERIPH peripherals */
2221 
2222 #define TIM1_BASE             (CD_APB2PERIPH_BASE + 0x0000UL)
2223 #define TIM8_BASE             (CD_APB2PERIPH_BASE + 0x0400UL)
2224 #define USART1_BASE           (CD_APB2PERIPH_BASE + 0x1000UL)
2225 #define USART6_BASE           (CD_APB2PERIPH_BASE + 0x1400UL)
2226 #define UART9_BASE            (CD_APB2PERIPH_BASE + 0x1800UL)
2227 #define USART10_BASE          (CD_APB2PERIPH_BASE + 0x1C00UL)
2228 #define SPI1_BASE             (CD_APB2PERIPH_BASE + 0x3000UL)
2229 #define SPI4_BASE             (CD_APB2PERIPH_BASE + 0x3400UL)
2230 #define TIM15_BASE            (CD_APB2PERIPH_BASE + 0x4000UL)
2231 #define TIM16_BASE            (CD_APB2PERIPH_BASE + 0x4400UL)
2232 #define TIM17_BASE            (CD_APB2PERIPH_BASE + 0x4800UL)
2233 #define SPI5_BASE             (CD_APB2PERIPH_BASE + 0x5000UL)
2234 #define SAI1_BASE             (CD_APB2PERIPH_BASE + 0x5800UL)
2235 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
2236 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
2237 #define SAI2_BASE             (CD_APB2PERIPH_BASE + 0x5C00UL)
2238 #define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
2239 #define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
2240 #define DFSDM1_BASE           (CD_APB2PERIPH_BASE + 0x7800UL)
2241 #define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
2242 #define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
2243 #define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
2244 #define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
2245 #define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)
2246 #define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)
2247 #define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)
2248 #define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)
2249 #define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
2250 #define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
2251 #define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
2252 #define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
2253 #define DFSDM1_Filter4_BASE   (DFSDM1_BASE + 0x300UL)
2254 #define DFSDM1_Filter5_BASE   (DFSDM1_BASE + 0x380UL)
2255 #define DFSDM1_Filter6_BASE   (DFSDM1_BASE + 0x400UL)
2256 #define DFSDM1_Filter7_BASE   (DFSDM1_BASE + 0x480UL)
2257 /*!< SRD_APB4PERIPH peripherals */
2258 #define EXTI_BASE             (SRD_APB4PERIPH_BASE + 0x0000UL)
2259 #define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)
2260 #define SYSCFG_BASE           (SRD_APB4PERIPH_BASE + 0x0400UL)
2261 #define LPUART1_BASE          (SRD_APB4PERIPH_BASE + 0x0C00UL)
2262 #define SPI6_BASE             (SRD_APB4PERIPH_BASE + 0x1400UL)
2263 #define I2C4_BASE             (SRD_APB4PERIPH_BASE + 0x1C00UL)
2264 #define LPTIM2_BASE           (SRD_APB4PERIPH_BASE + 0x2400UL)
2265 #define LPTIM3_BASE           (SRD_APB4PERIPH_BASE + 0x2800UL)
2266 #define DAC2_BASE             (SRD_APB4PERIPH_BASE + 0x3400UL)
2267 #define COMP12_BASE           (SRD_APB4PERIPH_BASE + 0x3800UL)
2268 #define COMP1_BASE            (COMP12_BASE + 0x0CUL)
2269 #define COMP2_BASE            (COMP12_BASE + 0x10UL)
2270 #define VREFBUF_BASE          (SRD_APB4PERIPH_BASE + 0x3C00UL)
2271 #define RTC_BASE              (SRD_APB4PERIPH_BASE + 0x4000UL)
2272 #define TAMP_BASE             (SRD_APB4PERIPH_BASE + 0x4400UL)
2273 #define IWDG1_BASE            (SRD_APB4PERIPH_BASE + 0x4800UL)
2274 
2275 #define DTS_BASE              (SRD_APB4PERIPH_BASE + 0x6800UL)
2276 
2277 #define DFSDM2_BASE           (SRD_APB4PERIPH_BASE + 0x6C00UL)
2278 #define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)
2279 #define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)
2280 #define DFSDM2_FLT0_BASE      (DFSDM2_BASE + 0x100UL)
2281 
2282 /*!< CD_AHB3PERIPH peripherals */
2283 
2284 #define OTFDEC1_BASE          (CD_AHB3PERIPH_BASE + 0xB800UL)
2285 #define OTFDEC1_REGION1_BASE  (OTFDEC1_BASE + 0x20UL)
2286 #define OTFDEC1_REGION2_BASE  (OTFDEC1_BASE + 0x50UL)
2287 #define OTFDEC1_REGION3_BASE  (OTFDEC1_BASE + 0x80UL)
2288 #define OTFDEC1_REGION4_BASE  (OTFDEC1_BASE + 0xB0UL)
2289 #define OTFDEC2_BASE          (CD_AHB3PERIPH_BASE + 0xBC00UL)
2290 #define OTFDEC2_REGION1_BASE  (OTFDEC2_BASE + 0x20UL)
2291 #define OTFDEC2_REGION2_BASE  (OTFDEC2_BASE + 0x50UL)
2292 #define OTFDEC2_REGION3_BASE  (OTFDEC2_BASE + 0x80UL)
2293 #define OTFDEC2_REGION4_BASE  (OTFDEC2_BASE + 0xB0UL)
2294 #define GFXMMU_BASE           (CD_AHB3PERIPH_BASE + 0xC000UL)
2295 
2296 #define BDMA1_Channel0_BASE    (BDMA1_BASE + 0x0008UL)
2297 #define BDMA1_Channel1_BASE    (BDMA1_BASE + 0x001CUL)
2298 #define BDMA1_Channel2_BASE    (BDMA1_BASE + 0x0030UL)
2299 #define BDMA1_Channel3_BASE    (BDMA1_BASE + 0x0044UL)
2300 #define BDMA1_Channel4_BASE    (BDMA1_BASE + 0x0058UL)
2301 #define BDMA1_Channel5_BASE    (BDMA1_BASE + 0x006CUL)
2302 #define BDMA1_Channel6_BASE    (BDMA1_BASE + 0x0080UL)
2303 #define BDMA1_Channel7_BASE    (BDMA1_BASE + 0x0094UL)
2304 
2305 #define BDMA2_Channel0_BASE    (BDMA2_BASE + 0x0008UL)
2306 #define BDMA2_Channel1_BASE    (BDMA2_BASE + 0x001CUL)
2307 #define BDMA2_Channel2_BASE    (BDMA2_BASE + 0x0030UL)
2308 #define BDMA2_Channel3_BASE    (BDMA2_BASE + 0x0044UL)
2309 #define BDMA2_Channel4_BASE    (BDMA2_BASE + 0x0058UL)
2310 #define BDMA2_Channel5_BASE    (BDMA2_BASE + 0x006CUL)
2311 #define BDMA2_Channel6_BASE    (BDMA2_BASE + 0x0080UL)
2312 #define BDMA2_Channel7_BASE    (BDMA2_BASE + 0x0094UL)
2313 
2314 
2315 #define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)
2316 #define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)
2317 #define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)
2318 #define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)
2319 #define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)
2320 #define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)
2321 #define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)
2322 #define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)
2323 
2324 #define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)
2325 #define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)
2326 #define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)
2327 #define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)
2328 #define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)
2329 #define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)
2330 #define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)
2331 #define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)
2332 
2333 #define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)
2334 #define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
2335 
2336 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
2337 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
2338 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
2339 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
2340 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
2341 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
2342 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
2343 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
2344 
2345 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
2346 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
2347 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
2348 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
2349 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
2350 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
2351 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
2352 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
2353 
2354 
2355 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
2356 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
2357 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
2358 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
2359 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
2360 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
2361 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
2362 #define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
2363 #define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
2364 #define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
2365 #define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
2366 #define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
2367 #define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
2368 #define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
2369 #define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
2370 #define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
2371 
2372 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
2373 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
2374 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
2375 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
2376 #define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)
2377 #define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)
2378 #define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)
2379 #define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)
2380 
2381 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
2382 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
2383 
2384 /*!< FMC Banks registers base  address */
2385 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
2386 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
2387 #define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)
2388 #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
2389 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
2390 
2391 /* Debug MCU registers base address */
2392 #define DBGMCU_BASE           (0x5C001000UL)
2393 
2394 #define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)
2395 #define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)
2396 #define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)
2397 #define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)
2398 #define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)
2399 #define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)
2400 #define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)
2401 #define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)
2402 #define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)
2403 #define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)
2404 #define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
2405 #define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
2406 #define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
2407 #define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
2408 #define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
2409 #define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
2410 
2411 /* GFXMMU virtual buffers base address */
2412 #define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)
2413 #define GFXMMU_VIRTUAL_BUFFER0_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE)
2414 #define GFXMMU_VIRTUAL_BUFFER1_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)
2415 #define GFXMMU_VIRTUAL_BUFFER2_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)
2416 #define GFXMMU_VIRTUAL_BUFFER3_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)
2417 
2418 #define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)
2419 #define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
2420 #define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
2421 
2422 
2423 #define GPV_BASE       (PERIPH_BASE + 0x11000000UL)   /*!<  GPV_BASE       (PERIPH_BASE + 0x11000000UL)                    */
2424 
2425 /**
2426   * @}
2427   */
2428 
2429 /** @addtogroup Peripheral_declaration
2430   * @{
2431   */
2432 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
2433 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
2434 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
2435 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
2436 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
2437 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
2438 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
2439 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
2440 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
2441 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
2442 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
2443 #define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)
2444 
2445 
2446 #define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)
2447 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
2448 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
2449 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
2450 #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
2451 #define SPI6                ((SPI_TypeDef *) SPI6_BASE)
2452 #define USART2              ((USART_TypeDef *) USART2_BASE)
2453 #define USART3              ((USART_TypeDef *) USART3_BASE)
2454 #define USART6              ((USART_TypeDef *) USART6_BASE)
2455 #define USART10             ((USART_TypeDef *) USART10_BASE)
2456 #define UART7               ((USART_TypeDef *) UART7_BASE)
2457 #define UART8               ((USART_TypeDef *) UART8_BASE)
2458 #define UART9               ((USART_TypeDef *) UART9_BASE)
2459 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
2460 #define UART4               ((USART_TypeDef *) UART4_BASE)
2461 #define UART5               ((USART_TypeDef *) UART5_BASE)
2462 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
2463 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
2464 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
2465 #define I2C4                ((I2C_TypeDef *) I2C4_BASE)
2466 #define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2467 #define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2468 #define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2469 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
2470 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
2471 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
2472 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
2473 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
2474 #define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
2475 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
2476 #define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
2477 #define DTS                 ((DTS_TypeDef *) DTS_BASE)
2478 
2479 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
2480 #define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)
2481 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
2482 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
2483 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
2484 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
2485 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
2486 #define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
2487 
2488 
2489 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
2490 #define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2491 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
2492 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
2493 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
2494 #define USART1              ((USART_TypeDef *) USART1_BASE)
2495 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
2496 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
2497 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
2498 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
2499 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
2500 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2501 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2502 #define SAI2                ((SAI_TypeDef *) SAI2_BASE)
2503 #define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2504 #define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2505 
2506 #define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2507 #define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2508 #define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2509 #define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2510 #define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2511 #define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2512 #define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2513 #define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2514 #define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2515 #define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2516 #define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2517 #define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2518 #define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2519 #define DFSDM1_Filter4      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
2520 #define DFSDM1_Filter5      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
2521 #define DFSDM1_Filter6      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)
2522 #define DFSDM1_Filter7      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)
2523 #define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
2524 #define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
2525 #define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)
2526 #define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)
2527 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
2528 #define PSSI                ((PSSI_TypeDef *) PSSI_BASE)
2529 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
2530 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
2531 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
2532 
2533 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
2534 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
2535 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
2536 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
2537 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
2538 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
2539 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
2540 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
2541 #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
2542 #define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
2543 #define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
2544 
2545 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
2546 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
2547 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2548 
2549 #define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
2550 #define HASH                ((HASH_TypeDef *) HASH_BASE)
2551 #define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2552 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
2553 #define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
2554 #define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2555 
2556 #define BDMA1                ((BDMA_TypeDef *) BDMA1_BASE)
2557 #define BDMA1_Channel0       ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)
2558 #define BDMA1_Channel1       ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)
2559 #define BDMA1_Channel2       ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)
2560 #define BDMA1_Channel3       ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)
2561 #define BDMA1_Channel4       ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)
2562 #define BDMA1_Channel5       ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)
2563 #define BDMA1_Channel6       ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)
2564 #define BDMA1_Channel7       ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)
2565 
2566 #define BDMA2                ((BDMA_TypeDef *) BDMA2_BASE)
2567 #define BDMA2_Channel0       ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)
2568 #define BDMA2_Channel1       ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)
2569 #define BDMA2_Channel2       ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)
2570 #define BDMA2_Channel3       ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)
2571 #define BDMA2_Channel4       ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)
2572 #define BDMA2_Channel5       ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)
2573 #define BDMA2_Channel6       ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)
2574 #define BDMA2_Channel7       ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)
2575 
2576 #define RAMECC               ((RAMECC_TypeDef *)RAMECC_BASE)
2577 #define RAMECC_Monitor1      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)
2578 #define RAMECC_Monitor2      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)
2579 #define RAMECC_Monitor3      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)
2580 
2581 #define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2582 #define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2583 #define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2584 #define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2585 #define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2586 #define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2587 #define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2588 #define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2589 #define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2590 
2591 
2592 #define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2593 #define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2594 #define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2595 #define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2596 #define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2597 #define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2598 #define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2599 #define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2600 
2601 #define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2602 #define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2603 
2604 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
2605 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2606 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2607 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2608 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2609 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2610 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2611 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2612 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2613 
2614 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
2615 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2616 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2617 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2618 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2619 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2620 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2621 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2622 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2623 
2624 
2625 #define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2626 #define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2627 #define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2628 #define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2629 #define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2630 #define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2631 #define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2632 #define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2633 #define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2634 #define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2635 #define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2636 #define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2637 #define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2638 #define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2639 #define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2640 #define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2641 #define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2642 
2643 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2644 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2645 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2646 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2647 #define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2648 #define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2649 #define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2650 #define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2651 
2652 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)
2653 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2654 
2655 
2656 #define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2657 #define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2658 #define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2659 #define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2660 #define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2661 
2662 #define DAC2                ((DAC_TypeDef *) DAC2_BASE)
2663 #define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
2664 #define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
2665 #define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
2666 #define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
2667 #define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
2668 
2669 #define OTFDEC1               ((OTFDEC_TypeDef *) OTFDEC1_BASE)
2670 #define OTFDEC1_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)
2671 #define OTFDEC1_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)
2672 #define OTFDEC1_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)
2673 #define OTFDEC1_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)
2674 
2675 #define OTFDEC2               ((OTFDEC_TypeDef *) OTFDEC2_BASE)
2676 #define OTFDEC2_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)
2677 #define OTFDEC2_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)
2678 #define OTFDEC2_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)
2679 #define OTFDEC2_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)
2680 #define GFXMMU              ((GFXMMU_TypeDef *) GFXMMU_BASE)
2681 
2682 #define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)
2683 #define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2684 
2685 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
2686 
2687 #define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)
2688 #define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
2689 #define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2690 
2691 #define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
2692 #define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2693 #define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2694 
2695 #define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
2696 
2697 #define MDMA                ((MDMA_TypeDef *)MDMA_BASE)
2698 #define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2699 #define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2700 #define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2701 #define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2702 #define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2703 #define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2704 #define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2705 #define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2706 #define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2707 #define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2708 #define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2709 #define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2710 #define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2711 #define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2712 #define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2713 #define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2714 
2715 
2716 #define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2717 
2718 /* Legacy defines */
2719 #define USB_OTG_HS                   USB1_OTG_HS
2720 #define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE
2721 
2722 #define GPV                ((GPV_TypeDef *) GPV_BASE)
2723 
2724 /**
2725   * @}
2726   */
2727 
2728 /** @addtogroup Exported_constants
2729   * @{
2730   */
2731 
2732   /** @addtogroup Hardware_Constant_Definition
2733     * @{
2734     */
2735 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
2736 
2737   /**
2738     * @}
2739     */
2740 
2741   /** @addtogroup Peripheral_Registers_Bits_Definition
2742   * @{
2743   */
2744 
2745 /******************************************************************************/
2746 /*                         Peripheral Registers_Bits_Definition               */
2747 /******************************************************************************/
2748 
2749 /******************************************************************************/
2750 /*                                                                            */
2751 /*                        Analog to Digital Converter                         */
2752 /*                                                                            */
2753 /******************************************************************************/
2754 /*******************************  ADC VERSION  ********************************/
2755 #define ADC_VER_V5_3
2756 /********************  Bit definition for ADC_ISR register  ********************/
2757 #define ADC_ISR_ADRDY_Pos                 (0U)
2758 #define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */
2759 #define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */
2760 #define ADC_ISR_EOSMP_Pos                 (1U)
2761 #define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */
2762 #define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */
2763 #define ADC_ISR_EOC_Pos                   (2U)
2764 #define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */
2765 #define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */
2766 #define ADC_ISR_EOS_Pos                   (3U)
2767 #define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */
2768 #define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */
2769 #define ADC_ISR_OVR_Pos                   (4U)
2770 #define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */
2771 #define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */
2772 #define ADC_ISR_JEOC_Pos                  (5U)
2773 #define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */
2774 #define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */
2775 #define ADC_ISR_JEOS_Pos                  (6U)
2776 #define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */
2777 #define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */
2778 #define ADC_ISR_AWD1_Pos                  (7U)
2779 #define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */
2780 #define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */
2781 #define ADC_ISR_AWD2_Pos                  (8U)
2782 #define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */
2783 #define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */
2784 #define ADC_ISR_AWD3_Pos                  (9U)
2785 #define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */
2786 #define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */
2787 #define ADC_ISR_JQOVF_Pos                 (10U)
2788 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
2789 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
2790 #define ADC_ISR_LDORDY_Pos                (12U)
2791 #define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
2792 #define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
2793 
2794 /********************  Bit definition for ADC_IER register  ********************/
2795 #define ADC_IER_ADRDYIE_Pos               (0U)
2796 #define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */
2797 #define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */
2798 #define ADC_IER_EOSMPIE_Pos               (1U)
2799 #define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */
2800 #define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */
2801 #define ADC_IER_EOCIE_Pos                 (2U)
2802 #define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */
2803 #define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */
2804 #define ADC_IER_EOSIE_Pos                 (3U)
2805 #define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */
2806 #define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */
2807 #define ADC_IER_OVRIE_Pos                 (4U)
2808 #define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */
2809 #define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */
2810 #define ADC_IER_JEOCIE_Pos                (5U)
2811 #define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */
2812 #define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */
2813 #define ADC_IER_JEOSIE_Pos                (6U)
2814 #define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */
2815 #define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */
2816 #define ADC_IER_AWD1IE_Pos                (7U)
2817 #define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */
2818 #define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */
2819 #define ADC_IER_AWD2IE_Pos                (8U)
2820 #define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */
2821 #define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */
2822 #define ADC_IER_AWD3IE_Pos                (9U)
2823 #define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */
2824 #define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */
2825 #define ADC_IER_JQOVFIE_Pos               (10U)
2826 #define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */
2827 #define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */
2828 
2829 /********************  Bit definition for ADC_CR register  ********************/
2830 #define ADC_CR_ADEN_Pos                   (0U)
2831 #define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */
2832 #define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */
2833 #define ADC_CR_ADDIS_Pos                  (1U)
2834 #define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */
2835 #define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */
2836 #define ADC_CR_ADSTART_Pos                (2U)
2837 #define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */
2838 #define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */
2839 #define ADC_CR_JADSTART_Pos               (3U)
2840 #define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */
2841 #define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */
2842 #define ADC_CR_ADSTP_Pos                  (4U)
2843 #define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */
2844 #define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */
2845 #define ADC_CR_JADSTP_Pos                 (5U)
2846 #define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */
2847 #define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */
2848 #define ADC_CR_BOOST_Pos                  (8U)
2849 #define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */
2850 #define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */
2851 #define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */
2852 #define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */
2853 #define ADC_CR_ADCALLIN_Pos               (16U)
2854 #define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */
2855 #define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */
2856 #define ADC_CR_LINCALRDYW1_Pos            (22U)
2857 #define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */
2858 #define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */
2859 #define ADC_CR_LINCALRDYW2_Pos            (23U)
2860 #define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */
2861 #define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */
2862 #define ADC_CR_LINCALRDYW3_Pos            (24U)
2863 #define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */
2864 #define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */
2865 #define ADC_CR_LINCALRDYW4_Pos            (25U)
2866 #define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */
2867 #define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */
2868 #define ADC_CR_LINCALRDYW5_Pos            (26U)
2869 #define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */
2870 #define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */
2871 #define ADC_CR_LINCALRDYW6_Pos            (27U)
2872 #define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */
2873 #define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */
2874 #define ADC_CR_ADVREGEN_Pos               (28U)
2875 #define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */
2876 #define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */
2877 #define ADC_CR_DEEPPWD_Pos                (29U)
2878 #define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */
2879 #define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */
2880 #define ADC_CR_ADCALDIF_Pos               (30U)
2881 #define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */
2882 #define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */
2883 #define ADC_CR_ADCAL_Pos                  (31U)
2884 #define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */
2885 #define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */
2886 
2887 /********************  Bit definition for ADC_CFGR register  ********************/
2888 #define ADC_CFGR_DMNGT_Pos                (0U)
2889 #define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */
2890 #define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */
2891 #define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */
2892 #define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */
2893 
2894 #define ADC_CFGR_RES_Pos                  (2U)
2895 #define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */
2896 #define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */
2897 #define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */
2898 #define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */
2899 #define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */
2900 
2901 #define ADC_CFGR_EXTSEL_Pos               (5U)
2902 #define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */
2903 #define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */
2904 #define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */
2905 #define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */
2906 #define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */
2907 #define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */
2908 #define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */
2909 
2910 #define ADC_CFGR_EXTEN_Pos                (10U)
2911 #define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */
2912 #define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */
2913 #define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */
2914 #define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */
2915 
2916 #define ADC_CFGR_OVRMOD_Pos               (12U)
2917 #define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */
2918 #define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */
2919 #define ADC_CFGR_CONT_Pos                 (13U)
2920 #define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */
2921 #define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */
2922 #define ADC_CFGR_AUTDLY_Pos               (14U)
2923 #define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */
2924 #define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */
2925 
2926 #define ADC_CFGR_DISCEN_Pos               (16U)
2927 #define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */
2928 #define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */
2929 
2930 #define ADC_CFGR_DISCNUM_Pos              (17U)
2931 #define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */
2932 #define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */
2933 #define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */
2934 #define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */
2935 #define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */
2936 
2937 #define ADC_CFGR_JDISCEN_Pos              (20U)
2938 #define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */
2939 #define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */
2940 #define ADC_CFGR_JQM_Pos                  (21U)
2941 #define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */
2942 #define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */
2943 #define ADC_CFGR_AWD1SGL_Pos              (22U)
2944 #define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */
2945 #define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */
2946 #define ADC_CFGR_AWD1EN_Pos               (23U)
2947 #define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */
2948 #define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */
2949 #define ADC_CFGR_JAWD1EN_Pos              (24U)
2950 #define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */
2951 #define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */
2952 #define ADC_CFGR_JAUTO_Pos                (25U)
2953 #define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */
2954 #define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */
2955 
2956 #define ADC_CFGR_AWD1CH_Pos               (26U)
2957 #define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */
2958 #define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */
2959 #define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */
2960 #define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */
2961 #define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */
2962 #define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */
2963 #define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */
2964 
2965 #define ADC_CFGR_JQDIS_Pos                (31U)
2966 #define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */
2967 #define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */
2968 
2969 /********************  Bit definition for ADC_CFGR2 register  ********************/
2970 #define ADC_CFGR2_ROVSE_Pos               (0U)
2971 #define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */
2972 #define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */
2973 #define ADC_CFGR2_JOVSE_Pos               (1U)
2974 #define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */
2975 #define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */
2976 
2977 #define ADC_CFGR2_OVSS_Pos                (5U)
2978 #define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */
2979 #define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */
2980 #define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
2981 #define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
2982 #define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
2983 #define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
2984 
2985 #define ADC_CFGR2_TROVS_Pos               (9U)
2986 #define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */
2987 #define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */
2988 #define ADC_CFGR2_ROVSM_Pos               (10U)
2989 #define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */
2990 #define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */
2991 
2992 #define ADC_CFGR2_RSHIFT1_Pos             (11U)
2993 #define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */
2994 #define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */
2995 #define ADC_CFGR2_RSHIFT2_Pos             (12U)
2996 #define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */
2997 #define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */
2998 #define ADC_CFGR2_RSHIFT3_Pos             (13U)
2999 #define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */
3000 #define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */
3001 #define ADC_CFGR2_RSHIFT4_Pos             (14U)
3002 #define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */
3003 #define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */
3004 
3005 #define ADC_CFGR2_OVSR_Pos                (16U)
3006 #define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */
3007 #define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */
3008 #define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */
3009 #define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */
3010 #define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */
3011 #define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */
3012 #define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */
3013 #define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */
3014 #define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */
3015 #define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */
3016 #define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
3017 #define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
3018 
3019 #define ADC_CFGR2_LSHIFT_Pos              (28U)
3020 #define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */
3021 #define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */
3022 #define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
3023 #define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
3024 #define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
3025 #define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
3026 
3027 /********************  Bit definition for ADC_SMPR1 register  ********************/
3028 #define ADC_SMPR1_SMP0_Pos                (0U)
3029 #define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */
3030 #define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */
3031 #define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
3032 #define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
3033 #define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
3034 
3035 #define ADC_SMPR1_SMP1_Pos                (3U)
3036 #define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */
3037 #define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */
3038 #define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
3039 #define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
3040 #define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
3041 
3042 #define ADC_SMPR1_SMP2_Pos                (6U)
3043 #define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */
3044 #define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */
3045 #define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
3046 #define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
3047 #define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
3048 
3049 #define ADC_SMPR1_SMP3_Pos                (9U)
3050 #define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */
3051 #define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */
3052 #define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
3053 #define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
3054 #define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
3055 
3056 #define ADC_SMPR1_SMP4_Pos                (12U)
3057 #define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */
3058 #define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */
3059 #define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
3060 #define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
3061 #define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
3062 
3063 #define ADC_SMPR1_SMP5_Pos                (15U)
3064 #define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */
3065 #define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */
3066 #define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
3067 #define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
3068 #define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
3069 
3070 #define ADC_SMPR1_SMP6_Pos                (18U)
3071 #define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */
3072 #define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */
3073 #define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
3074 #define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
3075 #define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
3076 
3077 #define ADC_SMPR1_SMP7_Pos                (21U)
3078 #define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */
3079 #define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */
3080 #define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
3081 #define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
3082 #define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
3083 
3084 #define ADC_SMPR1_SMP8_Pos                (24U)
3085 #define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */
3086 #define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */
3087 #define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
3088 #define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
3089 #define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
3090 
3091 #define ADC_SMPR1_SMP9_Pos                (27U)
3092 #define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */
3093 #define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */
3094 #define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
3095 #define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
3096 #define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
3097 
3098 /********************  Bit definition for ADC_SMPR2 register  ********************/
3099 #define ADC_SMPR2_SMP10_Pos               (0U)
3100 #define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */
3101 #define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */
3102 #define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
3103 #define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
3104 #define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
3105 
3106 #define ADC_SMPR2_SMP11_Pos               (3U)
3107 #define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */
3108 #define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */
3109 #define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
3110 #define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
3111 #define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
3112 
3113 #define ADC_SMPR2_SMP12_Pos               (6U)
3114 #define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */
3115 #define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */
3116 #define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
3117 #define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
3118 #define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
3119 
3120 #define ADC_SMPR2_SMP13_Pos               (9U)
3121 #define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */
3122 #define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */
3123 #define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
3124 #define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
3125 #define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
3126 
3127 #define ADC_SMPR2_SMP14_Pos               (12U)
3128 #define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */
3129 #define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */
3130 #define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
3131 #define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
3132 #define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
3133 
3134 #define ADC_SMPR2_SMP15_Pos               (15U)
3135 #define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */
3136 #define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */
3137 #define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
3138 #define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
3139 #define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
3140 
3141 #define ADC_SMPR2_SMP16_Pos               (18U)
3142 #define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */
3143 #define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */
3144 #define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
3145 #define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
3146 #define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
3147 
3148 #define ADC_SMPR2_SMP17_Pos               (21U)
3149 #define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */
3150 #define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */
3151 #define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
3152 #define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
3153 #define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
3154 
3155 #define ADC_SMPR2_SMP18_Pos               (24U)
3156 #define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */
3157 #define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */
3158 #define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
3159 #define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
3160 #define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
3161 
3162 #define ADC_SMPR2_SMP19_Pos               (27U)
3163 #define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */
3164 #define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */
3165 #define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
3166 #define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
3167 #define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
3168 
3169 /********************  Bit definition for ADC_PCSEL register  ********************/
3170 #define ADC_PCSEL_PCSEL_Pos               (0U)
3171 #define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */
3172 #define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */
3173 #define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
3174 #define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
3175 #define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
3176 #define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
3177 #define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
3178 #define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
3179 #define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
3180 #define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
3181 #define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
3182 #define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
3183 #define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
3184 #define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
3185 #define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
3186 #define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
3187 #define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
3188 #define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
3189 #define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
3190 #define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
3191 #define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
3192 #define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
3193 
3194 /*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/
3195 #define ADC_LTR_LT_Pos                    (0U)
3196 #define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */
3197 #define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
3198 
3199 /*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/
3200 #define ADC_HTR_HT_Pos                    (0U)
3201 #define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */
3202 #define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
3203 
3204 
3205 /********************  Bit definition for ADC_SQR1 register  ********************/
3206 #define ADC_SQR1_L_Pos                    (0U)
3207 #define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */
3208 #define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence length */
3209 #define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
3210 #define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
3211 #define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
3212 #define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
3213 
3214 #define ADC_SQR1_SQ1_Pos                  (6U)
3215 #define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */
3216 #define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */
3217 #define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
3218 #define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
3219 #define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
3220 #define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
3221 #define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
3222 
3223 #define ADC_SQR1_SQ2_Pos                  (12U)
3224 #define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */
3225 #define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */
3226 #define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
3227 #define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
3228 #define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
3229 #define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
3230 #define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
3231 
3232 #define ADC_SQR1_SQ3_Pos                  (18U)
3233 #define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */
3234 #define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */
3235 #define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
3236 #define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
3237 #define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
3238 #define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
3239 #define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
3240 
3241 #define ADC_SQR1_SQ4_Pos                  (24U)
3242 #define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */
3243 #define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */
3244 #define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
3245 #define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
3246 #define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
3247 #define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
3248 #define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
3249 
3250 /********************  Bit definition for ADC_SQR2 register  ********************/
3251 #define ADC_SQR2_SQ5_Pos                  (0U)
3252 #define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */
3253 #define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */
3254 #define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
3255 #define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
3256 #define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
3257 #define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
3258 #define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
3259 
3260 #define ADC_SQR2_SQ6_Pos                  (6U)
3261 #define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */
3262 #define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */
3263 #define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
3264 #define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
3265 #define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
3266 #define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
3267 #define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
3268 
3269 #define ADC_SQR2_SQ7_Pos                  (12U)
3270 #define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */
3271 #define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */
3272 #define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
3273 #define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
3274 #define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
3275 #define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
3276 #define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
3277 
3278 #define ADC_SQR2_SQ8_Pos                  (18U)
3279 #define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */
3280 #define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */
3281 #define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
3282 #define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
3283 #define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
3284 #define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
3285 #define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
3286 
3287 #define ADC_SQR2_SQ9_Pos                  (24U)
3288 #define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */
3289 #define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */
3290 #define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
3291 #define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
3292 #define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
3293 #define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
3294 #define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
3295 
3296 /********************  Bit definition for ADC_SQR3 register  ********************/
3297 #define ADC_SQR3_SQ10_Pos                 (0U)
3298 #define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */
3299 #define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */
3300 #define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
3301 #define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
3302 #define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
3303 #define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
3304 #define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
3305 
3306 #define ADC_SQR3_SQ11_Pos                 (6U)
3307 #define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */
3308 #define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */
3309 #define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
3310 #define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
3311 #define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
3312 #define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
3313 #define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
3314 
3315 #define ADC_SQR3_SQ12_Pos                 (12U)
3316 #define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */
3317 #define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */
3318 #define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
3319 #define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
3320 #define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
3321 #define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
3322 #define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
3323 
3324 #define ADC_SQR3_SQ13_Pos                 (18U)
3325 #define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */
3326 #define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */
3327 #define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
3328 #define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
3329 #define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
3330 #define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
3331 #define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
3332 
3333 #define ADC_SQR3_SQ14_Pos                 (24U)
3334 #define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */
3335 #define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */
3336 #define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
3337 #define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
3338 #define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
3339 #define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
3340 #define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
3341 
3342 /********************  Bit definition for ADC_SQR4 register  ********************/
3343 #define ADC_SQR4_SQ15_Pos                 (0U)
3344 #define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */
3345 #define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */
3346 #define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
3347 #define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
3348 #define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
3349 #define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
3350 #define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
3351 
3352 #define ADC_SQR4_SQ16_Pos                 (6U)
3353 #define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */
3354 #define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */
3355 #define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
3356 #define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
3357 #define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
3358 #define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
3359 #define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
3360 /********************  Bit definition for ADC_DR register  ********************/
3361 #define ADC_DR_RDATA_Pos                  (0U)
3362 #define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */
3363 #define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */
3364 
3365 /********************  Bit definition for ADC_JSQR register  ********************/
3366 #define ADC_JSQR_JL_Pos                   (0U)
3367 #define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */
3368 #define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */
3369 #define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */
3370 #define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */
3371 
3372 #define ADC_JSQR_JEXTSEL_Pos              (2U)
3373 #define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */
3374 #define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */
3375 #define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */
3376 #define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */
3377 #define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */
3378 #define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */
3379 #define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */
3380 
3381 #define ADC_JSQR_JEXTEN_Pos               (7U)
3382 #define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */
3383 #define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */
3384 #define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */
3385 #define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */
3386 
3387 #define ADC_JSQR_JSQ1_Pos                 (9U)
3388 #define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */
3389 #define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */
3390 #define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */
3391 #define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */
3392 #define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */
3393 #define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */
3394 #define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */
3395 
3396 #define ADC_JSQR_JSQ2_Pos                 (15U)
3397 #define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */
3398 #define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */
3399 #define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */
3400 #define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */
3401 #define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */
3402 #define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */
3403 #define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */
3404 
3405 #define ADC_JSQR_JSQ3_Pos                 (21U)
3406 #define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */
3407 #define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */
3408 #define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */
3409 #define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */
3410 #define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */
3411 #define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */
3412 #define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */
3413 
3414 #define ADC_JSQR_JSQ4_Pos                 (27U)
3415 #define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */
3416 #define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */
3417 #define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */
3418 #define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */
3419 #define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */
3420 #define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */
3421 #define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */
3422 
3423 /********************  Bit definition for ADC_OFR1 register  ********************/
3424 #define ADC_OFR1_OFFSET1_Pos              (0U)
3425 #define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3426 #define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3427 #define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3428 #define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3429 #define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3430 #define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3431 #define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3432 #define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3433 #define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3434 #define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3435 #define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3436 #define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3437 #define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3438 #define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3439 #define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3440 #define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3441 #define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3442 #define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3443 #define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3444 #define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3445 #define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3446 #define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3447 #define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3448 #define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3449 #define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3450 #define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3451 #define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3452 #define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3453 
3454 #define ADC_OFR1_OFFSET1_CH_Pos           (26U)
3455 #define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
3456 #define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */
3457 #define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
3458 #define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
3459 #define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
3460 #define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
3461 #define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
3462 
3463 #define ADC_OFR1_SSATE_Pos                (31U)
3464 #define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */
3465 #define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */
3466 
3467 
3468 /********************  Bit definition for ADC_OFR2 register  ********************/
3469 #define ADC_OFR2_OFFSET2_Pos              (0U)
3470 #define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3471 #define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3472 #define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3473 #define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3474 #define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3475 #define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3476 #define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3477 #define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3478 #define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3479 #define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3480 #define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3481 #define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3482 #define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3483 #define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3484 #define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3485 #define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3486 #define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3487 #define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3488 #define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3489 #define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3490 #define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3491 #define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3492 #define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3493 #define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3494 #define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3495 #define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3496 #define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3497 #define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3498 
3499 #define ADC_OFR2_OFFSET2_CH_Pos           (26U)
3500 #define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
3501 #define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */
3502 #define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
3503 #define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
3504 #define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
3505 #define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
3506 #define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
3507 
3508 #define ADC_OFR2_SSATE_Pos                (31U)
3509 #define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */
3510 #define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */
3511 
3512 
3513 /********************  Bit definition for ADC_OFR3 register  ********************/
3514 #define ADC_OFR3_OFFSET3_Pos              (0U)
3515 #define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3516 #define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3517 #define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3518 #define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3519 #define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3520 #define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3521 #define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3522 #define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3523 #define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3524 #define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3525 #define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3526 #define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3527 #define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3528 #define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3529 #define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3530 #define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3531 #define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3532 #define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3533 #define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3534 #define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3535 #define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3536 #define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3537 #define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3538 #define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3539 #define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3540 #define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3541 #define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3542 #define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3543 
3544 #define ADC_OFR3_OFFSET3_CH_Pos           (26U)
3545 #define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
3546 #define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */
3547 #define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
3548 #define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
3549 #define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
3550 #define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
3551 #define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
3552 
3553 #define ADC_OFR3_SSATE_Pos                (31U)
3554 #define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */
3555 #define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */
3556 
3557 
3558 /********************  Bit definition for ADC_OFR4 register  ********************/
3559 #define ADC_OFR4_OFFSET4_Pos              (0U)
3560 #define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3561 #define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3562 #define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3563 #define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3564 #define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3565 #define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3566 #define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3567 #define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3568 #define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3569 #define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3570 #define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3571 #define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3572 #define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3573 #define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3574 #define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3575 #define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3576 #define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3577 #define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3578 #define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3579 #define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3580 #define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3581 #define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3582 #define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3583 #define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3584 #define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3585 #define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3586 #define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3587 #define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3588 
3589 #define ADC_OFR4_OFFSET4_CH_Pos           (26U)
3590 #define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
3591 #define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */
3592 #define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
3593 #define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
3594 #define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
3595 #define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
3596 #define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
3597 
3598 #define ADC_OFR4_SSATE_Pos                (31U)
3599 #define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */
3600 #define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */
3601 
3602 
3603 /********************  Bit definition for ADC_JDR1 register  ********************/
3604 #define ADC_JDR1_JDATA_Pos                (0U)
3605 #define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */
3606 #define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */
3607 #define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */
3608 #define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */
3609 #define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */
3610 #define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */
3611 #define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */
3612 #define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */
3613 #define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */
3614 #define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */
3615 #define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */
3616 #define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */
3617 #define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */
3618 #define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */
3619 #define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */
3620 #define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */
3621 #define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */
3622 #define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */
3623 #define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */
3624 #define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */
3625 #define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */
3626 #define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */
3627 #define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */
3628 #define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */
3629 #define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */
3630 #define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */
3631 #define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */
3632 #define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */
3633 #define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */
3634 #define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */
3635 #define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
3636 #define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
3637 #define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
3638 #define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
3639 
3640 /********************  Bit definition for ADC_JDR2 register  ********************/
3641 #define ADC_JDR2_JDATA_Pos                (0U)
3642 #define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */
3643 #define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */
3644 #define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */
3645 #define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */
3646 #define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */
3647 #define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */
3648 #define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */
3649 #define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */
3650 #define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */
3651 #define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */
3652 #define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */
3653 #define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */
3654 #define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */
3655 #define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */
3656 #define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */
3657 #define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */
3658 #define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */
3659 #define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */
3660 #define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */
3661 #define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */
3662 #define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */
3663 #define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */
3664 #define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */
3665 #define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */
3666 #define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */
3667 #define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */
3668 #define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */
3669 #define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */
3670 #define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */
3671 #define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */
3672 #define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
3673 #define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
3674 #define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
3675 #define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
3676 
3677 /********************  Bit definition for ADC_JDR3 register  ********************/
3678 #define ADC_JDR3_JDATA_Pos                (0U)
3679 #define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */
3680 #define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */
3681 #define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */
3682 #define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */
3683 #define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */
3684 #define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */
3685 #define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */
3686 #define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */
3687 #define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */
3688 #define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */
3689 #define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */
3690 #define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */
3691 #define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */
3692 #define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */
3693 #define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */
3694 #define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */
3695 #define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */
3696 #define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */
3697 #define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */
3698 #define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */
3699 #define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */
3700 #define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */
3701 #define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */
3702 #define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */
3703 #define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */
3704 #define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */
3705 #define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */
3706 #define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */
3707 #define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */
3708 #define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */
3709 #define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
3710 #define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
3711 #define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
3712 #define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
3713 
3714 /********************  Bit definition for ADC_JDR4 register  ********************/
3715 #define ADC_JDR4_JDATA_Pos                (0U)
3716 #define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */
3717 #define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */
3718 #define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */
3719 #define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */
3720 #define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */
3721 #define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */
3722 #define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */
3723 #define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */
3724 #define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */
3725 #define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */
3726 #define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */
3727 #define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */
3728 #define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */
3729 #define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */
3730 #define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */
3731 #define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */
3732 #define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */
3733 #define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */
3734 #define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */
3735 #define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */
3736 #define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */
3737 #define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */
3738 #define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */
3739 #define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */
3740 #define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */
3741 #define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */
3742 #define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */
3743 #define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */
3744 #define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */
3745 #define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */
3746 #define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
3747 #define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
3748 #define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
3749 #define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
3750 
3751 /********************  Bit definition for ADC_AWD2CR register  ********************/
3752 #define ADC_AWD2CR_AWD2CH_Pos             (0U)
3753 #define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */
3754 #define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
3755 #define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
3756 #define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
3757 #define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
3758 #define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
3759 #define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
3760 #define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
3761 #define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
3762 #define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
3763 #define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
3764 #define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
3765 #define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
3766 #define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
3767 #define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
3768 #define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
3769 #define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
3770 #define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
3771 #define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
3772 #define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
3773 #define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
3774 #define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
3775 
3776 /********************  Bit definition for ADC_AWD3CR register  ********************/
3777 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
3778 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
3779 #define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
3780 #define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
3781 #define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
3782 #define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
3783 #define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
3784 #define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
3785 #define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
3786 #define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
3787 #define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
3788 #define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
3789 #define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
3790 #define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
3791 #define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
3792 #define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
3793 #define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
3794 #define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
3795 #define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
3796 #define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
3797 #define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
3798 #define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
3799 #define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
3800 
3801 /********************  Bit definition for ADC_DIFSEL register  ********************/
3802 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
3803 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
3804 #define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */
3805 #define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
3806 #define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
3807 #define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
3808 #define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
3809 #define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
3810 #define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
3811 #define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
3812 #define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
3813 #define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
3814 #define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
3815 #define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
3816 #define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
3817 #define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
3818 #define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
3819 #define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
3820 #define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
3821 #define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
3822 #define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
3823 #define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
3824 #define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
3825 
3826 /********************  Bit definition for ADC_CALFACT register  ********************/
3827 #define ADC_CALFACT_CALFACT_S_Pos         (0U)
3828 #define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3829 #define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */
3830 #define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3831 #define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3832 #define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3833 #define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3834 #define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3835 #define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3836 #define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3837 #define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3838 #define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3839 #define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3840 #define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3841 #define ADC_CALFACT_CALFACT_D_Pos         (16U)
3842 #define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3843 #define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */
3844 #define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3845 #define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3846 #define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3847 #define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3848 #define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3849 #define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3850 #define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3851 #define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3852 #define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3853 #define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3854 #define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3855 
3856 /********************  Bit definition for ADC_CALFACT2 register  ********************/
3857 #define ADC_CALFACT2_LINCALFACT_Pos       (0U)
3858 #define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3859 #define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */
3860 #define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3861 #define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3862 #define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3863 #define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3864 #define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3865 #define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3866 #define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3867 #define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3868 #define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3869 #define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3870 #define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3871 #define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3872 #define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3873 #define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3874 #define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3875 #define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3876 #define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3877 #define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3878 #define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3879 #define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3880 #define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3881 #define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3882 #define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3883 #define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3884 #define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3885 #define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3886 #define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3887 #define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3888 #define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3889 #define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3890 
3891 /*************************  ADC Common registers  *****************************/
3892 /********************  Bit definition for ADC_CSR register  ********************/
3893 #define ADC_CSR_ADRDY_MST_Pos             (0U)
3894 #define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
3895 #define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */
3896 #define ADC_CSR_EOSMP_MST_Pos             (1U)
3897 #define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */
3898 #define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */
3899 #define ADC_CSR_EOC_MST_Pos               (2U)
3900 #define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */
3901 #define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */
3902 #define ADC_CSR_EOS_MST_Pos               (3U)
3903 #define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */
3904 #define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */
3905 #define ADC_CSR_OVR_MST_Pos               (4U)
3906 #define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */
3907 #define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */
3908 #define ADC_CSR_JEOC_MST_Pos              (5U)
3909 #define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */
3910 #define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */
3911 #define ADC_CSR_JEOS_MST_Pos              (6U)
3912 #define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */
3913 #define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */
3914 #define ADC_CSR_AWD1_MST_Pos              (7U)
3915 #define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
3916 #define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */
3917 #define ADC_CSR_AWD2_MST_Pos              (8U)
3918 #define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
3919 #define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */
3920 #define ADC_CSR_AWD3_MST_Pos              (9U)
3921 #define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
3922 #define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */
3923 #define ADC_CSR_JQOVF_MST_Pos             (10U)
3924 #define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
3925 #define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */
3926 #define ADC_CSR_ADRDY_SLV_Pos             (16U)
3927 #define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
3928 #define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */
3929 #define ADC_CSR_EOSMP_SLV_Pos             (17U)
3930 #define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */
3931 #define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */
3932 #define ADC_CSR_EOC_SLV_Pos               (18U)
3933 #define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */
3934 #define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */
3935 #define ADC_CSR_EOS_SLV_Pos               (19U)
3936 #define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */
3937 #define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */
3938 #define ADC_CSR_OVR_SLV_Pos               (20U)
3939 #define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */
3940 #define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */
3941 #define ADC_CSR_JEOC_SLV_Pos              (21U)
3942 #define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */
3943 #define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */
3944 #define ADC_CSR_JEOS_SLV_Pos              (22U)
3945 #define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */
3946 #define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */
3947 #define ADC_CSR_AWD1_SLV_Pos              (23U)
3948 #define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
3949 #define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */
3950 #define ADC_CSR_AWD2_SLV_Pos              (24U)
3951 #define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
3952 #define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */
3953 #define ADC_CSR_AWD3_SLV_Pos              (25U)
3954 #define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
3955 #define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */
3956 #define ADC_CSR_JQOVF_SLV_Pos             (26U)
3957 #define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
3958 #define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */
3959 
3960 /********************  Bit definition for ADC_CCR register  ********************/
3961 #define ADC_CCR_DUAL_Pos                  (0U)
3962 #define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
3963 #define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */
3964 #define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
3965 #define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
3966 #define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
3967 #define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
3968 #define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
3969 
3970 #define ADC_CCR_DELAY_Pos                 (8U)
3971 #define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
3972 #define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */
3973 #define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
3974 #define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
3975 #define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
3976 #define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
3977 
3978 
3979 #define ADC_CCR_DAMDF_Pos                 (14U)
3980 #define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
3981 #define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */
3982 #define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
3983 #define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
3984 
3985 #define ADC_CCR_CKMODE_Pos                (16U)
3986 #define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */
3987 #define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */
3988 #define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */
3989 #define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */
3990 
3991 #define ADC_CCR_PRESC_Pos                 (18U)
3992 #define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
3993 #define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */
3994 #define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
3995 #define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
3996 #define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
3997 #define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
3998 
3999 #define ADC_CCR_VREFEN_Pos                (22U)
4000 #define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
4001 #define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */
4002 #define ADC_CCR_TSEN_Pos                  (23U)
4003 #define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */
4004 #define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */
4005 #define ADC_CCR_VBATEN_Pos                (24U)
4006 #define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
4007 #define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */
4008 
4009 /********************  Bit definition for ADC_CDR register  *******************/
4010 #define ADC_CDR_RDATA_MST_Pos             (0U)
4011 #define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */
4012 #define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */
4013 
4014 #define ADC_CDR_RDATA_SLV_Pos             (16U)
4015 #define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */
4016 #define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */
4017 
4018 /********************  Bit definition for ADC_CDR2 register  ******************/
4019 #define ADC_CDR2_RDATA_ALT_Pos            (0U)
4020 #define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
4021 #define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */
4022 
4023 
4024 /******************************************************************************/
4025 /*                                                                            */
4026 /*                                   VREFBUF                                  */
4027 /*                                                                            */
4028 /******************************************************************************/
4029 /*******************  Bit definition for VREFBUF_CSR register  ****************/
4030 #define VREFBUF_CSR_ENVR_Pos        (0U)
4031 #define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */
4032 #define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
4033 #define VREFBUF_CSR_HIZ_Pos         (1U)
4034 #define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */
4035 #define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
4036 #define VREFBUF_CSR_VRR_Pos         (3U)
4037 #define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */
4038 #define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
4039 #define VREFBUF_CSR_VRS_Pos         (4U)
4040 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
4041 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
4042 
4043 #define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
4044 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
4045 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
4046 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
4047 #define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
4048 #define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */
4049 #define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
4050 #define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
4051 #define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */
4052 #define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */
4053 
4054 /*******************  Bit definition for VREFBUF_CCR register  ****************/
4055 #define VREFBUF_CCR_TRIM_Pos        (0U)
4056 #define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */
4057 #define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */
4058 
4059 /******************************************************************************/
4060 /*                                                                            */
4061 /*                 Flexible Datarate Controller Area Network                  */
4062 /*                                                                            */
4063 /******************************************************************************/
4064 /*!<FDCAN control and status registers */
4065 /*****************  Bit definition for FDCAN_CREL register  *******************/
4066 #define FDCAN_CREL_DAY_Pos        (0U)
4067 #define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
4068 #define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
4069 #define FDCAN_CREL_MON_Pos        (8U)
4070 #define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
4071 #define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
4072 #define FDCAN_CREL_YEAR_Pos       (16U)
4073 #define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
4074 #define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
4075 #define FDCAN_CREL_SUBSTEP_Pos    (20U)
4076 #define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
4077 #define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
4078 #define FDCAN_CREL_STEP_Pos       (24U)
4079 #define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
4080 #define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
4081 #define FDCAN_CREL_REL_Pos        (28U)
4082 #define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
4083 #define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
4084 
4085 /*****************  Bit definition for FDCAN_ENDN register  *******************/
4086 #define FDCAN_ENDN_ETV_Pos        (0U)
4087 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
4088 #define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                   */
4089 
4090 /*****************  Bit definition for FDCAN_DBTP register  *******************/
4091 #define FDCAN_DBTP_DSJW_Pos       (0U)
4092 #define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
4093 #define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
4094 #define FDCAN_DBTP_DTSEG2_Pos     (4U)
4095 #define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
4096 #define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
4097 #define FDCAN_DBTP_DTSEG1_Pos     (8U)
4098 #define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
4099 #define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
4100 #define FDCAN_DBTP_DBRP_Pos       (16U)
4101 #define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
4102 #define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
4103 #define FDCAN_DBTP_TDC_Pos        (23U)
4104 #define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
4105 #define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
4106 
4107 /*****************  Bit definition for FDCAN_TEST register  *******************/
4108 #define FDCAN_TEST_LBCK_Pos       (4U)
4109 #define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
4110 #define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
4111 #define FDCAN_TEST_TX_Pos         (5U)
4112 #define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
4113 #define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
4114 #define FDCAN_TEST_RX_Pos         (7U)
4115 #define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
4116 #define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
4117 
4118 /*****************  Bit definition for FDCAN_RWD register  ********************/
4119 #define FDCAN_RWD_WDC_Pos         (0U)
4120 #define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
4121 #define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
4122 #define FDCAN_RWD_WDV_Pos         (8U)
4123 #define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
4124 #define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
4125 
4126 /*****************  Bit definition for FDCAN_CCCR register  ********************/
4127 #define FDCAN_CCCR_INIT_Pos       (0U)
4128 #define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
4129 #define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
4130 #define FDCAN_CCCR_CCE_Pos        (1U)
4131 #define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
4132 #define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
4133 #define FDCAN_CCCR_ASM_Pos        (2U)
4134 #define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
4135 #define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
4136 #define FDCAN_CCCR_CSA_Pos        (3U)
4137 #define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
4138 #define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
4139 #define FDCAN_CCCR_CSR_Pos        (4U)
4140 #define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
4141 #define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
4142 #define FDCAN_CCCR_MON_Pos        (5U)
4143 #define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
4144 #define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
4145 #define FDCAN_CCCR_DAR_Pos        (6U)
4146 #define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
4147 #define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
4148 #define FDCAN_CCCR_TEST_Pos       (7U)
4149 #define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
4150 #define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
4151 #define FDCAN_CCCR_FDOE_Pos       (8U)
4152 #define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
4153 #define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
4154 #define FDCAN_CCCR_BRSE_Pos       (9U)
4155 #define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
4156 #define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
4157 #define FDCAN_CCCR_PXHD_Pos       (12U)
4158 #define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
4159 #define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
4160 #define FDCAN_CCCR_EFBI_Pos       (13U)
4161 #define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
4162 #define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
4163 #define FDCAN_CCCR_TXP_Pos        (14U)
4164 #define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
4165 #define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
4166 #define FDCAN_CCCR_NISO_Pos       (15U)
4167 #define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
4168 #define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
4169 
4170 /*****************  Bit definition for FDCAN_NBTP register  ********************/
4171 #define FDCAN_NBTP_NTSEG2_Pos     (0U)
4172 #define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
4173 #define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
4174 #define FDCAN_NBTP_NTSEG1_Pos     (8U)
4175 #define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
4176 #define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
4177 #define FDCAN_NBTP_NBRP_Pos       (16U)
4178 #define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
4179 #define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
4180 #define FDCAN_NBTP_NSJW_Pos       (25U)
4181 #define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
4182 #define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
4183 
4184 /*****************  Bit definition for FDCAN_TSCC register  ********************/
4185 #define FDCAN_TSCC_TSS_Pos        (0U)
4186 #define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
4187 #define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
4188 #define FDCAN_TSCC_TCP_Pos        (16U)
4189 #define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
4190 #define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
4191 
4192 /*****************  Bit definition for FDCAN_TSCV register  ********************/
4193 #define FDCAN_TSCV_TSC_Pos        (0U)
4194 #define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
4195 #define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
4196 
4197 /*****************  Bit definition for FDCAN_TOCC register  ********************/
4198 #define FDCAN_TOCC_ETOC_Pos       (0U)
4199 #define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
4200 #define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
4201 #define FDCAN_TOCC_TOS_Pos        (1U)
4202 #define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
4203 #define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
4204 #define FDCAN_TOCC_TOP_Pos        (16U)
4205 #define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
4206 #define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
4207 
4208 /*****************  Bit definition for FDCAN_TOCV register  ********************/
4209 #define FDCAN_TOCV_TOC_Pos        (0U)
4210 #define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
4211 #define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
4212 
4213 /*****************  Bit definition for FDCAN_ECR register  *********************/
4214 #define FDCAN_ECR_TEC_Pos         (0U)
4215 #define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x000000FF */
4216 #define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
4217 #define FDCAN_ECR_REC_Pos         (8U)
4218 #define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
4219 #define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
4220 #define FDCAN_ECR_RP_Pos          (15U)
4221 #define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
4222 #define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
4223 #define FDCAN_ECR_CEL_Pos         (16U)
4224 #define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
4225 #define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
4226 
4227 /*****************  Bit definition for FDCAN_PSR register  *********************/
4228 #define FDCAN_PSR_LEC_Pos         (0U)
4229 #define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
4230 #define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
4231 #define FDCAN_PSR_ACT_Pos         (3U)
4232 #define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
4233 #define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
4234 #define FDCAN_PSR_EP_Pos          (5U)
4235 #define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
4236 #define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
4237 #define FDCAN_PSR_EW_Pos          (6U)
4238 #define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
4239 #define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
4240 #define FDCAN_PSR_BO_Pos          (7U)
4241 #define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
4242 #define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
4243 #define FDCAN_PSR_DLEC_Pos        (8U)
4244 #define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
4245 #define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
4246 #define FDCAN_PSR_RESI_Pos        (11U)
4247 #define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
4248 #define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
4249 #define FDCAN_PSR_RBRS_Pos        (12U)
4250 #define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
4251 #define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
4252 #define FDCAN_PSR_REDL_Pos        (13U)
4253 #define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
4254 #define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
4255 #define FDCAN_PSR_PXE_Pos         (14U)
4256 #define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
4257 #define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
4258 #define FDCAN_PSR_TDCV_Pos        (16U)
4259 #define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
4260 #define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
4261 
4262 /*****************  Bit definition for FDCAN_TDCR register  ********************/
4263 #define FDCAN_TDCR_TDCF_Pos       (0U)
4264 #define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
4265 #define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
4266 #define FDCAN_TDCR_TDCO_Pos       (8U)
4267 #define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
4268 #define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
4269 
4270 /*****************  Bit definition for FDCAN_IR register  **********************/
4271 #define FDCAN_IR_RF0N_Pos         (0U)
4272 #define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
4273 #define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
4274 #define FDCAN_IR_RF0W_Pos         (1U)
4275 #define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */
4276 #define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */
4277 #define FDCAN_IR_RF0F_Pos         (2U)
4278 #define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */
4279 #define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
4280 #define FDCAN_IR_RF0L_Pos         (3U)
4281 #define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */
4282 #define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
4283 #define FDCAN_IR_RF1N_Pos         (4U)
4284 #define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */
4285 #define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
4286 #define FDCAN_IR_RF1W_Pos         (5U)
4287 #define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */
4288 #define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */
4289 #define FDCAN_IR_RF1F_Pos         (6U)
4290 #define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */
4291 #define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
4292 #define FDCAN_IR_RF1L_Pos         (7U)
4293 #define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */
4294 #define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
4295 #define FDCAN_IR_HPM_Pos          (8U)
4296 #define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */
4297 #define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
4298 #define FDCAN_IR_TC_Pos           (9U)
4299 #define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */
4300 #define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
4301 #define FDCAN_IR_TCF_Pos          (10U)
4302 #define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */
4303 #define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
4304 #define FDCAN_IR_TFE_Pos          (11U)
4305 #define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */
4306 #define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
4307 #define FDCAN_IR_TEFN_Pos         (12U)
4308 #define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */
4309 #define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
4310 #define FDCAN_IR_TEFW_Pos         (13U)
4311 #define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */
4312 #define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */
4313 #define FDCAN_IR_TEFF_Pos         (14U)
4314 #define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */
4315 #define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
4316 #define FDCAN_IR_TEFL_Pos         (15U)
4317 #define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */
4318 #define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
4319 #define FDCAN_IR_TSW_Pos          (16U)
4320 #define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */
4321 #define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
4322 #define FDCAN_IR_MRAF_Pos         (17U)
4323 #define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */
4324 #define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
4325 #define FDCAN_IR_TOO_Pos          (18U)
4326 #define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */
4327 #define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
4328 #define FDCAN_IR_DRX_Pos          (19U)
4329 #define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */
4330 #define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */
4331 #define FDCAN_IR_ELO_Pos          (22U)
4332 #define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */
4333 #define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
4334 #define FDCAN_IR_EP_Pos           (23U)
4335 #define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */
4336 #define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
4337 #define FDCAN_IR_EW_Pos           (24U)
4338 #define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */
4339 #define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
4340 #define FDCAN_IR_BO_Pos           (25U)
4341 #define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */
4342 #define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
4343 #define FDCAN_IR_WDI_Pos          (26U)
4344 #define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */
4345 #define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
4346 #define FDCAN_IR_PEA_Pos          (27U)
4347 #define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */
4348 #define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
4349 #define FDCAN_IR_PED_Pos          (28U)
4350 #define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */
4351 #define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
4352 #define FDCAN_IR_ARA_Pos          (29U)
4353 #define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */
4354 #define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
4355 
4356 /*****************  Bit definition for FDCAN_IE register  **********************/
4357 #define FDCAN_IE_RF0NE_Pos        (0U)
4358 #define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
4359 #define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */
4360 #define FDCAN_IE_RF0WE_Pos        (1U)
4361 #define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */
4362 #define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */
4363 #define FDCAN_IE_RF0FE_Pos        (2U)
4364 #define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */
4365 #define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */
4366 #define FDCAN_IE_RF0LE_Pos        (3U)
4367 #define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */
4368 #define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */
4369 #define FDCAN_IE_RF1NE_Pos        (4U)
4370 #define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */
4371 #define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */
4372 #define FDCAN_IE_RF1WE_Pos        (5U)
4373 #define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */
4374 #define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */
4375 #define FDCAN_IE_RF1FE_Pos        (6U)
4376 #define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */
4377 #define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */
4378 #define FDCAN_IE_RF1LE_Pos        (7U)
4379 #define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */
4380 #define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */
4381 #define FDCAN_IE_HPME_Pos         (8U)
4382 #define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */
4383 #define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */
4384 #define FDCAN_IE_TCE_Pos          (9U)
4385 #define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */
4386 #define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */
4387 #define FDCAN_IE_TCFE_Pos         (10U)
4388 #define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */
4389 #define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */
4390 #define FDCAN_IE_TFEE_Pos         (11U)
4391 #define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */
4392 #define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */
4393 #define FDCAN_IE_TEFNE_Pos        (12U)
4394 #define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */
4395 #define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */
4396 #define FDCAN_IE_TEFWE_Pos        (13U)
4397 #define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */
4398 #define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */
4399 #define FDCAN_IE_TEFFE_Pos        (14U)
4400 #define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */
4401 #define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */
4402 #define FDCAN_IE_TEFLE_Pos        (15U)
4403 #define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */
4404 #define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */
4405 #define FDCAN_IE_TSWE_Pos         (16U)
4406 #define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */
4407 #define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */
4408 #define FDCAN_IE_MRAFE_Pos        (17U)
4409 #define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */
4410 #define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */
4411 #define FDCAN_IE_TOOE_Pos         (18U)
4412 #define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */
4413 #define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */
4414 #define FDCAN_IE_DRXE_Pos         (19U)
4415 #define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */
4416 #define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */
4417 #define FDCAN_IE_BECE_Pos         (20U)
4418 #define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */
4419 #define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */
4420 #define FDCAN_IE_BEUE_Pos         (21U)
4421 #define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */
4422 #define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */
4423 #define FDCAN_IE_ELOE_Pos         (22U)
4424 #define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */
4425 #define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */
4426 #define FDCAN_IE_EPE_Pos          (23U)
4427 #define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */
4428 #define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */
4429 #define FDCAN_IE_EWE_Pos          (24U)
4430 #define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */
4431 #define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */
4432 #define FDCAN_IE_BOE_Pos          (25U)
4433 #define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */
4434 #define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */
4435 #define FDCAN_IE_WDIE_Pos         (26U)
4436 #define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */
4437 #define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */
4438 #define FDCAN_IE_PEAE_Pos         (27U)
4439 #define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */
4440 #define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */
4441 #define FDCAN_IE_PEDE_Pos         (28U)
4442 #define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */
4443 #define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */
4444 #define FDCAN_IE_ARAE_Pos         (29U)
4445 #define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */
4446 #define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */
4447 
4448 /*****************  Bit definition for FDCAN_ILS register  **********************/
4449 #define FDCAN_ILS_RF0NL_Pos       (0U)
4450 #define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */
4451 #define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */
4452 #define FDCAN_ILS_RF0WL_Pos       (1U)
4453 #define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */
4454 #define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */
4455 #define FDCAN_ILS_RF0FL_Pos       (2U)
4456 #define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */
4457 #define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */
4458 #define FDCAN_ILS_RF0LL_Pos       (3U)
4459 #define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */
4460 #define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */
4461 #define FDCAN_ILS_RF1NL_Pos       (4U)
4462 #define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */
4463 #define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */
4464 #define FDCAN_ILS_RF1WL_Pos       (5U)
4465 #define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */
4466 #define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */
4467 #define FDCAN_ILS_RF1FL_Pos       (6U)
4468 #define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */
4469 #define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */
4470 #define FDCAN_ILS_RF1LL_Pos       (7U)
4471 #define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */
4472 #define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */
4473 #define FDCAN_ILS_HPML_Pos        (8U)
4474 #define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */
4475 #define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */
4476 #define FDCAN_ILS_TCL_Pos         (9U)
4477 #define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */
4478 #define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */
4479 #define FDCAN_ILS_TCFL_Pos        (10U)
4480 #define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */
4481 #define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */
4482 #define FDCAN_ILS_TFEL_Pos        (11U)
4483 #define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */
4484 #define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */
4485 #define FDCAN_ILS_TEFNL_Pos       (12U)
4486 #define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */
4487 #define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */
4488 #define FDCAN_ILS_TEFWL_Pos       (13U)
4489 #define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */
4490 #define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */
4491 #define FDCAN_ILS_TEFFL_Pos       (14U)
4492 #define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */
4493 #define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */
4494 #define FDCAN_ILS_TEFLL_Pos       (15U)
4495 #define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */
4496 #define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */
4497 #define FDCAN_ILS_TSWL_Pos        (16U)
4498 #define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */
4499 #define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */
4500 #define FDCAN_ILS_MRAFE_Pos       (17U)
4501 #define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */
4502 #define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */
4503 #define FDCAN_ILS_TOOE_Pos        (18U)
4504 #define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */
4505 #define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */
4506 #define FDCAN_ILS_DRXE_Pos        (19U)
4507 #define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */
4508 #define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */
4509 #define FDCAN_ILS_BECE_Pos        (20U)
4510 #define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */
4511 #define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */
4512 #define FDCAN_ILS_BEUE_Pos        (21U)
4513 #define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */
4514 #define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */
4515 #define FDCAN_ILS_ELOE_Pos        (22U)
4516 #define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */
4517 #define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */
4518 #define FDCAN_ILS_EPE_Pos         (23U)
4519 #define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */
4520 #define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */
4521 #define FDCAN_ILS_EWE_Pos         (24U)
4522 #define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */
4523 #define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */
4524 #define FDCAN_ILS_BOE_Pos         (25U)
4525 #define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */
4526 #define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */
4527 #define FDCAN_ILS_WDIE_Pos        (26U)
4528 #define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */
4529 #define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */
4530 #define FDCAN_ILS_PEAE_Pos        (27U)
4531 #define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */
4532 #define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */
4533 #define FDCAN_ILS_PEDE_Pos        (28U)
4534 #define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */
4535 #define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */
4536 #define FDCAN_ILS_ARAE_Pos        (29U)
4537 #define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */
4538 #define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */
4539 
4540 /*****************  Bit definition for FDCAN_ILE register  **********************/
4541 #define FDCAN_ILE_EINT0_Pos       (0U)
4542 #define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
4543 #define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */
4544 #define FDCAN_ILE_EINT1_Pos       (1U)
4545 #define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
4546 #define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */
4547 
4548 /*****************  Bit definition for FDCAN_GFC register  **********************/
4549 #define FDCAN_GFC_RRFE_Pos        (0U)
4550 #define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */
4551 #define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */
4552 #define FDCAN_GFC_RRFS_Pos        (1U)
4553 #define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */
4554 #define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */
4555 #define FDCAN_GFC_ANFE_Pos        (2U)
4556 #define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */
4557 #define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */
4558 #define FDCAN_GFC_ANFS_Pos        (4U)
4559 #define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */
4560 #define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */
4561 
4562 /*****************  Bit definition for FDCAN_SIDFC register  ********************/
4563 #define FDCAN_SIDFC_FLSSA_Pos     (2U)
4564 #define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */
4565 #define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */
4566 #define FDCAN_SIDFC_LSS_Pos       (16U)
4567 #define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */
4568 #define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */
4569 
4570 /*****************  Bit definition for FDCAN_XIDFC register  ********************/
4571 #define FDCAN_XIDFC_FLESA_Pos     (2U)
4572 #define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */
4573 #define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */
4574 #define FDCAN_XIDFC_LSE_Pos       (16U)
4575 #define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */
4576 #define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */
4577 
4578 /*****************  Bit definition for FDCAN_XIDAM register  ********************/
4579 #define FDCAN_XIDAM_EIDM_Pos      (0U)
4580 #define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
4581 #define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */
4582 
4583 /*****************  Bit definition for FDCAN_HPMS register  *********************/
4584 #define FDCAN_HPMS_BIDX_Pos       (0U)
4585 #define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */
4586 #define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */
4587 #define FDCAN_HPMS_MSI_Pos        (6U)
4588 #define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
4589 #define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */
4590 #define FDCAN_HPMS_FIDX_Pos       (8U)
4591 #define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */
4592 #define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */
4593 #define FDCAN_HPMS_FLST_Pos       (15U)
4594 #define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
4595 #define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */
4596 
4597 /*****************  Bit definition for FDCAN_NDAT1 register  ********************/
4598 #define FDCAN_NDAT1_ND0_Pos       (0U)
4599 #define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */
4600 #define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */
4601 #define FDCAN_NDAT1_ND1_Pos       (1U)
4602 #define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */
4603 #define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */
4604 #define FDCAN_NDAT1_ND2_Pos       (2U)
4605 #define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */
4606 #define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */
4607 #define FDCAN_NDAT1_ND3_Pos       (3U)
4608 #define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */
4609 #define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */
4610 #define FDCAN_NDAT1_ND4_Pos       (4U)
4611 #define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */
4612 #define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */
4613 #define FDCAN_NDAT1_ND5_Pos       (5U)
4614 #define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */
4615 #define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */
4616 #define FDCAN_NDAT1_ND6_Pos       (6U)
4617 #define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */
4618 #define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */
4619 #define FDCAN_NDAT1_ND7_Pos       (7U)
4620 #define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */
4621 #define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */
4622 #define FDCAN_NDAT1_ND8_Pos       (8U)
4623 #define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */
4624 #define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */
4625 #define FDCAN_NDAT1_ND9_Pos       (9U)
4626 #define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */
4627 #define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */
4628 #define FDCAN_NDAT1_ND10_Pos      (10U)
4629 #define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */
4630 #define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */
4631 #define FDCAN_NDAT1_ND11_Pos      (11U)
4632 #define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */
4633 #define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */
4634 #define FDCAN_NDAT1_ND12_Pos      (12U)
4635 #define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */
4636 #define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */
4637 #define FDCAN_NDAT1_ND13_Pos      (13U)
4638 #define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */
4639 #define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */
4640 #define FDCAN_NDAT1_ND14_Pos      (14U)
4641 #define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */
4642 #define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */
4643 #define FDCAN_NDAT1_ND15_Pos      (15U)
4644 #define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */
4645 #define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */
4646 #define FDCAN_NDAT1_ND16_Pos      (16U)
4647 #define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */
4648 #define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */
4649 #define FDCAN_NDAT1_ND17_Pos      (17U)
4650 #define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */
4651 #define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */
4652 #define FDCAN_NDAT1_ND18_Pos      (18U)
4653 #define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */
4654 #define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */
4655 #define FDCAN_NDAT1_ND19_Pos      (19U)
4656 #define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */
4657 #define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */
4658 #define FDCAN_NDAT1_ND20_Pos      (20U)
4659 #define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */
4660 #define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */
4661 #define FDCAN_NDAT1_ND21_Pos      (21U)
4662 #define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */
4663 #define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */
4664 #define FDCAN_NDAT1_ND22_Pos      (22U)
4665 #define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */
4666 #define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */
4667 #define FDCAN_NDAT1_ND23_Pos      (23U)
4668 #define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */
4669 #define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */
4670 #define FDCAN_NDAT1_ND24_Pos      (24U)
4671 #define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */
4672 #define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */
4673 #define FDCAN_NDAT1_ND25_Pos      (25U)
4674 #define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */
4675 #define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */
4676 #define FDCAN_NDAT1_ND26_Pos      (26U)
4677 #define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */
4678 #define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */
4679 #define FDCAN_NDAT1_ND27_Pos      (27U)
4680 #define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */
4681 #define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */
4682 #define FDCAN_NDAT1_ND28_Pos      (28U)
4683 #define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */
4684 #define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */
4685 #define FDCAN_NDAT1_ND29_Pos      (29U)
4686 #define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */
4687 #define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */
4688 #define FDCAN_NDAT1_ND30_Pos      (30U)
4689 #define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */
4690 #define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */
4691 #define FDCAN_NDAT1_ND31_Pos      (31U)
4692 #define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */
4693 #define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */
4694 
4695 /*****************  Bit definition for FDCAN_NDAT2 register  ********************/
4696 #define FDCAN_NDAT2_ND32_Pos      (0U)
4697 #define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */
4698 #define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */
4699 #define FDCAN_NDAT2_ND33_Pos      (1U)
4700 #define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */
4701 #define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */
4702 #define FDCAN_NDAT2_ND34_Pos      (2U)
4703 #define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */
4704 #define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */
4705 #define FDCAN_NDAT2_ND35_Pos      (3U)
4706 #define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */
4707 #define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */
4708 #define FDCAN_NDAT2_ND36_Pos      (4U)
4709 #define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */
4710 #define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */
4711 #define FDCAN_NDAT2_ND37_Pos      (5U)
4712 #define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */
4713 #define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */
4714 #define FDCAN_NDAT2_ND38_Pos      (6U)
4715 #define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */
4716 #define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */
4717 #define FDCAN_NDAT2_ND39_Pos      (7U)
4718 #define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */
4719 #define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */
4720 #define FDCAN_NDAT2_ND40_Pos      (8U)
4721 #define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */
4722 #define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */
4723 #define FDCAN_NDAT2_ND41_Pos      (9U)
4724 #define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */
4725 #define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */
4726 #define FDCAN_NDAT2_ND42_Pos      (10U)
4727 #define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */
4728 #define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */
4729 #define FDCAN_NDAT2_ND43_Pos      (11U)
4730 #define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */
4731 #define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */
4732 #define FDCAN_NDAT2_ND44_Pos      (12U)
4733 #define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */
4734 #define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */
4735 #define FDCAN_NDAT2_ND45_Pos      (13U)
4736 #define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */
4737 #define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */
4738 #define FDCAN_NDAT2_ND46_Pos      (14U)
4739 #define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */
4740 #define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */
4741 #define FDCAN_NDAT2_ND47_Pos      (15U)
4742 #define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */
4743 #define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */
4744 #define FDCAN_NDAT2_ND48_Pos      (16U)
4745 #define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */
4746 #define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */
4747 #define FDCAN_NDAT2_ND49_Pos      (17U)
4748 #define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */
4749 #define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */
4750 #define FDCAN_NDAT2_ND50_Pos      (18U)
4751 #define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */
4752 #define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */
4753 #define FDCAN_NDAT2_ND51_Pos      (19U)
4754 #define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */
4755 #define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */
4756 #define FDCAN_NDAT2_ND52_Pos      (20U)
4757 #define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */
4758 #define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */
4759 #define FDCAN_NDAT2_ND53_Pos      (21U)
4760 #define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */
4761 #define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */
4762 #define FDCAN_NDAT2_ND54_Pos      (22U)
4763 #define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */
4764 #define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */
4765 #define FDCAN_NDAT2_ND55_Pos      (23U)
4766 #define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */
4767 #define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */
4768 #define FDCAN_NDAT2_ND56_Pos      (24U)
4769 #define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */
4770 #define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */
4771 #define FDCAN_NDAT2_ND57_Pos      (25U)
4772 #define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */
4773 #define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */
4774 #define FDCAN_NDAT2_ND58_Pos      (26U)
4775 #define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */
4776 #define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */
4777 #define FDCAN_NDAT2_ND59_Pos      (27U)
4778 #define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */
4779 #define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */
4780 #define FDCAN_NDAT2_ND60_Pos      (28U)
4781 #define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */
4782 #define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */
4783 #define FDCAN_NDAT2_ND61_Pos      (29U)
4784 #define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */
4785 #define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */
4786 #define FDCAN_NDAT2_ND62_Pos      (30U)
4787 #define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */
4788 #define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */
4789 #define FDCAN_NDAT2_ND63_Pos      (31U)
4790 #define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */
4791 #define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */
4792 
4793 /*****************  Bit definition for FDCAN_RXF0C register  ********************/
4794 #define FDCAN_RXF0C_F0SA_Pos      (2U)
4795 #define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */
4796 #define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */
4797 #define FDCAN_RXF0C_F0S_Pos       (16U)
4798 #define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */
4799 #define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */
4800 #define FDCAN_RXF0C_F0WM_Pos      (24U)
4801 #define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */
4802 #define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */
4803 #define FDCAN_RXF0C_F0OM_Pos      (31U)
4804 #define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */
4805 #define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */
4806 
4807 /*****************  Bit definition for FDCAN_RXF0S register  ********************/
4808 #define FDCAN_RXF0S_F0FL_Pos      (0U)
4809 #define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */
4810 #define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */
4811 #define FDCAN_RXF0S_F0GI_Pos      (8U)
4812 #define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */
4813 #define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */
4814 #define FDCAN_RXF0S_F0PI_Pos      (16U)
4815 #define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */
4816 #define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */
4817 #define FDCAN_RXF0S_F0F_Pos       (24U)
4818 #define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
4819 #define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */
4820 #define FDCAN_RXF0S_RF0L_Pos      (25U)
4821 #define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
4822 #define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */
4823 
4824 /*****************  Bit definition for FDCAN_RXF0A register  ********************/
4825 #define FDCAN_RXF0A_F0AI_Pos      (0U)
4826 #define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */
4827 #define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */
4828 
4829 /*****************  Bit definition for FDCAN_RXBC register  ********************/
4830 #define FDCAN_RXBC_RBSA_Pos       (2U)
4831 #define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */
4832 #define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */
4833 
4834 /*****************  Bit definition for FDCAN_RXF1C register  ********************/
4835 #define FDCAN_RXF1C_F1SA_Pos      (2U)
4836 #define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */
4837 #define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */
4838 #define FDCAN_RXF1C_F1S_Pos       (16U)
4839 #define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */
4840 #define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */
4841 #define FDCAN_RXF1C_F1WM_Pos      (24U)
4842 #define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */
4843 #define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */
4844 #define FDCAN_RXF1C_F1OM_Pos      (31U)
4845 #define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */
4846 #define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */
4847 
4848 /*****************  Bit definition for FDCAN_RXF1S register  ********************/
4849 #define FDCAN_RXF1S_F1FL_Pos      (0U)
4850 #define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */
4851 #define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */
4852 #define FDCAN_RXF1S_F1GI_Pos      (8U)
4853 #define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */
4854 #define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */
4855 #define FDCAN_RXF1S_F1PI_Pos      (16U)
4856 #define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */
4857 #define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */
4858 #define FDCAN_RXF1S_F1F_Pos       (24U)
4859 #define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
4860 #define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */
4861 #define FDCAN_RXF1S_RF1L_Pos      (25U)
4862 #define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
4863 #define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */
4864 
4865 /*****************  Bit definition for FDCAN_RXF1A register  ********************/
4866 #define FDCAN_RXF1A_F1AI_Pos      (0U)
4867 #define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */
4868 #define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */
4869 
4870 /*****************  Bit definition for FDCAN_RXESC register  ********************/
4871 #define FDCAN_RXESC_F0DS_Pos      (0U)
4872 #define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */
4873 #define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */
4874 #define FDCAN_RXESC_F1DS_Pos      (4U)
4875 #define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */
4876 #define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */
4877 #define FDCAN_RXESC_RBDS_Pos      (8U)
4878 #define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */
4879 #define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */
4880 
4881 /*****************  Bit definition for FDCAN_TXBC register  *********************/
4882 #define FDCAN_TXBC_TBSA_Pos       (2U)
4883 #define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */
4884 #define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */
4885 #define FDCAN_TXBC_NDTB_Pos       (16U)
4886 #define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */
4887 #define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */
4888 #define FDCAN_TXBC_TFQS_Pos       (24U)
4889 #define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */
4890 #define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */
4891 #define FDCAN_TXBC_TFQM_Pos       (30U)
4892 #define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */
4893 #define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */
4894 
4895 /*****************  Bit definition for FDCAN_TXFQS register  *********************/
4896 #define FDCAN_TXFQS_TFFL_Pos      (0U)
4897 #define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */
4898 #define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */
4899 #define FDCAN_TXFQS_TFGI_Pos      (8U)
4900 #define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */
4901 #define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */
4902 #define FDCAN_TXFQS_TFQPI_Pos     (16U)
4903 #define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */
4904 #define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */
4905 #define FDCAN_TXFQS_TFQF_Pos      (21U)
4906 #define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
4907 #define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */
4908 
4909 /*****************  Bit definition for FDCAN_TXESC register  *********************/
4910 #define FDCAN_TXESC_TBDS_Pos      (0U)
4911 #define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */
4912 #define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */
4913 
4914 /*****************  Bit definition for FDCAN_TXBRP register  *********************/
4915 #define FDCAN_TXBRP_TRP_Pos       (0U)
4916 #define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */
4917 #define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */
4918 
4919 /*****************  Bit definition for FDCAN_TXBAR register  *********************/
4920 #define FDCAN_TXBAR_AR_Pos        (0U)
4921 #define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */
4922 #define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */
4923 
4924 /*****************  Bit definition for FDCAN_TXBCR register  *********************/
4925 #define FDCAN_TXBCR_CR_Pos        (0U)
4926 #define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */
4927 #define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */
4928 
4929 /*****************  Bit definition for FDCAN_TXBTO register  *********************/
4930 #define FDCAN_TXBTO_TO_Pos        (0U)
4931 #define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */
4932 #define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */
4933 
4934 /*****************  Bit definition for FDCAN_TXBCF register  *********************/
4935 #define FDCAN_TXBCF_CF_Pos        (0U)
4936 #define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */
4937 #define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */
4938 
4939 /*****************  Bit definition for FDCAN_TXBTIE register  ********************/
4940 #define FDCAN_TXBTIE_TIE_Pos      (0U)
4941 #define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */
4942 #define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */
4943 
4944 /*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
4945 #define FDCAN_TXBCIE_CFIE_Pos     (0U)
4946 #define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */
4947 #define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */
4948 
4949 /*****************  Bit definition for FDCAN_TXEFC register  *********************/
4950 #define FDCAN_TXEFC_EFSA_Pos      (2U)
4951 #define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */
4952 #define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */
4953 #define FDCAN_TXEFC_EFS_Pos       (16U)
4954 #define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */
4955 #define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */
4956 #define FDCAN_TXEFC_EFWM_Pos      (24U)
4957 #define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */
4958 #define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */
4959 
4960 /*****************  Bit definition for FDCAN_TXEFS register  *********************/
4961 #define FDCAN_TXEFS_EFFL_Pos      (0U)
4962 #define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */
4963 #define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */
4964 #define FDCAN_TXEFS_EFGI_Pos      (8U)
4965 #define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */
4966 #define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */
4967 #define FDCAN_TXEFS_EFPI_Pos      (16U)
4968 #define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */
4969 #define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */
4970 #define FDCAN_TXEFS_EFF_Pos       (24U)
4971 #define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
4972 #define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */
4973 #define FDCAN_TXEFS_TEFL_Pos      (25U)
4974 #define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
4975 #define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */
4976 
4977 /*****************  Bit definition for FDCAN_TXEFA register  *********************/
4978 #define FDCAN_TXEFA_EFAI_Pos      (0U)
4979 #define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */
4980 #define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */
4981 
4982 /*****************  Bit definition for FDCAN_TTTMC register  *********************/
4983 #define FDCAN_TTTMC_TMSA_Pos      (2U)
4984 #define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */
4985 #define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */
4986 #define FDCAN_TTTMC_TME_Pos       (16U)
4987 #define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */
4988 #define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */
4989 
4990 /*****************  Bit definition for FDCAN_TTRMC register  *********************/
4991 #define FDCAN_TTRMC_RID_Pos       (0U)
4992 #define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */
4993 #define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */
4994 #define FDCAN_TTRMC_XTD_Pos       (30U)
4995 #define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */
4996 #define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */
4997 #define FDCAN_TTRMC_RMPS_Pos      (31U)
4998 #define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */
4999 #define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */
5000 
5001 /*****************  Bit definition for FDCAN_TTOCF register  *********************/
5002 #define FDCAN_TTOCF_OM_Pos        (0U)
5003 #define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */
5004 #define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */
5005 #define FDCAN_TTOCF_GEN_Pos       (3U)
5006 #define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */
5007 #define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */
5008 #define FDCAN_TTOCF_TM_Pos        (4U)
5009 #define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */
5010 #define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */
5011 #define FDCAN_TTOCF_LDSDL_Pos     (5U)
5012 #define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */
5013 #define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */
5014 #define FDCAN_TTOCF_IRTO_Pos      (8U)
5015 #define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */
5016 #define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */
5017 #define FDCAN_TTOCF_EECS_Pos      (15U)
5018 #define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */
5019 #define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */
5020 #define FDCAN_TTOCF_AWL_Pos       (16U)
5021 #define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */
5022 #define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */
5023 #define FDCAN_TTOCF_EGTF_Pos      (24U)
5024 #define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */
5025 #define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */
5026 #define FDCAN_TTOCF_ECC_Pos       (25U)
5027 #define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */
5028 #define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */
5029 #define FDCAN_TTOCF_EVTP_Pos      (26U)
5030 #define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */
5031 #define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */
5032 
5033 /*****************  Bit definition for FDCAN_TTMLM register  *********************/
5034 #define FDCAN_TTMLM_CCM_Pos       (0U)
5035 #define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */
5036 #define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */
5037 #define FDCAN_TTMLM_CSS_Pos       (6U)
5038 #define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */
5039 #define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */
5040 #define FDCAN_TTMLM_TXEW_Pos      (8U)
5041 #define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */
5042 #define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */
5043 #define FDCAN_TTMLM_ENTT_Pos      (16U)
5044 #define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */
5045 #define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */
5046 
5047 /*****************  Bit definition for FDCAN_TURCF register  *********************/
5048 #define FDCAN_TURCF_NCL_Pos       (0U)
5049 #define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */
5050 #define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */
5051 #define FDCAN_TURCF_DC_Pos        (16U)
5052 #define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */
5053 #define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */
5054 #define FDCAN_TURCF_ELT_Pos       (31U)
5055 #define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */
5056 #define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */
5057 
5058 /*****************  Bit definition for FDCAN_TTOCN register  ********************/
5059 #define FDCAN_TTOCN_SGT_Pos       (0U)
5060 #define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */
5061 #define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */
5062 #define FDCAN_TTOCN_ECS_Pos       (1U)
5063 #define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */
5064 #define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */
5065 #define FDCAN_TTOCN_SWP_Pos       (2U)
5066 #define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */
5067 #define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */
5068 #define FDCAN_TTOCN_SWS_Pos       (3U)
5069 #define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */
5070 #define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */
5071 #define FDCAN_TTOCN_RTIE_Pos      (5U)
5072 #define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */
5073 #define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */
5074 #define FDCAN_TTOCN_TMC_Pos       (6U)
5075 #define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */
5076 #define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */
5077 #define FDCAN_TTOCN_TTIE_Pos      (8U)
5078 #define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */
5079 #define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */
5080 #define FDCAN_TTOCN_GCS_Pos       (9U)
5081 #define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */
5082 #define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */
5083 #define FDCAN_TTOCN_FGP_Pos       (10U)
5084 #define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */
5085 #define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */
5086 #define FDCAN_TTOCN_TMG_Pos       (11U)
5087 #define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */
5088 #define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */
5089 #define FDCAN_TTOCN_NIG_Pos       (12U)
5090 #define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */
5091 #define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */
5092 #define FDCAN_TTOCN_ESCN_Pos      (13U)
5093 #define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */
5094 #define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */
5095 #define FDCAN_TTOCN_LCKC_Pos      (15U)
5096 #define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */
5097 #define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */
5098 
5099 /*****************  Bit definition for FDCAN_TTGTP register  ********************/
5100 #define FDCAN_TTGTP_TP_Pos        (0U)
5101 #define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */
5102 #define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */
5103 #define FDCAN_TTGTP_CTP_Pos       (16U)
5104 #define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */
5105 #define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */
5106 
5107 /*****************  Bit definition for FDCAN_TTTMK register  ********************/
5108 #define FDCAN_TTTMK_TM_Pos        (0U)
5109 #define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */
5110 #define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */
5111 #define FDCAN_TTTMK_TICC_Pos      (16U)
5112 #define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */
5113 #define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */
5114 #define FDCAN_TTTMK_LCKM_Pos      (31U)
5115 #define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */
5116 #define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */
5117 
5118 /*****************  Bit definition for FDCAN_TTIR register  ********************/
5119 #define FDCAN_TTIR_SBC_Pos        (0U)
5120 #define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */
5121 #define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */
5122 #define FDCAN_TTIR_SMC_Pos        (1U)
5123 #define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */
5124 #define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */
5125 #define FDCAN_TTIR_CSM_Pos        (2U)
5126 #define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */
5127 #define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */
5128 #define FDCAN_TTIR_SOG_Pos        (3U)
5129 #define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */
5130 #define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */
5131 #define FDCAN_TTIR_RTMI_Pos       (4U)
5132 #define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */
5133 #define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */
5134 #define FDCAN_TTIR_TTMI_Pos       (5U)
5135 #define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */
5136 #define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */
5137 #define FDCAN_TTIR_SWE_Pos        (6U)
5138 #define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */
5139 #define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */
5140 #define FDCAN_TTIR_GTW_Pos        (7U)
5141 #define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */
5142 #define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */
5143 #define FDCAN_TTIR_GTD_Pos        (8U)
5144 #define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */
5145 #define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */
5146 #define FDCAN_TTIR_GTE_Pos        (9U)
5147 #define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */
5148 #define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */
5149 #define FDCAN_TTIR_TXU_Pos        (10U)
5150 #define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */
5151 #define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */
5152 #define FDCAN_TTIR_TXO_Pos        (11U)
5153 #define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */
5154 #define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */
5155 #define FDCAN_TTIR_SE1_Pos        (12U)
5156 #define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */
5157 #define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */
5158 #define FDCAN_TTIR_SE2_Pos        (13U)
5159 #define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */
5160 #define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */
5161 #define FDCAN_TTIR_ELC_Pos        (14U)
5162 #define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */
5163 #define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */
5164 #define FDCAN_TTIR_IWT_Pos        (15U)
5165 #define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */
5166 #define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */
5167 #define FDCAN_TTIR_WT_Pos         (16U)
5168 #define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */
5169 #define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */
5170 #define FDCAN_TTIR_AW_Pos         (17U)
5171 #define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */
5172 #define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */
5173 #define FDCAN_TTIR_CER_Pos        (18U)
5174 #define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */
5175 #define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */
5176 
5177 /*****************  Bit definition for FDCAN_TTIE register  ********************/
5178 #define FDCAN_TTIE_SBCE_Pos       (0U)
5179 #define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */
5180 #define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */
5181 #define FDCAN_TTIE_SMCE_Pos       (1U)
5182 #define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */
5183 #define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */
5184 #define FDCAN_TTIE_CSME_Pos       (2U)
5185 #define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */
5186 #define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */
5187 #define FDCAN_TTIE_SOGE_Pos       (3U)
5188 #define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */
5189 #define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */
5190 #define FDCAN_TTIE_RTMIE_Pos      (4U)
5191 #define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */
5192 #define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */
5193 #define FDCAN_TTIE_TTMIE_Pos      (5U)
5194 #define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */
5195 #define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */
5196 #define FDCAN_TTIE_SWEE_Pos       (6U)
5197 #define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */
5198 #define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */
5199 #define FDCAN_TTIE_GTWE_Pos       (7U)
5200 #define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */
5201 #define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */
5202 #define FDCAN_TTIE_GTDE_Pos       (8U)
5203 #define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */
5204 #define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */
5205 #define FDCAN_TTIE_GTEE_Pos       (9U)
5206 #define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */
5207 #define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */
5208 #define FDCAN_TTIE_TXUE_Pos       (10U)
5209 #define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */
5210 #define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */
5211 #define FDCAN_TTIE_TXOE_Pos       (11U)
5212 #define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */
5213 #define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */
5214 #define FDCAN_TTIE_SE1E_Pos       (12U)
5215 #define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */
5216 #define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */
5217 #define FDCAN_TTIE_SE2E_Pos       (13U)
5218 #define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */
5219 #define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */
5220 #define FDCAN_TTIE_ELCE_Pos       (14U)
5221 #define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */
5222 #define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */
5223 #define FDCAN_TTIE_IWTE_Pos       (15U)
5224 #define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */
5225 #define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */
5226 #define FDCAN_TTIE_WTE_Pos        (16U)
5227 #define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */
5228 #define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */
5229 #define FDCAN_TTIE_AWE_Pos        (17U)
5230 #define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */
5231 #define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */
5232 #define FDCAN_TTIE_CERE_Pos       (18U)
5233 #define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */
5234 #define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */
5235 
5236 /*****************  Bit definition for FDCAN_TTILS register  ********************/
5237 #define FDCAN_TTILS_SBCS_Pos      (0U)
5238 #define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */
5239 #define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */
5240 #define FDCAN_TTILS_SMCS_Pos      (1U)
5241 #define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */
5242 #define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */
5243 #define FDCAN_TTILS_CSMS_Pos      (2U)
5244 #define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */
5245 #define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */
5246 #define FDCAN_TTILS_SOGS_Pos      (3U)
5247 #define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */
5248 #define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */
5249 #define FDCAN_TTILS_RTMIS_Pos     (4U)
5250 #define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */
5251 #define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */
5252 #define FDCAN_TTILS_TTMIS_Pos     (5U)
5253 #define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */
5254 #define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */
5255 #define FDCAN_TTILS_SWES_Pos      (6U)
5256 #define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */
5257 #define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */
5258 #define FDCAN_TTILS_GTWS_Pos      (7U)
5259 #define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */
5260 #define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */
5261 #define FDCAN_TTILS_GTDS_Pos      (8U)
5262 #define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */
5263 #define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */
5264 #define FDCAN_TTILS_GTES_Pos      (9U)
5265 #define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */
5266 #define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */
5267 #define FDCAN_TTILS_TXUS_Pos      (10U)
5268 #define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */
5269 #define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */
5270 #define FDCAN_TTILS_TXOS_Pos      (11U)
5271 #define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */
5272 #define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */
5273 #define FDCAN_TTILS_SE1S_Pos      (12U)
5274 #define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */
5275 #define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */
5276 #define FDCAN_TTILS_SE2S_Pos      (13U)
5277 #define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */
5278 #define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */
5279 #define FDCAN_TTILS_ELCS_Pos      (14U)
5280 #define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */
5281 #define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */
5282 #define FDCAN_TTILS_IWTS_Pos      (15U)
5283 #define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */
5284 #define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */
5285 #define FDCAN_TTILS_WTS_Pos       (16U)
5286 #define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */
5287 #define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */
5288 #define FDCAN_TTILS_AWS_Pos       (17U)
5289 #define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */
5290 #define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */
5291 #define FDCAN_TTILS_CERS_Pos      (18U)
5292 #define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */
5293 #define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */
5294 
5295 /*****************  Bit definition for FDCAN_TTOST register  ********************/
5296 #define FDCAN_TTOST_EL_Pos        (0U)
5297 #define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */
5298 #define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */
5299 #define FDCAN_TTOST_MS_Pos        (2U)
5300 #define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */
5301 #define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */
5302 #define FDCAN_TTOST_SYS_Pos       (4U)
5303 #define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */
5304 #define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */
5305 #define FDCAN_TTOST_QGTP_Pos      (6U)
5306 #define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */
5307 #define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */
5308 #define FDCAN_TTOST_QCS_Pos       (7U)
5309 #define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */
5310 #define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */
5311 #define FDCAN_TTOST_RTO_Pos       (8U)
5312 #define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */
5313 #define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */
5314 #define FDCAN_TTOST_WGTD_Pos      (22U)
5315 #define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */
5316 #define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */
5317 #define FDCAN_TTOST_GFI_Pos       (23U)
5318 #define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */
5319 #define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */
5320 #define FDCAN_TTOST_TMP_Pos       (24U)
5321 #define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */
5322 #define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */
5323 #define FDCAN_TTOST_GSI_Pos       (27U)
5324 #define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */
5325 #define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */
5326 #define FDCAN_TTOST_WFE_Pos       (28U)
5327 #define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */
5328 #define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */
5329 #define FDCAN_TTOST_AWE_Pos       (29U)
5330 #define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */
5331 #define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */
5332 #define FDCAN_TTOST_WECS_Pos      (30U)
5333 #define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */
5334 #define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */
5335 #define FDCAN_TTOST_SPL_Pos       (31U)
5336 #define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */
5337 #define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */
5338 
5339 /*****************  Bit definition for FDCAN_TURNA register  ********************/
5340 #define FDCAN_TURNA_NAV_Pos       (0U)
5341 #define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */
5342 #define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */
5343 
5344 /*****************  Bit definition for FDCAN_TTLGT register  ********************/
5345 #define FDCAN_TTLGT_LT_Pos        (0U)
5346 #define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */
5347 #define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */
5348 #define FDCAN_TTLGT_GT_Pos        (16U)
5349 #define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */
5350 #define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */
5351 
5352 /*****************  Bit definition for FDCAN_TTCTC register  ********************/
5353 #define FDCAN_TTCTC_CT_Pos        (0U)
5354 #define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */
5355 #define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */
5356 #define FDCAN_TTCTC_CC_Pos        (16U)
5357 #define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */
5358 #define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */
5359 
5360 /*****************  Bit definition for FDCAN_TTCPT register  ********************/
5361 #define FDCAN_TTCPT_CCV_Pos       (0U)
5362 #define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */
5363 #define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */
5364 #define FDCAN_TTCPT_SWV_Pos       (16U)
5365 #define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */
5366 #define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */
5367 
5368 /*****************  Bit definition for FDCAN_TTCSM register  ********************/
5369 #define FDCAN_TTCSM_CSM_Pos       (0U)
5370 #define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */
5371 #define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */
5372 
5373 /*****************  Bit definition for FDCAN_TTTS register  *********************/
5374 #define FDCAN_TTTS_SWTSEL_Pos     (0U)
5375 #define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */
5376 #define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */
5377 #define FDCAN_TTTS_EVTSEL_Pos     (4U)
5378 #define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */
5379 #define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */
5380 
5381 /********************************************************************************/
5382 /*                                                                              */
5383 /*                      FDCANCCU (Clock Calibration unit)                       */
5384 /*                                                                              */
5385 /********************************************************************************/
5386 
5387 /*****************  Bit definition for FDCANCCU_CREL register  ******************/
5388 #define FDCANCCU_CREL_DAY_Pos        (0U)
5389 #define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
5390 #define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
5391 #define FDCANCCU_CREL_MON_Pos        (8U)
5392 #define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
5393 #define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
5394 #define FDCANCCU_CREL_YEAR_Pos       (16U)
5395 #define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
5396 #define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
5397 #define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
5398 #define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
5399 #define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
5400 #define FDCANCCU_CREL_STEP_Pos       (24U)
5401 #define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
5402 #define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
5403 #define FDCANCCU_CREL_REL_Pos        (28U)
5404 #define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
5405 #define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
5406 
5407 /*****************  Bit definition for FDCANCCU_CCFG register  ******************/
5408 #define FDCANCCU_CCFG_TQBT_Pos       (0U)
5409 #define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
5410 #define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
5411 #define FDCANCCU_CCFG_BCC_Pos        (6U)
5412 #define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
5413 #define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
5414 #define FDCANCCU_CCFG_CFL_Pos        (7U)
5415 #define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
5416 #define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
5417 #define FDCANCCU_CCFG_OCPM_Pos       (8U)
5418 #define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
5419 #define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
5420 #define FDCANCCU_CCFG_CDIV_Pos       (16U)
5421 #define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
5422 #define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
5423 #define FDCANCCU_CCFG_SWR_Pos        (31U)
5424 #define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
5425 #define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
5426 
5427 /*****************  Bit definition for FDCANCCU_CSTAT register  *****************/
5428 #define FDCANCCU_CSTAT_OCPC_Pos      (0U)
5429 #define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
5430 #define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
5431 #define FDCANCCU_CSTAT_TQC_Pos       (18U)
5432 #define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
5433 #define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
5434 #define FDCANCCU_CSTAT_CALS_Pos      (30U)
5435 #define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
5436 #define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
5437 
5438 /******************  Bit definition for FDCANCCU_CWD register  ******************/
5439 #define FDCANCCU_CWD_WDC_Pos         (0U)
5440 #define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
5441 #define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
5442 #define FDCANCCU_CWD_WDV_Pos         (16U)
5443 #define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
5444 #define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
5445 
5446 /******************  Bit definition for FDCANCCU_IR register  *******************/
5447 #define FDCANCCU_IR_CWE_Pos          (0U)
5448 #define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
5449 #define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
5450 #define FDCANCCU_IR_CSC_Pos          (1U)
5451 #define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
5452 #define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
5453 
5454 /******************  Bit definition for FDCANCCU_IE register  *******************/
5455 #define FDCANCCU_IE_CWEE_Pos         (0U)
5456 #define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
5457 #define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
5458 #define FDCANCCU_IE_CSCE_Pos         (1U)
5459 #define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
5460 #define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
5461 
5462 /******************************************************************************/
5463 /*                                                                            */
5464 /*                          HDMI-CEC (CEC)                                    */
5465 /*                                                                            */
5466 /******************************************************************************/
5467 
5468 /*******************  Bit definition for CEC_CR register  *********************/
5469 #define CEC_CR_CECEN_Pos         (0U)
5470 #define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
5471 #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
5472 #define CEC_CR_TXSOM_Pos         (1U)
5473 #define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
5474 #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
5475 #define CEC_CR_TXEOM_Pos         (2U)
5476 #define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
5477 #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
5478 
5479 /*******************  Bit definition for CEC_CFGR register  *******************/
5480 #define CEC_CFGR_SFT_Pos         (0U)
5481 #define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
5482 #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
5483 #define CEC_CFGR_RXTOL_Pos       (3U)
5484 #define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
5485 #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
5486 #define CEC_CFGR_BRESTP_Pos      (4U)
5487 #define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
5488 #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
5489 #define CEC_CFGR_BREGEN_Pos      (5U)
5490 #define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
5491 #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
5492 #define CEC_CFGR_LBPEGEN_Pos     (6U)
5493 #define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
5494 #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
5495 #define CEC_CFGR_SFTOPT_Pos      (8U)
5496 #define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
5497 #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
5498 #define CEC_CFGR_BRDNOGEN_Pos    (7U)
5499 #define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
5500 #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
5501 #define CEC_CFGR_OAR_Pos         (16U)
5502 #define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
5503 #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
5504 #define CEC_CFGR_LSTN_Pos        (31U)
5505 #define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
5506 #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
5507 
5508 /*******************  Bit definition for CEC_TXDR register  *******************/
5509 #define CEC_TXDR_TXD_Pos         (0U)
5510 #define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
5511 #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
5512 
5513 /*******************  Bit definition for CEC_RXDR register  *******************/
5514 #define CEC_RXDR_RXD_Pos         (0U)
5515 #define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
5516 #define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */
5517 
5518 /*******************  Bit definition for CEC_ISR register  ********************/
5519 #define CEC_ISR_RXBR_Pos         (0U)
5520 #define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
5521 #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
5522 #define CEC_ISR_RXEND_Pos        (1U)
5523 #define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
5524 #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
5525 #define CEC_ISR_RXOVR_Pos        (2U)
5526 #define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
5527 #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
5528 #define CEC_ISR_BRE_Pos          (3U)
5529 #define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
5530 #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
5531 #define CEC_ISR_SBPE_Pos         (4U)
5532 #define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
5533 #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
5534 #define CEC_ISR_LBPE_Pos         (5U)
5535 #define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
5536 #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
5537 #define CEC_ISR_RXACKE_Pos       (6U)
5538 #define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
5539 #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
5540 #define CEC_ISR_ARBLST_Pos       (7U)
5541 #define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
5542 #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
5543 #define CEC_ISR_TXBR_Pos         (8U)
5544 #define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
5545 #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
5546 #define CEC_ISR_TXEND_Pos        (9U)
5547 #define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
5548 #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
5549 #define CEC_ISR_TXUDR_Pos        (10U)
5550 #define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
5551 #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
5552 #define CEC_ISR_TXERR_Pos        (11U)
5553 #define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
5554 #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
5555 #define CEC_ISR_TXACKE_Pos       (12U)
5556 #define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
5557 #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
5558 
5559 /*******************  Bit definition for CEC_IER register  ********************/
5560 #define CEC_IER_RXBRIE_Pos       (0U)
5561 #define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
5562 #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
5563 #define CEC_IER_RXENDIE_Pos      (1U)
5564 #define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
5565 #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
5566 #define CEC_IER_RXOVRIE_Pos      (2U)
5567 #define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
5568 #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
5569 #define CEC_IER_BREIE_Pos        (3U)
5570 #define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
5571 #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
5572 #define CEC_IER_SBPEIE_Pos       (4U)
5573 #define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
5574 #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
5575 #define CEC_IER_LBPEIE_Pos       (5U)
5576 #define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
5577 #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
5578 #define CEC_IER_RXACKEIE_Pos     (6U)
5579 #define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
5580 #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
5581 #define CEC_IER_ARBLSTIE_Pos     (7U)
5582 #define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
5583 #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
5584 #define CEC_IER_TXBRIE_Pos       (8U)
5585 #define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
5586 #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
5587 #define CEC_IER_TXENDIE_Pos      (9U)
5588 #define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
5589 #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
5590 #define CEC_IER_TXUDRIE_Pos      (10U)
5591 #define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
5592 #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
5593 #define CEC_IER_TXERRIE_Pos      (11U)
5594 #define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
5595 #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
5596 #define CEC_IER_TXACKEIE_Pos     (12U)
5597 #define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
5598 #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
5599 
5600 /******************************************************************************/
5601 /*                                                                            */
5602 /*                          CRC calculation unit                              */
5603 /*                                                                            */
5604 /******************************************************************************/
5605 /*******************  Bit definition for CRC_DR register  *********************/
5606 #define CRC_DR_DR_Pos            (0U)
5607 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
5608 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
5609 
5610 /*******************  Bit definition for CRC_IDR register  ********************/
5611 #define CRC_IDR_IDR_Pos          (0U)
5612 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
5613 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
5614 
5615 /********************  Bit definition for CRC_CR register  ********************/
5616 #define CRC_CR_RESET_Pos         (0U)
5617 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
5618 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
5619 #define CRC_CR_POLYSIZE_Pos      (3U)
5620 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
5621 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
5622 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
5623 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
5624 #define CRC_CR_REV_IN_Pos        (5U)
5625 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
5626 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
5627 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
5628 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
5629 #define CRC_CR_REV_OUT_Pos       (7U)
5630 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
5631 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
5632 
5633 /*******************  Bit definition for CRC_INIT register  *******************/
5634 #define CRC_INIT_INIT_Pos        (0U)
5635 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
5636 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
5637 
5638 /*******************  Bit definition for CRC_POL register  ********************/
5639 #define CRC_POL_POL_Pos          (0U)
5640 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
5641 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
5642 
5643 /******************************************************************************/
5644 /*                                                                            */
5645 /*                          CRS Clock Recovery System                         */
5646 /******************************************************************************/
5647 
5648 /*******************  Bit definition for CRS_CR register  *********************/
5649 #define CRS_CR_SYNCOKIE_Pos       (0U)
5650 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
5651 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
5652 #define CRS_CR_SYNCWARNIE_Pos     (1U)
5653 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
5654 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
5655 #define CRS_CR_ERRIE_Pos          (2U)
5656 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
5657 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
5658 #define CRS_CR_ESYNCIE_Pos        (3U)
5659 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
5660 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
5661 #define CRS_CR_CEN_Pos            (5U)
5662 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
5663 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
5664 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
5665 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
5666 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
5667 #define CRS_CR_SWSYNC_Pos         (7U)
5668 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
5669 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
5670 #define CRS_CR_TRIM_Pos           (8U)
5671 #define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
5672 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
5673 
5674 /*******************  Bit definition for CRS_CFGR register  *********************/
5675 #define CRS_CFGR_RELOAD_Pos       (0U)
5676 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
5677 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
5678 #define CRS_CFGR_FELIM_Pos        (16U)
5679 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
5680 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
5681 
5682 #define CRS_CFGR_SYNCDIV_Pos      (24U)
5683 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
5684 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
5685 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
5686 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
5687 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
5688 
5689 #define CRS_CFGR_SYNCSRC_Pos      (28U)
5690 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
5691 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
5692 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
5693 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
5694 
5695 #define CRS_CFGR_SYNCPOL_Pos      (31U)
5696 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
5697 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
5698 
5699 /*******************  Bit definition for CRS_ISR register  *********************/
5700 #define CRS_ISR_SYNCOKF_Pos       (0U)
5701 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
5702 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
5703 #define CRS_ISR_SYNCWARNF_Pos     (1U)
5704 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
5705 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
5706 #define CRS_ISR_ERRF_Pos          (2U)
5707 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
5708 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
5709 #define CRS_ISR_ESYNCF_Pos        (3U)
5710 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
5711 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
5712 #define CRS_ISR_SYNCERR_Pos       (8U)
5713 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
5714 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
5715 #define CRS_ISR_SYNCMISS_Pos      (9U)
5716 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
5717 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
5718 #define CRS_ISR_TRIMOVF_Pos       (10U)
5719 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
5720 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
5721 #define CRS_ISR_FEDIR_Pos         (15U)
5722 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
5723 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
5724 #define CRS_ISR_FECAP_Pos         (16U)
5725 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
5726 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
5727 
5728 /*******************  Bit definition for CRS_ICR register  *********************/
5729 #define CRS_ICR_SYNCOKC_Pos       (0U)
5730 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
5731 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
5732 #define CRS_ICR_SYNCWARNC_Pos     (1U)
5733 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
5734 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
5735 #define CRS_ICR_ERRC_Pos          (2U)
5736 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
5737 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
5738 #define CRS_ICR_ESYNCC_Pos        (3U)
5739 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
5740 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
5741 
5742 /******************************************************************************/
5743 /*                                                                            */
5744 /*                            Crypto Processor                                */
5745 /*                                                                            */
5746 /******************************************************************************/
5747 /********************************  CRYP VER  **********************************/
5748 #define  CRYP_VER_2_2
5749 /******************* Bits definition for CRYP_CR register  ********************/
5750 #define CRYP_CR_ALGODIR_Pos              (2U)
5751 #define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */
5752 #define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk
5753 
5754 #define CRYP_CR_ALGOMODE_Pos             (3U)
5755 #define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */
5756 #define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk
5757 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
5758 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
5759 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
5760 #define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
5761 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
5762 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5763 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
5764 #define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)
5765 #define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5766 #define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk
5767 #define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)
5768 #define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5769 #define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk
5770 #define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)
5771 #define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5772 #define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk
5773 #define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)
5774 #define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5775 #define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk
5776 #define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)
5777 #define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5778 #define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk
5779 #define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)
5780 #define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5781 #define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk
5782 #define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)
5783 #define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
5784 #define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk
5785 #define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)
5786 #define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
5787 #define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk
5788 
5789 #define CRYP_CR_DATATYPE_Pos             (6U)
5790 #define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */
5791 #define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk
5792 #define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */
5793 #define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */
5794 #define CRYP_CR_KEYSIZE_Pos              (8U)
5795 #define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */
5796 #define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk
5797 #define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */
5798 #define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */
5799 #define CRYP_CR_FFLUSH_Pos               (14U)
5800 #define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */
5801 #define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk
5802 #define CRYP_CR_CRYPEN_Pos               (15U)
5803 #define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */
5804 #define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk
5805 
5806 #define CRYP_CR_GCM_CCMPH_Pos            (16U)
5807 #define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */
5808 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
5809 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
5810 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
5811 #define CRYP_CR_ALGOMODE_3               (0x00080000U)
5812 #define CRYP_CR_NPBLB_Pos                (20U)
5813 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
5814 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
5815 
5816 /****************** Bits definition for CRYP_SR register  *********************/
5817 #define CRYP_SR_IFEM_Pos                 (0U)
5818 #define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */
5819 #define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk
5820 #define CRYP_SR_IFNF_Pos                 (1U)
5821 #define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */
5822 #define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk
5823 #define CRYP_SR_OFNE_Pos                 (2U)
5824 #define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */
5825 #define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk
5826 #define CRYP_SR_OFFU_Pos                 (3U)
5827 #define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */
5828 #define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk
5829 #define CRYP_SR_BUSY_Pos                 (4U)
5830 #define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */
5831 #define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk
5832 /****************** Bits definition for CRYP_DMACR register  ******************/
5833 #define CRYP_DMACR_DIEN_Pos              (0U)
5834 #define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */
5835 #define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk
5836 #define CRYP_DMACR_DOEN_Pos              (1U)
5837 #define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */
5838 #define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk
5839 /*****************  Bits definition for CRYP_IMSCR register  ******************/
5840 #define CRYP_IMSCR_INIM_Pos              (0U)
5841 #define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */
5842 #define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk
5843 #define CRYP_IMSCR_OUTIM_Pos             (1U)
5844 #define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */
5845 #define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk
5846 /****************** Bits definition for CRYP_RISR register  *******************/
5847 #define CRYP_RISR_INRIS_Pos              (0U)
5848 #define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */
5849 #define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk
5850 #define CRYP_RISR_OUTRIS_Pos             (1U)
5851 #define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */
5852 #define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk
5853 /****************** Bits definition for CRYP_MISR register  *******************/
5854 #define CRYP_MISR_INMIS_Pos              (0U)
5855 #define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */
5856 #define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk
5857 #define CRYP_MISR_OUTMIS_Pos             (1U)
5858 #define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */
5859 #define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk
5860 
5861 /******************************************************************************/
5862 /*                                                                            */
5863 /*                      Digital to Analog Converter                           */
5864 /*                                                                            */
5865 /******************************************************************************/
5866 /********************  Bit definition for DAC_CR register  ********************/
5867 #define DAC_CR_EN1_Pos              (0U)
5868 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
5869 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
5870 #define DAC_CR_TEN1_Pos             (1U)
5871 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
5872 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
5873 
5874 #define DAC_CR_TSEL1_Pos            (2U)
5875 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
5876 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5877 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
5878 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5879 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5880 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5881 
5882 
5883 #define DAC_CR_WAVE1_Pos            (6U)
5884 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
5885 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5886 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5887 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5888 
5889 #define DAC_CR_MAMP1_Pos            (8U)
5890 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
5891 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5892 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5893 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5894 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5895 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5896 
5897 #define DAC_CR_DMAEN1_Pos           (12U)
5898 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
5899 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
5900 #define DAC_CR_DMAUDRIE1_Pos        (13U)
5901 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
5902 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
5903 #define DAC_CR_CEN1_Pos             (14U)
5904 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
5905 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
5906 
5907 #define DAC_CR_EN2_Pos              (16U)
5908 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
5909 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
5910 #define DAC_CR_TEN2_Pos             (17U)
5911 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
5912 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
5913 
5914 #define DAC_CR_TSEL2_Pos            (18U)
5915 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
5916 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5917 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
5918 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5919 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5920 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5921 
5922 
5923 #define DAC_CR_WAVE2_Pos            (22U)
5924 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
5925 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5926 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5927 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5928 
5929 #define DAC_CR_MAMP2_Pos            (24U)
5930 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
5931 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5932 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5933 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5934 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5935 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5936 
5937 #define DAC_CR_DMAEN2_Pos           (28U)
5938 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
5939 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
5940 #define DAC_CR_DMAUDRIE2_Pos        (29U)
5941 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
5942 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
5943 #define DAC_CR_CEN2_Pos             (30U)
5944 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
5945 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
5946 
5947 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5948 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5949 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
5950 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5951 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5952 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
5953 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5954 
5955 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5956 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5957 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
5958 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5959 
5960 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5961 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5962 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
5963 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5964 
5965 /******************  Bit definition for DAC_DHR8R1 register  ******************/
5966 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5967 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
5968 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5969 
5970 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5971 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5972 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
5973 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5974 
5975 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5976 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5977 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
5978 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5979 
5980 /******************  Bit definition for DAC_DHR8R2 register  ******************/
5981 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5982 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
5983 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5984 
5985 /*****************  Bit definition for DAC_DHR12RD register  ******************/
5986 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5987 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
5988 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5989 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5990 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
5991 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5992 
5993 /*****************  Bit definition for DAC_DHR12LD register  ******************/
5994 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5995 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
5996 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5997 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5998 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
5999 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
6000 
6001 /******************  Bit definition for DAC_DHR8RD register  ******************/
6002 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
6003 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
6004 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
6005 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
6006 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
6007 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
6008 
6009 /*******************  Bit definition for DAC_DOR1 register  *******************/
6010 #define DAC_DOR1_DACC1DOR_Pos       (0U)
6011 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
6012 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
6013 
6014 /*******************  Bit definition for DAC_DOR2 register  *******************/
6015 #define DAC_DOR2_DACC2DOR_Pos       (0U)
6016 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
6017 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
6018 
6019 /********************  Bit definition for DAC_SR register  ********************/
6020 #define DAC_SR_DMAUDR1_Pos          (13U)
6021 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
6022 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
6023 #define DAC_SR_CAL_FLAG1_Pos        (14U)
6024 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
6025 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
6026 #define DAC_SR_BWST1_Pos            (15U)
6027 #define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
6028 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
6029 
6030 #define DAC_SR_DMAUDR2_Pos          (29U)
6031 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
6032 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
6033 #define DAC_SR_CAL_FLAG2_Pos        (30U)
6034 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
6035 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
6036 #define DAC_SR_BWST2_Pos            (31U)
6037 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
6038 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
6039 
6040 /*******************  Bit definition for DAC_CCR register  ********************/
6041 #define DAC_CCR_OTRIM1_Pos          (0U)
6042 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
6043 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
6044 #define DAC_CCR_OTRIM2_Pos          (16U)
6045 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
6046 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
6047 
6048 /*******************  Bit definition for DAC_MCR register  *******************/
6049 #define DAC_MCR_MODE1_Pos           (0U)
6050 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
6051 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
6052 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
6053 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
6054 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
6055 
6056 #define DAC_MCR_MODE2_Pos           (16U)
6057 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
6058 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
6059 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
6060 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
6061 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
6062 
6063 /******************  Bit definition for DAC_SHSR1 register  ******************/
6064 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
6065 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
6066 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
6067 
6068 /******************  Bit definition for DAC_SHSR2 register  ******************/
6069 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
6070 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
6071 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
6072 
6073 /******************  Bit definition for DAC_SHHR register  ******************/
6074 #define DAC_SHHR_THOLD1_Pos         (0U)
6075 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
6076 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
6077 #define DAC_SHHR_THOLD2_Pos         (16U)
6078 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
6079 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
6080 
6081 /******************  Bit definition for DAC_SHRR register  ******************/
6082 #define DAC_SHRR_TREFRESH1_Pos      (0U)
6083 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
6084 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
6085 #define DAC_SHRR_TREFRESH2_Pos      (16U)
6086 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
6087 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
6088 
6089 /******************************************************************************/
6090 /*                                                                            */
6091 /*                                    DCMI                                    */
6092 /*                                                                            */
6093 /******************************************************************************/
6094 /********************  Bits definition for DCMI_CR register  ******************/
6095 #define DCMI_CR_CAPTURE_Pos        (0U)
6096 #define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */
6097 #define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
6098 #define DCMI_CR_CM_Pos             (1U)
6099 #define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */
6100 #define DCMI_CR_CM                 DCMI_CR_CM_Msk
6101 #define DCMI_CR_CROP_Pos           (2U)
6102 #define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */
6103 #define DCMI_CR_CROP               DCMI_CR_CROP_Msk
6104 #define DCMI_CR_JPEG_Pos           (3U)
6105 #define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */
6106 #define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
6107 #define DCMI_CR_ESS_Pos            (4U)
6108 #define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */
6109 #define DCMI_CR_ESS                DCMI_CR_ESS_Msk
6110 #define DCMI_CR_PCKPOL_Pos         (5U)
6111 #define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */
6112 #define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
6113 #define DCMI_CR_HSPOL_Pos          (6U)
6114 #define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */
6115 #define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
6116 #define DCMI_CR_VSPOL_Pos          (7U)
6117 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
6118 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
6119 #define DCMI_CR_FCRC_0             (0x00000100U)
6120 #define DCMI_CR_FCRC_1             (0x00000200U)
6121 #define DCMI_CR_EDM_0              (0x00000400U)
6122 #define DCMI_CR_EDM_1              (0x00000800U)
6123 #define DCMI_CR_CRE_Pos            (12U)
6124 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
6125 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
6126 #define DCMI_CR_ENABLE_Pos         (14U)
6127 #define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */
6128 #define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
6129 #define DCMI_CR_BSM_Pos            (16U)
6130 #define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */
6131 #define DCMI_CR_BSM                DCMI_CR_BSM_Msk
6132 #define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
6133 #define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
6134 #define DCMI_CR_OEBS_Pos           (18U)
6135 #define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */
6136 #define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
6137 #define DCMI_CR_LSM_Pos            (19U)
6138 #define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */
6139 #define DCMI_CR_LSM                DCMI_CR_LSM_Msk
6140 #define DCMI_CR_OELS_Pos           (20U)
6141 #define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */
6142 #define DCMI_CR_OELS               DCMI_CR_OELS_Msk
6143 
6144 /********************  Bits definition for DCMI_SR register  ******************/
6145 #define DCMI_SR_HSYNC_Pos          (0U)
6146 #define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */
6147 #define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
6148 #define DCMI_SR_VSYNC_Pos          (1U)
6149 #define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */
6150 #define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
6151 #define DCMI_SR_FNE_Pos            (2U)
6152 #define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */
6153 #define DCMI_SR_FNE                DCMI_SR_FNE_Msk
6154 
6155 /********************  Bits definition for DCMI_RIS register   ****************/
6156 #define DCMI_RIS_FRAME_RIS_Pos     (0U)
6157 #define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */
6158 #define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
6159 #define DCMI_RIS_OVR_RIS_Pos       (1U)
6160 #define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */
6161 #define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
6162 #define DCMI_RIS_ERR_RIS_Pos       (2U)
6163 #define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */
6164 #define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
6165 #define DCMI_RIS_VSYNC_RIS_Pos     (3U)
6166 #define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */
6167 #define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
6168 #define DCMI_RIS_LINE_RIS_Pos      (4U)
6169 #define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */
6170 #define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
6171 
6172 /********************  Bits definition for DCMI_IER register  *****************/
6173 #define DCMI_IER_FRAME_IE_Pos      (0U)
6174 #define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */
6175 #define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
6176 #define DCMI_IER_OVR_IE_Pos        (1U)
6177 #define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */
6178 #define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
6179 #define DCMI_IER_ERR_IE_Pos        (2U)
6180 #define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */
6181 #define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
6182 #define DCMI_IER_VSYNC_IE_Pos      (3U)
6183 #define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */
6184 #define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
6185 #define DCMI_IER_LINE_IE_Pos       (4U)
6186 #define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */
6187 #define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
6188 
6189 
6190 /********************  Bits definition for DCMI_MIS register  *****************/
6191 #define DCMI_MIS_FRAME_MIS_Pos     (0U)
6192 #define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */
6193 #define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
6194 #define DCMI_MIS_OVR_MIS_Pos       (1U)
6195 #define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */
6196 #define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
6197 #define DCMI_MIS_ERR_MIS_Pos       (2U)
6198 #define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */
6199 #define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
6200 #define DCMI_MIS_VSYNC_MIS_Pos     (3U)
6201 #define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */
6202 #define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
6203 #define DCMI_MIS_LINE_MIS_Pos      (4U)
6204 #define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */
6205 #define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
6206 
6207 
6208 /********************  Bits definition for DCMI_ICR register  *****************/
6209 #define DCMI_ICR_FRAME_ISC_Pos     (0U)
6210 #define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */
6211 #define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
6212 #define DCMI_ICR_OVR_ISC_Pos       (1U)
6213 #define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */
6214 #define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
6215 #define DCMI_ICR_ERR_ISC_Pos       (2U)
6216 #define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */
6217 #define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
6218 #define DCMI_ICR_VSYNC_ISC_Pos     (3U)
6219 #define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */
6220 #define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
6221 #define DCMI_ICR_LINE_ISC_Pos      (4U)
6222 #define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */
6223 #define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
6224 
6225 
6226 /********************  Bits definition for DCMI_ESCR register  ******************/
6227 #define DCMI_ESCR_FSC_Pos          (0U)
6228 #define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */
6229 #define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
6230 #define DCMI_ESCR_LSC_Pos          (8U)
6231 #define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */
6232 #define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
6233 #define DCMI_ESCR_LEC_Pos          (16U)
6234 #define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */
6235 #define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
6236 #define DCMI_ESCR_FEC_Pos          (24U)
6237 #define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */
6238 #define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
6239 
6240 /********************  Bits definition for DCMI_ESUR register  ******************/
6241 #define DCMI_ESUR_FSU_Pos          (0U)
6242 #define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */
6243 #define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
6244 #define DCMI_ESUR_LSU_Pos          (8U)
6245 #define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */
6246 #define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
6247 #define DCMI_ESUR_LEU_Pos          (16U)
6248 #define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */
6249 #define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
6250 #define DCMI_ESUR_FEU_Pos          (24U)
6251 #define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */
6252 #define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
6253 
6254 /********************  Bits definition for DCMI_CWSTRT register  ******************/
6255 #define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
6256 #define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */
6257 #define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
6258 #define DCMI_CWSTRT_VST_Pos        (16U)
6259 #define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */
6260 #define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
6261 
6262 /********************  Bits definition for DCMI_CWSIZE register  ******************/
6263 #define DCMI_CWSIZE_CAPCNT_Pos     (0U)
6264 #define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */
6265 #define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
6266 #define DCMI_CWSIZE_VLINE_Pos      (16U)
6267 #define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */
6268 #define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
6269 
6270 /********************  Bits definition for DCMI_DR register  ******************/
6271 #define DCMI_DR_BYTE0_Pos          (0U)
6272 #define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */
6273 #define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
6274 #define DCMI_DR_BYTE1_Pos          (8U)
6275 #define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */
6276 #define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
6277 #define DCMI_DR_BYTE2_Pos          (16U)
6278 #define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */
6279 #define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
6280 #define DCMI_DR_BYTE3_Pos          (24U)
6281 #define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */
6282 #define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
6283 
6284 /******************************************************************************/
6285 /*                                                                            */
6286 /*                 Digital Filter for Sigma Delta Modulators                  */
6287 /*                                                                            */
6288 /******************************************************************************/
6289 
6290 /****************   DFSDM channel configuration registers  ********************/
6291 
6292 /***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
6293 #define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
6294 #define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */
6295 #define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
6296 #define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
6297 #define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */
6298 #define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
6299 #define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
6300 #define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6301 #define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
6302 #define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
6303 #define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */
6304 #define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
6305 #define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
6306 #define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
6307 #define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
6308 #define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */
6309 #define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
6310 #define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
6311 #define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
6312 #define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
6313 #define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */
6314 #define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
6315 #define DFSDM_CHCFGR1_CHEN_Pos          (7U)
6316 #define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */
6317 #define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
6318 #define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
6319 #define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */
6320 #define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
6321 #define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
6322 #define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */
6323 #define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
6324 #define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
6325 #define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */
6326 #define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
6327 #define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
6328 #define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
6329 #define DFSDM_CHCFGR1_SITP_Pos          (0U)
6330 #define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */
6331 #define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
6332 #define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
6333 #define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
6334 
6335 /***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
6336 #define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
6337 #define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6338 #define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6339 #define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
6340 #define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */
6341 #define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
6342 
6343 /******************  Bit definition for DFSDM_CHAWSCDR register *****************/
6344 #define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
6345 #define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */
6346 #define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6347 #define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
6348 #define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
6349 #define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
6350 #define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */
6351 #define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6352 #define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
6353 #define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */
6354 #define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6355 #define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
6356 #define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */
6357 #define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6358 
6359 /****************  Bit definition for DFSDM_CHWDATR register *******************/
6360 #define DFSDM_CHWDATR_WDATA_Pos         (0U)
6361 #define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */
6362 #define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
6363 
6364 /****************  Bit definition for DFSDM_CHDATINR register *****************/
6365 #define DFSDM_CHDATINR_INDAT0_Pos       (0U)
6366 #define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6367 #define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6368 #define DFSDM_CHDATINR_INDAT1_Pos       (16U)
6369 #define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6370 #define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
6371 
6372 /****************  Bit definition for DFSDM_CHDLYR register *****************/
6373 #define DFSDM_CHDLYR_PLSSKP_Pos         (0U)
6374 #define DFSDM_CHDLYR_PLSSKP_Msk         (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)    /*!< 0x0000003F*/
6375 #define DFSDM_CHDLYR_PLSSKP             DFSDM_CHDLYR_PLSSKP_Msk
6376 /************************   DFSDM module registers  ****************************/
6377 
6378 /********************  Bit definition for DFSDM_FLTCR1 register *******************/
6379 #define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
6380 #define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */
6381 #define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
6382 #define DFSDM_FLTCR1_FAST_Pos           (29U)
6383 #define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */
6384 #define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
6385 #define DFSDM_FLTCR1_RCH_Pos            (24U)
6386 #define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */
6387 #define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
6388 #define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
6389 #define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */
6390 #define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
6391 #define DFSDM_FLTCR1_RSYNC_Pos          (19U)
6392 #define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */
6393 #define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
6394 #define DFSDM_FLTCR1_RCONT_Pos          (18U)
6395 #define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */
6396 #define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
6397 #define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
6398 #define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */
6399 #define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
6400 #define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
6401 #define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */
6402 #define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6403 #define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
6404 #define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
6405 #define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
6406 #define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */
6407 #define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6408 #define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */
6409 #define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */
6410 #define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */
6411 #define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */
6412 #define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */
6413 
6414 #define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
6415 #define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */
6416 #define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
6417 #define DFSDM_FLTCR1_JSCAN_Pos          (4U)
6418 #define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */
6419 #define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
6420 #define DFSDM_FLTCR1_JSYNC_Pos          (3U)
6421 #define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */
6422 #define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
6423 #define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
6424 #define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */
6425 #define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
6426 #define DFSDM_FLTCR1_DFEN_Pos           (0U)
6427 #define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */
6428 #define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
6429 
6430 /********************  Bit definition for DFSDM_FLTCR2 register *******************/
6431 #define DFSDM_FLTCR2_AWDCH_Pos          (16U)
6432 #define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */
6433 #define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
6434 #define DFSDM_FLTCR2_EXCH_Pos           (8U)
6435 #define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */
6436 #define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
6437 #define DFSDM_FLTCR2_CKABIE_Pos         (6U)
6438 #define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */
6439 #define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
6440 #define DFSDM_FLTCR2_SCDIE_Pos          (5U)
6441 #define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */
6442 #define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
6443 #define DFSDM_FLTCR2_AWDIE_Pos          (4U)
6444 #define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */
6445 #define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
6446 #define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
6447 #define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */
6448 #define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
6449 #define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
6450 #define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */
6451 #define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
6452 #define DFSDM_FLTCR2_REOCIE_Pos         (1U)
6453 #define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */
6454 #define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
6455 #define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
6456 #define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */
6457 #define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
6458 
6459 /********************  Bit definition for DFSDM_FLTISR register *******************/
6460 #define DFSDM_FLTISR_SCDF_Pos           (24U)
6461 #define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */
6462 #define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
6463 #define DFSDM_FLTISR_CKABF_Pos          (16U)
6464 #define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */
6465 #define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
6466 #define DFSDM_FLTISR_RCIP_Pos           (14U)
6467 #define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */
6468 #define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
6469 #define DFSDM_FLTISR_JCIP_Pos           (13U)
6470 #define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */
6471 #define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
6472 #define DFSDM_FLTISR_AWDF_Pos           (4U)
6473 #define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */
6474 #define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
6475 #define DFSDM_FLTISR_ROVRF_Pos          (3U)
6476 #define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */
6477 #define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
6478 #define DFSDM_FLTISR_JOVRF_Pos          (2U)
6479 #define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */
6480 #define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
6481 #define DFSDM_FLTISR_REOCF_Pos          (1U)
6482 #define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */
6483 #define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
6484 #define DFSDM_FLTISR_JEOCF_Pos          (0U)
6485 #define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */
6486 #define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
6487 
6488 /********************  Bit definition for DFSDM_FLTICR register *******************/
6489 #define DFSDM_FLTICR_CLRSCDF_Pos        (24U)
6490 #define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */
6491 #define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6492 #define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
6493 #define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */
6494 #define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
6495 #define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
6496 #define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */
6497 #define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
6498 #define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
6499 #define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */
6500 #define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
6501 
6502 /*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
6503 #define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
6504 #define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */
6505 #define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
6506 
6507 /********************  Bit definition for DFSDM_FLTFCR register *******************/
6508 #define DFSDM_FLTFCR_FORD_Pos           (29U)
6509 #define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */
6510 #define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
6511 #define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
6512 #define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
6513 #define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
6514 #define DFSDM_FLTFCR_FOSR_Pos           (16U)
6515 #define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */
6516 #define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6517 #define DFSDM_FLTFCR_IOSR_Pos           (0U)
6518 #define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */
6519 #define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6520 
6521 /******************  Bit definition for DFSDM_FLTJDATAR register *****************/
6522 #define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
6523 #define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6524 #define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
6525 #define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
6526 #define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6527 #define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
6528 
6529 /******************  Bit definition for DFSDM_FLTRDATAR register *****************/
6530 #define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
6531 #define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6532 #define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
6533 #define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
6534 #define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */
6535 #define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
6536 #define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
6537 #define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6538 #define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
6539 
6540 /******************  Bit definition for DFSDM_FLTAWHTR register ******************/
6541 #define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
6542 #define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6543 #define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
6544 #define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
6545 #define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */
6546 #define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6547 
6548 /******************  Bit definition for DFSDM_FLTAWLTR register ******************/
6549 #define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
6550 #define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6551 #define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */
6552 #define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
6553 #define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */
6554 #define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6555 
6556 /******************  Bit definition for DFSDM_FLTAWSR register ******************/
6557 #define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
6558 #define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */
6559 #define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6560 #define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
6561 #define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */
6562 #define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6563 
6564 /******************  Bit definition for DFSDM_FLTAWCFR) register *****************/
6565 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
6566 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6567 #define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6568 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
6569 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6570 #define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6571 
6572 /******************  Bit definition for DFSDM_FLTEXMAX register ******************/
6573 #define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
6574 #define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6575 #define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
6576 #define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
6577 #define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */
6578 #define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6579 
6580 /******************  Bit definition for DFSDM_FLTEXMIN register ******************/
6581 #define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
6582 #define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6583 #define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
6584 #define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
6585 #define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */
6586 #define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6587 
6588 /******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
6589 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
6590 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6591 #define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6592 
6593 /******************************************************************************/
6594 /*                                                                            */
6595 /*                           BDMA Controller                                  */
6596 /*                                                                            */
6597 /******************************************************************************/
6598 
6599 /*******************  Bit definition for BDMA_ISR register  ********************/
6600 #define BDMA_ISR_GIF0_Pos       (0U)
6601 #define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */
6602 #define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */
6603 #define BDMA_ISR_TCIF0_Pos      (1U)
6604 #define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */
6605 #define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */
6606 #define BDMA_ISR_HTIF0_Pos      (2U)
6607 #define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */
6608 #define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */
6609 #define BDMA_ISR_TEIF0_Pos      (3U)
6610 #define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */
6611 #define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */
6612 #define BDMA_ISR_GIF1_Pos       (4U)
6613 #define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */
6614 #define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */
6615 #define BDMA_ISR_TCIF1_Pos      (5U)
6616 #define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */
6617 #define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */
6618 #define BDMA_ISR_HTIF1_Pos      (6U)
6619 #define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */
6620 #define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */
6621 #define BDMA_ISR_TEIF1_Pos      (7U)
6622 #define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */
6623 #define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */
6624 #define BDMA_ISR_GIF2_Pos       (8U)
6625 #define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */
6626 #define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */
6627 #define BDMA_ISR_TCIF2_Pos      (9U)
6628 #define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */
6629 #define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */
6630 #define BDMA_ISR_HTIF2_Pos      (10U)
6631 #define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */
6632 #define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */
6633 #define BDMA_ISR_TEIF2_Pos      (11U)
6634 #define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */
6635 #define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */
6636 #define BDMA_ISR_GIF3_Pos       (12U)
6637 #define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */
6638 #define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */
6639 #define BDMA_ISR_TCIF3_Pos      (13U)
6640 #define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */
6641 #define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */
6642 #define BDMA_ISR_HTIF3_Pos      (14U)
6643 #define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */
6644 #define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */
6645 #define BDMA_ISR_TEIF3_Pos      (15U)
6646 #define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */
6647 #define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */
6648 #define BDMA_ISR_GIF4_Pos       (16U)
6649 #define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */
6650 #define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */
6651 #define BDMA_ISR_TCIF4_Pos      (17U)
6652 #define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */
6653 #define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */
6654 #define BDMA_ISR_HTIF4_Pos      (18U)
6655 #define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */
6656 #define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */
6657 #define BDMA_ISR_TEIF4_Pos      (19U)
6658 #define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */
6659 #define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */
6660 #define BDMA_ISR_GIF5_Pos       (20U)
6661 #define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */
6662 #define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */
6663 #define BDMA_ISR_TCIF5_Pos      (21U)
6664 #define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */
6665 #define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */
6666 #define BDMA_ISR_HTIF5_Pos      (22U)
6667 #define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */
6668 #define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */
6669 #define BDMA_ISR_TEIF5_Pos      (23U)
6670 #define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */
6671 #define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */
6672 #define BDMA_ISR_GIF6_Pos       (24U)
6673 #define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */
6674 #define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */
6675 #define BDMA_ISR_TCIF6_Pos      (25U)
6676 #define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */
6677 #define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */
6678 #define BDMA_ISR_HTIF6_Pos      (26U)
6679 #define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */
6680 #define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */
6681 #define BDMA_ISR_TEIF6_Pos      (27U)
6682 #define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */
6683 #define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */
6684 #define BDMA_ISR_GIF7_Pos       (28U)
6685 #define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */
6686 #define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */
6687 #define BDMA_ISR_TCIF7_Pos      (29U)
6688 #define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */
6689 #define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */
6690 #define BDMA_ISR_HTIF7_Pos      (30U)
6691 #define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */
6692 #define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */
6693 #define BDMA_ISR_TEIF7_Pos      (31U)
6694 #define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */
6695 #define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */
6696 
6697 /*******************  Bit definition for BDMA_IFCR register  *******************/
6698 #define BDMA_IFCR_CGIF0_Pos     (0U)
6699 #define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */
6700 #define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */
6701 #define BDMA_IFCR_CTCIF0_Pos    (1U)
6702 #define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */
6703 #define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */
6704 #define BDMA_IFCR_CHTIF0_Pos    (2U)
6705 #define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */
6706 #define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */
6707 #define BDMA_IFCR_CTEIF0_Pos    (3U)
6708 #define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */
6709 #define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */
6710 #define BDMA_IFCR_CGIF1_Pos     (4U)
6711 #define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */
6712 #define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */
6713 #define BDMA_IFCR_CTCIF1_Pos    (5U)
6714 #define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */
6715 #define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */
6716 #define BDMA_IFCR_CHTIF1_Pos    (6U)
6717 #define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */
6718 #define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */
6719 #define BDMA_IFCR_CTEIF1_Pos    (7U)
6720 #define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */
6721 #define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */
6722 #define BDMA_IFCR_CGIF2_Pos     (8U)
6723 #define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */
6724 #define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */
6725 #define BDMA_IFCR_CTCIF2_Pos    (9U)
6726 #define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */
6727 #define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */
6728 #define BDMA_IFCR_CHTIF2_Pos    (10U)
6729 #define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */
6730 #define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */
6731 #define BDMA_IFCR_CTEIF2_Pos    (11U)
6732 #define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */
6733 #define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */
6734 #define BDMA_IFCR_CGIF3_Pos     (12U)
6735 #define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */
6736 #define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */
6737 #define BDMA_IFCR_CTCIF3_Pos    (13U)
6738 #define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */
6739 #define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */
6740 #define BDMA_IFCR_CHTIF3_Pos    (14U)
6741 #define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */
6742 #define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */
6743 #define BDMA_IFCR_CTEIF3_Pos    (15U)
6744 #define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */
6745 #define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */
6746 #define BDMA_IFCR_CGIF4_Pos     (16U)
6747 #define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */
6748 #define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */
6749 #define BDMA_IFCR_CTCIF4_Pos    (17U)
6750 #define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */
6751 #define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */
6752 #define BDMA_IFCR_CHTIF4_Pos    (18U)
6753 #define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */
6754 #define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */
6755 #define BDMA_IFCR_CTEIF4_Pos    (19U)
6756 #define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */
6757 #define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */
6758 #define BDMA_IFCR_CGIF5_Pos     (20U)
6759 #define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */
6760 #define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */
6761 #define BDMA_IFCR_CTCIF5_Pos    (21U)
6762 #define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */
6763 #define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */
6764 #define BDMA_IFCR_CHTIF5_Pos    (22U)
6765 #define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */
6766 #define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */
6767 #define BDMA_IFCR_CTEIF5_Pos    (23U)
6768 #define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */
6769 #define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */
6770 #define BDMA_IFCR_CGIF6_Pos     (24U)
6771 #define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */
6772 #define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */
6773 #define BDMA_IFCR_CTCIF6_Pos    (25U)
6774 #define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */
6775 #define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */
6776 #define BDMA_IFCR_CHTIF6_Pos    (26U)
6777 #define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */
6778 #define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */
6779 #define BDMA_IFCR_CTEIF6_Pos    (27U)
6780 #define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */
6781 #define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */
6782 #define BDMA_IFCR_CGIF7_Pos     (28U)
6783 #define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */
6784 #define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */
6785 #define BDMA_IFCR_CTCIF7_Pos    (29U)
6786 #define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */
6787 #define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */
6788 #define BDMA_IFCR_CHTIF7_Pos    (30U)
6789 #define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */
6790 #define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */
6791 #define BDMA_IFCR_CTEIF7_Pos    (31U)
6792 #define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */
6793 #define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */
6794 
6795 /*******************  Bit definition for BDMA_CCR register  ********************/
6796 #define BDMA_CCR_EN_Pos         (0U)
6797 #define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */
6798 #define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */
6799 #define BDMA_CCR_TCIE_Pos       (1U)
6800 #define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */
6801 #define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */
6802 #define BDMA_CCR_HTIE_Pos       (2U)
6803 #define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */
6804 #define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */
6805 #define BDMA_CCR_TEIE_Pos       (3U)
6806 #define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */
6807 #define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */
6808 #define BDMA_CCR_DIR_Pos        (4U)
6809 #define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */
6810 #define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */
6811 #define BDMA_CCR_CIRC_Pos       (5U)
6812 #define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */
6813 #define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */
6814 #define BDMA_CCR_PINC_Pos       (6U)
6815 #define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */
6816 #define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */
6817 #define BDMA_CCR_MINC_Pos       (7U)
6818 #define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */
6819 #define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */
6820 
6821 #define BDMA_CCR_PSIZE_Pos      (8U)
6822 #define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */
6823 #define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */
6824 #define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */
6825 #define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */
6826 
6827 #define BDMA_CCR_MSIZE_Pos      (10U)
6828 #define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */
6829 #define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */
6830 #define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */
6831 #define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */
6832 
6833 #define BDMA_CCR_PL_Pos         (12U)
6834 #define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */
6835 #define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/
6836 #define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */
6837 #define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */
6838 
6839 #define BDMA_CCR_MEM2MEM_Pos    (14U)
6840 #define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */
6841 #define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */
6842 #define BDMA_CCR_DBM_Pos        (15U)
6843 #define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */
6844 #define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */
6845 #define BDMA_CCR_CT_Pos         (16U)
6846 #define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */
6847 #define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */
6848 
6849 /******************  Bit definition for BDMA_CNDTR register  *******************/
6850 #define BDMA_CNDTR_NDT_Pos      (0U)
6851 #define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */
6852 #define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */
6853 
6854 /******************  Bit definition for BDMA_CPAR register  ********************/
6855 #define BDMA_CPAR_PA_Pos        (0U)
6856 #define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */
6857 #define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */
6858 
6859 /******************  Bit definition for BDMA_CM0AR register  ********************/
6860 #define BDMA_CM0AR_MA_Pos        (0U)
6861 #define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */
6862 #define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */
6863 
6864 /******************  Bit definition for BDMA_CM1AR register  ********************/
6865 #define BDMA_CM1AR_MA_Pos        (0U)
6866 #define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */
6867 #define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */
6868 
6869 /******************************************************************************/
6870 /*                                                                            */
6871 /*                             DMA Controller                                 */
6872 /*                                                                            */
6873 /******************************************************************************/
6874 /********************  Bits definition for DMA_SxCR register  *****************/
6875 #define DMA_SxCR_MBURST_Pos      (23U)
6876 #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */
6877 #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */
6878 #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
6879 #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
6880 #define DMA_SxCR_PBURST_Pos      (21U)
6881 #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */
6882 #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */
6883 #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
6884 #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
6885 #define DMA_SxCR_TRBUFF_Pos      (20U)
6886 #define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */
6887 #define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */
6888 #define DMA_SxCR_CT_Pos          (19U)
6889 #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */
6890 #define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */
6891 #define DMA_SxCR_DBM_Pos         (18U)
6892 #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */
6893 #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */
6894 #define DMA_SxCR_PL_Pos          (16U)
6895 #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */
6896 #define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */
6897 #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
6898 #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
6899 #define DMA_SxCR_PINCOS_Pos      (15U)
6900 #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */
6901 #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */
6902 #define DMA_SxCR_MSIZE_Pos       (13U)
6903 #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */
6904 #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */
6905 #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
6906 #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
6907 #define DMA_SxCR_PSIZE_Pos       (11U)
6908 #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */
6909 #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */
6910 #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
6911 #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
6912 #define DMA_SxCR_MINC_Pos        (10U)
6913 #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */
6914 #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */
6915 #define DMA_SxCR_PINC_Pos        (9U)
6916 #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */
6917 #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */
6918 #define DMA_SxCR_CIRC_Pos        (8U)
6919 #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */
6920 #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */
6921 #define DMA_SxCR_DIR_Pos         (6U)
6922 #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */
6923 #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */
6924 #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
6925 #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
6926 #define DMA_SxCR_PFCTRL_Pos      (5U)
6927 #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */
6928 #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */
6929 #define DMA_SxCR_TCIE_Pos        (4U)
6930 #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */
6931 #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */
6932 #define DMA_SxCR_HTIE_Pos        (3U)
6933 #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */
6934 #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */
6935 #define DMA_SxCR_TEIE_Pos        (2U)
6936 #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */
6937 #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */
6938 #define DMA_SxCR_DMEIE_Pos       (1U)
6939 #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */
6940 #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */
6941 #define DMA_SxCR_EN_Pos          (0U)
6942 #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */
6943 #define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */
6944 
6945 /********************  Bits definition for DMA_SxCNDTR register  **************/
6946 #define DMA_SxNDT_Pos            (0U)
6947 #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */
6948 #define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */
6949 #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
6950 #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
6951 #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
6952 #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
6953 #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
6954 #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
6955 #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
6956 #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
6957 #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
6958 #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
6959 #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
6960 #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
6961 #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
6962 #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
6963 #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
6964 #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
6965 
6966 /********************  Bits definition for DMA_SxFCR register  ****************/
6967 #define DMA_SxFCR_FEIE_Pos       (7U)
6968 #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */
6969 #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */
6970 #define DMA_SxFCR_FS_Pos         (3U)
6971 #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */
6972 #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */
6973 #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
6974 #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
6975 #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
6976 #define DMA_SxFCR_DMDIS_Pos      (2U)
6977 #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */
6978 #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */
6979 #define DMA_SxFCR_FTH_Pos        (0U)
6980 #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */
6981 #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */
6982 #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
6983 #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
6984 
6985 /********************  Bits definition for DMA_LISR register  *****************/
6986 #define DMA_LISR_TCIF3_Pos       (27U)
6987 #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */
6988 #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */
6989 #define DMA_LISR_HTIF3_Pos       (26U)
6990 #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */
6991 #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */
6992 #define DMA_LISR_TEIF3_Pos       (25U)
6993 #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */
6994 #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */
6995 #define DMA_LISR_DMEIF3_Pos      (24U)
6996 #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */
6997 #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */
6998 #define DMA_LISR_FEIF3_Pos       (22U)
6999 #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */
7000 #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */
7001 #define DMA_LISR_TCIF2_Pos       (21U)
7002 #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */
7003 #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */
7004 #define DMA_LISR_HTIF2_Pos       (20U)
7005 #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */
7006 #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */
7007 #define DMA_LISR_TEIF2_Pos       (19U)
7008 #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */
7009 #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */
7010 #define DMA_LISR_DMEIF2_Pos      (18U)
7011 #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */
7012 #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */
7013 #define DMA_LISR_FEIF2_Pos       (16U)
7014 #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */
7015 #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */
7016 #define DMA_LISR_TCIF1_Pos       (11U)
7017 #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */
7018 #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */
7019 #define DMA_LISR_HTIF1_Pos       (10U)
7020 #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */
7021 #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */
7022 #define DMA_LISR_TEIF1_Pos       (9U)
7023 #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */
7024 #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */
7025 #define DMA_LISR_DMEIF1_Pos      (8U)
7026 #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */
7027 #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */
7028 #define DMA_LISR_FEIF1_Pos       (6U)
7029 #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */
7030 #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */
7031 #define DMA_LISR_TCIF0_Pos       (5U)
7032 #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */
7033 #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */
7034 #define DMA_LISR_HTIF0_Pos       (4U)
7035 #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */
7036 #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */
7037 #define DMA_LISR_TEIF0_Pos       (3U)
7038 #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */
7039 #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */
7040 #define DMA_LISR_DMEIF0_Pos      (2U)
7041 #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */
7042 #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */
7043 #define DMA_LISR_FEIF0_Pos       (0U)
7044 #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */
7045 #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */
7046 
7047 /********************  Bits definition for DMA_HISR register  *****************/
7048 #define DMA_HISR_TCIF7_Pos       (27U)
7049 #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */
7050 #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */
7051 #define DMA_HISR_HTIF7_Pos       (26U)
7052 #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */
7053 #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */
7054 #define DMA_HISR_TEIF7_Pos       (25U)
7055 #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */
7056 #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */
7057 #define DMA_HISR_DMEIF7_Pos      (24U)
7058 #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */
7059 #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */
7060 #define DMA_HISR_FEIF7_Pos       (22U)
7061 #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */
7062 #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */
7063 #define DMA_HISR_TCIF6_Pos       (21U)
7064 #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */
7065 #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */
7066 #define DMA_HISR_HTIF6_Pos       (20U)
7067 #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */
7068 #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */
7069 #define DMA_HISR_TEIF6_Pos       (19U)
7070 #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */
7071 #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */
7072 #define DMA_HISR_DMEIF6_Pos      (18U)
7073 #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */
7074 #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */
7075 #define DMA_HISR_FEIF6_Pos       (16U)
7076 #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */
7077 #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */
7078 #define DMA_HISR_TCIF5_Pos       (11U)
7079 #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */
7080 #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */
7081 #define DMA_HISR_HTIF5_Pos       (10U)
7082 #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */
7083 #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */
7084 #define DMA_HISR_TEIF5_Pos       (9U)
7085 #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */
7086 #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */
7087 #define DMA_HISR_DMEIF5_Pos      (8U)
7088 #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */
7089 #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */
7090 #define DMA_HISR_FEIF5_Pos       (6U)
7091 #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */
7092 #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */
7093 #define DMA_HISR_TCIF4_Pos       (5U)
7094 #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */
7095 #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */
7096 #define DMA_HISR_HTIF4_Pos       (4U)
7097 #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */
7098 #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */
7099 #define DMA_HISR_TEIF4_Pos       (3U)
7100 #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */
7101 #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */
7102 #define DMA_HISR_DMEIF4_Pos      (2U)
7103 #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */
7104 #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */
7105 #define DMA_HISR_FEIF4_Pos       (0U)
7106 #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */
7107 #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */
7108 
7109 /********************  Bits definition for DMA_LIFCR register  ****************/
7110 #define DMA_LIFCR_CTCIF3_Pos     (27U)
7111 #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */
7112 #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */
7113 #define DMA_LIFCR_CHTIF3_Pos     (26U)
7114 #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */
7115 #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */
7116 #define DMA_LIFCR_CTEIF3_Pos     (25U)
7117 #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */
7118 #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */
7119 #define DMA_LIFCR_CDMEIF3_Pos    (24U)
7120 #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */
7121 #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */
7122 #define DMA_LIFCR_CFEIF3_Pos     (22U)
7123 #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */
7124 #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */
7125 #define DMA_LIFCR_CTCIF2_Pos     (21U)
7126 #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */
7127 #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */
7128 #define DMA_LIFCR_CHTIF2_Pos     (20U)
7129 #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */
7130 #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */
7131 #define DMA_LIFCR_CTEIF2_Pos     (19U)
7132 #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */
7133 #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */
7134 #define DMA_LIFCR_CDMEIF2_Pos    (18U)
7135 #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */
7136 #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */
7137 #define DMA_LIFCR_CFEIF2_Pos     (16U)
7138 #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */
7139 #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */
7140 #define DMA_LIFCR_CTCIF1_Pos     (11U)
7141 #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */
7142 #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */
7143 #define DMA_LIFCR_CHTIF1_Pos     (10U)
7144 #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */
7145 #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */
7146 #define DMA_LIFCR_CTEIF1_Pos     (9U)
7147 #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */
7148 #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */
7149 #define DMA_LIFCR_CDMEIF1_Pos    (8U)
7150 #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */
7151 #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */
7152 #define DMA_LIFCR_CFEIF1_Pos     (6U)
7153 #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */
7154 #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */
7155 #define DMA_LIFCR_CTCIF0_Pos     (5U)
7156 #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */
7157 #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */
7158 #define DMA_LIFCR_CHTIF0_Pos     (4U)
7159 #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */
7160 #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */
7161 #define DMA_LIFCR_CTEIF0_Pos     (3U)
7162 #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */
7163 #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */
7164 #define DMA_LIFCR_CDMEIF0_Pos    (2U)
7165 #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */
7166 #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */
7167 #define DMA_LIFCR_CFEIF0_Pos     (0U)
7168 #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */
7169 #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */
7170 
7171 /********************  Bits definition for DMA_HIFCR  register  ****************/
7172 #define DMA_HIFCR_CTCIF7_Pos     (27U)
7173 #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */
7174 #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */
7175 #define DMA_HIFCR_CHTIF7_Pos     (26U)
7176 #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */
7177 #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */
7178 #define DMA_HIFCR_CTEIF7_Pos     (25U)
7179 #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */
7180 #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */
7181 #define DMA_HIFCR_CDMEIF7_Pos    (24U)
7182 #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */
7183 #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */
7184 #define DMA_HIFCR_CFEIF7_Pos     (22U)
7185 #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */
7186 #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */
7187 #define DMA_HIFCR_CTCIF6_Pos     (21U)
7188 #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */
7189 #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */
7190 #define DMA_HIFCR_CHTIF6_Pos     (20U)
7191 #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */
7192 #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */
7193 #define DMA_HIFCR_CTEIF6_Pos     (19U)
7194 #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */
7195 #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */
7196 #define DMA_HIFCR_CDMEIF6_Pos    (18U)
7197 #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */
7198 #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */
7199 #define DMA_HIFCR_CFEIF6_Pos     (16U)
7200 #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */
7201 #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */
7202 #define DMA_HIFCR_CTCIF5_Pos     (11U)
7203 #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */
7204 #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */
7205 #define DMA_HIFCR_CHTIF5_Pos     (10U)
7206 #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */
7207 #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */
7208 #define DMA_HIFCR_CTEIF5_Pos     (9U)
7209 #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */
7210 #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */
7211 #define DMA_HIFCR_CDMEIF5_Pos    (8U)
7212 #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */
7213 #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */
7214 #define DMA_HIFCR_CFEIF5_Pos     (6U)
7215 #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */
7216 #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */
7217 #define DMA_HIFCR_CTCIF4_Pos     (5U)
7218 #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */
7219 #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */
7220 #define DMA_HIFCR_CHTIF4_Pos     (4U)
7221 #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */
7222 #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */
7223 #define DMA_HIFCR_CTEIF4_Pos     (3U)
7224 #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */
7225 #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */
7226 #define DMA_HIFCR_CDMEIF4_Pos    (2U)
7227 #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */
7228 #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */
7229 #define DMA_HIFCR_CFEIF4_Pos     (0U)
7230 #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */
7231 #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */
7232 
7233 /******************  Bit definition for DMA_SxPAR register  ********************/
7234 #define DMA_SxPAR_PA_Pos         (0U)
7235 #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */
7236 #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
7237 
7238 /******************  Bit definition for DMA_SxM0AR register  ********************/
7239 #define DMA_SxM0AR_M0A_Pos       (0U)
7240 #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */
7241 #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */
7242 
7243 /******************  Bit definition for DMA_SxM1AR register  ********************/
7244 #define DMA_SxM1AR_M1A_Pos       (0U)
7245 #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */
7246 #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */
7247 
7248 /******************************************************************************/
7249 /*                                                                            */
7250 /*                             DMAMUX Controller                              */
7251 /*                                                                            */
7252 /******************************************************************************/
7253 /********************  Bits definition for DMAMUX_CxCR register  **************/
7254 #define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)
7255 #define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */
7256 #define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */
7257 #define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */
7258 #define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */
7259 #define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */
7260 #define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */
7261 #define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */
7262 #define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */
7263 #define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */
7264 #define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */
7265 #define DMAMUX_CxCR_SOIE_Pos           (8U)
7266 #define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */
7267 #define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */
7268 #define DMAMUX_CxCR_EGE_Pos            (9U)
7269 #define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */
7270 #define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */
7271 #define DMAMUX_CxCR_SE_Pos             (16U)
7272 #define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */
7273 #define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */
7274 #define DMAMUX_CxCR_SPOL_Pos           (17U)
7275 #define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */
7276 #define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */
7277 #define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */
7278 #define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */
7279 #define DMAMUX_CxCR_NBREQ_Pos          (19U)
7280 #define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */
7281 #define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */
7282 #define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */
7283 #define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */
7284 #define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */
7285 #define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */
7286 #define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */
7287 #define DMAMUX_CxCR_SYNC_ID_Pos        (24U)
7288 #define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */
7289 #define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */
7290 #define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */
7291 #define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */
7292 #define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */
7293 #define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */
7294 #define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */
7295 
7296 /********************  Bits definition for DMAMUX_CSR register  **************/
7297 #define DMAMUX_CSR_SOF0_Pos            (0U)
7298 #define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */
7299 #define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */
7300 #define DMAMUX_CSR_SOF1_Pos            (1U)
7301 #define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */
7302 #define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */
7303 #define DMAMUX_CSR_SOF2_Pos            (2U)
7304 #define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */
7305 #define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */
7306 #define DMAMUX_CSR_SOF3_Pos            (3U)
7307 #define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */
7308 #define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */
7309 #define DMAMUX_CSR_SOF4_Pos            (4U)
7310 #define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */
7311 #define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */
7312 #define DMAMUX_CSR_SOF5_Pos            (5U)
7313 #define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */
7314 #define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */
7315 #define DMAMUX_CSR_SOF6_Pos            (6U)
7316 #define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */
7317 #define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */
7318 #define DMAMUX_CSR_SOF7_Pos            (7U)
7319 #define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */
7320 #define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */
7321 #define DMAMUX_CSR_SOF8_Pos            (8U)
7322 #define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */
7323 #define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */
7324 #define DMAMUX_CSR_SOF9_Pos            (9U)
7325 #define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */
7326 #define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */
7327 #define DMAMUX_CSR_SOF10_Pos           (10U)
7328 #define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */
7329 #define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */
7330 #define DMAMUX_CSR_SOF11_Pos           (11U)
7331 #define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */
7332 #define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */
7333 #define DMAMUX_CSR_SOF12_Pos           (12U)
7334 #define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */
7335 #define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */
7336 #define DMAMUX_CSR_SOF13_Pos           (13U)
7337 #define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */
7338 #define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */
7339 #define DMAMUX_CSR_SOF14_Pos           (14U)
7340 #define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */
7341 #define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */
7342 #define DMAMUX_CSR_SOF15_Pos           (15U)
7343 #define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */
7344 #define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */
7345 
7346 /********************  Bits definition for DMAMUX_CFR register  **************/
7347 #define DMAMUX_CFR_CSOF0_Pos           (0U)
7348 #define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */
7349 #define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */
7350 #define DMAMUX_CFR_CSOF1_Pos           (1U)
7351 #define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */
7352 #define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */
7353 #define DMAMUX_CFR_CSOF2_Pos           (2U)
7354 #define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */
7355 #define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */
7356 #define DMAMUX_CFR_CSOF3_Pos           (3U)
7357 #define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */
7358 #define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */
7359 #define DMAMUX_CFR_CSOF4_Pos           (4U)
7360 #define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */
7361 #define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */
7362 #define DMAMUX_CFR_CSOF5_Pos           (5U)
7363 #define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */
7364 #define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */
7365 #define DMAMUX_CFR_CSOF6_Pos           (6U)
7366 #define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */
7367 #define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */
7368 #define DMAMUX_CFR_CSOF7_Pos           (7U)
7369 #define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */
7370 #define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */
7371 #define DMAMUX_CFR_CSOF8_Pos           (8U)
7372 #define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */
7373 #define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */
7374 #define DMAMUX_CFR_CSOF9_Pos           (9U)
7375 #define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */
7376 #define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */
7377 #define DMAMUX_CFR_CSOF10_Pos          (10U)
7378 #define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */
7379 #define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */
7380 #define DMAMUX_CFR_CSOF11_Pos          (11U)
7381 #define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */
7382 #define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */
7383 #define DMAMUX_CFR_CSOF12_Pos          (12U)
7384 #define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */
7385 #define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */
7386 #define DMAMUX_CFR_CSOF13_Pos          (13U)
7387 #define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */
7388 #define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */
7389 #define DMAMUX_CFR_CSOF14_Pos          (14U)
7390 #define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */
7391 #define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */
7392 #define DMAMUX_CFR_CSOF15_Pos          (15U)
7393 #define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */
7394 #define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */
7395 
7396 /********************  Bits definition for DMAMUX_RGxCR register  ************/
7397 #define DMAMUX_RGxCR_SIG_ID_Pos        (0U)
7398 #define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */
7399 #define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */
7400 #define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */
7401 #define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */
7402 #define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */
7403 #define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */
7404 #define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */
7405 #define DMAMUX_RGxCR_OIE_Pos           (8U)
7406 #define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */
7407 #define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */
7408 #define DMAMUX_RGxCR_GE_Pos            (16U)
7409 #define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */
7410 #define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */
7411 #define DMAMUX_RGxCR_GPOL_Pos          (17U)
7412 #define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */
7413 #define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */
7414 #define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */
7415 #define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */
7416 #define DMAMUX_RGxCR_GNBREQ_Pos        (19U)
7417 #define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */
7418 #define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */
7419 #define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */
7420 #define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */
7421 #define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */
7422 #define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */
7423 #define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */
7424 
7425 /********************  Bits definition for DMAMUX_RGSR register  **************/
7426 #define DMAMUX_RGSR_OF0_Pos            (0U)
7427 #define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */
7428 #define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */
7429 #define DMAMUX_RGSR_OF1_Pos            (1U)
7430 #define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */
7431 #define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */
7432 #define DMAMUX_RGSR_OF2_Pos            (2U)
7433 #define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */
7434 #define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */
7435 #define DMAMUX_RGSR_OF3_Pos            (3U)
7436 #define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */
7437 #define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */
7438 #define DMAMUX_RGSR_OF4_Pos            (4U)
7439 #define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */
7440 #define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */
7441 #define DMAMUX_RGSR_OF5_Pos            (5U)
7442 #define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */
7443 #define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */
7444 #define DMAMUX_RGSR_OF6_Pos            (6U)
7445 #define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */
7446 #define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */
7447 #define DMAMUX_RGSR_OF7_Pos            (7U)
7448 #define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */
7449 #define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */
7450 
7451 /********************  Bits definition for DMAMUX_RGCFR register  **************/
7452 #define DMAMUX_RGCFR_COF0_Pos          (0U)
7453 #define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */
7454 #define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */
7455 #define DMAMUX_RGCFR_COF1_Pos          (1U)
7456 #define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */
7457 #define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */
7458 #define DMAMUX_RGCFR_COF2_Pos          (2U)
7459 #define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */
7460 #define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */
7461 #define DMAMUX_RGCFR_COF3_Pos          (3U)
7462 #define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */
7463 #define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */
7464 #define DMAMUX_RGCFR_COF4_Pos          (4U)
7465 #define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */
7466 #define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */
7467 #define DMAMUX_RGCFR_COF5_Pos          (5U)
7468 #define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */
7469 #define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */
7470 #define DMAMUX_RGCFR_COF6_Pos          (6U)
7471 #define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */
7472 #define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */
7473 #define DMAMUX_RGCFR_COF7_Pos          (7U)
7474 #define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */
7475 #define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */
7476 
7477 /******************************************************************************/
7478 /*                                                                            */
7479 /*                         AHB Master DMA2D Controller (DMA2D)                */
7480 /*                                                                            */
7481 /******************************************************************************/
7482 
7483 /********************  Bit definition for DMA2D_CR register  ******************/
7484 
7485 #define DMA2D_CR_START_Pos         (0U)
7486 #define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
7487 #define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */
7488 #define DMA2D_CR_SUSP_Pos          (1U)
7489 #define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
7490 #define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */
7491 #define DMA2D_CR_ABORT_Pos         (2U)
7492 #define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
7493 #define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */
7494 #define DMA2D_CR_LOM_Pos           (6U)
7495 #define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
7496 #define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */
7497 #define DMA2D_CR_TEIE_Pos          (8U)
7498 #define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
7499 #define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */
7500 #define DMA2D_CR_TCIE_Pos          (9U)
7501 #define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
7502 #define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */
7503 #define DMA2D_CR_TWIE_Pos          (10U)
7504 #define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
7505 #define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */
7506 #define DMA2D_CR_CAEIE_Pos         (11U)
7507 #define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
7508 #define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */
7509 #define DMA2D_CR_CTCIE_Pos         (12U)
7510 #define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
7511 #define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
7512 #define DMA2D_CR_CEIE_Pos          (13U)
7513 #define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
7514 #define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */
7515 #define DMA2D_CR_MODE_Pos          (16U)
7516 #define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
7517 #define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */
7518 #define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
7519 #define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
7520 #define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */
7521 
7522 /********************  Bit definition for DMA2D_ISR register  *****************/
7523 
7524 #define DMA2D_ISR_TEIF_Pos         (0U)
7525 #define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
7526 #define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */
7527 #define DMA2D_ISR_TCIF_Pos         (1U)
7528 #define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
7529 #define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */
7530 #define DMA2D_ISR_TWIF_Pos         (2U)
7531 #define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
7532 #define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */
7533 #define DMA2D_ISR_CAEIF_Pos        (3U)
7534 #define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
7535 #define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */
7536 #define DMA2D_ISR_CTCIF_Pos        (4U)
7537 #define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
7538 #define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
7539 #define DMA2D_ISR_CEIF_Pos         (5U)
7540 #define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
7541 #define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */
7542 
7543 /********************  Bit definition for DMA2D_IFCR register  ****************/
7544 
7545 #define DMA2D_IFCR_CTEIF_Pos       (0U)
7546 #define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
7547 #define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
7548 #define DMA2D_IFCR_CTCIF_Pos       (1U)
7549 #define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
7550 #define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
7551 #define DMA2D_IFCR_CTWIF_Pos       (2U)
7552 #define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
7553 #define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
7554 #define DMA2D_IFCR_CAECIF_Pos      (3U)
7555 #define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
7556 #define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
7557 #define DMA2D_IFCR_CCTCIF_Pos      (4U)
7558 #define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
7559 #define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
7560 #define DMA2D_IFCR_CCEIF_Pos       (5U)
7561 #define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
7562 #define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
7563 
7564 /********************  Bit definition for DMA2D_FGMAR register  ***************/
7565 
7566 #define DMA2D_FGMAR_MA_Pos         (0U)
7567 #define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
7568 #define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */
7569 
7570 /********************  Bit definition for DMA2D_FGOR register  ****************/
7571 
7572 #define DMA2D_FGOR_LO_Pos          (0U)
7573 #define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
7574 #define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
7575 
7576 /********************  Bit definition for DMA2D_BGMAR register  ***************/
7577 
7578 #define DMA2D_BGMAR_MA_Pos         (0U)
7579 #define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
7580 #define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */
7581 
7582 /********************  Bit definition for DMA2D_BGOR register  ****************/
7583 
7584 #define DMA2D_BGOR_LO_Pos          (0U)
7585 #define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
7586 #define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
7587 
7588 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
7589 
7590 #define DMA2D_FGPFCCR_CM_Pos       (0U)
7591 #define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
7592 #define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
7593 #define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
7594 #define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
7595 #define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
7596 #define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
7597 #define DMA2D_FGPFCCR_CCM_Pos      (4U)
7598 #define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
7599 #define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
7600 #define DMA2D_FGPFCCR_START_Pos    (5U)
7601 #define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
7602 #define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
7603 #define DMA2D_FGPFCCR_CS_Pos       (8U)
7604 #define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
7605 #define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
7606 #define DMA2D_FGPFCCR_AM_Pos       (16U)
7607 #define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
7608 #define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
7609 #define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
7610 #define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
7611 #define DMA2D_FGPFCCR_CSS_Pos      (18U)
7612 #define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
7613 #define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */
7614 #define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */
7615 #define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */
7616 #define DMA2D_FGPFCCR_AI_Pos       (20U)
7617 #define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
7618 #define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */
7619 #define DMA2D_FGPFCCR_RBS_Pos      (21U)
7620 #define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
7621 #define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */
7622 #define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
7623 #define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
7624 #define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
7625 
7626 /********************  Bit definition for DMA2D_FGCOLR register  **************/
7627 
7628 #define DMA2D_FGCOLR_BLUE_Pos      (0U)
7629 #define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
7630 #define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */
7631 #define DMA2D_FGCOLR_GREEN_Pos     (8U)
7632 #define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
7633 #define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */
7634 #define DMA2D_FGCOLR_RED_Pos       (16U)
7635 #define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
7636 #define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */
7637 
7638 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
7639 
7640 #define DMA2D_BGPFCCR_CM_Pos       (0U)
7641 #define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
7642 #define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
7643 #define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
7644 #define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
7645 #define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
7646 #define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
7647 #define DMA2D_BGPFCCR_CCM_Pos      (4U)
7648 #define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
7649 #define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
7650 #define DMA2D_BGPFCCR_START_Pos    (5U)
7651 #define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
7652 #define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
7653 #define DMA2D_BGPFCCR_CS_Pos       (8U)
7654 #define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
7655 #define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
7656 #define DMA2D_BGPFCCR_AM_Pos       (16U)
7657 #define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
7658 #define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
7659 #define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
7660 #define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
7661 #define DMA2D_BGPFCCR_AI_Pos       (20U)
7662 #define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
7663 #define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */
7664 #define DMA2D_BGPFCCR_RBS_Pos      (21U)
7665 #define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
7666 #define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */
7667 #define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
7668 #define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
7669 #define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
7670 
7671 /********************  Bit definition for DMA2D_BGCOLR register  **************/
7672 
7673 #define DMA2D_BGCOLR_BLUE_Pos      (0U)
7674 #define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
7675 #define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */
7676 #define DMA2D_BGCOLR_GREEN_Pos     (8U)
7677 #define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
7678 #define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */
7679 #define DMA2D_BGCOLR_RED_Pos       (16U)
7680 #define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
7681 #define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */
7682 
7683 /********************  Bit definition for DMA2D_FGCMAR register  **************/
7684 
7685 #define DMA2D_FGCMAR_MA_Pos        (0U)
7686 #define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
7687 #define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */
7688 
7689 /********************  Bit definition for DMA2D_BGCMAR register  **************/
7690 
7691 #define DMA2D_BGCMAR_MA_Pos        (0U)
7692 #define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
7693 #define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */
7694 
7695 /********************  Bit definition for DMA2D_OPFCCR register  **************/
7696 
7697 #define DMA2D_OPFCCR_CM_Pos        (0U)
7698 #define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
7699 #define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */
7700 #define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
7701 #define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
7702 #define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
7703 #define DMA2D_OPFCCR_SB_Pos        (8U)
7704 #define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
7705 #define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
7706 #define DMA2D_OPFCCR_AI_Pos        (20U)
7707 #define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
7708 #define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */
7709 #define DMA2D_OPFCCR_RBS_Pos       (21U)
7710 #define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
7711 #define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */
7712 
7713 /********************  Bit definition for DMA2D_OCOLR register  ***************/
7714 
7715 /*!<Mode_ARGB8888/RGB888 */
7716 
7717 #define DMA2D_OCOLR_BLUE_1_Pos     (0U)
7718 #define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/
7719 #define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */
7720 #define DMA2D_OCOLR_GREEN_1_Pos    (8U)
7721 #define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/
7722 #define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */
7723 #define DMA2D_OCOLR_RED_1_Pos      (16U)
7724 #define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */
7725 #define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */
7726 #define DMA2D_OCOLR_ALPHA_1_Pos    (24U)
7727 #define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/
7728 #define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */
7729 
7730 /*!<Mode_RGB565 */
7731 #define DMA2D_OCOLR_BLUE_2_Pos     (0U)
7732 #define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/
7733 #define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */
7734 #define DMA2D_OCOLR_GREEN_2_Pos    (5U)
7735 #define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */
7736 #define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */
7737 #define DMA2D_OCOLR_RED_2_Pos      (11U)
7738 #define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/
7739 #define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */
7740 
7741 /*!<Mode_ARGB1555 */
7742 #define DMA2D_OCOLR_BLUE_3_Pos     (0U)
7743 #define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/
7744 #define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */
7745 #define DMA2D_OCOLR_GREEN_3_Pos    (5U)
7746 #define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/
7747 #define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */
7748 #define DMA2D_OCOLR_RED_3_Pos      (10U)
7749 #define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/
7750 #define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */
7751 #define DMA2D_OCOLR_ALPHA_3_Pos    (15U)
7752 #define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/
7753 #define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */
7754 
7755 /*!<Mode_ARGB4444 */
7756 #define DMA2D_OCOLR_BLUE_4_Pos     (0U)
7757 #define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/
7758 #define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */
7759 #define DMA2D_OCOLR_GREEN_4_Pos    (4U)
7760 #define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/
7761 #define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */
7762 #define DMA2D_OCOLR_RED_4_Pos      (8U)
7763 #define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/
7764 #define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */
7765 #define DMA2D_OCOLR_ALPHA_4_Pos    (12U)
7766 #define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/
7767 #define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */
7768 
7769 /********************  Bit definition for DMA2D_OMAR register  ****************/
7770 
7771 #define DMA2D_OMAR_MA_Pos          (0U)
7772 #define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
7773 #define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */
7774 
7775 /********************  Bit definition for DMA2D_OOR register  *****************/
7776 
7777 #define DMA2D_OOR_LO_Pos           (0U)
7778 #define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
7779 #define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */
7780 
7781 /********************  Bit definition for DMA2D_NLR register  *****************/
7782 
7783 #define DMA2D_NLR_NL_Pos           (0U)
7784 #define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
7785 #define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
7786 #define DMA2D_NLR_PL_Pos           (16U)
7787 #define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
7788 #define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
7789 
7790 /********************  Bit definition for DMA2D_LWR register  *****************/
7791 
7792 #define DMA2D_LWR_LW_Pos           (0U)
7793 #define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
7794 #define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
7795 
7796 /********************  Bit definition for DMA2D_AMTCR register  ***************/
7797 
7798 #define DMA2D_AMTCR_EN_Pos         (0U)
7799 #define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
7800 #define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
7801 #define DMA2D_AMTCR_DT_Pos         (8U)
7802 #define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
7803 #define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
7804 
7805 
7806 /********************  Bit definition for DMA2D_FGCLUT register  **************/
7807 
7808 /********************  Bit definition for DMA2D_BGCLUT register  **************/
7809 
7810 
7811 /******************************************************************************/
7812 /*                                                                            */
7813 /*                    External Interrupt/Event Controller                     */
7814 /*                                                                            */
7815 /******************************************************************************/
7816 /******************  Bit definition for EXTI_RTSR1 register  *******************/
7817 #define EXTI_RTSR1_TR_Pos          (0U)
7818 #define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
7819 #define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
7820 #define EXTI_RTSR1_TR0_Pos         (0U)
7821 #define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
7822 #define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
7823 #define EXTI_RTSR1_TR1_Pos         (1U)
7824 #define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
7825 #define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
7826 #define EXTI_RTSR1_TR2_Pos         (2U)
7827 #define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
7828 #define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
7829 #define EXTI_RTSR1_TR3_Pos         (3U)
7830 #define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
7831 #define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
7832 #define EXTI_RTSR1_TR4_Pos         (4U)
7833 #define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
7834 #define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
7835 #define EXTI_RTSR1_TR5_Pos         (5U)
7836 #define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
7837 #define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
7838 #define EXTI_RTSR1_TR6_Pos         (6U)
7839 #define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
7840 #define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
7841 #define EXTI_RTSR1_TR7_Pos         (7U)
7842 #define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
7843 #define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
7844 #define EXTI_RTSR1_TR8_Pos         (8U)
7845 #define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
7846 #define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
7847 #define EXTI_RTSR1_TR9_Pos         (9U)
7848 #define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
7849 #define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
7850 #define EXTI_RTSR1_TR10_Pos        (10U)
7851 #define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
7852 #define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
7853 #define EXTI_RTSR1_TR11_Pos        (11U)
7854 #define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
7855 #define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
7856 #define EXTI_RTSR1_TR12_Pos        (12U)
7857 #define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
7858 #define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
7859 #define EXTI_RTSR1_TR13_Pos        (13U)
7860 #define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
7861 #define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
7862 #define EXTI_RTSR1_TR14_Pos        (14U)
7863 #define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
7864 #define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
7865 #define EXTI_RTSR1_TR15_Pos        (15U)
7866 #define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
7867 #define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
7868 #define EXTI_RTSR1_TR16_Pos        (16U)
7869 #define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
7870 #define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
7871 #define EXTI_RTSR1_TR17_Pos        (17U)
7872 #define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
7873 #define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
7874 #define EXTI_RTSR1_TR18_Pos        (18U)
7875 #define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */
7876 #define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
7877 #define EXTI_RTSR1_TR19_Pos        (19U)
7878 #define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */
7879 #define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
7880 #define EXTI_RTSR1_TR20_Pos        (20U)
7881 #define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
7882 #define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
7883 #define EXTI_RTSR1_TR21_Pos        (21U)
7884 #define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
7885 #define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
7886 
7887 /******************  Bit definition for EXTI_FTSR1 register  *******************/
7888 #define EXTI_FTSR1_TR_Pos          (0U)
7889 #define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
7890 #define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
7891 #define EXTI_FTSR1_TR0_Pos         (0U)
7892 #define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
7893 #define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
7894 #define EXTI_FTSR1_TR1_Pos         (1U)
7895 #define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
7896 #define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
7897 #define EXTI_FTSR1_TR2_Pos         (2U)
7898 #define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
7899 #define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
7900 #define EXTI_FTSR1_TR3_Pos         (3U)
7901 #define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
7902 #define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
7903 #define EXTI_FTSR1_TR4_Pos         (4U)
7904 #define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
7905 #define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
7906 #define EXTI_FTSR1_TR5_Pos         (5U)
7907 #define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
7908 #define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
7909 #define EXTI_FTSR1_TR6_Pos         (6U)
7910 #define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
7911 #define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
7912 #define EXTI_FTSR1_TR7_Pos         (7U)
7913 #define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
7914 #define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
7915 #define EXTI_FTSR1_TR8_Pos         (8U)
7916 #define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
7917 #define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
7918 #define EXTI_FTSR1_TR9_Pos         (9U)
7919 #define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
7920 #define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
7921 #define EXTI_FTSR1_TR10_Pos        (10U)
7922 #define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
7923 #define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
7924 #define EXTI_FTSR1_TR11_Pos        (11U)
7925 #define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
7926 #define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
7927 #define EXTI_FTSR1_TR12_Pos        (12U)
7928 #define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
7929 #define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
7930 #define EXTI_FTSR1_TR13_Pos        (13U)
7931 #define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
7932 #define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
7933 #define EXTI_FTSR1_TR14_Pos        (14U)
7934 #define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
7935 #define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
7936 #define EXTI_FTSR1_TR15_Pos        (15U)
7937 #define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
7938 #define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
7939 #define EXTI_FTSR1_TR16_Pos        (16U)
7940 #define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
7941 #define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
7942 #define EXTI_FTSR1_TR17_Pos        (17U)
7943 #define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
7944 #define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
7945 #define EXTI_FTSR1_TR18_Pos        (18U)
7946 #define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */
7947 #define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
7948 #define EXTI_FTSR1_TR19_Pos        (19U)
7949 #define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */
7950 #define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
7951 #define EXTI_FTSR1_TR20_Pos        (20U)
7952 #define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
7953 #define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
7954 #define EXTI_FTSR1_TR21_Pos        (21U)
7955 #define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
7956 #define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
7957 
7958 /******************  Bit definition for EXTI_SWIER1 register  ******************/
7959 #define EXTI_SWIER1_SWIER0_Pos     (0U)
7960 #define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
7961 #define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
7962 #define EXTI_SWIER1_SWIER1_Pos     (1U)
7963 #define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
7964 #define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
7965 #define EXTI_SWIER1_SWIER2_Pos     (2U)
7966 #define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
7967 #define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
7968 #define EXTI_SWIER1_SWIER3_Pos     (3U)
7969 #define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
7970 #define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
7971 #define EXTI_SWIER1_SWIER4_Pos     (4U)
7972 #define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
7973 #define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
7974 #define EXTI_SWIER1_SWIER5_Pos     (5U)
7975 #define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
7976 #define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
7977 #define EXTI_SWIER1_SWIER6_Pos     (6U)
7978 #define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
7979 #define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
7980 #define EXTI_SWIER1_SWIER7_Pos     (7U)
7981 #define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
7982 #define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
7983 #define EXTI_SWIER1_SWIER8_Pos     (8U)
7984 #define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
7985 #define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
7986 #define EXTI_SWIER1_SWIER9_Pos     (9U)
7987 #define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
7988 #define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
7989 #define EXTI_SWIER1_SWIER10_Pos    (10U)
7990 #define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
7991 #define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
7992 #define EXTI_SWIER1_SWIER11_Pos    (11U)
7993 #define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
7994 #define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
7995 #define EXTI_SWIER1_SWIER12_Pos    (12U)
7996 #define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
7997 #define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
7998 #define EXTI_SWIER1_SWIER13_Pos    (13U)
7999 #define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
8000 #define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
8001 #define EXTI_SWIER1_SWIER14_Pos    (14U)
8002 #define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
8003 #define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
8004 #define EXTI_SWIER1_SWIER15_Pos    (15U)
8005 #define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
8006 #define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
8007 #define EXTI_SWIER1_SWIER16_Pos    (16U)
8008 #define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
8009 #define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
8010 #define EXTI_SWIER1_SWIER17_Pos    (17U)
8011 #define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
8012 #define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
8013 #define EXTI_SWIER1_SWIER18_Pos    (18U)
8014 #define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */
8015 #define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
8016 #define EXTI_SWIER1_SWIER19_Pos    (19U)
8017 #define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */
8018 #define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
8019 #define EXTI_SWIER1_SWIER20_Pos    (20U)
8020 #define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
8021 #define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
8022 #define EXTI_SWIER1_SWIER21_Pos    (21U)
8023 #define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
8024 #define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
8025 
8026 /******************  Bit definition for EXTI_D3PMR1 register  ******************/
8027 #define EXTI_D3PMR1_MR0_Pos        (0U)
8028 #define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */
8029 #define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */
8030 #define EXTI_D3PMR1_MR1_Pos        (1U)
8031 #define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */
8032 #define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */
8033 #define EXTI_D3PMR1_MR2_Pos        (2U)
8034 #define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */
8035 #define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */
8036 #define EXTI_D3PMR1_MR3_Pos        (3U)
8037 #define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */
8038 #define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */
8039 #define EXTI_D3PMR1_MR4_Pos        (4U)
8040 #define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */
8041 #define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */
8042 #define EXTI_D3PMR1_MR5_Pos        (5U)
8043 #define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */
8044 #define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */
8045 #define EXTI_D3PMR1_MR6_Pos        (6U)
8046 #define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */
8047 #define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */
8048 #define EXTI_D3PMR1_MR7_Pos        (7U)
8049 #define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */
8050 #define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */
8051 #define EXTI_D3PMR1_MR8_Pos        (8U)
8052 #define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */
8053 #define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */
8054 #define EXTI_D3PMR1_MR9_Pos        (9U)
8055 #define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */
8056 #define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */
8057 #define EXTI_D3PMR1_MR10_Pos       (10U)
8058 #define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */
8059 #define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */
8060 #define EXTI_D3PMR1_MR11_Pos       (11U)
8061 #define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */
8062 #define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */
8063 #define EXTI_D3PMR1_MR12_Pos       (12U)
8064 #define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */
8065 #define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */
8066 #define EXTI_D3PMR1_MR13_Pos       (13U)
8067 #define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */
8068 #define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */
8069 #define EXTI_D3PMR1_MR14_Pos       (14U)
8070 #define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */
8071 #define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */
8072 #define EXTI_D3PMR1_MR15_Pos       (15U)
8073 #define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */
8074 #define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */
8075 #define EXTI_D3PMR1_MR19_Pos       (19U)
8076 #define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */
8077 #define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */
8078 #define EXTI_D3PMR1_MR20_Pos       (20U)
8079 #define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */
8080 #define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */
8081 #define EXTI_D3PMR1_MR21_Pos       (21U)
8082 #define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */
8083 #define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */
8084 #define EXTI_D3PMR1_MR25_Pos       (24U)
8085 #define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */
8086 #define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */
8087 
8088 /*******************  Bit definition for EXTI_D3PCR1L register  ****************/
8089 #define EXTI_D3PCR1L_PCS0_Pos       (0U)
8090 #define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */
8091 #define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */
8092 #define EXTI_D3PCR1L_PCS1_Pos       (2U)
8093 #define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */
8094 #define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */
8095 #define EXTI_D3PCR1L_PCS2_Pos       (4U)
8096 #define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */
8097 #define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */
8098 #define EXTI_D3PCR1L_PCS3_Pos       (6U)
8099 #define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */
8100 #define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */
8101 #define EXTI_D3PCR1L_PCS4_Pos       (8U)
8102 #define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */
8103 #define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */
8104 #define EXTI_D3PCR1L_PCS5_Pos       (10U)
8105 #define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */
8106 #define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */
8107 #define EXTI_D3PCR1L_PCS6_Pos       (12U)
8108 #define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */
8109 #define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */
8110 #define EXTI_D3PCR1L_PCS7_Pos       (14U)
8111 #define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */
8112 #define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */
8113 #define EXTI_D3PCR1L_PCS8_Pos       (16U)
8114 #define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */
8115 #define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */
8116 #define EXTI_D3PCR1L_PCS9_Pos       (18U)
8117 #define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */
8118 #define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */
8119 #define EXTI_D3PCR1L_PCS10_Pos      (20U)
8120 #define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */
8121 #define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/
8122 #define EXTI_D3PCR1L_PCS11_Pos      (22U)
8123 #define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */
8124 #define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/
8125 #define EXTI_D3PCR1L_PCS12_Pos      (24U)
8126 #define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */
8127 #define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/
8128 #define EXTI_D3PCR1L_PCS13_Pos      (26U)
8129 #define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */
8130 #define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/
8131 #define EXTI_D3PCR1L_PCS14_Pos      (28U)
8132 #define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */
8133 #define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/
8134 #define EXTI_D3PCR1L_PCS15_Pos      (30U)
8135 #define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */
8136 #define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/
8137 
8138 /*******************  Bit definition for EXTI_D3PCR1H register  ****************/
8139 #define EXTI_D3PCR1H_PCS19_Pos       (6U)
8140 #define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */
8141 #define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */
8142 #define EXTI_D3PCR1H_PCS20_Pos       (8U)
8143 #define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */
8144 #define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */
8145 #define EXTI_D3PCR1H_PCS21_Pos       (10U)
8146 #define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */
8147 #define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */
8148 #define EXTI_D3PCR1H_PCS25_Pos       (18U)
8149 #define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */
8150 #define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */
8151 
8152 /******************  Bit definition for EXTI_RTSR2 register  *******************/
8153 #define EXTI_RTSR2_TR_Pos          (17U)
8154 #define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */
8155 #define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
8156 #define EXTI_RTSR2_TR49_Pos        (17U)
8157 #define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */
8158 #define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */
8159 #define EXTI_RTSR2_TR51_Pos        (19U)
8160 #define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */
8161 #define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */
8162 
8163 /******************  Bit definition for EXTI_FTSR2 register  *******************/
8164 #define EXTI_FTSR2_TR_Pos          (17U)
8165 #define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */
8166 #define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
8167 #define EXTI_FTSR2_TR49_Pos        (17U)
8168 #define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */
8169 #define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */
8170 #define EXTI_FTSR2_TR51_Pos        (19U)
8171 #define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */
8172 #define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */
8173 
8174 /******************  Bit definition for EXTI_SWIER2 register  ******************/
8175 #define EXTI_SWIER2_SWIER49_Pos    (17U)
8176 #define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */
8177 #define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */
8178 #define EXTI_SWIER2_SWIER51_Pos    (19U)
8179 #define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */
8180 #define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */
8181 
8182 /******************  Bit definition for EXTI_D3PMR2 register  ******************/
8183 #define EXTI_D3PMR2_MR34_Pos       (2U)
8184 #define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */
8185 #define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */
8186 #define EXTI_D3PMR2_MR35_Pos       (3U)
8187 #define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */
8188 #define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */
8189 #define EXTI_D3PMR2_MR41_Pos       (9U)
8190 #define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */
8191 #define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */
8192 #define EXTI_D3PMR2_MR48_Pos       (16U)
8193 #define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */
8194 #define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */
8195 #define EXTI_D3PMR2_MR49_Pos       (17U)
8196 #define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */
8197 #define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */
8198 #define EXTI_D3PMR2_MR50_Pos       (18U)
8199 #define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */
8200 #define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */
8201 #define EXTI_D3PMR2_MR51_Pos       (19U)
8202 #define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */
8203 #define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */
8204 /*******************  Bit definition for EXTI_D3PCR2L register  ****************/
8205 #define EXTI_D3PCR2L_PCS34_Pos       (4U)
8206 #define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */
8207 #define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */
8208 #define EXTI_D3PCR2L_PCS35_Pos       (6U)
8209 #define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */
8210 #define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */
8211 #define EXTI_D3PCR2L_PCS41_Pos       (18U)
8212 #define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */
8213 #define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */
8214 
8215 
8216 /*******************  Bit definition for EXTI_D3PCR2H register  ****************/
8217 #define EXTI_D3PCR2H_PCS48_Pos       (0U)
8218 #define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */
8219 #define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */
8220 #define EXTI_D3PCR2H_PCS49_Pos       (2U)
8221 #define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */
8222 #define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */
8223 #define EXTI_D3PCR2H_PCS50_Pos       (4U)
8224 #define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */
8225 #define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */
8226 #define EXTI_D3PCR2H_PCS51_Pos       (6U)
8227 #define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */
8228 #define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */
8229 /******************  Bit definition for EXTI_RTSR3 register  *******************/
8230 #define EXTI_RTSR3_TR_Pos          (18U)
8231 #define EXTI_RTSR3_TR_Msk          (0x9UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00240000 */
8232 #define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit            */
8233 #define EXTI_RTSR3_TR82_Pos        (18U)
8234 #define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */
8235 #define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */
8236 #define EXTI_RTSR3_TR85_Pos        (21U)
8237 #define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */
8238 #define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */
8239 
8240 /******************  Bit definition for EXTI_FTSR3 register  *******************/
8241 #define EXTI_FTSR3_TR_Pos          (18U)
8242 #define EXTI_FTSR3_TR_Msk          (0x9UL << EXTI_FTSR3_TR_Pos)                /*!< 0x00240000 */
8243 #define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit            */
8244 #define EXTI_FTSR3_TR82_Pos        (18U)
8245 #define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */
8246 #define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */
8247 #define EXTI_FTSR3_TR85_Pos        (21U)
8248 #define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */
8249 #define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */
8250 
8251 /******************  Bit definition for EXTI_SWIER3 register  ******************/
8252 #define EXTI_SWIER3_SWI_Pos        (18U)
8253 #define EXTI_SWIER3_SWI_Msk        (0x9UL << EXTI_SWIER3_SWI_Pos)              /*!< 0x00240000 */
8254 #define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */
8255 #define EXTI_SWIER3_SWIER82_Pos    (18U)
8256 #define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */
8257 #define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */
8258 #define EXTI_SWIER3_SWIER85_Pos    (21U)
8259 #define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */
8260 #define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */
8261 
8262 /******************  Bit definition for EXTI_D3PMR3 register  ******************/
8263 #define EXTI_D3PMR3_MR88_Pos       (24U)
8264 #define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */
8265 #define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */
8266 
8267 /*******************  Bit definition for EXTI_D3PCR3H register  ****************/
8268 #define EXTI_D3PCR3H_PCS88_Pos       (16U)
8269 #define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */
8270 #define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */
8271 
8272 /*******************  Bit definition for EXTI_IMR1 register  *******************/
8273 #define EXTI_IMR1_IM_Pos           (0U)
8274 #define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
8275 #define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
8276 #define EXTI_IMR1_IM0_Pos          (0U)
8277 #define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
8278 #define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
8279 #define EXTI_IMR1_IM1_Pos          (1U)
8280 #define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
8281 #define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
8282 #define EXTI_IMR1_IM2_Pos          (2U)
8283 #define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
8284 #define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
8285 #define EXTI_IMR1_IM3_Pos          (3U)
8286 #define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
8287 #define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
8288 #define EXTI_IMR1_IM4_Pos          (4U)
8289 #define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
8290 #define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
8291 #define EXTI_IMR1_IM5_Pos          (5U)
8292 #define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
8293 #define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
8294 #define EXTI_IMR1_IM6_Pos          (6U)
8295 #define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
8296 #define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
8297 #define EXTI_IMR1_IM7_Pos          (7U)
8298 #define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
8299 #define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
8300 #define EXTI_IMR1_IM8_Pos          (8U)
8301 #define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
8302 #define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
8303 #define EXTI_IMR1_IM9_Pos          (9U)
8304 #define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
8305 #define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
8306 #define EXTI_IMR1_IM10_Pos         (10U)
8307 #define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
8308 #define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
8309 #define EXTI_IMR1_IM11_Pos         (11U)
8310 #define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
8311 #define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
8312 #define EXTI_IMR1_IM12_Pos         (12U)
8313 #define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
8314 #define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
8315 #define EXTI_IMR1_IM13_Pos         (13U)
8316 #define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
8317 #define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
8318 #define EXTI_IMR1_IM14_Pos         (14U)
8319 #define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
8320 #define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
8321 #define EXTI_IMR1_IM15_Pos         (15U)
8322 #define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
8323 #define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
8324 #define EXTI_IMR1_IM16_Pos         (16U)
8325 #define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
8326 #define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
8327 #define EXTI_IMR1_IM17_Pos         (17U)
8328 #define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
8329 #define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
8330 #define EXTI_IMR1_IM18_Pos         (18U)
8331 #define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */
8332 #define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
8333 #define EXTI_IMR1_IM19_Pos         (19U)
8334 #define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */
8335 #define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
8336 #define EXTI_IMR1_IM20_Pos         (20U)
8337 #define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
8338 #define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
8339 #define EXTI_IMR1_IM21_Pos         (21U)
8340 #define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
8341 #define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
8342 #define EXTI_IMR1_IM22_Pos         (22U)
8343 #define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */
8344 #define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
8345 #define EXTI_IMR1_IM23_Pos         (23U)
8346 #define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
8347 #define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
8348 #define EXTI_IMR1_IM24_Pos         (24U)
8349 #define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
8350 #define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
8351 #define EXTI_IMR1_IM25_Pos         (25U)
8352 #define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
8353 #define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
8354 #define EXTI_IMR1_IM26_Pos         (26U)
8355 #define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */
8356 #define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
8357 #define EXTI_IMR1_IM27_Pos         (27U)
8358 #define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
8359 #define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
8360 #define EXTI_IMR1_IM28_Pos         (28U)
8361 #define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
8362 #define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
8363 #define EXTI_IMR1_IM29_Pos         (29U)
8364 #define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
8365 #define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
8366 #define EXTI_IMR1_IM30_Pos         (30U)
8367 #define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
8368 #define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
8369 #define EXTI_IMR1_IM31_Pos         (31U)
8370 #define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
8371 #define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
8372 
8373 /*******************  Bit definition for EXTI_EMR1 register  *******************/
8374 #define EXTI_EMR1_EM_Pos           (0U)
8375 #define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
8376 #define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
8377 #define EXTI_EMR1_EM0_Pos          (0U)
8378 #define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
8379 #define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
8380 #define EXTI_EMR1_EM1_Pos          (1U)
8381 #define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
8382 #define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
8383 #define EXTI_EMR1_EM2_Pos          (2U)
8384 #define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
8385 #define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
8386 #define EXTI_EMR1_EM3_Pos          (3U)
8387 #define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
8388 #define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
8389 #define EXTI_EMR1_EM4_Pos          (4U)
8390 #define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
8391 #define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
8392 #define EXTI_EMR1_EM5_Pos          (5U)
8393 #define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
8394 #define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
8395 #define EXTI_EMR1_EM6_Pos          (6U)
8396 #define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
8397 #define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
8398 #define EXTI_EMR1_EM7_Pos          (7U)
8399 #define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
8400 #define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
8401 #define EXTI_EMR1_EM8_Pos          (8U)
8402 #define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
8403 #define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
8404 #define EXTI_EMR1_EM9_Pos          (9U)
8405 #define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
8406 #define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
8407 #define EXTI_EMR1_EM10_Pos         (10U)
8408 #define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
8409 #define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
8410 #define EXTI_EMR1_EM11_Pos         (11U)
8411 #define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
8412 #define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
8413 #define EXTI_EMR1_EM12_Pos         (12U)
8414 #define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
8415 #define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
8416 #define EXTI_EMR1_EM13_Pos         (13U)
8417 #define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
8418 #define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
8419 #define EXTI_EMR1_EM14_Pos         (14U)
8420 #define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
8421 #define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
8422 #define EXTI_EMR1_EM15_Pos         (15U)
8423 #define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
8424 #define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
8425 #define EXTI_EMR1_EM16_Pos         (16U)
8426 #define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
8427 #define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
8428 #define EXTI_EMR1_EM17_Pos         (17U)
8429 #define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
8430 #define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
8431 #define EXTI_EMR1_EM18_Pos         (18U)
8432 #define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */
8433 #define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
8434 #define EXTI_EMR1_EM20_Pos         (20U)
8435 #define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
8436 #define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
8437 #define EXTI_EMR1_EM21_Pos         (21U)
8438 #define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
8439 #define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
8440 #define EXTI_EMR1_EM22_Pos         (22U)
8441 #define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */
8442 #define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
8443 #define EXTI_EMR1_EM23_Pos         (23U)
8444 #define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
8445 #define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
8446 #define EXTI_EMR1_EM24_Pos         (24U)
8447 #define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
8448 #define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
8449 #define EXTI_EMR1_EM25_Pos         (25U)
8450 #define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
8451 #define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
8452 #define EXTI_EMR1_EM26_Pos         (26U)
8453 #define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */
8454 #define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
8455 #define EXTI_EMR1_EM27_Pos         (27U)
8456 #define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
8457 #define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
8458 #define EXTI_EMR1_EM28_Pos         (28U)
8459 #define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
8460 #define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
8461 #define EXTI_EMR1_EM29_Pos         (29U)
8462 #define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
8463 #define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
8464 #define EXTI_EMR1_EM30_Pos         (30U)
8465 #define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
8466 #define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
8467 #define EXTI_EMR1_EM31_Pos         (31U)
8468 #define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
8469 #define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
8470 
8471 /*******************  Bit definition for EXTI_PR1 register  ********************/
8472 #define EXTI_PR1_PR_Pos            (0U)
8473 #define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */
8474 #define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */
8475 #define EXTI_PR1_PR0_Pos           (0U)
8476 #define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */
8477 #define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */
8478 #define EXTI_PR1_PR1_Pos           (1U)
8479 #define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */
8480 #define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */
8481 #define EXTI_PR1_PR2_Pos           (2U)
8482 #define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */
8483 #define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */
8484 #define EXTI_PR1_PR3_Pos           (3U)
8485 #define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */
8486 #define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */
8487 #define EXTI_PR1_PR4_Pos           (4U)
8488 #define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */
8489 #define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */
8490 #define EXTI_PR1_PR5_Pos           (5U)
8491 #define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */
8492 #define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */
8493 #define EXTI_PR1_PR6_Pos           (6U)
8494 #define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */
8495 #define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */
8496 #define EXTI_PR1_PR7_Pos           (7U)
8497 #define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */
8498 #define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */
8499 #define EXTI_PR1_PR8_Pos           (8U)
8500 #define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */
8501 #define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */
8502 #define EXTI_PR1_PR9_Pos           (9U)
8503 #define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */
8504 #define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */
8505 #define EXTI_PR1_PR10_Pos          (10U)
8506 #define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */
8507 #define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */
8508 #define EXTI_PR1_PR11_Pos          (11U)
8509 #define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */
8510 #define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */
8511 #define EXTI_PR1_PR12_Pos          (12U)
8512 #define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */
8513 #define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */
8514 #define EXTI_PR1_PR13_Pos          (13U)
8515 #define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */
8516 #define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */
8517 #define EXTI_PR1_PR14_Pos          (14U)
8518 #define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */
8519 #define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */
8520 #define EXTI_PR1_PR15_Pos          (15U)
8521 #define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */
8522 #define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */
8523 #define EXTI_PR1_PR16_Pos          (16U)
8524 #define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */
8525 #define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */
8526 #define EXTI_PR1_PR17_Pos          (17U)
8527 #define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */
8528 #define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */
8529 #define EXTI_PR1_PR18_Pos          (18U)
8530 #define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */
8531 #define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */
8532 #define EXTI_PR1_PR19_Pos          (19U)
8533 #define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */
8534 #define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */
8535 #define EXTI_PR1_PR20_Pos          (20U)
8536 #define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */
8537 #define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */
8538 #define EXTI_PR1_PR21_Pos          (21U)
8539 #define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */
8540 #define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */
8541 
8542 /*******************  Bit definition for EXTI_IMR2 register  *******************/
8543 #define EXTI_IMR2_IM_Pos           (0U)
8544 #define EXTI_IMR2_IM_Msk           (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */
8545 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */
8546 #define EXTI_IMR2_IM32_Pos         (0U)
8547 #define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */
8548 #define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
8549 #define EXTI_IMR2_IM33_Pos         (1U)
8550 #define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
8551 #define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
8552 #define EXTI_IMR2_IM34_Pos         (2U)
8553 #define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
8554 #define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
8555 #define EXTI_IMR2_IM35_Pos         (3U)
8556 #define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
8557 #define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
8558 #define EXTI_IMR2_IM36_Pos         (4U)
8559 #define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */
8560 #define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
8561 #define EXTI_IMR2_IM37_Pos         (5U)
8562 #define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
8563 #define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
8564 #define EXTI_IMR2_IM38_Pos         (6U)
8565 #define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */
8566 #define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */
8567 #define EXTI_IMR2_IM39_Pos         (7U)
8568 #define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */
8569 #define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */
8570 #define EXTI_IMR2_IM40_Pos         (8U)
8571 #define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */
8572 #define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */
8573 #define EXTI_IMR2_IM41_Pos         (9U)
8574 #define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */
8575 #define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */
8576 #define EXTI_IMR2_IM42_Pos         (10U)
8577 #define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */
8578 #define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */
8579 #define EXTI_IMR2_IM43_Pos         (11U)
8580 #define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */
8581 #define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */
8582 #define EXTI_IMR2_IM47_Pos         (15U)
8583 #define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */
8584 #define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */
8585 #define EXTI_IMR2_IM48_Pos         (16U)
8586 #define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */
8587 #define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */
8588 #define EXTI_IMR2_IM49_Pos         (17U)
8589 #define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */
8590 #define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */
8591 #define EXTI_IMR2_IM50_Pos         (18U)
8592 #define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */
8593 #define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */
8594 #define EXTI_IMR2_IM51_Pos         (19U)
8595 #define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */
8596 #define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */
8597 #define EXTI_IMR2_IM52_Pos         (20U)
8598 #define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */
8599 #define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */
8600 #define EXTI_IMR2_IM53_Pos         (21U)
8601 #define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */
8602 #define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */
8603 #define EXTI_IMR2_IM54_Pos         (22U)
8604 #define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */
8605 #define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */
8606 #define EXTI_IMR2_IM55_Pos         (23U)
8607 #define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */
8608 #define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */
8609 #define EXTI_IMR2_IM56_Pos         (24U)
8610 #define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */
8611 #define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */
8612 #define EXTI_IMR2_IM57_Pos         (25U)
8613 #define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */
8614 #define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */
8615 #define EXTI_IMR2_IM58_Pos         (26U)
8616 #define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */
8617 #define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */
8618 #define EXTI_IMR2_IM59_Pos         (27U)
8619 #define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */
8620 #define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */
8621 #define EXTI_IMR2_IM60_Pos         (28U)
8622 #define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */
8623 #define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */
8624 #define EXTI_IMR2_IM61_Pos         (29U)
8625 #define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */
8626 #define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */
8627 #define EXTI_IMR2_IM62_Pos         (30U)
8628 #define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */
8629 #define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */
8630 #define EXTI_IMR2_IM63_Pos         (31U)
8631 #define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */
8632 #define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */
8633 
8634 /*******************  Bit definition for EXTI_EMR2 register  *******************/
8635 #define EXTI_EMR2_EM_Pos           (0U)
8636 #define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */
8637 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */
8638 #define EXTI_EMR2_EM32_Pos         (0U)
8639 #define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */
8640 #define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
8641 #define EXTI_EMR2_EM33_Pos         (1U)
8642 #define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
8643 #define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
8644 #define EXTI_EMR2_EM34_Pos         (2U)
8645 #define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
8646 #define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
8647 #define EXTI_EMR2_EM35_Pos         (3U)
8648 #define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
8649 #define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
8650 #define EXTI_EMR2_EM36_Pos         (4U)
8651 #define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */
8652 #define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
8653 #define EXTI_EMR2_EM37_Pos         (5U)
8654 #define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
8655 #define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
8656 #define EXTI_EMR2_EM38_Pos         (6U)
8657 #define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */
8658 #define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/
8659 #define EXTI_EMR2_EM39_Pos         (7U)
8660 #define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */
8661 #define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/
8662 #define EXTI_EMR2_EM40_Pos         (8U)
8663 #define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */
8664 #define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/
8665 #define EXTI_EMR2_EM41_Pos         (9U)
8666 #define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */
8667 #define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/
8668 #define EXTI_EMR2_EM42_Pos         (10U)
8669 #define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */
8670 #define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */
8671 #define EXTI_EMR2_EM43_Pos         (11U)
8672 #define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */
8673 #define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */
8674 #define EXTI_EMR2_EM47_Pos         (15U)
8675 #define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */
8676 #define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */
8677 #define EXTI_EMR2_EM48_Pos         (16U)
8678 #define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */
8679 #define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */
8680 #define EXTI_EMR2_EM49_Pos         (17U)
8681 #define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */
8682 #define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */
8683 #define EXTI_EMR2_EM50_Pos         (18U)
8684 #define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */
8685 #define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */
8686 #define EXTI_EMR2_EM51_Pos         (19U)
8687 #define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */
8688 #define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */
8689 #define EXTI_EMR2_EM52_Pos         (20U)
8690 #define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */
8691 #define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */
8692 #define EXTI_EMR2_EM53_Pos         (21U)
8693 #define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */
8694 #define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */
8695 #define EXTI_EMR2_EM54_Pos         (22U)
8696 #define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */
8697 #define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */
8698 #define EXTI_EMR2_EM55_Pos         (23U)
8699 #define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */
8700 #define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */
8701 #define EXTI_EMR2_EM56_Pos         (24U)
8702 #define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */
8703 #define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */
8704 #define EXTI_EMR2_EM57_Pos         (25U)
8705 #define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */
8706 #define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */
8707 #define EXTI_EMR2_EM58_Pos         (26U)
8708 #define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */
8709 #define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */
8710 #define EXTI_EMR2_EM59_Pos         (27U)
8711 #define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */
8712 #define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */
8713 #define EXTI_EMR2_EM60_Pos         (28U)
8714 #define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */
8715 #define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */
8716 #define EXTI_EMR2_EM61_Pos         (29U)
8717 #define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */
8718 #define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */
8719 #define EXTI_EMR2_EM62_Pos         (30U)
8720 #define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */
8721 #define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */
8722 #define EXTI_EMR2_EM63_Pos         (31U)
8723 #define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */
8724 #define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */
8725 
8726 /*******************  Bit definition for EXTI_PR2 register  ********************/
8727 #define EXTI_PR2_PR_Pos            (17U)
8728 #define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */
8729 #define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */
8730 #define EXTI_PR2_PR49_Pos          (17U)
8731 #define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */
8732 #define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */
8733 #define EXTI_PR2_PR51_Pos          (19U)
8734 #define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */
8735 #define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */
8736 
8737 /*******************  Bit definition for EXTI_IMR3 register  *******************/
8738 #define EXTI_IMR3_IM_Pos           (0U)
8739 #define EXTI_IMR3_IM_Msk           (0x01A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x01A527FF */
8740 #define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */
8741 #define EXTI_IMR3_IM64_Pos         (0U)
8742 #define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
8743 #define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */
8744 #define EXTI_IMR3_IM65_Pos         (1U)
8745 #define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */
8746 #define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */
8747 #define EXTI_IMR3_IM66_Pos         (2U)
8748 #define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */
8749 #define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */
8750 #define EXTI_IMR3_IM67_Pos         (3U)
8751 #define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */
8752 #define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */
8753 #define EXTI_IMR3_IM68_Pos         (4U)
8754 #define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */
8755 #define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */
8756 #define EXTI_IMR3_IM69_Pos         (5U)
8757 #define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */
8758 #define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */
8759 #define EXTI_IMR3_IM70_Pos         (6U)
8760 #define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */
8761 #define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */
8762 #define EXTI_IMR3_IM71_Pos         (7U)
8763 #define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */
8764 #define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */
8765 #define EXTI_IMR3_IM72_Pos         (8U)
8766 #define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */
8767 #define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */
8768 #define EXTI_IMR3_IM73_Pos         (9U)
8769 #define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */
8770 #define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */
8771 #define EXTI_IMR3_IM74_Pos         (10U)
8772 #define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */
8773 #define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */
8774 #define EXTI_IMR3_IM77_Pos         (13U)
8775 #define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */
8776 #define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */
8777 #define EXTI_IMR3_IM80_Pos         (16U)
8778 #define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */
8779 #define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */
8780 #define EXTI_IMR3_IM82_Pos         (18U)
8781 #define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */
8782 #define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */
8783 #define EXTI_IMR3_IM85_Pos         (21U)
8784 #define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */
8785 #define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */
8786 #define EXTI_IMR3_IM87_Pos         (23U)
8787 #define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */
8788 #define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */
8789 
8790 
8791 #define EXTI_IMR3_IM88_Pos         (24U)
8792 #define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */
8793 #define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */
8794 
8795 /*******************  Bit definition for EXTI_EMR3 register  *******************/
8796 #define EXTI_EMR3_EM_Pos           (0U)
8797 #define EXTI_EMR3_EM_Msk           (0x01A527FFUL << EXTI_EMR3_EM_Pos)          /*!< 0x01A527FF */
8798 #define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */
8799 #define EXTI_EMR3_EM64_Pos         (0U)
8800 #define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */
8801 #define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/
8802 #define EXTI_EMR3_EM65_Pos         (1U)
8803 #define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */
8804 #define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/
8805 #define EXTI_EMR3_EM66_Pos         (2U)
8806 #define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */
8807 #define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/
8808 #define EXTI_EMR3_EM67_Pos         (3U)
8809 #define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */
8810 #define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/
8811 #define EXTI_EMR3_EM68_Pos         (4U)
8812 #define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */
8813 #define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/
8814 #define EXTI_EMR3_EM69_Pos         (5U)
8815 #define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */
8816 #define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/
8817 #define EXTI_EMR3_EM70_Pos         (6U)
8818 #define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */
8819 #define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/
8820 #define EXTI_EMR3_EM71_Pos         (7U)
8821 #define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */
8822 #define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/
8823 #define EXTI_EMR3_EM72_Pos         (8U)
8824 #define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */
8825 #define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/
8826 #define EXTI_EMR3_EM73_Pos         (9U)
8827 #define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */
8828 #define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/
8829 #define EXTI_EMR3_EM74_Pos         (10U)
8830 #define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */
8831 #define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */
8832 #define EXTI_EMR3_EM77_Pos         (13U)
8833 #define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */
8834 #define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */
8835 #define EXTI_EMR3_EM80_Pos         (16U)
8836 #define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */
8837 #define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */
8838 #define EXTI_EMR3_EM81_Pos         (17U)
8839 #define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */
8840 #define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */
8841 #define EXTI_EMR3_EM82_Pos         (18U)
8842 #define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */
8843 #define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */
8844 #define EXTI_EMR3_EM85_Pos         (21U)
8845 #define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */
8846 #define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */
8847 #define EXTI_EMR3_EM87_Pos         (23U)
8848 #define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */
8849 #define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */
8850 
8851 #define EXTI_EMR3_EM88_Pos         (24U)
8852 #define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */
8853 #define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */
8854 
8855 /*******************  Bit definition for EXTI_PR3 register  ********************/
8856 #define EXTI_PR3_PR_Pos            (18U)
8857 #define EXTI_PR3_PR_Msk            (0x9UL << EXTI_PR3_PR_Pos)                  /*!< 0x00240000 */
8858 #define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */
8859 #define EXTI_PR3_PR82_Pos          (18U)
8860 #define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */
8861 #define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */
8862 #define EXTI_PR3_PR85_Pos          (21U)
8863 #define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */
8864 #define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */
8865 /******************************************************************************/
8866 /*                                                                            */
8867 /*                                    FLASH                                   */
8868 /*                                                                            */
8869 /******************************************************************************/
8870 /*
8871 * @brief FLASH Global Defines
8872 */
8873 #define FLASH_SIZE_DATA_REGISTER             0x08FFF80CU
8874 #define FLASH_SECTOR_TOTAL                   128U                  /* 128 sectors */
8875 #define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
8876                                              ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
8877                                              (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */
8878 #define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
8879 #define FLASH_SECTOR_SIZE                    0x00002000UL          /* 8 KB   */
8880 #define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
8881 #define FLASH_NB_32BITWORD_IN_FLASHWORD      4U                    /* 128 bits */
8882 #define DUAL_BANK                                                  /* Dual-bank Flash */
8883 
8884 /*******************  Bits definition for FLASH_ACR register  **********************/
8885 #define FLASH_ACR_LATENCY_Pos                (0U)
8886 #define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
8887 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
8888 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
8889 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
8890 #define FLASH_ACR_LATENCY_2WS                (0x00000002UL)
8891 #define FLASH_ACR_LATENCY_3WS                (0x00000003UL)
8892 #define FLASH_ACR_LATENCY_4WS                (0x00000004UL)
8893 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
8894 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
8895 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
8896 
8897 #define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
8898 #define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
8899 #define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
8900 #define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
8901 #define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
8902 
8903 /* Legacy FLASH Latency defines */
8904 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
8905 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
8906 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
8907 #define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)
8908 #define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)
8909 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
8910 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
8911 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
8912 /*******************  Bits definition for FLASH_CR register  ***********************/
8913 #define FLASH_CR_LOCK_Pos                    (0U)
8914 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
8915 #define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */
8916 #define FLASH_CR_PG_Pos                      (1U)
8917 #define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */
8918 #define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */
8919 #define FLASH_CR_SER_Pos                     (2U)
8920 #define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */
8921 #define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */
8922 #define FLASH_CR_BER_Pos                     (3U)
8923 #define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */
8924 #define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */
8925 #define FLASH_CR_FW_Pos                      (4U)
8926 #define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000010 */
8927 #define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */
8928 #define FLASH_CR_START_Pos                   (5U)
8929 #define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000020 */
8930 #define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */
8931 #define FLASH_CR_SNB_Pos                     (6U)
8932 #define FLASH_CR_SNB_Msk                     (0x7FUL << FLASH_CR_SNB_Pos)      /*!< 0x00001FC0 */
8933 #define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */
8934 #define FLASH_CR_SNB_0                       (0x01UL << FLASH_CR_SNB_Pos)      /*!< 0x00000040 */
8935 #define FLASH_CR_SNB_1                       (0x02UL << FLASH_CR_SNB_Pos)      /*!< 0x00000080 */
8936 #define FLASH_CR_SNB_2                       (0x04UL << FLASH_CR_SNB_Pos)      /*!< 0x00000100 */
8937 #define FLASH_CR_SNB_3                       (0x08UL << FLASH_CR_SNB_Pos)      /*!< 0x00000200 */
8938 #define FLASH_CR_SNB_4                       (0x10UL << FLASH_CR_SNB_Pos)      /*!< 0x00000400 */
8939 #define FLASH_CR_SNB_5                       (0x20UL << FLASH_CR_SNB_Pos)      /*!< 0x00000800 */
8940 #define FLASH_CR_SNB_6                       (0x40UL << FLASH_CR_SNB_Pos)      /*!< 0x00001000 */
8941 #define FLASH_CR_CRC_EN_Pos                  (15U)
8942 #define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */
8943 #define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */
8944 #define FLASH_CR_EOPIE_Pos                   (16U)
8945 #define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */
8946 #define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */
8947 #define FLASH_CR_WRPERRIE_Pos                (17U)
8948 #define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */
8949 #define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */
8950 #define FLASH_CR_PGSERRIE_Pos                (18U)
8951 #define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */
8952 #define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */
8953 #define FLASH_CR_STRBERRIE_Pos               (19U)
8954 #define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
8955 #define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */
8956 #define FLASH_CR_INCERRIE_Pos                (21U)
8957 #define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */
8958 #define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */
8959 #define FLASH_CR_RDPERRIE_Pos                (23U)
8960 #define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */
8961 #define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */
8962 #define FLASH_CR_RDSERRIE_Pos                (24U)
8963 #define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */
8964 #define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */
8965 #define FLASH_CR_SNECCERRIE_Pos              (25U)
8966 #define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
8967 #define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */
8968 #define FLASH_CR_DBECCERRIE_Pos              (26U)
8969 #define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
8970 #define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */
8971 #define FLASH_CR_CRCENDIE_Pos                (27U)
8972 #define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */
8973 #define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */
8974 #define FLASH_CR_CRCRDERRIE_Pos              (28U)
8975 #define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
8976 #define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */
8977 
8978 /*******************  Bits definition for FLASH_SR register  ***********************/
8979 #define FLASH_SR_BSY_Pos                     (0U)
8980 #define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */
8981 #define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */
8982 #define FLASH_SR_WBNE_Pos                    (1U)
8983 #define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */
8984 #define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */
8985 #define FLASH_SR_QW_Pos                      (2U)
8986 #define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */
8987 #define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */
8988 #define FLASH_SR_CRC_BUSY_Pos                (3U)
8989 #define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */
8990 #define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */
8991 #define FLASH_SR_EOP_Pos                     (16U)
8992 #define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */
8993 #define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */
8994 #define FLASH_SR_WRPERR_Pos                  (17U)
8995 #define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */
8996 #define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */
8997 #define FLASH_SR_PGSERR_Pos                  (18U)
8998 #define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */
8999 #define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */
9000 #define FLASH_SR_STRBERR_Pos                 (19U)
9001 #define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */
9002 #define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */
9003 #define FLASH_SR_INCERR_Pos                  (21U)
9004 #define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */
9005 #define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */
9006 #define FLASH_SR_RDPERR_Pos                  (23U)
9007 #define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */
9008 #define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */
9009 #define FLASH_SR_RDSERR_Pos                  (24U)
9010 #define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */
9011 #define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */
9012 #define FLASH_SR_SNECCERR_Pos                (25U)
9013 #define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */
9014 #define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */
9015 #define FLASH_SR_DBECCERR_Pos                (26U)
9016 #define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */
9017 #define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */
9018 #define FLASH_SR_CRCEND_Pos                  (27U)
9019 #define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */
9020 #define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */
9021 #define FLASH_SR_CRCRDERR_Pos                (28U)
9022 #define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */
9023 #define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */
9024 
9025 /*******************  Bits definition for FLASH_CCR register  *******************/
9026 #define FLASH_CCR_CLR_EOP_Pos                (16U)
9027 #define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */
9028 #define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */
9029 #define FLASH_CCR_CLR_WRPERR_Pos             (17U)
9030 #define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
9031 #define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */
9032 #define FLASH_CCR_CLR_PGSERR_Pos             (18U)
9033 #define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
9034 #define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */
9035 #define FLASH_CCR_CLR_STRBERR_Pos            (19U)
9036 #define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
9037 #define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */
9038 #define FLASH_CCR_CLR_INCERR_Pos             (21U)
9039 #define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
9040 #define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */
9041 #define FLASH_CCR_CLR_RDPERR_Pos             (23U)
9042 #define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
9043 #define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */
9044 #define FLASH_CCR_CLR_RDSERR_Pos             (24U)
9045 #define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
9046 #define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */
9047 #define FLASH_CCR_CLR_SNECCERR_Pos           (25U)
9048 #define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
9049 #define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */
9050 #define FLASH_CCR_CLR_DBECCERR_Pos           (26U)
9051 #define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
9052 #define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */
9053 #define FLASH_CCR_CLR_CRCEND_Pos             (27U)
9054 #define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
9055 #define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */
9056 #define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)
9057 #define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
9058 #define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */
9059 
9060 /*******************  Bits definition for FLASH_OPTCR register  *******************/
9061 #define FLASH_OPTCR_OPTLOCK_Pos              (0U)
9062 #define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */
9063 #define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */
9064 #define FLASH_OPTCR_OPTSTART_Pos             (1U)
9065 #define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
9066 #define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */
9067 #define FLASH_OPTCR_MER_Pos                  (4U)
9068 #define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */
9069 #define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */
9070 #define FLASH_OPTCR_PG_OTP_Pos               (5U)
9071 #define FLASH_OPTCR_PG_OTP_Msk               (0x1UL << FLASH_OPTCR_PG_OTP_Pos)   /*!< 0x00000020 */
9072 #define FLASH_OPTCR_PG_OTP                   FLASH_OPTCR_PG_OTP_Msk              /*!< OTP program control bit */
9073 #define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)
9074 #define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
9075 #define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */
9076 #define FLASH_OPTCR_SWAP_BANK_Pos            (31U)
9077 #define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
9078 #define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */
9079 
9080 /*******************  Bits definition for FLASH_OPTSR register  ***************/
9081 #define FLASH_OPTSR_OPT_BUSY_Pos             (0U)
9082 #define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
9083 #define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */
9084 #define FLASH_OPTSR_BOR_LEV_Pos              (2U)
9085 #define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
9086 #define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */
9087 #define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
9088 #define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
9089 #define FLASH_OPTSR_IWDG1_SW_Pos             (4U)
9090 #define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
9091 #define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */
9092 #define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)
9093 #define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
9094 #define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */
9095 #define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)
9096 #define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
9097 #define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */
9098 #define FLASH_OPTSR_RDP_Pos                  (8U)
9099 #define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */
9100 #define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */
9101 #define FLASH_OPTSR_VDDMMC_HSLV_Pos          (16U)
9102 #define FLASH_OPTSR_VDDMMC_HSLV_Msk          (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */
9103 #define FLASH_OPTSR_VDDMMC_HSLV              FLASH_OPTSR_VDDMMC_HSLV_Msk            /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */
9104 #define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)
9105 #define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
9106 #define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */
9107 #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)
9108 #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
9109 #define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */
9110 #define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)
9111 #define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
9112 #define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */
9113 #define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
9114 #define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
9115 #define FLASH_OPTSR_SECURITY_Pos             (21U)
9116 #define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
9117 #define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */
9118 #define FLASH_OPTSR_IO_HSLV_Pos              (29U)
9119 #define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
9120 #define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */
9121 #define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)
9122 #define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
9123 #define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */
9124 #define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)
9125 #define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
9126 #define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */
9127 
9128 /*******************  Bits definition for FLASH_OPTCCR register  *******************/
9129 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)
9130 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
9131 #define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */
9132 
9133 /*******************  Bits definition for FLASH_PRAR register  *********************/
9134 #define FLASH_PRAR_PROT_AREA_START_Pos       (0U)
9135 #define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
9136 #define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */
9137 #define FLASH_PRAR_PROT_AREA_END_Pos         (16U)
9138 #define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
9139 #define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */
9140 #define FLASH_PRAR_DMEP_Pos                  (31U)
9141 #define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */
9142 #define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */
9143 
9144 /*******************  Bits definition for FLASH_SCAR register  *********************/
9145 #define FLASH_SCAR_SEC_AREA_START_Pos        (0U)
9146 #define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
9147 #define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */
9148 #define FLASH_SCAR_SEC_AREA_END_Pos          (16U)
9149 #define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
9150 #define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */
9151 #define FLASH_SCAR_DMES_Pos                  (31U)
9152 #define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */
9153 #define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */
9154 
9155 /*******************  Bits definition for FLASH_WPSN register  *********************/
9156 #define FLASH_WPSN_WRPSN_Pos                 (0U)
9157 #define FLASH_WPSN_WRPSN_Msk                 (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0xFFFFFFFF */
9158 #define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */
9159 
9160 /*******************  Bits definition for FLASH_BOOT_CUR register  ****************/
9161 #define FLASH_BOOT_ADD0_Pos                  (0U)
9162 #define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
9163 #define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */
9164 #define FLASH_BOOT_ADD1_Pos                  (16U)
9165 #define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
9166 #define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */
9167 
9168 
9169 /*******************  Bits definition for FLASH_CRCCR register  ********************/
9170 #define FLASH_CRCCR_CRC_SECT_Pos             (0U)
9171 #define FLASH_CRCCR_CRC_SECT_Msk             (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */
9172 #define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk             /*!< CRC sector number */
9173 #define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)
9174 #define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
9175 #define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */
9176 #define FLASH_CRCCR_ADD_SECT_Pos             (9U)
9177 #define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
9178 #define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */
9179 #define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)
9180 #define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
9181 #define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */
9182 #define FLASH_CRCCR_START_CRC_Pos            (16U)
9183 #define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
9184 #define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */
9185 #define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)
9186 #define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
9187 #define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */
9188 #define FLASH_CRCCR_CRC_BURST_Pos            (20U)
9189 #define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
9190 #define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */
9191 #define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
9192 #define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
9193 #define FLASH_CRCCR_ALL_BANK_Pos             (22U)
9194 #define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
9195 #define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */
9196 
9197 /*******************  Bits definition for FLASH_CRCSADD register  ****************/
9198 #define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)
9199 #define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
9200 #define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */
9201 
9202 /*******************  Bits definition for FLASH_CRCEADD register  ****************/
9203 #define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)
9204 #define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
9205 #define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */
9206 
9207 /*******************  Bits definition for FLASH_CRCDATA register  ***************/
9208 #define FLASH_CRCDATA_CRC_DATA_Pos           (0U)
9209 #define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
9210 #define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */
9211 
9212 /*******************  Bits definition for FLASH_ECC_FA register  *******************/
9213 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)
9214 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */
9215 #define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */
9216 #define FLASH_ECC_FA_OTP_FAIL_ECC_Pos        (31U)
9217 #define FLASH_ECC_FA_OTP_FAIL_ECC_Msk        (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */
9218 #define FLASH_ECC_FA_OTP_FAIL_ECC            FLASH_ECC_FA_OTP_FAIL_ECC_Msk            /*!< OTP ECC error bit */
9219 
9220 /*******************  Bits definition for FLASH_OTPBL register  *******************/
9221 #define FLASH_OTPBL_LOCKBL_Pos               (0U)
9222 #define FLASH_OTPBL_LOCKBL_Msk               (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */
9223 #define FLASH_OTPBL_LOCKBL                   FLASH_OTPBL_LOCKBL_Msk               /*!< OTP Block Lock */
9224 
9225 /******************************************************************************/
9226 /*                                                                            */
9227 /*                          Flexible Memory Controller                        */
9228 /*                                                                            */
9229 /******************************************************************************/
9230 /******************  Bit definition for FMC_BCR1 register  *******************/
9231 #define FMC_BCR1_CCLKEN_Pos        (20U)
9232 #define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
9233 #define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable     */
9234 #define FMC_BCR1_WFDIS_Pos         (21U)
9235 #define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
9236 #define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
9237 
9238 #define FMC_BCR1_BMAP_Pos          (24U)
9239 #define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */
9240 #define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */
9241 #define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */
9242 #define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */
9243 
9244 #define FMC_BCR1_FMCEN_Pos         (31U)
9245 #define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */
9246 #define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */
9247 /******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
9248 #define FMC_BCRx_MBKEN_Pos         (0U)
9249 #define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
9250 #define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
9251 #define FMC_BCRx_MUXEN_Pos         (1U)
9252 #define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
9253 #define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
9254 
9255 #define FMC_BCRx_MTYP_Pos          (2U)
9256 #define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
9257 #define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
9258 #define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
9259 #define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
9260 
9261 #define FMC_BCRx_MWID_Pos          (4U)
9262 #define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
9263 #define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
9264 #define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
9265 #define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
9266 
9267 #define FMC_BCRx_FACCEN_Pos        (6U)
9268 #define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
9269 #define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
9270 #define FMC_BCRx_BURSTEN_Pos       (8U)
9271 #define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
9272 #define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
9273 #define FMC_BCRx_WAITPOL_Pos       (9U)
9274 #define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
9275 #define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
9276 #define FMC_BCRx_WAITCFG_Pos       (11U)
9277 #define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
9278 #define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
9279 #define FMC_BCRx_WREN_Pos          (12U)
9280 #define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
9281 #define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
9282 #define FMC_BCRx_WAITEN_Pos        (13U)
9283 #define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
9284 #define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
9285 #define FMC_BCRx_EXTMOD_Pos        (14U)
9286 #define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
9287 #define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
9288 #define FMC_BCRx_ASYNCWAIT_Pos     (15U)
9289 #define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
9290 #define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
9291 
9292 #define FMC_BCRx_CPSIZE_Pos        (16U)
9293 #define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
9294 #define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */
9295 #define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
9296 #define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
9297 #define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
9298 
9299 #define FMC_BCRx_CBURSTRW_Pos      (19U)
9300 #define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
9301 #define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
9302 
9303 /******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
9304 #define FMC_BTRx_ADDSET_Pos        (0U)
9305 #define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
9306 #define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
9307 #define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
9308 #define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
9309 #define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
9310 #define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
9311 
9312 #define FMC_BTRx_ADDHLD_Pos        (4U)
9313 #define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
9314 #define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
9315 #define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
9316 #define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
9317 #define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
9318 #define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
9319 
9320 #define FMC_BTRx_DATAST_Pos        (8U)
9321 #define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
9322 #define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
9323 #define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
9324 #define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
9325 #define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
9326 #define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
9327 #define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
9328 #define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
9329 #define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
9330 #define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
9331 
9332 #define FMC_BTRx_BUSTURN_Pos       (16U)
9333 #define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
9334 #define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
9335 #define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
9336 #define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
9337 #define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
9338 #define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
9339 
9340 #define FMC_BTRx_CLKDIV_Pos        (20U)
9341 #define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
9342 #define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
9343 #define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
9344 #define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
9345 #define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
9346 #define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
9347 
9348 #define FMC_BTRx_DATLAT_Pos        (24U)
9349 #define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
9350 #define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
9351 #define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
9352 #define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
9353 #define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
9354 #define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
9355 
9356 #define FMC_BTRx_ACCMOD_Pos        (28U)
9357 #define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
9358 #define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
9359 #define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
9360 #define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
9361 
9362 /******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
9363 #define FMC_BWTRx_ADDSET_Pos       (0U)
9364 #define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
9365 #define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
9366 #define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
9367 #define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
9368 #define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
9369 #define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
9370 
9371 #define FMC_BWTRx_ADDHLD_Pos       (4U)
9372 #define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
9373 #define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
9374 #define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
9375 #define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
9376 #define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
9377 #define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
9378 
9379 #define FMC_BWTRx_DATAST_Pos       (8U)
9380 #define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
9381 #define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
9382 #define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
9383 #define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
9384 #define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
9385 #define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
9386 #define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
9387 #define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
9388 #define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
9389 #define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
9390 
9391 #define FMC_BWTRx_BUSTURN_Pos      (16U)
9392 #define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
9393 #define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
9394 #define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
9395 #define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
9396 #define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
9397 #define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
9398 
9399 #define FMC_BWTRx_ACCMOD_Pos       (28U)
9400 #define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
9401 #define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
9402 #define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
9403 #define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
9404 
9405 /******************  Bit definition for FMC_PCR register  *******************/
9406 #define FMC_PCR_PWAITEN_Pos        (1U)
9407 #define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
9408 #define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
9409 #define FMC_PCR_PBKEN_Pos          (2U)
9410 #define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
9411 #define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
9412 
9413 #define FMC_PCR_PWID_Pos           (4U)
9414 #define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
9415 #define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
9416 #define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
9417 #define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
9418 
9419 #define FMC_PCR_ECCEN_Pos          (6U)
9420 #define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
9421 #define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
9422 
9423 #define FMC_PCR_TCLR_Pos           (9U)
9424 #define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
9425 #define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
9426 #define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
9427 #define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
9428 #define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
9429 #define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
9430 
9431 #define FMC_PCR_TAR_Pos            (13U)
9432 #define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
9433 #define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
9434 #define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
9435 #define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
9436 #define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
9437 #define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
9438 
9439 #define FMC_PCR_ECCPS_Pos          (17U)
9440 #define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
9441 #define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
9442 #define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
9443 #define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
9444 #define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
9445 
9446 /*******************  Bit definition for FMC_SR register  *******************/
9447 #define FMC_SR_IRS_Pos             (0U)
9448 #define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
9449 #define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
9450 #define FMC_SR_ILS_Pos             (1U)
9451 #define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
9452 #define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
9453 #define FMC_SR_IFS_Pos             (2U)
9454 #define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
9455 #define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
9456 #define FMC_SR_IREN_Pos            (3U)
9457 #define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
9458 #define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
9459 #define FMC_SR_ILEN_Pos            (4U)
9460 #define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
9461 #define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
9462 #define FMC_SR_IFEN_Pos            (5U)
9463 #define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
9464 #define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
9465 #define FMC_SR_FEMPT_Pos           (6U)
9466 #define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
9467 #define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
9468 
9469 /******************  Bit definition for FMC_PMEM register  ******************/
9470 #define FMC_PMEM_MEMSET_Pos       (0U)
9471 #define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */
9472 #define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */
9473 #define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
9474 #define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
9475 #define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
9476 #define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
9477 #define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
9478 #define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
9479 #define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
9480 #define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
9481 
9482 #define FMC_PMEM_MEMWAIT_Pos      (8U)
9483 #define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */
9484 #define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */
9485 #define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
9486 #define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
9487 #define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
9488 #define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
9489 #define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
9490 #define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
9491 #define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
9492 #define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
9493 
9494 #define FMC_PMEM_MEMHOLD_Pos      (16U)
9495 #define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */
9496 #define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */
9497 #define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
9498 #define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
9499 #define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
9500 #define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
9501 #define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
9502 #define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
9503 #define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
9504 #define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
9505 
9506 #define FMC_PMEM_MEMHIZ_Pos       (24U)
9507 #define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */
9508 #define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
9509 #define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
9510 #define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
9511 #define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
9512 #define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
9513 #define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
9514 #define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
9515 #define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
9516 #define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
9517 
9518 /******************  Bit definition for FMC_PATT register  ******************/
9519 #define FMC_PATT_ATTSET_Pos       (0U)
9520 #define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */
9521 #define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */
9522 #define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
9523 #define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
9524 #define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
9525 #define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
9526 #define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
9527 #define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
9528 #define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
9529 #define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
9530 
9531 #define FMC_PATT_ATTWAIT_Pos      (8U)
9532 #define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */
9533 #define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
9534 #define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
9535 #define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
9536 #define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
9537 #define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
9538 #define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
9539 #define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
9540 #define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
9541 #define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
9542 
9543 #define FMC_PATT_ATTHOLD_Pos      (16U)
9544 #define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */
9545 #define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
9546 #define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
9547 #define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
9548 #define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
9549 #define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
9550 #define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
9551 #define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
9552 #define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
9553 #define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
9554 
9555 #define FMC_PATT_ATTHIZ_Pos       (24U)
9556 #define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */
9557 #define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
9558 #define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
9559 #define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
9560 #define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
9561 #define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
9562 #define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
9563 #define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
9564 #define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
9565 #define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
9566 
9567 /******************  Bit definition for FMC_ECCR3 register  ******************/
9568 #define FMC_ECCR3_ECC3_Pos         (0U)
9569 #define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
9570 #define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */
9571 
9572 /******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
9573 #define FMC_SDCRx_NC_Pos           (0U)
9574 #define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
9575 #define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
9576 #define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */
9577 #define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */
9578 
9579 #define FMC_SDCRx_NR_Pos           (2U)
9580 #define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
9581 #define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
9582 #define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */
9583 #define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */
9584 
9585 #define FMC_SDCRx_MWID_Pos         (4U)
9586 #define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
9587 #define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
9588 #define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */
9589 #define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */
9590 
9591 #define FMC_SDCRx_NB_Pos           (6U)
9592 #define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
9593 #define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */
9594 
9595 #define FMC_SDCRx_CAS_Pos          (7U)
9596 #define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
9597 #define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
9598 #define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */
9599 #define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */
9600 
9601 #define FMC_SDCRx_WP_Pos           (9U)
9602 #define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
9603 #define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */
9604 
9605 #define FMC_SDCRx_SDCLK_Pos        (10U)
9606 #define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
9607 #define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */
9608 #define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */
9609 #define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */
9610 
9611 #define FMC_SDCRx_RBURST_Pos       (12U)
9612 #define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
9613 #define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */
9614 
9615 #define FMC_SDCRx_RPIPE_Pos        (13U)
9616 #define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
9617 #define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */
9618 #define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */
9619 #define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */
9620 
9621 /******************  Bit definition for FMC_SDTRx(1,2) register  ******************/
9622 #define FMC_SDTRx_TMRD_Pos         (0U)
9623 #define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
9624 #define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
9625 #define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */
9626 #define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */
9627 #define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */
9628 #define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */
9629 
9630 #define FMC_SDTRx_TXSR_Pos         (4U)
9631 #define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
9632 #define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
9633 #define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */
9634 #define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */
9635 #define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */
9636 #define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */
9637 
9638 #define FMC_SDTRx_TRAS_Pos         (8U)
9639 #define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
9640 #define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
9641 #define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */
9642 #define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */
9643 #define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */
9644 #define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */
9645 
9646 #define FMC_SDTRx_TRC_Pos          (12U)
9647 #define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
9648 #define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
9649 #define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */
9650 #define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */
9651 #define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */
9652 
9653 #define FMC_SDTRx_TWR_Pos          (16U)
9654 #define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
9655 #define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
9656 #define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */
9657 #define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */
9658 #define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */
9659 
9660 #define FMC_SDTRx_TRP_Pos          (20U)
9661 #define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
9662 #define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
9663 #define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */
9664 #define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */
9665 #define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */
9666 
9667 #define FMC_SDTRx_TRCD_Pos         (24U)
9668 #define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
9669 #define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
9670 #define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */
9671 #define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */
9672 #define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */
9673 
9674 /******************  Bit definition for FMC_SDCMR register  ******************/
9675 #define FMC_SDCMR_MODE_Pos         (0U)
9676 #define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
9677 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
9678 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
9679 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
9680 #define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
9681 
9682 #define FMC_SDCMR_CTB2_Pos         (3U)
9683 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
9684 #define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
9685 
9686 #define FMC_SDCMR_CTB1_Pos         (4U)
9687 #define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
9688 #define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
9689 
9690 #define FMC_SDCMR_NRFS_Pos         (5U)
9691 #define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
9692 #define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
9693 #define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
9694 #define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
9695 #define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
9696 #define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
9697 
9698 #define FMC_SDCMR_MRD_Pos          (9U)
9699 #define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
9700 #define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
9701 
9702 /******************  Bit definition for FMC_SDRTR register  ******************/
9703 #define FMC_SDRTR_CRE_Pos          (0U)
9704 #define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
9705 #define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
9706 
9707 #define FMC_SDRTR_COUNT_Pos        (1U)
9708 #define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
9709 #define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
9710 
9711 #define FMC_SDRTR_REIE_Pos         (14U)
9712 #define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
9713 #define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interrupt enable */
9714 
9715 /******************  Bit definition for FMC_SDSR register  ******************/
9716 #define FMC_SDSR_RE_Pos            (0U)
9717 #define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
9718 #define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
9719 
9720 #define FMC_SDSR_MODES1_Pos        (1U)
9721 #define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
9722 #define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
9723 #define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
9724 #define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
9725 
9726 #define FMC_SDSR_MODES2_Pos        (3U)
9727 #define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
9728 #define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
9729 #define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
9730 #define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
9731 
9732 /******************************************************************************/
9733 /*                                                                            */
9734 /*                       Graphic MMU (GFXMMU)                                 */
9735 /*                                                                            */
9736 /******************************************************************************/
9737 /****************** Bits definition for GFXMMU_CR register ********************/
9738 #define GFXMMU_CR_B0OIE_Pos                (0U)
9739 #define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)       /*!< 0x00000001 */
9740 #define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */
9741 #define GFXMMU_CR_B1OIE_Pos                (1U)
9742 #define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)       /*!< 0x00000002 */
9743 #define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */
9744 #define GFXMMU_CR_B2OIE_Pos                (2U)
9745 #define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)       /*!< 0x00000004 */
9746 #define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */
9747 #define GFXMMU_CR_B3OIE_Pos                (3U)
9748 #define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)       /*!< 0x00000008 */
9749 #define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */
9750 #define GFXMMU_CR_AMEIE_Pos                (4U)
9751 #define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)       /*!< 0x00000010 */
9752 #define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */
9753 #define GFXMMU_CR_192BM_Pos                (6U)
9754 #define GFXMMU_CR_192BM_Msk                (0x1UL << GFXMMU_CR_192BM_Pos)       /*!< 0x00000040 */
9755 #define GFXMMU_CR_192BM                    GFXMMU_CR_192BM_Msk                 /*!< 192 block mode */
9756 #define GFXMMU_CR_CE_Pos                   (7U)
9757 #define GFXMMU_CR_CE_Msk                   (0x1UL << GFXMMU_CR_CE_Pos)          /*!< 0x00000080 */
9758 #define GFXMMU_CR_CE                       GFXMMU_CR_CE_Msk                    /*!< Cache Enable */
9759 #define GFXMMU_CR_CL_Pos                   (8U)
9760 #define GFXMMU_CR_CL_Msk                   (0x1UL << GFXMMU_CR_CL_Pos)          /*!< 0x00000100 */
9761 #define GFXMMU_CR_CL                       GFXMMU_CR_CL_Msk                    /*!< Cache Lock */
9762 #define GFXMMU_CR_CLB_Pos                  (9U)
9763 #define GFXMMU_CR_CLB_Msk                  (0x3UL << GFXMMU_CR_CLB_Pos)         /*!< 0x00000600 */
9764 #define GFXMMU_CR_CLB                      GFXMMU_CR_CLB_Msk                   /*!< CLB[1:0]: Cache Lock Buffer */
9765 #define GFXMMU_CR_CLB_0                    (0x1UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 1 */
9766 #define GFXMMU_CR_CLB_1                    (0x2UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 2 */
9767 #define GFXMMU_CR_FC_Pos                   (11U)
9768 #define GFXMMU_CR_FC_Msk                   (0x1UL << GFXMMU_CR_FC_Pos)          /*!< 0x00000800 */
9769 #define GFXMMU_CR_FC                       GFXMMU_CR_FC_Msk                    /*!< Force Caching */
9770 #define GFXMMU_CR_PD_Pos                   (12U)
9771 #define GFXMMU_CR_PD_Msk                   (0x1UL << GFXMMU_CR_PD_Pos)          /*!< 0x00001000 */
9772 #define GFXMMU_CR_PD                       GFXMMU_CR_PD_Msk                    /*!< Prefetch Disable */
9773 #define GFXMMU_CR_OC_Pos                   (16U)
9774 #define GFXMMU_CR_OC_Msk                   (0x1UL << GFXMMU_CR_OC_Pos)          /*!< 0x00002000 */
9775 #define GFXMMU_CR_OC                       GFXMMU_CR_OC_Msk                    /*!< Outer Cachability */
9776 #define GFXMMU_CR_OB_Pos                   (17U)
9777 #define GFXMMU_CR_OB_Msk                   (0x1UL << GFXMMU_CR_OB_Pos)          /*!< 0x00002000 */
9778 #define GFXMMU_CR_OB                       GFXMMU_CR_OB_Msk                    /*!< Outer Bufferability */
9779 
9780 /****************** Bits definition for GFXMMU_SR register ********************/
9781 #define GFXMMU_SR_B0OF_Pos                 (0U)
9782 #define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)        /*!< 0x00000001 */
9783 #define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */
9784 #define GFXMMU_SR_B1OF_Pos                 (1U)
9785 #define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)        /*!< 0x00000002 */
9786 #define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */
9787 #define GFXMMU_SR_B2OF_Pos                 (2U)
9788 #define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)        /*!< 0x00000004 */
9789 #define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */
9790 #define GFXMMU_SR_B3OF_Pos                 (3U)
9791 #define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)        /*!< 0x00000008 */
9792 #define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */
9793 #define GFXMMU_SR_AMEF_Pos                 (4U)
9794 #define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)        /*!< 0x00000010 */
9795 #define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AHB master error flag */
9796 
9797 /****************** Bits definition for GFXMMU_FCR register *******************/
9798 #define GFXMMU_FCR_CB0OF_Pos               (0U)
9799 #define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)      /*!< 0x00000001 */
9800 #define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */
9801 #define GFXMMU_FCR_CB1OF_Pos               (1U)
9802 #define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)      /*!< 0x00000002 */
9803 #define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */
9804 #define GFXMMU_FCR_CB2OF_Pos               (2U)
9805 #define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)      /*!< 0x00000004 */
9806 #define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */
9807 #define GFXMMU_FCR_CB3OF_Pos               (3U)
9808 #define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)      /*!< 0x00000008 */
9809 #define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */
9810 #define GFXMMU_FCR_CAMEF_Pos               (4U)
9811 #define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)      /*!< 0x00000010 */
9812 #define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */
9813 
9814 /****************** Bits definition for GFXMMU_CCR register *******************/
9815 #define GFXMMU_CCR_FF_Pos                  (0U)
9816 #define GFXMMU_CCR_FF_Msk                  (0x1UL << GFXMMU_CCR_FF_Pos)         /*!< 0x00000001 */
9817 #define GFXMMU_CCR_FF                      GFXMMU_CCR_FF_Msk                   /*!< Clear buffer 0 overflow flag */
9818 #define GFXMMU_CCR_FI_Pos                  (1U)
9819 #define GFXMMU_CCR_FI_Msk                  (0x1UL << GFXMMU_CCR_FI_Pos)         /*!< 0x00000002 */
9820 #define GFXMMU_CCR_FI                      GFXMMU_CCR_FI_Msk                   /*!< Clear buffer 1 overflow flag */
9821 
9822 /****************** Bits definition for GFXMMU_DVR register *******************/
9823 #define GFXMMU_DVR_DV_Pos                  (0U)
9824 #define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)  /*!< 0xFFFFFFFF */
9825 #define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */
9826 
9827 /****************** Bits definition for GFXMMU_B0CR register ******************/
9828 #define GFXMMU_B0CR_PBO_Pos                (4U)
9829 #define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)   /*!< 0x007FFFF0 */
9830 #define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
9831 #define GFXMMU_B0CR_PBBA_Pos               (23U)
9832 #define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)    /*!< 0xFF800000 */
9833 #define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
9834 
9835 /****************** Bits definition for GFXMMU_B1CR register ******************/
9836 #define GFXMMU_B1CR_PBO_Pos                (4U)
9837 #define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)   /*!< 0x007FFFF0 */
9838 #define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
9839 #define GFXMMU_B1CR_PBBA_Pos               (23U)
9840 #define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)    /*!< 0xFF800000 */
9841 #define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
9842 
9843 /****************** Bits definition for GFXMMU_B2CR register ******************/
9844 #define GFXMMU_B2CR_PBO_Pos                (4U)
9845 #define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)   /*!< 0x007FFFF0 */
9846 #define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
9847 #define GFXMMU_B2CR_PBBA_Pos               (23U)
9848 #define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)    /*!< 0xFF800000 */
9849 #define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
9850 
9851 /****************** Bits definition for GFXMMU_B3CR register ******************/
9852 #define GFXMMU_B3CR_PBO_Pos                (4U)
9853 #define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)   /*!< 0x007FFFF0 */
9854 #define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
9855 #define GFXMMU_B3CR_PBBA_Pos               (23U)
9856 #define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)    /*!< 0xFF800000 */
9857 #define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
9858 
9859 /****************** Bits definition for GFXMMU_LUTxL register *****************/
9860 #define GFXMMU_LUTxL_EN_Pos                (0U)
9861 #define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)       /*!< 0x00000001 */
9862 #define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */
9863 #define GFXMMU_LUTxL_FVB_Pos               (8U)
9864 #define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)     /*!< 0x0000FF00 */
9865 #define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */
9866 #define GFXMMU_LUTxL_LVB_Pos               (16U)
9867 #define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)     /*!< 0x00FF0000 */
9868 #define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */
9869 
9870 /****************** Bits definition for GFXMMU_LUTxH register *****************/
9871 #define GFXMMU_LUTxH_LO_Pos                (4U)
9872 #define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)   /*!< 0x003FFFF0 */
9873 #define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[21:4] bits (Line offset) */
9874 
9875 /******************************************************************************/
9876 /*                                                                            */
9877 /*                            General Purpose I/O                             */
9878 /*                                                                            */
9879 /******************************************************************************/
9880 /******************  Bits definition for GPIO_MODER register  *****************/
9881 #define GPIO_MODER_MODER0_Pos           (0U)
9882 #define GPIO_MODER_MODER0_Msk           (0x3UL << GPIO_MODER_MODER0_Pos)         /*!< 0x00000003 */
9883 #define GPIO_MODER_MODER0               GPIO_MODER_MODER0_Msk
9884 #define GPIO_MODER_MODER0_0             (0x1UL << GPIO_MODER_MODER0_Pos)          /*!< 0x00000001 */
9885 #define GPIO_MODER_MODER0_1             (0x2UL << GPIO_MODER_MODER0_Pos)          /*!< 0x00000002 */
9886 
9887 #define GPIO_MODER_MODER1_Pos           (2U)
9888 #define GPIO_MODER_MODER1_Msk           (0x3UL << GPIO_MODER_MODER1_Pos)         /*!< 0x0000000C */
9889 #define GPIO_MODER_MODER1               GPIO_MODER_MODER1_Msk
9890 #define GPIO_MODER_MODER1_0             (0x1UL << GPIO_MODER_MODER1_Pos)          /*!< 0x00000004 */
9891 #define GPIO_MODER_MODER1_1             (0x2UL << GPIO_MODER_MODER1_Pos)          /*!< 0x00000008 */
9892 
9893 #define GPIO_MODER_MODER2_Pos           (4U)
9894 #define GPIO_MODER_MODER2_Msk           (0x3UL << GPIO_MODER_MODER2_Pos)         /*!< 0x00000030 */
9895 #define GPIO_MODER_MODER2               GPIO_MODER_MODER2_Msk
9896 #define GPIO_MODER_MODER2_0             (0x1UL << GPIO_MODER_MODER2_Pos)          /*!< 0x00000010 */
9897 #define GPIO_MODER_MODER2_1             (0x2UL << GPIO_MODER_MODER2_Pos)          /*!< 0x00000020 */
9898 
9899 #define GPIO_MODER_MODER3_Pos           (6U)
9900 #define GPIO_MODER_MODER3_Msk           (0x3UL << GPIO_MODER_MODER3_Pos)         /*!< 0x000000C0 */
9901 #define GPIO_MODER_MODER3               GPIO_MODER_MODER3_Msk
9902 #define GPIO_MODER_MODER3_0             (0x1UL << GPIO_MODER_MODER3_Pos)          /*!< 0x00000040 */
9903 #define GPIO_MODER_MODER3_1             (0x2UL << GPIO_MODER_MODER3_Pos)          /*!< 0x00000080 */
9904 
9905 #define GPIO_MODER_MODER4_Pos           (8U)
9906 #define GPIO_MODER_MODER4_Msk           (0x3UL << GPIO_MODER_MODER4_Pos)         /*!< 0x00000300 */
9907 #define GPIO_MODER_MODER4               GPIO_MODER_MODER4_Msk
9908 #define GPIO_MODER_MODER4_0             (0x1UL << GPIO_MODER_MODER4_Pos)          /*!< 0x00000100 */
9909 #define GPIO_MODER_MODER4_1             (0x2UL << GPIO_MODER_MODER4_Pos)          /*!< 0x00000200 */
9910 
9911 #define GPIO_MODER_MODER5_Pos           (10U)
9912 #define GPIO_MODER_MODER5_Msk           (0x3UL << GPIO_MODER_MODER5_Pos)         /*!< 0x00000C00 */
9913 #define GPIO_MODER_MODER5               GPIO_MODER_MODER5_Msk
9914 #define GPIO_MODER_MODER5_0             (0x1UL << GPIO_MODER_MODER5_Pos)          /*!< 0x00000400 */
9915 #define GPIO_MODER_MODER5_1             (0x2UL << GPIO_MODER_MODER5_Pos)          /*!< 0x00000800 */
9916 
9917 #define GPIO_MODER_MODER6_Pos           (12U)
9918 #define GPIO_MODER_MODER6_Msk           (0x3UL << GPIO_MODER_MODER6_Pos)         /*!< 0x00003000 */
9919 #define GPIO_MODER_MODER6               GPIO_MODER_MODER6_Msk
9920 #define GPIO_MODER_MODER6_0             (0x1UL << GPIO_MODER_MODER6_Pos)          /*!< 0x00001000 */
9921 #define GPIO_MODER_MODER6_1             (0x2UL << GPIO_MODER_MODER6_Pos)          /*!< 0x00002000 */
9922 
9923 #define GPIO_MODER_MODER7_Pos           (14U)
9924 #define GPIO_MODER_MODER7_Msk           (0x3UL << GPIO_MODER_MODER7_Pos)         /*!< 0x0000C000 */
9925 #define GPIO_MODER_MODER7               GPIO_MODER_MODER7_Msk
9926 #define GPIO_MODER_MODER7_0             (0x1UL << GPIO_MODER_MODER7_Pos)          /*!< 0x00004000 */
9927 #define GPIO_MODER_MODER7_1             (0x2UL << GPIO_MODER_MODER7_Pos)          /*!< 0x00008000 */
9928 
9929 #define GPIO_MODER_MODER8_Pos           (16U)
9930 #define GPIO_MODER_MODER8_Msk           (0x3UL << GPIO_MODER_MODER8_Pos)         /*!< 0x00030000 */
9931 #define GPIO_MODER_MODER8               GPIO_MODER_MODER8_Msk
9932 #define GPIO_MODER_MODER8_0             (0x1UL << GPIO_MODER_MODER8_Pos)          /*!< 0x00010000 */
9933 #define GPIO_MODER_MODER8_1             (0x2UL << GPIO_MODER_MODER8_Pos)          /*!< 0x00020000 */
9934 
9935 #define GPIO_MODER_MODER9_Pos           (18U)
9936 #define GPIO_MODER_MODER9_Msk           (0x3UL << GPIO_MODER_MODER9_Pos)         /*!< 0x000C0000 */
9937 #define GPIO_MODER_MODER9               GPIO_MODER_MODER9_Msk
9938 #define GPIO_MODER_MODER9_0             (0x1UL << GPIO_MODER_MODER9_Pos)          /*!< 0x00040000 */
9939 #define GPIO_MODER_MODER9_1             (0x2UL << GPIO_MODER_MODER9_Pos)          /*!< 0x00080000 */
9940 
9941 #define GPIO_MODER_MODER10_Pos          (20U)
9942 #define GPIO_MODER_MODER10_Msk          (0x3UL << GPIO_MODER_MODER10_Pos)        /*!< 0x00300000 */
9943 #define GPIO_MODER_MODER10              GPIO_MODER_MODER10_Msk
9944 #define GPIO_MODER_MODER10_0            (0x1UL << GPIO_MODER_MODER10_Pos)         /*!< 0x00100000 */
9945 #define GPIO_MODER_MODER10_1            (0x2UL << GPIO_MODER_MODER10_Pos)         /*!< 0x00200000 */
9946 
9947 #define GPIO_MODER_MODER11_Pos          (22U)
9948 #define GPIO_MODER_MODER11_Msk          (0x3UL << GPIO_MODER_MODER11_Pos)        /*!< 0x00C00000 */
9949 #define GPIO_MODER_MODER11              GPIO_MODER_MODER11_Msk
9950 #define GPIO_MODER_MODER11_0            (0x1UL << GPIO_MODER_MODER11_Pos)         /*!< 0x00400000 */
9951 #define GPIO_MODER_MODER11_1            (0x2UL << GPIO_MODER_MODER11_Pos)         /*!< 0x00800000 */
9952 
9953 #define GPIO_MODER_MODER12_Pos          (24U)
9954 #define GPIO_MODER_MODER12_Msk          (0x3UL << GPIO_MODER_MODER12_Pos)        /*!< 0x03000000 */
9955 #define GPIO_MODER_MODER12              GPIO_MODER_MODER12_Msk
9956 #define GPIO_MODER_MODER12_0            (0x1UL << GPIO_MODER_MODER12_Pos)         /*!< 0x01000000 */
9957 #define GPIO_MODER_MODER12_1            (0x2UL << GPIO_MODER_MODER12_Pos)         /*!< 0x02000000 */
9958 
9959 #define GPIO_MODER_MODER13_Pos          (26U)
9960 #define GPIO_MODER_MODER13_Msk          (0x3UL << GPIO_MODER_MODER13_Pos)        /*!< 0x0C000000 */
9961 #define GPIO_MODER_MODER13              GPIO_MODER_MODER13_Msk
9962 #define GPIO_MODER_MODER13_0            (0x1UL << GPIO_MODER_MODER13_Pos)         /*!< 0x04000000 */
9963 #define GPIO_MODER_MODER13_1            (0x2UL << GPIO_MODER_MODER13_Pos)         /*!< 0x08000000 */
9964 
9965 #define GPIO_MODER_MODER14_Pos          (28U)
9966 #define GPIO_MODER_MODER14_Msk          (0x3UL << GPIO_MODER_MODER14_Pos)        /*!< 0x30000000 */
9967 #define GPIO_MODER_MODER14              GPIO_MODER_MODER14_Msk
9968 #define GPIO_MODER_MODER14_0            (0x1UL << GPIO_MODER_MODER14_Pos)         /*!< 0x10000000 */
9969 #define GPIO_MODER_MODER14_1            (0x2UL << GPIO_MODER_MODER14_Pos)         /*!< 0x20000000 */
9970 
9971 #define GPIO_MODER_MODER15_Pos          (30U)
9972 #define GPIO_MODER_MODER15_Msk          (0x3UL << GPIO_MODER_MODER15_Pos)        /*!< 0xC0000000 */
9973 #define GPIO_MODER_MODER15              GPIO_MODER_MODER15_Msk
9974 #define GPIO_MODER_MODER15_0            (0x1UL << GPIO_MODER_MODER15_Pos)         /*!< 0x40000000 */
9975 #define GPIO_MODER_MODER15_1            (0x2UL << GPIO_MODER_MODER15_Pos)         /*!< 0x80000000 */
9976 
9977 /* Legacy Defines */
9978 #define GPIO_MODER_MODE0_Pos           GPIO_MODER_MODER0_Pos
9979 #define GPIO_MODER_MODE0_Msk           GPIO_MODER_MODER0_Msk
9980 #define GPIO_MODER_MODE0               GPIO_MODER_MODER0
9981 #define GPIO_MODER_MODE0_0             GPIO_MODER_MODER0_0
9982 #define GPIO_MODER_MODE0_1             GPIO_MODER_MODER0_1
9983 
9984 #define GPIO_MODER_MODE1_Pos           GPIO_MODER_MODER1_Pos
9985 #define GPIO_MODER_MODE1_Msk           GPIO_MODER_MODER1_Msk
9986 #define GPIO_MODER_MODE1               GPIO_MODER_MODER1
9987 #define GPIO_MODER_MODE1_0             GPIO_MODER_MODER1_0
9988 #define GPIO_MODER_MODE1_1             GPIO_MODER_MODER1_1
9989 
9990 #define GPIO_MODER_MODE2_Pos           GPIO_MODER_MODER2_Pos
9991 #define GPIO_MODER_MODE2_Msk           GPIO_MODER_MODER2_Msk
9992 #define GPIO_MODER_MODE2               GPIO_MODER_MODER2
9993 #define GPIO_MODER_MODE2_0             GPIO_MODER_MODER2_0
9994 #define GPIO_MODER_MODE2_1             GPIO_MODER_MODER2_1
9995 
9996 #define GPIO_MODER_MODE3_Pos           GPIO_MODER_MODER3_Pos
9997 #define GPIO_MODER_MODE3_Msk           GPIO_MODER_MODER3_Msk
9998 #define GPIO_MODER_MODE3               GPIO_MODER_MODER3
9999 #define GPIO_MODER_MODE3_0             GPIO_MODER_MODER3_0
10000 #define GPIO_MODER_MODE3_1             GPIO_MODER_MODER3_1
10001 
10002 #define GPIO_MODER_MODE4_Pos           GPIO_MODER_MODER4_Pos
10003 #define GPIO_MODER_MODE4_Msk           GPIO_MODER_MODER4_Msk
10004 #define GPIO_MODER_MODE4               GPIO_MODER_MODER4
10005 #define GPIO_MODER_MODE4_0             GPIO_MODER_MODER4_0
10006 #define GPIO_MODER_MODE4_1             GPIO_MODER_MODER4_1
10007 
10008 #define GPIO_MODER_MODE5_Pos           GPIO_MODER_MODER5_Pos
10009 #define GPIO_MODER_MODE5_Msk           GPIO_MODER_MODER5_Msk
10010 #define GPIO_MODER_MODE5               GPIO_MODER_MODER5
10011 #define GPIO_MODER_MODE5_0             GPIO_MODER_MODER5_0
10012 #define GPIO_MODER_MODE5_1             GPIO_MODER_MODER5_1
10013 
10014 #define GPIO_MODER_MODE6_Pos           GPIO_MODER_MODER6_Pos
10015 #define GPIO_MODER_MODE6_Msk           GPIO_MODER_MODER6_Msk
10016 #define GPIO_MODER_MODE6               GPIO_MODER_MODER6
10017 #define GPIO_MODER_MODE6_0             GPIO_MODER_MODER6_0
10018 #define GPIO_MODER_MODE6_1             GPIO_MODER_MODER6_1
10019 
10020 #define GPIO_MODER_MODE7_Pos           GPIO_MODER_MODER7_Pos
10021 #define GPIO_MODER_MODE7_Msk           GPIO_MODER_MODER7_Msk
10022 #define GPIO_MODER_MODE7               GPIO_MODER_MODER7
10023 #define GPIO_MODER_MODE7_0             GPIO_MODER_MODER7_0
10024 #define GPIO_MODER_MODE7_1             GPIO_MODER_MODER7_1
10025 
10026 #define GPIO_MODER_MODE8_Pos           GPIO_MODER_MODER8_Pos
10027 #define GPIO_MODER_MODE8_Msk           GPIO_MODER_MODER8_Msk
10028 #define GPIO_MODER_MODE8               GPIO_MODER_MODER8
10029 #define GPIO_MODER_MODE8_0             GPIO_MODER_MODER8_0
10030 #define GPIO_MODER_MODE8_1             GPIO_MODER_MODER8_1
10031 
10032 #define GPIO_MODER_MODE9_Pos           GPIO_MODER_MODER9_Pos
10033 #define GPIO_MODER_MODE9_Msk           GPIO_MODER_MODER9_Msk
10034 #define GPIO_MODER_MODE9               GPIO_MODER_MODER9
10035 #define GPIO_MODER_MODE9_0             GPIO_MODER_MODER9_0
10036 #define GPIO_MODER_MODE9_1             GPIO_MODER_MODER9_1
10037 
10038 #define GPIO_MODER_MODE10_Pos          GPIO_MODER_MODER10_Po
10039 #define GPIO_MODER_MODE10_Msk          GPIO_MODER_MODER10_Ms
10040 #define GPIO_MODER_MODE10              GPIO_MODER_MODER10
10041 #define GPIO_MODER_MODE10_0            GPIO_MODER_MODER10_0
10042 #define GPIO_MODER_MODE10_1            GPIO_MODER_MODER10_1
10043 
10044 #define GPIO_MODER_MODE11_Pos          GPIO_MODER_MODER11_Po
10045 #define GPIO_MODER_MODE11_Msk          GPIO_MODER_MODER11_Ms
10046 #define GPIO_MODER_MODE11              GPIO_MODER_MODER11
10047 #define GPIO_MODER_MODE11_0            GPIO_MODER_MODER11_0
10048 #define GPIO_MODER_MODE11_1            GPIO_MODER_MODER11_1
10049 
10050 #define GPIO_MODER_MODE12_Pos          GPIO_MODER_MODER12_Po
10051 #define GPIO_MODER_MODE12_Msk          GPIO_MODER_MODER12_Ms
10052 #define GPIO_MODER_MODE12              GPIO_MODER_MODER12
10053 #define GPIO_MODER_MODE12_0            GPIO_MODER_MODER12_0
10054 #define GPIO_MODER_MODE12_1            GPIO_MODER_MODER12_1
10055 
10056 #define GPIO_MODER_MODE13_Pos          GPIO_MODER_MODER13_Po
10057 #define GPIO_MODER_MODE13_Msk          GPIO_MODER_MODER13_Ms
10058 #define GPIO_MODER_MODE13              GPIO_MODER_MODER13
10059 #define GPIO_MODER_MODE13_0            GPIO_MODER_MODER13_0
10060 #define GPIO_MODER_MODE13_1            GPIO_MODER_MODER13_1
10061 
10062 #define GPIO_MODER_MODE14_Pos          GPIO_MODER_MODER14_Po
10063 #define GPIO_MODER_MODE14_Msk          GPIO_MODER_MODER14_Ms
10064 #define GPIO_MODER_MODE14              GPIO_MODER_MODER14
10065 #define GPIO_MODER_MODE14_0            GPIO_MODER_MODER14_0
10066 #define GPIO_MODER_MODE14_1            GPIO_MODER_MODER14_1
10067 
10068 #define GPIO_MODER_MODE15_Pos          GPIO_MODER_MODER15_Po
10069 #define GPIO_MODER_MODE15_Msk          GPIO_MODER_MODER15_Ms
10070 #define GPIO_MODER_MODE15              GPIO_MODER_MODER15
10071 #define GPIO_MODER_MODE15_0            GPIO_MODER_MODER15_0
10072 #define GPIO_MODER_MODE15_1            GPIO_MODER_MODER15_1
10073 
10074 /******************  Bits definition for GPIO_OTYPER register  ****************/
10075 #define GPIO_OTYPER_OT0_Pos            (0U)
10076 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
10077 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
10078 #define GPIO_OTYPER_OT1_Pos            (1U)
10079 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
10080 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
10081 #define GPIO_OTYPER_OT2_Pos            (2U)
10082 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
10083 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
10084 #define GPIO_OTYPER_OT3_Pos            (3U)
10085 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
10086 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
10087 #define GPIO_OTYPER_OT4_Pos            (4U)
10088 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
10089 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
10090 #define GPIO_OTYPER_OT5_Pos            (5U)
10091 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
10092 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
10093 #define GPIO_OTYPER_OT6_Pos            (6U)
10094 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
10095 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
10096 #define GPIO_OTYPER_OT7_Pos            (7U)
10097 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
10098 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
10099 #define GPIO_OTYPER_OT8_Pos            (8U)
10100 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
10101 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
10102 #define GPIO_OTYPER_OT9_Pos            (9U)
10103 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
10104 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
10105 #define GPIO_OTYPER_OT10_Pos           (10U)
10106 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
10107 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
10108 #define GPIO_OTYPER_OT11_Pos           (11U)
10109 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
10110 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
10111 #define GPIO_OTYPER_OT12_Pos           (12U)
10112 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
10113 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
10114 #define GPIO_OTYPER_OT13_Pos           (13U)
10115 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
10116 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
10117 #define GPIO_OTYPER_OT14_Pos           (14U)
10118 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
10119 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
10120 #define GPIO_OTYPER_OT15_Pos           (15U)
10121 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
10122 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
10123 
10124 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
10125 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
10126 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
10127 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
10128 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
10129 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
10130 
10131 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
10132 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
10133 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
10134 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
10135 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
10136 
10137 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
10138 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
10139 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
10140 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
10141 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
10142 
10143 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
10144 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
10145 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
10146 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
10147 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
10148 
10149 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
10150 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
10151 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
10152 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
10153 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
10154 
10155 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
10156 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
10157 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
10158 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
10159 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
10160 
10161 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
10162 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
10163 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
10164 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
10165 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
10166 
10167 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
10168 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
10169 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
10170 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
10171 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
10172 
10173 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
10174 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
10175 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
10176 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
10177 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
10178 
10179 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
10180 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
10181 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
10182 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
10183 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
10184 
10185 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
10186 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
10187 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
10188 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
10189 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
10190 
10191 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
10192 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
10193 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
10194 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
10195 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
10196 
10197 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
10198 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
10199 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
10200 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
10201 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
10202 
10203 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
10204 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
10205 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
10206 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
10207 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
10208 
10209 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
10210 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
10211 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
10212 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
10213 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
10214 
10215 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
10216 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
10217 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
10218 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
10219 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
10220 
10221 /******************  Bits definition for GPIO_PUPDR register  *****************/
10222 #define GPIO_PUPDR_PUPD0_Pos           (0U)
10223 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
10224 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
10225 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
10226 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
10227 
10228 #define GPIO_PUPDR_PUPD1_Pos           (2U)
10229 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
10230 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
10231 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
10232 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
10233 
10234 #define GPIO_PUPDR_PUPD2_Pos           (4U)
10235 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
10236 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
10237 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
10238 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
10239 
10240 #define GPIO_PUPDR_PUPD3_Pos           (6U)
10241 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
10242 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
10243 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
10244 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
10245 
10246 #define GPIO_PUPDR_PUPD4_Pos           (8U)
10247 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
10248 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
10249 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
10250 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
10251 
10252 #define GPIO_PUPDR_PUPD5_Pos           (10U)
10253 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
10254 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
10255 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
10256 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
10257 
10258 #define GPIO_PUPDR_PUPD6_Pos           (12U)
10259 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
10260 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
10261 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
10262 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
10263 
10264 #define GPIO_PUPDR_PUPD7_Pos           (14U)
10265 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
10266 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
10267 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
10268 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
10269 
10270 #define GPIO_PUPDR_PUPD8_Pos           (16U)
10271 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
10272 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
10273 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
10274 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
10275 
10276 #define GPIO_PUPDR_PUPD9_Pos           (18U)
10277 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
10278 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
10279 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
10280 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
10281 
10282 #define GPIO_PUPDR_PUPD10_Pos          (20U)
10283 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
10284 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
10285 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
10286 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
10287 
10288 #define GPIO_PUPDR_PUPD11_Pos          (22U)
10289 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
10290 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
10291 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
10292 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
10293 
10294 #define GPIO_PUPDR_PUPD12_Pos          (24U)
10295 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
10296 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
10297 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
10298 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
10299 
10300 #define GPIO_PUPDR_PUPD13_Pos          (26U)
10301 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
10302 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
10303 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
10304 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
10305 
10306 #define GPIO_PUPDR_PUPD14_Pos          (28U)
10307 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
10308 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
10309 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
10310 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
10311 
10312 #define GPIO_PUPDR_PUPD15_Pos          (30U)
10313 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
10314 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
10315 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
10316 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
10317 
10318 /******************  Bits definition for GPIO_IDR register  *******************/
10319 #define GPIO_IDR_ID0_Pos               (0U)
10320 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
10321 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
10322 #define GPIO_IDR_ID1_Pos               (1U)
10323 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
10324 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
10325 #define GPIO_IDR_ID2_Pos               (2U)
10326 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
10327 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
10328 #define GPIO_IDR_ID3_Pos               (3U)
10329 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
10330 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
10331 #define GPIO_IDR_ID4_Pos               (4U)
10332 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
10333 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
10334 #define GPIO_IDR_ID5_Pos               (5U)
10335 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
10336 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
10337 #define GPIO_IDR_ID6_Pos               (6U)
10338 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
10339 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
10340 #define GPIO_IDR_ID7_Pos               (7U)
10341 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
10342 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
10343 #define GPIO_IDR_ID8_Pos               (8U)
10344 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
10345 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
10346 #define GPIO_IDR_ID9_Pos               (9U)
10347 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
10348 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
10349 #define GPIO_IDR_ID10_Pos              (10U)
10350 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
10351 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
10352 #define GPIO_IDR_ID11_Pos              (11U)
10353 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
10354 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
10355 #define GPIO_IDR_ID12_Pos              (12U)
10356 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
10357 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
10358 #define GPIO_IDR_ID13_Pos              (13U)
10359 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
10360 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
10361 #define GPIO_IDR_ID14_Pos              (14U)
10362 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
10363 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
10364 #define GPIO_IDR_ID15_Pos              (15U)
10365 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
10366 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
10367 
10368 /******************  Bits definition for GPIO_ODR register  *******************/
10369 #define GPIO_ODR_OD0_Pos               (0U)
10370 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
10371 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
10372 #define GPIO_ODR_OD1_Pos               (1U)
10373 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
10374 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
10375 #define GPIO_ODR_OD2_Pos               (2U)
10376 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
10377 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
10378 #define GPIO_ODR_OD3_Pos               (3U)
10379 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
10380 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
10381 #define GPIO_ODR_OD4_Pos               (4U)
10382 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
10383 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
10384 #define GPIO_ODR_OD5_Pos               (5U)
10385 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
10386 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
10387 #define GPIO_ODR_OD6_Pos               (6U)
10388 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
10389 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
10390 #define GPIO_ODR_OD7_Pos               (7U)
10391 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
10392 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
10393 #define GPIO_ODR_OD8_Pos               (8U)
10394 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
10395 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
10396 #define GPIO_ODR_OD9_Pos               (9U)
10397 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
10398 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
10399 #define GPIO_ODR_OD10_Pos              (10U)
10400 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
10401 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
10402 #define GPIO_ODR_OD11_Pos              (11U)
10403 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
10404 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
10405 #define GPIO_ODR_OD12_Pos              (12U)
10406 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
10407 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
10408 #define GPIO_ODR_OD13_Pos              (13U)
10409 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
10410 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
10411 #define GPIO_ODR_OD14_Pos              (14U)
10412 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
10413 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
10414 #define GPIO_ODR_OD15_Pos              (15U)
10415 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
10416 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
10417 
10418 /******************  Bits definition for GPIO_BSRR register  ******************/
10419 #define GPIO_BSRR_BS0_Pos              (0U)
10420 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
10421 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
10422 #define GPIO_BSRR_BS1_Pos              (1U)
10423 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
10424 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
10425 #define GPIO_BSRR_BS2_Pos              (2U)
10426 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
10427 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
10428 #define GPIO_BSRR_BS3_Pos              (3U)
10429 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
10430 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
10431 #define GPIO_BSRR_BS4_Pos              (4U)
10432 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
10433 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
10434 #define GPIO_BSRR_BS5_Pos              (5U)
10435 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
10436 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
10437 #define GPIO_BSRR_BS6_Pos              (6U)
10438 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
10439 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
10440 #define GPIO_BSRR_BS7_Pos              (7U)
10441 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
10442 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
10443 #define GPIO_BSRR_BS8_Pos              (8U)
10444 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
10445 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
10446 #define GPIO_BSRR_BS9_Pos              (9U)
10447 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
10448 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
10449 #define GPIO_BSRR_BS10_Pos             (10U)
10450 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
10451 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
10452 #define GPIO_BSRR_BS11_Pos             (11U)
10453 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
10454 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
10455 #define GPIO_BSRR_BS12_Pos             (12U)
10456 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
10457 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
10458 #define GPIO_BSRR_BS13_Pos             (13U)
10459 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
10460 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
10461 #define GPIO_BSRR_BS14_Pos             (14U)
10462 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
10463 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
10464 #define GPIO_BSRR_BS15_Pos             (15U)
10465 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
10466 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
10467 #define GPIO_BSRR_BR0_Pos              (16U)
10468 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
10469 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
10470 #define GPIO_BSRR_BR1_Pos              (17U)
10471 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
10472 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
10473 #define GPIO_BSRR_BR2_Pos              (18U)
10474 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
10475 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
10476 #define GPIO_BSRR_BR3_Pos              (19U)
10477 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
10478 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
10479 #define GPIO_BSRR_BR4_Pos              (20U)
10480 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
10481 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
10482 #define GPIO_BSRR_BR5_Pos              (21U)
10483 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
10484 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
10485 #define GPIO_BSRR_BR6_Pos              (22U)
10486 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
10487 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
10488 #define GPIO_BSRR_BR7_Pos              (23U)
10489 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
10490 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
10491 #define GPIO_BSRR_BR8_Pos              (24U)
10492 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
10493 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
10494 #define GPIO_BSRR_BR9_Pos              (25U)
10495 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
10496 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
10497 #define GPIO_BSRR_BR10_Pos             (26U)
10498 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
10499 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
10500 #define GPIO_BSRR_BR11_Pos             (27U)
10501 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
10502 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
10503 #define GPIO_BSRR_BR12_Pos             (28U)
10504 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
10505 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
10506 #define GPIO_BSRR_BR13_Pos             (29U)
10507 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
10508 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
10509 #define GPIO_BSRR_BR14_Pos             (30U)
10510 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
10511 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
10512 #define GPIO_BSRR_BR15_Pos             (31U)
10513 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
10514 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
10515 
10516 /****************** Bit definition for GPIO_LCKR register *********************/
10517 #define GPIO_LCKR_LCK0_Pos             (0U)
10518 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
10519 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
10520 #define GPIO_LCKR_LCK1_Pos             (1U)
10521 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
10522 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
10523 #define GPIO_LCKR_LCK2_Pos             (2U)
10524 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
10525 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
10526 #define GPIO_LCKR_LCK3_Pos             (3U)
10527 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
10528 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
10529 #define GPIO_LCKR_LCK4_Pos             (4U)
10530 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
10531 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
10532 #define GPIO_LCKR_LCK5_Pos             (5U)
10533 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
10534 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
10535 #define GPIO_LCKR_LCK6_Pos             (6U)
10536 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
10537 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
10538 #define GPIO_LCKR_LCK7_Pos             (7U)
10539 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
10540 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
10541 #define GPIO_LCKR_LCK8_Pos             (8U)
10542 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
10543 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
10544 #define GPIO_LCKR_LCK9_Pos             (9U)
10545 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
10546 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
10547 #define GPIO_LCKR_LCK10_Pos            (10U)
10548 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
10549 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
10550 #define GPIO_LCKR_LCK11_Pos            (11U)
10551 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
10552 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
10553 #define GPIO_LCKR_LCK12_Pos            (12U)
10554 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
10555 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
10556 #define GPIO_LCKR_LCK13_Pos            (13U)
10557 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
10558 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
10559 #define GPIO_LCKR_LCK14_Pos            (14U)
10560 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
10561 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
10562 #define GPIO_LCKR_LCK15_Pos            (15U)
10563 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
10564 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
10565 #define GPIO_LCKR_LCKK_Pos             (16U)
10566 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
10567 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
10568 
10569 /****************** Bit definition for GPIO_AFRL register  ********************/
10570 #define GPIO_AFRL_AFSEL0_Pos           (0U)
10571 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
10572 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
10573 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
10574 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
10575 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
10576 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
10577 #define GPIO_AFRL_AFSEL1_Pos           (4U)
10578 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
10579 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
10580 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
10581 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
10582 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
10583 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
10584 #define GPIO_AFRL_AFSEL2_Pos           (8U)
10585 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
10586 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
10587 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
10588 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
10589 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
10590 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
10591 #define GPIO_AFRL_AFSEL3_Pos           (12U)
10592 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
10593 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
10594 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
10595 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
10596 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
10597 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
10598 #define GPIO_AFRL_AFSEL4_Pos           (16U)
10599 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
10600 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
10601 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
10602 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
10603 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
10604 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
10605 #define GPIO_AFRL_AFSEL5_Pos           (20U)
10606 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
10607 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
10608 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
10609 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
10610 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
10611 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
10612 #define GPIO_AFRL_AFSEL6_Pos           (24U)
10613 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
10614 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
10615 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
10616 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
10617 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
10618 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
10619 #define GPIO_AFRL_AFSEL7_Pos           (28U)
10620 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
10621 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
10622 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
10623 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
10624 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
10625 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
10626 
10627 /* Legacy defines */
10628 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
10629 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
10630 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
10631 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
10632 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
10633 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
10634 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
10635 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
10636 
10637 /****************** Bit definition for GPIO_AFRH register  ********************/
10638 #define GPIO_AFRH_AFSEL8_Pos           (0U)
10639 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
10640 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
10641 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
10642 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
10643 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
10644 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
10645 #define GPIO_AFRH_AFSEL9_Pos           (4U)
10646 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
10647 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
10648 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
10649 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
10650 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
10651 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
10652 #define GPIO_AFRH_AFSEL10_Pos          (8U)
10653 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
10654 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
10655 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
10656 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
10657 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
10658 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
10659 #define GPIO_AFRH_AFSEL11_Pos          (12U)
10660 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
10661 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
10662 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
10663 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
10664 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
10665 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
10666 #define GPIO_AFRH_AFSEL12_Pos          (16U)
10667 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
10668 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
10669 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
10670 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
10671 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
10672 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
10673 #define GPIO_AFRH_AFSEL13_Pos          (20U)
10674 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
10675 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
10676 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
10677 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
10678 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
10679 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
10680 #define GPIO_AFRH_AFSEL14_Pos          (24U)
10681 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
10682 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
10683 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
10684 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
10685 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
10686 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
10687 #define GPIO_AFRH_AFSEL15_Pos          (28U)
10688 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
10689 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
10690 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
10691 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
10692 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
10693 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
10694 
10695 /* Legacy defines */
10696 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
10697 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
10698 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
10699 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
10700 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
10701 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
10702 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
10703 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
10704 
10705 /******************************************************************************/
10706 /*                                                                            */
10707 /*                        HSEM HW Semaphore                                   */
10708 /*                                                                            */
10709 /******************************************************************************/
10710 /********************  Bit definition for HSEM_R register  ********************/
10711 #define HSEM_R_PROCID_Pos         (0U)
10712 #define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */
10713 #define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */
10714 #define HSEM_R_COREID_Pos         (8U)
10715 #define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */
10716 #define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */
10717 #define HSEM_R_LOCK_Pos           (31U)
10718 #define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */
10719 #define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */
10720 
10721 /********************  Bit definition for HSEM_RLR register  ******************/
10722 #define HSEM_RLR_PROCID_Pos       (0U)
10723 #define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */
10724 #define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */
10725 #define HSEM_RLR_COREID_Pos       (8U)
10726 #define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */
10727 #define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */
10728 #define HSEM_RLR_LOCK_Pos         (31U)
10729 #define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */
10730 #define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */
10731 
10732 /********************  Bit definition for HSEM_C1IER register  *****************/
10733 #define HSEM_C1IER_ISE0_Pos       (0U)
10734 #define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */
10735 #define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */
10736 #define HSEM_C1IER_ISE1_Pos       (1U)
10737 #define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */
10738 #define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */
10739 #define HSEM_C1IER_ISE2_Pos       (2U)
10740 #define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */
10741 #define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */
10742 #define HSEM_C1IER_ISE3_Pos       (3U)
10743 #define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */
10744 #define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */
10745 #define HSEM_C1IER_ISE4_Pos       (4U)
10746 #define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */
10747 #define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */
10748 #define HSEM_C1IER_ISE5_Pos       (5U)
10749 #define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */
10750 #define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */
10751 #define HSEM_C1IER_ISE6_Pos       (6U)
10752 #define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */
10753 #define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */
10754 #define HSEM_C1IER_ISE7_Pos       (7U)
10755 #define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */
10756 #define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */
10757 #define HSEM_C1IER_ISE8_Pos       (8U)
10758 #define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */
10759 #define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */
10760 #define HSEM_C1IER_ISE9_Pos       (9U)
10761 #define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */
10762 #define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */
10763 #define HSEM_C1IER_ISE10_Pos      (10U)
10764 #define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */
10765 #define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */
10766 #define HSEM_C1IER_ISE11_Pos      (11U)
10767 #define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */
10768 #define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */
10769 #define HSEM_C1IER_ISE12_Pos      (12U)
10770 #define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */
10771 #define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */
10772 #define HSEM_C1IER_ISE13_Pos      (13U)
10773 #define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */
10774 #define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */
10775 #define HSEM_C1IER_ISE14_Pos      (14U)
10776 #define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */
10777 #define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */
10778 #define HSEM_C1IER_ISE15_Pos      (15U)
10779 #define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */
10780 #define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */
10781 #define HSEM_C1IER_ISE16_Pos      (16U)
10782 #define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */
10783 #define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */
10784 #define HSEM_C1IER_ISE17_Pos      (17U)
10785 #define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */
10786 #define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */
10787 #define HSEM_C1IER_ISE18_Pos      (18U)
10788 #define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */
10789 #define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */
10790 #define HSEM_C1IER_ISE19_Pos      (19U)
10791 #define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */
10792 #define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */
10793 #define HSEM_C1IER_ISE20_Pos      (20U)
10794 #define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */
10795 #define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */
10796 #define HSEM_C1IER_ISE21_Pos      (21U)
10797 #define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */
10798 #define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */
10799 #define HSEM_C1IER_ISE22_Pos      (22U)
10800 #define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */
10801 #define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */
10802 #define HSEM_C1IER_ISE23_Pos      (23U)
10803 #define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */
10804 #define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */
10805 #define HSEM_C1IER_ISE24_Pos      (24U)
10806 #define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */
10807 #define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */
10808 #define HSEM_C1IER_ISE25_Pos      (25U)
10809 #define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */
10810 #define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */
10811 #define HSEM_C1IER_ISE26_Pos      (26U)
10812 #define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */
10813 #define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */
10814 #define HSEM_C1IER_ISE27_Pos      (27U)
10815 #define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */
10816 #define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */
10817 #define HSEM_C1IER_ISE28_Pos      (28U)
10818 #define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */
10819 #define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */
10820 #define HSEM_C1IER_ISE29_Pos      (29U)
10821 #define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */
10822 #define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */
10823 #define HSEM_C1IER_ISE30_Pos      (30U)
10824 #define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */
10825 #define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */
10826 #define HSEM_C1IER_ISE31_Pos      (31U)
10827 #define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */
10828 #define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */
10829 
10830 /********************  Bit definition for HSEM_C1ICR register  *****************/
10831 #define HSEM_C1ICR_ISC0_Pos       (0U)
10832 #define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */
10833 #define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */
10834 #define HSEM_C1ICR_ISC1_Pos       (1U)
10835 #define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */
10836 #define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */
10837 #define HSEM_C1ICR_ISC2_Pos       (2U)
10838 #define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */
10839 #define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */
10840 #define HSEM_C1ICR_ISC3_Pos       (3U)
10841 #define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */
10842 #define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */
10843 #define HSEM_C1ICR_ISC4_Pos       (4U)
10844 #define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */
10845 #define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */
10846 #define HSEM_C1ICR_ISC5_Pos       (5U)
10847 #define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */
10848 #define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */
10849 #define HSEM_C1ICR_ISC6_Pos       (6U)
10850 #define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */
10851 #define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */
10852 #define HSEM_C1ICR_ISC7_Pos       (7U)
10853 #define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */
10854 #define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */
10855 #define HSEM_C1ICR_ISC8_Pos       (8U)
10856 #define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */
10857 #define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */
10858 #define HSEM_C1ICR_ISC9_Pos       (9U)
10859 #define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */
10860 #define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */
10861 #define HSEM_C1ICR_ISC10_Pos      (10U)
10862 #define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */
10863 #define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */
10864 #define HSEM_C1ICR_ISC11_Pos      (11U)
10865 #define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */
10866 #define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */
10867 #define HSEM_C1ICR_ISC12_Pos      (12U)
10868 #define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */
10869 #define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */
10870 #define HSEM_C1ICR_ISC13_Pos      (13U)
10871 #define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */
10872 #define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */
10873 #define HSEM_C1ICR_ISC14_Pos      (14U)
10874 #define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */
10875 #define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */
10876 #define HSEM_C1ICR_ISC15_Pos      (15U)
10877 #define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */
10878 #define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */
10879 #define HSEM_C1ICR_ISC16_Pos      (16U)
10880 #define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */
10881 #define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */
10882 #define HSEM_C1ICR_ISC17_Pos      (17U)
10883 #define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */
10884 #define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */
10885 #define HSEM_C1ICR_ISC18_Pos      (18U)
10886 #define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */
10887 #define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */
10888 #define HSEM_C1ICR_ISC19_Pos      (19U)
10889 #define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */
10890 #define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */
10891 #define HSEM_C1ICR_ISC20_Pos      (20U)
10892 #define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */
10893 #define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */
10894 #define HSEM_C1ICR_ISC21_Pos      (21U)
10895 #define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */
10896 #define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */
10897 #define HSEM_C1ICR_ISC22_Pos      (22U)
10898 #define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */
10899 #define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */
10900 #define HSEM_C1ICR_ISC23_Pos      (23U)
10901 #define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */
10902 #define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */
10903 #define HSEM_C1ICR_ISC24_Pos      (24U)
10904 #define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */
10905 #define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */
10906 #define HSEM_C1ICR_ISC25_Pos      (25U)
10907 #define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */
10908 #define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */
10909 #define HSEM_C1ICR_ISC26_Pos      (26U)
10910 #define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */
10911 #define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */
10912 #define HSEM_C1ICR_ISC27_Pos      (27U)
10913 #define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */
10914 #define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */
10915 #define HSEM_C1ICR_ISC28_Pos      (28U)
10916 #define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */
10917 #define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */
10918 #define HSEM_C1ICR_ISC29_Pos      (29U)
10919 #define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */
10920 #define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */
10921 #define HSEM_C1ICR_ISC30_Pos      (30U)
10922 #define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */
10923 #define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */
10924 #define HSEM_C1ICR_ISC31_Pos      (31U)
10925 #define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */
10926 #define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */
10927 
10928 /********************  Bit definition for HSEM_C1ISR register  *****************/
10929 #define HSEM_C1ISR_ISF0_Pos       (0U)
10930 #define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */
10931 #define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */
10932 #define HSEM_C1ISR_ISF1_Pos       (1U)
10933 #define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */
10934 #define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */
10935 #define HSEM_C1ISR_ISF2_Pos       (2U)
10936 #define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */
10937 #define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */
10938 #define HSEM_C1ISR_ISF3_Pos       (3U)
10939 #define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */
10940 #define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */
10941 #define HSEM_C1ISR_ISF4_Pos       (4U)
10942 #define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */
10943 #define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */
10944 #define HSEM_C1ISR_ISF5_Pos       (5U)
10945 #define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */
10946 #define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */
10947 #define HSEM_C1ISR_ISF6_Pos       (6U)
10948 #define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */
10949 #define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */
10950 #define HSEM_C1ISR_ISF7_Pos       (7U)
10951 #define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */
10952 #define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */
10953 #define HSEM_C1ISR_ISF8_Pos       (8U)
10954 #define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */
10955 #define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */
10956 #define HSEM_C1ISR_ISF9_Pos       (9U)
10957 #define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */
10958 #define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */
10959 #define HSEM_C1ISR_ISF10_Pos      (10U)
10960 #define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */
10961 #define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */
10962 #define HSEM_C1ISR_ISF11_Pos      (11U)
10963 #define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */
10964 #define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */
10965 #define HSEM_C1ISR_ISF12_Pos      (12U)
10966 #define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */
10967 #define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */
10968 #define HSEM_C1ISR_ISF13_Pos      (13U)
10969 #define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */
10970 #define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */
10971 #define HSEM_C1ISR_ISF14_Pos      (14U)
10972 #define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */
10973 #define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */
10974 #define HSEM_C1ISR_ISF15_Pos      (15U)
10975 #define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */
10976 #define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */
10977 #define HSEM_C1ISR_ISF16_Pos      (16U)
10978 #define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */
10979 #define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */
10980 #define HSEM_C1ISR_ISF17_Pos      (17U)
10981 #define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */
10982 #define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */
10983 #define HSEM_C1ISR_ISF18_Pos      (18U)
10984 #define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */
10985 #define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */
10986 #define HSEM_C1ISR_ISF19_Pos      (19U)
10987 #define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */
10988 #define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */
10989 #define HSEM_C1ISR_ISF20_Pos      (20U)
10990 #define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */
10991 #define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */
10992 #define HSEM_C1ISR_ISF21_Pos      (21U)
10993 #define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */
10994 #define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */
10995 #define HSEM_C1ISR_ISF22_Pos      (22U)
10996 #define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */
10997 #define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */
10998 #define HSEM_C1ISR_ISF23_Pos      (23U)
10999 #define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */
11000 #define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */
11001 #define HSEM_C1ISR_ISF24_Pos      (24U)
11002 #define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */
11003 #define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */
11004 #define HSEM_C1ISR_ISF25_Pos      (25U)
11005 #define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */
11006 #define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */
11007 #define HSEM_C1ISR_ISF26_Pos      (26U)
11008 #define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */
11009 #define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */
11010 #define HSEM_C1ISR_ISF27_Pos      (27U)
11011 #define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */
11012 #define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */
11013 #define HSEM_C1ISR_ISF28_Pos      (28U)
11014 #define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */
11015 #define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */
11016 #define HSEM_C1ISR_ISF29_Pos      (29U)
11017 #define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */
11018 #define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */
11019 #define HSEM_C1ISR_ISF30_Pos      (30U)
11020 #define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */
11021 #define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */
11022 #define HSEM_C1ISR_ISF31_Pos      (31U)
11023 #define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */
11024 #define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */
11025 
11026 /********************  Bit definition for HSEM_C1MISR register  *****************/
11027 #define HSEM_C1MISR_MISF0_Pos     (0U)
11028 #define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */
11029 #define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */
11030 #define HSEM_C1MISR_MISF1_Pos     (1U)
11031 #define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */
11032 #define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */
11033 #define HSEM_C1MISR_MISF2_Pos     (2U)
11034 #define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */
11035 #define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */
11036 #define HSEM_C1MISR_MISF3_Pos     (3U)
11037 #define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */
11038 #define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */
11039 #define HSEM_C1MISR_MISF4_Pos     (4U)
11040 #define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */
11041 #define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */
11042 #define HSEM_C1MISR_MISF5_Pos     (5U)
11043 #define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */
11044 #define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */
11045 #define HSEM_C1MISR_MISF6_Pos     (6U)
11046 #define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */
11047 #define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */
11048 #define HSEM_C1MISR_MISF7_Pos     (7U)
11049 #define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */
11050 #define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */
11051 #define HSEM_C1MISR_MISF8_Pos     (8U)
11052 #define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */
11053 #define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */
11054 #define HSEM_C1MISR_MISF9_Pos     (9U)
11055 #define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */
11056 #define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */
11057 #define HSEM_C1MISR_MISF10_Pos    (10U)
11058 #define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */
11059 #define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */
11060 #define HSEM_C1MISR_MISF11_Pos    (11U)
11061 #define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */
11062 #define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */
11063 #define HSEM_C1MISR_MISF12_Pos    (12U)
11064 #define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */
11065 #define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */
11066 #define HSEM_C1MISR_MISF13_Pos    (13U)
11067 #define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */
11068 #define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */
11069 #define HSEM_C1MISR_MISF14_Pos    (14U)
11070 #define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */
11071 #define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */
11072 #define HSEM_C1MISR_MISF15_Pos    (15U)
11073 #define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */
11074 #define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */
11075 #define HSEM_C1MISR_MISF16_Pos    (16U)
11076 #define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */
11077 #define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */
11078 #define HSEM_C1MISR_MISF17_Pos    (17U)
11079 #define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */
11080 #define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */
11081 #define HSEM_C1MISR_MISF18_Pos    (18U)
11082 #define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */
11083 #define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */
11084 #define HSEM_C1MISR_MISF19_Pos    (19U)
11085 #define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */
11086 #define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */
11087 #define HSEM_C1MISR_MISF20_Pos    (20U)
11088 #define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */
11089 #define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */
11090 #define HSEM_C1MISR_MISF21_Pos    (21U)
11091 #define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */
11092 #define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */
11093 #define HSEM_C1MISR_MISF22_Pos    (22U)
11094 #define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */
11095 #define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */
11096 #define HSEM_C1MISR_MISF23_Pos    (23U)
11097 #define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */
11098 #define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */
11099 #define HSEM_C1MISR_MISF24_Pos    (24U)
11100 #define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */
11101 #define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */
11102 #define HSEM_C1MISR_MISF25_Pos    (25U)
11103 #define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */
11104 #define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */
11105 #define HSEM_C1MISR_MISF26_Pos    (26U)
11106 #define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */
11107 #define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */
11108 #define HSEM_C1MISR_MISF27_Pos    (27U)
11109 #define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */
11110 #define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */
11111 #define HSEM_C1MISR_MISF28_Pos    (28U)
11112 #define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */
11113 #define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */
11114 #define HSEM_C1MISR_MISF29_Pos    (29U)
11115 #define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */
11116 #define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */
11117 #define HSEM_C1MISR_MISF30_Pos    (30U)
11118 #define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */
11119 #define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */
11120 #define HSEM_C1MISR_MISF31_Pos    (31U)
11121 #define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */
11122 #define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */
11123 
11124 /********************  Bit definition for HSEM_CR register  *****************/
11125 #define HSEM_CR_COREID_Pos        (8U)
11126 #define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */
11127 #define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */
11128 #define HSEM_CR_KEY_Pos           (16U)
11129 #define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */
11130 #define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */
11131 
11132 /********************  Bit definition for HSEM_KEYR register  *****************/
11133 #define HSEM_KEYR_KEY_Pos         (16U)
11134 #define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */
11135 #define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */
11136 
11137 /******************************************************************************/
11138 /*                                                                            */
11139 /*                                    HASH                                    */
11140 /*                                                                            */
11141 /******************************************************************************/
11142 /******************  Bits definition for HASH_CR register  ********************/
11143 #define HASH_CR_INIT_Pos          (2U)
11144 #define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */
11145 #define HASH_CR_INIT              HASH_CR_INIT_Msk
11146 #define HASH_CR_DMAE_Pos          (3U)
11147 #define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */
11148 #define HASH_CR_DMAE              HASH_CR_DMAE_Msk
11149 #define HASH_CR_DATATYPE_Pos      (4U)
11150 #define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */
11151 #define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk
11152 #define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */
11153 #define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */
11154 #define HASH_CR_MODE_Pos          (6U)
11155 #define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */
11156 #define HASH_CR_MODE              HASH_CR_MODE_Msk
11157 #define HASH_CR_ALGO_Pos          (7U)
11158 #define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */
11159 #define HASH_CR_ALGO              HASH_CR_ALGO_Msk
11160 #define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */
11161 #define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */
11162 #define HASH_CR_NBW_Pos           (8U)
11163 #define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */
11164 #define HASH_CR_NBW               HASH_CR_NBW_Msk
11165 #define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */
11166 #define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */
11167 #define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */
11168 #define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */
11169 #define HASH_CR_DINNE_Pos         (12U)
11170 #define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */
11171 #define HASH_CR_DINNE             HASH_CR_DINNE_Msk
11172 #define HASH_CR_MDMAT_Pos         (13U)
11173 #define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */
11174 #define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk
11175 #define HASH_CR_LKEY_Pos          (16U)
11176 #define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */
11177 #define HASH_CR_LKEY              HASH_CR_LKEY_Msk
11178 
11179 /******************  Bits definition for HASH_STR register  *******************/
11180 #define HASH_STR_NBLW_Pos         (0U)
11181 #define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */
11182 #define HASH_STR_NBLW             HASH_STR_NBLW_Msk
11183 #define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */
11184 #define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */
11185 #define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */
11186 #define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */
11187 #define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */
11188 #define HASH_STR_DCAL_Pos         (8U)
11189 #define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */
11190 #define HASH_STR_DCAL             HASH_STR_DCAL_Msk
11191 
11192 /******************  Bits definition for HASH_IMR register  *******************/
11193 #define HASH_IMR_DINIE_Pos        (0U)
11194 #define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */
11195 #define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk
11196 #define HASH_IMR_DCIE_Pos         (1U)
11197 #define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */
11198 #define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk
11199 
11200 /******************  Bits definition for HASH_SR register  ********************/
11201 #define HASH_SR_DINIS_Pos         (0U)
11202 #define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */
11203 #define HASH_SR_DINIS             HASH_SR_DINIS_Msk
11204 #define HASH_SR_DCIS_Pos          (1U)
11205 #define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */
11206 #define HASH_SR_DCIS              HASH_SR_DCIS_Msk
11207 #define HASH_SR_DMAS_Pos          (2U)
11208 #define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */
11209 #define HASH_SR_DMAS              HASH_SR_DMAS_Msk
11210 #define HASH_SR_BUSY_Pos          (3U)
11211 #define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */
11212 #define HASH_SR_BUSY              HASH_SR_BUSY_Msk
11213 /******************************************************************************/
11214 /*                                                                            */
11215 /*                      Inter-integrated Circuit Interface (I2C)              */
11216 /*                                                                            */
11217 /******************************************************************************/
11218 /*******************  Bit definition for I2C_CR1 register  *******************/
11219 #define I2C_CR1_PE_Pos               (0U)
11220 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
11221 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
11222 #define I2C_CR1_TXIE_Pos             (1U)
11223 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
11224 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
11225 #define I2C_CR1_RXIE_Pos             (2U)
11226 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
11227 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
11228 #define I2C_CR1_ADDRIE_Pos           (3U)
11229 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
11230 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
11231 #define I2C_CR1_NACKIE_Pos           (4U)
11232 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
11233 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
11234 #define I2C_CR1_STOPIE_Pos           (5U)
11235 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
11236 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
11237 #define I2C_CR1_TCIE_Pos             (6U)
11238 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
11239 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
11240 #define I2C_CR1_ERRIE_Pos            (7U)
11241 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
11242 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
11243 #define I2C_CR1_DNF_Pos              (8U)
11244 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
11245 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
11246 #define I2C_CR1_ANFOFF_Pos           (12U)
11247 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
11248 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
11249 #define I2C_CR1_TXDMAEN_Pos          (14U)
11250 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
11251 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
11252 #define I2C_CR1_RXDMAEN_Pos          (15U)
11253 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
11254 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
11255 #define I2C_CR1_SBC_Pos              (16U)
11256 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
11257 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
11258 #define I2C_CR1_NOSTRETCH_Pos        (17U)
11259 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
11260 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
11261 #define I2C_CR1_WUPEN_Pos            (18U)
11262 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
11263 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
11264 #define I2C_CR1_GCEN_Pos             (19U)
11265 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
11266 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
11267 #define I2C_CR1_SMBHEN_Pos           (20U)
11268 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
11269 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
11270 #define I2C_CR1_SMBDEN_Pos           (21U)
11271 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
11272 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
11273 #define I2C_CR1_ALERTEN_Pos          (22U)
11274 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
11275 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
11276 #define I2C_CR1_PECEN_Pos            (23U)
11277 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
11278 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
11279 
11280 /******************  Bit definition for I2C_CR2 register  ********************/
11281 #define I2C_CR2_SADD_Pos             (0U)
11282 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
11283 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
11284 #define I2C_CR2_RD_WRN_Pos           (10U)
11285 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
11286 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
11287 #define I2C_CR2_ADD10_Pos            (11U)
11288 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
11289 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
11290 #define I2C_CR2_HEAD10R_Pos          (12U)
11291 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
11292 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
11293 #define I2C_CR2_START_Pos            (13U)
11294 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
11295 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
11296 #define I2C_CR2_STOP_Pos             (14U)
11297 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
11298 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
11299 #define I2C_CR2_NACK_Pos             (15U)
11300 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
11301 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
11302 #define I2C_CR2_NBYTES_Pos           (16U)
11303 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
11304 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
11305 #define I2C_CR2_RELOAD_Pos           (24U)
11306 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
11307 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
11308 #define I2C_CR2_AUTOEND_Pos          (25U)
11309 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
11310 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
11311 #define I2C_CR2_PECBYTE_Pos          (26U)
11312 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
11313 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
11314 
11315 /*******************  Bit definition for I2C_OAR1 register  ******************/
11316 #define I2C_OAR1_OA1_Pos             (0U)
11317 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
11318 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
11319 #define I2C_OAR1_OA1MODE_Pos         (10U)
11320 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
11321 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
11322 #define I2C_OAR1_OA1EN_Pos           (15U)
11323 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
11324 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
11325 
11326 /*******************  Bit definition for I2C_OAR2 register  ******************/
11327 #define I2C_OAR2_OA2_Pos             (1U)
11328 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
11329 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
11330 #define I2C_OAR2_OA2MSK_Pos          (8U)
11331 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
11332 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
11333 #define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */
11334 #define I2C_OAR2_OA2MASK01_Pos       (8U)
11335 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
11336 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
11337 #define I2C_OAR2_OA2MASK02_Pos       (9U)
11338 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
11339 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
11340 #define I2C_OAR2_OA2MASK03_Pos       (8U)
11341 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
11342 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
11343 #define I2C_OAR2_OA2MASK04_Pos       (10U)
11344 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
11345 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
11346 #define I2C_OAR2_OA2MASK05_Pos       (8U)
11347 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
11348 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
11349 #define I2C_OAR2_OA2MASK06_Pos       (9U)
11350 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
11351 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
11352 #define I2C_OAR2_OA2MASK07_Pos       (8U)
11353 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
11354 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
11355 #define I2C_OAR2_OA2EN_Pos           (15U)
11356 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
11357 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
11358 
11359 /*******************  Bit definition for I2C_TIMINGR register *******************/
11360 #define I2C_TIMINGR_SCLL_Pos         (0U)
11361 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
11362 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
11363 #define I2C_TIMINGR_SCLH_Pos         (8U)
11364 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
11365 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
11366 #define I2C_TIMINGR_SDADEL_Pos       (16U)
11367 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
11368 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
11369 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
11370 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
11371 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
11372 #define I2C_TIMINGR_PRESC_Pos        (28U)
11373 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
11374 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
11375 
11376 /******************* Bit definition for I2C_TIMEOUTR register *******************/
11377 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
11378 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
11379 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
11380 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
11381 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
11382 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
11383 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
11384 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
11385 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
11386 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
11387 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
11388 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
11389 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
11390 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
11391 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
11392 
11393 /******************  Bit definition for I2C_ISR register  *********************/
11394 #define I2C_ISR_TXE_Pos              (0U)
11395 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
11396 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
11397 #define I2C_ISR_TXIS_Pos             (1U)
11398 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
11399 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
11400 #define I2C_ISR_RXNE_Pos             (2U)
11401 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
11402 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
11403 #define I2C_ISR_ADDR_Pos             (3U)
11404 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
11405 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
11406 #define I2C_ISR_NACKF_Pos            (4U)
11407 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
11408 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
11409 #define I2C_ISR_STOPF_Pos            (5U)
11410 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
11411 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
11412 #define I2C_ISR_TC_Pos               (6U)
11413 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
11414 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
11415 #define I2C_ISR_TCR_Pos              (7U)
11416 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
11417 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
11418 #define I2C_ISR_BERR_Pos             (8U)
11419 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
11420 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
11421 #define I2C_ISR_ARLO_Pos             (9U)
11422 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
11423 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
11424 #define I2C_ISR_OVR_Pos              (10U)
11425 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
11426 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
11427 #define I2C_ISR_PECERR_Pos           (11U)
11428 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
11429 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
11430 #define I2C_ISR_TIMEOUT_Pos          (12U)
11431 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
11432 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
11433 #define I2C_ISR_ALERT_Pos            (13U)
11434 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
11435 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
11436 #define I2C_ISR_BUSY_Pos             (15U)
11437 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
11438 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
11439 #define I2C_ISR_DIR_Pos              (16U)
11440 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
11441 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
11442 #define I2C_ISR_ADDCODE_Pos          (17U)
11443 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
11444 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
11445 
11446 /******************  Bit definition for I2C_ICR register  *********************/
11447 #define I2C_ICR_ADDRCF_Pos           (3U)
11448 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
11449 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
11450 #define I2C_ICR_NACKCF_Pos           (4U)
11451 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
11452 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
11453 #define I2C_ICR_STOPCF_Pos           (5U)
11454 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
11455 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
11456 #define I2C_ICR_BERRCF_Pos           (8U)
11457 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
11458 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
11459 #define I2C_ICR_ARLOCF_Pos           (9U)
11460 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
11461 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
11462 #define I2C_ICR_OVRCF_Pos            (10U)
11463 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
11464 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
11465 #define I2C_ICR_PECCF_Pos            (11U)
11466 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
11467 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
11468 #define I2C_ICR_TIMOUTCF_Pos         (12U)
11469 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
11470 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
11471 #define I2C_ICR_ALERTCF_Pos          (13U)
11472 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
11473 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
11474 
11475 /******************  Bit definition for I2C_PECR register  *********************/
11476 #define I2C_PECR_PEC_Pos             (0U)
11477 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
11478 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
11479 
11480 /******************  Bit definition for I2C_RXDR register  *********************/
11481 #define I2C_RXDR_RXDATA_Pos          (0U)
11482 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
11483 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
11484 
11485 /******************  Bit definition for I2C_TXDR register  *********************/
11486 #define I2C_TXDR_TXDATA_Pos          (0U)
11487 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
11488 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
11489 
11490 /******************************************************************************/
11491 /*                                                                            */
11492 /*                           Independent WATCHDOG                             */
11493 /*                                                                            */
11494 /******************************************************************************/
11495 /*******************  Bit definition for IWDG_KR register  ********************/
11496 #define IWDG_KR_KEY_Pos      (0U)
11497 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
11498 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
11499 
11500 /*******************  Bit definition for IWDG_PR register  ********************/
11501 #define IWDG_PR_PR_Pos       (0U)
11502 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
11503 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
11504 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
11505 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
11506 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
11507 
11508 /*******************  Bit definition for IWDG_RLR register  *******************/
11509 #define IWDG_RLR_RL_Pos      (0U)
11510 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
11511 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
11512 
11513 /*******************  Bit definition for IWDG_SR register  ********************/
11514 #define IWDG_SR_PVU_Pos      (0U)
11515 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
11516 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
11517 #define IWDG_SR_RVU_Pos      (1U)
11518 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
11519 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
11520 #define IWDG_SR_WVU_Pos      (2U)
11521 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
11522 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
11523 
11524 /*******************  Bit definition for IWDG_KR register  ********************/
11525 #define IWDG_WINR_WIN_Pos    (0U)
11526 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
11527 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
11528 
11529 /******************************************************************************/
11530 /*                                                                            */
11531 /*                        JPEG Encoder/Decoder                                */
11532 /*                                                                            */
11533 /******************************************************************************/
11534 /********************  Bit definition for CONFR0 register  ********************/
11535 #define JPEG_CONFR0_START_Pos           (0U)
11536 #define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */
11537 #define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */
11538 
11539 /********************  Bit definition for CONFR1 register  ********************/
11540 #define JPEG_CONFR1_NF_Pos              (0U)
11541 #define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */
11542 #define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */
11543 #define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
11544 #define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
11545 #define JPEG_CONFR1_DE_Pos              (3U)
11546 #define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */
11547 #define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */
11548 #define JPEG_CONFR1_COLORSPACE_Pos      (4U)
11549 #define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */
11550 #define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */
11551 #define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
11552 #define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
11553 #define JPEG_CONFR1_NS_Pos              (6U)
11554 #define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */
11555 #define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */
11556 #define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
11557 #define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
11558 #define JPEG_CONFR1_HDR_Pos             (8U)
11559 #define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */
11560 #define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */
11561 #define JPEG_CONFR1_YSIZE_Pos           (16U)
11562 #define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */
11563 #define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */
11564 
11565 /********************  Bit definition for CONFR2 register  ********************/
11566 #define JPEG_CONFR2_NMCU_Pos            (0U)
11567 #define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */
11568 #define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */
11569 
11570 /********************  Bit definition for CONFR3 register  ********************/
11571 #define JPEG_CONFR3_XSIZE_Pos           (16U)
11572 #define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */
11573 #define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */
11574 
11575 /********************  Bit definition for CONFR4 register  ********************/
11576 #define JPEG_CONFR4_HD_Pos              (0U)
11577 #define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */
11578 #define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
11579 #define JPEG_CONFR4_HA_Pos              (1U)
11580 #define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */
11581 #define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
11582 #define JPEG_CONFR4_QT_Pos              (2U)
11583 #define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */
11584 #define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */
11585 #define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
11586 #define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
11587 #define JPEG_CONFR4_NB_Pos              (4U)
11588 #define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */
11589 #define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11590 #define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
11591 #define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
11592 #define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
11593 #define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
11594 #define JPEG_CONFR4_VSF_Pos             (8U)
11595 #define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */
11596 #define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */
11597 #define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
11598 #define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
11599 #define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
11600 #define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
11601 #define JPEG_CONFR4_HSF_Pos             (12U)
11602 #define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */
11603 #define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */
11604 #define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
11605 #define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
11606 #define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
11607 #define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */
11608 
11609 /********************  Bit definition for CONFR5 register  ********************/
11610 #define JPEG_CONFR5_HD_Pos              (0U)
11611 #define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */
11612 #define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
11613 #define JPEG_CONFR5_HA_Pos              (1U)
11614 #define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */
11615 #define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
11616 #define JPEG_CONFR5_QT_Pos              (2U)
11617 #define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */
11618 #define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */
11619 #define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
11620 #define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
11621 #define JPEG_CONFR5_NB_Pos              (4U)
11622 #define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */
11623 #define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11624 #define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
11625 #define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
11626 #define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
11627 #define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
11628 #define JPEG_CONFR5_VSF_Pos             (8U)
11629 #define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */
11630 #define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
11631 #define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
11632 #define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
11633 #define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
11634 #define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
11635 #define JPEG_CONFR5_HSF_Pos             (12U)
11636 #define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */
11637 #define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
11638 #define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
11639 #define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
11640 #define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
11641 #define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */
11642 
11643 /********************  Bit definition for CONFR6 register  ********************/
11644 #define JPEG_CONFR6_HD_Pos              (0U)
11645 #define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */
11646 #define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
11647 #define JPEG_CONFR6_HA_Pos              (1U)
11648 #define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */
11649 #define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
11650 #define JPEG_CONFR6_QT_Pos              (2U)
11651 #define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */
11652 #define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */
11653 #define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
11654 #define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
11655 #define JPEG_CONFR6_NB_Pos              (4U)
11656 #define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */
11657 #define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11658 #define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
11659 #define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
11660 #define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
11661 #define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
11662 #define JPEG_CONFR6_VSF_Pos             (8U)
11663 #define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */
11664 #define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
11665 #define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
11666 #define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
11667 #define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
11668 #define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
11669 #define JPEG_CONFR6_HSF_Pos             (12U)
11670 #define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */
11671 #define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
11672 #define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
11673 #define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
11674 #define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
11675 #define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */
11676 
11677 /********************  Bit definition for CONFR7 register  ********************/
11678 #define JPEG_CONFR7_HD_Pos              (0U)
11679 #define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */
11680 #define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
11681 #define JPEG_CONFR7_HA_Pos              (1U)
11682 #define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */
11683 #define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
11684 #define JPEG_CONFR7_QT_Pos              (2U)
11685 #define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */
11686 #define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */
11687 #define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
11688 #define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
11689 #define JPEG_CONFR7_NB_Pos              (4U)
11690 #define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */
11691 #define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11692 #define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
11693 #define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
11694 #define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
11695 #define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
11696 #define JPEG_CONFR7_VSF_Pos             (8U)
11697 #define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */
11698 #define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
11699 #define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
11700 #define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
11701 #define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
11702 #define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
11703 #define JPEG_CONFR7_HSF_Pos             (12U)
11704 #define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */
11705 #define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
11706 #define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
11707 #define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
11708 #define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
11709 #define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */
11710 
11711 /********************  Bit definition for CR register  ********************/
11712 #define JPEG_CR_JCEN_Pos                (0U)
11713 #define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */
11714 #define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */
11715 #define JPEG_CR_IFTIE_Pos               (1U)
11716 #define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */
11717 #define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */
11718 #define JPEG_CR_IFNFIE_Pos              (2U)
11719 #define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */
11720 #define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */
11721 #define JPEG_CR_OFTIE_Pos               (3U)
11722 #define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */
11723 #define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */
11724 #define JPEG_CR_OFNEIE_Pos              (4U)
11725 #define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */
11726 #define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */
11727 #define JPEG_CR_EOCIE_Pos               (5U)
11728 #define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */
11729 #define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */
11730 #define JPEG_CR_HPDIE_Pos               (6U)
11731 #define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */
11732 #define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */
11733 #define JPEG_CR_IFF_Pos                 (13U)
11734 #define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */
11735 #define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */
11736 #define JPEG_CR_OFF_Pos                 (14U)
11737 #define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */
11738 #define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */
11739 
11740 /********************  Bit definition for SR register  ********************/
11741 #define JPEG_SR_IFTF_Pos                (1U)
11742 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
11743 #define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
11744 #define JPEG_SR_IFNFF_Pos               (2U)
11745 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
11746 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
11747 #define JPEG_SR_OFTF_Pos                (3U)
11748 #define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */
11749 #define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */
11750 #define JPEG_SR_OFNEF_Pos               (4U)
11751 #define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */
11752 #define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */
11753 #define JPEG_SR_EOCF_Pos                (5U)
11754 #define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */
11755 #define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
11756 #define JPEG_SR_HPDF_Pos                (6U)
11757 #define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */
11758 #define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
11759 #define JPEG_SR_COF_Pos                 (7U)
11760 #define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */
11761 #define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */
11762 
11763 /********************  Bit definition for CFR register  ********************/
11764 #define JPEG_CFR_CEOCF_Pos              (5U)
11765 #define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */
11766 #define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */
11767 #define JPEG_CFR_CHPDF_Pos              (6U)
11768 #define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */
11769 #define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */
11770 
11771 /********************  Bit definition for DIR register  ********************/
11772 #define JPEG_DIR_DATAIN_Pos             (0U)
11773 #define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */
11774 #define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */
11775 
11776 /********************  Bit definition for DOR register  ********************/
11777 #define JPEG_DOR_DATAOUT_Pos            (0U)
11778 #define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
11779 #define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */
11780 
11781 /******************************************************************************/
11782 /*                                                                            */
11783 /*                      LCD-TFT Display Controller (LTDC)                     */
11784 /*                                                                            */
11785 /******************************************************************************/
11786 
11787 /********************  Bit definition for LTDC_SSCR register  *****************/
11788 
11789 #define LTDC_SSCR_VSH_Pos            (0U)
11790 #define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */
11791 #define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
11792 #define LTDC_SSCR_HSW_Pos            (16U)
11793 #define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */
11794 #define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
11795 
11796 /********************  Bit definition for LTDC_BPCR register  *****************/
11797 
11798 #define LTDC_BPCR_AVBP_Pos           (0U)
11799 #define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */
11800 #define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
11801 #define LTDC_BPCR_AHBP_Pos           (16U)
11802 #define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */
11803 #define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
11804 
11805 /********************  Bit definition for LTDC_AWCR register  *****************/
11806 
11807 #define LTDC_AWCR_AAH_Pos            (0U)
11808 #define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */
11809 #define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active height */
11810 #define LTDC_AWCR_AAW_Pos            (16U)
11811 #define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */
11812 #define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
11813 
11814 /********************  Bit definition for LTDC_TWCR register  *****************/
11815 
11816 #define LTDC_TWCR_TOTALH_Pos         (0U)
11817 #define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */
11818 #define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total height */
11819 #define LTDC_TWCR_TOTALW_Pos         (16U)
11820 #define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */
11821 #define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
11822 
11823 /********************  Bit definition for LTDC_GCR register  ******************/
11824 
11825 #define LTDC_GCR_LTDCEN_Pos          (0U)
11826 #define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */
11827 #define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
11828 #define LTDC_GCR_DBW_Pos             (4U)
11829 #define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */
11830 #define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
11831 #define LTDC_GCR_DGW_Pos             (8U)
11832 #define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */
11833 #define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
11834 #define LTDC_GCR_DRW_Pos             (12U)
11835 #define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */
11836 #define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
11837 #define LTDC_GCR_DEN_Pos             (16U)
11838 #define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */
11839 #define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
11840 #define LTDC_GCR_PCPOL_Pos           (28U)
11841 #define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */
11842 #define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
11843 #define LTDC_GCR_DEPOL_Pos           (29U)
11844 #define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */
11845 #define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
11846 #define LTDC_GCR_VSPOL_Pos           (30U)
11847 #define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */
11848 #define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
11849 #define LTDC_GCR_HSPOL_Pos           (31U)
11850 #define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */
11851 #define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
11852 
11853 
11854 /********************  Bit definition for LTDC_SRCR register  *****************/
11855 
11856 #define LTDC_SRCR_IMR_Pos            (0U)
11857 #define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */
11858 #define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
11859 #define LTDC_SRCR_VBR_Pos            (1U)
11860 #define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */
11861 #define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
11862 
11863 /********************  Bit definition for LTDC_BCCR register  *****************/
11864 
11865 #define LTDC_BCCR_BCBLUE_Pos         (0U)
11866 #define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */
11867 #define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
11868 #define LTDC_BCCR_BCGREEN_Pos        (8U)
11869 #define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */
11870 #define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
11871 #define LTDC_BCCR_BCRED_Pos          (16U)
11872 #define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */
11873 #define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
11874 
11875 /********************  Bit definition for LTDC_IER register  ******************/
11876 
11877 #define LTDC_IER_LIE_Pos             (0U)
11878 #define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */
11879 #define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
11880 #define LTDC_IER_FUIE_Pos            (1U)
11881 #define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */
11882 #define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
11883 #define LTDC_IER_TERRIE_Pos          (2U)
11884 #define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */
11885 #define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
11886 #define LTDC_IER_RRIE_Pos            (3U)
11887 #define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */
11888 #define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
11889 
11890 /********************  Bit definition for LTDC_ISR register  ******************/
11891 
11892 #define LTDC_ISR_LIF_Pos             (0U)
11893 #define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */
11894 #define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
11895 #define LTDC_ISR_FUIF_Pos            (1U)
11896 #define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */
11897 #define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
11898 #define LTDC_ISR_TERRIF_Pos          (2U)
11899 #define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */
11900 #define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
11901 #define LTDC_ISR_RRIF_Pos            (3U)
11902 #define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */
11903 #define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
11904 
11905 /********************  Bit definition for LTDC_ICR register  ******************/
11906 
11907 #define LTDC_ICR_CLIF_Pos            (0U)
11908 #define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */
11909 #define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
11910 #define LTDC_ICR_CFUIF_Pos           (1U)
11911 #define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */
11912 #define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
11913 #define LTDC_ICR_CTERRIF_Pos         (2U)
11914 #define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */
11915 #define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
11916 #define LTDC_ICR_CRRIF_Pos           (3U)
11917 #define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */
11918 #define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
11919 
11920 /********************  Bit definition for LTDC_LIPCR register  ****************/
11921 
11922 #define LTDC_LIPCR_LIPOS_Pos         (0U)
11923 #define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */
11924 #define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
11925 
11926 /********************  Bit definition for LTDC_CPSR register  *****************/
11927 
11928 #define LTDC_CPSR_CYPOS_Pos          (0U)
11929 #define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */
11930 #define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
11931 #define LTDC_CPSR_CXPOS_Pos          (16U)
11932 #define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */
11933 #define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
11934 
11935 /********************  Bit definition for LTDC_CDSR register  *****************/
11936 
11937 #define LTDC_CDSR_VDES_Pos           (0U)
11938 #define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */
11939 #define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
11940 #define LTDC_CDSR_HDES_Pos           (1U)
11941 #define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */
11942 #define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
11943 #define LTDC_CDSR_VSYNCS_Pos         (2U)
11944 #define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */
11945 #define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
11946 #define LTDC_CDSR_HSYNCS_Pos         (3U)
11947 #define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */
11948 #define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
11949 
11950 /********************  Bit definition for LTDC_LxCR register  *****************/
11951 
11952 #define LTDC_LxCR_LEN_Pos            (0U)
11953 #define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */
11954 #define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
11955 #define LTDC_LxCR_COLKEN_Pos         (1U)
11956 #define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */
11957 #define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
11958 #define LTDC_LxCR_CLUTEN_Pos         (4U)
11959 #define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */
11960 #define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
11961 
11962 /********************  Bit definition for LTDC_LxWHPCR register  **************/
11963 
11964 #define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
11965 #define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */
11966 #define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
11967 #define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
11968 #define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */
11969 #define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
11970 
11971 /********************  Bit definition for LTDC_LxWVPCR register  **************/
11972 
11973 #define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
11974 #define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */
11975 #define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
11976 #define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
11977 #define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */
11978 #define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
11979 
11980 /********************  Bit definition for LTDC_LxCKCR register  ***************/
11981 
11982 #define LTDC_LxCKCR_CKBLUE_Pos       (0U)
11983 #define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */
11984 #define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
11985 #define LTDC_LxCKCR_CKGREEN_Pos      (8U)
11986 #define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */
11987 #define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
11988 #define LTDC_LxCKCR_CKRED_Pos        (16U)
11989 #define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */
11990 #define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
11991 
11992 /********************  Bit definition for LTDC_LxPFCR register  ***************/
11993 
11994 #define LTDC_LxPFCR_PF_Pos           (0U)
11995 #define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */
11996 #define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
11997 
11998 /********************  Bit definition for LTDC_LxCACR register  ***************/
11999 
12000 #define LTDC_LxCACR_CONSTA_Pos       (0U)
12001 #define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */
12002 #define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
12003 
12004 /********************  Bit definition for LTDC_LxDCCR register  ***************/
12005 
12006 #define LTDC_LxDCCR_DCBLUE_Pos       (0U)
12007 #define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */
12008 #define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
12009 #define LTDC_LxDCCR_DCGREEN_Pos      (8U)
12010 #define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */
12011 #define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
12012 #define LTDC_LxDCCR_DCRED_Pos        (16U)
12013 #define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */
12014 #define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
12015 #define LTDC_LxDCCR_DCALPHA_Pos      (24U)
12016 #define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */
12017 #define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
12018 
12019 /********************  Bit definition for LTDC_LxBFCR register  ***************/
12020 
12021 #define LTDC_LxBFCR_BF2_Pos          (0U)
12022 #define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */
12023 #define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
12024 #define LTDC_LxBFCR_BF1_Pos          (8U)
12025 #define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */
12026 #define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
12027 
12028 /********************  Bit definition for LTDC_LxCFBAR register  **************/
12029 
12030 #define LTDC_LxCFBAR_CFBADD_Pos      (0U)
12031 #define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
12032 #define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
12033 
12034 /********************  Bit definition for LTDC_LxCFBLR register  **************/
12035 
12036 #define LTDC_LxCFBLR_CFBLL_Pos       (0U)
12037 #define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */
12038 #define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
12039 #define LTDC_LxCFBLR_CFBP_Pos        (16U)
12040 #define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */
12041 #define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
12042 
12043 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
12044 
12045 #define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
12046 #define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */
12047 #define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
12048 
12049 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
12050 
12051 #define LTDC_LxCLUTWR_BLUE_Pos       (0U)
12052 #define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */
12053 #define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
12054 #define LTDC_LxCLUTWR_GREEN_Pos      (8U)
12055 #define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */
12056 #define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
12057 #define LTDC_LxCLUTWR_RED_Pos        (16U)
12058 #define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */
12059 #define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
12060 #define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
12061 #define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */
12062 #define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
12063 
12064 /******************************************************************************/
12065 /*                                                                            */
12066 /*                                     MDMA                                   */
12067 /*                                                                            */
12068 /******************************************************************************/
12069 /********************  Bit definition for MDMA_GISR0 register  ****************/
12070 #define MDMA_GISR0_GIF0_Pos       (0U)
12071 #define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */
12072 #define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */
12073 #define MDMA_GISR0_GIF1_Pos       (1U)
12074 #define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */
12075 #define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */
12076 #define MDMA_GISR0_GIF2_Pos       (2U)
12077 #define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */
12078 #define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */
12079 #define MDMA_GISR0_GIF3_Pos       (3U)
12080 #define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */
12081 #define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */
12082 #define MDMA_GISR0_GIF4_Pos       (4U)
12083 #define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */
12084 #define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */
12085 #define MDMA_GISR0_GIF5_Pos       (5U)
12086 #define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */
12087 #define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */
12088 #define MDMA_GISR0_GIF6_Pos       (6U)
12089 #define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */
12090 #define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */
12091 #define MDMA_GISR0_GIF7_Pos       (7U)
12092 #define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */
12093 #define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */
12094 #define MDMA_GISR0_GIF8_Pos       (8U)
12095 #define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */
12096 #define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */
12097 #define MDMA_GISR0_GIF9_Pos       (9U)
12098 #define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */
12099 #define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */
12100 #define MDMA_GISR0_GIF10_Pos      (10U)
12101 #define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */
12102 #define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */
12103 #define MDMA_GISR0_GIF11_Pos      (11U)
12104 #define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */
12105 #define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */
12106 #define MDMA_GISR0_GIF12_Pos      (12U)
12107 #define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */
12108 #define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */
12109 #define MDMA_GISR0_GIF13_Pos      (13U)
12110 #define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */
12111 #define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */
12112 #define MDMA_GISR0_GIF14_Pos      (14U)
12113 #define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */
12114 #define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */
12115 #define MDMA_GISR0_GIF15_Pos      (15U)
12116 #define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */
12117 #define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */
12118 
12119 /********************  Bit definition for MDMA_CxISR register  ****************/
12120 #define MDMA_CISR_TEIF_Pos        (0U)
12121 #define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */
12122 #define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */
12123 #define MDMA_CISR_CTCIF_Pos       (1U)
12124 #define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */
12125 #define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */
12126 #define MDMA_CISR_BRTIF_Pos       (2U)
12127 #define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */
12128 #define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */
12129 #define MDMA_CISR_BTIF_Pos        (3U)
12130 #define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */
12131 #define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */
12132 #define MDMA_CISR_TCIF_Pos        (4U)
12133 #define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */
12134 #define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */
12135 #define MDMA_CISR_CRQA_Pos        (16U)
12136 #define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */
12137 #define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x request Active flag */
12138 
12139 /********************  Bit definition for MDMA_CxIFCR register  ****************/
12140 #define MDMA_CIFCR_CTEIF_Pos      (0U)
12141 #define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */
12142 #define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */
12143 #define MDMA_CIFCR_CCTCIF_Pos     (1U)
12144 #define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */
12145 #define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */
12146 #define MDMA_CIFCR_CBRTIF_Pos     (2U)
12147 #define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */
12148 #define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */
12149 #define MDMA_CIFCR_CBTIF_Pos      (3U)
12150 #define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */
12151 #define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */
12152 #define MDMA_CIFCR_CLTCIF_Pos     (4U)
12153 #define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */
12154 #define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
12155 
12156 /********************  Bit definition for MDMA_CxESR register  ****************/
12157 #define MDMA_CESR_TEA_Pos         (0U)
12158 #define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */
12159 #define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */
12160 #define MDMA_CESR_TED_Pos         (7U)
12161 #define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */
12162 #define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */
12163 #define MDMA_CESR_TELD_Pos        (8U)
12164 #define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */
12165 #define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */
12166 #define MDMA_CESR_TEMD_Pos        (9U)
12167 #define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */
12168 #define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */
12169 #define MDMA_CESR_ASE_Pos         (10U)
12170 #define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */
12171 #define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */
12172 #define MDMA_CESR_BSE_Pos         (11U)
12173 #define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */
12174 #define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */
12175 
12176 /********************  Bit definition for MDMA_CxCR register  ****************/
12177 #define MDMA_CCR_EN_Pos           (0U)
12178 #define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */
12179 #define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */
12180 #define MDMA_CCR_TEIE_Pos         (1U)
12181 #define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */
12182 #define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */
12183 #define MDMA_CCR_CTCIE_Pos        (2U)
12184 #define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */
12185 #define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */
12186 #define MDMA_CCR_BRTIE_Pos        (3U)
12187 #define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */
12188 #define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */
12189 #define MDMA_CCR_BTIE_Pos         (4U)
12190 #define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */
12191 #define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */
12192 #define MDMA_CCR_TCIE_Pos         (5U)
12193 #define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */
12194 #define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */
12195 #define MDMA_CCR_PL_Pos           (6U)
12196 #define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */
12197 #define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */
12198 #define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */
12199 #define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */
12200 #define MDMA_CCR_BEX_Pos          (12U)
12201 #define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */
12202 #define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianness eXchange */
12203 #define MDMA_CCR_HEX_Pos          (13U)
12204 #define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */
12205 #define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianness eXchange */
12206 #define MDMA_CCR_WEX_Pos          (14U)
12207 #define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */
12208 #define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianness eXchange */
12209 #define MDMA_CCR_SWRQ_Pos         (16U)
12210 #define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */
12211 #define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */
12212 
12213 /********************  Bit definition for MDMA_CxTCR register  ****************/
12214 #define MDMA_CTCR_SINC_Pos        (0U)
12215 #define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */
12216 #define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */
12217 #define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */
12218 #define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */
12219 #define MDMA_CTCR_DINC_Pos        (2U)
12220 #define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */
12221 #define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */
12222 #define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */
12223 #define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */
12224 #define MDMA_CTCR_SSIZE_Pos       (4U)
12225 #define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */
12226 #define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */
12227 #define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */
12228 #define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */
12229 #define MDMA_CTCR_DSIZE_Pos       (6U)
12230 #define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */
12231 #define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */
12232 #define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */
12233 #define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */
12234 #define MDMA_CTCR_SINCOS_Pos      (8U)
12235 #define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */
12236 #define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */
12237 #define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */
12238 #define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */
12239 #define MDMA_CTCR_DINCOS_Pos      (10U)
12240 #define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */
12241 #define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */
12242 #define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */
12243 #define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */
12244 #define MDMA_CTCR_SBURST_Pos      (12U)
12245 #define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */
12246 #define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */
12247 #define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */
12248 #define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */
12249 #define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */
12250 #define MDMA_CTCR_DBURST_Pos      (15U)
12251 #define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */
12252 #define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */
12253 #define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */
12254 #define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */
12255 #define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */
12256 #define MDMA_CTCR_TLEN_Pos        (18U)
12257 #define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */
12258 #define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */
12259 #define MDMA_CTCR_PKE_Pos         (25U)
12260 #define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */
12261 #define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */
12262 #define MDMA_CTCR_PAM_Pos         (26U)
12263 #define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */
12264 #define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignment Mode */
12265 #define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */
12266 #define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */
12267 #define MDMA_CTCR_TRGM_Pos        (28U)
12268 #define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */
12269 #define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */
12270 #define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */
12271 #define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */
12272 #define MDMA_CTCR_SWRM_Pos        (30U)
12273 #define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */
12274 #define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */
12275 #define MDMA_CTCR_BWM_Pos         (31U)
12276 #define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */
12277 #define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */
12278 
12279 /********************  Bit definition for MDMA_CxBNDTR register  ****************/
12280 #define MDMA_CBNDTR_BNDT_Pos      (0U)
12281 #define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */
12282 #define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */
12283 #define MDMA_CBNDTR_BRSUM_Pos     (18U)
12284 #define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */
12285 #define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */
12286 #define MDMA_CBNDTR_BRDUM_Pos     (19U)
12287 #define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */
12288 #define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */
12289 #define MDMA_CBNDTR_BRC_Pos       (20U)
12290 #define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */
12291 #define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */
12292 
12293 /********************  Bit definition for MDMA_CxSAR register  ****************/
12294 #define MDMA_CSAR_SAR_Pos         (0U)
12295 #define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */
12296 #define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */
12297 
12298 /********************  Bit definition for MDMA_CxDAR register  ****************/
12299 #define MDMA_CDAR_DAR_Pos         (0U)
12300 #define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */
12301 #define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */
12302 
12303 /********************  Bit definition for MDMA_CxBRUR  ************************/
12304 #define MDMA_CBRUR_SUV_Pos        (0U)
12305 #define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */
12306 #define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */
12307 #define MDMA_CBRUR_DUV_Pos        (16U)
12308 #define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */
12309 #define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */
12310 
12311 /********************  Bit definition for MDMA_CxLAR  *************************/
12312 #define MDMA_CLAR_LAR_Pos         (0U)
12313 #define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */
12314 #define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */
12315 
12316 /********************  Bit definition for MDMA_CxTBR)  ************************/
12317 #define MDMA_CTBR_TSEL_Pos        (0U)
12318 #define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */
12319 #define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */
12320 #define MDMA_CTBR_SBUS_Pos        (16U)
12321 #define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */
12322 #define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */
12323 #define MDMA_CTBR_DBUS_Pos        (17U)
12324 #define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */
12325 #define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */
12326 
12327 /********************  Bit definition for MDMA_CxMAR)  ************************/
12328 #define MDMA_CMAR_MAR_Pos         (0U)
12329 #define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */
12330 #define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */
12331 
12332 /********************  Bit definition for MDMA_CxMDR)  ************************/
12333 #define MDMA_CMDR_MDR_Pos         (0U)
12334 #define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */
12335 #define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */
12336 
12337 /******************************************************************************/
12338 /*                                                                            */
12339 /*                         Operational Amplifier (OPAMP)                      */
12340 /*                                                                            */
12341 /******************************************************************************/
12342 /*********************  Bit definition for OPAMPx_CSR register  ***************/
12343 #define OPAMP_CSR_OPAMPxEN_Pos           (0U)
12344 #define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
12345 #define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
12346 #define OPAMP_CSR_FORCEVP_Pos            (1U)
12347 #define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */
12348 #define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */
12349 
12350 #define OPAMP_CSR_VPSEL_Pos              (2U)
12351 #define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */
12352 #define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
12353 #define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */
12354 #define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */
12355 
12356 #define OPAMP_CSR_VMSEL_Pos              (5U)
12357 #define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */
12358 #define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
12359 #define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */
12360 #define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */
12361 
12362 #define OPAMP_CSR_OPAHSM_Pos             (8U)
12363 #define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */
12364 #define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */
12365 #define OPAMP_CSR_CALON_Pos              (11U)
12366 #define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */
12367 #define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
12368 
12369 #define OPAMP_CSR_CALSEL_Pos             (12U)
12370 #define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */
12371 #define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
12372 #define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */
12373 #define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
12374 
12375 #define OPAMP_CSR_PGGAIN_Pos             (14U)
12376 #define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */
12377 #define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
12378 #define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */
12379 #define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */
12380 #define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */
12381 #define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */
12382 
12383 #define OPAMP_CSR_USERTRIM_Pos           (18U)
12384 #define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */
12385 #define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
12386 #define OPAMP_CSR_TSTREF_Pos             (29U)
12387 #define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */
12388 #define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */
12389 #define OPAMP_CSR_CALOUT_Pos             (30U)
12390 #define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */
12391 #define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */
12392 
12393 /*********************  Bit definition for OPAMP1_CSR register  ***************/
12394 #define OPAMP1_CSR_OPAEN_Pos              (0U)
12395 #define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
12396 #define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
12397 #define OPAMP1_CSR_FORCEVP_Pos            (1U)
12398 #define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
12399 #define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
12400 
12401 #define OPAMP1_CSR_VPSEL_Pos              (2U)
12402 #define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */
12403 #define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
12404 #define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */
12405 #define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */
12406 
12407 #define OPAMP1_CSR_VMSEL_Pos              (5U)
12408 #define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */
12409 #define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
12410 #define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */
12411 #define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */
12412 
12413 #define OPAMP1_CSR_OPAHSM_Pos             (8U)
12414 #define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
12415 #define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */
12416 #define OPAMP1_CSR_CALON_Pos              (11U)
12417 #define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */
12418 #define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
12419 
12420 #define OPAMP1_CSR_CALSEL_Pos             (12U)
12421 #define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */
12422 #define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
12423 #define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */
12424 #define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
12425 
12426 #define OPAMP1_CSR_PGGAIN_Pos             (14U)
12427 #define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
12428 #define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */
12429 #define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
12430 #define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
12431 #define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
12432 #define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
12433 
12434 #define OPAMP1_CSR_USERTRIM_Pos           (18U)
12435 #define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
12436 #define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
12437 #define OPAMP1_CSR_TSTREF_Pos             (29U)
12438 #define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */
12439 #define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
12440 #define OPAMP1_CSR_CALOUT_Pos             (30U)
12441 #define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */
12442 #define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
12443 
12444 /*********************  Bit definition for OPAMP2_CSR register  ***************/
12445 #define OPAMP2_CSR_OPAEN_Pos              (0U)
12446 #define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */
12447 #define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
12448 #define OPAMP2_CSR_FORCEVP_Pos            (1U)
12449 #define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
12450 #define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
12451 
12452 #define OPAMP2_CSR_VPSEL_Pos              (2U)
12453 #define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */
12454 #define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
12455 #define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */
12456 #define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */
12457 
12458 #define OPAMP2_CSR_VMSEL_Pos              (5U)
12459 #define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */
12460 #define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
12461 #define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */
12462 #define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */
12463 
12464 #define OPAMP2_CSR_OPAHSM_Pos             (8U)
12465 #define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
12466 #define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */
12467 #define OPAMP2_CSR_CALON_Pos              (11U)
12468 #define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */
12469 #define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
12470 
12471 #define OPAMP2_CSR_CALSEL_Pos             (12U)
12472 #define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */
12473 #define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
12474 #define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */
12475 #define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
12476 
12477 #define OPAMP2_CSR_PGGAIN_Pos             (14U)
12478 #define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
12479 #define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */
12480 #define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
12481 #define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
12482 #define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
12483 #define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
12484 
12485 #define OPAMP2_CSR_USERTRIM_Pos           (18U)
12486 #define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
12487 #define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
12488 #define OPAMP2_CSR_TSTREF_Pos             (29U)
12489 #define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */
12490 #define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
12491 #define OPAMP2_CSR_CALOUT_Pos             (30U)
12492 #define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */
12493 #define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
12494 
12495 /*******************  Bit definition for OPAMP_OTR register  ******************/
12496 #define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
12497 #define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
12498 #define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
12499 #define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
12500 #define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
12501 #define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
12502 
12503 /*******************  Bit definition for OPAMP1_OTR register  ******************/
12504 #define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
12505 #define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
12506 #define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
12507 #define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
12508 #define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
12509 #define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
12510 
12511 /*******************  Bit definition for OPAMP2_OTR register  ******************/
12512 #define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
12513 #define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
12514 #define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
12515 #define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
12516 #define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
12517 #define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
12518 
12519 /*******************  Bit definition for OPAMP_HSOTR register  ****************/
12520 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
12521 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
12522 #define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
12523 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
12524 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
12525 #define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
12526 
12527 /*******************  Bit definition for OPAMP1_HSOTR register  ****************/
12528 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)
12529 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
12530 #define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
12531 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)
12532 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
12533 #define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
12534 
12535 /*******************  Bit definition for OPAMP2_HSOTR register  ****************/
12536 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)
12537 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
12538 #define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
12539 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)
12540 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
12541 #define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
12542 
12543 /******************************************************************************/
12544 /*                                                                            */
12545 /*                Parallel Synchronous Slave Interface (PSSI )                */
12546 /*                                                                            */
12547 /******************************************************************************/
12548 
12549 /********************  Bit definition for PSSI_CR register  *******************/
12550 #define PSSI_CR_OUTEN_Pos               (31U)
12551 #define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */
12552 #define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */
12553 #define PSSI_CR_DMAEN_Pos               (30U)
12554 #define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */
12555 #define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */
12556 #define PSSI_CR_DERDYCFG_Pos            (18U)
12557 #define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */
12558 #define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */
12559 #define PSSI_CR_ENABLE_Pos              (14U)
12560 #define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */
12561 #define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */
12562 #define PSSI_CR_EDM_Pos                 (10U)
12563 #define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */
12564 #define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */
12565 #define PSSI_CR_RDYPOL_Pos              (8U)
12566 #define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */
12567 #define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */
12568 #define PSSI_CR_DEPOL_Pos               (6U)
12569 #define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */
12570 #define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */
12571 #define PSSI_CR_CKPOL_Pos               (5U)
12572 #define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */
12573 #define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */
12574 /********************  Bit definition for PSSI_SR register  *******************/
12575 #define PSSI_SR_RTT1B_Pos               (3U)
12576 #define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */
12577 #define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */
12578 #define PSSI_SR_RTT4B_Pos               (2U)
12579 #define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */
12580 #define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */
12581 /********************  Bit definition for PSSI_RIS register  *******************/
12582 #define PSSI_RIS_OVR_RIS_Pos            (1U)
12583 #define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */
12584 #define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */
12585 /********************  Bit definition for PSSI_IER register  *******************/
12586 #define PSSI_IER_OVR_IE_Pos             (1U)
12587 #define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */
12588 #define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */
12589 /********************  Bit definition for PSSI_MIS register  *******************/
12590 #define PSSI_MIS_OVR_MIS_Pos            (1U)
12591 #define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */
12592 #define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */
12593 /********************  Bit definition for PSSI_ICR register  *******************/
12594 #define PSSI_ICR_OVR_ISC_Pos            (1U)
12595 #define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */
12596 #define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */
12597 /********************  Bit definition for PSSI_DR register  *******************/
12598 #define PSSI_DR_DR_Pos                  (0U)
12599 #define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */
12600 #define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */
12601 
12602 /******************************************************************************/
12603 /*                                                                            */
12604 /*                              On The Fly Decryption                         */
12605 /*                                                                            */
12606 /******************************************************************************/
12607 /******************  Bit definition for OTFDEC_CR register  ******************/
12608 #define OTFDEC_CR_ENC_Pos                      (0U)
12609 #define OTFDEC_CR_ENC_Msk                      (0x1UL << OTFDEC_CR_ENC_Pos)                  /*!< 0x00000001 */
12610 #define OTFDEC_CR_ENC                          OTFDEC_CR_ENC_Msk                             /*!< Encryption mode bit */
12611 
12612 /******************  Bit definition for OTFDEC_PRIVCFGR register  ************/
12613 #define OTFDEC_PRIVCFGR_PRIV_Pos               (0U)
12614 #define OTFDEC_PRIVCFGR_PRIV_Msk               (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)           /*!< 0x00000001 */
12615 #define OTFDEC_PRIVCFGR_PRIV                   OTFDEC_PRIVCFGR_PRIV_Msk                      /*!< Privileged access protection */
12616 
12617 /******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/
12618 #define OTFDEC_REG_CONFIGR_REG_EN_Pos          (0U)
12619 #define OTFDEC_REG_CONFIGR_REG_EN_Msk          (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)      /*!< 0x00000001 */
12620 #define OTFDEC_REG_CONFIGR_REG_EN              OTFDEC_REG_CONFIGR_REG_EN_Msk                 /*!< Region on-the-fly decryption enable */
12621 
12622 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos      (1U)
12623 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)  /*!< 0x00000002 */
12624 #define OTFDEC_REG_CONFIGR_CONFIGLOCK          OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk             /*!< Region config lock */
12625 
12626 #define OTFDEC_REG_CONFIGR_KEYLOCK_Pos         (2U)
12627 #define OTFDEC_REG_CONFIGR_KEYLOCK_Msk         (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)     /*!< 0x00000004 */
12628 #define OTFDEC_REG_CONFIGR_KEYLOCK             OTFDEC_REG_CONFIGR_KEYLOCK_Msk                /*!< Region key lock */
12629 
12630 #define OTFDEC_REG_CONFIGR_MODE_Pos            (4U)
12631 #define OTFDEC_REG_CONFIGR_MODE_Msk            (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000030 */
12632 #define OTFDEC_REG_CONFIGR_MODE                OTFDEC_REG_CONFIGR_MODE_Msk                   /*!< Region operating mode */
12633 #define OTFDEC_REG_CONFIGR_MODE_0              (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000010 */
12634 #define OTFDEC_REG_CONFIGR_MODE_1              (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000020 */
12635 
12636 #define OTFDEC_REG_CONFIGR_KEYCRC_Pos          (8U)
12637 #define OTFDEC_REG_CONFIGR_KEYCRC_Msk          (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)     /*!< 0x0000FF00 */
12638 #define OTFDEC_REG_CONFIGR_KEYCRC              OTFDEC_REG_CONFIGR_KEYCRC_Msk                 /*!< Region key 8-bit CRC */
12639 
12640 #define OTFDEC_REG_CONFIGR_VERSION_Pos         (16U)
12641 #define OTFDEC_REG_CONFIGR_VERSION_Msk         (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)  /*!< 0xFFFF0000 */
12642 #define OTFDEC_REG_CONFIGR_VERSION             OTFDEC_REG_CONFIGR_VERSION_Msk                /*!< Region firmware version */
12643 
12644 /******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/
12645 #define OTFDEC_REG_START_ADDR_Pos              (0U)
12646 #define OTFDEC_REG_START_ADDR_Msk              (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)   /*!< 0xFFFFFFFF */
12647 #define OTFDEC_REG_START_ADDR                  OTFDEC_REG_START_ADDR_Msk                     /*!< Region AHB start address */
12648 
12649 /******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/
12650 #define OTFDEC_REG_END_ADDR_Pos                (0U)
12651 #define OTFDEC_REG_END_ADDR_Msk                (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)     /*!< 0xFFFFFFFF */
12652 #define OTFDEC_REG_END_ADDR                    OTFDEC_REG_END_ADDR_Msk                       /*!< Region AHB end address */
12653 
12654 /******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/
12655 #define OTFDEC_REG_NONCER0_Pos                 (0U)
12656 #define OTFDEC_REG_NONCER0_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)      /*!< 0xFFFFFFFF */
12657 #define OTFDEC_REG_NONCER0                     OTFDEC_REG_NONCER0_Msk                        /*!< Region Nonce Register (LSB nonce[31:0]) */
12658 
12659 /******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/
12660 #define OTFDEC_REG_NONCER1_Pos                 (0U)
12661 #define OTFDEC_REG_NONCER1_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)      /*!< 0xFFFFFFFF */
12662 #define OTFDEC_REG_NONCER1                     OTFDEC_REG_NONCER1_Msk                        /*!< Region Nonce Register (MSB nonce[63:32]) */
12663 
12664 /******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/
12665 #define OTFDEC_REG_KEYR0_Pos                   (0U)
12666 #define OTFDEC_REG_KEYR0_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)        /*!< 0xFFFFFFFF */
12667 #define OTFDEC_REG_KEYR0                       OTFDEC_REG_KEYR0_Msk                          /*!< Region Key Register (LSB key[31:0]) */
12668 
12669 /******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/
12670 #define OTFDEC_REG_KEYR1_Pos                   (0U)
12671 #define OTFDEC_REG_KEYR1_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)        /*!< 0xFFFFFFFF */
12672 #define OTFDEC_REG_KEYR1                       OTFDEC_REG_KEYR1_Msk                          /*!< Region Key Register (key[63:32]) */
12673 
12674 /******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/
12675 #define OTFDEC_REG_KEYR2_Pos                   (0U)
12676 #define OTFDEC_REG_KEYR2_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)        /*!< 0xFFFFFFFF */
12677 #define OTFDEC_REG_KEYR2                       OTFDEC_REG_KEYR2_Msk                          /*!< Region Key Register (key[95:64]) */
12678 
12679 /******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/
12680 #define OTFDEC_REG_KEYR3_Pos                   (0U)
12681 #define OTFDEC_REG_KEYR3_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)        /*!< 0xFFFFFFFF */
12682 #define OTFDEC_REG_KEYR3                       OTFDEC_REG_KEYR3_Msk                          /*!< Region Key Register (key[127:96]) */
12683 
12684 /******************  Bit definition for OTFDEC_ISR register  *****************/
12685 #define OTFDEC_ISR_SEIF_Pos                    (0U)
12686 #define OTFDEC_ISR_SEIF_Msk                    (0x1UL << OTFDEC_ISR_SEIF_Pos)                /*!< 0x00000001 */
12687 #define OTFDEC_ISR_SEIF                        OTFDEC_ISR_SEIF_Msk                           /*!< Security Error Interrupt Flag status bit before enable (mask) */
12688 
12689 #define OTFDEC_ISR_XONEIF_Pos                  (1U)
12690 #define OTFDEC_ISR_XONEIF_Msk                  (0x1UL << OTFDEC_ISR_XONEIF_Pos)              /*!< 0x00000002 */
12691 #define OTFDEC_ISR_XONEIF                      OTFDEC_ISR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */
12692 
12693 #define OTFDEC_ISR_KEIF_Pos                    (2U)
12694 #define OTFDEC_ISR_KEIF_Msk                    (0x1UL << OTFDEC_ISR_KEIF_Pos)                /*!< 0x00000004 */
12695 #define OTFDEC_ISR_KEIF                        OTFDEC_ISR_KEIF_Msk                           /*!< Key Error Interrupt Flag status bit before enable (mask) */
12696 
12697 /******************  Bit definition  for OTFDEC_ICR register  *****************/
12698 #define OTFDEC_ICR_SEIF_Pos                    (0U)
12699 #define OTFDEC_ICR_SEIF_Msk                    (0x1UL << OTFDEC_ICR_SEIF_Pos)                /*!< 0x00000001 */
12700 #define OTFDEC_ICR_SEIF                        OTFDEC_ICR_SEIF_Msk                           /*!< Security Error Interrupt Flag clear bit */
12701 
12702 #define OTFDEC_ICR_XONEIF_Pos                  (1U)
12703 #define OTFDEC_ICR_XONEIF_Msk                  (0x1UL << OTFDEC_ICR_XONEIF_Pos)              /*!< 0x00000002 */
12704 #define OTFDEC_ICR_XONEIF                      OTFDEC_ICR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag clear bit */
12705 
12706 #define OTFDEC_ICR_KEIF_Pos                    (2U)
12707 #define OTFDEC_ICR_KEIF_Msk                    (0x1UL << OTFDEC_ICR_KEIF_Pos)                /*!< 0x00000004 */
12708 #define OTFDEC_ICR_KEIF                        OTFDEC_ICR_KEIF_Msk                           /*!< Key Error Interrupt Flag clear bit */
12709 
12710 /******************  Bit definition for OTFDEC_IER register  *****************/
12711 #define OTFDEC_IER_SEIE_Pos                    (0U)
12712 #define OTFDEC_IER_SEIE_Msk                    (0x1UL << OTFDEC_IER_SEIE_Pos)                /*!< 0x00000001 */
12713 #define OTFDEC_IER_SEIE                        OTFDEC_IER_SEIE_Msk                           /*!< Security Error Interrupt Enable bit */
12714 
12715 #define OTFDEC_IER_XONEIE_Pos                  (1U)
12716 #define OTFDEC_IER_XONEIE_Msk                  (0x1UL << OTFDEC_IER_XONEIE_Pos)              /*!< 0x00000002 */
12717 #define OTFDEC_IER_XONEIE                      OTFDEC_IER_XONEIE_Msk                         /*!< Execute-only Error Interrupt Enable bit */
12718 
12719 #define OTFDEC_IER_KEIE_Pos                    (2U)
12720 #define OTFDEC_IER_KEIE_Msk                    (0x1UL << OTFDEC_IER_KEIE_Pos)                /*!< 0x00000004 */
12721 #define OTFDEC_IER_KEIE                        OTFDEC_IER_KEIE_Msk
12722 
12723 /******************************************************************************/
12724 /*                                                                            */
12725 /*                             Power Control                                  */
12726 /*                                                                            */
12727 /******************************************************************************/
12728 /*************************  NUMBER OF POWER DOMAINS  **************************/
12729 #define POWER_DOMAINS_NUMBER           2U                                      /*!< 2 Domains */
12730 
12731 /********************  Bit definition for PWR_CR1 register  *******************/
12732 #define PWR_CR1_SRDRAMSO_Pos           (27U)
12733 #define PWR_CR1_SRDRAMSO_Msk           (0x1UL << PWR_CR1_SRDRAMSO_Pos)         /*!< 0x08000000 */
12734 #define PWR_CR1_SRDRAMSO               PWR_CR1_SRDRAMSO_Msk                    /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */
12735 #define PWR_CR1_HSITFSO_Pos            (26U)
12736 #define PWR_CR1_HSITFSO_Msk            (0x1UL << PWR_CR1_HSITFSO_Pos)          /*!< 0x04000000 */
12737 #define PWR_CR1_HSITFSO                PWR_CR1_HSITFSO_Msk                     /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */
12738 #define PWR_CR1_GFXSO_Pos              (25U)
12739 #define PWR_CR1_GFXSO_Msk              (0x1UL << PWR_CR1_GFXSO_Pos)            /*!< 0x02000000 */
12740 #define PWR_CR1_GFXSO                  PWR_CR1_GFXSO_Msk                       /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */
12741 #define PWR_CR1_ITCMSO_Pos             (24U)
12742 #define PWR_CR1_ITCMSO_Msk             (0x1UL << PWR_CR1_ITCMSO_Pos)           /*!< 0x01000000 */
12743 #define PWR_CR1_ITCMSO                 PWR_CR1_ITCMSO_Msk                      /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */
12744 #define PWR_CR1_AHBRAM2SO_Pos          (23U)
12745 #define PWR_CR1_AHBRAM2SO_Msk          (0x1UL << PWR_CR1_AHBRAM2SO_Pos)        /*!< 0x00800000 */
12746 #define PWR_CR1_AHBRAM2SO              PWR_CR1_AHBRAM2SO_Msk                   /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */
12747 #define PWR_CR1_AHBRAM1SO_Pos          (22U)
12748 #define PWR_CR1_AHBRAM1SO_Msk          (0x1UL << PWR_CR1_AHBRAM1SO_Pos)        /*!< 0x00400000 */
12749 #define PWR_CR1_AHBRAM1SO              PWR_CR1_AHBRAM1SO_Msk                   /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */
12750 #define PWR_CR1_AXIRAM3SO_Pos          (21U)
12751 #define PWR_CR1_AXIRAM3SO_Msk          (0x1UL << PWR_CR1_AXIRAM3SO_Pos)        /*!< 0x00200000 */
12752 #define PWR_CR1_AXIRAM3SO              PWR_CR1_AXIRAM3SO_Msk                   /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */
12753 #define PWR_CR1_AXIRAM2SO_Pos          (20U)
12754 #define PWR_CR1_AXIRAM2SO_Msk          (0x1UL << PWR_CR1_AXIRAM2SO_Pos)        /*!< 0x00100000 */
12755 #define PWR_CR1_AXIRAM2SO              PWR_CR1_AXIRAM2SO_Msk                   /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */
12756 #define PWR_CR1_AXIRAM1SO_Pos          (19U)
12757 #define PWR_CR1_AXIRAM1SO_Msk          (0x1UL << PWR_CR1_AXIRAM1SO_Pos)        /*!< 0x00080000 */
12758 #define PWR_CR1_AXIRAM1SO              PWR_CR1_AXIRAM1SO_Msk                   /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */
12759 #define PWR_CR1_ALS_Pos                (17U)
12760 #define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */
12761 #define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
12762 #define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */
12763 #define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */
12764 #define PWR_CR1_AVDEN_Pos              (16U)
12765 #define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */
12766 #define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */
12767 #define PWR_CR1_SVOS_Pos               (14U)
12768 #define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */
12769 #define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */
12770 #define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */
12771 #define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */
12772 #define PWR_CR1_AVD_READY_Pos          (13U)
12773 #define PWR_CR1_AVD_READY_Msk          (0x1UL << PWR_CR1_AVD_READY_Pos)        /*!< 0x00002000 */
12774 #define PWR_CR1_AVD_READY              PWR_CR1_AVD_READY_Msk                   /*!< Analog Voltage Ready. */
12775 #define PWR_CR1_BOOSTE_Pos             (12U)
12776 #define PWR_CR1_BOOSTE_Msk             (0x1UL << PWR_CR1_BOOSTE_Pos)           /*!< 0x00001000 */
12777 #define PWR_CR1_BOOSTE                 PWR_CR1_BOOSTE_Msk                      /*!< Analog Switch VBoost control */
12778 #define PWR_CR1_FLPS_Pos               (9U)
12779 #define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */
12780 #define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */
12781 #define PWR_CR1_DBP_Pos                (8U)
12782 #define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
12783 #define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */
12784 #define PWR_CR1_PLS_Pos                (5U)
12785 #define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */
12786 #define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
12787 #define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */
12788 #define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */
12789 #define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */
12790 #define PWR_CR1_PVDEN_Pos              (4U)
12791 #define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */
12792 #define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
12793 #define PWR_CR1_LPDS_Pos               (0U)
12794 #define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */
12795 #define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */
12796 
12797 /*!< PVD level configuration */
12798 #define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */
12799 #define PWR_CR1_PLS_LEV1_Pos           (5U)
12800 #define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */
12801 #define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */
12802 #define PWR_CR1_PLS_LEV2_Pos           (6U)
12803 #define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */
12804 #define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */
12805 #define PWR_CR1_PLS_LEV3_Pos           (5U)
12806 #define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */
12807 #define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */
12808 #define PWR_CR1_PLS_LEV4_Pos           (7U)
12809 #define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */
12810 #define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */
12811 #define PWR_CR1_PLS_LEV5_Pos           (5U)
12812 #define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */
12813 #define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */
12814 #define PWR_CR1_PLS_LEV6_Pos           (6U)
12815 #define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */
12816 #define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */
12817 #define PWR_CR1_PLS_LEV7_Pos           (5U)
12818 #define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */
12819 #define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */
12820 
12821 /*!< AVD level configuration */
12822 #define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */
12823 #define PWR_CR1_ALS_LEV1_Pos           (17U)
12824 #define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */
12825 #define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */
12826 #define PWR_CR1_ALS_LEV2_Pos           (18U)
12827 #define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */
12828 #define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */
12829 #define PWR_CR1_ALS_LEV3_Pos           (17U)
12830 #define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */
12831 #define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */
12832 
12833 /********************  Bit definition for PWR_CSR1 register  ******************/
12834 #define PWR_CSR1_MMCVDO_Pos            (17U)
12835 #define PWR_CSR1_MMCVDO_Msk            (0x1UL << PWR_CSR1_MMCVDO_Pos)          /*!< 0x00020000                        */
12836 #define PWR_CSR1_MMCVDO                PWR_CSR1_MMCVDO_Msk                     /*!< voltage detector output on VDDMMC */
12837 #define PWR_CSR1_AVDO_Pos              (16U)
12838 #define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */
12839 #define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */
12840 #define PWR_CSR1_ACTVOS_Pos            (14U)
12841 #define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */
12842 #define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */
12843 #define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */
12844 #define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */
12845 #define PWR_CSR1_ACTVOSRDY_Pos         (13U)
12846 #define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */
12847 #define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */
12848 #define PWR_CSR1_PVDO_Pos              (4U)
12849 #define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */
12850 #define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */
12851 
12852 /********************  Bit definition for PWR_CR2 register  *******************/
12853 #define PWR_CR2_TEMPH_Pos              (23U)
12854 #define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */
12855 #define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */
12856 #define PWR_CR2_TEMPL_Pos              (22U)
12857 #define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */
12858 #define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */
12859 #define PWR_CR2_VBATH_Pos              (21U)
12860 #define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */
12861 #define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */
12862 #define PWR_CR2_VBATL_Pos              (20U)
12863 #define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */
12864 #define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */
12865 #define PWR_CR2_BRRDY_Pos              (16U)
12866 #define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */
12867 #define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */
12868 #define PWR_CR2_MONEN_Pos              (4U)
12869 #define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */
12870 #define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */
12871 #define PWR_CR2_BREN_Pos               (0U)
12872 #define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */
12873 #define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */
12874 
12875 /********************  Bit definition for PWR_CR3 register  *******************/
12876 #define PWR_CR3_USB33RDY_Pos           (26U)
12877 #define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */
12878 #define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */
12879 #define PWR_CR3_USBREGEN_Pos           (25U)
12880 #define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */
12881 #define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */
12882 #define PWR_CR3_USB33DEN_Pos           (24U)
12883 #define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */
12884 #define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */
12885 #define PWR_CR3_VBRS_Pos               (9U)
12886 #define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */
12887 #define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */
12888 #define PWR_CR3_VBE_Pos                (8U)
12889 #define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */
12890 #define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */
12891 #define PWR_CR3_SCUEN_Pos              (2U)
12892 #define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */
12893 #define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */
12894 #define PWR_CR3_LDOEN_Pos              (1U)
12895 #define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */
12896 #define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */
12897 #define PWR_CR3_BYPASS_Pos             (0U)
12898 #define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */
12899 #define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */
12900 
12901 /********************  Bit definition for PWR_CPUCR register  *****************/
12902 #define PWR_CPUCR_RUN_SRD_Pos          (11U)
12903 #define PWR_CPUCR_RUN_SRD_Msk          (0x1UL << PWR_CPUCR_RUN_SRD_Pos)        /*!< 0x00000800 */
12904 #define PWR_CPUCR_RUN_SRD              PWR_CPUCR_RUN_SRD_Msk                   /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */
12905 #define PWR_CPUCR_CSSF_Pos             (9U)
12906 #define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */
12907 #define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
12908 #define PWR_CPUCR_SBF_Pos              (6U)
12909 #define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */
12910 #define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */
12911 #define PWR_CPUCR_STOPF_Pos            (5U)
12912 #define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */
12913 #define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */
12914 #define PWR_CPUCR_PDDS_SRD_Pos         (2U)
12915 #define PWR_CPUCR_PDDS_SRD_Msk         (0x1UL << PWR_CPUCR_PDDS_SRD_Pos)       /*!< 0x00000004 */
12916 #define PWR_CPUCR_PDDS_SRD             PWR_CPUCR_PDDS_SRD_Msk                  /*!< System SRD domain Power Down Deepsleep */
12917 #define PWR_CPUCR_RETDS_CD_Pos         (0U)
12918 #define PWR_CPUCR_RETDS_CD_Msk         (0x1UL << PWR_CPUCR_RETDS_CD_Pos)       /*!< 0x00000001 */
12919 #define PWR_CPUCR_RETDS_CD             PWR_CPUCR_RETDS_CD_Msk                  /*!< CD domain Power Down Deepsleep selection */
12920 /********************  Bit definition for PWR_SRDCR register  *****************/
12921 #define PWR_SRDCR_VOS_Pos              (14U)
12922 #define PWR_SRDCR_VOS_Msk              (0x3UL << PWR_SRDCR_VOS_Pos)             /*!< 0x0000C000 */
12923 #define PWR_SRDCR_VOS                  PWR_SRDCR_VOS_Msk                        /*!< Voltage Scaling selection according performance */
12924 #define PWR_SRDCR_VOS_0                (0x1UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00004000 */
12925 #define PWR_SRDCR_VOS_1                (0x2UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00008000 */
12926 #define PWR_SRDCR_VOSRDY_Pos           (13U)
12927 #define PWR_SRDCR_VOSRDY_Msk           (0x1UL << PWR_SRDCR_VOSRDY_Pos)          /*!< 0x00002000 */
12928 #define PWR_SRDCR_VOSRDY               PWR_SRDCR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
12929 /******************  Bit definition for PWR_WKUPCR register  ******************/
12930 #define PWR_WKUPCR_WKUPC6_Pos          (5U)
12931 #define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */
12932 #define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */
12933 #define PWR_WKUPCR_WKUPC5_Pos          (4U)
12934 #define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */
12935 #define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */
12936 #define PWR_WKUPCR_WKUPC4_Pos          (3U)
12937 #define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */
12938 #define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */
12939 #define PWR_WKUPCR_WKUPC3_Pos          (2U)
12940 #define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */
12941 #define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
12942 #define PWR_WKUPCR_WKUPC2_Pos          (1U)
12943 #define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */
12944 #define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
12945 #define PWR_WKUPCR_WKUPC1_Pos          (0U)
12946 #define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */
12947 #define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
12948 
12949 /********************  Bit definition for PWR_WKUPFR register  ****************/
12950 #define PWR_WKUPFR_WKUPF6_Pos          (5U)
12951 #define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */
12952 #define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */
12953 #define PWR_WKUPFR_WKUPF5_Pos          (4U)
12954 #define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */
12955 #define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */
12956 #define PWR_WKUPFR_WKUPF4_Pos          (3U)
12957 #define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */
12958 #define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */
12959 #define PWR_WKUPFR_WKUPF3_Pos          (2U)
12960 #define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */
12961 #define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
12962 #define PWR_WKUPFR_WKUPF2_Pos          (1U)
12963 #define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */
12964 #define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
12965 #define PWR_WKUPFR_WKUPF1_Pos          (0U)
12966 #define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */
12967 #define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
12968 
12969 /******************  Bit definition for PWR_WKUPEPR register  *****************/
12970 #define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)
12971 #define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */
12972 #define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */
12973 #define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */
12974 #define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */
12975 #define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)
12976 #define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */
12977 #define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */
12978 #define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */
12979 #define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */
12980 #define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
12981 #define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */
12982 #define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */
12983 #define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */
12984 #define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */
12985 #define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
12986 #define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */
12987 #define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */
12988 #define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */
12989 #define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */
12990 #define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
12991 #define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */
12992 #define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */
12993 #define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */
12994 #define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */
12995 #define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
12996 #define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */
12997 #define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */
12998 #define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */
12999 #define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */
13000 #define PWR_WKUPEPR_WKUPP6_Pos         (13U)
13001 #define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */
13002 #define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */
13003 #define PWR_WKUPEPR_WKUPP5_Pos         (12U)
13004 #define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */
13005 #define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */
13006 #define PWR_WKUPEPR_WKUPP4_Pos         (11U)
13007 #define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */
13008 #define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */
13009 #define PWR_WKUPEPR_WKUPP3_Pos         (10U)
13010 #define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */
13011 #define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */
13012 #define PWR_WKUPEPR_WKUPP2_Pos         (9U)
13013 #define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */
13014 #define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */
13015 #define PWR_WKUPEPR_WKUPP1_Pos         (8U)
13016 #define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */
13017 #define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */
13018 #define PWR_WKUPEPR_WKUPEN6_Pos        (5U)
13019 #define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */
13020 #define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */
13021 #define PWR_WKUPEPR_WKUPEN5_Pos        (4U)
13022 #define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */
13023 #define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */
13024 #define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
13025 #define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */
13026 #define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */
13027 #define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
13028 #define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */
13029 #define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */
13030 #define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
13031 #define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */
13032 #define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */
13033 #define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
13034 #define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */
13035 #define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */
13036 #define PWR_WKUPEPR_WKUPEN_Pos         (0U)
13037 #define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */
13038 #define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */
13039 
13040 /******************************************************************************/
13041 /*                                                                            */
13042 /*                         Reset and Clock Control                            */
13043 /*                                                                            */
13044 /******************************************************************************/
13045 /*******************************  RCC VERSION  ********************************/
13046 #define RCC_VER_2_0
13047 
13048 /********************  Bit definition for RCC_CR register  ********************/
13049 #define RCC_CR_HSION_Pos                       (0U)
13050 #define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */
13051 #define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */
13052 #define RCC_CR_HSIKERON_Pos                    (1U)
13053 #define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */
13054 #define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */
13055 #define RCC_CR_HSIRDY_Pos                      (2U)
13056 #define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */
13057 #define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */
13058 #define RCC_CR_HSIDIV_Pos                      (3U)
13059 #define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */
13060 #define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */
13061 #define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */
13062 #define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */
13063 #define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */
13064 #define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */
13065 
13066 #define RCC_CR_HSIDIVF_Pos                     (5U)
13067 #define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */
13068 #define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */
13069 #define RCC_CR_CSION_Pos                       (7U)
13070 #define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */
13071 #define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */
13072 #define RCC_CR_CSIRDY_Pos                      (8U)
13073 #define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */
13074 #define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */
13075 #define RCC_CR_CSIKERON_Pos                    (9U)
13076 #define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */
13077 #define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
13078 #define RCC_CR_HSI48ON_Pos                     (12U)
13079 #define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */
13080 #define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */
13081 #define RCC_CR_HSI48RDY_Pos                    (13U)
13082 #define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */
13083 #define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */
13084 
13085 #define RCC_CR_CPUCKRDY_Pos                     (14U)
13086 #define RCC_CR_CPUCKRDY_Msk                     (0x1UL << RCC_CR_CPUCKRDY_Pos)   /*!< 0x00004000 */
13087 #define RCC_CR_CPUCKRDY                         RCC_CR_CPUCKRDY_Msk              /*!< CPU domain clocks ready flag  */
13088 #define RCC_CR_CDCKRDY_Pos                     (15U)
13089 #define RCC_CR_CDCKRDY_Msk                     (0x1UL << RCC_CR_CDCKRDY_Pos)   /*!< 0x00008000 */
13090 #define RCC_CR_CDCKRDY                         RCC_CR_CDCKRDY_Msk              /*!< CD domain clocks ready flag */
13091 
13092 #define RCC_CR_HSEON_Pos                       (16U)
13093 #define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */
13094 #define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */
13095 #define RCC_CR_HSERDY_Pos                      (17U)
13096 #define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */
13097 #define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */
13098 #define RCC_CR_HSEBYP_Pos                      (18U)
13099 #define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */
13100 #define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */
13101 #define RCC_CR_CSSHSEON_Pos                    (19U)
13102 #define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */
13103 #define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */
13104 
13105 #define RCC_CR_HSEEXT_Pos                    (20U)
13106 #define RCC_CR_HSEEXT_Msk                    (0x1UL << RCC_CR_HSEEXT_Pos)  /*!< 0x00080000 */
13107 #define RCC_CR_HSEEXT                        RCC_CR_HSEEXT_Msk             /*!< HSE Clock security System enable */
13108 
13109 #define RCC_CR_PLL1ON_Pos                      (24U)
13110 #define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */
13111 #define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */
13112 #define RCC_CR_PLL1RDY_Pos                     (25U)
13113 #define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */
13114 #define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */
13115 #define RCC_CR_PLL2ON_Pos                      (26U)
13116 #define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */
13117 #define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */
13118 #define RCC_CR_PLL2RDY_Pos                     (27U)
13119 #define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */
13120 #define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */
13121 #define RCC_CR_PLL3ON_Pos                      (28U)
13122 #define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */
13123 #define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */
13124 #define RCC_CR_PLL3RDY_Pos                     (29U)
13125 #define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */
13126 #define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */
13127 
13128 /*Legacy */
13129 #define RCC_CR_PLLON_Pos                       (24U)
13130 #define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */
13131 #define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */
13132 #define RCC_CR_PLLRDY_Pos                      (25U)
13133 #define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */
13134 #define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */
13135 
13136 /********************  Bit definition for RCC_HSICFGR register  ***************/
13137 /*!< HSICAL configuration */
13138 #define RCC_HSICFGR_HSICAL_Pos                 (0U)
13139 #define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
13140 #define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */
13141 #define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
13142 #define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
13143 #define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
13144 #define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
13145 #define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
13146 #define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
13147 #define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
13148 #define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
13149 #define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
13150 #define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
13151 #define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
13152 #define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
13153 
13154 /*!< HSITRIM configuration */
13155 #define RCC_HSICFGR_HSITRIM_Pos                (24U)
13156 #define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
13157 #define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */
13158 #define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
13159 #define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
13160 #define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
13161 #define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
13162 #define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
13163 #define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
13164 #define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
13165 
13166 
13167 /********************  Bit definition for RCC_CRRCR register  *****************/
13168 
13169 /*!< HSI48CAL configuration */
13170 #define RCC_CRRCR_HSI48CAL_Pos                 (0U)
13171 #define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
13172 #define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */
13173 #define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
13174 #define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
13175 #define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
13176 #define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
13177 #define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
13178 #define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
13179 #define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
13180 #define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
13181 #define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
13182 #define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
13183 
13184 
13185 /********************  Bit definition for RCC_CSICFGR register  *****************/
13186 /*!< CSICAL configuration */
13187 #define RCC_CSICFGR_CSICAL_Pos                 (0U)
13188 #define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
13189 #define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */
13190 #define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
13191 #define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
13192 #define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
13193 #define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
13194 #define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
13195 #define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
13196 #define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
13197 #define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
13198 
13199 /*!< CSITRIM configuration */
13200 #define RCC_CSICFGR_CSITRIM_Pos                (24U)
13201 #define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
13202 #define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */
13203 #define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
13204 #define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
13205 #define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
13206 #define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
13207 #define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
13208 #define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
13209 
13210 /********************  Bit definition for RCC_CFGR register  ******************/
13211 /*!< SW configuration */
13212 #define RCC_CFGR_SW_Pos                        (0U)
13213 #define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */
13214 #define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */
13215 #define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
13216 #define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
13217 #define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */
13218 
13219 #define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */
13220 #define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */
13221 #define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */
13222 #define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */
13223 
13224 /*!< SWS configuration */
13225 #define RCC_CFGR_SWS_Pos                       (3U)
13226 #define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */
13227 #define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */
13228 #define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
13229 #define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */
13230 #define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */
13231 
13232 #define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */
13233 #define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */
13234 #define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */
13235 #define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */
13236 
13237 #define RCC_CFGR_STOPWUCK_Pos                  (6U)
13238 #define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */
13239 #define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */
13240 
13241 #define RCC_CFGR_STOPKERWUCK_Pos               (7U)
13242 #define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */
13243 #define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */
13244 
13245 /*!< RTCPRE configuration */
13246 #define RCC_CFGR_RTCPRE_Pos                    (8U)
13247 #define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)
13248 #define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */
13249 #define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */
13250 #define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */
13251 #define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */
13252 #define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */
13253 #define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */
13254 #define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */
13255 
13256 
13257 /*!< TIMPRE configuration */
13258 #define RCC_CFGR_TIMPRE_Pos                    (15U)
13259 #define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)
13260 #define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */
13261 
13262 /*!< MCO1 configuration */
13263 #define RCC_CFGR_MCO1_Pos                      (22U)
13264 #define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)
13265 #define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */
13266 #define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */
13267 #define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */
13268 #define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */
13269 
13270 #define RCC_CFGR_MCO1PRE_Pos                   (18U)
13271 #define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)
13272 #define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */
13273 #define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */
13274 #define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */
13275 #define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */
13276 #define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */
13277 
13278 #define RCC_CFGR_MCO2PRE_Pos                   (25U)
13279 #define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)
13280 #define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */
13281 #define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */
13282 #define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */
13283 #define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */
13284 #define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */
13285 
13286 #define RCC_CFGR_MCO2_Pos                      (29U)
13287 #define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)
13288 #define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */
13289 #define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */
13290 #define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */
13291 #define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */
13292 
13293 /********************  Bit definition for RCC_D1CFGR register  ******************/
13294 /*!< D1HPRE configuration */
13295 #define RCC_CDCFGR1_HPRE_Pos                    (0U)
13296 #define RCC_CDCFGR1_HPRE_Msk                    (0xFUL << RCC_CDCFGR1_HPRE_Pos)  /*!< 0x0000000F */
13297 #define RCC_CDCFGR1_HPRE                        RCC_CDCFGR1_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */
13298 #define RCC_CDCFGR1_HPRE_0                      (0x1UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000001 */
13299 #define RCC_CDCFGR1_HPRE_1                      (0x2UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000002 */
13300 #define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */
13301 #define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */
13302 
13303 #define RCC_CDCFGR1_HPRE_DIV1                   (0U)                 /*!< AHB3 Clock not divided */
13304 #define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)
13305 #define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */
13306 #define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */
13307 #define RCC_CDCFGR1_HPRE_DIV4_Pos               (0U)
13308 #define RCC_CDCFGR1_HPRE_DIV4_Msk               (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos)   /*!< 0x00000009 */
13309 #define RCC_CDCFGR1_HPRE_DIV4                   RCC_CDCFGR1_HPRE_DIV4_Msk              /*!< AHB3 Clock divided by 4 */
13310 #define RCC_CDCFGR1_HPRE_DIV8_Pos               (1U)
13311 #define RCC_CDCFGR1_HPRE_DIV8_Msk               (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos)   /*!< 0x0000000A */
13312 #define RCC_CDCFGR1_HPRE_DIV8                   RCC_CDCFGR1_HPRE_DIV8_Msk              /*!< AHB3 Clock divided by 8 */
13313 #define RCC_CDCFGR1_HPRE_DIV16_Pos              (0U)
13314 #define RCC_CDCFGR1_HPRE_DIV16_Msk              (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos)  /*!< 0x0000000B */
13315 #define RCC_CDCFGR1_HPRE_DIV16                  RCC_CDCFGR1_HPRE_DIV16_Msk             /*!< AHB3 Clock divided by 16 */
13316 #define RCC_CDCFGR1_HPRE_DIV64_Pos              (2U)
13317 #define RCC_CDCFGR1_HPRE_DIV64_Msk              (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos)  /*!< 0x0000000C */
13318 #define RCC_CDCFGR1_HPRE_DIV64                  RCC_CDCFGR1_HPRE_DIV64_Msk             /*!< AHB3 Clock divided by 64 */
13319 #define RCC_CDCFGR1_HPRE_DIV128_Pos             (0U)
13320 #define RCC_CDCFGR1_HPRE_DIV128_Msk             (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */
13321 #define RCC_CDCFGR1_HPRE_DIV128                 RCC_CDCFGR1_HPRE_DIV128_Msk            /*!< AHB3 Clock divided by 128 */
13322 #define RCC_CDCFGR1_HPRE_DIV256_Pos             (1U)
13323 #define RCC_CDCFGR1_HPRE_DIV256_Msk             (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */
13324 #define RCC_CDCFGR1_HPRE_DIV256                 RCC_CDCFGR1_HPRE_DIV256_Msk            /*!< AHB3 Clock divided by 256 */
13325 #define RCC_CDCFGR1_HPRE_DIV512_Pos             (0U)
13326 #define RCC_CDCFGR1_HPRE_DIV512_Msk             (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */
13327 #define RCC_CDCFGR1_HPRE_DIV512                 RCC_CDCFGR1_HPRE_DIV512_Msk            /*!< AHB3 Clock divided by 512 */
13328 
13329 /*!< D1PPRE configuration */
13330 #define RCC_CDCFGR1_CDPPRE_Pos                  (4U)
13331 #define RCC_CDCFGR1_CDPPRE_Msk                  (0x7UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000070 */
13332 #define RCC_CDCFGR1_CDPPRE                      RCC_CDCFGR1_CDPPRE_Msk                 /*!< CDPRE[2:0] bits (APB3 prescaler) */
13333 #define RCC_CDCFGR1_CDPPRE_0                    (0x1UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000010 */
13334 #define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */
13335 #define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */
13336 
13337 #define RCC_CDCFGR1_CDPPRE_DIV1                 (0U)                 /*!< APB3 clock not divided */
13338 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)
13339 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
13340 #define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */
13341 #define RCC_CDCFGR1_CDPPRE_DIV4_Pos             (4U)
13342 #define RCC_CDCFGR1_CDPPRE_DIV4_Msk             (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */
13343 #define RCC_CDCFGR1_CDPPRE_DIV4                 RCC_CDCFGR1_CDPPRE_DIV4_Msk            /*!< APB3 clock divided by 4 */
13344 #define RCC_CDCFGR1_CDPPRE_DIV8_Pos             (5U)
13345 #define RCC_CDCFGR1_CDPPRE_DIV8_Msk             (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */
13346 #define RCC_CDCFGR1_CDPPRE_DIV8                 RCC_CDCFGR1_CDPPRE_DIV8_Msk            /*!< APB3 clock divided by 8 */
13347 #define RCC_CDCFGR1_CDPPRE_DIV16_Pos            (4U)
13348 #define RCC_CDCFGR1_CDPPRE_DIV16_Msk            (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */
13349 #define RCC_CDCFGR1_CDPPRE_DIV16                RCC_CDCFGR1_CDPPRE_DIV16_Msk            /*!< APB3 clock divided by 16 */
13350 
13351 #define RCC_CDCFGR1_CDCPRE_Pos                  (8U)
13352 #define RCC_CDCFGR1_CDCPRE_Msk                  (0xFUL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000F00 */
13353 #define RCC_CDCFGR1_CDCPRE                      RCC_CDCFGR1_CDCPRE_Msk                  /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */
13354 #define RCC_CDCFGR1_CDCPRE_0                    (0x1UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000100 */
13355 #define RCC_CDCFGR1_CDCPRE_1                    (0x2UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000200 */
13356 #define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */
13357 #define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */
13358 
13359 #define RCC_CDCFGR1_CDCPRE_DIV1                 (0U)                  /*!< Domain 1 Core clock not divided */
13360 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)
13361 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */
13362 #define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */
13363 #define RCC_CDCFGR1_CDCPRE_DIV4_Pos             (8U)
13364 #define RCC_CDCFGR1_CDCPRE_DIV4_Msk             (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos)  /*!< 0x00000900 */
13365 #define RCC_CDCFGR1_CDCPRE_DIV4                 RCC_CDCFGR1_CDCPRE_DIV4_Msk             /*!< Domain 1 Core clock divided by 4 */
13366 #define RCC_CDCFGR1_CDCPRE_DIV8_Pos             (9U)
13367 #define RCC_CDCFGR1_CDCPRE_DIV8_Msk             (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos)  /*!< 0x00000A00 */
13368 #define RCC_CDCFGR1_CDCPRE_DIV8                 RCC_CDCFGR1_CDCPRE_DIV8_Msk             /*!< Domain 1 Core clock divided by 8 */
13369 #define RCC_CDCFGR1_CDCPRE_DIV16_Pos            (8U)
13370 #define RCC_CDCFGR1_CDCPRE_DIV16_Msk            (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */
13371 #define RCC_CDCFGR1_CDCPRE_DIV16                RCC_CDCFGR1_CDCPRE_DIV16_Msk            /*!< Domain 1 Core clock divided by 16 */
13372 #define RCC_CDCFGR1_CDCPRE_DIV64_Pos            (10U)
13373 #define RCC_CDCFGR1_CDCPRE_DIV64_Msk            (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */
13374 #define RCC_CDCFGR1_CDCPRE_DIV64                RCC_CDCFGR1_CDCPRE_DIV64_Msk            /*!< Domain 1 Core clock divided by 64 */
13375 #define RCC_CDCFGR1_CDCPRE_DIV128_Pos           (8U)
13376 #define RCC_CDCFGR1_CDCPRE_DIV128_Msk           (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */
13377 #define RCC_CDCFGR1_CDCPRE_DIV128               RCC_CDCFGR1_CDCPRE_DIV128_Msk           /*!< Domain 1 Core clock divided by 128 */
13378 #define RCC_CDCFGR1_CDCPRE_DIV256_Pos           (9U)
13379 #define RCC_CDCFGR1_CDCPRE_DIV256_Msk           (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */
13380 #define RCC_CDCFGR1_CDCPRE_DIV256               RCC_CDCFGR1_CDCPRE_DIV256_Msk           /*!< Domain 1 Core clock divided by 256 */
13381 #define RCC_CDCFGR1_CDCPRE_DIV512_Pos           (8U)
13382 #define RCC_CDCFGR1_CDCPRE_DIV512_Msk           (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */
13383 #define RCC_CDCFGR1_CDCPRE_DIV512               RCC_CDCFGR1_CDCPRE_DIV512_Msk           /*!< Domain 1 Core clock divided by 512 */
13384 
13385 /********************  Bit definition for RCC_CDCFGR2 register  ******************/
13386 /*!< CDPPRE1 configuration */
13387 #define RCC_CDCFGR2_CDPPRE1_Pos                 (4U)
13388 #define RCC_CDCFGR2_CDPPRE1_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */
13389 #define RCC_CDCFGR2_CDPPRE1                     RCC_CDCFGR2_CDPPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
13390 #define RCC_CDCFGR2_CDPPRE1_0                   (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */
13391 #define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
13392 #define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
13393 
13394 #define RCC_CDCFGR2_CDPPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
13395 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)
13396 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
13397 #define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
13398 #define RCC_CDCFGR2_CDPPRE1_DIV4_Pos            (4U)
13399 #define RCC_CDCFGR2_CDPPRE1_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */
13400 #define RCC_CDCFGR2_CDPPRE1_DIV4                RCC_CDCFGR2_CDPPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */
13401 #define RCC_CDCFGR2_CDPPRE1_DIV8_Pos            (5U)
13402 #define RCC_CDCFGR2_CDPPRE1_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */
13403 #define RCC_CDCFGR2_CDPPRE1_DIV8                RCC_CDCFGR2_CDPPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */
13404 #define RCC_CDCFGR2_CDPPRE1_DIV16_Pos           (4U)
13405 #define RCC_CDCFGR2_CDPPRE1_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */
13406 #define RCC_CDCFGR2_CDPPRE1_DIV16               RCC_CDCFGR2_CDPPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */
13407 
13408 /*!< CDPPRE2 configuration */
13409 #define RCC_CDCFGR2_CDPPRE2_Pos                 (8U)
13410 #define RCC_CDCFGR2_CDPPRE2_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */
13411 #define RCC_CDCFGR2_CDPPRE2                     RCC_CDCFGR2_CDPPRE2_Msk          /*!< CDPPRE2[2:0] bits (APB2 prescaler) */
13412 #define RCC_CDCFGR2_CDPPRE2_0                   (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */
13413 #define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
13414 #define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
13415 
13416 #define RCC_CDCFGR2_CDPPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
13417 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)
13418 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
13419 #define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
13420 #define RCC_CDCFGR2_CDPPRE2_DIV4_Pos            (8U)
13421 #define RCC_CDCFGR2_CDPPRE2_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */
13422 #define RCC_CDCFGR2_CDPPRE2_DIV4                RCC_CDCFGR2_CDPPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */
13423 #define RCC_CDCFGR2_CDPPRE2_DIV8_Pos            (9U)
13424 #define RCC_CDCFGR2_CDPPRE2_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */
13425 #define RCC_CDCFGR2_CDPPRE2_DIV8                RCC_CDCFGR2_CDPPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */
13426 #define RCC_CDCFGR2_CDPPRE2_DIV16_Pos           (8U)
13427 #define RCC_CDCFGR2_CDPPRE2_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */
13428 #define RCC_CDCFGR2_CDPPRE2_DIV16               RCC_CDCFGR2_CDPPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */
13429 
13430 /********************  Bit definition for RCC_SRDCFGR register  ******************/
13431 /*!< SRDPPRE configuration */
13432 #define RCC_SRDCFGR_SRDPPRE_Pos                  (4U)
13433 #define RCC_SRDCFGR_SRDPPRE_Msk                  (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */
13434 #define RCC_SRDCFGR_SRDPPRE                      RCC_SRDCFGR_SRDPPRE_Msk           /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */
13435 #define RCC_SRDCFGR_SRDPPRE_0                    (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */
13436 #define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
13437 #define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
13438 
13439 #define RCC_SRDCFGR_SRDPPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
13440 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)
13441 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
13442 #define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
13443 #define RCC_SRDCFGR_SRDPPRE_DIV4_Pos             (4U)
13444 #define RCC_SRDCFGR_SRDPPRE_DIV4_Msk             (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */
13445 #define RCC_SRDCFGR_SRDPPRE_DIV4                 RCC_SRDCFGR_SRDPPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */
13446 #define RCC_SRDCFGR_SRDPPRE_DIV8_Pos             (5U)
13447 #define RCC_SRDCFGR_SRDPPRE_DIV8_Msk             (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */
13448 #define RCC_SRDCFGR_SRDPPRE_DIV8                 RCC_SRDCFGR_SRDPPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */
13449 #define RCC_SRDCFGR_SRDPPRE_DIV16_Pos            (4U)
13450 #define RCC_SRDCFGR_SRDPPRE_DIV16_Msk            (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */
13451 #define RCC_SRDCFGR_SRDPPRE_DIV16                RCC_SRDCFGR_SRDPPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */
13452 
13453 /********************  Bit definition for RCC_PLLCKSELR register  *************/
13454 
13455 #define RCC_PLLCKSELR_PLLSRC_Pos               (0U)
13456 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
13457 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
13458 
13459 #define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
13460 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
13461 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
13462 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
13463 #define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)
13464 #define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
13465 #define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */
13466 #define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)
13467 #define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
13468 #define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */
13469 
13470 #define RCC_PLLCKSELR_DIVM1_Pos                (4U)
13471 #define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
13472 #define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk
13473 #define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
13474 #define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
13475 #define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
13476 #define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
13477 #define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
13478 #define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
13479 
13480 #define RCC_PLLCKSELR_DIVM2_Pos                (12U)
13481 #define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
13482 #define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk
13483 #define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
13484 #define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
13485 #define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
13486 #define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
13487 #define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
13488 #define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
13489 
13490 #define RCC_PLLCKSELR_DIVM3_Pos                (20U)
13491 #define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
13492 #define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk
13493 #define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
13494 #define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
13495 #define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
13496 #define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
13497 #define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
13498 #define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
13499 
13500 /********************  Bit definition for RCC_PLLCFGR register  ***************/
13501 
13502 #define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)
13503 #define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
13504 #define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk
13505 #define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)
13506 #define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
13507 #define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk
13508 #define RCC_PLLCFGR_PLL1RGE_Pos                (2U)
13509 #define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13510 #define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk
13511 #define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
13512 #define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
13513 #define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
13514 #define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13515 
13516 #define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)
13517 #define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
13518 #define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk
13519 #define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)
13520 #define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
13521 #define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk
13522 #define RCC_PLLCFGR_PLL2RGE_Pos                (6U)
13523 #define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
13524 #define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk
13525 #define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
13526 #define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
13527 #define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
13528 #define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
13529 
13530 #define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)
13531 #define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
13532 #define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk
13533 #define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)
13534 #define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
13535 #define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk
13536 #define RCC_PLLCFGR_PLL3RGE_Pos                (10U)
13537 #define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
13538 #define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk
13539 #define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
13540 #define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
13541 #define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
13542 #define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
13543 
13544 #define RCC_PLLCFGR_DIVP1EN_Pos                (16U)
13545 #define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
13546 #define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk
13547 #define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)
13548 #define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
13549 #define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk
13550 #define RCC_PLLCFGR_DIVR1EN_Pos                (18U)
13551 #define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
13552 #define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk
13553 
13554 #define RCC_PLLCFGR_DIVP2EN_Pos                (19U)
13555 #define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
13556 #define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk
13557 #define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)
13558 #define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
13559 #define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk
13560 #define RCC_PLLCFGR_DIVR2EN_Pos                (21U)
13561 #define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
13562 #define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk
13563 
13564 #define RCC_PLLCFGR_DIVP3EN_Pos                (22U)
13565 #define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
13566 #define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk
13567 #define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)
13568 #define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
13569 #define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk
13570 #define RCC_PLLCFGR_DIVR3EN_Pos                (24U)
13571 #define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
13572 #define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk
13573 
13574 
13575 /********************  Bit definition for RCC_PLL1DIVR register  ***************/
13576 #define RCC_PLL1DIVR_N1_Pos                    (0U)
13577 #define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
13578 #define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk
13579 #define RCC_PLL1DIVR_P1_Pos                    (9U)
13580 #define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
13581 #define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk
13582 #define RCC_PLL1DIVR_Q1_Pos                    (16U)
13583 #define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
13584 #define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk
13585 #define RCC_PLL1DIVR_R1_Pos                    (24U)
13586 #define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
13587 #define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk
13588 
13589 /********************  Bit definition for RCC_PLL1FRACR register  ***************/
13590 #define RCC_PLL1FRACR_FRACN1_Pos               (3U)
13591 #define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
13592 #define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk
13593 
13594 /********************  Bit definition for RCC_PLL2DIVR register  ***************/
13595 #define RCC_PLL2DIVR_N2_Pos                    (0U)
13596 #define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
13597 #define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk
13598 #define RCC_PLL2DIVR_P2_Pos                    (9U)
13599 #define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
13600 #define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk
13601 #define RCC_PLL2DIVR_Q2_Pos                    (16U)
13602 #define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
13603 #define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk
13604 #define RCC_PLL2DIVR_R2_Pos                    (24U)
13605 #define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
13606 #define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk
13607 
13608 /********************  Bit definition for RCC_PLL2FRACR register  ***************/
13609 #define RCC_PLL2FRACR_FRACN2_Pos               (3U)
13610 #define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
13611 #define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk
13612 
13613 /********************  Bit definition for RCC_PLL3DIVR register  ***************/
13614 #define RCC_PLL3DIVR_N3_Pos                    (0U)
13615 #define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
13616 #define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk
13617 #define RCC_PLL3DIVR_P3_Pos                    (9U)
13618 #define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
13619 #define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk
13620 #define RCC_PLL3DIVR_Q3_Pos                    (16U)
13621 #define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
13622 #define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk
13623 #define RCC_PLL3DIVR_R3_Pos                    (24U)
13624 #define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
13625 #define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk
13626 
13627 /********************  Bit definition for RCC_PLL3FRACR register  ***************/
13628 #define RCC_PLL3FRACR_FRACN3_Pos               (3U)
13629 #define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
13630 #define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk
13631 
13632 /********************  Bit definition for RCC_CDCCIPR register  ***************/
13633 #define RCC_CDCCIPR_FMCSEL_Pos                 (0U)
13634 #define RCC_CDCCIPR_FMCSEL_Msk                 (0x3UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000003 */
13635 #define RCC_CDCCIPR_FMCSEL                     RCC_CDCCIPR_FMCSEL_Msk
13636 #define RCC_CDCCIPR_FMCSEL_0                   (0x1UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000001 */
13637 #define RCC_CDCCIPR_FMCSEL_1                   (0x2UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000002 */
13638 #define RCC_CDCCIPR_OCTOSPISEL_Pos             (4U)
13639 #define RCC_CDCCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */
13640 #define RCC_CDCCIPR_OCTOSPISEL                 RCC_CDCCIPR_OCTOSPISEL_Msk
13641 #define RCC_CDCCIPR_OCTOSPISEL_0               (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */
13642 #define RCC_CDCCIPR_OCTOSPISEL_1               (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */
13643 #define RCC_CDCCIPR_SDMMCSEL_Pos               (16U)
13644 #define RCC_CDCCIPR_SDMMCSEL_Msk               (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos)   /*!< 0x00010000 */
13645 #define RCC_CDCCIPR_SDMMCSEL                   RCC_CDCCIPR_SDMMCSEL_Msk
13646 #define RCC_CDCCIPR_CKPERSEL_Pos               (28U)
13647 #define RCC_CDCCIPR_CKPERSEL_Msk               (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x30000000 */
13648 #define RCC_CDCCIPR_CKPERSEL                   RCC_CDCCIPR_CKPERSEL_Msk
13649 #define RCC_CDCCIPR_CKPERSEL_0                 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x10000000 */
13650 #define RCC_CDCCIPR_CKPERSEL_1                 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x20000000 */
13651 
13652 /********************  Bit definition for RCC_CDCCIP1R register  ***************/
13653 #define RCC_CDCCIP1R_SAI1SEL_Pos               (0U)
13654 #define RCC_CDCCIP1R_SAI1SEL_Msk               (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000007 */
13655 #define RCC_CDCCIP1R_SAI1SEL                   RCC_CDCCIP1R_SAI1SEL_Msk
13656 #define RCC_CDCCIP1R_SAI1SEL_0                 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000001 */
13657 #define RCC_CDCCIP1R_SAI1SEL_1                 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000002 */
13658 #define RCC_CDCCIP1R_SAI1SEL_2                 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000004 */
13659 
13660 #define RCC_CDCCIP1R_SAI2ASEL_Pos              (6U)
13661 #define RCC_CDCCIP1R_SAI2ASEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x000001C0 */
13662 #define RCC_CDCCIP1R_SAI2ASEL                  RCC_CDCCIP1R_SAI2ASEL_Msk
13663 #define RCC_CDCCIP1R_SAI2ASEL_0                (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000040 */
13664 #define RCC_CDCCIP1R_SAI2ASEL_1                (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000080 */
13665 #define RCC_CDCCIP1R_SAI2ASEL_2                (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000100 */
13666 
13667 #define RCC_CDCCIP1R_SAI2BSEL_Pos              (9U)
13668 #define RCC_CDCCIP1R_SAI2BSEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000E00 */
13669 #define RCC_CDCCIP1R_SAI2BSEL                  RCC_CDCCIP1R_SAI2BSEL_Msk
13670 #define RCC_CDCCIP1R_SAI2BSEL_0                (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000200 */
13671 #define RCC_CDCCIP1R_SAI2BSEL_1                (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000400 */
13672 #define RCC_CDCCIP1R_SAI2BSEL_2                (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000800 */
13673 
13674 #define RCC_CDCCIP1R_SPI123SEL_Pos             (12U)
13675 #define RCC_CDCCIP1R_SPI123SEL_Msk             (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
13676 #define RCC_CDCCIP1R_SPI123SEL                 RCC_CDCCIP1R_SPI123SEL_Msk
13677 #define RCC_CDCCIP1R_SPI123SEL_0               (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
13678 #define RCC_CDCCIP1R_SPI123SEL_1               (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
13679 #define RCC_CDCCIP1R_SPI123SEL_2               (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
13680 
13681 #define RCC_CDCCIP1R_SPI45SEL_Pos              (16U)
13682 #define RCC_CDCCIP1R_SPI45SEL_Msk              (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00070000 */
13683 #define RCC_CDCCIP1R_SPI45SEL                  RCC_CDCCIP1R_SPI45SEL_Msk
13684 #define RCC_CDCCIP1R_SPI45SEL_0                (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00010000 */
13685 #define RCC_CDCCIP1R_SPI45SEL_1                (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00020000 */
13686 #define RCC_CDCCIP1R_SPI45SEL_2                (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00040000 */
13687 
13688 #define RCC_CDCCIP1R_SPDIFSEL_Pos              (20U)
13689 #define RCC_CDCCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00300000 */
13690 #define RCC_CDCCIP1R_SPDIFSEL                  RCC_CDCCIP1R_SPDIFSEL_Msk
13691 #define RCC_CDCCIP1R_SPDIFSEL_0                (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00100000 */
13692 #define RCC_CDCCIP1R_SPDIFSEL_1                (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00200000 */
13693 
13694 #define RCC_CDCCIP1R_DFSDM1SEL_Pos             (24U)
13695 #define RCC_CDCCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
13696 #define RCC_CDCCIP1R_DFSDM1SEL                 RCC_CDCCIP1R_DFSDM1SEL_Msk
13697 
13698 #define RCC_CDCCIP1R_FDCANSEL_Pos              (28U)
13699 #define RCC_CDCCIP1R_FDCANSEL_Msk              (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x30000000 */
13700 #define RCC_CDCCIP1R_FDCANSEL                  RCC_CDCCIP1R_FDCANSEL_Msk
13701 #define RCC_CDCCIP1R_FDCANSEL_0                (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x10000000 */
13702 #define RCC_CDCCIP1R_FDCANSEL_1                (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x20000000 */
13703 
13704 #define RCC_CDCCIP1R_SWPSEL_Pos                (31U)
13705 #define RCC_CDCCIP1R_SWPSEL_Msk                (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos)    /*!< 0x80000000 */
13706 #define RCC_CDCCIP1R_SWPSEL                    RCC_CDCCIP1R_SWPSEL_Msk
13707 
13708 /********************  Bit definition for RCC_CDCCIP2R register  ***************/
13709 #define RCC_CDCCIP2R_USART234578SEL_Pos        (0U)
13710 #define RCC_CDCCIP2R_USART234578SEL_Msk        (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000007 */
13711 #define RCC_CDCCIP2R_USART234578SEL            RCC_CDCCIP2R_USART234578SEL_Msk
13712 #define RCC_CDCCIP2R_USART234578SEL_0          (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000001 */
13713 #define RCC_CDCCIP2R_USART234578SEL_1          (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000002 */
13714 #define RCC_CDCCIP2R_USART234578SEL_2          (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000004 */
13715 
13716 #define RCC_CDCCIP2R_USART16910SEL_Pos         (3U)
13717 #define RCC_CDCCIP2R_USART16910SEL_Msk         (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000038 */
13718 #define RCC_CDCCIP2R_USART16910SEL             RCC_CDCCIP2R_USART16910SEL_Msk
13719 #define RCC_CDCCIP2R_USART16910SEL_0           (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000008 */
13720 #define RCC_CDCCIP2R_USART16910SEL_1           (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000010 */
13721 #define RCC_CDCCIP2R_USART16910SEL_2           (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000020 */
13722 
13723 #define RCC_CDCCIP2R_RNGSEL_Pos                (8U)
13724 #define RCC_CDCCIP2R_RNGSEL_Msk                (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000300 */
13725 #define RCC_CDCCIP2R_RNGSEL                    RCC_CDCCIP2R_RNGSEL_Msk
13726 #define RCC_CDCCIP2R_RNGSEL_0                  (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000100 */
13727 #define RCC_CDCCIP2R_RNGSEL_1                  (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000200 */
13728 
13729 #define RCC_CDCCIP2R_I2C123SEL_Pos             (12U)
13730 #define RCC_CDCCIP2R_I2C123SEL_Msk             (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00003000 */
13731 #define RCC_CDCCIP2R_I2C123SEL                 RCC_CDCCIP2R_I2C123SEL_Msk
13732 #define RCC_CDCCIP2R_I2C123SEL_0               (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00001000 */
13733 #define RCC_CDCCIP2R_I2C123SEL_1               (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00002000 */
13734 
13735 #define RCC_CDCCIP2R_USBSEL_Pos                (20U)
13736 #define RCC_CDCCIP2R_USBSEL_Msk                (0x3UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00300000 */
13737 #define RCC_CDCCIP2R_USBSEL                    RCC_CDCCIP2R_USBSEL_Msk
13738 #define RCC_CDCCIP2R_USBSEL_0                  (0x1UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00100000 */
13739 #define RCC_CDCCIP2R_USBSEL_1                  (0x2UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00200000 */
13740 
13741 #define RCC_CDCCIP2R_CECSEL_Pos                (22U)
13742 #define RCC_CDCCIP2R_CECSEL_Msk                (0x3UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00C00000 */
13743 #define RCC_CDCCIP2R_CECSEL                    RCC_CDCCIP2R_CECSEL_Msk
13744 #define RCC_CDCCIP2R_CECSEL_0                  (0x1UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00400000 */
13745 #define RCC_CDCCIP2R_CECSEL_1                  (0x2UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00800000 */
13746 
13747 #define RCC_CDCCIP2R_LPTIM1SEL_Pos             (28U)
13748 #define RCC_CDCCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x70000000 */
13749 #define RCC_CDCCIP2R_LPTIM1SEL                 RCC_CDCCIP2R_LPTIM1SEL_Msk
13750 #define RCC_CDCCIP2R_LPTIM1SEL_0               (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x10000000 */
13751 #define RCC_CDCCIP2R_LPTIM1SEL_1               (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x20000000 */
13752 #define RCC_CDCCIP2R_LPTIM1SEL_2               (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x40000000 */
13753 
13754 /********************  Bit definition for RCC_SRDCCIPR register  ***************/
13755 #define RCC_SRDCCIPR_LPUART1SEL_Pos             (0U)
13756 #define RCC_SRDCCIPR_LPUART1SEL_Msk             (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000007 */
13757 #define RCC_SRDCCIPR_LPUART1SEL                 RCC_SRDCCIPR_LPUART1SEL_Msk
13758 #define RCC_SRDCCIPR_LPUART1SEL_0               (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000001 */
13759 #define RCC_SRDCCIPR_LPUART1SEL_1               (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000002 */
13760 #define RCC_SRDCCIPR_LPUART1SEL_2               (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000004 */
13761 
13762 #define RCC_SRDCCIPR_I2C4SEL_Pos                (8U)
13763 #define RCC_SRDCCIPR_I2C4SEL_Msk                (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000300 */
13764 #define RCC_SRDCCIPR_I2C4SEL                    RCC_SRDCCIPR_I2C4SEL_Msk
13765 #define RCC_SRDCCIPR_I2C4SEL_0                  (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000100 */
13766 #define RCC_SRDCCIPR_I2C4SEL_1                  (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000200 */
13767 
13768 #define RCC_SRDCCIPR_LPTIM2SEL_Pos              (10U)
13769 #define RCC_SRDCCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001C00 */
13770 #define RCC_SRDCCIPR_LPTIM2SEL                  RCC_SRDCCIPR_LPTIM2SEL_Msk
13771 #define RCC_SRDCCIPR_LPTIM2SEL_0                (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000400 */
13772 #define RCC_SRDCCIPR_LPTIM2SEL_1                (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000800 */
13773 #define RCC_SRDCCIPR_LPTIM2SEL_2                (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001000 */
13774 
13775 #define RCC_SRDCCIPR_LPTIM3SEL_Pos            (13U)
13776 #define RCC_SRDCCIPR_LPTIM3SEL_Msk            (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x0000E000 */
13777 #define RCC_SRDCCIPR_LPTIM3SEL                RCC_SRDCCIPR_LPTIM3SEL_Msk
13778 #define RCC_SRDCCIPR_LPTIM3SEL_0              (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00002000 */
13779 #define RCC_SRDCCIPR_LPTIM3SEL_1              (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00004000 */
13780 #define RCC_SRDCCIPR_LPTIM3SEL_2              (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00008000 */
13781 
13782 #define RCC_SRDCCIPR_ADCSEL_Pos                 (16U)
13783 #define RCC_SRDCCIPR_ADCSEL_Msk                 (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00030000 */
13784 #define RCC_SRDCCIPR_ADCSEL                     RCC_SRDCCIPR_ADCSEL_Msk
13785 #define RCC_SRDCCIPR_ADCSEL_0                   (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00010000 */
13786 #define RCC_SRDCCIPR_ADCSEL_1                   (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00020000 */
13787 
13788 #define RCC_SRDCCIPR_DFSDM2SEL_Pos              (27U)
13789 #define RCC_SRDCCIPR_DFSDM2SEL_Msk              (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos)       /*!< 0x08000000 */
13790 #define RCC_SRDCCIPR_DFSDM2SEL                   RCC_SRDCCIPR_DFSDM2SEL_Msk
13791 
13792 #define RCC_SRDCCIPR_SPI6SEL_Pos                (28U)
13793 #define RCC_SRDCCIPR_SPI6SEL_Msk                (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x70000000 */
13794 #define RCC_SRDCCIPR_SPI6SEL                    RCC_SRDCCIPR_SPI6SEL_Msk
13795 #define RCC_SRDCCIPR_SPI6SEL_0                  (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x10000000 */
13796 #define RCC_SRDCCIPR_SPI6SEL_1                  (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x20000000 */
13797 #define RCC_SRDCCIPR_SPI6SEL_2                  (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x40000000 */
13798 
13799 /********************  Bit definition for RCC_CIER register  ******************/
13800 #define RCC_CIER_LSIRDYIE_Pos                  (0U)
13801 #define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
13802 #define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk
13803 #define RCC_CIER_LSERDYIE_Pos                  (1U)
13804 #define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
13805 #define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk
13806 #define RCC_CIER_HSIRDYIE_Pos                  (2U)
13807 #define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
13808 #define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk
13809 #define RCC_CIER_HSERDYIE_Pos                  (3U)
13810 #define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
13811 #define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk
13812 #define RCC_CIER_CSIRDYIE_Pos                  (4U)
13813 #define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
13814 #define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk
13815 #define RCC_CIER_HSI48RDYIE_Pos                (5U)
13816 #define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
13817 #define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk
13818 #define RCC_CIER_PLL1RDYIE_Pos                 (6U)
13819 #define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
13820 #define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk
13821 #define RCC_CIER_PLL2RDYIE_Pos                 (7U)
13822 #define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
13823 #define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk
13824 #define RCC_CIER_PLL3RDYIE_Pos                 (8U)
13825 #define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
13826 #define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk
13827 #define RCC_CIER_LSECSSIE_Pos                  (9U)
13828 #define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
13829 #define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk
13830 
13831 /********************  Bit definition for RCC_CIFR register  ******************/
13832 #define RCC_CIFR_LSIRDYF_Pos                   (0U)
13833 #define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
13834 #define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk
13835 #define RCC_CIFR_LSERDYF_Pos                   (1U)
13836 #define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
13837 #define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk
13838 #define RCC_CIFR_HSIRDYF_Pos                   (2U)
13839 #define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
13840 #define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk
13841 #define RCC_CIFR_HSERDYF_Pos                   (3U)
13842 #define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
13843 #define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk
13844 #define RCC_CIFR_CSIRDYF_Pos                   (4U)
13845 #define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
13846 #define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk
13847 #define RCC_CIFR_HSI48RDYF_Pos                 (5U)
13848 #define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
13849 #define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk
13850 #define RCC_CIFR_PLLRDYF_Pos                   (6U)
13851 #define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
13852 #define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk
13853 #define RCC_CIFR_PLL2RDYF_Pos                  (7U)
13854 #define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
13855 #define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk
13856 #define RCC_CIFR_PLL3RDYF_Pos                  (8U)
13857 #define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
13858 #define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk
13859 #define RCC_CIFR_LSECSSF_Pos                   (9U)
13860 #define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
13861 #define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk
13862 #define RCC_CIFR_HSECSSF_Pos                   (10U)
13863 #define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
13864 #define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk
13865 
13866 /********************  Bit definition for RCC_CICR register  ******************/
13867 #define RCC_CICR_LSIRDYC_Pos                   (0U)
13868 #define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
13869 #define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk
13870 #define RCC_CICR_LSERDYC_Pos                   (1U)
13871 #define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
13872 #define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk
13873 #define RCC_CICR_HSIRDYC_Pos                   (2U)
13874 #define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
13875 #define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk
13876 #define RCC_CICR_HSERDYC_Pos                   (3U)
13877 #define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
13878 #define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk
13879 #define RCC_CICR_CSIRDYC_Pos                   (4U)
13880 #define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
13881 #define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk
13882 #define RCC_CICR_HSI48RDYC_Pos                 (5U)
13883 #define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
13884 #define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk
13885 #define RCC_CICR_PLLRDYC_Pos                   (6U)
13886 #define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
13887 #define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk
13888 #define RCC_CICR_PLL2RDYC_Pos                  (7U)
13889 #define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
13890 #define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk
13891 #define RCC_CICR_PLL3RDYC_Pos                  (8U)
13892 #define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
13893 #define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk
13894 #define RCC_CICR_LSECSSC_Pos                   (9U)
13895 #define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
13896 #define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk
13897 #define RCC_CICR_HSECSSC_Pos                   (10U)
13898 #define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
13899 #define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk
13900 
13901 /********************  Bit definition for RCC_BDCR register  ******************/
13902 #define RCC_BDCR_LSEON_Pos                     (0U)
13903 #define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */
13904 #define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk
13905 #define RCC_BDCR_LSERDY_Pos                    (1U)
13906 #define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */
13907 #define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk
13908 #define RCC_BDCR_LSEBYP_Pos                    (2U)
13909 #define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */
13910 #define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk
13911 
13912 #define RCC_BDCR_LSEDRV_Pos                    (3U)
13913 #define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */
13914 #define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk
13915 #define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */
13916 #define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */
13917 
13918 #define RCC_BDCR_LSECSSON_Pos                  (5U)
13919 #define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
13920 #define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk
13921 #define RCC_BDCR_LSECSSD_Pos                   (6U)
13922 #define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
13923 #define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk
13924 #define RCC_BDCR_LSEEXT_Pos                    (7U)
13925 #define RCC_BDCR_LSEEXT_Msk                    (0x1UL << RCC_BDCR_LSEEXT_Pos)  /*!< 0x00000080 */
13926 #define RCC_BDCR_LSEEXT                        RCC_BDCR_LSEEXT_Msk
13927 
13928 #define RCC_BDCR_RTCSEL_Pos                    (8U)
13929 #define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */
13930 #define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk
13931 #define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */
13932 #define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */
13933 
13934 #define RCC_BDCR_RTCEN_Pos                     (15U)
13935 #define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */
13936 #define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk
13937 #define RCC_BDCR_VSWRST_Pos                    (16U)
13938 #define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */
13939 #define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk
13940 /* Legacy define */
13941 #define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos
13942 #define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk
13943 #define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST
13944 /********************  Bit definition for RCC_CSR register  *******************/
13945 #define RCC_CSR_LSION_Pos                      (0U)
13946 #define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */
13947 #define RCC_CSR_LSION                          RCC_CSR_LSION_Msk
13948 #define RCC_CSR_LSIRDY_Pos                     (1U)
13949 #define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */
13950 #define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk
13951 
13952 
13953 /********************  Bit definition for RCC_AHB3ENR register  **************/
13954 #define RCC_AHB3ENR_MDMAEN_Pos                 (0U)
13955 #define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */
13956 #define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk
13957 #define RCC_AHB3ENR_DMA2DEN_Pos                (4U)
13958 #define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */
13959 #define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk
13960 #define RCC_AHB3ENR_JPGDECEN_Pos               (5U)
13961 #define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */
13962 #define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk
13963 #define RCC_AHB3ENR_FMCEN_Pos                  (12U)
13964 #define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */
13965 #define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk
13966 #define RCC_AHB3ENR_OSPI1EN_Pos                (14U)
13967 #define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */
13968 #define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk
13969 #define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)
13970 #define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */
13971 #define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk
13972 #define RCC_AHB3ENR_OSPI2EN_Pos                (19U)
13973 #define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */
13974 #define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk
13975 #define RCC_AHB3ENR_IOMNGREN_Pos               (21U)
13976 #define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */
13977 #define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk
13978 #define RCC_AHB3ENR_OTFDEC1EN_Pos              (22U)
13979 #define RCC_AHB3ENR_OTFDEC1EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)    /*!< 0x00200000 */
13980 #define RCC_AHB3ENR_OTFDEC1EN                  RCC_AHB3ENR_OTFDEC1EN_Msk
13981 #define RCC_AHB3ENR_OTFDEC2EN_Pos              (23U)
13982 #define RCC_AHB3ENR_OTFDEC2EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)    /*!< 0x00400000 */
13983 #define RCC_AHB3ENR_OTFDEC2EN                  RCC_AHB3ENR_OTFDEC2EN_Msk
13984 #define RCC_AHB3ENR_GFXMMUEN_Pos               (24U)
13985 #define RCC_AHB3ENR_GFXMMUEN_Msk               (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos)     /*!< 0x00800000 */
13986 #define RCC_AHB3ENR_GFXMMUEN                   RCC_AHB3ENR_GFXMMUEN_Msk
13987 
13988 /********************  Bit definition for RCC_AHB1ENR register  ***************/
13989 #define RCC_AHB1ENR_DMA1EN_Pos                 (0U)
13990 #define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */
13991 #define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk
13992 #define RCC_AHB1ENR_DMA2EN_Pos                 (1U)
13993 #define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */
13994 #define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk
13995 #define RCC_AHB1ENR_ADC12EN_Pos                (5U)
13996 #define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */
13997 #define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk
13998 #define RCC_AHB1ENR_CRCEN_Pos                  (9U)
13999 #define RCC_AHB1ENR_CRCEN_Msk                  (0x1UL << RCC_AHB1ENR_CRCEN_Pos)           /*!< 0x00000200 */
14000 #define RCC_AHB1ENR_CRCEN                      RCC_AHB1ENR_CRCEN_Msk
14001 #define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)
14002 #define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */
14003 #define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk
14004 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)
14005 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
14006 #define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
14007 
14008 /********************  Bit definition for RCC_AHB2ENR register  ***************/
14009 #define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)
14010 #define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */
14011 #define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk
14012 #define RCC_AHB2ENR_HSEMEN_Pos                 (2U)
14013 #define RCC_AHB2ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB2ENR_HSEMEN_Pos)          /*!< 0x00000004 */
14014 #define RCC_AHB2ENR_HSEMEN                     RCC_AHB2ENR_HSEMEN_Msk
14015 #define RCC_AHB2ENR_CRYPEN_Pos                 (4U)
14016 #define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */
14017 #define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk
14018 #define RCC_AHB2ENR_HASHEN_Pos                 (5U)
14019 #define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */
14020 #define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk
14021 #define RCC_AHB2ENR_RNGEN_Pos                  (6U)
14022 #define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */
14023 #define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk
14024 #define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)
14025 #define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */
14026 #define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk
14027 #define RCC_AHB2ENR_BDMA1EN_Pos                (11U)
14028 #define RCC_AHB2ENR_BDMA1EN_Msk                (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos)         /*!< 0x00000800 */
14029 #define RCC_AHB2ENR_BDMA1EN                    RCC_AHB2ENR_BDMA1EN_Msk
14030 #define RCC_AHB2ENR_AHBSRAM1EN_Pos             (29U)
14031 #define RCC_AHB2ENR_AHBSRAM1EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos)       /*!< 0x20000000 */
14032 #define RCC_AHB2ENR_AHBSRAM1EN                 RCC_AHB2ENR_AHBSRAM1EN_Msk
14033 #define RCC_AHB2ENR_AHBSRAM2EN_Pos             (30U)
14034 #define RCC_AHB2ENR_AHBSRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos)       /*!< 0x40000000 */
14035 #define RCC_AHB2ENR_AHBSRAM2EN                 RCC_AHB2ENR_AHBSRAM2EN_Msk
14036 
14037 /* Legacy define */
14038 #define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos
14039 #define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk
14040 #define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN
14041 
14042 /********************  Bit definition for RCC_AHB4ENR register  ******************/
14043 #define RCC_AHB4ENR_GPIOAEN_Pos                (0U)
14044 #define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */
14045 #define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk
14046 #define RCC_AHB4ENR_GPIOBEN_Pos                (1U)
14047 #define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */
14048 #define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk
14049 #define RCC_AHB4ENR_GPIOCEN_Pos                (2U)
14050 #define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */
14051 #define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk
14052 #define RCC_AHB4ENR_GPIODEN_Pos                (3U)
14053 #define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */
14054 #define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk
14055 #define RCC_AHB4ENR_GPIOEEN_Pos                (4U)
14056 #define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */
14057 #define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk
14058 #define RCC_AHB4ENR_GPIOFEN_Pos                (5U)
14059 #define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */
14060 #define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk
14061 #define RCC_AHB4ENR_GPIOGEN_Pos                (6U)
14062 #define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */
14063 #define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk
14064 #define RCC_AHB4ENR_GPIOHEN_Pos                (7U)
14065 #define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */
14066 #define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk
14067 #define RCC_AHB4ENR_GPIOIEN_Pos                (8U)
14068 #define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */
14069 #define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk
14070 #define RCC_AHB4ENR_GPIOJEN_Pos                (9U)
14071 #define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */
14072 #define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk
14073 #define RCC_AHB4ENR_GPIOKEN_Pos                (10U)
14074 #define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */
14075 #define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk
14076 #define RCC_AHB4ENR_BDMA2EN_Pos                (21U)
14077 #define RCC_AHB4ENR_BDMA2EN_Msk                (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos)         /*!< 0x00080000 */
14078 #define RCC_AHB4ENR_BDMA2EN                    RCC_AHB4ENR_BDMA2EN_Msk
14079 #define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)
14080 #define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */
14081 #define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk
14082 #define RCC_AHB4ENR_SRDSRAMEN_Pos              (29U)
14083 #define RCC_AHB4ENR_SRDSRAMEN_Msk              (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos)       /*!< 0x20000000 */
14084 #define RCC_AHB4ENR_SRDSRAMEN                  RCC_AHB4ENR_SRDSRAMEN_Msk
14085 
14086 /********************  Bit definition for RCC_APB3ENR register  ******************/
14087 #define RCC_APB3ENR_LTDCEN_Pos                 (3U)
14088 #define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
14089 #define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk
14090 #define RCC_APB3ENR_WWDGEN_Pos                 (6U)
14091 #define RCC_APB3ENR_WWDGEN_Msk                 (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */
14092 #define RCC_APB3ENR_WWDGEN                     RCC_APB3ENR_WWDGEN_Msk
14093 
14094 /* Legacy define */
14095 #define RCC_APB3ENR_WWDG1EN_Pos                 RCC_APB3ENR_WWDGEN_Pos
14096 #define RCC_APB3ENR_WWDG1EN_Msk                 RCC_APB3ENR_WWDGEN_Msk
14097 #define RCC_APB3ENR_WWDG1EN                     RCC_APB3ENR_WWDGEN
14098 /********************  Bit definition for RCC_APB1LENR register  ******************/
14099 
14100 #define RCC_APB1LENR_TIM2EN_Pos                (0U)
14101 #define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
14102 #define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk
14103 #define RCC_APB1LENR_TIM3EN_Pos                (1U)
14104 #define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
14105 #define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk
14106 #define RCC_APB1LENR_TIM4EN_Pos                (2U)
14107 #define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
14108 #define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk
14109 #define RCC_APB1LENR_TIM5EN_Pos                (3U)
14110 #define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
14111 #define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk
14112 #define RCC_APB1LENR_TIM6EN_Pos                (4U)
14113 #define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
14114 #define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk
14115 #define RCC_APB1LENR_TIM7EN_Pos                (5U)
14116 #define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
14117 #define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk
14118 #define RCC_APB1LENR_TIM12EN_Pos               (6U)
14119 #define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
14120 #define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk
14121 #define RCC_APB1LENR_TIM13EN_Pos               (7U)
14122 #define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
14123 #define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk
14124 #define RCC_APB1LENR_TIM14EN_Pos               (8U)
14125 #define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
14126 #define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk
14127 #define RCC_APB1LENR_LPTIM1EN_Pos              (9U)
14128 #define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
14129 #define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk
14130 
14131 
14132 #define RCC_APB1LENR_SPI2EN_Pos                (14U)
14133 #define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
14134 #define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk
14135 #define RCC_APB1LENR_SPI3EN_Pos                (15U)
14136 #define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
14137 #define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk
14138 #define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)
14139 #define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
14140 #define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk
14141 #define RCC_APB1LENR_USART2EN_Pos              (17U)
14142 #define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
14143 #define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk
14144 #define RCC_APB1LENR_USART3EN_Pos              (18U)
14145 #define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
14146 #define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk
14147 #define RCC_APB1LENR_UART4EN_Pos               (19U)
14148 #define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
14149 #define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk
14150 #define RCC_APB1LENR_UART5EN_Pos               (20U)
14151 #define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
14152 #define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk
14153 #define RCC_APB1LENR_I2C1EN_Pos                (21U)
14154 #define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
14155 #define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk
14156 #define RCC_APB1LENR_I2C2EN_Pos                (22U)
14157 #define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
14158 #define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk
14159 #define RCC_APB1LENR_I2C3EN_Pos                (23U)
14160 #define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
14161 #define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk
14162 #define RCC_APB1LENR_CECEN_Pos                 (27U)
14163 #define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
14164 #define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk
14165 #define RCC_APB1LENR_DAC12EN_Pos               (29U)
14166 #define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
14167 #define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk
14168 #define RCC_APB1LENR_UART7EN_Pos               (30U)
14169 #define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
14170 #define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk
14171 #define RCC_APB1LENR_UART8EN_Pos               (31U)
14172 #define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
14173 #define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk
14174 
14175 /* Legacy define */
14176 #define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos
14177 #define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk
14178 #define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN
14179 /********************  Bit definition for RCC_APB1HENR register  ******************/
14180 #define RCC_APB1HENR_CRSEN_Pos                 (1U)
14181 #define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
14182 #define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk
14183 #define RCC_APB1HENR_SWPMIEN_Pos               (2U)
14184 #define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
14185 #define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk
14186 #define RCC_APB1HENR_OPAMPEN_Pos               (4U)
14187 #define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
14188 #define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk
14189 #define RCC_APB1HENR_MDIOSEN_Pos               (5U)
14190 #define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
14191 #define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk
14192 #define RCC_APB1HENR_FDCANEN_Pos               (8U)
14193 #define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
14194 #define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk
14195 
14196 /********************  Bit definition for RCC_APB2ENR register  ******************/
14197 #define RCC_APB2ENR_TIM1EN_Pos                 (0U)
14198 #define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
14199 #define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk
14200 #define RCC_APB2ENR_TIM8EN_Pos                 (1U)
14201 #define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
14202 #define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk
14203 #define RCC_APB2ENR_USART1EN_Pos               (4U)
14204 #define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
14205 #define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk
14206 #define RCC_APB2ENR_USART6EN_Pos               (5U)
14207 #define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
14208 #define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk
14209 #define RCC_APB2ENR_UART9EN_Pos                (6U)
14210 #define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */
14211 #define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk
14212 #define RCC_APB2ENR_USART10EN_Pos              (7U)
14213 #define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */
14214 #define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk
14215 #define RCC_APB2ENR_SPI1EN_Pos                 (12U)
14216 #define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
14217 #define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk
14218 #define RCC_APB2ENR_SPI4EN_Pos                 (13U)
14219 #define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
14220 #define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk
14221 #define RCC_APB2ENR_TIM15EN_Pos                (16U)
14222 #define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
14223 #define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk
14224 #define RCC_APB2ENR_TIM16EN_Pos                (17U)
14225 #define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
14226 #define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk
14227 #define RCC_APB2ENR_TIM17EN_Pos                (18U)
14228 #define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
14229 #define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk
14230 #define RCC_APB2ENR_SPI5EN_Pos                 (20U)
14231 #define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
14232 #define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk
14233 #define RCC_APB2ENR_SAI1EN_Pos                 (22U)
14234 #define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
14235 #define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk
14236 #define RCC_APB2ENR_SAI2EN_Pos                 (23U)
14237 #define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
14238 #define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk
14239 #define RCC_APB2ENR_DFSDM1EN_Pos               (30U)
14240 #define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */
14241 #define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk
14242 
14243 /********************  Bit definition for RCC_APB4ENR register  ******************/
14244 #define RCC_APB4ENR_SYSCFGEN_Pos               (1U)
14245 #define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
14246 #define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk
14247 #define RCC_APB4ENR_LPUART1EN_Pos              (3U)
14248 #define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
14249 #define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk
14250 #define RCC_APB4ENR_SPI6EN_Pos                 (5U)
14251 #define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
14252 #define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk
14253 #define RCC_APB4ENR_I2C4EN_Pos                 (7U)
14254 #define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
14255 #define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk
14256 #define RCC_APB4ENR_LPTIM2EN_Pos               (9U)
14257 #define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
14258 #define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk
14259 #define RCC_APB4ENR_LPTIM3EN_Pos               (10U)
14260 #define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
14261 #define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk
14262 #define RCC_APB4ENR_DAC2EN_Pos                 (13U)
14263 #define RCC_APB4ENR_DAC2EN_Msk                 (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */
14264 #define RCC_APB4ENR_DAC2EN                     RCC_APB4ENR_DAC2EN_Msk
14265 #define RCC_APB4ENR_COMP12EN_Pos               (14U)
14266 #define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
14267 #define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk
14268 #define RCC_APB4ENR_VREFEN_Pos                 (15U)
14269 #define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
14270 #define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk
14271 #define RCC_APB4ENR_RTCAPBEN_Pos               (16U)
14272 #define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
14273 #define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk
14274 
14275 #define RCC_APB4ENR_DTSEN_Pos                  (26U)
14276 #define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */
14277 #define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk
14278 #define RCC_APB4ENR_DFSDM2EN_Pos               (27U)
14279 #define RCC_APB4ENR_DFSDM2EN_Msk               (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */
14280 #define RCC_APB4ENR_DFSDM2EN                   RCC_APB4ENR_DFSDM2EN_Msk
14281 
14282 /********************  Bit definition for RCC_AHB3RSTR register  ***************/
14283 #define RCC_AHB3RSTR_MDMARST_Pos               (0U)
14284 #define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */
14285 #define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk
14286 #define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)
14287 #define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */
14288 #define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk
14289 #define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)
14290 #define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */
14291 #define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk
14292 #define RCC_AHB3RSTR_FMCRST_Pos                (12U)
14293 #define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */
14294 #define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk
14295 #define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)
14296 #define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */
14297 #define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk
14298 #define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)
14299 #define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */
14300 #define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk
14301 #define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)
14302 #define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */
14303 #define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk
14304 #define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)
14305 #define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */
14306 #define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk
14307 #define RCC_AHB3RSTR_OTFDEC1RST_Pos            (22U)
14308 #define RCC_AHB3RSTR_OTFDEC1RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)  /*!< 0x00040000 */
14309 #define RCC_AHB3RSTR_OTFDEC1RST                RCC_AHB3RSTR_OTFDEC1RST_Msk
14310 #define RCC_AHB3RSTR_OTFDEC2RST_Pos            (23U)
14311 #define RCC_AHB3RSTR_OTFDEC2RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)  /*!< 0x00080000 */
14312 #define RCC_AHB3RSTR_OTFDEC2RST                RCC_AHB3RSTR_OTFDEC2RST_Msk
14313 #define RCC_AHB3RSTR_GFXMMURST_Pos             (24U)
14314 #define RCC_AHB3RSTR_GFXMMURST_Msk             (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos)   /*!< 0x00100000 */
14315 #define RCC_AHB3RSTR_GFXMMURST                 RCC_AHB3RSTR_GFXMMURST_Msk
14316 
14317 
14318 /********************  Bit definition for RCC_AHB1RSTR register  ***************/
14319 #define RCC_AHB1RSTR_DMA1RST_Pos               (0U)
14320 #define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */
14321 #define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk
14322 #define RCC_AHB1RSTR_DMA2RST_Pos               (1U)
14323 #define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */
14324 #define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk
14325 #define RCC_AHB1RSTR_ADC12RST_Pos              (5U)
14326 #define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */
14327 #define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk
14328 #define RCC_AHB1RSTR_CRCRST_Pos                (9U)
14329 #define RCC_AHB1RSTR_CRCRST_Msk                (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)       /*!< 0x00000200 */
14330 #define RCC_AHB1RSTR_CRCRST                    RCC_AHB1RSTR_CRCRST_Msk
14331 #define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)
14332 #define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
14333 #define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk
14334 
14335 /********************  Bit definition for RCC_AHB2RSTR register  ***************/
14336 #define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)
14337 #define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */
14338 #define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk
14339 #define RCC_AHB2RSTR_HSEMRST_Pos               (2U)
14340 #define RCC_AHB2RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos)       /*!< 0x00000004 */
14341 #define RCC_AHB2RSTR_HSEMRST                   RCC_AHB2RSTR_HSEMRST_Msk
14342 #define RCC_AHB2RSTR_CRYPRST_Pos               (4U)
14343 #define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */
14344 #define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk
14345 #define RCC_AHB2RSTR_HASHRST_Pos               (5U)
14346 #define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */
14347 #define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk
14348 #define RCC_AHB2RSTR_RNGRST_Pos                (6U)
14349 #define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */
14350 #define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk
14351 #define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)
14352 #define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */
14353 #define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk
14354 #define RCC_AHB2RSTR_BDMA1RST_Pos              (11U)
14355 #define RCC_AHB2RSTR_BDMA1RST_Msk              (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos)      /*!< 0x00000200 */
14356 #define RCC_AHB2RSTR_BDMA1RST                  RCC_AHB2RSTR_BDMA1RST_Msk
14357 
14358 /* Legacy define */
14359 #define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos
14360 #define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk
14361 #define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST
14362 /********************  Bit definition for RCC_AHB4RSTR register  ******************/
14363 #define RCC_AHB4RSTR_GPIOARST_Pos              (0U)
14364 #define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */
14365 #define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk
14366 #define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)
14367 #define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */
14368 #define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk
14369 #define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)
14370 #define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */
14371 #define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk
14372 #define RCC_AHB4RSTR_GPIODRST_Pos              (3U)
14373 #define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */
14374 #define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk
14375 #define RCC_AHB4RSTR_GPIOERST_Pos              (4U)
14376 #define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */
14377 #define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk
14378 #define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)
14379 #define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */
14380 #define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk
14381 #define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)
14382 #define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */
14383 #define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk
14384 #define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)
14385 #define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */
14386 #define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk
14387 #define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)
14388 #define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */
14389 #define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk
14390 #define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)
14391 #define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */
14392 #define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk
14393 #define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)
14394 #define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */
14395 #define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk
14396 #define RCC_AHB4RSTR_BDMA2RST_Pos              (21U)
14397 #define RCC_AHB4RSTR_BDMA2RST_Msk              (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos)       /*!< 0x00200000 */
14398 #define RCC_AHB4RSTR_BDMA2RST                   RCC_AHB4RSTR_BDMA2RST_Msk
14399 
14400 
14401 /********************  Bit definition for RCC_APB3RSTR register  ******************/
14402 #define RCC_APB3RSTR_LTDCRST_Pos               (3U)
14403 #define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
14404 #define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk
14405 
14406 /********************  Bit definition for RCC_APB1LRSTR register  ******************/
14407 
14408 #define RCC_APB1LRSTR_TIM2RST_Pos              (0U)
14409 #define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
14410 #define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk
14411 #define RCC_APB1LRSTR_TIM3RST_Pos              (1U)
14412 #define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
14413 #define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk
14414 #define RCC_APB1LRSTR_TIM4RST_Pos              (2U)
14415 #define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
14416 #define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk
14417 #define RCC_APB1LRSTR_TIM5RST_Pos              (3U)
14418 #define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
14419 #define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk
14420 #define RCC_APB1LRSTR_TIM6RST_Pos              (4U)
14421 #define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
14422 #define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk
14423 #define RCC_APB1LRSTR_TIM7RST_Pos              (5U)
14424 #define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
14425 #define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk
14426 #define RCC_APB1LRSTR_TIM12RST_Pos             (6U)
14427 #define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
14428 #define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk
14429 #define RCC_APB1LRSTR_TIM13RST_Pos             (7U)
14430 #define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
14431 #define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk
14432 #define RCC_APB1LRSTR_TIM14RST_Pos             (8U)
14433 #define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
14434 #define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk
14435 #define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)
14436 #define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
14437 #define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk
14438 #define RCC_APB1LRSTR_SPI2RST_Pos              (14U)
14439 #define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
14440 #define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk
14441 #define RCC_APB1LRSTR_SPI3RST_Pos              (15U)
14442 #define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
14443 #define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk
14444 #define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)
14445 #define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
14446 #define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk
14447 #define RCC_APB1LRSTR_USART2RST_Pos            (17U)
14448 #define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
14449 #define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk
14450 #define RCC_APB1LRSTR_USART3RST_Pos            (18U)
14451 #define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
14452 #define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk
14453 #define RCC_APB1LRSTR_UART4RST_Pos             (19U)
14454 #define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
14455 #define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk
14456 #define RCC_APB1LRSTR_UART5RST_Pos             (20U)
14457 #define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
14458 #define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk
14459 #define RCC_APB1LRSTR_I2C1RST_Pos              (21U)
14460 #define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
14461 #define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk
14462 #define RCC_APB1LRSTR_I2C2RST_Pos              (22U)
14463 #define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
14464 #define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk
14465 #define RCC_APB1LRSTR_I2C3RST_Pos              (23U)
14466 #define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
14467 #define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk
14468 #define RCC_APB1LRSTR_CECRST_Pos               (27U)
14469 #define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
14470 #define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk
14471 #define RCC_APB1LRSTR_DAC12RST_Pos             (29U)
14472 #define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
14473 #define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk
14474 #define RCC_APB1LRSTR_UART7RST_Pos             (30U)
14475 #define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
14476 #define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk
14477 #define RCC_APB1LRSTR_UART8RST_Pos             (31U)
14478 #define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
14479 #define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk
14480 
14481 /* Legacy define */
14482 #define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos
14483 #define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk
14484 #define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST
14485 /********************  Bit definition for RCC_APB1HRSTR register  ******************/
14486 #define RCC_APB1HRSTR_CRSRST_Pos               (1U)
14487 #define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
14488 #define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk
14489 #define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)
14490 #define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
14491 #define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk
14492 #define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)
14493 #define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
14494 #define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk
14495 #define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)
14496 #define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
14497 #define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk
14498 #define RCC_APB1HRSTR_FDCANRST_Pos             (8U)
14499 #define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
14500 #define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk
14501 
14502 /********************  Bit definition for RCC_APB2RSTR register  ******************/
14503 #define RCC_APB2RSTR_TIM1RST_Pos               (0U)
14504 #define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
14505 #define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk
14506 #define RCC_APB2RSTR_TIM8RST_Pos               (1U)
14507 #define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
14508 #define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk
14509 #define RCC_APB2RSTR_USART1RST_Pos             (4U)
14510 #define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
14511 #define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk
14512 #define RCC_APB2RSTR_USART6RST_Pos             (5U)
14513 #define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
14514 #define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk
14515 #define RCC_APB2RSTR_UART9RST_Pos              (6U)
14516 #define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
14517 #define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk
14518 #define RCC_APB2RSTR_USART10RST_Pos            (7U)
14519 #define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */
14520 #define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk
14521 #define RCC_APB2RSTR_SPI1RST_Pos               (12U)
14522 #define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
14523 #define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk
14524 #define RCC_APB2RSTR_SPI4RST_Pos               (13U)
14525 #define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
14526 #define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk
14527 #define RCC_APB2RSTR_TIM15RST_Pos              (16U)
14528 #define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
14529 #define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk
14530 #define RCC_APB2RSTR_TIM16RST_Pos              (17U)
14531 #define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
14532 #define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk
14533 #define RCC_APB2RSTR_TIM17RST_Pos              (18U)
14534 #define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
14535 #define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk
14536 #define RCC_APB2RSTR_SPI5RST_Pos               (20U)
14537 #define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
14538 #define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk
14539 #define RCC_APB2RSTR_SAI1RST_Pos               (22U)
14540 #define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
14541 #define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk
14542 #define RCC_APB2RSTR_SAI2RST_Pos               (23U)
14543 #define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
14544 #define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk
14545 #define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)
14546 #define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
14547 #define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk
14548 
14549 /********************  Bit definition for RCC_APB4RSTR register  ******************/
14550 #define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)
14551 #define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
14552 #define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk
14553 #define RCC_APB4RSTR_LPUART1RST_Pos            (3U)
14554 #define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
14555 #define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk
14556 #define RCC_APB4RSTR_SPI6RST_Pos               (5U)
14557 #define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
14558 #define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk
14559 #define RCC_APB4RSTR_I2C4RST_Pos               (7U)
14560 #define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
14561 #define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk
14562 #define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)
14563 #define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
14564 #define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk
14565 #define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)
14566 #define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
14567 #define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk
14568 #define RCC_APB4RSTR_DAC2RST_Pos               (13U)
14569 #define RCC_APB4RSTR_DAC2RST_Msk               (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */
14570 #define RCC_APB4RSTR_DAC2RST                    RCC_APB4RSTR_DAC2RST_Msk
14571 #define RCC_APB4RSTR_COMP12RST_Pos             (14U)
14572 #define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
14573 #define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk
14574 #define RCC_APB4RSTR_VREFRST_Pos               (15U)
14575 #define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
14576 #define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk
14577 
14578 #define RCC_APB4RSTR_DTSRST_Pos                (26U)
14579 #define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */
14580 #define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk
14581 #define RCC_APB4RSTR_DFSDM2RST_Pos             (27U)
14582 #define RCC_APB4RSTR_DFSDM2RST_Msk             (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */
14583 #define RCC_APB4RSTR_DFSDM2RST                 RCC_APB4RSTR_DFSDM2RST_Msk
14584 
14585 
14586 /********************  Bit definition for RCC_SRDAMR register  ********************/
14587 #define RCC_SRDAMR_BDMA2AMEN_Pos               (0U)
14588 #define RCC_SRDAMR_BDMA2AMEN_Msk               (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */
14589 #define RCC_SRDAMR_BDMA2AMEN                   RCC_SRDAMR_BDMA2AMEN_Msk
14590 #define RCC_SRDAMR_GPIOAMEN_Pos                (1U)
14591 #define RCC_SRDAMR_GPIOAMEN_Msk                (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */
14592 #define RCC_SRDAMR_GPIOAMEN                    RCC_SRDAMR_GPIOAMEN_Msk
14593 #define RCC_SRDAMR_LPUART1AMEN_Pos             (3U)
14594 #define RCC_SRDAMR_LPUART1AMEN_Msk             (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
14595 #define RCC_SRDAMR_LPUART1AMEN                 RCC_SRDAMR_LPUART1AMEN_Msk
14596 #define RCC_SRDAMR_SPI6AMEN_Pos                (5U)
14597 #define RCC_SRDAMR_SPI6AMEN_Msk                (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */
14598 #define RCC_SRDAMR_SPI6AMEN                    RCC_SRDAMR_SPI6AMEN_Msk
14599 #define RCC_SRDAMR_I2C4AMEN_Pos                (7U)
14600 #define RCC_SRDAMR_I2C4AMEN_Msk                (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */
14601 #define RCC_SRDAMR_I2C4AMEN                    RCC_SRDAMR_I2C4AMEN_Msk
14602 #define RCC_SRDAMR_LPTIM2AMEN_Pos              (9U)
14603 #define RCC_SRDAMR_LPTIM2AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
14604 #define RCC_SRDAMR_LPTIM2AMEN                  RCC_SRDAMR_LPTIM2AMEN_Msk
14605 #define RCC_SRDAMR_LPTIM3AMEN_Pos              (10U)
14606 #define RCC_SRDAMR_LPTIM3AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
14607 #define RCC_SRDAMR_LPTIM3AMEN                  RCC_SRDAMR_LPTIM3AMEN_Msk
14608 #define RCC_SRDAMR_DAC2AMEN_Pos                (13U)
14609 #define RCC_SRDAMR_DAC2AMEN_Msk                (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */
14610 #define RCC_SRDAMR_DAC2AMEN                    RCC_SRDAMR_DAC2AMEN_Msk
14611 #define RCC_SRDAMR_COMP12AMEN_Pos              (14U)
14612 #define RCC_SRDAMR_COMP12AMEN_Msk              (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */
14613 #define RCC_SRDAMR_COMP12AMEN                  RCC_SRDAMR_COMP12AMEN_Msk
14614 #define RCC_SRDAMR_VREFAMEN_Pos                (15U)
14615 #define RCC_SRDAMR_VREFAMEN_Msk                (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */
14616 #define RCC_SRDAMR_VREFAMEN                     RCC_SRDAMR_VREFAMEN_Msk
14617 #define RCC_SRDAMR_RTCAMEN_Pos                 (16U)
14618 #define RCC_SRDAMR_RTCAMEN_Msk                 (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */
14619 #define RCC_SRDAMR_RTCAMEN                     RCC_SRDAMR_RTCAMEN_Msk
14620 #define RCC_SRDAMR_DTSAMEN_Pos                 (26U)
14621 #define RCC_SRDAMR_DTSAMEN_Msk                 (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */
14622 #define RCC_SRDAMR_DTSAMEN                     RCC_SRDAMR_DTSAMEN_Msk
14623 #define RCC_SRDAMR_DFSDM2AMEN_Pos              (27U)
14624 #define RCC_SRDAMR_DFSDM2AMEN_Msk              (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */
14625 #define RCC_SRDAMR_DFSDM2AMEN                   RCC_SRDAMR_DFSDM2AMEN_Msk
14626 #define RCC_SRDAMR_BKPRAMAMEN_Pos              (28U)
14627 #define RCC_SRDAMR_BKPRAMAMEN_Msk              (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
14628 #define RCC_SRDAMR_BKPRAMAMEN                  RCC_SRDAMR_BKPRAMAMEN_Msk
14629 #define RCC_SRDAMR_SRDSRAMAMEN_Pos             (29U)
14630 #define RCC_SRDAMR_SRDSRAMAMEN_Msk             (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */
14631 #define RCC_SRDAMR_SRDSRAMAMEN                  RCC_SRDAMR_SRDSRAMAMEN_Msk
14632 /********************  Bit definition for RCC_CKGAENR register  ********************/
14633 #define RCC_CKGAENR_AXICKG_Pos                 (0U)
14634 #define RCC_CKGAENR_AXICKG_Msk                 (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */
14635 #define RCC_CKGAENR_AXICKG                      RCC_CKGAENR_AXICKG_Msk
14636 #define RCC_CKGAENR_AHBCKG_Pos                 (1U)
14637 #define RCC_CKGAENR_AHBCKG_Msk                 (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */
14638 #define RCC_CKGAENR_AHBCKG                     RCC_CKGAENR_AHBCKG_Msk
14639 #define RCC_CKGAENR_CPUCKG_Pos                 (2U)
14640 #define RCC_CKGAENR_CPUCKG_Msk                 (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */
14641 #define RCC_CKGAENR_CPUCKG                     RCC_CKGAENR_CPUCKG_Msk
14642 #define RCC_CKGAENR_SDMMCCKG_Pos               (3U)
14643 #define RCC_CKGAENR_SDMMCCKG_Msk               (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */
14644 #define RCC_CKGAENR_SDMMCCKG                    RCC_CKGAENR_SDMMCCKG_Msk
14645 #define RCC_CKGAENR_MDMACKG_Pos                (4U)
14646 #define RCC_CKGAENR_MDMACKG_Msk                (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */
14647 #define RCC_CKGAENR_MDMACKG                    RCC_CKGAENR_MDMACKG_Msk
14648 #define RCC_CKGAENR_DMA2DCKG_Pos               (5U)
14649 #define RCC_CKGAENR_DMA2DCKG_Msk               (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */
14650 #define RCC_CKGAENR_DMA2DCKG                    RCC_CKGAENR_DMA2DCKG_Msk
14651 #define RCC_CKGAENR_LTDCCKG_Pos                (6U)
14652 #define RCC_CKGAENR_LTDCCKG_Msk                (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */
14653 #define RCC_CKGAENR_LTDCCKG                    RCC_CKGAENR_LTDCCKG_Msk
14654 #define RCC_CKGAENR_GFXMMUMCKG_Pos             (7U)
14655 #define RCC_CKGAENR_GFXMMUMCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */
14656 #define RCC_CKGAENR_GFXMMUMCKG                 RCC_CKGAENR_GFXMMUMCKG_Msk
14657 #define RCC_CKGAENR_AHB12CKG_Pos               (8U)
14658 #define RCC_CKGAENR_AHB12CKG_Msk               (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */
14659 #define RCC_CKGAENR_AHB12CKG                   RCC_CKGAENR_AHB12CKG_Msk
14660 #define RCC_CKGAENR_AHB34CKG_Pos               (9U)
14661 #define RCC_CKGAENR_AHB34CKG_Msk               (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */
14662 #define RCC_CKGAENR_AHB34CKG                   RCC_CKGAENR_AHB34CKG_Msk
14663 #define RCC_CKGAENR_FLIFTCKG_Pos               (10U)
14664 #define RCC_CKGAENR_FLIFTCKG_Msk               (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */
14665 #define RCC_CKGAENR_FLIFTCKG                   RCC_CKGAENR_FLIFTCKG_Msk
14666 #define RCC_CKGAENR_OCTOSPI2CKG_Pos            (11U)
14667 #define RCC_CKGAENR_OCTOSPI2CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */
14668 #define RCC_CKGAENR_OCTOSPI2CKG                RCC_CKGAENR_OCTOSPI2CKG_Msk
14669 #define RCC_CKGAENR_FMCCKG_Pos                 (12U)
14670 #define RCC_CKGAENR_FMCCKG_Msk                 (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */
14671 #define RCC_CKGAENR_FMCCKG                     RCC_CKGAENR_FMCCKG_Msk
14672 #define RCC_CKGAENR_OCTOSPI1CKG_Pos            (13U)
14673 #define RCC_CKGAENR_OCTOSPI1CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */
14674 #define RCC_CKGAENR_OCTOSPI1CKG                RCC_CKGAENR_OCTOSPI1CKG_Msk
14675 #define RCC_CKGAENR_AXIRAM1CKG_Pos             (14U)
14676 #define RCC_CKGAENR_AXIRAM1CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */
14677 #define RCC_CKGAENR_AXIRAM1CKG                 RCC_CKGAENR_AXIRAM1CKG_Msk
14678 #define RCC_CKGAENR_AXIRAM2CKG_Pos             (15U)
14679 #define RCC_CKGAENR_AXIRAM2CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */
14680 #define RCC_CKGAENR_AXIRAM2CKG                 RCC_CKGAENR_AXIRAM2CKG_Msk
14681 #define RCC_CKGAENR_AXIRAM3CKG_Pos             (16U)
14682 #define RCC_CKGAENR_AXIRAM3CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */
14683 #define RCC_CKGAENR_AXIRAM3CKG                 RCC_CKGAENR_AXIRAM3CKG_Msk
14684 #define RCC_CKGAENR_GFXMMUSCKG_Pos             (17U)
14685 #define RCC_CKGAENR_GFXMMUSCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */
14686 #define RCC_CKGAENR_GFXMMUSCKG                 RCC_CKGAENR_GFXMMUSCKG_Msk
14687 #define RCC_CKGAENR_ECCRAMCKG_Pos              (29U)
14688 #define RCC_CKGAENR_ECCRAMCKG_Msk              (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */
14689 #define RCC_CKGAENR_ECCRAMCKG                  RCC_CKGAENR_ECCRAMCKG_Msk
14690 #define RCC_CKGAENR_EXTICKG_Pos                (30U)
14691 #define RCC_CKGAENR_EXTICKG_Msk                (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */
14692 #define RCC_CKGAENR_EXTICKG                    RCC_CKGAENR_EXTICKG_Msk
14693 #define RCC_CKGAENR_JTAGCKG_Pos                (31U)
14694 #define RCC_CKGAENR_JTAGCKG_Msk                (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */
14695 #define RCC_CKGAENR_JTAGCKG                    RCC_CKGAENR_JTAGCKG_Msk
14696 /********************  Bit definition for RCC_AHB3LPENR register  **************/
14697 #define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)
14698 #define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */
14699 #define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk
14700 #define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)
14701 #define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */
14702 #define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk
14703 #define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)
14704 #define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */
14705 #define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk
14706 #define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)
14707 #define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */
14708 #define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk
14709 #define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)
14710 #define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */
14711 #define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk
14712 #define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)
14713 #define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */
14714 #define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk
14715 #define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)
14716 #define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */
14717 #define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk
14718 #define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)
14719 #define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */
14720 #define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk
14721 #define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)
14722 #define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */
14723 #define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk
14724 #define RCC_AHB3LPENR_OTFDEC1LPEN_Pos          (22U)
14725 #define RCC_AHB3LPENR_OTFDEC1LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)      /*!< 0x00400000 */
14726 #define RCC_AHB3LPENR_OTFDEC1LPEN              RCC_AHB3LPENR_OTFDEC1LPEN_Msk
14727 #define RCC_AHB3LPENR_OTFDEC2LPEN_Pos          (23U)
14728 #define RCC_AHB3LPENR_OTFDEC2LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)      /*!< 0x00800000 */
14729 #define RCC_AHB3LPENR_OTFDEC2LPEN              RCC_AHB3LPENR_OTFDEC2LPEN_Msk
14730 #define RCC_AHB3LPENR_GFXMMULPEN_Pos           (24U)
14731 #define RCC_AHB3LPENR_GFXMMULPEN_Msk           (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos)       /*!< 0x01000000 */
14732 #define RCC_AHB3LPENR_GFXMMULPEN               RCC_AHB3LPENR_GFXMMULPEN_Msk
14733 #define RCC_AHB3LPENR_AXISRAM2LPEN_Pos         (26U)
14734 #define RCC_AHB3LPENR_AXISRAM2LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos)     /*!< 0x02000000 */
14735 #define RCC_AHB3LPENR_AXISRAM2LPEN             RCC_AHB3LPENR_AXISRAM2LPEN_Msk
14736 #define RCC_AHB3LPENR_AXISRAM3LPEN_Pos         (27U)
14737 #define RCC_AHB3LPENR_AXISRAM3LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos)     /*!< 0x04000000 */
14738 #define RCC_AHB3LPENR_AXISRAM3LPEN             RCC_AHB3LPENR_AXISRAM3LPEN_Msk
14739 #define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)
14740 #define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */
14741 #define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk
14742 #define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)
14743 #define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */
14744 #define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk
14745 #define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)
14746 #define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */
14747 #define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk
14748 #define RCC_AHB3LPENR_AXISRAM1LPEN_Pos         (31U)
14749 #define RCC_AHB3LPENR_AXISRAM1LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos)      /*!< 0x80000000 */
14750 #define RCC_AHB3LPENR_AXISRAM1LPEN             RCC_AHB3LPENR_AXISRAM1LPEN_Msk
14751 
14752 
14753 /* Legacy define */
14754 #define RCC_AHB3LPENR_AXISRAMLPEN_Pos          RCC_AHB3LPENR_AXISRAM1LPEN_Pos
14755 #define RCC_AHB3LPENR_AXISRAMLPEN_Msk          RCC_AHB3LPENR_AXISRAM1LPEN_Msk
14756 #define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAM1LPEN
14757 /********************  Bit definition for RCC_AHB1LPENR register  ***************/
14758 #define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)
14759 #define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
14760 #define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk
14761 #define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)
14762 #define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
14763 #define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk
14764 #define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)
14765 #define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
14766 #define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk
14767 #define RCC_AHB1LPENR_CRCLPEN_Pos              (9U)
14768 #define RCC_AHB1LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */
14769 #define RCC_AHB1LPENR_CRCLPEN                   RCC_AHB1LPENR_CRCLPEN_Msk
14770 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)
14771 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
14772 #define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
14773 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)
14774 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
14775 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
14776 
14777 /********************  Bit definition for RCC_AHB2LPENR register  ***************/
14778 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)
14779 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */
14780 #define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
14781 #define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)
14782 #define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
14783 #define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk
14784 #define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)
14785 #define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
14786 #define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk
14787 #define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)
14788 #define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
14789 #define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk
14790 #define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)
14791 #define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
14792 #define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk
14793 #define RCC_AHB2LPENR_BDMA1LPEN_Pos            (11U)
14794 #define RCC_AHB2LPENR_BDMA1LPEN_Msk            (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos)   /*!< 0x00000800 */
14795 #define RCC_AHB2LPENR_BDMA1LPEN                RCC_AHB2LPENR_BDMA1LPEN_Msk
14796 #define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos         (29U)
14797 #define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */
14798 #define RCC_AHB2LPENR_AHBSRAM1LPEN             RCC_AHB2LPENR_AHBSRAM1LPEN_Msk
14799 #define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos         (30U)
14800 #define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */
14801 #define RCC_AHB2LPENR_AHBSRAM2LPEN             RCC_AHB2LPENR_AHBSRAM2LPEN_Msk
14802 
14803 /* Legacy define */
14804 #define RCC_AHB2LPENR_DFSDMDMALPEN_Pos         RCC_AHB2LPENR_BDMA1LPEN_Pos
14805 #define RCC_AHB2LPENR_DFSDMDMALPEN_Msk         RCC_AHB2LPENR_BDMA1LPEN_Msk
14806 #define RCC_AHB2LPENR_DFSDMDMALPEN             RCC_AHB2LPENR_BDMA1LPEN
14807 #define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos
14808 #define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
14809 #define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN
14810 
14811 /********************  Bit definition for RCC_AHB4LPENR register  ******************/
14812 #define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)
14813 #define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
14814 #define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk
14815 #define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)
14816 #define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
14817 #define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk
14818 #define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)
14819 #define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
14820 #define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk
14821 #define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)
14822 #define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
14823 #define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk
14824 #define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)
14825 #define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
14826 #define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk
14827 #define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)
14828 #define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
14829 #define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk
14830 #define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)
14831 #define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
14832 #define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk
14833 #define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)
14834 #define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
14835 #define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk
14836 #define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)
14837 #define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
14838 #define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk
14839 #define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)
14840 #define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
14841 #define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk
14842 #define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)
14843 #define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
14844 #define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk
14845 #define RCC_AHB4LPENR_BDMA2LPEN_Pos             (21U)
14846 #define RCC_AHB4LPENR_BDMA2LPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */
14847 #define RCC_AHB4LPENR_BDMA2LPEN                 RCC_AHB4LPENR_BDMA2LPEN_Msk
14848 #define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)
14849 #define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
14850 #define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk
14851 #define RCC_AHB4LPENR_SRDSRAMLPEN_Pos          (29U)
14852 #define RCC_AHB4LPENR_SRDSRAMLPEN_Msk          (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */
14853 #define RCC_AHB4LPENR_SRDSRAMLPEN              RCC_AHB4LPENR_SRDSRAMLPEN_Msk
14854 
14855 /********************  Bit definition for RCC_APB3LPENR register  ******************/
14856 #define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)
14857 #define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
14858 #define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk
14859 #define RCC_APB3LPENR_WWDGLPEN_Pos             (6U)
14860 #define RCC_APB3LPENR_WWDGLPEN_Msk             (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos)  /*!< 0x00000040 */
14861 #define RCC_APB3LPENR_WWDGLPEN                 RCC_APB3LPENR_WWDGLPEN_Msk
14862 
14863 /* Legacy define */
14864 #define RCC_APB3LPENR_WWDG1LPEN_Pos            RCC_APB3LPENR_WWDGLPEN_Pos
14865 #define RCC_APB3LPENR_WWDG1LPEN_Msk            RCC_APB3LPENR_WWDGLPEN_Msk
14866 #define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDGLPEN
14867 /********************  Bit definition for RCC_APB1LLPENR register  ******************/
14868 
14869 #define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)
14870 #define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
14871 #define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk
14872 #define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)
14873 #define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
14874 #define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk
14875 #define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)
14876 #define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
14877 #define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk
14878 #define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)
14879 #define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
14880 #define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk
14881 #define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)
14882 #define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
14883 #define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk
14884 #define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)
14885 #define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
14886 #define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk
14887 #define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)
14888 #define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
14889 #define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk
14890 #define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)
14891 #define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
14892 #define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk
14893 #define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)
14894 #define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
14895 #define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk
14896 #define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)
14897 #define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
14898 #define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk
14899 
14900 
14901 #define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)
14902 #define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
14903 #define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk
14904 #define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)
14905 #define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
14906 #define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk
14907 #define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)
14908 #define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
14909 #define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk
14910 #define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)
14911 #define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
14912 #define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk
14913 #define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)
14914 #define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
14915 #define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk
14916 #define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)
14917 #define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
14918 #define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk
14919 #define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)
14920 #define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
14921 #define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk
14922 #define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)
14923 #define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
14924 #define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk
14925 #define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)
14926 #define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
14927 #define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk
14928 #define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)
14929 #define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
14930 #define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk
14931 #define RCC_APB1LLPENR_CECLPEN_Pos             (27U)
14932 #define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
14933 #define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk
14934 #define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)
14935 #define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
14936 #define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk
14937 #define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)
14938 #define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
14939 #define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk
14940 #define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)
14941 #define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
14942 #define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk
14943 
14944 /* Legacy define */
14945 #define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos
14946 #define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk
14947 #define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN
14948 /********************  Bit definition for RCC_APB1HLPENR register  ******************/
14949 #define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)
14950 #define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
14951 #define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk
14952 #define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)
14953 #define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
14954 #define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk
14955 #define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)
14956 #define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
14957 #define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk
14958 #define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)
14959 #define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
14960 #define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk
14961 #define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)
14962 #define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
14963 #define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk
14964 
14965 /********************  Bit definition for RCC_APB2LPENR register  ******************/
14966 #define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)
14967 #define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
14968 #define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk
14969 #define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)
14970 #define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
14971 #define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk
14972 #define RCC_APB2LPENR_USART1LPEN_Pos           (4U)
14973 #define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
14974 #define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk
14975 #define RCC_APB2LPENR_USART6LPEN_Pos           (5U)
14976 #define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
14977 #define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk
14978 #define RCC_APB2LPENR_UART9LPEN_Pos            (6U)
14979 #define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */
14980 #define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk
14981 #define RCC_APB2LPENR_USART10LPEN_Pos          (7U)
14982 #define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */
14983 #define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk
14984 #define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)
14985 #define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
14986 #define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk
14987 #define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)
14988 #define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
14989 #define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk
14990 #define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)
14991 #define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
14992 #define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk
14993 #define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)
14994 #define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
14995 #define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk
14996 #define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)
14997 #define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
14998 #define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk
14999 #define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)
15000 #define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
15001 #define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk
15002 #define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)
15003 #define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
15004 #define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk
15005 #define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)
15006 #define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
15007 #define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk
15008 #define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)
15009 #define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */
15010 #define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk
15011 
15012 /********************  Bit definition for RCC_APB4LPENR register  ******************/
15013 #define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)
15014 #define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
15015 #define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk
15016 #define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)
15017 #define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
15018 #define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk
15019 #define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)
15020 #define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
15021 #define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk
15022 #define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)
15023 #define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
15024 #define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk
15025 #define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)
15026 #define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
15027 #define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk
15028 #define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)
15029 #define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
15030 #define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk
15031 #define RCC_APB4LPENR_DAC2LPEN_Pos             (13U)
15032 #define RCC_APB4LPENR_DAC2LPEN_Msk             (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */
15033 #define RCC_APB4LPENR_DAC2LPEN                 RCC_APB4LPENR_DAC2LPEN_Msk
15034 #define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)
15035 #define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
15036 #define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk
15037 #define RCC_APB4LPENR_VREFLPEN_Pos             (15U)
15038 #define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
15039 #define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk
15040 #define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)
15041 #define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
15042 #define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk
15043 
15044 #define RCC_APB4LPENR_DTSLPEN_Pos              (26U)
15045 #define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */
15046 #define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk
15047 #define RCC_APB4LPENR_DFSDM2LPEN_Pos           (27U)
15048 #define RCC_APB4LPENR_DFSDM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */
15049 #define RCC_APB4LPENR_DFSDM2LPEN                RCC_APB4LPENR_DFSDM2LPEN_Msk
15050 
15051 /********************  Bit definition for RCC_RSR register  *******************/
15052 #define RCC_RSR_RMVF_Pos                       (16U)
15053 #define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */
15054 #define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk
15055 #define RCC_RSR_CDRSTF_Pos                     (19U)
15056 #define RCC_RSR_CDRSTF_Msk                     (0x1UL << RCC_RSR_CDRSTF_Pos)   /*!< 0x00080000 */
15057 #define RCC_RSR_CDRSTF                         RCC_RSR_CDRSTF_Msk
15058 #define RCC_RSR_BORRSTF_Pos                    (21U)
15059 #define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */
15060 #define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk
15061 #define RCC_RSR_PINRSTF_Pos                    (22U)
15062 #define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */
15063 #define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk
15064 #define RCC_RSR_PORRSTF_Pos                    (23U)
15065 #define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */
15066 #define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk
15067 #define RCC_RSR_SFTRSTF_Pos                    (24U)
15068 #define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */
15069 #define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk
15070 #define RCC_RSR_IWDGRSTF_Pos                   (26U)
15071 #define RCC_RSR_IWDGRSTF_Msk                   (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */
15072 #define RCC_RSR_IWDGRSTF                       RCC_RSR_IWDGRSTF_Msk
15073 #define RCC_RSR_WWDGRSTF_Pos                   (28U)
15074 #define RCC_RSR_WWDGRSTF_Msk                   (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */
15075 #define RCC_RSR_WWDGRSTF                       RCC_RSR_WWDGRSTF_Msk
15076 
15077 #define RCC_RSR_LPWRRSTF_Pos                   (30U)
15078 #define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
15079 #define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk
15080 
15081 
15082 /* Legacy define */
15083 #define RCC_RSR_IWDG1RSTF_Pos                  RCC_RSR_IWDGRSTF_Pos
15084 #define RCC_RSR_IWDG1RSTF_Msk                  RCC_RSR_IWDGRSTF_Msk
15085 #define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDGRSTF
15086 #define RCC_RSR_WWDG1RSTF_Pos                  RCC_RSR_WWDGRSTF_Pos
15087 #define RCC_RSR_WWDG1RSTF_Msk                  RCC_RSR_WWDGRSTF_Msk
15088 #define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDGRSTF
15089 /******************************************************************************/
15090 /*                                                                            */
15091 /*                                    RNG                                     */
15092 /*                                                                            */
15093 /******************************************************************************/
15094 /***************************    RNG VER  **************************************/
15095 #define RNG_VER_3_1
15096 /********************  Bits definition for RNG_CR register  *******************/
15097 #define RNG_CR_RNGEN_Pos    (2U)
15098 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
15099 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
15100 #define RNG_CR_IE_Pos       (3U)
15101 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
15102 #define RNG_CR_IE           RNG_CR_IE_Msk
15103 #define RNG_CR_CED_Pos      (5U)
15104 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */
15105 #define RNG_CR_CED          RNG_CR_CED_Msk
15106 #define RNG_CR_RNG_CONFIG3_Pos      (8U)
15107 #define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */
15108 #define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk
15109 #define RNG_CR_NISTC_Pos            (12U)
15110 #define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */
15111 #define RNG_CR_NISTC                RNG_CR_NISTC_Msk
15112 #define RNG_CR_RNG_CONFIG2_Pos      (13U)
15113 #define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */
15114 #define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk
15115 #define RNG_CR_CLKDIV_Pos           (16U)
15116 #define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */
15117 #define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk
15118 #define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */
15119 #define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */
15120 #define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */
15121 #define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */
15122 #define RNG_CR_RNG_CONFIG1_Pos      (20U)
15123 #define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */
15124 #define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk
15125 #define RNG_CR_CONDRST_Pos         (30U)
15126 #define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */
15127 #define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk
15128 #define RNG_CR_CONFIGLOCK_Pos      (31U)
15129 #define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */
15130 #define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk
15131 
15132 /********************  Bits definition for RNG_SR register  *******************/
15133 #define RNG_SR_DRDY_Pos     (0U)
15134 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
15135 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
15136 #define RNG_SR_CECS_Pos     (1U)
15137 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
15138 #define RNG_SR_CECS         RNG_SR_CECS_Msk
15139 #define RNG_SR_SECS_Pos     (2U)
15140 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
15141 #define RNG_SR_SECS         RNG_SR_SECS_Msk
15142 #define RNG_SR_CEIS_Pos     (5U)
15143 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
15144 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
15145 #define RNG_SR_SEIS_Pos     (6U)
15146 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
15147 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
15148 
15149 /******************************************************************************/
15150 /*                                                                            */
15151 /*                           Real-Time Clock (RTC)                            */
15152 /*                                                                            */
15153 /******************************************************************************/
15154 /********************  Bits definition for RTC_TR register  *******************/
15155 #define RTC_TR_PM_Pos                  (22U)
15156 #define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
15157 #define RTC_TR_PM                      RTC_TR_PM_Msk
15158 #define RTC_TR_HT_Pos                  (20U)
15159 #define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
15160 #define RTC_TR_HT                      RTC_TR_HT_Msk
15161 #define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
15162 #define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
15163 #define RTC_TR_HU_Pos                  (16U)
15164 #define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
15165 #define RTC_TR_HU                      RTC_TR_HU_Msk
15166 #define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
15167 #define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
15168 #define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
15169 #define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
15170 #define RTC_TR_MNT_Pos                 (12U)
15171 #define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
15172 #define RTC_TR_MNT                     RTC_TR_MNT_Msk
15173 #define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
15174 #define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
15175 #define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
15176 #define RTC_TR_MNU_Pos                 (8U)
15177 #define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
15178 #define RTC_TR_MNU                     RTC_TR_MNU_Msk
15179 #define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
15180 #define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
15181 #define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
15182 #define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
15183 #define RTC_TR_ST_Pos                  (4U)
15184 #define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
15185 #define RTC_TR_ST                      RTC_TR_ST_Msk
15186 #define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
15187 #define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
15188 #define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
15189 #define RTC_TR_SU_Pos                  (0U)
15190 #define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
15191 #define RTC_TR_SU                      RTC_TR_SU_Msk
15192 #define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
15193 #define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
15194 #define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
15195 #define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
15196 
15197 /********************  Bits definition for RTC_DR register  *******************/
15198 #define RTC_DR_YT_Pos                  (20U)
15199 #define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
15200 #define RTC_DR_YT                      RTC_DR_YT_Msk
15201 #define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
15202 #define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
15203 #define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
15204 #define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
15205 #define RTC_DR_YU_Pos                  (16U)
15206 #define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
15207 #define RTC_DR_YU                      RTC_DR_YU_Msk
15208 #define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
15209 #define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
15210 #define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
15211 #define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
15212 #define RTC_DR_WDU_Pos                 (13U)
15213 #define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
15214 #define RTC_DR_WDU                     RTC_DR_WDU_Msk
15215 #define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
15216 #define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
15217 #define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
15218 #define RTC_DR_MT_Pos                  (12U)
15219 #define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
15220 #define RTC_DR_MT                      RTC_DR_MT_Msk
15221 #define RTC_DR_MU_Pos                  (8U)
15222 #define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
15223 #define RTC_DR_MU                      RTC_DR_MU_Msk
15224 #define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
15225 #define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
15226 #define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
15227 #define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
15228 #define RTC_DR_DT_Pos                  (4U)
15229 #define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
15230 #define RTC_DR_DT                      RTC_DR_DT_Msk
15231 #define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
15232 #define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
15233 #define RTC_DR_DU_Pos                  (0U)
15234 #define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
15235 #define RTC_DR_DU                      RTC_DR_DU_Msk
15236 #define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
15237 #define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
15238 #define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
15239 #define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
15240 
15241 /********************  Bits definition for RTC_CR register  *******************/
15242 #define RTC_CR_OUT2EN_Pos            (31U)
15243 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
15244 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
15245 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
15246 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
15247 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
15248 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
15249 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
15250 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
15251 #define RTC_CR_TAMPOE_Pos            (26U)
15252 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
15253 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
15254 #define RTC_CR_TAMPTS_Pos            (25U)
15255 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
15256 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
15257 #define RTC_CR_ITSE_Pos                (24U)
15258 #define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
15259 #define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
15260 #define RTC_CR_COE_Pos                 (23U)
15261 #define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
15262 #define RTC_CR_COE                     RTC_CR_COE_Msk
15263 #define RTC_CR_OSEL_Pos                (21U)
15264 #define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
15265 #define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
15266 #define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
15267 #define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
15268 #define RTC_CR_POL_Pos                 (20U)
15269 #define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
15270 #define RTC_CR_POL                     RTC_CR_POL_Msk
15271 #define RTC_CR_COSEL_Pos               (19U)
15272 #define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
15273 #define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
15274 #define RTC_CR_BKP_Pos                 (18U)
15275 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
15276 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
15277 #define RTC_CR_SUB1H_Pos               (17U)
15278 #define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
15279 #define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
15280 #define RTC_CR_ADD1H_Pos               (16U)
15281 #define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
15282 #define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
15283 #define RTC_CR_TSIE_Pos                (15U)
15284 #define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
15285 #define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
15286 #define RTC_CR_WUTIE_Pos               (14U)
15287 #define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
15288 #define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
15289 #define RTC_CR_ALRBIE_Pos              (13U)
15290 #define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
15291 #define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
15292 #define RTC_CR_ALRAIE_Pos              (12U)
15293 #define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
15294 #define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
15295 #define RTC_CR_TSE_Pos                 (11U)
15296 #define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
15297 #define RTC_CR_TSE                     RTC_CR_TSE_Msk
15298 #define RTC_CR_WUTE_Pos                (10U)
15299 #define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
15300 #define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
15301 #define RTC_CR_ALRBE_Pos               (9U)
15302 #define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
15303 #define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
15304 #define RTC_CR_ALRAE_Pos               (8U)
15305 #define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
15306 #define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
15307 #define RTC_CR_FMT_Pos                 (6U)
15308 #define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
15309 #define RTC_CR_FMT                     RTC_CR_FMT_Msk
15310 #define RTC_CR_BYPSHAD_Pos             (5U)
15311 #define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
15312 #define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
15313 #define RTC_CR_REFCKON_Pos             (4U)
15314 #define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
15315 #define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
15316 #define RTC_CR_TSEDGE_Pos              (3U)
15317 #define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
15318 #define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
15319 #define RTC_CR_WUCKSEL_Pos             (0U)
15320 #define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
15321 #define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
15322 #define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
15323 #define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
15324 #define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
15325 
15326 /********************  Bits definition for RTC_ICSR register  ******************/
15327 #define RTC_ICSR_RECALPF_Pos         (16U)
15328 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
15329 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
15330 #define RTC_ICSR_INIT_Pos            (7U)
15331 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
15332 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
15333 #define RTC_ICSR_INITF_Pos           (6U)
15334 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
15335 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
15336 #define RTC_ICSR_RSF_Pos             (5U)
15337 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
15338 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
15339 #define RTC_ICSR_INITS_Pos           (4U)
15340 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
15341 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
15342 #define RTC_ICSR_SHPF_Pos            (3U)
15343 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
15344 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
15345 #define RTC_ICSR_WUTWF_Pos           (2U)
15346 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
15347 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
15348 #define RTC_ICSR_ALRBWF_Pos          (1U)
15349 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */
15350 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
15351 #define RTC_ICSR_ALRAWF_Pos          (0U)
15352 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */
15353 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
15354 
15355 /********************  Bits definition for RTC_PRER register  *****************/
15356 #define RTC_PRER_PREDIV_A_Pos          (16U)
15357 #define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
15358 #define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
15359 #define RTC_PRER_PREDIV_S_Pos          (0U)
15360 #define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
15361 #define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
15362 
15363 /********************  Bits definition for RTC_WUTR register  *****************/
15364 #define RTC_WUTR_WUT_Pos               (0U)
15365 #define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
15366 #define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
15367 
15368 /********************  Bits definition for RTC_ALRMAR register  ***************/
15369 #define RTC_ALRMAR_MSK4_Pos            (31U)
15370 #define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
15371 #define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
15372 #define RTC_ALRMAR_WDSEL_Pos           (30U)
15373 #define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
15374 #define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
15375 #define RTC_ALRMAR_DT_Pos              (28U)
15376 #define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
15377 #define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
15378 #define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
15379 #define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
15380 #define RTC_ALRMAR_DU_Pos              (24U)
15381 #define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
15382 #define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
15383 #define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
15384 #define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
15385 #define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
15386 #define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
15387 #define RTC_ALRMAR_MSK3_Pos            (23U)
15388 #define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
15389 #define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
15390 #define RTC_ALRMAR_PM_Pos              (22U)
15391 #define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
15392 #define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
15393 #define RTC_ALRMAR_HT_Pos              (20U)
15394 #define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
15395 #define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
15396 #define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
15397 #define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
15398 #define RTC_ALRMAR_HU_Pos              (16U)
15399 #define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
15400 #define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
15401 #define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
15402 #define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
15403 #define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
15404 #define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
15405 #define RTC_ALRMAR_MSK2_Pos            (15U)
15406 #define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
15407 #define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
15408 #define RTC_ALRMAR_MNT_Pos             (12U)
15409 #define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
15410 #define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
15411 #define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
15412 #define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
15413 #define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
15414 #define RTC_ALRMAR_MNU_Pos             (8U)
15415 #define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
15416 #define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
15417 #define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
15418 #define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
15419 #define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
15420 #define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
15421 #define RTC_ALRMAR_MSK1_Pos            (7U)
15422 #define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
15423 #define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
15424 #define RTC_ALRMAR_ST_Pos              (4U)
15425 #define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
15426 #define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
15427 #define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
15428 #define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
15429 #define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
15430 #define RTC_ALRMAR_SU_Pos              (0U)
15431 #define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
15432 #define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
15433 #define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
15434 #define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
15435 #define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
15436 #define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
15437 
15438 /********************  Bits definition for RTC_ALRMBR register  ***************/
15439 #define RTC_ALRMBR_MSK4_Pos            (31U)
15440 #define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
15441 #define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
15442 #define RTC_ALRMBR_WDSEL_Pos           (30U)
15443 #define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
15444 #define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
15445 #define RTC_ALRMBR_DT_Pos              (28U)
15446 #define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
15447 #define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
15448 #define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
15449 #define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
15450 #define RTC_ALRMBR_DU_Pos              (24U)
15451 #define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
15452 #define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
15453 #define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
15454 #define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
15455 #define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
15456 #define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
15457 #define RTC_ALRMBR_MSK3_Pos            (23U)
15458 #define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
15459 #define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
15460 #define RTC_ALRMBR_PM_Pos              (22U)
15461 #define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
15462 #define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
15463 #define RTC_ALRMBR_HT_Pos              (20U)
15464 #define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
15465 #define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
15466 #define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
15467 #define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
15468 #define RTC_ALRMBR_HU_Pos              (16U)
15469 #define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
15470 #define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
15471 #define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
15472 #define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
15473 #define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
15474 #define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
15475 #define RTC_ALRMBR_MSK2_Pos            (15U)
15476 #define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
15477 #define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
15478 #define RTC_ALRMBR_MNT_Pos             (12U)
15479 #define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
15480 #define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
15481 #define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
15482 #define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
15483 #define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
15484 #define RTC_ALRMBR_MNU_Pos             (8U)
15485 #define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
15486 #define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
15487 #define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
15488 #define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
15489 #define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
15490 #define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
15491 #define RTC_ALRMBR_MSK1_Pos            (7U)
15492 #define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
15493 #define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
15494 #define RTC_ALRMBR_ST_Pos              (4U)
15495 #define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
15496 #define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
15497 #define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
15498 #define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
15499 #define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
15500 #define RTC_ALRMBR_SU_Pos              (0U)
15501 #define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
15502 #define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
15503 #define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
15504 #define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
15505 #define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
15506 #define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
15507 
15508 /********************  Bits definition for RTC_WPR register  ******************/
15509 #define RTC_WPR_KEY_Pos                (0U)
15510 #define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
15511 #define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
15512 
15513 /********************  Bits definition for RTC_SSR register  ******************/
15514 #define RTC_SSR_SS_Pos                 (0U)
15515 #define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
15516 #define RTC_SSR_SS                     RTC_SSR_SS_Msk
15517 
15518 /********************  Bits definition for RTC_SHIFTR register  ***************/
15519 #define RTC_SHIFTR_SUBFS_Pos           (0U)
15520 #define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
15521 #define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
15522 #define RTC_SHIFTR_ADD1S_Pos           (31U)
15523 #define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
15524 #define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
15525 
15526 /********************  Bits definition for RTC_TSTR register  *****************/
15527 #define RTC_TSTR_PM_Pos                (22U)
15528 #define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
15529 #define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
15530 #define RTC_TSTR_HT_Pos                (20U)
15531 #define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
15532 #define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
15533 #define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
15534 #define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
15535 #define RTC_TSTR_HU_Pos                (16U)
15536 #define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
15537 #define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
15538 #define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
15539 #define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
15540 #define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
15541 #define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
15542 #define RTC_TSTR_MNT_Pos               (12U)
15543 #define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
15544 #define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
15545 #define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
15546 #define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
15547 #define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
15548 #define RTC_TSTR_MNU_Pos               (8U)
15549 #define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
15550 #define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
15551 #define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
15552 #define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
15553 #define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
15554 #define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
15555 #define RTC_TSTR_ST_Pos                (4U)
15556 #define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
15557 #define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
15558 #define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
15559 #define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
15560 #define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
15561 #define RTC_TSTR_SU_Pos                (0U)
15562 #define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
15563 #define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
15564 #define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
15565 #define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
15566 #define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
15567 #define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
15568 
15569 /********************  Bits definition for RTC_TSDR register  *****************/
15570 #define RTC_TSDR_WDU_Pos               (13U)
15571 #define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
15572 #define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
15573 #define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
15574 #define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
15575 #define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
15576 #define RTC_TSDR_MT_Pos                (12U)
15577 #define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
15578 #define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
15579 #define RTC_TSDR_MU_Pos                (8U)
15580 #define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
15581 #define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
15582 #define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
15583 #define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
15584 #define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
15585 #define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
15586 #define RTC_TSDR_DT_Pos                (4U)
15587 #define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
15588 #define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
15589 #define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
15590 #define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
15591 #define RTC_TSDR_DU_Pos                (0U)
15592 #define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
15593 #define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
15594 #define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
15595 #define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
15596 #define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
15597 #define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
15598 
15599 /********************  Bits definition for RTC_TSSSR register  ****************/
15600 #define RTC_TSSSR_SS_Pos               (0U)
15601 #define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
15602 #define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
15603 
15604 /********************  Bits definition for RTC_CALR register  *****************/
15605 #define RTC_CALR_CALP_Pos              (15U)
15606 #define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
15607 #define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
15608 #define RTC_CALR_CALW8_Pos             (14U)
15609 #define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
15610 #define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
15611 #define RTC_CALR_CALW16_Pos            (13U)
15612 #define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
15613 #define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
15614 #define RTC_CALR_CALM_Pos              (0U)
15615 #define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
15616 #define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
15617 #define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
15618 #define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
15619 #define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
15620 #define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
15621 #define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
15622 #define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
15623 #define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
15624 #define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
15625 #define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
15626 
15627 
15628 /********************  Bits definition for RTC_ALRMASSR register  *************/
15629 #define RTC_ALRMASSR_MASKSS_Pos        (24U)
15630 #define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
15631 #define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
15632 #define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
15633 #define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
15634 #define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
15635 #define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
15636 #define RTC_ALRMASSR_SS_Pos            (0U)
15637 #define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
15638 #define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
15639 
15640 /********************  Bits definition for RTC_ALRMBSSR register  *************/
15641 #define RTC_ALRMBSSR_MASKSS_Pos        (24U)
15642 #define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
15643 #define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
15644 #define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
15645 #define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
15646 #define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
15647 #define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
15648 #define RTC_ALRMBSSR_SS_Pos            (0U)
15649 #define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
15650 #define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
15651 
15652 
15653 /********************  Bits definition for RTC_SR register  *******************/
15654 #define RTC_SR_ITSF_Pos              (5U)
15655 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                 /*!< 0x00000020 */
15656 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
15657 #define RTC_SR_TSOVF_Pos             (4U)
15658 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)                /*!< 0x00000010 */
15659 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
15660 #define RTC_SR_TSF_Pos               (3U)
15661 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                  /*!< 0x00000008 */
15662 #define RTC_SR_TSF                   RTC_SR_TSF_Msk
15663 #define RTC_SR_WUTF_Pos              (2U)
15664 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                 /*!< 0x00000004 */
15665 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
15666 #define RTC_SR_ALRBF_Pos             (1U)
15667 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)                /*!< 0x00000002 */
15668 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
15669 #define RTC_SR_ALRAF_Pos             (0U)
15670 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)                /*!< 0x00000001 */
15671 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
15672 
15673 /********************  Bits definition for RTC_MISR register  *****************/
15674 #define RTC_MISR_ITSMF_Pos           (5U)
15675 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)              /*!< 0x00000020 */
15676 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
15677 #define RTC_MISR_TSOVMF_Pos          (4U)
15678 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)             /*!< 0x00000010 */
15679 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
15680 #define RTC_MISR_TSMF_Pos            (3U)
15681 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)               /*!< 0x00000008 */
15682 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
15683 #define RTC_MISR_WUTMF_Pos           (2U)
15684 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)              /*!< 0x00000004 */
15685 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
15686 #define RTC_MISR_ALRBMF_Pos          (1U)
15687 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)             /*!< 0x00000002 */
15688 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
15689 #define RTC_MISR_ALRAMF_Pos          (0U)
15690 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)             /*!< 0x00000001 */
15691 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
15692 
15693 /********************  Bits definition for RTC_SCR register  ******************/
15694 #define RTC_SCR_CITSF_Pos            (5U)
15695 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)               /*!< 0x00000020 */
15696 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
15697 #define RTC_SCR_CTSOVF_Pos           (4U)
15698 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)              /*!< 0x00000010 */
15699 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
15700 #define RTC_SCR_CTSF_Pos             (3U)
15701 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)                /*!< 0x00000008 */
15702 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
15703 #define RTC_SCR_CWUTF_Pos            (2U)
15704 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)               /*!< 0x00000004 */
15705 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
15706 #define RTC_SCR_CALRBF_Pos           (1U)
15707 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)              /*!< 0x00000002 */
15708 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
15709 #define RTC_SCR_CALRAF_Pos           (0U)
15710 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)              /*!< 0x00000001 */
15711 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
15712 
15713 /******************************************************************************/
15714 /*                                                                            */
15715 /*                     Tamper and backup register (TAMP)                      */
15716 /*                                                                            */
15717 /******************************************************************************/
15718 /********************  Bits definition for TAMP_CR1 register  *****************/
15719 #define TAMP_CR1_TAMP1E_Pos          (0U)
15720 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
15721 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
15722 #define TAMP_CR1_TAMP2E_Pos          (1U)
15723 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
15724 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
15725 #define TAMP_CR1_TAMP3E_Pos          (2U)
15726 #define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
15727 #define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
15728 #define TAMP_CR1_ITAMP1E_Pos         (16U)
15729 #define TAMP_CR1_ITAMP1E_Msk         (0x1UL << TAMP_CR1_ITAMP1E_Pos)           /*!< 0x00010000 */
15730 #define TAMP_CR1_ITAMP1E             TAMP_CR1_ITAMP1E_Msk
15731 #define TAMP_CR1_ITAMP2E_Pos         (17U)
15732 #define TAMP_CR1_ITAMP2E_Msk         (0x1UL << TAMP_CR1_ITAMP2E_Pos)           /*!< 0x00020000 */
15733 #define TAMP_CR1_ITAMP2E             TAMP_CR1_ITAMP2E_Msk
15734 #define TAMP_CR1_ITAMP3E_Pos         (18U)
15735 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
15736 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
15737 #define TAMP_CR1_ITAMP4E_Pos         (19U)
15738 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
15739 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
15740 #define TAMP_CR1_ITAMP5E_Pos         (20U)
15741 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
15742 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
15743 #define TAMP_CR1_ITAMP6E_Pos         (21U)
15744 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
15745 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
15746 #define TAMP_CR1_ITAMP8E_Pos         (23U)
15747 #define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */
15748 #define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk
15749 
15750 /********************  Bits definition for TAMP_CR2 register  *****************/
15751 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
15752 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
15753 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
15754 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
15755 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
15756 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
15757 #define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
15758 #define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
15759 #define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
15760 #define TAMP_CR2_TAMP1MSK_Pos        (16U)
15761 #define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */
15762 #define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
15763 #define TAMP_CR2_TAMP2MSK_Pos        (17U)
15764 #define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */
15765 #define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
15766 #define TAMP_CR2_TAMP3MSK_Pos        (18U)
15767 #define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */
15768 #define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk
15769 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
15770 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
15771 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
15772 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
15773 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
15774 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
15775 #define TAMP_CR2_TAMP3TRG_Pos        (26U)
15776 #define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
15777 #define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
15778 
15779 /********************  Bits definition for TAMP_FLTCR register  ***************/
15780 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
15781 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */
15782 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
15783 #define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */
15784 #define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */
15785 #define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */
15786 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
15787 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */
15788 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
15789 #define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */
15790 #define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */
15791 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
15792 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */
15793 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
15794 #define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */
15795 #define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */
15796 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
15797 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */
15798 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
15799 
15800 /*******************  Bits definition for TAMP_ATCR1 register  ****************/
15801 #define TAMP_ATCR1_TAMP1AM_Pos       (0U)
15802 #define TAMP_ATCR1_TAMP1AM_Msk       (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)         /*!< 0x00000001 */
15803 #define TAMP_ATCR1_TAMP1AM           TAMP_ATCR1_TAMP1AM_Msk
15804 #define TAMP_ATCR1_TAMP2AM_Pos       (1U)
15805 #define TAMP_ATCR1_TAMP2AM_Msk       (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)         /*!< 0x00000002 */
15806 #define TAMP_ATCR1_TAMP2AM           TAMP_ATCR1_TAMP2AM_Msk
15807 #define TAMP_ATCR1_TAMP3AM_Pos       (2U)
15808 #define TAMP_ATCR1_TAMP3AM_Msk       (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)         /*!< 0x00000004 */
15809 #define TAMP_ATCR1_TAMP3AM           TAMP_ATCR1_TAMP3AM_Msk
15810 #define TAMP_ATCR1_ATOSEL1_Pos       (8U)
15811 #define TAMP_ATCR1_ATOSEL1_Msk       (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)          /*!< 0x00000300 */
15812 #define TAMP_ATCR1_ATOSEL1            TAMP_ATCR1_ATOSEL1_Msk
15813 #define TAMP_ATCR1_ATOSEL1_0         (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000100 */
15814 #define TAMP_ATCR1_ATOSEL1_1         (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000200 */
15815 #define TAMP_ATCR1_ATOSEL2_Pos       (10U)
15816 #define TAMP_ATCR1_ATOSEL2_Msk       (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)          /*!< 0x00000C00 */
15817 #define TAMP_ATCR1_ATOSEL2            TAMP_ATCR1_ATOSEL2_Msk
15818 #define TAMP_ATCR1_ATOSEL2_0         (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000400 */
15819 #define TAMP_ATCR1_ATOSEL2_1         (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000800 */
15820 #define TAMP_ATCR1_ATOSEL3_Pos       (12U)
15821 #define TAMP_ATCR1_ATOSEL3_Msk       (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)          /*!< 0x00003000 */
15822 #define TAMP_ATCR1_ATOSEL3            TAMP_ATCR1_ATOSEL3_Msk
15823 #define TAMP_ATCR1_ATOSEL3_0         (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00001000 */
15824 #define TAMP_ATCR1_ATOSEL3_1         (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00002000 */
15825 #define TAMP_ATCR1_ATOSEL4_Pos       (14U)
15826 #define TAMP_ATCR1_ATOSEL4_Msk       (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)          /*!< 0x0000C000 */
15827 #define TAMP_ATCR1_ATOSEL4            TAMP_ATCR1_ATOSEL4_Msk
15828 #define TAMP_ATCR1_ATOSEL4_0         (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00004000 */
15829 #define TAMP_ATCR1_ATOSEL4_1         (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00008000 */
15830 #define TAMP_ATCR1_ATCKSEL_Pos       (16U)
15831 #define TAMP_ATCR1_ATCKSEL_Msk       (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)          /*!< 0x00070000 */
15832 #define TAMP_ATCR1_ATCKSEL            TAMP_ATCR1_ATCKSEL_Msk
15833 #define TAMP_ATCR1_ATCKSEL_0         (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00010000 */
15834 #define TAMP_ATCR1_ATCKSEL_1         (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00020000 */
15835 #define TAMP_ATCR1_ATCKSEL_2         (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00040000 */
15836 #define TAMP_ATCR1_ATPER_Pos         (24U)
15837 #define TAMP_ATCR1_ATPER_Msk         (0x7UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x07000000 */
15838 #define TAMP_ATCR1_ATPER             TAMP_ATCR1_ATPER_Msk
15839 #define TAMP_ATCR1_ATOSHARE_Pos      (30U)
15840 #define TAMP_ATCR1_ATOSHARE_Msk      (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)        /*!< 0x40000000 */
15841 #define TAMP_ATCR1_ATOSHARE          TAMP_ATCR1_ATOSHARE_Msk
15842 #define TAMP_ATCR1_FLTEN_Pos         (31U)
15843 #define TAMP_ATCR1_FLTEN_Msk         (0x1UL << TAMP_ATCR1_FLTEN_Pos)           /*!< 0x80000000 */
15844 #define TAMP_ATCR1_FLTEN             TAMP_ATCR1_FLTEN_Msk
15845 
15846 /********************  Bits definition for TAMP_ATSEEDR register  *************/
15847 #define TAMP_ATSEEDR_SEED_Pos        (0U)
15848 #define TAMP_ATSEEDR_SEED_Msk        (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos)   /*!< 0xFFFFFFFF */
15849 #define TAMP_ATSEEDR_SEED            TAMP_ATSEEDR_SEED_Msk
15850 
15851 /********************  Bits definition for TAMP_ATOR register  ****************/
15852 #define TAMP_ATOR_PRNG_Pos           (0U)
15853 #define TAMP_ATOR_PRNG_Msk           (0x000000FFUL << TAMP_ATOR_PRNG_Pos)      /*!< 0x000000FF */
15854 #define TAMP_ATOR_PRNG               TAMP_ATOR_PRNG_Msk
15855 #define TAMP_ATOR_SEEDF_Pos          (14U)
15856 #define TAMP_ATOR_SEEDF_Msk          (0x01UL << TAMP_ATOR_SEEDF_Pos)           /*!< 0x00004000 */
15857 #define TAMP_ATOR_SEEDF              TAMP_ATOR_SEEDF_Msk
15858 #define TAMP_ATOR_INITS_Pos          (15U)
15859 #define TAMP_ATOR_INITS_Msk          (0x01UL << TAMP_ATOR_INITS_Pos)           /*!< 0x00008000 */
15860 #define TAMP_ATOR_INITS              TAMP_ATOR_INITS_Msk
15861 
15862 /********************  Bits definition for TAMP_IER register  *****************/
15863 #define TAMP_IER_TAMP1IE_Pos         (0U)
15864 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
15865 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
15866 #define TAMP_IER_TAMP2IE_Pos         (1U)
15867 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
15868 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
15869 #define TAMP_IER_TAMP3IE_Pos         (2U)
15870 #define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
15871 #define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
15872 #define TAMP_IER_ITAMP1IE_Pos        (16U)
15873 #define TAMP_IER_ITAMP1IE_Msk        (0x1UL << TAMP_IER_ITAMP1IE_Pos)          /*!< 0x00010000 */
15874 #define TAMP_IER_ITAMP1IE            TAMP_IER_ITAMP1IE_Msk
15875 #define TAMP_IER_ITAMP2IE_Pos        (17U)
15876 #define TAMP_IER_ITAMP2IE_Msk        (0x1UL << TAMP_IER_ITAMP2IE_Pos)          /*!< 0x00020000 */
15877 #define TAMP_IER_ITAMP2IE            TAMP_IER_ITAMP2IE_Msk
15878 #define TAMP_IER_ITAMP3IE_Pos        (18U)
15879 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
15880 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
15881 #define TAMP_IER_ITAMP4IE_Pos        (19U)
15882 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
15883 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
15884 #define TAMP_IER_ITAMP5IE_Pos        (20U)
15885 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
15886 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
15887 #define TAMP_IER_ITAMP6IE_Pos        (21U)
15888 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
15889 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
15890 #define TAMP_IER_ITAMP8IE_Pos        (23U)
15891 #define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */
15892 #define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk
15893 
15894 /********************  Bits definition for TAMP_SR register  *****************/
15895 #define TAMP_SR_TAMP1F_Pos           (0U)
15896 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */
15897 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
15898 #define TAMP_SR_TAMP2F_Pos           (1U)
15899 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */
15900 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
15901 #define TAMP_SR_TAMP3F_Pos           (2U)
15902 #define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */
15903 #define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
15904 #define TAMP_SR_ITAMP1F_Pos          (16U)
15905 #define TAMP_SR_ITAMP1F_Msk          (0x1UL << TAMP_SR_ITAMP1F_Pos)            /*!< 0x00010000 */
15906 #define TAMP_SR_ITAMP1F              TAMP_SR_ITAMP1F_Msk
15907 #define TAMP_SR_ITAMP2F_Pos          (17U)
15908 #define TAMP_SR_ITAMP2F_Msk          (0x1UL << TAMP_SR_ITAMP2F_Pos)            /*!< 0x00020000 */
15909 #define TAMP_SR_ITAMP2F              TAMP_SR_ITAMP2F_Msk
15910 #define TAMP_SR_ITAMP3F_Pos          (18U)
15911 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */
15912 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
15913 #define TAMP_SR_ITAMP4F_Pos          (19U)
15914 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */
15915 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
15916 #define TAMP_SR_ITAMP5F_Pos          (20U)
15917 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */
15918 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
15919 #define TAMP_SR_ITAMP6F_Pos          (21U)
15920 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */
15921 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
15922 #define TAMP_SR_ITAMP8F_Pos          (23U)
15923 #define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)            /*!< 0x00800000 */
15924 #define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk
15925 
15926 /********************  Bits definition for TAMP_MISR register  ************ *****/
15927 #define TAMP_MISR_TAMP1MF_Pos        (0U)
15928 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */
15929 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
15930 #define TAMP_MISR_TAMP2MF_Pos        (1U)
15931 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */
15932 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
15933 #define TAMP_MISR_TAMP3MF_Pos        (2U)
15934 #define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */
15935 #define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
15936 #define TAMP_MISR_ITAMP1MF_Pos       (16U)
15937 #define TAMP_MISR_ITAMP1MF_Msk       (0x1UL << TAMP_MISR_ITAMP1MF_Pos)         /*!< 0x00010000 */
15938 #define TAMP_MISR_ITAMP1MF           TAMP_MISR_ITAMP1MF_Msk
15939 #define TAMP_MISR_ITAMP2MF_Pos       (17U)
15940 #define TAMP_MISR_ITAMP2MF_Msk       (0x1UL << TAMP_MISR_ITAMP2MF_Pos)         /*!< 0x00020000 */
15941 #define TAMP_MISR_ITAMP2MF           TAMP_MISR_ITAMP2MF_Msk
15942 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
15943 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */
15944 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
15945 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
15946 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */
15947 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
15948 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
15949 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */
15950 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
15951 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
15952 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */
15953 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
15954 #define TAMP_MISR_ITAMP8MF_Pos       (23U)
15955 #define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)         /*!< 0x00800000 */
15956 #define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk
15957 
15958 /********************  Bits definition for TAMP_SCR register  *****************/
15959 #define TAMP_SCR_CTAMP1F_Pos         (0U)
15960 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */
15961 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
15962 #define TAMP_SCR_CTAMP2F_Pos         (1U)
15963 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */
15964 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
15965 #define TAMP_SCR_CTAMP3F_Pos         (2U)
15966 #define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */
15967 #define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
15968 #define TAMP_SCR_CITAMP1F_Pos        (16U)
15969 #define TAMP_SCR_CITAMP1F_Msk        (0x1UL << TAMP_SCR_CITAMP1F_Pos)          /*!< 0x00010000 */
15970 #define TAMP_SCR_CITAMP1F            TAMP_SCR_CITAMP1F_Msk
15971 #define TAMP_SCR_CITAMP2F_Pos        (17U)
15972 #define TAMP_SCR_CITAMP2F_Msk        (0x1UL << TAMP_SCR_CITAMP2F_Pos)          /*!< 0x00020000 */
15973 #define TAMP_SCR_CITAMP2F            TAMP_SCR_CITAMP2F_Msk
15974 #define TAMP_SCR_CITAMP3F_Pos        (18U)
15975 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */
15976 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
15977 #define TAMP_SCR_CITAMP4F_Pos        (19U)
15978 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */
15979 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
15980 #define TAMP_SCR_CITAMP5F_Pos        (20U)
15981 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */
15982 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
15983 #define TAMP_SCR_CITAMP6F_Pos        (21U)
15984 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */
15985 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
15986 #define TAMP_SCR_CITAMP8F_Pos        (23U)
15987 #define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */
15988 #define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk
15989 
15990 /********************  Bits definition for TAMP_COUNTR register  **************/
15991 #define TAMP_COUNTR_Pos              (16U)
15992 #define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */
15993 #define TAMP_COUNTR                  TAMP_COUNTR_Msk
15994 
15995 /********************  Bits definition for TAMP_OR register  ******************/
15996 #define TAMP_OR_OUT3_RMP_Pos         (0U)
15997 #define TAMP_OR_OUT3_RMP_Msk         (0x1UL << TAMP_OR_OUT3_RMP_Pos)           /*!< 0x00000001 */
15998 #define TAMP_OR_OUT3_RMP             TAMP_OR_OUT3_RMP_Msk
15999 
16000 /********************  Bits definition for TAMP_BKP0R register  ***************/
16001 #define TAMP_BKP0R_Pos               (0U)
16002 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */
16003 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
16004 
16005 /********************  Bits definition for TAMP_BKP1R register  ****************/
16006 #define TAMP_BKP1R_Pos               (0U)
16007 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */
16008 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
16009 
16010 /********************  Bits definition for TAMP_BKP2R register  ****************/
16011 #define TAMP_BKP2R_Pos               (0U)
16012 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */
16013 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
16014 
16015 /********************  Bits definition for TAMP_BKP3R register  ****************/
16016 #define TAMP_BKP3R_Pos               (0U)
16017 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */
16018 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
16019 
16020 /********************  Bits definition for TAMP_BKP4R register  ****************/
16021 #define TAMP_BKP4R_Pos               (0U)
16022 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */
16023 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
16024 
16025 /********************  Bits definition for TAMP_BKP5R register  ****************/
16026 #define TAMP_BKP5R_Pos               (0U)
16027 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
16028 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
16029 
16030 /********************  Bits definition for TAMP_BKP6R register  ****************/
16031 #define TAMP_BKP6R_Pos               (0U)
16032 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
16033 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
16034 
16035 /********************  Bits definition for TAMP_BKP7R register  ****************/
16036 #define TAMP_BKP7R_Pos               (0U)
16037 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
16038 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
16039 
16040 /********************  Bits definition for TAMP_BKP8R register  ****************/
16041 #define TAMP_BKP8R_Pos               (0U)
16042 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
16043 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
16044 
16045 /********************  Bits definition for TAMP_BKP9R register  ****************/
16046 #define TAMP_BKP9R_Pos               (0U)
16047 #define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
16048 #define TAMP_BKP9R                   TAMP_BKP9R_Msk
16049 
16050 /********************  Bits definition for TAMP_BKP10R register  ***************/
16051 #define TAMP_BKP10R_Pos              (0U)
16052 #define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */
16053 #define TAMP_BKP10R                  TAMP_BKP10R_Msk
16054 
16055 /********************  Bits definition for TAMP_BKP11R register  ***************/
16056 #define TAMP_BKP11R_Pos              (0U)
16057 #define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */
16058 #define TAMP_BKP11R                  TAMP_BKP11R_Msk
16059 
16060 /********************  Bits definition for TAMP_BKP12R register  ***************/
16061 #define TAMP_BKP12R_Pos              (0U)
16062 #define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */
16063 #define TAMP_BKP12R                  TAMP_BKP12R_Msk
16064 
16065 /********************  Bits definition for TAMP_BKP13R register  ***************/
16066 #define TAMP_BKP13R_Pos              (0U)
16067 #define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */
16068 #define TAMP_BKP13R                  TAMP_BKP13R_Msk
16069 
16070 /********************  Bits definition for TAMP_BKP14R register  ***************/
16071 #define TAMP_BKP14R_Pos              (0U)
16072 #define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
16073 #define TAMP_BKP14R                  TAMP_BKP14R_Msk
16074 
16075 /********************  Bits definition for TAMP_BKP15R register  ***************/
16076 #define TAMP_BKP15R_Pos              (0U)
16077 #define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
16078 #define TAMP_BKP15R                  TAMP_BKP15R_Msk
16079 
16080 /********************  Bits definition for TAMP_BKP16R register  ***************/
16081 #define TAMP_BKP16R_Pos              (0U)
16082 #define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */
16083 #define TAMP_BKP16R                  TAMP_BKP16R_Msk
16084 
16085 /********************  Bits definition for TAMP_BKP17R register  ***************/
16086 #define TAMP_BKP17R_Pos              (0U)
16087 #define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */
16088 #define TAMP_BKP17R                  TAMP_BKP17R_Msk
16089 
16090 /********************  Bits definition for TAMP_BKP18R register  ***************/
16091 #define TAMP_BKP18R_Pos              (0U)
16092 #define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */
16093 #define TAMP_BKP18R                  TAMP_BKP18R_Msk
16094 
16095 /********************  Bits definition for TAMP_BKP19R register  ***************/
16096 #define TAMP_BKP19R_Pos              (0U)
16097 #define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */
16098 #define TAMP_BKP19R                  TAMP_BKP19R_Msk
16099 
16100 /********************  Bits definition for TAMP_BKP20R register  ***************/
16101 #define TAMP_BKP20R_Pos              (0U)
16102 #define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */
16103 #define TAMP_BKP20R                  TAMP_BKP20R_Msk
16104 
16105 /********************  Bits definition for TAMP_BKP21R register  ***************/
16106 #define TAMP_BKP21R_Pos              (0U)
16107 #define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */
16108 #define TAMP_BKP21R                  TAMP_BKP21R_Msk
16109 
16110 /********************  Bits definition for TAMP_BKP22R register  ***************/
16111 #define TAMP_BKP22R_Pos              (0U)
16112 #define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */
16113 #define TAMP_BKP22R                  TAMP_BKP22R_Msk
16114 
16115 /********************  Bits definition for TAMP_BKP23R register  ***************/
16116 #define TAMP_BKP23R_Pos              (0U)
16117 #define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */
16118 #define TAMP_BKP23R                  TAMP_BKP23R_Msk
16119 
16120 /********************  Bits definition for TAMP_BKP24R register  ***************/
16121 #define TAMP_BKP24R_Pos              (0U)
16122 #define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */
16123 #define TAMP_BKP24R                  TAMP_BKP24R_Msk
16124 
16125 /********************  Bits definition for TAMP_BKP25R register  ***************/
16126 #define TAMP_BKP25R_Pos              (0U)
16127 #define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */
16128 #define TAMP_BKP25R                  TAMP_BKP25R_Msk
16129 
16130 /********************  Bits definition for TAMP_BKP26R register  ***************/
16131 #define TAMP_BKP26R_Pos              (0U)
16132 #define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */
16133 #define TAMP_BKP26R                  TAMP_BKP26R_Msk
16134 
16135 /********************  Bits definition for TAMP_BKP27R register  ***************/
16136 #define TAMP_BKP27R_Pos              (0U)
16137 #define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */
16138 #define TAMP_BKP27R                  TAMP_BKP27R_Msk
16139 
16140 /********************  Bits definition for TAMP_BKP28R register  ***************/
16141 #define TAMP_BKP28R_Pos              (0U)
16142 #define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */
16143 #define TAMP_BKP28R                  TAMP_BKP28R_Msk
16144 
16145 /********************  Bits definition for TAMP_BKP29R register  ***************/
16146 #define TAMP_BKP29R_Pos              (0U)
16147 #define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */
16148 #define TAMP_BKP29R                  TAMP_BKP29R_Msk
16149 
16150 /********************  Bits definition for TAMP_BKP30R register  ***************/
16151 #define TAMP_BKP30R_Pos              (0U)
16152 #define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */
16153 #define TAMP_BKP30R                  TAMP_BKP30R_Msk
16154 
16155 /********************  Bits definition for TAMP_BKP31R register  ***************/
16156 #define TAMP_BKP31R_Pos              (0U)
16157 #define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */
16158 #define TAMP_BKP31R                  TAMP_BKP31R_Msk
16159 
16160 /******************** Number of backup registers ******************************/
16161 #define TAMP_BKP_NUMBER_Pos             (5U)
16162 #define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */
16163 #define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 32 BKPREG  */
16164 
16165 /******************************************************************************/
16166 /*                                                                            */
16167 /*                              SPDIF-RX Interface                            */
16168 /*                                                                            */
16169 /******************************************************************************/
16170 /********************  Bit definition for SPDIF_CR register  ******************/
16171 #define SPDIFRX_CR_SPDIFEN_Pos      (0U)
16172 #define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */
16173 #define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
16174 #define SPDIFRX_CR_RXDMAEN_Pos      (2U)
16175 #define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */
16176 #define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
16177 #define SPDIFRX_CR_RXSTEO_Pos       (3U)
16178 #define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */
16179 #define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
16180 #define SPDIFRX_CR_DRFMT_Pos        (4U)
16181 #define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */
16182 #define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
16183 #define SPDIFRX_CR_PMSK_Pos         (6U)
16184 #define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */
16185 #define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
16186 #define SPDIFRX_CR_VMSK_Pos         (7U)
16187 #define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */
16188 #define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
16189 #define SPDIFRX_CR_CUMSK_Pos        (8U)
16190 #define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */
16191 #define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
16192 #define SPDIFRX_CR_PTMSK_Pos        (9U)
16193 #define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */
16194 #define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
16195 #define SPDIFRX_CR_CBDMAEN_Pos      (10U)
16196 #define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */
16197 #define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
16198 #define SPDIFRX_CR_CHSEL_Pos        (11U)
16199 #define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */
16200 #define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
16201 #define SPDIFRX_CR_NBTR_Pos         (12U)
16202 #define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */
16203 #define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
16204 #define SPDIFRX_CR_WFA_Pos          (14U)
16205 #define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */
16206 #define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
16207 #define SPDIFRX_CR_INSEL_Pos        (16U)
16208 #define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */
16209 #define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
16210 #define SPDIFRX_CR_CKSEN_Pos        (20U)
16211 #define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */
16212 #define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */
16213 #define SPDIFRX_CR_CKSBKPEN_Pos     (21U)
16214 #define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */
16215 #define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */
16216 
16217 /*******************  Bit definition for SPDIFRX_IMR register  *******************/
16218 #define SPDIFRX_IMR_RXNEIE_Pos      (0U)
16219 #define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */
16220 #define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
16221 #define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
16222 #define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */
16223 #define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
16224 #define SPDIFRX_IMR_PERRIE_Pos      (2U)
16225 #define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */
16226 #define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
16227 #define SPDIFRX_IMR_OVRIE_Pos       (3U)
16228 #define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */
16229 #define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
16230 #define SPDIFRX_IMR_SBLKIE_Pos      (4U)
16231 #define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */
16232 #define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
16233 #define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
16234 #define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */
16235 #define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
16236 #define SPDIFRX_IMR_IFEIE_Pos       (6U)
16237 #define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */
16238 #define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
16239 
16240 /*******************  Bit definition for SPDIFRX_SR register  *******************/
16241 #define SPDIFRX_SR_RXNE_Pos         (0U)
16242 #define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */
16243 #define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
16244 #define SPDIFRX_SR_CSRNE_Pos        (1U)
16245 #define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */
16246 #define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
16247 #define SPDIFRX_SR_PERR_Pos         (2U)
16248 #define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */
16249 #define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
16250 #define SPDIFRX_SR_OVR_Pos          (3U)
16251 #define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */
16252 #define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
16253 #define SPDIFRX_SR_SBD_Pos          (4U)
16254 #define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */
16255 #define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
16256 #define SPDIFRX_SR_SYNCD_Pos        (5U)
16257 #define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */
16258 #define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
16259 #define SPDIFRX_SR_FERR_Pos         (6U)
16260 #define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */
16261 #define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
16262 #define SPDIFRX_SR_SERR_Pos         (7U)
16263 #define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */
16264 #define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
16265 #define SPDIFRX_SR_TERR_Pos         (8U)
16266 #define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */
16267 #define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
16268 #define SPDIFRX_SR_WIDTH5_Pos       (16U)
16269 #define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */
16270 #define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
16271 
16272 /*******************  Bit definition for SPDIFRX_IFCR register  *******************/
16273 #define SPDIFRX_IFCR_PERRCF_Pos     (2U)
16274 #define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */
16275 #define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
16276 #define SPDIFRX_IFCR_OVRCF_Pos      (3U)
16277 #define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */
16278 #define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
16279 #define SPDIFRX_IFCR_SBDCF_Pos      (4U)
16280 #define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */
16281 #define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
16282 #define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
16283 #define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */
16284 #define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
16285 
16286 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
16287 #define SPDIFRX_DR0_DR_Pos          (0U)
16288 #define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */
16289 #define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
16290 #define SPDIFRX_DR0_PE_Pos          (24U)
16291 #define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */
16292 #define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
16293 #define SPDIFRX_DR0_V_Pos           (25U)
16294 #define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */
16295 #define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
16296 #define SPDIFRX_DR0_U_Pos           (26U)
16297 #define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */
16298 #define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
16299 #define SPDIFRX_DR0_C_Pos           (27U)
16300 #define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */
16301 #define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
16302 #define SPDIFRX_DR0_PT_Pos          (28U)
16303 #define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */
16304 #define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
16305 
16306 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
16307 #define SPDIFRX_DR1_DR_Pos          (8U)
16308 #define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */
16309 #define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
16310 #define SPDIFRX_DR1_PT_Pos          (4U)
16311 #define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */
16312 #define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
16313 #define SPDIFRX_DR1_C_Pos           (3U)
16314 #define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */
16315 #define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
16316 #define SPDIFRX_DR1_U_Pos           (2U)
16317 #define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */
16318 #define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
16319 #define SPDIFRX_DR1_V_Pos           (1U)
16320 #define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */
16321 #define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
16322 #define SPDIFRX_DR1_PE_Pos          (0U)
16323 #define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */
16324 #define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
16325 
16326 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
16327 #define SPDIFRX_DR1_DRNL1_Pos       (16U)
16328 #define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */
16329 #define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
16330 #define SPDIFRX_DR1_DRNL2_Pos       (0U)
16331 #define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */
16332 #define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
16333 
16334 /*******************  Bit definition for SPDIFRX_CSR register   *******************/
16335 #define SPDIFRX_CSR_USR_Pos         (0U)
16336 #define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */
16337 #define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
16338 #define SPDIFRX_CSR_CS_Pos          (16U)
16339 #define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */
16340 #define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
16341 #define SPDIFRX_CSR_SOB_Pos         (24U)
16342 #define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */
16343 #define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
16344 
16345 /*******************  Bit definition for SPDIFRX_DIR register    *******************/
16346 #define SPDIFRX_DIR_THI_Pos         (0U)
16347 #define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */
16348 #define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
16349 #define SPDIFRX_DIR_TLO_Pos         (16U)
16350 #define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */
16351 #define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
16352 
16353 /*******************  Bit definition for SPDIFRX_VERR register    *******************/
16354 #define SPDIFRX_VERR_MINREV_Pos     (0U)
16355 #define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */
16356 #define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */
16357 #define SPDIFRX_VERR_MAJREV_Pos     (4U)
16358 #define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */
16359 #define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */
16360 
16361 /*******************  Bit definition for SPDIFRX_IDR register    *******************/
16362 #define SPDIFRX_IDR_ID_Pos          (0U)
16363 #define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */
16364 #define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */
16365 
16366 /*******************  Bit definition for SPDIFRX_SIDR register    *******************/
16367 #define SPDIFRX_SIDR_SID_Pos        (0U)
16368 #define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */
16369 #define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */
16370 
16371 /******************************************************************************/
16372 /*                                                                            */
16373 /*                          Serial Audio Interface                            */
16374 /*                                                                            */
16375 /******************************************************************************/
16376 /*******************************  SAI VERSION  ********************************/
16377 #define SAI_VER_V2_1
16378 
16379 /********************  Bit definition for SAI_GCR register  *******************/
16380 #define SAI_GCR_SYNCIN_Pos         (0U)
16381 #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
16382 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
16383 #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
16384 #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
16385 
16386 #define SAI_GCR_SYNCOUT_Pos        (4U)
16387 #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
16388 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
16389 #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
16390 #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
16391 
16392 /*******************  Bit definition for SAI_xCR1 register  *******************/
16393 #define SAI_xCR1_MODE_Pos          (0U)
16394 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
16395 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
16396 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
16397 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
16398 
16399 #define SAI_xCR1_PRTCFG_Pos        (2U)
16400 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
16401 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
16402 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
16403 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
16404 
16405 #define SAI_xCR1_DS_Pos            (5U)
16406 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
16407 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
16408 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
16409 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
16410 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
16411 
16412 #define SAI_xCR1_LSBFIRST_Pos      (8U)
16413 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
16414 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
16415 #define SAI_xCR1_CKSTR_Pos         (9U)
16416 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
16417 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
16418 
16419 #define SAI_xCR1_SYNCEN_Pos        (10U)
16420 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
16421 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
16422 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
16423 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
16424 
16425 #define SAI_xCR1_MONO_Pos          (12U)
16426 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
16427 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
16428 #define SAI_xCR1_OUTDRIV_Pos       (13U)
16429 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
16430 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
16431 #define SAI_xCR1_SAIEN_Pos         (16U)
16432 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
16433 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
16434 #define SAI_xCR1_DMAEN_Pos         (17U)
16435 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
16436 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
16437 #define SAI_xCR1_NODIV_Pos         (19U)
16438 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
16439 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
16440 
16441 #define SAI_xCR1_MCKDIV_Pos        (20U)
16442 #define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
16443 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
16444 #define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
16445 #define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
16446 #define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
16447 #define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
16448 #define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */
16449 #define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */
16450 
16451 #define SAI_xCR1_MCKEN_Pos         (27U)
16452 #define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
16453 #define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */
16454 
16455 #define SAI_xCR1_OSR_Pos           (26U)
16456 #define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
16457 #define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */
16458 
16459 /* Legacy define */
16460 #define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV
16461 
16462 /*******************  Bit definition for SAI_xCR2 register  *******************/
16463 #define SAI_xCR2_FTH_Pos           (0U)
16464 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
16465 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
16466 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
16467 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
16468 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
16469 
16470 #define SAI_xCR2_FFLUSH_Pos        (3U)
16471 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
16472 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
16473 #define SAI_xCR2_TRIS_Pos          (4U)
16474 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
16475 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
16476 #define SAI_xCR2_MUTE_Pos          (5U)
16477 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
16478 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
16479 #define SAI_xCR2_MUTEVAL_Pos       (6U)
16480 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
16481 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
16482 
16483 #define SAI_xCR2_MUTECNT_Pos       (7U)
16484 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
16485 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
16486 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
16487 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
16488 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
16489 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
16490 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
16491 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
16492 
16493 #define SAI_xCR2_CPL_Pos           (13U)
16494 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
16495 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
16496 
16497 #define SAI_xCR2_COMP_Pos          (14U)
16498 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
16499 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
16500 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
16501 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
16502 
16503 /******************  Bit definition for SAI_xFRCR register  *******************/
16504 #define SAI_xFRCR_FRL_Pos          (0U)
16505 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
16506 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */
16507 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
16508 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
16509 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
16510 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
16511 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
16512 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
16513 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
16514 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
16515 
16516 #define SAI_xFRCR_FSALL_Pos        (8U)
16517 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
16518 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */
16519 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
16520 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
16521 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
16522 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
16523 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
16524 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
16525 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
16526 
16527 #define SAI_xFRCR_FSDEF_Pos        (16U)
16528 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
16529 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
16530 #define SAI_xFRCR_FSPOL_Pos        (17U)
16531 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
16532 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
16533 #define SAI_xFRCR_FSOFF_Pos        (18U)
16534 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
16535 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
16536 
16537 /* Legacy define */
16538 #define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
16539 
16540 /******************  Bit definition for SAI_xSLOTR register  *******************/
16541 #define SAI_xSLOTR_FBOFF_Pos       (0U)
16542 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
16543 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */
16544 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
16545 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
16546 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
16547 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
16548 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
16549 
16550 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
16551 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
16552 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
16553 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
16554 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
16555 
16556 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
16557 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
16558 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
16559 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
16560 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
16561 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
16562 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
16563 
16564 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
16565 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
16566 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
16567 
16568 /*******************  Bit definition for SAI_xIMR register  *******************/
16569 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
16570 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
16571 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
16572 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
16573 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
16574 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
16575 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
16576 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
16577 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
16578 #define SAI_xIMR_FREQIE_Pos        (3U)
16579 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
16580 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
16581 #define SAI_xIMR_CNRDYIE_Pos       (4U)
16582 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
16583 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
16584 #define SAI_xIMR_AFSDETIE_Pos      (5U)
16585 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
16586 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
16587 #define SAI_xIMR_LFSDETIE_Pos      (6U)
16588 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
16589 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
16590 
16591 /********************  Bit definition for SAI_xSR register  *******************/
16592 #define SAI_xSR_OVRUDR_Pos         (0U)
16593 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
16594 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
16595 #define SAI_xSR_MUTEDET_Pos        (1U)
16596 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
16597 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
16598 #define SAI_xSR_WCKCFG_Pos         (2U)
16599 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
16600 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
16601 #define SAI_xSR_FREQ_Pos           (3U)
16602 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
16603 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
16604 #define SAI_xSR_CNRDY_Pos          (4U)
16605 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
16606 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
16607 #define SAI_xSR_AFSDET_Pos         (5U)
16608 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
16609 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
16610 #define SAI_xSR_LFSDET_Pos         (6U)
16611 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
16612 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
16613 
16614 #define SAI_xSR_FLVL_Pos           (16U)
16615 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
16616 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
16617 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
16618 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
16619 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
16620 
16621 /******************  Bit definition for SAI_xCLRFR register  ******************/
16622 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
16623 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
16624 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
16625 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
16626 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
16627 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
16628 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
16629 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
16630 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
16631 #define SAI_xCLRFR_CFREQ_Pos       (3U)
16632 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
16633 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
16634 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
16635 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
16636 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
16637 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
16638 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
16639 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
16640 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
16641 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
16642 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
16643 
16644 /******************  Bit definition for SAI_xDR register  *********************/
16645 #define SAI_xDR_DATA_Pos           (0U)
16646 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
16647 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
16648 
16649 /*******************  Bit definition for SAI_PDMCR register  ******************/
16650 #define SAI_PDMCR_PDMEN_Pos        (0U)
16651 #define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
16652 #define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */
16653 
16654 #define SAI_PDMCR_MICNBR_Pos       (4U)
16655 #define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
16656 #define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */
16657 #define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */
16658 #define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */
16659 
16660 #define SAI_PDMCR_CKEN1_Pos        (8U)
16661 #define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
16662 #define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */
16663 #define SAI_PDMCR_CKEN2_Pos        (9U)
16664 #define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
16665 #define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */
16666 #define SAI_PDMCR_CKEN3_Pos        (10U)
16667 #define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
16668 #define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */
16669 #define SAI_PDMCR_CKEN4_Pos        (11U)
16670 #define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
16671 #define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */
16672 
16673 /******************  Bit definition for SAI_PDMDLY register  ******************/
16674 #define SAI_PDMDLY_DLYM1L_Pos      (0U)
16675 #define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
16676 #define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
16677 #define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */
16678 #define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */
16679 #define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */
16680 
16681 #define SAI_PDMDLY_DLYM1R_Pos      (4U)
16682 #define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
16683 #define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
16684 #define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */
16685 #define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */
16686 #define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */
16687 
16688 #define SAI_PDMDLY_DLYM2L_Pos      (8U)
16689 #define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
16690 #define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
16691 #define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */
16692 #define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */
16693 #define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */
16694 
16695 #define SAI_PDMDLY_DLYM2R_Pos      (12U)
16696 #define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
16697 #define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
16698 #define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */
16699 #define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */
16700 #define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */
16701 
16702 #define SAI_PDMDLY_DLYM3L_Pos      (16U)
16703 #define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
16704 #define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
16705 #define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */
16706 #define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */
16707 #define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */
16708 
16709 #define SAI_PDMDLY_DLYM3R_Pos      (20U)
16710 #define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
16711 #define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
16712 #define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */
16713 #define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */
16714 #define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */
16715 
16716 #define SAI_PDMDLY_DLYM4L_Pos      (24U)
16717 #define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
16718 #define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
16719 #define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */
16720 #define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */
16721 #define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */
16722 
16723 #define SAI_PDMDLY_DLYM4R_Pos      (28U)
16724 #define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
16725 #define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
16726 #define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */
16727 #define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */
16728 #define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */
16729 
16730 /******************************************************************************/
16731 /*                                                                            */
16732 /*                           SDMMC Interface                                  */
16733 /*                                                                            */
16734 /******************************************************************************/
16735 /******************  Bit definition for SDMMC_POWER register  ******************/
16736 #define SDMMC_POWER_PWRCTRL_Pos          (0U)
16737 #define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */
16738 #define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
16739 #define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */
16740 #define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */
16741 #define SDMMC_POWER_VSWITCH_Pos          (2U)
16742 #define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */
16743 #define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */
16744 #define SDMMC_POWER_VSWITCHEN_Pos        (3U)
16745 #define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */
16746 #define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */
16747 #define SDMMC_POWER_DIRPOL_Pos           (4U)
16748 #define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */
16749 #define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */
16750 
16751 /******************  Bit definition for SDMMC_CLKCR register  ******************/
16752 #define SDMMC_CLKCR_CLKDIV_Pos           (0U)
16753 #define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */
16754 #define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */
16755 #define SDMMC_CLKCR_PWRSAV_Pos           (12U)
16756 #define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */
16757 #define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */
16758 
16759 #define SDMMC_CLKCR_WIDBUS_Pos           (14U)
16760 #define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */
16761 #define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
16762 #define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */
16763 #define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */
16764 
16765 #define SDMMC_CLKCR_NEGEDGE_Pos          (16U)
16766 #define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */
16767 #define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */
16768 #define SDMMC_CLKCR_HWFC_EN_Pos          (17U)
16769 #define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */
16770 #define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */
16771 #define SDMMC_CLKCR_DDR_Pos              (18U)
16772 #define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */
16773 #define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */
16774 #define SDMMC_CLKCR_BUSSPEED_Pos         (19U)
16775 #define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */
16776 #define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */
16777 #define SDMMC_CLKCR_SELCLKRX_Pos         (20U)
16778 #define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */
16779 #define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */
16780 #define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */
16781 #define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */
16782 
16783 /*******************  Bit definition for SDMMC_ARG register  *******************/
16784 #define SDMMC_ARG_CMDARG_Pos             (0U)
16785 #define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
16786 #define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */
16787 
16788 /*******************  Bit definition for SDMMC_CMD register  *******************/
16789 #define SDMMC_CMD_CMDINDEX_Pos           (0U)
16790 #define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */
16791 #define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */
16792 #define SDMMC_CMD_CMDTRANS_Pos           (6U)
16793 #define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */
16794 #define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */
16795 #define SDMMC_CMD_CMDSTOP_Pos            (7U)
16796 #define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */
16797 #define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */
16798 
16799 #define SDMMC_CMD_WAITRESP_Pos           (8U)
16800 #define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */
16801 #define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */
16802 #define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */
16803 #define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */
16804 
16805 #define SDMMC_CMD_WAITINT_Pos            (10U)
16806 #define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */
16807 #define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */
16808 #define SDMMC_CMD_WAITPEND_Pos           (11U)
16809 #define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */
16810 #define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
16811 #define SDMMC_CMD_CPSMEN_Pos             (12U)
16812 #define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */
16813 #define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */
16814 #define SDMMC_CMD_DTHOLD_Pos             (13U)
16815 #define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */
16816 #define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */
16817 #define SDMMC_CMD_BOOTMODE_Pos           (14U)
16818 #define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */
16819 #define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */
16820 #define SDMMC_CMD_BOOTEN_Pos             (15U)
16821 #define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */
16822 #define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */
16823 #define SDMMC_CMD_CMDSUSPEND_Pos         (16U)
16824 #define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */
16825 #define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */
16826 
16827 /*****************  Bit definition for SDMMC_RESPCMD register  *****************/
16828 #define SDMMC_RESPCMD_RESPCMD_Pos        (0U)
16829 #define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
16830 #define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */
16831 
16832 /******************  Bit definition for SDMMC_RESP0 register  ******************/
16833 #define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)
16834 #define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
16835 #define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */
16836 
16837 /******************  Bit definition for SDMMC_RESP1 register  ******************/
16838 #define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)
16839 #define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
16840 #define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */
16841 
16842 /******************  Bit definition for SDMMC_RESP2 register  ******************/
16843 #define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)
16844 #define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
16845 #define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */
16846 
16847 /******************  Bit definition for SDMMC_RESP3 register  ******************/
16848 #define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)
16849 #define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
16850 #define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */
16851 
16852 /******************  Bit definition for SDMMC_RESP4 register  ******************/
16853 #define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)
16854 #define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
16855 #define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */
16856 
16857 /******************  Bit definition for SDMMC_DTIMER register  *****************/
16858 #define SDMMC_DTIMER_DATATIME_Pos        (0U)
16859 #define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
16860 #define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */
16861 
16862 /******************  Bit definition for SDMMC_DLEN register  *******************/
16863 #define SDMMC_DLEN_DATALENGTH_Pos        (0U)
16864 #define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
16865 #define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */
16866 
16867 /******************  Bit definition for SDMMC_DCTRL register  ******************/
16868 #define SDMMC_DCTRL_DTEN_Pos             (0U)
16869 #define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */
16870 #define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */
16871 #define SDMMC_DCTRL_DTDIR_Pos            (1U)
16872 #define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */
16873 #define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */
16874 #define SDMMC_DCTRL_DTMODE_Pos           (2U)
16875 #define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */
16876 #define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */
16877 #define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */
16878 #define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */
16879 
16880 #define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)
16881 #define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
16882 #define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
16883 #define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */
16884 #define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */
16885 #define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */
16886 #define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */
16887 
16888 #define SDMMC_DCTRL_RWSTART_Pos          (8U)
16889 #define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */
16890 #define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */
16891 #define SDMMC_DCTRL_RWSTOP_Pos           (9U)
16892 #define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */
16893 #define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */
16894 #define SDMMC_DCTRL_RWMOD_Pos            (10U)
16895 #define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */
16896 #define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */
16897 #define SDMMC_DCTRL_SDIOEN_Pos           (11U)
16898 #define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */
16899 #define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */
16900 #define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)
16901 #define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */
16902 #define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */
16903 #define SDMMC_DCTRL_FIFORST_Pos          (13U)
16904 #define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */
16905 #define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */
16906 
16907 /******************  Bit definition for SDMMC_DCOUNT register  *****************/
16908 #define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)
16909 #define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
16910 #define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */
16911 
16912 /******************  Bit definition for SDMMC_STA register  ********************/
16913 #define SDMMC_STA_CCRCFAIL_Pos           (0U)
16914 #define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */
16915 #define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */
16916 #define SDMMC_STA_DCRCFAIL_Pos           (1U)
16917 #define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */
16918 #define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */
16919 #define SDMMC_STA_CTIMEOUT_Pos           (2U)
16920 #define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */
16921 #define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */
16922 #define SDMMC_STA_DTIMEOUT_Pos           (3U)
16923 #define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */
16924 #define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */
16925 #define SDMMC_STA_TXUNDERR_Pos           (4U)
16926 #define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */
16927 #define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */
16928 #define SDMMC_STA_RXOVERR_Pos            (5U)
16929 #define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */
16930 #define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */
16931 #define SDMMC_STA_CMDREND_Pos            (6U)
16932 #define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */
16933 #define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */
16934 #define SDMMC_STA_CMDSENT_Pos            (7U)
16935 #define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */
16936 #define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */
16937 #define SDMMC_STA_DATAEND_Pos            (8U)
16938 #define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */
16939 #define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */
16940 #define SDMMC_STA_DHOLD_Pos              (9U)
16941 #define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */
16942 #define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */
16943 #define SDMMC_STA_DBCKEND_Pos            (10U)
16944 #define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */
16945 #define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */
16946 #define SDMMC_STA_DABORT_Pos             (11U)
16947 #define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */
16948 #define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */
16949 #define SDMMC_STA_DPSMACT_Pos            (12U)
16950 #define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */
16951 #define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */
16952 #define SDMMC_STA_CPSMACT_Pos            (13U)
16953 #define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */
16954 #define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */
16955 #define SDMMC_STA_TXFIFOHE_Pos           (14U)
16956 #define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */
16957 #define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
16958 #define SDMMC_STA_RXFIFOHF_Pos           (15U)
16959 #define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */
16960 #define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
16961 #define SDMMC_STA_TXFIFOF_Pos            (16U)
16962 #define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */
16963 #define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */
16964 #define SDMMC_STA_RXFIFOF_Pos            (17U)
16965 #define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */
16966 #define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */
16967 #define SDMMC_STA_TXFIFOE_Pos            (18U)
16968 #define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */
16969 #define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */
16970 #define SDMMC_STA_RXFIFOE_Pos            (19U)
16971 #define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */
16972 #define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */
16973 #define SDMMC_STA_BUSYD0_Pos             (20U)
16974 #define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */
16975 #define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
16976 #define SDMMC_STA_BUSYD0END_Pos          (21U)
16977 #define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */
16978 #define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
16979 #define SDMMC_STA_SDIOIT_Pos             (22U)
16980 #define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */
16981 #define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */
16982 #define SDMMC_STA_ACKFAIL_Pos            (23U)
16983 #define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */
16984 #define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */
16985 #define SDMMC_STA_ACKTIMEOUT_Pos         (24U)
16986 #define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */
16987 #define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */
16988 #define SDMMC_STA_VSWEND_Pos             (25U)
16989 #define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */
16990 #define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */
16991 #define SDMMC_STA_CKSTOP_Pos             (26U)
16992 #define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */
16993 #define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */
16994 #define SDMMC_STA_IDMATE_Pos             (27U)
16995 #define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */
16996 #define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */
16997 #define SDMMC_STA_IDMABTC_Pos            (28U)
16998 #define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */
16999 #define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */
17000 
17001 /*******************  Bit definition for SDMMC_ICR register  *******************/
17002 #define SDMMC_ICR_CCRCFAILC_Pos          (0U)
17003 #define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */
17004 #define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */
17005 #define SDMMC_ICR_DCRCFAILC_Pos          (1U)
17006 #define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */
17007 #define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */
17008 #define SDMMC_ICR_CTIMEOUTC_Pos          (2U)
17009 #define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */
17010 #define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */
17011 #define SDMMC_ICR_DTIMEOUTC_Pos          (3U)
17012 #define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */
17013 #define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */
17014 #define SDMMC_ICR_TXUNDERRC_Pos          (4U)
17015 #define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */
17016 #define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */
17017 #define SDMMC_ICR_RXOVERRC_Pos           (5U)
17018 #define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */
17019 #define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */
17020 #define SDMMC_ICR_CMDRENDC_Pos           (6U)
17021 #define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */
17022 #define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */
17023 #define SDMMC_ICR_CMDSENTC_Pos           (7U)
17024 #define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */
17025 #define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */
17026 #define SDMMC_ICR_DATAENDC_Pos           (8U)
17027 #define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */
17028 #define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */
17029 #define SDMMC_ICR_DHOLDC_Pos             (9U)
17030 #define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */
17031 #define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */
17032 #define SDMMC_ICR_DBCKENDC_Pos           (10U)
17033 #define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */
17034 #define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */
17035 #define SDMMC_ICR_DABORTC_Pos            (11U)
17036 #define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */
17037 #define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */
17038 #define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)
17039 #define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */
17040 #define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */
17041 #define SDMMC_ICR_SDIOITC_Pos            (22U)
17042 #define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */
17043 #define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */
17044 #define SDMMC_ICR_ACKFAILC_Pos           (23U)
17045 #define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */
17046 #define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */
17047 #define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)
17048 #define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */
17049 #define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */
17050 #define SDMMC_ICR_VSWENDC_Pos            (25U)
17051 #define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */
17052 #define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */
17053 #define SDMMC_ICR_CKSTOPC_Pos            (26U)
17054 #define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */
17055 #define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */
17056 #define SDMMC_ICR_IDMATEC_Pos            (27U)
17057 #define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */
17058 #define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */
17059 #define SDMMC_ICR_IDMABTCC_Pos           (28U)
17060 #define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */
17061 #define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */
17062 
17063 /******************  Bit definition for SDMMC_MASK register  *******************/
17064 #define SDMMC_MASK_CCRCFAILIE_Pos        (0U)
17065 #define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */
17066 #define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */
17067 #define SDMMC_MASK_DCRCFAILIE_Pos        (1U)
17068 #define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */
17069 #define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */
17070 #define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)
17071 #define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */
17072 #define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */
17073 #define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)
17074 #define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */
17075 #define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */
17076 #define SDMMC_MASK_TXUNDERRIE_Pos        (4U)
17077 #define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */
17078 #define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */
17079 #define SDMMC_MASK_RXOVERRIE_Pos         (5U)
17080 #define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */
17081 #define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */
17082 #define SDMMC_MASK_CMDRENDIE_Pos         (6U)
17083 #define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */
17084 #define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */
17085 #define SDMMC_MASK_CMDSENTIE_Pos         (7U)
17086 #define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */
17087 #define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */
17088 #define SDMMC_MASK_DATAENDIE_Pos         (8U)
17089 #define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */
17090 #define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */
17091 #define SDMMC_MASK_DHOLDIE_Pos           (9U)
17092 #define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */
17093 #define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */
17094 #define SDMMC_MASK_DBCKENDIE_Pos         (10U)
17095 #define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */
17096 #define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */
17097 #define SDMMC_MASK_DABORTIE_Pos          (11U)
17098 #define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */
17099 #define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */
17100 
17101 #define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)
17102 #define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */
17103 #define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */
17104 #define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)
17105 #define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */
17106 #define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */
17107 
17108 #define SDMMC_MASK_RXFIFOFIE_Pos         (17U)
17109 #define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */
17110 #define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */
17111 #define SDMMC_MASK_TXFIFOEIE_Pos         (18U)
17112 #define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */
17113 #define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */
17114 
17115 #define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)
17116 #define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
17117 #define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */
17118 #define SDMMC_MASK_SDIOITIE_Pos           (22U)
17119 #define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
17120 #define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */
17121 #define SDMMC_MASK_ACKFAILIE_Pos         (23U)
17122 #define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */
17123 #define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */
17124 #define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)
17125 #define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
17126 #define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */
17127 #define SDMMC_MASK_VSWENDIE_Pos          (25U)
17128 #define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */
17129 #define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */
17130 #define SDMMC_MASK_CKSTOPIE_Pos          (26U)
17131 #define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */
17132 #define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */
17133 #define SDMMC_MASK_IDMABTCIE_Pos         (28U)
17134 #define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */
17135 #define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */
17136 
17137 /*****************  Bit definition for SDMMC_ACKTIME register  *****************/
17138 #define SDMMC_ACKTIME_ACKTIME_Pos        (0U)
17139 #define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
17140 #define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */
17141 
17142 /******************  Bit definition for SDMMC_FIFO register  *******************/
17143 #define SDMMC_FIFO_FIFODATA_Pos          (0U)
17144 #define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
17145 #define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */
17146 
17147 /******************  Bit definition for SDMMC_IDMACTRL register ****************/
17148 #define SDMMC_IDMA_IDMAEN_Pos            (0U)
17149 #define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */
17150 #define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */
17151 #define SDMMC_IDMA_IDMABMODE_Pos         (1U)
17152 #define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */
17153 #define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */
17154 #define SDMMC_IDMA_IDMABACT_Pos          (2U)
17155 #define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */
17156 #define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */
17157 
17158 /*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
17159 #define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)
17160 #define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
17161 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
17162 
17163 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
17164 #define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
17165 
17166 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
17167 #define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
17168 
17169 /******************************************************************************/
17170 /*                                                                            */
17171 /*                        Delay Block Interface (DLYB)                        */
17172 /*                                                                            */
17173 /******************************************************************************/
17174 /*******************  Bit definition for DLYB_CR register  ********************/
17175 #define DLYB_CR_DEN_Pos         (0U)
17176 #define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */
17177 #define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */
17178 #define DLYB_CR_SEN_Pos         (1U)
17179 #define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */
17180 #define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */
17181 
17182 
17183 /*******************  Bit definition for DLYB_CFGR register  ********************/
17184 #define DLYB_CFGR_SEL_Pos       (0U)
17185 #define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */
17186 #define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */
17187 #define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */
17188 #define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */
17189 #define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */
17190 #define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */
17191 
17192 #define DLYB_CFGR_UNIT_Pos      (8U)
17193 #define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */
17194 #define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */
17195 #define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */
17196 #define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */
17197 #define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */
17198 #define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */
17199 #define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */
17200 #define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */
17201 #define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */
17202 
17203 #define DLYB_CFGR_LNG_Pos       (16U)
17204 #define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */
17205 #define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */
17206 #define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */
17207 #define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */
17208 #define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */
17209 #define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */
17210 #define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */
17211 #define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */
17212 #define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */
17213 #define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */
17214 #define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */
17215 #define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */
17216 #define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */
17217 #define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */
17218 
17219 #define DLYB_CFGR_LNGF_Pos      (31U)
17220 #define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */
17221 #define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */
17222 
17223 /******************************************************************************/
17224 /*                                                                            */
17225 /*                   Serial Peripheral Interface (SPI/I2S)                    */
17226 /*                                                                            */
17227 /******************************************************************************/
17228 #define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */
17229 /*******************  Bit definition for SPI_CR1 register  ********************/
17230 #define SPI_CR1_SPE_Pos             (0U)
17231 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
17232 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */
17233 #define SPI_CR1_MASRX_Pos           (8U)
17234 #define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */
17235 #define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */
17236 #define SPI_CR1_CSTART_Pos          (9U)
17237 #define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */
17238 #define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */
17239 #define SPI_CR1_CSUSP_Pos           (10U)
17240 #define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */
17241 #define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */
17242 #define SPI_CR1_HDDIR_Pos           (11U)
17243 #define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */
17244 #define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */
17245 #define SPI_CR1_SSI_Pos             (12U)
17246 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */
17247 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */
17248 #define SPI_CR1_CRC33_17_Pos        (13U)
17249 #define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */
17250 #define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */
17251 #define SPI_CR1_RCRCINI_Pos         (14U)
17252 #define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */
17253 #define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */
17254 #define SPI_CR1_TCRCINI_Pos         (15U)
17255 #define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */
17256 #define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */
17257 #define SPI_CR1_IOLOCK_Pos          (16U)
17258 #define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */
17259 #define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */
17260 
17261 /*******************  Bit definition for SPI_CR2 register  ********************/
17262 #define SPI_CR2_TSER_Pos            (16U)
17263 #define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */
17264 #define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */
17265 #define SPI_CR2_TSIZE_Pos           (0U)
17266 #define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */
17267 #define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */
17268 
17269 /*******************  Bit definition for SPI_CFG1 register  ********************/
17270 #define SPI_CFG1_DSIZE_Pos          (0U)
17271 #define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */
17272 #define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */
17273 #define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */
17274 #define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */
17275 #define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */
17276 #define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */
17277 #define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */
17278 
17279 #define SPI_CFG1_FTHLV_Pos          (5U)
17280 #define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */
17281 #define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/
17282 #define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */
17283 #define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */
17284 #define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */
17285 #define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */
17286 
17287 #define SPI_CFG1_UDRCFG_Pos         (9U)
17288 #define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */
17289 #define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
17290 #define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */
17291 #define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */
17292 
17293 
17294 #define SPI_CFG1_UDRDET_Pos         (11U)
17295 #define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */
17296 #define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */
17297 #define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */
17298 #define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */
17299 
17300 #define SPI_CFG1_RXDMAEN_Pos        (14U)
17301 #define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */
17302 #define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */
17303 #define SPI_CFG1_TXDMAEN_Pos        (15U)
17304 #define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */
17305 #define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */
17306 
17307 #define SPI_CFG1_CRCSIZE_Pos        (16U)
17308 #define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */
17309 #define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/
17310 #define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */
17311 #define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */
17312 #define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */
17313 #define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */
17314 #define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */
17315 
17316 #define SPI_CFG1_CRCEN_Pos          (22U)
17317 #define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */
17318 #define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */
17319 
17320 #define SPI_CFG1_MBR_Pos            (28U)
17321 #define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */
17322 #define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */
17323 #define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */
17324 #define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */
17325 #define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */
17326 
17327 /*******************  Bit definition for SPI_CFG2 register  ********************/
17328 #define SPI_CFG2_MSSI_Pos           (0U)
17329 #define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */
17330 #define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */
17331 #define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */
17332 #define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */
17333 #define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */
17334 #define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */
17335 
17336 #define SPI_CFG2_MIDI_Pos           (4U)
17337 #define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */
17338 #define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */
17339 #define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */
17340 #define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */
17341 #define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */
17342 #define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */
17343 
17344 #define SPI_CFG2_IOSWP_Pos          (15U)
17345 #define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */
17346 #define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */
17347 
17348 #define SPI_CFG2_COMM_Pos           (17U)
17349 #define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */
17350 #define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/
17351 #define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */
17352 #define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */
17353 
17354 #define SPI_CFG2_SP_Pos             (19U)
17355 #define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */
17356 #define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */
17357 #define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */
17358 #define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */
17359 #define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */
17360 
17361 #define SPI_CFG2_MASTER_Pos         (22U)
17362 #define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */
17363 #define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */
17364 #define SPI_CFG2_LSBFRST_Pos        (23U)
17365 #define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */
17366 #define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */
17367 #define SPI_CFG2_CPHA_Pos           (24U)
17368 #define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */
17369 #define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */
17370 #define SPI_CFG2_CPOL_Pos           (25U)
17371 #define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */
17372 #define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */
17373 #define SPI_CFG2_SSM_Pos            (26U)
17374 #define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */
17375 #define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */
17376 
17377 #define SPI_CFG2_SSIOP_Pos          (28U)
17378 #define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */
17379 #define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */
17380 #define SPI_CFG2_SSOE_Pos           (29U)
17381 #define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */
17382 #define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */
17383 #define SPI_CFG2_SSOM_Pos           (30U)
17384 #define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */
17385 #define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */
17386 
17387 #define SPI_CFG2_AFCNTR_Pos         (31U)
17388 #define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */
17389 #define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */
17390 
17391 /*******************  Bit definition for SPI_IER register  ********************/
17392 #define SPI_IER_RXPIE_Pos           (0U)
17393 #define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */
17394 #define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */
17395 #define SPI_IER_TXPIE_Pos           (1U)
17396 #define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */
17397 #define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */
17398 #define SPI_IER_DXPIE_Pos           (2U)
17399 #define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */
17400 #define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */
17401 #define SPI_IER_EOTIE_Pos           (3U)
17402 #define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */
17403 #define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */
17404 #define SPI_IER_TXTFIE_Pos          (4U)
17405 #define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */
17406 #define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */
17407 #define SPI_IER_UDRIE_Pos           (5U)
17408 #define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */
17409 #define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */
17410 #define SPI_IER_OVRIE_Pos           (6U)
17411 #define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */
17412 #define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */
17413 #define SPI_IER_CRCEIE_Pos          (7U)
17414 #define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */
17415 #define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */
17416 #define SPI_IER_TIFREIE_Pos         (8U)
17417 #define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */
17418 #define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */
17419 #define SPI_IER_MODFIE_Pos          (9U)
17420 #define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */
17421 #define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */
17422 #define SPI_IER_TSERFIE_Pos         (10U)
17423 #define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */
17424 #define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */
17425 
17426 /*******************  Bit definition for SPI_SR register  ********************/
17427 #define SPI_SR_RXP_Pos              (0U)
17428 #define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */
17429 #define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */
17430 #define SPI_SR_TXP_Pos              (1U)
17431 #define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */
17432 #define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */
17433 #define SPI_SR_DXP_Pos              (2U)
17434 #define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */
17435 #define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */
17436 #define SPI_SR_EOT_Pos              (3U)
17437 #define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */
17438 #define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */
17439 #define SPI_SR_TXTF_Pos             (4U)
17440 #define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */
17441 #define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */
17442 #define SPI_SR_UDR_Pos              (5U)
17443 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */
17444 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */
17445 #define SPI_SR_OVR_Pos              (6U)
17446 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
17447 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */
17448 #define SPI_SR_CRCE_Pos             (7U)
17449 #define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */
17450 #define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */
17451 #define SPI_SR_TIFRE_Pos            (8U)
17452 #define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */
17453 #define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */
17454 #define SPI_SR_MODF_Pos             (9U)
17455 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */
17456 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */
17457 #define SPI_SR_TSERF_Pos            (10U)
17458 #define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */
17459 #define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */
17460 #define SPI_SR_SUSP_Pos             (11U)
17461 #define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */
17462 #define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */
17463 #define SPI_SR_TXC_Pos              (12U)
17464 #define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */
17465 #define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */
17466 #define SPI_SR_RXPLVL_Pos           (13U)
17467 #define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */
17468 #define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */
17469 #define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */
17470 #define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */
17471 #define SPI_SR_RXWNE_Pos            (15U)
17472 #define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */
17473 #define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */
17474 #define SPI_SR_CTSIZE_Pos           (16U)
17475 #define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */
17476 #define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */
17477 
17478 /*******************  Bit definition for SPI_IFCR register  ********************/
17479 #define SPI_IFCR_EOTC_Pos           (3U)
17480 #define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */
17481 #define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */
17482 #define SPI_IFCR_TXTFC_Pos          (4U)
17483 #define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */
17484 #define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */
17485 #define SPI_IFCR_UDRC_Pos           (5U)
17486 #define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */
17487 #define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */
17488 #define SPI_IFCR_OVRC_Pos           (6U)
17489 #define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */
17490 #define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */
17491 #define SPI_IFCR_CRCEC_Pos          (7U)
17492 #define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */
17493 #define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */
17494 #define SPI_IFCR_TIFREC_Pos         (8U)
17495 #define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */
17496 #define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */
17497 #define SPI_IFCR_MODFC_Pos          (9U)
17498 #define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */
17499 #define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */
17500 #define SPI_IFCR_TSERFC_Pos         (10U)
17501 #define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */
17502 #define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */
17503 #define SPI_IFCR_SUSPC_Pos          (11U)
17504 #define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */
17505 #define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */
17506 
17507 /*******************  Bit definition for SPI_TXDR register  ********************/
17508 #define SPI_TXDR_TXDR_Pos           (0U)
17509 #define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */
17510 #define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */
17511 
17512 /*******************  Bit definition for SPI_RXDR register  ********************/
17513 #define SPI_RXDR_RXDR_Pos           (0U)
17514 #define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */
17515 #define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */
17516 
17517 /*******************  Bit definition for SPI_CRCPOLY register  ********************/
17518 #define SPI_CRCPOLY_CRCPOLY_Pos     (0U)
17519 #define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */
17520 #define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */
17521 
17522 /*******************  Bit definition for SPI_TXCRC register  ********************/
17523 #define SPI_TXCRC_TXCRC_Pos         (0U)
17524 #define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */
17525 #define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */
17526 
17527 /*******************  Bit definition for SPI_RXCRC register  ********************/
17528 #define SPI_RXCRC_RXCRC_Pos         (0U)
17529 #define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */
17530 #define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */
17531 
17532 /*******************  Bit definition for SPI_UDRDR register  ********************/
17533 #define SPI_UDRDR_UDRDR_Pos         (0U)
17534 #define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */
17535 #define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */
17536 
17537 /******************  Bit definition for SPI_I2SCFGR register  *****************/
17538 #define SPI_I2SCFGR_I2SMOD_Pos      (0U)
17539 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
17540 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
17541 #define SPI_I2SCFGR_I2SCFG_Pos      (1U)
17542 #define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
17543 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
17544 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
17545 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
17546 #define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
17547 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
17548 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
17549 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
17550 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
17551 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
17552 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
17553 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
17554 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
17555 #define SPI_I2SCFGR_DATLEN_Pos      (8U)
17556 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
17557 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
17558 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
17559 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
17560 #define SPI_I2SCFGR_CHLEN_Pos       (10U)
17561 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
17562 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
17563 #define SPI_I2SCFGR_CKPOL_Pos       (11U)
17564 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
17565 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
17566 #define SPI_I2SCFGR_FIXCH_Pos       (12U)
17567 #define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
17568 #define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
17569 #define SPI_I2SCFGR_WSINV_Pos       (13U)
17570 #define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
17571 #define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
17572 #define SPI_I2SCFGR_DATFMT_Pos      (14U)
17573 #define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
17574 #define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
17575 #define SPI_I2SCFGR_I2SDIV_Pos      (16U)
17576 #define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
17577 #define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
17578 #define SPI_I2SCFGR_ODD_Pos         (24U)
17579 #define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
17580 #define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
17581 #define SPI_I2SCFGR_MCKOE_Pos       (25U)
17582 #define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
17583 #define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
17584 
17585 
17586 
17587 /******************************************************************************/
17588 /*                                                                            */
17589 /*                                 SYSCFG                                     */
17590 /*                                                                            */
17591 /******************************************************************************/
17592 
17593 /******************  Bit definition for SYSCFG_PMCR register  ******************/
17594 #define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)
17595 #define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */
17596 #define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */
17597 #define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)
17598 #define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */
17599 #define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */
17600 #define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)
17601 #define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */
17602 #define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */
17603 #define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)
17604 #define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */
17605 #define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */
17606 #define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)
17607 #define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
17608 #define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */
17609 #define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)
17610 #define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
17611 #define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */
17612 #define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)
17613 #define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
17614 #define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */
17615 #define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)
17616 #define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
17617 #define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */
17618 #define SYSCFG_PMCR_PA0SO_Pos           (24U)
17619 #define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */
17620 #define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */
17621 #define SYSCFG_PMCR_PA1SO_Pos           (25U)
17622 #define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */
17623 #define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */
17624 #define SYSCFG_PMCR_PC2SO_Pos           (26U)
17625 #define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */
17626 #define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */
17627 #define SYSCFG_PMCR_PC3SO_Pos           (27U)
17628 #define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */
17629 #define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */
17630 
17631 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
17632 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
17633 #define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
17634 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
17635 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
17636 #define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
17637 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
17638 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
17639 #define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
17640 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
17641 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
17642 #define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
17643 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
17644 /**
17645   * @brief   EXTI0 configuration
17646   */
17647 #define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
17648 #define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
17649 #define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
17650 #define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
17651 #define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
17652 #define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
17653 #define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
17654 #define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
17655 #define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
17656 #define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
17657 #define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
17658 
17659 /**
17660   * @brief   EXTI1 configuration
17661   */
17662 #define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
17663 #define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
17664 #define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
17665 #define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
17666 #define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
17667 #define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
17668 #define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
17669 #define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
17670 #define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
17671 #define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
17672 #define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
17673 /**
17674   * @brief   EXTI2 configuration
17675   */
17676 #define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
17677 #define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
17678 #define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
17679 #define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
17680 #define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
17681 #define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
17682 #define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
17683 #define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
17684 #define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
17685 #define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
17686 #define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
17687 
17688 /**
17689   * @brief   EXTI3 configuration
17690   */
17691 #define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
17692 #define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
17693 #define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
17694 #define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
17695 #define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
17696 #define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
17697 #define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
17698 #define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
17699 #define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
17700 #define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
17701 #define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
17702 
17703 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
17704 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
17705 #define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
17706 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
17707 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
17708 #define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
17709 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
17710 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
17711 #define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
17712 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
17713 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
17714 #define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
17715 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
17716 /**
17717   * @brief   EXTI4 configuration
17718   */
17719 #define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
17720 #define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
17721 #define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
17722 #define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
17723 #define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
17724 #define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
17725 #define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
17726 #define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
17727 #define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
17728 #define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
17729 #define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
17730 /**
17731   * @brief   EXTI5 configuration
17732   */
17733 #define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
17734 #define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
17735 #define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
17736 #define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
17737 #define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
17738 #define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
17739 #define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
17740 #define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
17741 #define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
17742 #define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
17743 #define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
17744 /**
17745   * @brief   EXTI6 configuration
17746   */
17747 #define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
17748 #define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
17749 #define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
17750 #define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
17751 #define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
17752 #define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
17753 #define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
17754 #define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
17755 #define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
17756 #define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
17757 #define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
17758 
17759 /**
17760   * @brief   EXTI7 configuration
17761   */
17762 #define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
17763 #define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
17764 #define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
17765 #define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
17766 #define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
17767 #define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
17768 #define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
17769 #define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
17770 #define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
17771 #define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
17772 #define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
17773 
17774 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
17775 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
17776 #define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
17777 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
17778 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
17779 #define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
17780 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
17781 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
17782 #define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
17783 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
17784 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
17785 #define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
17786 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
17787 
17788 /**
17789   * @brief   EXTI8 configuration
17790   */
17791 #define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
17792 #define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
17793 #define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
17794 #define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
17795 #define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
17796 #define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
17797 #define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
17798 #define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
17799 #define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
17800 #define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
17801 #define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
17802 
17803 /**
17804   * @brief   EXTI9 configuration
17805   */
17806 #define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
17807 #define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
17808 #define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
17809 #define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
17810 #define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
17811 #define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
17812 #define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
17813 #define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
17814 #define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
17815 #define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
17816 #define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
17817 
17818 /**
17819   * @brief   EXTI10 configuration
17820   */
17821 #define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
17822 #define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
17823 #define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
17824 #define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
17825 #define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
17826 #define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
17827 #define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
17828 #define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
17829 #define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
17830 #define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
17831 #define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
17832 
17833 /**
17834   * @brief   EXTI11 configuration
17835   */
17836 #define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
17837 #define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
17838 #define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
17839 #define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
17840 #define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
17841 #define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
17842 #define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
17843 #define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
17844 #define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
17845 #define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
17846 #define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
17847 
17848 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
17849 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
17850 #define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */
17851 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
17852 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
17853 #define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */
17854 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
17855 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
17856 #define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */
17857 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
17858 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
17859 #define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */
17860 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
17861 /**
17862   * @brief   EXTI12 configuration
17863   */
17864 #define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
17865 #define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
17866 #define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
17867 #define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
17868 #define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
17869 #define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
17870 #define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
17871 #define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
17872 #define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
17873 #define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
17874 #define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
17875 /**
17876   * @brief   EXTI13 configuration
17877   */
17878 #define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
17879 #define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
17880 #define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
17881 #define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
17882 #define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
17883 #define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
17884 #define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
17885 #define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
17886 #define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
17887 #define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
17888 #define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
17889 /**
17890   * @brief   EXTI14 configuration
17891   */
17892 #define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
17893 #define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
17894 #define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
17895 #define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
17896 #define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
17897 #define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
17898 #define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
17899 #define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
17900 #define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
17901 #define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
17902 #define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
17903 /**
17904   * @brief   EXTI15 configuration
17905   */
17906 #define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
17907 #define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
17908 #define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
17909 #define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
17910 #define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
17911 #define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
17912 #define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
17913 #define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
17914 #define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
17915 #define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
17916 #define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
17917 
17918 /******************  Bit definition for SYSCFG_CFGR register  ******************/
17919 #define SYSCFG_CFGR_PVDL_Pos            (2U)
17920 #define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */
17921 #define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */
17922 #define SYSCFG_CFGR_FLASHL_Pos          (3U)
17923 #define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */
17924 #define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */
17925 #define SYSCFG_CFGR_CM7L_Pos            (6U)
17926 #define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */
17927 #define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
17928 #define SYSCFG_CFGR_DTCML_Pos           (13U)
17929 #define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */
17930 #define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */
17931 #define SYSCFG_CFGR_ITCML_Pos           (14U)
17932 #define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */
17933 #define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */
17934 /******************  Bit definition for SYSCFG_CCCSR register  ******************/
17935 #define SYSCFG_CCCSR_EN_Pos             (0U)
17936 #define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */
17937 #define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */
17938 #define SYSCFG_CCCSR_CS_Pos             (1U)
17939 #define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */
17940 #define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */
17941 #define SYSCFG_CCCSR_CS_MMC_Pos         (3U)
17942 #define SYSCFG_CCCSR_CS_MMC_Msk         (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos)         /*!< 0x00000004 */
17943 #define SYSCFG_CCCSR_CS_MMC             SYSCFG_CCCSR_CS_MMC_Msk                    /*!< I/O compensation cell code selection */
17944 #define SYSCFG_CCCSR_READY_Pos          (8U)
17945 #define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */
17946 #define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */
17947 #define SYSCFG_CCCSR_HSLV0_Pos           (16U)
17948 #define SYSCFG_CCCSR_HSLV0_Msk           (0x1UL << SYSCFG_CCCSR_HSLV0_Pos)       /*!< 0x00010000 */
17949 #define SYSCFG_CCCSR_HSLV0               SYSCFG_CCCSR_HSLV0_Msk                  /*!< High-speed at low-voltage */
17950 #define SYSCFG_CCCSR_HSLV1_Pos           (17U)
17951 #define SYSCFG_CCCSR_HSLV1_Msk           (0x1UL << SYSCFG_CCCSR_HSLV1_Pos)       /*!< 0x00020000 */
17952 #define SYSCFG_CCCSR_HSLV1               SYSCFG_CCCSR_HSLV1_Msk                  /*!< High-speed at low-voltage */
17953 #define SYSCFG_CCCSR_HSLV2_Pos           (18U)
17954 #define SYSCFG_CCCSR_HSLV2_Msk           (0x1UL << SYSCFG_CCCSR_HSLV2_Pos)       /*!< 0x00040000 */
17955 #define SYSCFG_CCCSR_HSLV2               SYSCFG_CCCSR_HSLV2_Msk                  /*!< High-speed at low-voltage */
17956 #define SYSCFG_CCCSR_HSLV3_Pos           (19U)
17957 #define SYSCFG_CCCSR_HSLV3_Msk           (0x1UL << SYSCFG_CCCSR_HSLV3_Pos)       /*!< 0x00080000 */
17958 #define SYSCFG_CCCSR_HSLV3               SYSCFG_CCCSR_HSLV3_Msk                  /*!< High-speed at low-voltage */
17959 /******************  Bit definition for SYSCFG_CCVR register  *******************/
17960 #define SYSCFG_CCVR_NCV_Pos             (0U)
17961 #define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */
17962 #define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */
17963 #define SYSCFG_CCVR_PCV_Pos             (4U)
17964 #define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */
17965 #define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */
17966 
17967 /******************  Bit definition for SYSCFG_CCCR register  *******************/
17968 #define SYSCFG_CCCR_NCC_Pos             (0U)
17969 #define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */
17970 #define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */
17971 #define SYSCFG_CCCR_PCC_Pos             (4U)
17972 #define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */
17973 #define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */
17974 #define SYSCFG_CCCR_NCC_MMC_Pos         (8U)
17975 #define SYSCFG_CCCR_NCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos)     /*!< 0x00000F00 */
17976 #define SYSCFG_CCCR_NCC_MMC             SYSCFG_CCCR_NCC_MMC_Msk                /*!< NMOS compensation code */
17977 #define SYSCFG_CCCR_PCC_MMC_Pos         (12U)
17978 #define SYSCFG_CCCR_PCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos)     /*!< 0x0000F000 */
17979 #define SYSCFG_CCCR_PCC_MMC             SYSCFG_CCCR_PCC_MMC_Msk                /*!< PMOS compensation code */
17980 /******************************************************************************/
17981 /*                                                                            */
17982 /*                    Digital Temperature Sensor (DTS)                        */
17983 /*                                                                            */
17984 /******************************************************************************/
17985 
17986 /******************  Bit definition for DTS_CFGR1 register  ******************/
17987 #define DTS_CFGR1_TS1_EN_Pos               (0U)
17988 #define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
17989 #define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */
17990 #define DTS_CFGR1_TS1_START_Pos            (4U)
17991 #define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
17992 #define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */
17993 #define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)
17994 #define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
17995 #define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */
17996 #define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
17997 #define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
17998 #define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
17999 #define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
18000 #define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)
18001 #define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
18002 #define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */
18003 #define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
18004 #define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
18005 #define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
18006 #define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
18007 #define DTS_CFGR1_REFCLK_SEL_Pos           (20U)
18008 #define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
18009 #define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */
18010 #define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)
18011 #define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
18012 #define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */
18013 #define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)
18014 #define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
18015 #define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
18016 
18017 /******************  Bit definition for DTS_T0VALR1 register  ******************/
18018 #define DTS_T0VALR1_TS1_FMT0_Pos           (0U)
18019 #define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
18020 #define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */
18021 #define DTS_T0VALR1_TS1_T0_Pos             (16U)
18022 #define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
18023 #define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */
18024 
18025 /******************  Bit definition for DTS_RAMPVALR register  ******************/
18026 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)
18027 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
18028 #define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */
18029 
18030 /******************  Bit definition for DTS_ITR1 register      ******************/
18031 #define DTS_ITR1_TS1_LITTHD_Pos            (0U)
18032 #define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
18033 #define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */
18034 #define DTS_ITR1_TS1_HITTHD_Pos            (16U)
18035 #define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
18036 #define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */
18037 
18038 /******************  Bit definition for DTS_DR register        ******************/
18039 #define DTS_DR_TS1_MFREQ_Pos               (0U)
18040 #define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
18041 #define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */
18042 
18043 /******************  Bit definition for DTS_SR register        ******************/
18044 #define DTS_SR_TS1_ITEF_Pos                (0U)
18045 #define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
18046 #define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */
18047 #define DTS_SR_TS1_ITLF_Pos                (1U)
18048 #define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
18049 #define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */
18050 #define DTS_SR_TS1_ITHF_Pos                (2U)
18051 #define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
18052 #define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */
18053 #define DTS_SR_TS1_AITEF_Pos               (4U)
18054 #define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
18055 #define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */
18056 #define DTS_SR_TS1_AITLF_Pos               (5U)
18057 #define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
18058 #define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */
18059 #define DTS_SR_TS1_AITHF_Pos               (6U)
18060 #define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
18061 #define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */
18062 #define DTS_SR_TS1_RDY_Pos                 (15U)
18063 #define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
18064 #define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */
18065 
18066 /******************  Bit definition for DTS_ITENR register      ******************/
18067 #define DTS_ITENR_TS1_ITEEN_Pos            (0U)
18068 #define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
18069 #define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */
18070 #define DTS_ITENR_TS1_ITLEN_Pos            (1U)
18071 #define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
18072 #define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */
18073 #define DTS_ITENR_TS1_ITHEN_Pos            (2U)
18074 #define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
18075 #define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */
18076 #define DTS_ITENR_TS1_AITEEN_Pos           (4U)
18077 #define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
18078 #define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */
18079 #define DTS_ITENR_TS1_AITLEN_Pos           (5U)
18080 #define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
18081 #define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */
18082 #define DTS_ITENR_TS1_AITHEN_Pos           (6U)
18083 #define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
18084 #define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */
18085 
18086 /******************  Bit definition for DTS_ICIFR register      ******************/
18087 #define DTS_ICIFR_TS1_CITEF_Pos            (0U)
18088 #define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
18089 #define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */
18090 #define DTS_ICIFR_TS1_CITLF_Pos            (1U)
18091 #define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
18092 #define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */
18093 #define DTS_ICIFR_TS1_CITHF_Pos            (2U)
18094 #define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
18095 #define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */
18096 #define DTS_ICIFR_TS1_CAITEF_Pos           (4U)
18097 #define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
18098 #define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */
18099 #define DTS_ICIFR_TS1_CAITLF_Pos           (5U)
18100 #define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
18101 #define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */
18102 #define DTS_ICIFR_TS1_CAITHF_Pos           (6U)
18103 #define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
18104 #define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */
18105 
18106 
18107 /******************************************************************************/
18108 /*                                                                            */
18109 /*                                    TIM                                     */
18110 /*                                                                            */
18111 /******************************************************************************/
18112 #define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */
18113 
18114 /*******************  Bit definition for TIM_CR1 register  ********************/
18115 #define TIM_CR1_CEN_Pos           (0U)
18116 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
18117 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
18118 #define TIM_CR1_UDIS_Pos          (1U)
18119 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
18120 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
18121 #define TIM_CR1_URS_Pos           (2U)
18122 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
18123 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
18124 #define TIM_CR1_OPM_Pos           (3U)
18125 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
18126 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
18127 #define TIM_CR1_DIR_Pos           (4U)
18128 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
18129 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
18130 
18131 #define TIM_CR1_CMS_Pos           (5U)
18132 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
18133 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
18134 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
18135 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
18136 
18137 #define TIM_CR1_ARPE_Pos          (7U)
18138 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
18139 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
18140 
18141 #define TIM_CR1_CKD_Pos           (8U)
18142 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
18143 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
18144 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
18145 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
18146 
18147 #define TIM_CR1_UIFREMAP_Pos      (11U)
18148 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
18149 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
18150 
18151 /*******************  Bit definition for TIM_CR2 register  ********************/
18152 #define TIM_CR2_CCPC_Pos          (0U)
18153 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
18154 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
18155 #define TIM_CR2_CCUS_Pos          (2U)
18156 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
18157 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
18158 #define TIM_CR2_CCDS_Pos          (3U)
18159 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
18160 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
18161 
18162 #define TIM_CR2_MMS_Pos           (4U)
18163 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
18164 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
18165 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
18166 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
18167 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
18168 
18169 #define TIM_CR2_TI1S_Pos          (7U)
18170 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
18171 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
18172 #define TIM_CR2_OIS1_Pos          (8U)
18173 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
18174 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
18175 #define TIM_CR2_OIS1N_Pos         (9U)
18176 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
18177 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
18178 #define TIM_CR2_OIS2_Pos          (10U)
18179 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
18180 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
18181 #define TIM_CR2_OIS2N_Pos         (11U)
18182 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
18183 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
18184 #define TIM_CR2_OIS3_Pos          (12U)
18185 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
18186 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
18187 #define TIM_CR2_OIS3N_Pos         (13U)
18188 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
18189 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
18190 #define TIM_CR2_OIS4_Pos          (14U)
18191 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
18192 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
18193 #define TIM_CR2_OIS5_Pos          (16U)
18194 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
18195 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
18196 #define TIM_CR2_OIS6_Pos          (18U)
18197 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
18198 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
18199 
18200 #define TIM_CR2_MMS2_Pos          (20U)
18201 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
18202 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
18203 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
18204 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
18205 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
18206 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
18207 
18208 /*******************  Bit definition for TIM_SMCR register  *******************/
18209 #define TIM_SMCR_SMS_Pos          (0U)
18210 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
18211 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
18212 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
18213 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
18214 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
18215 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
18216 
18217 #define TIM_SMCR_TS_Pos           (4U)
18218 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
18219 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */
18220 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
18221 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
18222 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
18223 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
18224 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
18225 
18226 #define TIM_SMCR_MSM_Pos          (7U)
18227 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
18228 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
18229 
18230 #define TIM_SMCR_ETF_Pos          (8U)
18231 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
18232 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
18233 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
18234 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
18235 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
18236 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
18237 
18238 #define TIM_SMCR_ETPS_Pos         (12U)
18239 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
18240 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
18241 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
18242 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
18243 
18244 #define TIM_SMCR_ECE_Pos          (14U)
18245 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
18246 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
18247 #define TIM_SMCR_ETP_Pos          (15U)
18248 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
18249 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
18250 
18251 /*******************  Bit definition for TIM_DIER register  *******************/
18252 #define TIM_DIER_UIE_Pos          (0U)
18253 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
18254 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
18255 #define TIM_DIER_CC1IE_Pos        (1U)
18256 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
18257 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
18258 #define TIM_DIER_CC2IE_Pos        (2U)
18259 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
18260 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
18261 #define TIM_DIER_CC3IE_Pos        (3U)
18262 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
18263 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
18264 #define TIM_DIER_CC4IE_Pos        (4U)
18265 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
18266 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
18267 #define TIM_DIER_COMIE_Pos        (5U)
18268 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
18269 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
18270 #define TIM_DIER_TIE_Pos          (6U)
18271 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
18272 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
18273 #define TIM_DIER_BIE_Pos          (7U)
18274 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
18275 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
18276 #define TIM_DIER_UDE_Pos          (8U)
18277 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
18278 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
18279 #define TIM_DIER_CC1DE_Pos        (9U)
18280 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
18281 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
18282 #define TIM_DIER_CC2DE_Pos        (10U)
18283 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
18284 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
18285 #define TIM_DIER_CC3DE_Pos        (11U)
18286 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
18287 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
18288 #define TIM_DIER_CC4DE_Pos        (12U)
18289 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
18290 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
18291 #define TIM_DIER_COMDE_Pos        (13U)
18292 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
18293 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
18294 #define TIM_DIER_TDE_Pos          (14U)
18295 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
18296 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
18297 
18298 /********************  Bit definition for TIM_SR register  ********************/
18299 #define TIM_SR_UIF_Pos            (0U)
18300 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
18301 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
18302 #define TIM_SR_CC1IF_Pos          (1U)
18303 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
18304 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
18305 #define TIM_SR_CC2IF_Pos          (2U)
18306 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
18307 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
18308 #define TIM_SR_CC3IF_Pos          (3U)
18309 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
18310 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
18311 #define TIM_SR_CC4IF_Pos          (4U)
18312 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
18313 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
18314 #define TIM_SR_COMIF_Pos          (5U)
18315 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
18316 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
18317 #define TIM_SR_TIF_Pos            (6U)
18318 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
18319 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
18320 #define TIM_SR_BIF_Pos            (7U)
18321 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
18322 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
18323 #define TIM_SR_B2IF_Pos           (8U)
18324 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
18325 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
18326 #define TIM_SR_CC1OF_Pos          (9U)
18327 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
18328 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
18329 #define TIM_SR_CC2OF_Pos          (10U)
18330 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
18331 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
18332 #define TIM_SR_CC3OF_Pos          (11U)
18333 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
18334 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
18335 #define TIM_SR_CC4OF_Pos          (12U)
18336 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
18337 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
18338 #define TIM_SR_CC5IF_Pos          (16U)
18339 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
18340 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
18341 #define TIM_SR_CC6IF_Pos          (17U)
18342 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
18343 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
18344 #define TIM_SR_SBIF_Pos           (13U)
18345 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
18346 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */
18347 
18348 /*******************  Bit definition for TIM_EGR register  ********************/
18349 #define TIM_EGR_UG_Pos            (0U)
18350 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
18351 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
18352 #define TIM_EGR_CC1G_Pos          (1U)
18353 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
18354 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
18355 #define TIM_EGR_CC2G_Pos          (2U)
18356 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
18357 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
18358 #define TIM_EGR_CC3G_Pos          (3U)
18359 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
18360 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
18361 #define TIM_EGR_CC4G_Pos          (4U)
18362 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
18363 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
18364 #define TIM_EGR_COMG_Pos          (5U)
18365 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
18366 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
18367 #define TIM_EGR_TG_Pos            (6U)
18368 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
18369 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
18370 #define TIM_EGR_BG_Pos            (7U)
18371 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
18372 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
18373 #define TIM_EGR_B2G_Pos           (8U)
18374 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
18375 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
18376 
18377 
18378 /******************  Bit definition for TIM_CCMR1 register  *******************/
18379 #define TIM_CCMR1_CC1S_Pos        (0U)
18380 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
18381 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
18382 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
18383 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
18384 
18385 #define TIM_CCMR1_OC1FE_Pos       (2U)
18386 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
18387 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
18388 #define TIM_CCMR1_OC1PE_Pos       (3U)
18389 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
18390 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
18391 
18392 #define TIM_CCMR1_OC1M_Pos        (4U)
18393 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
18394 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
18395 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
18396 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
18397 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
18398 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
18399 
18400 #define TIM_CCMR1_OC1CE_Pos       (7U)
18401 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
18402 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
18403 
18404 #define TIM_CCMR1_CC2S_Pos        (8U)
18405 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
18406 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
18407 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
18408 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
18409 
18410 #define TIM_CCMR1_OC2FE_Pos       (10U)
18411 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
18412 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
18413 #define TIM_CCMR1_OC2PE_Pos       (11U)
18414 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
18415 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
18416 
18417 #define TIM_CCMR1_OC2M_Pos        (12U)
18418 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
18419 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
18420 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
18421 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
18422 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
18423 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
18424 
18425 #define TIM_CCMR1_OC2CE_Pos       (15U)
18426 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
18427 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
18428 
18429 /*----------------------------------------------------------------------------*/
18430 
18431 #define TIM_CCMR1_IC1PSC_Pos      (2U)
18432 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
18433 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
18434 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
18435 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
18436 
18437 #define TIM_CCMR1_IC1F_Pos        (4U)
18438 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
18439 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
18440 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
18441 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
18442 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
18443 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
18444 
18445 #define TIM_CCMR1_IC2PSC_Pos      (10U)
18446 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
18447 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
18448 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
18449 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
18450 
18451 #define TIM_CCMR1_IC2F_Pos        (12U)
18452 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
18453 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
18454 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
18455 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
18456 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
18457 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
18458 
18459 /******************  Bit definition for TIM_CCMR2 register  *******************/
18460 #define TIM_CCMR2_CC3S_Pos        (0U)
18461 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
18462 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
18463 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
18464 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
18465 
18466 #define TIM_CCMR2_OC3FE_Pos       (2U)
18467 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
18468 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
18469 #define TIM_CCMR2_OC3PE_Pos       (3U)
18470 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
18471 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
18472 
18473 #define TIM_CCMR2_OC3M_Pos        (4U)
18474 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
18475 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
18476 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
18477 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
18478 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
18479 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
18480 
18481 #define TIM_CCMR2_OC3CE_Pos       (7U)
18482 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
18483 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
18484 
18485 #define TIM_CCMR2_CC4S_Pos        (8U)
18486 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
18487 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
18488 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
18489 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
18490 
18491 #define TIM_CCMR2_OC4FE_Pos       (10U)
18492 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
18493 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
18494 #define TIM_CCMR2_OC4PE_Pos       (11U)
18495 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
18496 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
18497 
18498 #define TIM_CCMR2_OC4M_Pos        (12U)
18499 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
18500 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
18501 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
18502 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
18503 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
18504 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
18505 
18506 #define TIM_CCMR2_OC4CE_Pos       (15U)
18507 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
18508 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
18509 
18510 /*----------------------------------------------------------------------------*/
18511 
18512 #define TIM_CCMR2_IC3PSC_Pos      (2U)
18513 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
18514 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
18515 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
18516 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
18517 
18518 #define TIM_CCMR2_IC3F_Pos        (4U)
18519 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
18520 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
18521 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
18522 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
18523 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
18524 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
18525 
18526 #define TIM_CCMR2_IC4PSC_Pos      (10U)
18527 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
18528 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
18529 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
18530 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
18531 
18532 #define TIM_CCMR2_IC4F_Pos        (12U)
18533 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
18534 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
18535 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
18536 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
18537 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
18538 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
18539 
18540 /*******************  Bit definition for TIM_CCER register  *******************/
18541 #define TIM_CCER_CC1E_Pos         (0U)
18542 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
18543 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
18544 #define TIM_CCER_CC1P_Pos         (1U)
18545 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
18546 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
18547 #define TIM_CCER_CC1NE_Pos        (2U)
18548 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
18549 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
18550 #define TIM_CCER_CC1NP_Pos        (3U)
18551 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
18552 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
18553 #define TIM_CCER_CC2E_Pos         (4U)
18554 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
18555 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
18556 #define TIM_CCER_CC2P_Pos         (5U)
18557 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
18558 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
18559 #define TIM_CCER_CC2NE_Pos        (6U)
18560 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
18561 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
18562 #define TIM_CCER_CC2NP_Pos        (7U)
18563 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
18564 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
18565 #define TIM_CCER_CC3E_Pos         (8U)
18566 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
18567 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
18568 #define TIM_CCER_CC3P_Pos         (9U)
18569 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
18570 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
18571 #define TIM_CCER_CC3NE_Pos        (10U)
18572 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
18573 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
18574 #define TIM_CCER_CC3NP_Pos        (11U)
18575 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
18576 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
18577 #define TIM_CCER_CC4E_Pos         (12U)
18578 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
18579 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
18580 #define TIM_CCER_CC4P_Pos         (13U)
18581 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
18582 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
18583 #define TIM_CCER_CC4NP_Pos        (15U)
18584 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
18585 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
18586 #define TIM_CCER_CC5E_Pos         (16U)
18587 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
18588 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
18589 #define TIM_CCER_CC5P_Pos         (17U)
18590 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
18591 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
18592 #define TIM_CCER_CC6E_Pos         (20U)
18593 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
18594 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
18595 #define TIM_CCER_CC6P_Pos         (21U)
18596 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
18597 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
18598 /*******************  Bit definition for TIM_CNT register  ********************/
18599 #define TIM_CNT_CNT_Pos           (0U)
18600 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
18601 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
18602 #define TIM_CNT_UIFCPY_Pos        (31U)
18603 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
18604 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
18605 /*******************  Bit definition for TIM_PSC register  ********************/
18606 #define TIM_PSC_PSC_Pos           (0U)
18607 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
18608 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
18609 
18610 /*******************  Bit definition for TIM_ARR register  ********************/
18611 #define TIM_ARR_ARR_Pos           (0U)
18612 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
18613 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
18614 
18615 /*******************  Bit definition for TIM_RCR register  ********************/
18616 #define TIM_RCR_REP_Pos           (0U)
18617 #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */
18618 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
18619 
18620 /*******************  Bit definition for TIM_CCR1 register  *******************/
18621 #define TIM_CCR1_CCR1_Pos         (0U)
18622 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
18623 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
18624 
18625 /*******************  Bit definition for TIM_CCR2 register  *******************/
18626 #define TIM_CCR2_CCR2_Pos         (0U)
18627 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
18628 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
18629 
18630 /*******************  Bit definition for TIM_CCR3 register  *******************/
18631 #define TIM_CCR3_CCR3_Pos         (0U)
18632 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
18633 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
18634 
18635 /*******************  Bit definition for TIM_CCR4 register  *******************/
18636 #define TIM_CCR4_CCR4_Pos         (0U)
18637 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
18638 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
18639 
18640 /*******************  Bit definition for TIM_CCR5 register  *******************/
18641 #define TIM_CCR5_CCR5_Pos         (0U)
18642 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
18643 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
18644 #define TIM_CCR5_GC5C1_Pos        (29U)
18645 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
18646 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
18647 #define TIM_CCR5_GC5C2_Pos        (30U)
18648 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
18649 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
18650 #define TIM_CCR5_GC5C3_Pos        (31U)
18651 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
18652 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
18653 
18654 /*******************  Bit definition for TIM_CCR6 register  *******************/
18655 #define TIM_CCR6_CCR6_Pos         (0U)
18656 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
18657 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
18658 
18659 /*******************  Bit definition for TIM_BDTR register  *******************/
18660 #define TIM_BDTR_DTG_Pos          (0U)
18661 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
18662 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
18663 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
18664 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
18665 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
18666 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
18667 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
18668 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
18669 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
18670 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
18671 
18672 #define TIM_BDTR_LOCK_Pos         (8U)
18673 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
18674 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
18675 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
18676 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
18677 
18678 #define TIM_BDTR_OSSI_Pos         (10U)
18679 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
18680 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
18681 #define TIM_BDTR_OSSR_Pos         (11U)
18682 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
18683 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
18684 #define TIM_BDTR_BKE_Pos          (12U)
18685 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
18686 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
18687 #define TIM_BDTR_BKP_Pos          (13U)
18688 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
18689 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
18690 #define TIM_BDTR_AOE_Pos          (14U)
18691 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
18692 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
18693 #define TIM_BDTR_MOE_Pos          (15U)
18694 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
18695 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
18696 
18697 #define TIM_BDTR_BKF_Pos          (16U)
18698 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
18699 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
18700 #define TIM_BDTR_BK2F_Pos         (20U)
18701 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
18702 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
18703 
18704 #define TIM_BDTR_BK2E_Pos         (24U)
18705 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
18706 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
18707 #define TIM_BDTR_BK2P_Pos         (25U)
18708 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
18709 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
18710 #define TIM_BDTR_BKDSRM_Pos       (26U)
18711 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
18712 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
18713 #define TIM_BDTR_BK2DSRM_Pos      (27U)
18714 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
18715 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
18716 #define TIM_BDTR_BKBID_Pos        (28U)
18717 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
18718 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
18719 #define TIM_BDTR_BK2BID_Pos       (29U)
18720 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
18721 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
18722 
18723 /*******************  Bit definition for TIM_DCR register  ********************/
18724 #define TIM_DCR_DBA_Pos           (0U)
18725 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
18726 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
18727 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
18728 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
18729 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
18730 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
18731 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
18732 
18733 #define TIM_DCR_DBL_Pos           (8U)
18734 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
18735 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
18736 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
18737 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
18738 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
18739 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
18740 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
18741 
18742 /*******************  Bit definition for TIM_DMAR register  *******************/
18743 #define TIM_DMAR_DMAB_Pos         (0U)
18744 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
18745 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
18746 
18747 /******************  Bit definition for TIM_CCMR3 register  *******************/
18748 #define TIM_CCMR3_OC5FE_Pos       (2U)
18749 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
18750 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
18751 #define TIM_CCMR3_OC5PE_Pos       (3U)
18752 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
18753 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
18754 
18755 #define TIM_CCMR3_OC5M_Pos        (4U)
18756 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
18757 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
18758 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
18759 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
18760 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
18761 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
18762 
18763 #define TIM_CCMR3_OC5CE_Pos       (7U)
18764 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
18765 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
18766 
18767 #define TIM_CCMR3_OC6FE_Pos       (10U)
18768 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
18769 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
18770 #define TIM_CCMR3_OC6PE_Pos       (11U)
18771 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
18772 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
18773 
18774 #define TIM_CCMR3_OC6M_Pos        (12U)
18775 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
18776 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
18777 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
18778 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
18779 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
18780 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
18781 
18782 #define TIM_CCMR3_OC6CE_Pos       (15U)
18783 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
18784 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
18785 /*******************  Bit definition for TIM1_AF1 register  *********************/
18786 #define TIM1_AF1_BKINE_Pos        (0U)
18787 #define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
18788 #define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
18789 #define TIM1_AF1_BKCMP1E_Pos      (1U)
18790 #define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
18791 #define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
18792 #define TIM1_AF1_BKCMP2E_Pos      (2U)
18793 #define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
18794 #define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */
18795 #define TIM1_AF1_BKDF1BK0E_Pos    (8U)
18796 #define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */
18797 #define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */
18798 #define TIM1_AF1_BKINP_Pos        (9U)
18799 #define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
18800 #define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
18801 #define TIM1_AF1_BKCMP1P_Pos      (10U)
18802 #define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
18803 #define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
18804 #define TIM1_AF1_BKCMP2P_Pos      (11U)
18805 #define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
18806 #define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
18807 
18808 #define TIM1_AF1_ETRSEL_Pos       (14U)
18809 #define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
18810 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
18811 #define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
18812 #define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
18813 #define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
18814 #define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
18815 
18816 /*******************  Bit definition for TIM1_AF2 register  *********************/
18817 #define TIM1_AF2_BK2INE_Pos       (0U)
18818 #define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
18819 #define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
18820 #define TIM1_AF2_BK2CMP1E_Pos     (1U)
18821 #define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
18822 #define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
18823 #define TIM1_AF2_BK2CMP2E_Pos     (2U)
18824 #define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
18825 #define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
18826 #define TIM1_AF2_BK2DFBK1E_Pos    (8U)
18827 #define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */
18828 #define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
18829 #define TIM1_AF2_BK2INP_Pos       (9U)
18830 #define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
18831 #define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
18832 #define TIM1_AF2_BK2CMP1P_Pos     (10U)
18833 #define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
18834 #define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
18835 #define TIM1_AF2_BK2CMP2P_Pos     (11U)
18836 #define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
18837 #define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
18838 
18839 /*******************  Bit definition for TIM_TISEL register  *********************/
18840 #define TIM_TISEL_TI1SEL_Pos      (0U)
18841 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
18842 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
18843 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */
18844 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */
18845 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */
18846 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */
18847 
18848 #define TIM_TISEL_TI2SEL_Pos      (8U)
18849 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
18850 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
18851 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */
18852 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */
18853 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */
18854 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */
18855 
18856 #define TIM_TISEL_TI3SEL_Pos      (16U)
18857 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
18858 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
18859 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */
18860 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */
18861 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */
18862 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */
18863 
18864 #define TIM_TISEL_TI4SEL_Pos      (24U)
18865 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
18866 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
18867 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */
18868 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */
18869 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */
18870 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */
18871 
18872 /*******************  Bit definition for TIM8_AF1 register  *********************/
18873 #define TIM8_AF1_BKINE_Pos        (0U)
18874 #define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */
18875 #define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
18876 #define TIM8_AF1_BKCMP1E_Pos      (1U)
18877 #define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
18878 #define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
18879 #define TIM8_AF1_BKCMP2E_Pos      (2U)
18880 #define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
18881 #define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */
18882 #define TIM8_AF1_BKDFBK2E_Pos     (8U)
18883 #define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */
18884 #define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */
18885 #define TIM8_AF1_BKINP_Pos        (9U)
18886 #define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */
18887 #define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
18888 #define TIM8_AF1_BKCMP1P_Pos      (10U)
18889 #define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
18890 #define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
18891 #define TIM8_AF1_BKCMP2P_Pos      (11U)
18892 #define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
18893 #define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
18894 
18895 #define TIM8_AF1_ETRSEL_Pos       (14U)
18896 #define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
18897 #define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
18898 #define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
18899 #define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
18900 #define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
18901 #define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
18902 /*******************  Bit definition for TIM8_AF2 register  *********************/
18903 #define TIM8_AF2_BK2INE_Pos       (0U)
18904 #define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */
18905 #define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
18906 #define TIM8_AF2_BK2CMP1E_Pos     (1U)
18907 #define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
18908 #define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
18909 #define TIM8_AF2_BK2CMP2E_Pos     (2U)
18910 #define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
18911 #define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
18912 #define TIM8_AF2_BK2DFBK3E_Pos    (8U)
18913 #define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */
18914 #define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
18915 #define TIM8_AF2_BK2INP_Pos       (9U)
18916 #define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */
18917 #define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
18918 #define TIM8_AF2_BK2CMP1P_Pos     (10U)
18919 #define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
18920 #define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
18921 #define TIM8_AF2_BK2CMP2P_Pos     (11U)
18922 #define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
18923 #define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
18924 
18925 /*******************  Bit definition for TIM2_AF1 register  *********************/
18926 #define TIM2_AF1_ETRSEL_Pos      (14U)
18927 #define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
18928 #define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
18929 #define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
18930 #define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
18931 #define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
18932 #define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
18933 
18934 /*******************  Bit definition for TIM3_AF1 register  *********************/
18935 #define TIM3_AF1_ETRSEL_Pos      (14U)
18936 #define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
18937 #define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
18938 #define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
18939 #define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
18940 #define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
18941 #define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
18942 
18943 /*******************  Bit definition for TIM5_AF1 register  *********************/
18944 #define TIM5_AF1_ETRSEL_Pos      (14U)
18945 #define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
18946 #define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
18947 #define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
18948 #define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
18949 #define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
18950 #define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
18951 
18952 /*******************  Bit definition for TIM15_AF1 register  *********************/
18953 #define TIM15_AF1_BKINE_Pos        (0U)
18954 #define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */
18955 #define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
18956 #define TIM15_AF1_BKCMP1E_Pos      (1U)
18957 #define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
18958 #define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
18959 #define TIM15_AF1_BKCMP2E_Pos      (2U)
18960 #define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
18961 #define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
18962 #define TIM15_AF1_BKDF1BK2E_Pos    (8U)
18963 #define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
18964 #define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */
18965 #define TIM15_AF1_BKINP_Pos        (9U)
18966 #define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */
18967 #define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
18968 #define TIM15_AF1_BKCMP1P_Pos      (10U)
18969 #define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
18970 #define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
18971 #define TIM15_AF1_BKCMP2P_Pos      (11U)
18972 #define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
18973 #define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
18974 
18975 /*******************  Bit definition for TIM16_ register  *********************/
18976 #define TIM16_AF1_BKINE_Pos        (0U)
18977 #define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */
18978 #define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
18979 #define TIM16_AF1_BKCMP1E_Pos      (1U)
18980 #define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
18981 #define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
18982 #define TIM16_AF1_BKCMP2E_Pos      (2U)
18983 #define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
18984 #define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
18985 #define TIM16_AF1_BKDF1BK2E_Pos    (8U)
18986 #define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
18987 #define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */
18988 #define TIM16_AF1_BKINP_Pos        (9U)
18989 #define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */
18990 #define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
18991 #define TIM16_AF1_BKCMP1P_Pos      (10U)
18992 #define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
18993 #define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
18994 #define TIM16_AF1_BKCMP2P_Pos      (11U)
18995 #define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
18996 #define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
18997 
18998 /*******************  Bit definition for TIM17_AF1 register  *********************/
18999 #define TIM17_AF1_BKINE_Pos        (0U)
19000 #define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */
19001 #define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
19002 #define TIM17_AF1_BKCMP1E_Pos      (1U)
19003 #define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
19004 #define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
19005 #define TIM17_AF1_BKCMP2E_Pos      (2U)
19006 #define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
19007 #define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
19008 #define TIM17_AF1_BKDF1BK2E_Pos    (8U)
19009 #define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
19010 #define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */
19011 #define TIM17_AF1_BKINP_Pos        (9U)
19012 #define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */
19013 #define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
19014 #define TIM17_AF1_BKCMP1P_Pos      (10U)
19015 #define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
19016 #define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
19017 #define TIM17_AF1_BKCMP2P_Pos      (11U)
19018 #define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
19019 #define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
19020 
19021 /******************************************************************************/
19022 /*                                                                            */
19023 /*                         Low Power Timer (LPTTIM)                           */
19024 /*                                                                            */
19025 /******************************************************************************/
19026 /******************  Bit definition for LPTIM_ISR register  *******************/
19027 #define LPTIM_ISR_CMPM_Pos          (0U)
19028 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
19029 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
19030 #define LPTIM_ISR_ARRM_Pos          (1U)
19031 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
19032 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
19033 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
19034 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
19035 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
19036 #define LPTIM_ISR_CMPOK_Pos         (3U)
19037 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
19038 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
19039 #define LPTIM_ISR_ARROK_Pos         (4U)
19040 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
19041 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
19042 #define LPTIM_ISR_UP_Pos            (5U)
19043 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
19044 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
19045 #define LPTIM_ISR_DOWN_Pos          (6U)
19046 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
19047 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
19048 
19049 /******************  Bit definition for LPTIM_ICR register  *******************/
19050 #define LPTIM_ICR_CMPMCF_Pos        (0U)
19051 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
19052 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
19053 #define LPTIM_ICR_ARRMCF_Pos        (1U)
19054 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
19055 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
19056 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
19057 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
19058 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
19059 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
19060 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
19061 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
19062 #define LPTIM_ICR_ARROKCF_Pos       (4U)
19063 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
19064 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
19065 #define LPTIM_ICR_UPCF_Pos          (5U)
19066 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
19067 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
19068 #define LPTIM_ICR_DOWNCF_Pos        (6U)
19069 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
19070 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
19071 
19072 /******************  Bit definition for LPTIM_IER register ********************/
19073 #define LPTIM_IER_CMPMIE_Pos        (0U)
19074 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
19075 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
19076 #define LPTIM_IER_ARRMIE_Pos        (1U)
19077 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
19078 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
19079 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
19080 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
19081 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
19082 #define LPTIM_IER_CMPOKIE_Pos       (3U)
19083 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
19084 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
19085 #define LPTIM_IER_ARROKIE_Pos       (4U)
19086 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
19087 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
19088 #define LPTIM_IER_UPIE_Pos          (5U)
19089 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
19090 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
19091 #define LPTIM_IER_DOWNIE_Pos        (6U)
19092 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
19093 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
19094 
19095 /******************  Bit definition for LPTIM_CFGR register *******************/
19096 #define LPTIM_CFGR_CKSEL_Pos        (0U)
19097 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
19098 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
19099 
19100 #define LPTIM_CFGR_CKPOL_Pos        (1U)
19101 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
19102 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
19103 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
19104 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
19105 
19106 #define LPTIM_CFGR_CKFLT_Pos        (3U)
19107 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
19108 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
19109 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
19110 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
19111 
19112 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
19113 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
19114 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
19115 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
19116 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
19117 
19118 #define LPTIM_CFGR_PRESC_Pos        (9U)
19119 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
19120 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
19121 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
19122 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
19123 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
19124 
19125 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
19126 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
19127 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
19128 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
19129 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
19130 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
19131 
19132 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
19133 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
19134 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
19135 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
19136 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
19137 
19138 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
19139 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
19140 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
19141 #define LPTIM_CFGR_WAVE_Pos         (20U)
19142 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
19143 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
19144 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
19145 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
19146 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
19147 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
19148 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
19149 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
19150 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
19151 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
19152 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
19153 #define LPTIM_CFGR_ENC_Pos          (24U)
19154 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
19155 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
19156 
19157 /******************  Bit definition for LPTIM_CR register  ********************/
19158 #define LPTIM_CR_ENABLE_Pos         (0U)
19159 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
19160 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
19161 #define LPTIM_CR_SNGSTRT_Pos        (1U)
19162 #define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */
19163 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
19164 #define LPTIM_CR_CNTSTRT_Pos        (2U)
19165 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
19166 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
19167 #define LPTIM_CR_COUNTRST_Pos       (3U)
19168 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
19169 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
19170 #define LPTIM_CR_RSTARE_Pos         (4U)
19171 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
19172 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
19173 
19174 
19175 /******************  Bit definition for LPTIM_CMP register  *******************/
19176 #define LPTIM_CMP_CMP_Pos           (0U)
19177 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
19178 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
19179 
19180 /******************  Bit definition for LPTIM_ARR register  *******************/
19181 #define LPTIM_ARR_ARR_Pos           (0U)
19182 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
19183 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
19184 
19185 /******************  Bit definition for LPTIM_CNT register  *******************/
19186 #define LPTIM_CNT_CNT_Pos           (0U)
19187 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
19188 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
19189 
19190 /******************  Bit definition for LPTIM_CFGR2 register  *****************/
19191 #define LPTIM_CFGR2_IN1SEL_Pos      (0U)
19192 #define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
19193 #define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
19194 #define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
19195 #define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
19196 #define LPTIM_CFGR2_IN2SEL_Pos      (4U)
19197 #define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
19198 #define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
19199 #define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
19200 #define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
19201 
19202 /******************************************************************************/
19203 /*                                                                            */
19204 /*                                    OCTOSPI                                 */
19205 /*                                                                            */
19206 /******************************************************************************/
19207 /*****************  Bit definition for OCTOSPI_CR register  *******************/
19208 #define OCTOSPI_CR_EN_Pos              (0U)
19209 #define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */
19210 #define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */
19211 #define OCTOSPI_CR_ABORT_Pos           (1U)
19212 #define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */
19213 #define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */
19214 #define OCTOSPI_CR_DMAEN_Pos           (2U)
19215 #define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */
19216 #define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
19217 #define OCTOSPI_CR_TCEN_Pos            (3U)
19218 #define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */
19219 #define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
19220 #define OCTOSPI_CR_DQM_Pos             (6U)
19221 #define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */
19222 #define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */
19223 #define OCTOSPI_CR_FSEL_Pos            (7U)
19224 #define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */
19225 #define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */
19226 #define OCTOSPI_CR_FTHRES_Pos          (8U)
19227 #define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */
19228 #define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */
19229 #define OCTOSPI_CR_TEIE_Pos            (16U)
19230 #define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */
19231 #define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
19232 #define OCTOSPI_CR_TCIE_Pos            (17U)
19233 #define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */
19234 #define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
19235 #define OCTOSPI_CR_FTIE_Pos            (18U)
19236 #define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */
19237 #define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
19238 #define OCTOSPI_CR_SMIE_Pos            (19U)
19239 #define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */
19240 #define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
19241 #define OCTOSPI_CR_TOIE_Pos            (20U)
19242 #define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */
19243 #define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
19244 #define OCTOSPI_CR_APMS_Pos            (22U)
19245 #define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */
19246 #define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */
19247 #define OCTOSPI_CR_PMM_Pos             (23U)
19248 #define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */
19249 #define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
19250 #define OCTOSPI_CR_FMODE_Pos           (28U)
19251 #define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */
19252 #define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */
19253 #define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */
19254 #define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */
19255 
19256 /****************  Bit definition for OCTOSPI_DCR1 register  ******************/
19257 #define OCTOSPI_DCR1_CKMODE_Pos        (0U)
19258 #define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */
19259 #define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */
19260 #define OCTOSPI_DCR1_FRCK_Pos          (1U)
19261 #define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */
19262 #define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */
19263 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
19264 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
19265 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
19266 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
19267 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
19268 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
19269 #define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)
19270 #define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */
19271 #define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */
19272 #define OCTOSPI_DCR1_MTYP_Pos          (24U)
19273 #define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */
19274 #define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */
19275 #define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */
19276 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
19277 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
19278 
19279 /* Legacy define */
19280 #define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
19281 #define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
19282 #define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
19283 
19284 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
19285 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
19286 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
19287 #define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */
19288 #define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)
19289 #define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */
19290 #define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */
19291 #define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */
19292 #define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */
19293 #define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */
19294 
19295 /****************  Bit definition for OCTOSPI_DCR3 register  ******************/
19296 #define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)
19297 #define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */
19298 #define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */
19299 #define OCTOSPI_DCR3_CSBOUND_Pos       (16U)
19300 #define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */
19301 #define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */
19302 
19303 /****************  Bit definition for OCTOSPI_DCR4 register  ******************/
19304 #define OCTOSPI_DCR4_REFRESH_Pos       (0U)
19305 #define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
19306 #define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */
19307 
19308 /*****************  Bit definition for OCTOSPI_SR register  *******************/
19309 #define OCTOSPI_SR_TEF_Pos             (0U)
19310 #define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */
19311 #define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
19312 #define OCTOSPI_SR_TCF_Pos             (1U)
19313 #define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */
19314 #define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
19315 #define OCTOSPI_SR_FTF_Pos             (2U)
19316 #define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */
19317 #define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */
19318 #define OCTOSPI_SR_SMF_Pos             (3U)
19319 #define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */
19320 #define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */
19321 #define OCTOSPI_SR_TOF_Pos             (4U)
19322 #define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */
19323 #define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */
19324 #define OCTOSPI_SR_BUSY_Pos            (5U)
19325 #define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */
19326 #define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */
19327 #define OCTOSPI_SR_FLEVEL_Pos          (8U)
19328 #define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */
19329 #define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */
19330 
19331 /****************  Bit definition for OCTOSPI_FCR register  *******************/
19332 #define OCTOSPI_FCR_CTEF_Pos           (0U)
19333 #define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */
19334 #define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
19335 #define OCTOSPI_FCR_CTCF_Pos           (1U)
19336 #define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */
19337 #define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
19338 #define OCTOSPI_FCR_CSMF_Pos           (3U)
19339 #define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */
19340 #define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
19341 #define OCTOSPI_FCR_CTOF_Pos           (4U)
19342 #define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */
19343 #define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
19344 
19345 /****************  Bit definition for OCTOSPI_DLR register  *******************/
19346 #define OCTOSPI_DLR_DL_Pos             (0U)
19347 #define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */
19348 #define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */
19349 
19350 /*****************  Bit definition for OCTOSPI_AR register  *******************/
19351 #define OCTOSPI_AR_ADDRESS_Pos         (0U)
19352 #define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
19353 #define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */
19354 
19355 /*****************  Bit definition for OCTOSPI_DR register  *******************/
19356 #define OCTOSPI_DR_DATA_Pos            (0U)
19357 #define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */
19358 #define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */
19359 
19360 /***************  Bit definition for OCTOSPI_PSMKR register  ******************/
19361 #define OCTOSPI_PSMKR_MASK_Pos         (0U)
19362 #define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
19363 #define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */
19364 
19365 /***************  Bit definition for OCTOSPI_PSMAR register  ******************/
19366 #define OCTOSPI_PSMAR_MATCH_Pos        (0U)
19367 #define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
19368 #define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */
19369 
19370 /****************  Bit definition for OCTOSPI_PIR register  *******************/
19371 #define OCTOSPI_PIR_INTERVAL_Pos       (0U)
19372 #define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */
19373 #define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */
19374 
19375 /****************  Bit definition for OCTOSPI_CCR register  *******************/
19376 #define OCTOSPI_CCR_IMODE_Pos          (0U)
19377 #define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */
19378 #define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */
19379 #define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */
19380 #define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */
19381 #define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */
19382 #define OCTOSPI_CCR_IDTR_Pos           (3U)
19383 #define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */
19384 #define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */
19385 #define OCTOSPI_CCR_ISIZE_Pos          (4U)
19386 #define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */
19387 #define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */
19388 #define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */
19389 #define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */
19390 #define OCTOSPI_CCR_ADMODE_Pos         (8U)
19391 #define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */
19392 #define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */
19393 #define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */
19394 #define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */
19395 #define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */
19396 #define OCTOSPI_CCR_ADDTR_Pos          (11U)
19397 #define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */
19398 #define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */
19399 #define OCTOSPI_CCR_ADSIZE_Pos         (12U)
19400 #define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */
19401 #define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */
19402 #define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */
19403 #define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */
19404 #define OCTOSPI_CCR_ABMODE_Pos         (16U)
19405 #define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */
19406 #define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */
19407 #define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */
19408 #define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */
19409 #define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */
19410 #define OCTOSPI_CCR_ABDTR_Pos          (19U)
19411 #define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */
19412 #define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */
19413 #define OCTOSPI_CCR_ABSIZE_Pos         (20U)
19414 #define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */
19415 #define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */
19416 #define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */
19417 #define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */
19418 #define OCTOSPI_CCR_DMODE_Pos          (24U)
19419 #define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */
19420 #define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */
19421 #define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */
19422 #define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */
19423 #define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */
19424 #define OCTOSPI_CCR_DDTR_Pos           (27U)
19425 #define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */
19426 #define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */
19427 #define OCTOSPI_CCR_DQSE_Pos           (29U)
19428 #define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */
19429 #define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */
19430 #define OCTOSPI_CCR_SIOO_Pos           (31U)
19431 #define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */
19432 #define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */
19433 
19434 /****************  Bit definition for OCTOSPI_TCR register  *******************/
19435 #define OCTOSPI_TCR_DCYC_Pos           (0U)
19436 #define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */
19437 #define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */
19438 #define OCTOSPI_TCR_DHQC_Pos           (28U)
19439 #define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */
19440 #define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */
19441 #define OCTOSPI_TCR_SSHIFT_Pos         (30U)
19442 #define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */
19443 #define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */
19444 
19445 /*****************  Bit definition for OCTOSPI_IR register  *******************/
19446 #define OCTOSPI_IR_INSTRUCTION_Pos     (0U)
19447 #define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
19448 #define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */
19449 
19450 /****************  Bit definition for OCTOSPI_ABR register  *******************/
19451 #define OCTOSPI_ABR_ALTERNATE_Pos      (0U)
19452 #define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
19453 #define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */
19454 
19455 /****************  Bit definition for OCTOSPI_LPTR register  ******************/
19456 #define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)
19457 #define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */
19458 #define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */
19459 
19460 /****************  Bit definition for OCTOSPI_WPCCR register  *******************/
19461 #define OCTOSPI_WPCCR_IMODE_Pos        (0U)
19462 #define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */
19463 #define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */
19464 #define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */
19465 #define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */
19466 #define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */
19467 #define OCTOSPI_WPCCR_IDTR_Pos         (3U)
19468 #define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */
19469 #define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */
19470 #define OCTOSPI_WPCCR_ISIZE_Pos        (4U)
19471 #define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */
19472 #define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */
19473 #define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */
19474 #define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */
19475 #define OCTOSPI_WPCCR_ADMODE_Pos       (8U)
19476 #define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */
19477 #define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */
19478 #define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */
19479 #define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */
19480 #define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */
19481 #define OCTOSPI_WPCCR_ADDTR_Pos        (11U)
19482 #define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */
19483 #define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */
19484 #define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)
19485 #define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */
19486 #define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */
19487 #define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */
19488 #define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */
19489 #define OCTOSPI_WPCCR_ABMODE_Pos       (16U)
19490 #define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */
19491 #define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */
19492 #define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */
19493 #define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */
19494 #define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */
19495 #define OCTOSPI_WPCCR_ABDTR_Pos        (19U)
19496 #define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */
19497 #define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */
19498 #define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)
19499 #define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */
19500 #define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */
19501 #define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */
19502 #define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */
19503 #define OCTOSPI_WPCCR_DMODE_Pos        (24U)
19504 #define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */
19505 #define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */
19506 #define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */
19507 #define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */
19508 #define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */
19509 #define OCTOSPI_WPCCR_DDTR_Pos         (27U)
19510 #define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */
19511 #define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */
19512 #define OCTOSPI_WPCCR_DQSE_Pos         (29U)
19513 #define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */
19514 #define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */
19515 #define OCTOSPI_WPCCR_SIOO_Pos         (31U)
19516 #define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */
19517 #define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */
19518 
19519 /****************  Bit definition for OCTOSPI_WPTCR register  *******************/
19520 #define OCTOSPI_WPTCR_DCYC_Pos         (0U)
19521 #define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */
19522 #define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */
19523 #define OCTOSPI_WPTCR_DHQC_Pos         (28U)
19524 #define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */
19525 #define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */
19526 #define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)
19527 #define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */
19528 #define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */
19529 
19530 /*****************  Bit definition for OCTOSPI_WPIR register  *******************/
19531 #define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)
19532 #define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
19533 #define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */
19534 
19535 /****************  Bit definition for OCTOSPI_WPABR register  *******************/
19536 #define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)
19537 #define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
19538 #define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */
19539 
19540 /****************  Bit definition for OCTOSPI_WCCR register  ******************/
19541 #define OCTOSPI_WCCR_IMODE_Pos         (0U)
19542 #define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */
19543 #define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */
19544 #define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */
19545 #define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */
19546 #define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */
19547 #define OCTOSPI_WCCR_IDTR_Pos          (3U)
19548 #define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */
19549 #define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */
19550 #define OCTOSPI_WCCR_ISIZE_Pos         (4U)
19551 #define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */
19552 #define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */
19553 #define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */
19554 #define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */
19555 #define OCTOSPI_WCCR_ADMODE_Pos        (8U)
19556 #define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */
19557 #define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */
19558 #define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */
19559 #define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */
19560 #define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */
19561 #define OCTOSPI_WCCR_ADDTR_Pos         (11U)
19562 #define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */
19563 #define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */
19564 #define OCTOSPI_WCCR_ADSIZE_Pos        (12U)
19565 #define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */
19566 #define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */
19567 #define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */
19568 #define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */
19569 #define OCTOSPI_WCCR_ABMODE_Pos        (16U)
19570 #define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */
19571 #define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */
19572 #define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */
19573 #define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */
19574 #define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */
19575 #define OCTOSPI_WCCR_ABDTR_Pos         (19U)
19576 #define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */
19577 #define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */
19578 #define OCTOSPI_WCCR_ABSIZE_Pos        (20U)
19579 #define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */
19580 #define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */
19581 #define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */
19582 #define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */
19583 #define OCTOSPI_WCCR_DMODE_Pos         (24U)
19584 #define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */
19585 #define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */
19586 #define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */
19587 #define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */
19588 #define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */
19589 #define OCTOSPI_WCCR_DDTR_Pos          (27U)
19590 #define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */
19591 #define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */
19592 #define OCTOSPI_WCCR_DQSE_Pos          (29U)
19593 #define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */
19594 #define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */
19595 #define OCTOSPI_WCCR_SIOO_Pos          (31U)
19596 #define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */
19597 #define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */
19598 
19599 /****************  Bit definition for OCTOSPI_WTCR register  ******************/
19600 #define OCTOSPI_WTCR_DCYC_Pos          (0U)
19601 #define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */
19602 #define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */
19603 
19604 /****************  Bit definition for OCTOSPI_WIR register  *******************/
19605 #define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)
19606 #define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
19607 #define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */
19608 
19609 /****************  Bit definition for OCTOSPI_WABR register  ******************/
19610 #define OCTOSPI_WABR_ALTERNATE_Pos     (0U)
19611 #define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
19612 #define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */
19613 
19614 /****************  Bit definition for OCTOSPI_HLCR register  ******************/
19615 #define OCTOSPI_HLCR_LM_Pos            (0U)
19616 #define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */
19617 #define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */
19618 #define OCTOSPI_HLCR_WZL_Pos           (1U)
19619 #define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */
19620 #define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */
19621 #define OCTOSPI_HLCR_TACC_Pos          (8U)
19622 #define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */
19623 #define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */
19624 #define OCTOSPI_HLCR_TRWR_Pos          (16U)
19625 #define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */
19626 #define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */
19627 
19628 /****************  Bit definition for OCTOSPI_VER register  *******************/
19629 #define OCTOSPI_VER_VER_Pos            (0U)
19630 #define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */
19631 #define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */
19632 
19633 /*****************  Bit definition for OCTOSPI_ID register  *******************/
19634 #define OCTOSPI_ID_ID_Pos              (0U)
19635 #define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */
19636 #define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */
19637 
19638 /****************  Bit definition for OCTOSPI_MID register  *******************/
19639 #define OCTOSPI_MID_MID_Pos            (0U)
19640 #define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */
19641 #define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */
19642 
19643 /******************************************************************************/
19644 /*                                                                            */
19645 /*                                  OCTOSPIM                                  */
19646 /*                                                                            */
19647 /******************************************************************************/
19648 
19649 /***************  Bit definition for OCTOSPIM_CR register  ********************/
19650 #define OCTOSPIM_CR_MUXEN_Pos          (0U)
19651 #define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */
19652 #define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */
19653 #define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)
19654 #define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
19655 #define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */
19656 
19657 /***************  Bit definition for OCTOSPIM_PCR register  *******************/
19658 #define OCTOSPIM_PCR_CLKEN_Pos         (0U)
19659 #define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */
19660 #define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */
19661 #define OCTOSPIM_PCR_CLKSRC_Pos        (1U)
19662 #define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */
19663 #define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */
19664 #define OCTOSPIM_PCR_DQSEN_Pos         (4U)
19665 #define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */
19666 #define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */
19667 #define OCTOSPIM_PCR_DQSSRC_Pos        (5U)
19668 #define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */
19669 #define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */
19670 #define OCTOSPIM_PCR_NCSEN_Pos         (8U)
19671 #define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */
19672 #define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */
19673 #define OCTOSPIM_PCR_NCSSRC_Pos        (9U)
19674 #define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */
19675 #define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */
19676 #define OCTOSPIM_PCR_IOLEN_Pos         (16U)
19677 #define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */
19678 #define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */
19679 #define OCTOSPIM_PCR_IOLSRC_Pos        (17U)
19680 #define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */
19681 #define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */
19682 #define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */
19683 #define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */
19684 #define OCTOSPIM_PCR_IOHEN_Pos         (24U)
19685 #define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */
19686 #define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */
19687 #define OCTOSPIM_PCR_IOHSRC_Pos        (25U)
19688 #define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */
19689 #define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */
19690 #define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */
19691 #define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */
19692 /******************************************************************************/
19693 /*                                                                            */
19694 /*                      Analog Comparators (COMP)                             */
19695 /*                                                                            */
19696 /******************************************************************************/
19697 
19698 /*******************  Bit definition for COMP_SR register  ********************/
19699 #define COMP_SR_C1VAL_Pos            (0U)
19700 #define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */
19701 #define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
19702 #define COMP_SR_C2VAL_Pos            (1U)
19703 #define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */
19704 #define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk
19705 #define COMP_SR_C1IF_Pos             (16U)
19706 #define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */
19707 #define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
19708 #define COMP_SR_C2IF_Pos             (17U)
19709 #define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */
19710 #define COMP_SR_C2IF                 COMP_SR_C2IF_Msk
19711 /*******************  Bit definition for COMP_ICFR register  ********************/
19712 #define COMP_ICFR_C1IF_Pos           (16U)
19713 #define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */
19714 #define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk
19715 #define COMP_ICFR_C2IF_Pos           (17U)
19716 #define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */
19717 #define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk
19718 /*******************  Bit definition for COMP_OR register  ********************/
19719 #define COMP_OR_AFOPA6_Pos           (0U)
19720 #define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */
19721 #define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk
19722 #define COMP_OR_AFOPA8_Pos           (1U)
19723 #define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */
19724 #define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk
19725 #define COMP_OR_AFOPB12_Pos          (2U)
19726 #define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */
19727 #define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk
19728 #define COMP_OR_AFOPE6_Pos           (3U)
19729 #define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */
19730 #define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk
19731 #define COMP_OR_AFOPE15_Pos          (4U)
19732 #define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */
19733 #define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk
19734 #define COMP_OR_AFOPG2_Pos           (5U)
19735 #define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */
19736 #define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk
19737 #define COMP_OR_AFOPG3_Pos           (6U)
19738 #define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */
19739 #define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk
19740 #define COMP_OR_AFOPG4_Pos           (7U)
19741 #define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */
19742 #define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk
19743 #define COMP_OR_AFOPI1_Pos           (8U)
19744 #define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */
19745 #define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk
19746 #define COMP_OR_AFOPI4_Pos           (9U)
19747 #define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */
19748 #define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk
19749 #define COMP_OR_AFOPK2_Pos           (10U)
19750 #define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */
19751 #define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk
19752 
19753 /*!< ******************  Bit definition for COMP_CFGRx register  ********************/
19754 #define COMP_CFGRx_EN_Pos            (0U)
19755 #define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */
19756 #define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */
19757 #define COMP_CFGRx_BRGEN_Pos         (1U)
19758 #define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */
19759 #define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */
19760 #define COMP_CFGRx_SCALEN_Pos        (2U)
19761 #define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */
19762 #define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */
19763 #define COMP_CFGRx_POLARITY_Pos      (3U)
19764 #define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */
19765 #define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */
19766 #define COMP_CFGRx_WINMODE_Pos       (4U)
19767 #define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */
19768 #define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */
19769 #define COMP_CFGRx_ITEN_Pos          (6U)
19770 #define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */
19771 #define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */
19772 #define COMP_CFGRx_HYST_Pos          (8U)
19773 #define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */
19774 #define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */
19775 #define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */
19776 #define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */
19777 #define COMP_CFGRx_PWRMODE_Pos       (12U)
19778 #define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */
19779 #define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */
19780 #define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */
19781 #define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */
19782 #define COMP_CFGRx_INMSEL_Pos        (16U)
19783 #define COMP_CFGRx_INMSEL_Msk        (0xFUL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x000F0000 */
19784 #define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */
19785 #define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */
19786 #define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */
19787 #define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */
19788 #define COMP_CFGRx_INMSEL_3          (0x8UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00080000 */
19789 #define COMP_CFGRx_INPSEL_Pos        (20U)
19790 #define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */
19791 #define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */
19792 #define COMP_CFGRx_INP2SEL_Pos        (22U)
19793 #define COMP_CFGRx_INP2SEL_Msk        (0x1UL << COMP_CFGRx_INP2SEL_Pos)        /*!< 0x00400000 */
19794 #define COMP_CFGRx_INP2SEL            COMP_CFGRx_INP2SEL_Msk                   /*!< COMPx  input plus 2 selection bit     */
19795 #define COMP_CFGRx_BLANKING_Pos      (24U)
19796 #define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */
19797 #define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */
19798 #define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */
19799 #define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */
19800 #define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */
19801 #define COMP_CFGRx_LOCK_Pos          (31U)
19802 #define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */
19803 #define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */
19804 
19805 
19806 /******************************************************************************/
19807 /*                                                                            */
19808 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
19809 /*                                                                            */
19810 /******************************************************************************/
19811 /******************  Bit definition for USART_CR1 register  *******************/
19812 #define USART_CR1_UE_Pos                (0U)
19813 #define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
19814 #define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
19815 #define USART_CR1_UESM_Pos              (1U)
19816 #define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
19817 #define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
19818 #define USART_CR1_RE_Pos                (2U)
19819 #define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
19820 #define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
19821 #define USART_CR1_TE_Pos                (3U)
19822 #define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
19823 #define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
19824 #define USART_CR1_IDLEIE_Pos            (4U)
19825 #define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
19826 #define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
19827 #define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
19828 #define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
19829 #define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
19830 #define USART_CR1_TCIE_Pos              (6U)
19831 #define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
19832 #define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
19833 #define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
19834 #define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
19835 #define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
19836 #define USART_CR1_PEIE_Pos              (8U)
19837 #define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
19838 #define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
19839 #define USART_CR1_PS_Pos                (9U)
19840 #define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
19841 #define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
19842 #define USART_CR1_PCE_Pos               (10U)
19843 #define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
19844 #define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
19845 #define USART_CR1_WAKE_Pos              (11U)
19846 #define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
19847 #define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
19848 #define USART_CR1_M_Pos                 (12U)
19849 #define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
19850 #define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
19851 #define USART_CR1_M0_Pos                (12U)
19852 #define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
19853 #define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
19854 #define USART_CR1_MME_Pos               (13U)
19855 #define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
19856 #define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
19857 #define USART_CR1_CMIE_Pos              (14U)
19858 #define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
19859 #define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
19860 #define USART_CR1_OVER8_Pos             (15U)
19861 #define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
19862 #define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
19863 #define USART_CR1_DEDT_Pos              (16U)
19864 #define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
19865 #define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
19866 #define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
19867 #define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
19868 #define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
19869 #define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
19870 #define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
19871 #define USART_CR1_DEAT_Pos              (21U)
19872 #define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
19873 #define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
19874 #define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
19875 #define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
19876 #define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
19877 #define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
19878 #define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
19879 #define USART_CR1_RTOIE_Pos             (26U)
19880 #define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
19881 #define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
19882 #define USART_CR1_EOBIE_Pos             (27U)
19883 #define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
19884 #define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
19885 #define USART_CR1_M1_Pos                (28U)
19886 #define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
19887 #define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
19888 #define USART_CR1_FIFOEN_Pos            (29U)
19889 #define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
19890 #define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
19891 #define USART_CR1_TXFEIE_Pos            (30U)
19892 #define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
19893 #define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
19894 #define USART_CR1_RXFFIE_Pos            (31U)
19895 #define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
19896 #define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
19897 
19898 /* Legacy define */
19899 #define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
19900 #define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
19901 
19902 /******************  Bit definition for USART_CR2 register  *******************/
19903 #define USART_CR2_SLVEN_Pos             (0U)
19904 #define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
19905 #define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
19906 #define USART_CR2_DIS_NSS_Pos           (3U)
19907 #define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
19908 #define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
19909 #define USART_CR2_ADDM7_Pos             (4U)
19910 #define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
19911 #define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
19912 #define USART_CR2_LBDL_Pos              (5U)
19913 #define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
19914 #define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
19915 #define USART_CR2_LBDIE_Pos             (6U)
19916 #define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
19917 #define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
19918 #define USART_CR2_LBCL_Pos              (8U)
19919 #define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
19920 #define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
19921 #define USART_CR2_CPHA_Pos              (9U)
19922 #define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
19923 #define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
19924 #define USART_CR2_CPOL_Pos              (10U)
19925 #define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
19926 #define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
19927 #define USART_CR2_CLKEN_Pos             (11U)
19928 #define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
19929 #define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
19930 #define USART_CR2_STOP_Pos              (12U)
19931 #define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
19932 #define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
19933 #define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
19934 #define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
19935 #define USART_CR2_LINEN_Pos             (14U)
19936 #define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
19937 #define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
19938 #define USART_CR2_SWAP_Pos              (15U)
19939 #define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
19940 #define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
19941 #define USART_CR2_RXINV_Pos             (16U)
19942 #define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
19943 #define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
19944 #define USART_CR2_TXINV_Pos             (17U)
19945 #define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
19946 #define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
19947 #define USART_CR2_DATAINV_Pos           (18U)
19948 #define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
19949 #define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
19950 #define USART_CR2_MSBFIRST_Pos          (19U)
19951 #define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
19952 #define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
19953 #define USART_CR2_ABREN_Pos             (20U)
19954 #define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
19955 #define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
19956 #define USART_CR2_ABRMODE_Pos           (21U)
19957 #define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
19958 #define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
19959 #define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
19960 #define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
19961 #define USART_CR2_RTOEN_Pos             (23U)
19962 #define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
19963 #define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
19964 #define USART_CR2_ADD_Pos               (24U)
19965 #define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
19966 #define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
19967 
19968 /******************  Bit definition for USART_CR3 register  *******************/
19969 #define USART_CR3_EIE_Pos               (0U)
19970 #define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
19971 #define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
19972 #define USART_CR3_IREN_Pos              (1U)
19973 #define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
19974 #define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
19975 #define USART_CR3_IRLP_Pos              (2U)
19976 #define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
19977 #define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
19978 #define USART_CR3_HDSEL_Pos             (3U)
19979 #define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
19980 #define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
19981 #define USART_CR3_NACK_Pos              (4U)
19982 #define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
19983 #define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
19984 #define USART_CR3_SCEN_Pos              (5U)
19985 #define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
19986 #define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
19987 #define USART_CR3_DMAR_Pos              (6U)
19988 #define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
19989 #define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
19990 #define USART_CR3_DMAT_Pos              (7U)
19991 #define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
19992 #define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
19993 #define USART_CR3_RTSE_Pos              (8U)
19994 #define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
19995 #define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
19996 #define USART_CR3_CTSE_Pos              (9U)
19997 #define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
19998 #define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
19999 #define USART_CR3_CTSIE_Pos             (10U)
20000 #define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
20001 #define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
20002 #define USART_CR3_ONEBIT_Pos            (11U)
20003 #define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
20004 #define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
20005 #define USART_CR3_OVRDIS_Pos            (12U)
20006 #define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
20007 #define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
20008 #define USART_CR3_DDRE_Pos              (13U)
20009 #define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
20010 #define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
20011 #define USART_CR3_DEM_Pos               (14U)
20012 #define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
20013 #define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
20014 #define USART_CR3_DEP_Pos               (15U)
20015 #define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
20016 #define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
20017 #define USART_CR3_SCARCNT_Pos           (17U)
20018 #define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
20019 #define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
20020 #define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
20021 #define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
20022 #define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
20023 #define USART_CR3_WUS_Pos               (20U)
20024 #define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
20025 #define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
20026 #define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
20027 #define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
20028 #define USART_CR3_WUFIE_Pos             (22U)
20029 #define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
20030 #define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
20031 #define USART_CR3_TXFTIE_Pos            (23U)
20032 #define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
20033 #define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
20034 #define USART_CR3_TCBGTIE_Pos           (24U)
20035 #define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
20036 #define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
20037 #define USART_CR3_RXFTCFG_Pos           (25U)
20038 #define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
20039 #define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
20040 #define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
20041 #define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
20042 #define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
20043 #define USART_CR3_RXFTIE_Pos            (28U)
20044 #define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
20045 #define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
20046 #define USART_CR3_TXFTCFG_Pos           (29U)
20047 #define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
20048 #define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
20049 #define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
20050 #define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
20051 #define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
20052 
20053 /******************  Bit definition for USART_BRR register  *******************/
20054 #define USART_BRR_DIV_FRACTION_Pos      (0U)
20055 #define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
20056 #define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
20057 #define USART_BRR_DIV_MANTISSA_Pos      (4U)
20058 #define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
20059 #define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
20060 
20061 /******************  Bit definition for USART_GTPR register  ******************/
20062 #define USART_GTPR_PSC_Pos              (0U)
20063 #define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
20064 #define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
20065 #define USART_GTPR_GT_Pos               (8U)
20066 #define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
20067 #define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
20068 
20069 /*******************  Bit definition for USART_RTOR register  *****************/
20070 #define USART_RTOR_RTO_Pos              (0U)
20071 #define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
20072 #define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
20073 #define USART_RTOR_BLEN_Pos             (24U)
20074 #define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
20075 #define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
20076 
20077 /*******************  Bit definition for USART_RQR register  ******************/
20078 #define USART_RQR_ABRRQ_Pos             (0U)
20079 #define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
20080 #define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
20081 #define USART_RQR_SBKRQ_Pos             (1U)
20082 #define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
20083 #define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
20084 #define USART_RQR_MMRQ_Pos              (2U)
20085 #define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
20086 #define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
20087 #define USART_RQR_RXFRQ_Pos             (3U)
20088 #define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
20089 #define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
20090 #define USART_RQR_TXFRQ_Pos             (4U)
20091 #define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
20092 #define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
20093 
20094 /*******************  Bit definition for USART_ISR register  ******************/
20095 #define USART_ISR_PE_Pos                (0U)
20096 #define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
20097 #define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
20098 #define USART_ISR_FE_Pos                (1U)
20099 #define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
20100 #define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
20101 #define USART_ISR_NE_Pos                (2U)
20102 #define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
20103 #define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
20104 #define USART_ISR_ORE_Pos               (3U)
20105 #define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
20106 #define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
20107 #define USART_ISR_IDLE_Pos              (4U)
20108 #define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
20109 #define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
20110 #define USART_ISR_RXNE_RXFNE_Pos        (5U)
20111 #define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
20112 #define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
20113 #define USART_ISR_TC_Pos                (6U)
20114 #define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
20115 #define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
20116 #define USART_ISR_TXE_TXFNF_Pos         (7U)
20117 #define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
20118 #define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
20119 #define USART_ISR_LBDF_Pos              (8U)
20120 #define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
20121 #define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
20122 #define USART_ISR_CTSIF_Pos             (9U)
20123 #define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
20124 #define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
20125 #define USART_ISR_CTS_Pos               (10U)
20126 #define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
20127 #define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
20128 #define USART_ISR_RTOF_Pos              (11U)
20129 #define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
20130 #define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
20131 #define USART_ISR_EOBF_Pos              (12U)
20132 #define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
20133 #define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
20134 #define USART_ISR_UDR_Pos               (13U)
20135 #define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
20136 #define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
20137 #define USART_ISR_ABRE_Pos              (14U)
20138 #define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
20139 #define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
20140 #define USART_ISR_ABRF_Pos              (15U)
20141 #define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
20142 #define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
20143 #define USART_ISR_BUSY_Pos              (16U)
20144 #define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
20145 #define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
20146 #define USART_ISR_CMF_Pos               (17U)
20147 #define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
20148 #define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
20149 #define USART_ISR_SBKF_Pos              (18U)
20150 #define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
20151 #define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
20152 #define USART_ISR_RWU_Pos               (19U)
20153 #define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
20154 #define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
20155 #define USART_ISR_WUF_Pos               (20U)
20156 #define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
20157 #define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
20158 #define USART_ISR_TEACK_Pos             (21U)
20159 #define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
20160 #define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
20161 #define USART_ISR_REACK_Pos             (22U)
20162 #define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
20163 #define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
20164 #define USART_ISR_TXFE_Pos              (23U)
20165 #define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
20166 #define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
20167 #define USART_ISR_RXFF_Pos              (24U)
20168 #define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
20169 #define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
20170 #define USART_ISR_TCBGT_Pos             (25U)
20171 #define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
20172 #define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
20173 #define USART_ISR_RXFT_Pos              (26U)
20174 #define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
20175 #define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
20176 #define USART_ISR_TXFT_Pos              (27U)
20177 #define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
20178 #define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
20179 
20180 /*******************  Bit definition for USART_ICR register  ******************/
20181 #define USART_ICR_PECF_Pos              (0U)
20182 #define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
20183 #define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
20184 #define USART_ICR_FECF_Pos              (1U)
20185 #define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
20186 #define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
20187 #define USART_ICR_NECF_Pos              (2U)
20188 #define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
20189 #define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
20190 #define USART_ICR_ORECF_Pos             (3U)
20191 #define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
20192 #define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
20193 #define USART_ICR_IDLECF_Pos            (4U)
20194 #define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
20195 #define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
20196 #define USART_ICR_TXFECF_Pos            (5U)
20197 #define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
20198 #define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
20199 #define USART_ICR_TCCF_Pos              (6U)
20200 #define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
20201 #define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
20202 #define USART_ICR_TCBGTCF_Pos           (7U)
20203 #define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
20204 #define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
20205 #define USART_ICR_LBDCF_Pos             (8U)
20206 #define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
20207 #define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
20208 #define USART_ICR_CTSCF_Pos             (9U)
20209 #define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
20210 #define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
20211 #define USART_ICR_RTOCF_Pos             (11U)
20212 #define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
20213 #define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
20214 #define USART_ICR_EOBCF_Pos             (12U)
20215 #define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
20216 #define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
20217 #define USART_ICR_UDRCF_Pos             (13U)
20218 #define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
20219 #define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
20220 #define USART_ICR_CMCF_Pos              (17U)
20221 #define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
20222 #define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
20223 #define USART_ICR_WUCF_Pos              (20U)
20224 #define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
20225 #define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
20226 
20227 /*******************  Bit definition for USART_RDR register  ******************/
20228 #define USART_RDR_RDR_Pos               (0U)
20229 #define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
20230 #define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
20231 
20232 /*******************  Bit definition for USART_TDR register  ******************/
20233 #define USART_TDR_TDR_Pos               (0U)
20234 #define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
20235 #define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
20236 
20237 /*******************  Bit definition for USART_PRESC register  ******************/
20238 #define USART_PRESC_PRESCALER_Pos       (0U)
20239 #define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
20240 #define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
20241 #define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
20242 #define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
20243 #define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
20244 #define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
20245 
20246 /******************************************************************************/
20247 /*                                                                            */
20248 /*           Single Wire Protocol Master Interface (SWPMI)                    */
20249 /*                                                                            */
20250 /******************************************************************************/
20251 
20252 /*******************  Bit definition for SWPMI_CR register   ********************/
20253 #define SWPMI_CR_RXDMA_Pos       (0U)
20254 #define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
20255 #define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
20256 #define SWPMI_CR_TXDMA_Pos       (1U)
20257 #define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
20258 #define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
20259 #define SWPMI_CR_RXMODE_Pos      (2U)
20260 #define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
20261 #define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
20262 #define SWPMI_CR_TXMODE_Pos      (3U)
20263 #define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
20264 #define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
20265 #define SWPMI_CR_LPBK_Pos        (4U)
20266 #define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
20267 #define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
20268 #define SWPMI_CR_SWPACT_Pos      (5U)
20269 #define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
20270 #define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
20271 #define SWPMI_CR_DEACT_Pos       (10U)
20272 #define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
20273 #define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
20274 #define SWPMI_CR_SWPEN_Pos       (11U)
20275 #define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
20276 #define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
20277 
20278 /*******************  Bit definition for SWPMI_BRR register  ********************/
20279 #define SWPMI_BRR_BR_Pos         (0U)
20280 #define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
20281 #define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
20282 
20283 /*******************  Bit definition for SWPMI_ISR register  ********************/
20284 #define SWPMI_ISR_RXBFF_Pos      (0U)
20285 #define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
20286 #define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
20287 #define SWPMI_ISR_TXBEF_Pos      (1U)
20288 #define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
20289 #define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
20290 #define SWPMI_ISR_RXBERF_Pos     (2U)
20291 #define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
20292 #define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
20293 #define SWPMI_ISR_RXOVRF_Pos     (3U)
20294 #define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
20295 #define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
20296 #define SWPMI_ISR_TXUNRF_Pos     (4U)
20297 #define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
20298 #define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
20299 #define SWPMI_ISR_RXNE_Pos       (5U)
20300 #define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
20301 #define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
20302 #define SWPMI_ISR_TXE_Pos        (6U)
20303 #define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
20304 #define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
20305 #define SWPMI_ISR_TCF_Pos        (7U)
20306 #define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
20307 #define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
20308 #define SWPMI_ISR_SRF_Pos        (8U)
20309 #define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
20310 #define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
20311 #define SWPMI_ISR_SUSP_Pos       (9U)
20312 #define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
20313 #define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
20314 #define SWPMI_ISR_DEACTF_Pos     (10U)
20315 #define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
20316 #define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
20317 #define SWPMI_ISR_RDYF_Pos       (11U)
20318 #define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
20319 #define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
20320 
20321 /*******************  Bit definition for SWPMI_ICR register  ********************/
20322 #define SWPMI_ICR_CRXBFF_Pos     (0U)
20323 #define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
20324 #define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
20325 #define SWPMI_ICR_CTXBEF_Pos     (1U)
20326 #define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
20327 #define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
20328 #define SWPMI_ICR_CRXBERF_Pos    (2U)
20329 #define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
20330 #define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
20331 #define SWPMI_ICR_CRXOVRF_Pos    (3U)
20332 #define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
20333 #define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
20334 #define SWPMI_ICR_CTXUNRF_Pos    (4U)
20335 #define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
20336 #define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
20337 #define SWPMI_ICR_CTCF_Pos       (7U)
20338 #define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
20339 #define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
20340 #define SWPMI_ICR_CSRF_Pos       (8U)
20341 #define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
20342 #define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
20343 #define SWPMI_ICR_CRDYF_Pos      (11U)
20344 #define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
20345 #define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
20346 
20347 /*******************  Bit definition for SWPMI_IER register  ********************/
20348 #define SWPMI_IER_RXBFIE_Pos     (0U)
20349 #define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
20350 #define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
20351 #define SWPMI_IER_TXBEIE_Pos     (1U)
20352 #define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
20353 #define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
20354 #define SWPMI_IER_RXBERIE_Pos    (2U)
20355 #define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
20356 #define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
20357 #define SWPMI_IER_RXOVRIE_Pos    (3U)
20358 #define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
20359 #define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
20360 #define SWPMI_IER_TXUNRIE_Pos    (4U)
20361 #define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
20362 #define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
20363 #define SWPMI_IER_RIE_Pos        (5U)
20364 #define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
20365 #define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
20366 #define SWPMI_IER_TIE_Pos        (6U)
20367 #define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
20368 #define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
20369 #define SWPMI_IER_TCIE_Pos       (7U)
20370 #define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
20371 #define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
20372 #define SWPMI_IER_SRIE_Pos       (8U)
20373 #define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
20374 #define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
20375 #define SWPMI_IER_RDYIE_Pos      (11U)
20376 #define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
20377 #define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
20378 
20379 /*******************  Bit definition for SWPMI_RFL register  ********************/
20380 #define SWPMI_RFL_RFL_Pos        (0U)
20381 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
20382 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
20383 #define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
20384 
20385 /*******************  Bit definition for SWPMI_TDR register  ********************/
20386 #define SWPMI_TDR_TD_Pos         (0U)
20387 #define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
20388 #define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
20389 
20390 /*******************  Bit definition for SWPMI_RDR register  ********************/
20391 #define SWPMI_RDR_RD_Pos         (0U)
20392 #define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
20393 #define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register           */
20394 
20395 
20396 /*******************  Bit definition for SWPMI_OR register  ********************/
20397 #define SWPMI_OR_TBYP_Pos        (0U)
20398 #define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
20399 #define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
20400 #define SWPMI_OR_CLASS_Pos       (1U)
20401 #define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
20402 #define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
20403 
20404 /******************************************************************************/
20405 /*                                                                            */
20406 /*                            Window WATCHDOG                                 */
20407 /*                                                                            */
20408 /******************************************************************************/
20409 /*******************  Bit definition for WWDG_CR register  ********************/
20410 #define WWDG_CR_T_Pos           (0U)
20411 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
20412 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
20413 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
20414 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
20415 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
20416 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
20417 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
20418 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
20419 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
20420 
20421 #define WWDG_CR_WDGA_Pos        (7U)
20422 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
20423 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
20424 
20425 /*******************  Bit definition for WWDG_CFR register  *******************/
20426 #define WWDG_CFR_W_Pos          (0U)
20427 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
20428 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
20429 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
20430 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
20431 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
20432 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
20433 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
20434 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
20435 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
20436 
20437 #define WWDG_CFR_EWI_Pos        (9U)
20438 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
20439 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
20440 
20441 #define WWDG_CFR_WDGTB_Pos      (11U)
20442 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
20443 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
20444 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
20445 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
20446 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
20447 
20448 /*******************  Bit definition for WWDG_SR register  ********************/
20449 #define WWDG_SR_EWIF_Pos        (0U)
20450 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
20451 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
20452 
20453 
20454 /******************************************************************************/
20455 /*                                                                            */
20456 /*                                DBG                                         */
20457 /*                                                                            */
20458 /******************************************************************************/
20459 /*********************************  DEVICE ID  ********************************/
20460 #define STM32H7_DEV_ID           0x480UL
20461 
20462 /********************  Bit definition for DBGMCU_IDCODE register  *************/
20463 #define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
20464 #define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
20465 #define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
20466 #define DBGMCU_IDCODE_REV_ID_Pos          (16U)
20467 #define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
20468 #define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
20469 
20470 /********************  Bit definition for DBGMCU_CR register  *****************/
20471 #define DBGMCU_CR_DBG_SLEEPCD_Pos         (0U)
20472 #define DBGMCU_CR_DBG_SLEEPCD_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */
20473 #define DBGMCU_CR_DBG_SLEEPCD             DBGMCU_CR_DBG_SLEEPCD_Msk
20474 #define DBGMCU_CR_DBG_STOPCD_Pos          (1U)
20475 #define DBGMCU_CR_DBG_STOPCD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos)  /*!< 0x00000002 */
20476 #define DBGMCU_CR_DBG_STOPCD              DBGMCU_CR_DBG_STOPCD_Msk
20477 #define DBGMCU_CR_DBG_STANDBYCD_Pos       (2U)
20478 #define DBGMCU_CR_DBG_STANDBYCD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */
20479 #define DBGMCU_CR_DBG_STANDBYCD           DBGMCU_CR_DBG_STANDBYCD_Msk
20480 
20481 /* Legacy defines */
20482 #define DBGMCU_CR_DBG_SLEEPD1_Pos         DBGMCU_CR_DBG_SLEEPCD_Pos
20483 #define DBGMCU_CR_DBG_SLEEPD1_Msk         DBGMCU_CR_DBG_SLEEPCD_Msk
20484 #define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPCD
20485 #define DBGMCU_CR_DBG_STOPD1_Pos          DBGMCU_CR_DBG_STOPCD_Pos
20486 #define DBGMCU_CR_DBG_STOPD1_Msk          DBGMCU_CR_DBG_STOPCD_Msk
20487 #define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPCD
20488 #define DBGMCU_CR_DBG_STANDBYD1_Pos       DBGMCU_CR_DBG_STANDBYCD_Pos
20489 #define DBGMCU_CR_DBG_STANDBYD1_Msk       DBGMCU_CR_DBG_STANDBYCD_Msk
20490 #define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYCD
20491 #define DBGMCU_CR_DBG_STOPSRD_Pos          (7U)
20492 #define DBGMCU_CR_DBG_STOPSRD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos)  /*!< 0x00000080 */
20493 #define DBGMCU_CR_DBG_STOPSRD              DBGMCU_CR_DBG_STOPSRD_Msk
20494 #define DBGMCU_CR_DBG_STANDBYSRD_Pos       (8U)
20495 #define DBGMCU_CR_DBG_STANDBYSRD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */
20496 #define DBGMCU_CR_DBG_STANDBYSRD           DBGMCU_CR_DBG_STANDBYSRD_Msk
20497 
20498 /* Legacy defines */
20499 #define DBGMCU_CR_DBG_STOPD3_Pos          DBGMCU_CR_DBG_STOPSRD_Pos
20500 #define DBGMCU_CR_DBG_STOPD3_Msk          DBGMCU_CR_DBG_STOPSRD_Msk
20501 #define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPSRD
20502 #define DBGMCU_CR_DBG_STANDBYD3_Pos       DBGMCU_CR_DBG_STANDBYSRD_Pos
20503 #define DBGMCU_CR_DBG_STANDBYD3_Msk       DBGMCU_CR_DBG_STANDBYSRD_Msk
20504 #define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYSRD
20505 
20506 #define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)
20507 #define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
20508 #define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk
20509 #define DBGMCU_CR_DBG_CKCDEN_Pos          (21U)
20510 #define DBGMCU_CR_DBG_CKCDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos)  /*!< 0x00200000 */
20511 #define DBGMCU_CR_DBG_CKCDEN              DBGMCU_CR_DBG_CKCDEN_Msk
20512 #define DBGMCU_CR_DBG_CKSRDEN_Pos          (22U)
20513 #define DBGMCU_CR_DBG_CKSRDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos)  /*!< 0x00400000 */
20514 #define DBGMCU_CR_DBG_CKSRDEN              DBGMCU_CR_DBG_CKSRDEN_Msk
20515 
20516 /* Legacy defines */
20517 #define DBGMCU_CR_DBG_CKD1EN_Pos          DBGMCU_CR_DBG_CKCDEN_Pos
20518 #define DBGMCU_CR_DBG_CKD1EN_Msk          DBGMCU_CR_DBG_CKCDEN_Msk
20519 #define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKCDEN
20520 #define DBGMCU_CR_DBG_CKD3EN_Pos          DBGMCU_CR_DBG_CKSRDEN_Pos
20521 #define DBGMCU_CR_DBG_CKD3EN_Msk          DBGMCU_CR_DBG_CKSRDEN_Msk
20522 #define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKSRDEN
20523 
20524 #define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)
20525 #define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */
20526 #define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk
20527 
20528 /********************  Bit definition for APB3FZ1 register  ************/
20529 #define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)
20530 #define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
20531 #define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk
20532 /********************  Bit definition for APB1LFZ1 register  ************/
20533 #define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)
20534 #define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
20535 #define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk
20536 #define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)
20537 #define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
20538 #define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk
20539 #define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)
20540 #define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
20541 #define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk
20542 #define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)
20543 #define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
20544 #define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk
20545 #define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)
20546 #define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
20547 #define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk
20548 #define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)
20549 #define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
20550 #define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk
20551 #define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)
20552 #define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
20553 #define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk
20554 #define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)
20555 #define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
20556 #define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk
20557 #define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)
20558 #define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
20559 #define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk
20560 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)
20561 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
20562 #define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
20563 #define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)
20564 #define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
20565 #define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk
20566 #define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)
20567 #define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
20568 #define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk
20569 #define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)
20570 #define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
20571 #define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk
20572 
20573 /********************  Bit definition for APB2FZ1 register  ************/
20574 #define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)
20575 #define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
20576 #define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk
20577 #define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)
20578 #define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
20579 #define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk
20580 #define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)
20581 #define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
20582 #define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk
20583 #define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)
20584 #define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
20585 #define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk
20586 #define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)
20587 #define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
20588 #define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk
20589 /********************  Bit definition for APB4FZ1 register  ************/
20590 #define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)
20591 #define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
20592 #define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk
20593 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)
20594 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
20595 #define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
20596 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)
20597 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
20598 #define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
20599 #define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)
20600 #define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
20601 #define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk
20602 #define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)
20603 #define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
20604 #define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk
20605 /******************************************************************************/
20606 /*                                                                            */
20607 /*                             RAM ECC monitoring                             */
20608 /*                                                                            */
20609 /******************************************************************************/
20610 /******************  Bit definition for RAMECC_IER register  ******************/
20611 #define RAMECC_IER_GECCDEBWIE_Pos         (3U)
20612 #define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */
20613 #define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */
20614 #define RAMECC_IER_GECCDEIE_Pos           (2U)
20615 #define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */
20616 #define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */
20617 #define RAMECC_IER_GECCSEIE_Pos           (1U)
20618 #define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */
20619 #define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */
20620 #define RAMECC_IER_GIE_Pos                (0U)
20621 #define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */
20622 #define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */
20623 
20624 /*******************  Bit definition for RAMECC_CR register  ******************/
20625 #define RAMECC_CR_ECCELEN_Pos             (5U)
20626 #define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */
20627 #define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */
20628 #define RAMECC_CR_ECCDEBWIE_Pos           (4U)
20629 #define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */
20630 #define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */
20631 #define RAMECC_CR_ECCDEIE_Pos             (3U)
20632 #define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */
20633 #define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */
20634 #define RAMECC_CR_ECCSEIE_Pos             (2U)
20635 #define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */
20636 #define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */
20637 
20638 /*******************  Bit definition for RAMECC_SR register  ******************/
20639 #define RAMECC_SR_DEBWDF_Pos             (2U)
20640 #define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */
20641 #define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */
20642 #define RAMECC_SR_DEDF_Pos               (1U)
20643 #define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */
20644 #define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */
20645 #define RAMECC_SR_SEDCF_Pos              (0U)
20646 #define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */
20647 #define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */
20648 
20649 /******************  Bit definition for RAMECC_FAR register  ******************/
20650 #define RAMECC_FAR_FADD_Pos              (0U)
20651 #define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */
20652 #define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */
20653 
20654 /******************  Bit definition for RAMECC_FDRL register  *****************/
20655 #define RAMECC_FAR_FDATAL_Pos            (0U)
20656 #define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
20657 #define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */
20658 
20659 /******************  Bit definition for RAMECC_FDRH register  *****************/
20660 #define RAMECC_FAR_FDATAH_Pos            (0U)
20661 #define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
20662 #define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */
20663 
20664 /*****************  Bit definition for RAMECC_FECR register  ******************/
20665 #define RAMECC_FECR_FEC_Pos              (0U)
20666 #define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */
20667 #define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */
20668 
20669 /******************************************************************************/
20670 /*                                                                            */
20671 /*                                MDIOS                                        */
20672 /*                                                                            */
20673 /******************************************************************************/
20674 /********************  Bit definition for MDIOS_CR register  *******************/
20675 #define MDIOS_CR_EN_Pos                (0U)
20676 #define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
20677 #define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
20678 #define MDIOS_CR_WRIE_Pos              (1U)
20679 #define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
20680 #define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
20681 #define MDIOS_CR_RDIE_Pos              (2U)
20682 #define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
20683 #define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
20684 #define MDIOS_CR_EIE_Pos               (3U)
20685 #define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
20686 #define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
20687 #define MDIOS_CR_DPC_Pos               (7U)
20688 #define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
20689 #define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
20690 #define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
20691 #define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
20692 #define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
20693 #define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
20694 #define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
20695 #define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
20696 #define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
20697 #define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
20698 
20699 /********************  Bit definition for MDIOS_SR register  *******************/
20700 #define MDIOS_SR_PERF_Pos              (0U)
20701 #define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
20702 #define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
20703 #define MDIOS_SR_SERF_Pos              (1U)
20704 #define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
20705 #define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
20706 #define MDIOS_SR_TERF_Pos              (2U)
20707 #define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
20708 #define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
20709 
20710 /********************  Bit definition for MDIOS_CLRFR register  *******************/
20711 #define MDIOS_SR_CPERF_Pos             (0U)
20712 #define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
20713 #define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
20714 #define MDIOS_SR_CSERF_Pos             (1U)
20715 #define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
20716 #define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
20717 #define MDIOS_SR_CTERF_Pos             (2U)
20718 #define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
20719 #define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
20720 
20721 /******************************************************************************/
20722 /*                                                                            */
20723 /*                                       USB_OTG                              */
20724 /*                                                                            */
20725 /******************************************************************************/
20726 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
20727 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
20728 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
20729 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
20730 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
20731 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
20732 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
20733 #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
20734 #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
20735 #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
20736 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
20737 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
20738 #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
20739 #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
20740 #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
20741 #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
20742 #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
20743 #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
20744 #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
20745 #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
20746 #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
20747 #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
20748 #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
20749 #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
20750 #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
20751 #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
20752 #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
20753 #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
20754 #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
20755 #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
20756 #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
20757 #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
20758 #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
20759 #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
20760 #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
20761 #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
20762 #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
20763 #define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
20764 #define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
20765 #define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
20766 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
20767 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
20768 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
20769 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
20770 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
20771 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
20772 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
20773 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
20774 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
20775 #define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
20776 #define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
20777 #define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
20778 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
20779 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
20780 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
20781 #define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
20782 #define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
20783 #define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
20784 
20785 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
20786 
20787 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
20788 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
20789 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
20790 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
20791 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
20792 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
20793 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
20794 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
20795 
20796 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
20797 
20798 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
20799 #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
20800 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
20801 #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
20802 #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
20803 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
20804 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
20805 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
20806 
20807 #define USB_OTG_DCFG_DAD_Pos                     (4U)
20808 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
20809 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
20810 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
20811 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
20812 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
20813 #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
20814 #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
20815 #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
20816 #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
20817 
20818 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
20819 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
20820 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
20821 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
20822 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
20823 
20824 #define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
20825 #define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
20826 #define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
20827 
20828 #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
20829 #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
20830 #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
20831 
20832 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
20833 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
20834 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
20835 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
20836 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
20837 
20838 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
20839 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
20840 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
20841 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
20842 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
20843 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
20844 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
20845 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
20846 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
20847 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
20848 
20849 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
20850 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
20851 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
20852 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
20853 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
20854 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
20855 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
20856 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
20857 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
20858 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
20859 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
20860 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
20861 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
20862 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
20863 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
20864 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
20865 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
20866 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
20867 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
20868 
20869 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
20870 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
20871 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
20872 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
20873 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
20874 #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
20875 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
20876 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
20877 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
20878 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
20879 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
20880 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
20881 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
20882 
20883 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
20884 #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
20885 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
20886 #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
20887 #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
20888 #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
20889 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
20890 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
20891 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
20892 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
20893 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
20894 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
20895 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
20896 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
20897 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
20898 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
20899 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
20900 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
20901 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
20902 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
20903 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
20904 #define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
20905 #define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
20906 #define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
20907 #define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
20908 #define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
20909 #define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
20910 
20911 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
20912 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
20913 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
20914 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
20915 
20916 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
20917 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
20918 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
20919 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
20920 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
20921 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
20922 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
20923 
20924 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
20925 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
20926 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
20927 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
20928 
20929 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
20930 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
20931 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
20932 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
20933 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
20934 #define USB_OTG_DSTS_EERR_Pos                    (3U)
20935 #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
20936 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
20937 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
20938 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
20939 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
20940 
20941 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
20942 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
20943 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
20944 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
20945 
20946 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
20947 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
20948 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
20949 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
20950 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
20951 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
20952 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
20953 #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
20954 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
20955 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
20956 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
20957 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
20958 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
20959 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
20960 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
20961 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
20962 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
20963 
20964 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
20965 
20966 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
20967 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
20968 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
20969 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
20970 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
20971 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
20972 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
20973 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
20974 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
20975 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
20976 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
20977 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
20978 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
20979 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
20980 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
20981 
20982 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
20983 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
20984 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
20985 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
20986 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
20987 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
20988 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
20989 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
20990 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
20991 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
20992 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
20993 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
20994 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
20995 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
20996 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
20997 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
20998 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
20999 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
21000 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
21001 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
21002 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
21003 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
21004 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
21005 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
21006 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
21007 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
21008 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
21009 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
21010 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
21011 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
21012 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
21013 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
21014 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
21015 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
21016 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
21017 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
21018 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
21019 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
21020 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
21021 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
21022 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
21023 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
21024 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
21025 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
21026 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
21027 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
21028 
21029 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
21030 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
21031 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
21032 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
21033 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
21034 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
21035 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
21036 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
21037 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
21038 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
21039 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
21040 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
21041 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
21042 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
21043 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
21044 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
21045 
21046 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
21047 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
21048 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
21049 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
21050 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
21051 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
21052 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
21053 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
21054 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
21055 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
21056 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
21057 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
21058 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
21059 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
21060 
21061 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
21062 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
21063 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
21064 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
21065 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
21066 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
21067 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
21068 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
21069 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
21070 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
21071 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
21072 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
21073 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
21074 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
21075 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
21076 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
21077 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
21078 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
21079 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
21080 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
21081 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
21082 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
21083 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
21084 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
21085 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
21086 
21087 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
21088 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
21089 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
21090 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
21091 
21092 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
21093 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
21094 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
21095 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
21096 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
21097 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
21098 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
21099 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
21100 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
21101 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
21102 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
21103 
21104 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
21105 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
21106 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
21107 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
21108 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
21109 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
21110 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
21111 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
21112 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
21113 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
21114 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
21115 
21116 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
21117 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
21118 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
21119 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
21120 
21121 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
21122 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
21123 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
21124 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
21125 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
21126 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
21127 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
21128 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
21129 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
21130 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
21131 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
21132 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
21133 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
21134 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
21135 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
21136 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
21137 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
21138 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
21139 #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
21140 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
21141 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
21142 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
21143 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
21144 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
21145 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
21146 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
21147 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
21148 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
21149 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
21150 #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
21151 #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
21152 #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
21153 #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
21154 #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
21155 #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
21156 #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
21157 #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
21158 
21159 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
21160 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
21161 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
21162 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
21163 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
21164 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
21165 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
21166 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
21167 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
21168 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
21169 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
21170 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
21171 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
21172 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
21173 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
21174 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
21175 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
21176 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
21177 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
21178 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
21179 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
21180 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
21181 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
21182 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
21183 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
21184 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
21185 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
21186 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
21187 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
21188 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
21189 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
21190 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
21191 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
21192 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
21193 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
21194 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
21195 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
21196 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
21197 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
21198 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
21199 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
21200 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
21201 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
21202 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
21203 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
21204 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
21205 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
21206 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
21207 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
21208 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
21209 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
21210 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
21211 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
21212 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
21213 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
21214 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
21215 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
21216 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
21217 #define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
21218 #define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
21219 #define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
21220 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
21221 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
21222 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
21223 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
21224 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
21225 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
21226 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
21227 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
21228 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
21229 #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
21230 #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
21231 #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
21232 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
21233 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
21234 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
21235 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
21236 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
21237 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
21238 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
21239 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
21240 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
21241 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
21242 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
21243 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
21244 
21245 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
21246 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
21247 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
21248 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
21249 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
21250 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
21251 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
21252 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
21253 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
21254 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
21255 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
21256 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
21257 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
21258 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
21259 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
21260 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
21261 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
21262 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
21263 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
21264 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
21265 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
21266 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
21267 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
21268 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
21269 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
21270 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
21271 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
21272 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
21273 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
21274 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
21275 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
21276 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
21277 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
21278 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
21279 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
21280 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
21281 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
21282 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
21283 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
21284 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
21285 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
21286 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
21287 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
21288 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
21289 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
21290 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
21291 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
21292 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
21293 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
21294 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
21295 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
21296 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
21297 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
21298 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
21299 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
21300 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
21301 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
21302 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
21303 #define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
21304 #define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
21305 #define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
21306 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
21307 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
21308 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
21309 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
21310 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
21311 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
21312 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
21313 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
21314 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
21315 #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
21316 #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
21317 #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
21318 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
21319 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
21320 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
21321 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
21322 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
21323 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
21324 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
21325 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
21326 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
21327 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
21328 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
21329 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
21330 
21331 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
21332 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
21333 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
21334 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
21335 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
21336 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
21337 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
21338 
21339 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
21340 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
21341 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
21342 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
21343 
21344 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
21345 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
21346 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
21347 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
21348 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
21349 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
21350 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
21351 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
21352 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
21353 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
21354 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
21355 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
21356 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
21357 
21358 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
21359 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
21360 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
21361 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
21362 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
21363 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
21364 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
21365 
21366 /********************  Bit definition for OTG register  ********************/
21367 
21368 #define USB_OTG_CHNUM_Pos                        (0U)
21369 #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
21370 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
21371 #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
21372 #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
21373 #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
21374 #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
21375 #define USB_OTG_BCNT_Pos                         (4U)
21376 #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
21377 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
21378 
21379 #define USB_OTG_DPID_Pos                         (15U)
21380 #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
21381 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
21382 #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
21383 #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
21384 
21385 #define USB_OTG_PKTSTS_Pos                       (17U)
21386 #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
21387 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
21388 #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
21389 #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
21390 #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
21391 #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
21392 
21393 #define USB_OTG_EPNUM_Pos                        (0U)
21394 #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
21395 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
21396 #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
21397 #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
21398 #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
21399 #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
21400 
21401 #define USB_OTG_FRMNUM_Pos                       (21U)
21402 #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
21403 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
21404 #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
21405 #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
21406 #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
21407 #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
21408 
21409 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
21410 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
21411 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
21412 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
21413 
21414 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
21415 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
21416 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
21417 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
21418 
21419 /********************  Bit definition for OTG register  ********************/
21420 #define USB_OTG_NPTXFSA_Pos                      (0U)
21421 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
21422 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
21423 #define USB_OTG_NPTXFD_Pos                       (16U)
21424 #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
21425 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
21426 #define USB_OTG_TX0FSA_Pos                       (0U)
21427 #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
21428 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
21429 #define USB_OTG_TX0FD_Pos                        (16U)
21430 #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
21431 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
21432 
21433 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
21434 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
21435 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
21436 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
21437 
21438 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
21439 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
21440 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
21441 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
21442 
21443 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
21444 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
21445 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
21446 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
21447 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
21448 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
21449 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
21450 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
21451 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
21452 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
21453 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
21454 
21455 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
21456 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
21457 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
21458 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
21459 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
21460 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
21461 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
21462 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
21463 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
21464 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
21465 
21466 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
21467 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
21468 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
21469 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
21470 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
21471 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
21472 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
21473 
21474 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
21475 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
21476 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
21477 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
21478 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
21479 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
21480 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
21481 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
21482 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
21483 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
21484 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
21485 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
21486 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
21487 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
21488 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
21489 
21490 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
21491 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
21492 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
21493 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
21494 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
21495 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
21496 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
21497 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
21498 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
21499 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
21500 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
21501 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
21502 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
21503 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
21504 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
21505 
21506 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
21507 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
21508 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
21509 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
21510 
21511 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
21512 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
21513 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
21514 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
21515 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
21516 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
21517 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
21518 
21519 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
21520 #define USB_OTG_GCCFG_DCDET_Pos                  (0U)
21521 #define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
21522 #define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
21523 #define USB_OTG_GCCFG_PDET_Pos                   (1U)
21524 #define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
21525 #define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
21526 #define USB_OTG_GCCFG_SDET_Pos                   (2U)
21527 #define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
21528 #define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
21529 #define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
21530 #define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
21531 #define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
21532 #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
21533 #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
21534 #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
21535 #define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
21536 #define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
21537 #define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
21538 #define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
21539 #define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
21540 #define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
21541 #define USB_OTG_GCCFG_PDEN_Pos                   (19U)
21542 #define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
21543 #define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
21544 #define USB_OTG_GCCFG_SDEN_Pos                   (20U)
21545 #define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
21546 #define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
21547 #define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
21548 #define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
21549 #define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
21550 
21551 /********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/
21552 #define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
21553 #define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
21554 #define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
21555 #define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
21556 #define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
21557 #define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
21558 
21559 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
21560 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
21561 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
21562 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
21563 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
21564 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
21565 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
21566 
21567 /********************  Bit definition forUSB_OTG_CID register  ********************/
21568 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
21569 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
21570 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
21571 
21572 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
21573 #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
21574 #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
21575 #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
21576 #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
21577 #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
21578 #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
21579 #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
21580 #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
21581 #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
21582 #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
21583 #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
21584 #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
21585 #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
21586 #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
21587 #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
21588 #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
21589 #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
21590 #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
21591 #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
21592 #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
21593 #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
21594 #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
21595 #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
21596 #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
21597 #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
21598 #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
21599 #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
21600 #define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
21601 #define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
21602 #define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
21603 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
21604 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
21605 #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
21606 #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
21607 #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
21608 #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
21609 #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
21610 #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
21611 #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
21612 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
21613 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
21614 #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
21615 #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
21616 #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
21617 #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
21618 
21619 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
21620 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
21621 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
21622 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
21623 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
21624 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
21625 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
21626 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
21627 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
21628 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
21629 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
21630 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
21631 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
21632 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
21633 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
21634 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
21635 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
21636 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
21637 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
21638 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
21639 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
21640 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
21641 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
21642 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
21643 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
21644 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
21645 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
21646 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
21647 
21648 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
21649 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
21650 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
21651 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
21652 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
21653 #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
21654 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
21655 #define USB_OTG_HPRT_PENA_Pos                    (2U)
21656 #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
21657 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
21658 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
21659 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
21660 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
21661 #define USB_OTG_HPRT_POCA_Pos                    (4U)
21662 #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
21663 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
21664 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
21665 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
21666 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
21667 #define USB_OTG_HPRT_PRES_Pos                    (6U)
21668 #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
21669 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
21670 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
21671 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
21672 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
21673 #define USB_OTG_HPRT_PRST_Pos                    (8U)
21674 #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
21675 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
21676 
21677 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
21678 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
21679 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
21680 #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
21681 #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
21682 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
21683 #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
21684 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
21685 
21686 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
21687 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
21688 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
21689 #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
21690 #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
21691 #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
21692 #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
21693 
21694 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
21695 #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
21696 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
21697 #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
21698 #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
21699 
21700 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
21701 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
21702 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
21703 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
21704 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
21705 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
21706 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
21707 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
21708 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
21709 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
21710 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
21711 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
21712 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
21713 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
21714 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
21715 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
21716 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
21717 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
21718 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
21719 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
21720 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
21721 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
21722 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
21723 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
21724 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
21725 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
21726 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
21727 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
21728 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
21729 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
21730 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
21731 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
21732 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
21733 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
21734 
21735 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
21736 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
21737 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
21738 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
21739 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
21740 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
21741 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
21742 
21743 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
21744 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
21745 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
21746 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
21747 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
21748 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
21749 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
21750 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
21751 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
21752 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
21753 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
21754 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
21755 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
21756 
21757 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
21758 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
21759 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
21760 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
21761 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
21762 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
21763 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
21764 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
21765 
21766 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
21767 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
21768 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
21769 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
21770 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
21771 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
21772 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
21773 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
21774 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
21775 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
21776 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
21777 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
21778 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
21779 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
21780 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
21781 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
21782 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
21783 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
21784 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
21785 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
21786 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
21787 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
21788 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
21789 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
21790 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
21791 
21792 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
21793 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
21794 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
21795 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
21796 
21797 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
21798 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
21799 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
21800 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
21801 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
21802 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
21803 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
21804 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
21805 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
21806 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
21807 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
21808 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
21809 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
21810 
21811 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
21812 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
21813 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
21814 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
21815 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
21816 
21817 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
21818 #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
21819 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
21820 #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
21821 #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
21822 
21823 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
21824 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
21825 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
21826 #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
21827 #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
21828 #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
21829 #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
21830 #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
21831 #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
21832 #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
21833 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
21834 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
21835 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
21836 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
21837 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
21838 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
21839 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
21840 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
21841 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
21842 
21843 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
21844 
21845 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
21846 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
21847 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
21848 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
21849 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
21850 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
21851 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
21852 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
21853 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
21854 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
21855 
21856 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
21857 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
21858 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
21859 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
21860 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
21861 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
21862 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
21863 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
21864 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
21865 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
21866 
21867 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
21868 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
21869 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
21870 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
21871 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
21872 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
21873 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
21874 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
21875 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
21876 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
21877 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
21878 
21879 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
21880 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
21881 #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
21882 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
21883 #define USB_OTG_HCINT_CHH_Pos                    (1U)
21884 #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
21885 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
21886 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
21887 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
21888 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
21889 #define USB_OTG_HCINT_STALL_Pos                  (3U)
21890 #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
21891 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
21892 #define USB_OTG_HCINT_NAK_Pos                    (4U)
21893 #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
21894 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
21895 #define USB_OTG_HCINT_ACK_Pos                    (5U)
21896 #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
21897 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
21898 #define USB_OTG_HCINT_NYET_Pos                   (6U)
21899 #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
21900 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
21901 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
21902 #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
21903 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
21904 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
21905 #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
21906 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
21907 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
21908 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
21909 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
21910 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
21911 #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
21912 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
21913 
21914 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
21915 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
21916 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
21917 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
21918 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
21919 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
21920 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
21921 #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
21922 #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
21923 #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
21924 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
21925 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
21926 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
21927 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
21928 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
21929 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
21930 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
21931 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
21932 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
21933 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
21934 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
21935 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
21936 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
21937 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
21938 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
21939 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
21940 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
21941 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
21942 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
21943 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
21944 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
21945 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
21946 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
21947 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
21948 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
21949 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
21950 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
21951 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
21952 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
21953 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
21954 
21955 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
21956 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
21957 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
21958 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
21959 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
21960 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
21961 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
21962 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
21963 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
21964 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
21965 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
21966 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
21967 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
21968 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
21969 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
21970 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
21971 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
21972 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
21973 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
21974 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
21975 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
21976 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
21977 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
21978 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
21979 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
21980 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
21981 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
21982 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
21983 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
21984 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
21985 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
21986 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
21987 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
21988 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
21989 
21990 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
21991 
21992 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
21993 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
21994 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
21995 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
21996 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
21997 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
21998 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
21999 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
22000 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
22001 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
22002 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
22003 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
22004 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
22005 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
22006 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
22007 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
22008 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
22009 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
22010 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
22011 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
22012 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
22013 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
22014 #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
22015 #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
22016 
22017 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
22018 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
22019 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
22020 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
22021 
22022 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
22023 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
22024 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
22025 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
22026 
22027 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
22028 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
22029 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
22030 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
22031 
22032 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
22033 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
22034 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
22035 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
22036 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
22037 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
22038 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
22039 
22040 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
22041 
22042 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
22043 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
22044 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
22045 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
22046 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
22047 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
22048 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
22049 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
22050 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
22051 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
22052 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
22053 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
22054 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
22055 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
22056 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
22057 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
22058 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
22059 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
22060 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
22061 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
22062 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
22063 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
22064 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
22065 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
22066 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
22067 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
22068 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
22069 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
22070 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
22071 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
22072 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
22073 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
22074 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
22075 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
22076 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
22077 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
22078 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
22079 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
22080 
22081 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
22082 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
22083 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
22084 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
22085 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
22086 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
22087 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
22088 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
22089 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
22090 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
22091 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
22092 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
22093 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
22094 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
22095 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
22096 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
22097 #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
22098 #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
22099 #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
22100 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
22101 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
22102 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
22103 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
22104 #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
22105 #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
22106 #define USB_OTG_DOEPINT_BNA_Pos                  (9U)
22107 #define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */
22108 #define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */
22109 #define USB_OTG_DOEPINT_BERR_Pos                 (12U)
22110 #define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
22111 #define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
22112 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
22113 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
22114 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
22115 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
22116 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
22117 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
22118 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
22119 #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
22120 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
22121 
22122 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
22123 
22124 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
22125 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
22126 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
22127 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
22128 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
22129 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
22130 
22131 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
22132 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
22133 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
22134 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
22135 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
22136 
22137 /********************  Bit definition for PCGCCTL register  ********************/
22138 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
22139 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
22140 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
22141 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
22142 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
22143 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
22144 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
22145 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
22146 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
22147 
22148 /**
22149   * @}
22150   */
22151 
22152 /**
22153   * @}
22154   */
22155 
22156 /** @addtogroup Exported_macros
22157   * @{
22158   */
22159 
22160 /******************************* ADC Instances ********************************/
22161 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
22162                                        ((INSTANCE) == ADC2))
22163 
22164 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
22165 
22166 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
22167 
22168 /******************************** COMP Instances ******************************/
22169 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
22170                                        ((INSTANCE) == COMP2))
22171 
22172 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
22173 /******************** COMP Instances with window mode capability **************/
22174 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
22175 
22176 /******************************** DTS Instances ******************************/
22177 #define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)
22178 
22179 /******************************* CRC Instances ********************************/
22180 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
22181 
22182 /******************************* DAC Instances ********************************/
22183 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \
22184                                        ((INSTANCE) == DAC2))
22185 /******************************* DCMI Instances *******************************/
22186 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
22187 
22188 /******************************* DELAYBLOCK Instances *******************************/
22189 #define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \
22190                                          ((INSTANCE) == DLYB_SDMMC2) || \
22191                                          ((INSTANCE) == DLYB_OCTOSPI1) || \
22192                                          ((INSTANCE) == DLYB_OCTOSPI2) )
22193 /****************************** DFSDM Instances *******************************/
22194 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
22195                                          ((INSTANCE) == DFSDM1_Filter1) || \
22196                                          ((INSTANCE) == DFSDM1_Filter2) || \
22197                                          ((INSTANCE) == DFSDM1_Filter3) || \
22198                                          ((INSTANCE) == DFSDM1_Filter4) || \
22199                                          ((INSTANCE) == DFSDM1_Filter5) || \
22200                                          ((INSTANCE) == DFSDM1_Filter6) || \
22201                                          ((INSTANCE) == DFSDM1_Filter7) || \
22202                                          ((INSTANCE) == DFSDM2_Filter0))
22203 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
22204                                                  ((INSTANCE) == DFSDM1_Channel1) || \
22205                                                  ((INSTANCE) == DFSDM1_Channel2) || \
22206                                                  ((INSTANCE) == DFSDM1_Channel3) || \
22207                                                  ((INSTANCE) == DFSDM1_Channel4) || \
22208                                                  ((INSTANCE) == DFSDM1_Channel5) || \
22209                                                  ((INSTANCE) == DFSDM1_Channel6) || \
22210                                                  ((INSTANCE) == DFSDM1_Channel7) || \
22211                                                  ((INSTANCE) == DFSDM2_Channel0) || \
22212                                                  ((INSTANCE) == DFSDM2_Channel1))
22213 /****************************** RAMECC Instances ******************************/
22214 #define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1)   || \
22215                                                   ((INSTANCE) == RAMECC_Monitor2)   || \
22216                                                   ((INSTANCE) == RAMECC_Monitor3))
22217 
22218 /******************************** DMA Instances *******************************/
22219 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
22220                                        ((INSTANCE) == DMA1_Stream1)   || \
22221                                        ((INSTANCE) == DMA1_Stream2)   || \
22222                                        ((INSTANCE) == DMA1_Stream3)   || \
22223                                        ((INSTANCE) == DMA1_Stream4)   || \
22224                                        ((INSTANCE) == DMA1_Stream5)   || \
22225                                        ((INSTANCE) == DMA1_Stream6)   || \
22226                                        ((INSTANCE) == DMA1_Stream7)   || \
22227                                        ((INSTANCE) == DMA2_Stream0)   || \
22228                                        ((INSTANCE) == DMA2_Stream1)   || \
22229                                        ((INSTANCE) == DMA2_Stream2)   || \
22230                                        ((INSTANCE) == DMA2_Stream3)   || \
22231                                        ((INSTANCE) == DMA2_Stream4)   || \
22232                                        ((INSTANCE) == DMA2_Stream5)   || \
22233                                        ((INSTANCE) == DMA2_Stream6)   || \
22234                                        ((INSTANCE) == DMA2_Stream7)   || \
22235                                        ((INSTANCE) == BDMA1_Channel0) || \
22236                                        ((INSTANCE) == BDMA1_Channel1) || \
22237                                        ((INSTANCE) == BDMA1_Channel2) || \
22238                                        ((INSTANCE) == BDMA1_Channel3) || \
22239                                        ((INSTANCE) == BDMA1_Channel4) || \
22240                                        ((INSTANCE) == BDMA1_Channel5) || \
22241                                        ((INSTANCE) == BDMA1_Channel6) || \
22242                                        ((INSTANCE) == BDMA1_Channel7) || \
22243                                        ((INSTANCE) == BDMA2_Channel0) || \
22244                                        ((INSTANCE) == BDMA2_Channel1) || \
22245                                        ((INSTANCE) == BDMA2_Channel2) || \
22246                                        ((INSTANCE) == BDMA2_Channel3) || \
22247                                        ((INSTANCE) == BDMA2_Channel4) || \
22248                                        ((INSTANCE) == BDMA2_Channel5) || \
22249                                        ((INSTANCE) == BDMA2_Channel6) || \
22250                                        ((INSTANCE) == BDMA2_Channel7))
22251 
22252 /****************************** BDMA CHANNEL Instances ***************************/
22253 #define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \
22254                                             ((INSTANCE) == BDMA1_Channel1) || \
22255                                             ((INSTANCE) == BDMA1_Channel2) || \
22256                                             ((INSTANCE) == BDMA1_Channel3) || \
22257                                             ((INSTANCE) == BDMA1_Channel4) || \
22258                                             ((INSTANCE) == BDMA1_Channel5) || \
22259                                             ((INSTANCE) == BDMA1_Channel6) || \
22260                                             ((INSTANCE) == BDMA1_Channel7) || \
22261                                             ((INSTANCE) == BDMA2_Channel0) || \
22262                                             ((INSTANCE) == BDMA2_Channel1) || \
22263                                             ((INSTANCE) == BDMA2_Channel2) || \
22264                                             ((INSTANCE) == BDMA2_Channel3) || \
22265                                             ((INSTANCE) == BDMA2_Channel4) || \
22266                                             ((INSTANCE) == BDMA2_Channel5) || \
22267                                             ((INSTANCE) == BDMA2_Channel6) || \
22268                                             ((INSTANCE) == BDMA2_Channel7))
22269 
22270 /****************************** DMA DMAMUX ALL Instances ***************************/
22271 #define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \
22272                                                ((INSTANCE) == DMA1_Stream1)    || \
22273                                                ((INSTANCE) == DMA1_Stream2)    || \
22274                                                ((INSTANCE) == DMA1_Stream3)    || \
22275                                                ((INSTANCE) == DMA1_Stream4)    || \
22276                                                ((INSTANCE) == DMA1_Stream5)    || \
22277                                                ((INSTANCE) == DMA1_Stream6)    || \
22278                                                ((INSTANCE) == DMA1_Stream7)    || \
22279                                                ((INSTANCE) == DMA2_Stream0)    || \
22280                                                ((INSTANCE) == DMA2_Stream1)    || \
22281                                                ((INSTANCE) == DMA2_Stream2)    || \
22282                                                ((INSTANCE) == DMA2_Stream3)    || \
22283                                                ((INSTANCE) == DMA2_Stream4)    || \
22284                                                ((INSTANCE) == DMA2_Stream5)    || \
22285                                                ((INSTANCE) == DMA2_Stream6)    || \
22286                                                ((INSTANCE) == DMA2_Stream7)    || \
22287                                                ((INSTANCE) == BDMA2_Channel0)  || \
22288                                                ((INSTANCE) == BDMA2_Channel1)  || \
22289                                                ((INSTANCE) == BDMA2_Channel2)  || \
22290                                                ((INSTANCE) == BDMA2_Channel3)  || \
22291                                                ((INSTANCE) == BDMA2_Channel4)  || \
22292                                                ((INSTANCE) == BDMA2_Channel5)  || \
22293                                                ((INSTANCE) == BDMA2_Channel6)  || \
22294                                                ((INSTANCE) == BDMA2_Channel7))
22295 
22296 /****************************** BDMA DMAMUX Instances ***************************/
22297 #define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA2_Channel0) || \
22298                                                     ((INSTANCE) == BDMA2_Channel1) || \
22299                                                     ((INSTANCE) == BDMA2_Channel2) || \
22300                                                     ((INSTANCE) == BDMA2_Channel3) || \
22301                                                     ((INSTANCE) == BDMA2_Channel4) || \
22302                                                     ((INSTANCE) == BDMA2_Channel5) || \
22303                                                     ((INSTANCE) == BDMA2_Channel6) || \
22304                                                     ((INSTANCE) == BDMA2_Channel7))
22305 
22306 /****************************** DMA STREAM Instances ***************************/
22307 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
22308                                           ((INSTANCE) == DMA1_Stream1)   || \
22309                                           ((INSTANCE) == DMA1_Stream2)   || \
22310                                           ((INSTANCE) == DMA1_Stream3)   || \
22311                                           ((INSTANCE) == DMA1_Stream4)   || \
22312                                           ((INSTANCE) == DMA1_Stream5)   || \
22313                                           ((INSTANCE) == DMA1_Stream6)   || \
22314                                           ((INSTANCE) == DMA1_Stream7)   || \
22315                                           ((INSTANCE) == DMA2_Stream0)   || \
22316                                           ((INSTANCE) == DMA2_Stream1)   || \
22317                                           ((INSTANCE) == DMA2_Stream2)   || \
22318                                           ((INSTANCE) == DMA2_Stream3)   || \
22319                                           ((INSTANCE) == DMA2_Stream4)   || \
22320                                           ((INSTANCE) == DMA2_Stream5)   || \
22321                                           ((INSTANCE) == DMA2_Stream6)   || \
22322                                           ((INSTANCE) == DMA2_Stream7))
22323 
22324 /****************************** DMA DMAMUX Instances ***************************/
22325 #define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \
22326                                                   ((INSTANCE) == DMA1_Stream1)   || \
22327                                                   ((INSTANCE) == DMA1_Stream2)   || \
22328                                                   ((INSTANCE) == DMA1_Stream3)   || \
22329                                                   ((INSTANCE) == DMA1_Stream4)   || \
22330                                                   ((INSTANCE) == DMA1_Stream5)   || \
22331                                                   ((INSTANCE) == DMA1_Stream6)   || \
22332                                                   ((INSTANCE) == DMA1_Stream7)   || \
22333                                                   ((INSTANCE) == DMA2_Stream0)   || \
22334                                                   ((INSTANCE) == DMA2_Stream1)   || \
22335                                                   ((INSTANCE) == DMA2_Stream2)   || \
22336                                                   ((INSTANCE) == DMA2_Stream3)   || \
22337                                                   ((INSTANCE) == DMA2_Stream4)   || \
22338                                                   ((INSTANCE) == DMA2_Stream5)   || \
22339                                                   ((INSTANCE) == DMA2_Stream6)   || \
22340                                                   ((INSTANCE) == DMA2_Stream7))
22341 
22342 /******************************** DMA Request Generator Instances **************/
22343 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
22344                                                    ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
22345                                                    ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
22346                                                    ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
22347                                                    ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
22348                                                    ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
22349                                                    ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
22350                                                    ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
22351                                                    ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
22352                                                    ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
22353                                                    ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
22354                                                    ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
22355                                                    ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
22356                                                    ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
22357                                                    ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
22358                                                    ((INSTANCE) == DMAMUX2_RequestGenerator7))
22359 
22360 /******************************* DMA2D Instances *******************************/
22361 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
22362 
22363 /******************************* OTFDEC Instances ******************************/
22364 #define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \
22365                                               ((__INSTANCE__) == OTFDEC2))
22366 
22367 /****************************** PSSI Instance *********************************/
22368 #define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)
22369 
22370 /******************************** MDMA Request Generator Instances **************/
22371 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \
22372                                                ((INSTANCE) == MDMA_Channel1)  || \
22373                                                ((INSTANCE) == MDMA_Channel2)  || \
22374                                                ((INSTANCE) == MDMA_Channel3)  || \
22375                                                ((INSTANCE) == MDMA_Channel4)  || \
22376                                                ((INSTANCE) == MDMA_Channel5)  || \
22377                                                ((INSTANCE) == MDMA_Channel6)  || \
22378                                                ((INSTANCE) == MDMA_Channel7)  || \
22379                                                ((INSTANCE) == MDMA_Channel8)  || \
22380                                                ((INSTANCE) == MDMA_Channel9)  || \
22381                                                ((INSTANCE) == MDMA_Channel10) || \
22382                                                ((INSTANCE) == MDMA_Channel11) || \
22383                                                ((INSTANCE) == MDMA_Channel12) || \
22384                                                ((INSTANCE) == MDMA_Channel13) || \
22385                                                ((INSTANCE) == MDMA_Channel14) || \
22386                                                ((INSTANCE) == MDMA_Channel15))
22387 
22388 
22389 /******************************* FDCAN Instances ******************************/
22390 #define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
22391                                              ((__INSTANCE__) == FDCAN2))
22392 
22393 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
22394 
22395 /******************************* GFXMMU Instances *******************************/
22396 #define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)
22397 
22398 /******************************* GPIO Instances *******************************/
22399 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
22400                                         ((INSTANCE) == GPIOB) || \
22401                                         ((INSTANCE) == GPIOC) || \
22402                                         ((INSTANCE) == GPIOD) || \
22403                                         ((INSTANCE) == GPIOE) || \
22404                                         ((INSTANCE) == GPIOF) || \
22405                                         ((INSTANCE) == GPIOG) || \
22406                                         ((INSTANCE) == GPIOH) || \
22407                                         ((INSTANCE) == GPIOI) || \
22408                                         ((INSTANCE) == GPIOJ) || \
22409                                         ((INSTANCE) == GPIOK))
22410 
22411 /******************************* GPIO AF Instances ****************************/
22412 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
22413 
22414 /**************************** GPIO Lock Instances *****************************/
22415 /* On H7, all GPIO Bank support the Lock mechanism */
22416 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
22417 
22418 /******************************** HSEM Instances *******************************/
22419 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
22420 #define HSEM_CPU1_COREID         (0x00000001U) /* Semaphore Core CM7 ID */
22421 #define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
22422 #define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
22423 
22424 #define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
22425 #define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */
22426 
22427 #define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
22428 #define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
22429 
22430 #define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
22431 #define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
22432 
22433 /******************************** I2C Instances *******************************/
22434 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
22435                                        ((INSTANCE) == I2C2) || \
22436                                        ((INSTANCE) == I2C3) || \
22437                                        ((INSTANCE) == I2C4))
22438 
22439 /****************************** SMBUS Instances *******************************/
22440 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
22441                                          ((INSTANCE) == I2C2) || \
22442                                          ((INSTANCE) == I2C3) || \
22443                                          ((INSTANCE) == I2C4))
22444 
22445 /************** I2C Instances : wakeup capability from stop modes *************/
22446 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
22447 
22448 /******************************** I2S Instances *******************************/
22449 #define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
22450                                          ((INSTANCE) == SPI2) || \
22451                                          ((INSTANCE) == SPI3) || \
22452                                          ((INSTANCE) == SPI6))
22453 
22454 /****************************** LTDC Instances ********************************/
22455 #define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
22456 
22457 /******************************* RNG Instances ********************************/
22458 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
22459 
22460 /****************************** RTC Instances *********************************/
22461 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
22462 
22463 /****************************** SDMMC Instances *********************************/
22464 #define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
22465                                            ((_INSTANCE_) == SDMMC2))
22466 
22467 /******************************** SPI Instances *******************************/
22468 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
22469                                        ((INSTANCE) == SPI2) || \
22470                                        ((INSTANCE) == SPI3) || \
22471                                        ((INSTANCE) == SPI4) || \
22472                                        ((INSTANCE) == SPI5) || \
22473                                        ((INSTANCE) == SPI6))
22474 
22475 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
22476                                            ((INSTANCE) == SPI2) || \
22477                                            ((INSTANCE) == SPI3))
22478 
22479 /******************************** SWPMI Instances *****************************/
22480 #define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
22481 
22482 /****************** LPTIM Instances : All supported instances *****************/
22483 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
22484                                          ((INSTANCE) == LPTIM2) || \
22485                                          ((INSTANCE) == LPTIM3))
22486 
22487 /****************** LPTIM Instances : supporting encoder interface **************/
22488 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
22489                                                            ((INSTANCE) == LPTIM2))
22490 
22491 /****************** TIM Instances : All supported instances *******************/
22492 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
22493                                          ((INSTANCE) == TIM2)   || \
22494                                          ((INSTANCE) == TIM3)   || \
22495                                          ((INSTANCE) == TIM4)   || \
22496                                          ((INSTANCE) == TIM5)   || \
22497                                          ((INSTANCE) == TIM6)   || \
22498                                          ((INSTANCE) == TIM7)   || \
22499                                          ((INSTANCE) == TIM8)   || \
22500                                          ((INSTANCE) == TIM12)  || \
22501                                          ((INSTANCE) == TIM13)  || \
22502                                          ((INSTANCE) == TIM14)  || \
22503                                          ((INSTANCE) == TIM15)  || \
22504                                          ((INSTANCE) == TIM16)  || \
22505                                          ((INSTANCE) == TIM17))
22506 
22507 /************* TIM Instances : at least 1 capture/compare channel *************/
22508 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22509                                          ((INSTANCE) == TIM2)   || \
22510                                          ((INSTANCE) == TIM3)   || \
22511                                          ((INSTANCE) == TIM4)   || \
22512                                          ((INSTANCE) == TIM5)   || \
22513                                          ((INSTANCE) == TIM8)   || \
22514                                          ((INSTANCE) == TIM12)  || \
22515                                          ((INSTANCE) == TIM13)  || \
22516                                          ((INSTANCE) == TIM14)  || \
22517                                          ((INSTANCE) == TIM15)  || \
22518                                          ((INSTANCE) == TIM16)  || \
22519                                          ((INSTANCE) == TIM17))
22520 
22521 /************ TIM Instances : at least 2 capture/compare channels *************/
22522 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22523                                          ((INSTANCE) == TIM2)   || \
22524                                          ((INSTANCE) == TIM3)   || \
22525                                          ((INSTANCE) == TIM4)   || \
22526                                          ((INSTANCE) == TIM5)   || \
22527                                          ((INSTANCE) == TIM8)   || \
22528                                          ((INSTANCE) == TIM12)  || \
22529                                          ((INSTANCE) == TIM15))
22530 
22531 /************ TIM Instances : at least 3 capture/compare channels *************/
22532 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22533                                          ((INSTANCE) == TIM2)   || \
22534                                          ((INSTANCE) == TIM3)   || \
22535                                          ((INSTANCE) == TIM4)   || \
22536                                          ((INSTANCE) == TIM5)   || \
22537                                          ((INSTANCE) == TIM8))
22538 
22539 /************ TIM Instances : at least 4 capture/compare channels *************/
22540 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22541                                          ((INSTANCE) == TIM2)   || \
22542                                          ((INSTANCE) == TIM3)   || \
22543                                          ((INSTANCE) == TIM4)   || \
22544                                          ((INSTANCE) == TIM5)   || \
22545                                          ((INSTANCE) == TIM8))
22546 
22547 /************ TIM Instances : at least 5 capture/compare channels *************/
22548 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22549                                          ((INSTANCE) == TIM8))
22550 /************ TIM Instances : at least 6 capture/compare channels *************/
22551 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22552                                          ((INSTANCE) == TIM8))
22553 
22554 /******************** TIM Instances : Advanced-control timers *****************/
22555 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22556                                                 ((__INSTANCE__) == TIM8))
22557 
22558 /******************** TIM Instances : Advanced-control timers *****************/
22559 
22560 /******************* TIM Instances : Timer input XOR function *****************/
22561 #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22562                                          ((INSTANCE) == TIM2)   || \
22563                                          ((INSTANCE) == TIM3)   || \
22564                                          ((INSTANCE) == TIM4)   || \
22565                                          ((INSTANCE) == TIM5)   || \
22566                                          ((INSTANCE) == TIM8)   || \
22567                                          ((INSTANCE) == TIM15))
22568 
22569 /****************** TIM Instances : DMA requests generation (UDE) *************/
22570 #define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
22571                                            ((INSTANCE) == TIM2)   || \
22572                                            ((INSTANCE) == TIM3)   || \
22573                                            ((INSTANCE) == TIM4)   || \
22574                                            ((INSTANCE) == TIM5)   || \
22575                                            ((INSTANCE) == TIM6)   || \
22576                                            ((INSTANCE) == TIM7)   || \
22577                                            ((INSTANCE) == TIM8)   || \
22578                                            ((INSTANCE) == TIM15)  || \
22579                                            ((INSTANCE) == TIM16)  || \
22580                                            ((INSTANCE) == TIM17))
22581 
22582 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
22583 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22584                                             ((INSTANCE) == TIM2)   || \
22585                                             ((INSTANCE) == TIM3)   || \
22586                                             ((INSTANCE) == TIM4)   || \
22587                                             ((INSTANCE) == TIM5)   || \
22588                                             ((INSTANCE) == TIM8)   || \
22589                                             ((INSTANCE) == TIM15)  || \
22590                                             ((INSTANCE) == TIM16)  || \
22591                                             ((INSTANCE) == TIM17))
22592 
22593 /************ TIM Instances : DMA requests generation (COMDE) *****************/
22594 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
22595                                             ((INSTANCE) == TIM2)   || \
22596                                             ((INSTANCE) == TIM3)   || \
22597                                             ((INSTANCE) == TIM4)   || \
22598                                             ((INSTANCE) == TIM5)   || \
22599                                             ((INSTANCE) == TIM8)   || \
22600                                             ((INSTANCE) == TIM15))
22601 
22602 /******************** TIM Instances : DMA burst feature ***********************/
22603 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
22604                                             ((INSTANCE) == TIM2)   || \
22605                                             ((INSTANCE) == TIM3)   || \
22606                                             ((INSTANCE) == TIM4)   || \
22607                                             ((INSTANCE) == TIM5)   || \
22608                                             ((INSTANCE) == TIM8))
22609 
22610 /*************** TIM Instances : external trigger reamp input available *******/
22611 #define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
22612                                            ((INSTANCE) == TIM2)   || \
22613                                            ((INSTANCE) == TIM3)   || \
22614                                            ((INSTANCE) == TIM4)   || \
22615                                            ((INSTANCE) == TIM5)   || \
22616                                            ((INSTANCE) == TIM8))
22617 
22618 /****************** TIM Instances : remapping capability **********************/
22619 #define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
22620                                           ((INSTANCE) == TIM2)  || \
22621                                           ((INSTANCE) == TIM3)  || \
22622                                           ((INSTANCE) == TIM5)  || \
22623                                           ((INSTANCE) == TIM8)  || \
22624                                           ((INSTANCE) == TIM16) || \
22625                                           ((INSTANCE) == TIM17))
22626 
22627 /*************** TIM Instances : external trigger reamp input available *******/
22628 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
22629                                               ((INSTANCE) == TIM2)   || \
22630                                               ((INSTANCE) == TIM3)   || \
22631                                               ((INSTANCE) == TIM5)   || \
22632                                               ((INSTANCE) == TIM8))
22633 
22634 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
22635 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22636                                             ((INSTANCE) == TIM2)   || \
22637                                             ((INSTANCE) == TIM3)   || \
22638                                             ((INSTANCE) == TIM4)   || \
22639                                             ((INSTANCE) == TIM5)   || \
22640                                             ((INSTANCE) == TIM6)   || \
22641                                             ((INSTANCE) == TIM7)   || \
22642                                             ((INSTANCE) == TIM8)   || \
22643                                             ((INSTANCE) == TIM12)  || \
22644                                             ((INSTANCE) == TIM15))
22645 
22646 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
22647 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22648                                            ((INSTANCE) == TIM2)   || \
22649                                            ((INSTANCE) == TIM3)   || \
22650                                            ((INSTANCE) == TIM4)   || \
22651                                            ((INSTANCE) == TIM5)   || \
22652                                            ((INSTANCE) == TIM8)   || \
22653                                            ((INSTANCE) == TIM12)  || \
22654                                            ((INSTANCE) == TIM15))
22655 
22656 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
22657 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22658                                            ((INSTANCE) == TIM8))
22659 
22660 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
22661 #define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
22662                                           ((INSTANCE) == TIM2)   || \
22663                                           ((INSTANCE) == TIM3)   || \
22664                                           ((INSTANCE) == TIM4)   || \
22665                                           ((INSTANCE) == TIM5)   || \
22666                                           ((INSTANCE) == TIM8)   || \
22667                                           ((INSTANCE) == TIM15)  || \
22668                                           ((INSTANCE) == TIM16)  || \
22669                                           ((INSTANCE) == TIM17))
22670 
22671 /****************** TIM Instances : supporting commutation event *************/
22672 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
22673                                                      ((INSTANCE) == TIM8)    || \
22674                                                      ((INSTANCE) == TIM15)   || \
22675                                                      ((INSTANCE) == TIM16)   || \
22676                                                      ((INSTANCE) == TIM17))
22677 
22678 /****************** TIM Instances : supporting encoder interface **************/
22679 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
22680                                                       ((__INSTANCE__) == TIM2)      || \
22681                                                       ((__INSTANCE__) == TIM3)      || \
22682                                                       ((__INSTANCE__) == TIM4)      || \
22683                                                       ((__INSTANCE__) == TIM5)      || \
22684                                                       ((__INSTANCE__) == TIM8))
22685 
22686 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
22687 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
22688                                                        ((INSTANCE) == TIM8))
22689 /******************* TIM Instances : output(s) available **********************/
22690 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
22691     ((((INSTANCE) == TIM1) &&                  \
22692      (((CHANNEL) == TIM_CHANNEL_1) ||          \
22693       ((CHANNEL) == TIM_CHANNEL_2) ||          \
22694       ((CHANNEL) == TIM_CHANNEL_3) ||          \
22695       ((CHANNEL) == TIM_CHANNEL_4) ||          \
22696       ((CHANNEL) == TIM_CHANNEL_5) ||          \
22697       ((CHANNEL) == TIM_CHANNEL_6)))           \
22698      ||                                        \
22699      (((INSTANCE) == TIM2) &&                  \
22700      (((CHANNEL) == TIM_CHANNEL_1) ||          \
22701       ((CHANNEL) == TIM_CHANNEL_2) ||          \
22702       ((CHANNEL) == TIM_CHANNEL_3) ||          \
22703       ((CHANNEL) == TIM_CHANNEL_4)))           \
22704   ||                                           \
22705       (((INSTANCE) == TIM3) &&                 \
22706       (((CHANNEL) == TIM_CHANNEL_1)||          \
22707       ((CHANNEL) == TIM_CHANNEL_2) ||          \
22708       ((CHANNEL) == TIM_CHANNEL_3) ||          \
22709       ((CHANNEL) == TIM_CHANNEL_4)))           \
22710   ||                                           \
22711       (((INSTANCE) == TIM4) &&                 \
22712       (((CHANNEL) == TIM_CHANNEL_1) ||         \
22713       ((CHANNEL) == TIM_CHANNEL_2) ||          \
22714       ((CHANNEL) == TIM_CHANNEL_3) ||          \
22715       ((CHANNEL) == TIM_CHANNEL_4)))           \
22716   ||                                           \
22717       (((INSTANCE) == TIM5) &&                 \
22718       (((CHANNEL) == TIM_CHANNEL_1) ||         \
22719       ((CHANNEL) == TIM_CHANNEL_2) ||          \
22720       ((CHANNEL) == TIM_CHANNEL_3) ||          \
22721       ((CHANNEL) == TIM_CHANNEL_4)))           \
22722   ||                                           \
22723       (((INSTANCE) == TIM8) &&                 \
22724       (((CHANNEL) == TIM_CHANNEL_1) ||         \
22725       ((CHANNEL) == TIM_CHANNEL_2) ||          \
22726       ((CHANNEL) == TIM_CHANNEL_3) ||          \
22727       ((CHANNEL) == TIM_CHANNEL_4) ||          \
22728       ((CHANNEL) == TIM_CHANNEL_5) ||          \
22729       ((CHANNEL) == TIM_CHANNEL_6)))           \
22730   ||                                           \
22731      (((INSTANCE) == TIM12) &&                 \
22732      (((CHANNEL) == TIM_CHANNEL_1) ||          \
22733       ((CHANNEL) == TIM_CHANNEL_2)))           \
22734   ||                                           \
22735      (((INSTANCE) == TIM13) &&                 \
22736      (((CHANNEL) == TIM_CHANNEL_1)))           \
22737   ||                                           \
22738      (((INSTANCE) == TIM14) &&                 \
22739      (((CHANNEL) == TIM_CHANNEL_1)))           \
22740   ||                                           \
22741      (((INSTANCE) == TIM15) &&                 \
22742      (((CHANNEL) == TIM_CHANNEL_1) ||          \
22743      ((CHANNEL) == TIM_CHANNEL_2)))            \
22744   ||                                           \
22745      (((INSTANCE) == TIM16) &&                 \
22746      (((CHANNEL) == TIM_CHANNEL_1)))           \
22747   ||                                           \
22748      (((INSTANCE) == TIM17) &&                 \
22749      (((CHANNEL) == TIM_CHANNEL_1))))
22750 
22751 /****************** TIM Instances : supporting the break function *************/
22752 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
22753       (((INSTANCE) == TIM1)    || \
22754       ((INSTANCE) == TIM8)     || \
22755        ((INSTANCE) == TIM15)   || \
22756        ((INSTANCE) == TIM16)   || \
22757        ((INSTANCE) == TIM17))
22758 
22759 /************** TIM Instances : supporting Break source selection *************/
22760 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
22761                                                ((INSTANCE) == TIM8))
22762 
22763 /****************** TIM Instances : supporting complementary output(s) ********/
22764 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
22765    ((((INSTANCE) == TIM1) &&                    \
22766      (((CHANNEL) == TIM_CHANNEL_1) ||           \
22767       ((CHANNEL) == TIM_CHANNEL_2) ||           \
22768       ((CHANNEL) == TIM_CHANNEL_3)))            \
22769  ||                                             \
22770       (((INSTANCE) == TIM8) &&                  \
22771       (((CHANNEL) == TIM_CHANNEL_1) ||          \
22772       ((CHANNEL) == TIM_CHANNEL_2) ||           \
22773       ((CHANNEL) == TIM_CHANNEL_3)))            \
22774     ||                                          \
22775     (((INSTANCE) == TIM15) &&                   \
22776       ((CHANNEL) == TIM_CHANNEL_1))             \
22777     ||                                          \
22778     (((INSTANCE) == TIM16) &&                   \
22779      ((CHANNEL) == TIM_CHANNEL_1))              \
22780     ||                                          \
22781     (((INSTANCE) == TIM17) &&                   \
22782      ((CHANNEL) == TIM_CHANNEL_1)))
22783 
22784 /****************** TIM Instances : supporting counting mode selection ********/
22785 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
22786   (((INSTANCE) == TIM1)    || \
22787    ((INSTANCE) == TIM2)    || \
22788    ((INSTANCE) == TIM3)    || \
22789    ((INSTANCE) == TIM4)    || \
22790    ((INSTANCE) == TIM5)    || \
22791    ((INSTANCE) == TIM8))
22792 
22793 /****************** TIM Instances : supporting repetition counter *************/
22794 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
22795   (((INSTANCE) == TIM1)    || \
22796    ((INSTANCE) == TIM8)    || \
22797    ((INSTANCE) == TIM15)   || \
22798    ((INSTANCE) == TIM16)   || \
22799    ((INSTANCE) == TIM17))
22800 
22801 /****************** TIM Instances : supporting synchronization ****************/
22802 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
22803     (((__INSTANCE__) == TIM1)    || \
22804      ((__INSTANCE__) == TIM2)    || \
22805      ((__INSTANCE__) == TIM3)    || \
22806      ((__INSTANCE__) == TIM4)    || \
22807      ((__INSTANCE__) == TIM5)    || \
22808      ((__INSTANCE__) == TIM6)    || \
22809      ((__INSTANCE__) == TIM8)    || \
22810      ((__INSTANCE__) == TIM12)   || \
22811      ((__INSTANCE__) == TIM15))
22812 
22813 /****************** TIM Instances : supporting clock division *****************/
22814 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
22815   (((INSTANCE) == TIM1)    || \
22816    ((INSTANCE) == TIM2)    || \
22817    ((INSTANCE) == TIM3)    || \
22818    ((INSTANCE) == TIM4)    || \
22819    ((INSTANCE) == TIM5)    || \
22820    ((INSTANCE) == TIM8)    || \
22821    ((INSTANCE) == TIM15)   || \
22822    ((INSTANCE) == TIM16)   || \
22823    ((INSTANCE) == TIM17))
22824 
22825 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
22826 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
22827   (((INSTANCE) == TIM1)    || \
22828    ((INSTANCE) == TIM2)    || \
22829    ((INSTANCE) == TIM3)    || \
22830    ((INSTANCE) == TIM4)    || \
22831    ((INSTANCE) == TIM5)    || \
22832    ((INSTANCE) == TIM8))
22833 
22834 /****************** TIM Instances : supporting external clock mode 2 **********/
22835 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
22836  (((INSTANCE) == TIM1)     || \
22837    ((INSTANCE) == TIM2)    || \
22838    ((INSTANCE) == TIM3)    || \
22839    ((INSTANCE) == TIM4)    || \
22840    ((INSTANCE) == TIM5)    || \
22841    ((INSTANCE) == TIM8))
22842 
22843 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
22844 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
22845   (((INSTANCE) == TIM1)    || \
22846    ((INSTANCE) == TIM2)    || \
22847    ((INSTANCE) == TIM3)    || \
22848    ((INSTANCE) == TIM4)    || \
22849    ((INSTANCE) == TIM5)    || \
22850    ((INSTANCE) == TIM8)    || \
22851    ((INSTANCE) == TIM12)   || \
22852    ((INSTANCE) == TIM15))
22853 
22854 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
22855 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
22856   (((INSTANCE) == TIM1)    || \
22857    ((INSTANCE) == TIM2)    || \
22858    ((INSTANCE) == TIM3)    || \
22859    ((INSTANCE) == TIM4)    || \
22860    ((INSTANCE) == TIM5)    || \
22861    ((INSTANCE) == TIM8)    || \
22862    ((INSTANCE) == TIM12)   || \
22863    ((INSTANCE) == TIM15))
22864 
22865 /****************** TIM Instances : supporting OCxREF clear *******************/
22866 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
22867   (((INSTANCE) == TIM1)    || \
22868    ((INSTANCE) == TIM2)    || \
22869    ((INSTANCE) == TIM3))
22870 
22871 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
22872 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
22873   (((INSTANCE) == TIM2)    || \
22874    ((INSTANCE) == TIM5))
22875 
22876 /****************** TIM Instances : TIM_BKIN2 ***************************/
22877 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
22878   (((INSTANCE) == TIM1)    || \
22879    ((INSTANCE) == TIM8))
22880 
22881 /****************** TIM Instances : supporting Hall sensor interface **********/
22882 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \
22883                                                              ((__INSTANCE__) == TIM2)  || \
22884                                                              ((__INSTANCE__) == TIM3)  || \
22885                                                              ((__INSTANCE__) == TIM4)  || \
22886                                                              ((__INSTANCE__) == TIM5)  || \
22887                                                              ((__INSTANCE__) == TIM15) || \
22888                                                              ((__INSTANCE__) == TIM8))
22889 
22890 /******************** USART Instances : Synchronous mode **********************/
22891 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22892                                      ((INSTANCE) == USART2) || \
22893                                      ((INSTANCE) == USART3) || \
22894                                      ((INSTANCE) == USART6) || \
22895                                      ((INSTANCE) == USART10))
22896 
22897 /******************** USART Instances : SPI slave mode ************************/
22898 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22899                                               ((INSTANCE) == USART2) || \
22900                                               ((INSTANCE) == USART3) || \
22901                                               ((INSTANCE) == USART6) || \
22902                                               ((INSTANCE) == USART10))
22903 
22904 /******************** UART Instances : Asynchronous mode **********************/
22905 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22906                                     ((INSTANCE) == USART2) || \
22907                                     ((INSTANCE) == USART3) || \
22908                                     ((INSTANCE) == UART4)  || \
22909                                     ((INSTANCE) == UART5)  || \
22910                                     ((INSTANCE) == USART6) || \
22911                                     ((INSTANCE) == UART7)  || \
22912                                     ((INSTANCE) == UART8)  || \
22913                                     ((INSTANCE) == UART9)  || \
22914                                     ((INSTANCE) == USART10))
22915 
22916 /******************** UART Instances : FIFO mode.******************************/
22917 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22918                                          ((INSTANCE) == USART2) || \
22919                                          ((INSTANCE) == USART3) || \
22920                                          ((INSTANCE) == UART4)  || \
22921                                          ((INSTANCE) == UART5)  || \
22922                                          ((INSTANCE) == USART6) || \
22923                                          ((INSTANCE) == UART7)  || \
22924                                          ((INSTANCE) == UART8)  || \
22925                                          ((INSTANCE) == UART9)  || \
22926                                          ((INSTANCE) == USART10)|| \
22927                                          ((INSTANCE) == LPUART1))
22928 
22929 /****************** UART Instances : Auto Baud Rate detection *****************/
22930 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22931                                                             ((INSTANCE) == USART2) || \
22932                                                             ((INSTANCE) == USART3) || \
22933                                                             ((INSTANCE) == UART4)  || \
22934                                                             ((INSTANCE) == UART5)  || \
22935                                                             ((INSTANCE) == USART6) || \
22936                                                             ((INSTANCE) == UART7)  || \
22937                                                             ((INSTANCE) == UART8)  || \
22938                                                             ((INSTANCE) == UART9)  || \
22939                                                             ((INSTANCE) == USART10))
22940 
22941 /*********************** UART Instances : Driver Enable ***********************/
22942 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22943                                                   ((INSTANCE) == USART2) || \
22944                                                   ((INSTANCE) == USART3) || \
22945                                                   ((INSTANCE) == UART4)  || \
22946                                                   ((INSTANCE) == UART5)  || \
22947                                                   ((INSTANCE) == USART6) || \
22948                                                   ((INSTANCE) == UART7)  || \
22949                                                   ((INSTANCE) == UART8)  || \
22950                                                   ((INSTANCE) == UART9)  || \
22951                                                   ((INSTANCE) == USART10)|| \
22952                                                   ((INSTANCE) == LPUART1))
22953 
22954 /********************* UART Instances : Half-Duplex mode **********************/
22955 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22956                                                ((INSTANCE) == USART2) || \
22957                                                ((INSTANCE) == USART3) || \
22958                                                ((INSTANCE) == UART4)  || \
22959                                                ((INSTANCE) == UART5)  || \
22960                                                ((INSTANCE) == USART6) || \
22961                                                ((INSTANCE) == UART7)  || \
22962                                                ((INSTANCE) == UART8)  || \
22963                                                ((INSTANCE) == UART9)  || \
22964                                                ((INSTANCE) == USART10)|| \
22965                                                ((INSTANCE) == LPUART1))
22966 
22967 /******************* UART Instances : Hardware Flow control *******************/
22968 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22969                                            ((INSTANCE) == USART2) || \
22970                                            ((INSTANCE) == USART3) || \
22971                                            ((INSTANCE) == UART4)  || \
22972                                            ((INSTANCE) == UART5)  || \
22973                                            ((INSTANCE) == USART6) || \
22974                                            ((INSTANCE) == UART7)  || \
22975                                            ((INSTANCE) == UART8)  || \
22976                                            ((INSTANCE) == UART9)  || \
22977                                            ((INSTANCE) == USART10)|| \
22978                                            ((INSTANCE) == LPUART1))
22979 
22980 /************************* UART Instances : LIN mode **************************/
22981 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22982                                         ((INSTANCE) == USART2) || \
22983                                         ((INSTANCE) == USART3) || \
22984                                         ((INSTANCE) == UART4)  || \
22985                                         ((INSTANCE) == UART5)  || \
22986                                         ((INSTANCE) == USART6) || \
22987                                         ((INSTANCE) == UART7)  || \
22988                                         ((INSTANCE) == UART8)  || \
22989                                         ((INSTANCE) == UART9)  || \
22990                                         ((INSTANCE) == USART10))
22991 
22992 /****************** UART Instances : Wake-up from Stop mode *******************/
22993 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22994                                                     ((INSTANCE) == USART2) || \
22995                                                     ((INSTANCE) == USART3) || \
22996                                                     ((INSTANCE) == UART4)  || \
22997                                                     ((INSTANCE) == UART5)  || \
22998                                                     ((INSTANCE) == USART6) || \
22999                                                     ((INSTANCE) == UART7)  || \
23000                                                     ((INSTANCE) == UART8)  || \
23001                                                     ((INSTANCE) == UART9)  || \
23002                                                     ((INSTANCE) == USART10)|| \
23003                                                     ((INSTANCE) == LPUART1))
23004 
23005 /************************* UART Instances : IRDA mode *************************/
23006 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
23007                                     ((INSTANCE) == USART2) || \
23008                                     ((INSTANCE) == USART3) || \
23009                                     ((INSTANCE) == UART4)  || \
23010                                     ((INSTANCE) == UART5)  || \
23011                                     ((INSTANCE) == USART6) || \
23012                                     ((INSTANCE) == UART7)  || \
23013                                     ((INSTANCE) == UART8)  || \
23014                                     ((INSTANCE) == UART9)  || \
23015                                     ((INSTANCE) == USART10))
23016 
23017 /********************* USART Instances : Smard card mode **********************/
23018 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
23019                                          ((INSTANCE) == USART2) || \
23020                                          ((INSTANCE) == USART3) || \
23021                                          ((INSTANCE) == USART6) ||\
23022                                          ((INSTANCE) == USART10))
23023 
23024 /****************************** LPUART Instance *******************************/
23025 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
23026 
23027 /****************************** IWDG Instances ********************************/
23028 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)
23029 /****************************** USB Instances ********************************/
23030 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
23031 
23032 /****************************** WWDG Instances ********************************/
23033 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)
23034 /****************************** MDIOS Instances ********************************/
23035 #define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)
23036 
23037 /****************************** CEC Instances *********************************/
23038 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
23039 
23040 /****************************** SAI Instances ********************************/
23041 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
23042                                        ((INSTANCE) == SAI1_Block_B) || \
23043                                        ((INSTANCE) == SAI2_Block_A) || \
23044                                        ((INSTANCE) == SAI2_Block_B))
23045 
23046 /****************************** SPDIFRX Instances ********************************/
23047 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
23048 
23049 /****************************** OPAMP Instances *******************************/
23050 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
23051                                          ((INSTANCE) == OPAMP2))
23052 
23053 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
23054 
23055 /*********************** USB OTG PCD Instances ********************************/
23056 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
23057 
23058 /*********************** USB OTG HCD Instances ********************************/
23059 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
23060 
23061 /******************************************************************************/
23062 /*  For a painless codes migration between the STM32H7xx device product       */
23063 /*  lines, or with STM32F7xx devices the aliases defined below are put        */
23064 /*   in place to overcome the differences in the interrupt handlers and IRQn  */
23065 /*   definitions. No need to update developed interrupt code when moving      */
23066 /*  across product lines within the same STM32H7 Family                       */
23067 /******************************************************************************/
23068 
23069 /* Aliases for __IRQn */
23070 #define  RNG_IRQn                       HASH_RNG_IRQn
23071 #define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn
23072 #define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn
23073 #define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn
23074 #define  PVD_IRQn                       PVD_AVD_IRQn
23075 
23076 /* Aliases for BDMA __IRQn */
23077 #define  BDMA_Channel0_IRQn             BDMA2_Channel0_IRQn
23078 #define  BDMA_Channel1_IRQn             BDMA2_Channel1_IRQn
23079 #define  BDMA_Channel2_IRQn             BDMA2_Channel2_IRQn
23080 #define  BDMA_Channel3_IRQn             BDMA2_Channel3_IRQn
23081 #define  BDMA_Channel4_IRQn             BDMA2_Channel4_IRQn
23082 #define  BDMA_Channel5_IRQn             BDMA2_Channel5_IRQn
23083 #define  BDMA_Channel6_IRQn             BDMA2_Channel6_IRQn
23084 #define  BDMA_Channel7_IRQn             BDMA2_Channel7_IRQn
23085 
23086 /* Aliases for PWR __IRQn */
23087 #define  PVD_AVD_IRQn                   PVD_PVM_IRQn
23088 
23089 /* Aliases for DCMI/PSSI __IRQn */
23090 #define  DCMI_IRQn                      DCMI_PSSI_IRQn
23091 
23092 /* Aliases for __IRQHandler */
23093 #define   RNG_IRQHandler               HASH_RNG_IRQHandler
23094 #define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler
23095 #define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler
23096 #define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler
23097 #define PVD_IRQHandler                 PVD_AVD_IRQHandler
23098 
23099 
23100 /* Aliases for BDMA __IRQHandler */
23101 #define  BDMA_Channel0_IRQHandler      BDMA2_Channel0_IRQHandler
23102 #define  BDMA_Channel1_IRQHandler      BDMA2_Channel1_IRQHandler
23103 #define  BDMA_Channel2_IRQHandler      BDMA2_Channel2_IRQHandler
23104 #define  BDMA_Channel3_IRQHandler      BDMA2_Channel3_IRQHandler
23105 #define  BDMA_Channel4_IRQHandler      BDMA2_Channel4_IRQHandler
23106 #define  BDMA_Channel5_IRQHandler      BDMA2_Channel5_IRQHandler
23107 #define  BDMA_Channel6_IRQHandler      BDMA2_Channel6_IRQHandler
23108 #define  BDMA_Channel7_IRQHandler      BDMA2_Channel7_IRQHandler
23109 
23110 /* Aliases for PWR __IRQHandler */
23111 #define  PVD_AVD_IRQHandler            PVD_PVM_IRQHandler
23112 
23113 /* Aliases for DCMI/PSSI __IRQHandler */
23114 #define  DCMI_IRQHandler               DCMI_PSSI_IRQHandler
23115 
23116 /* Alias for BDMA defines */
23117 #define BDMA_BASE              BDMA2_BASE
23118 #define BDMA_Channel0_BASE     BDMA2_Channel0_BASE
23119 #define BDMA_Channel1_BASE     BDMA2_Channel1_BASE
23120 #define BDMA_Channel2_BASE     BDMA2_Channel2_BASE
23121 #define BDMA_Channel3_BASE     BDMA2_Channel3_BASE
23122 #define BDMA_Channel4_BASE     BDMA2_Channel4_BASE
23123 #define BDMA_Channel5_BASE     BDMA2_Channel5_BASE
23124 #define BDMA_Channel6_BASE     BDMA2_Channel6_BASE
23125 #define BDMA_Channel7_BASE     BDMA2_Channel7_BASE
23126 
23127 #define BDMA                   BDMA2
23128 #define BDMA_Channel0          BDMA2_Channel0
23129 #define BDMA_Channel1          BDMA2_Channel1
23130 #define BDMA_Channel2          BDMA2_Channel2
23131 #define BDMA_Channel3          BDMA2_Channel3
23132 #define BDMA_Channel4          BDMA2_Channel4
23133 #define BDMA_Channel5          BDMA2_Channel5
23134 #define BDMA_Channel6          BDMA2_Channel6
23135 #define BDMA_Channel7          BDMA2_Channel7
23136 
23137 /* Alias for PWR defines */
23138 #define PWR_CPUCR_RUN_D3       PWR_CPUCR_RUN_SRD
23139 #define PWR_CPUCR_PDDS_D3      PWR_CPUCR_PDDS_SRD
23140 #define PWR_CPUCR_PDDS_D1      PWR_CPUCR_RETDS_CD
23141 
23142 #define PWR_D3CR_VOS           PWR_SRDCR_VOS
23143 
23144 #define PWR_D3CR_VOS_0         PWR_SRDCR_VOS_0
23145 #define PWR_D3CR_VOS_1         PWR_SRDCR_VOS_1
23146 #define PWR_D3CR_VOSRDY        PWR_SRDCR_VOSRDY
23147 
23148 /**
23149   * @}
23150   */
23151 
23152 /**
23153   * @}
23154   */
23155 
23156 /**
23157   * @}
23158   */
23159 
23160 #ifdef __cplusplus
23161 }
23162 #endif /* __cplusplus */
23163 
23164 #endif /* STM32H7B3xx_H */
23165 
23166