1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32H5xx_LL_TIM_H
21 #define __STM32H5xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM4) \
38 || defined (TIM5) \
39 || defined (TIM6) \
40 || defined (TIM7) \
41 || defined (TIM8) \
42 || defined (TIM12) \
43 || defined (TIM13) \
44 || defined (TIM14) \
45 || defined (TIM15) \
46 || defined (TIM16) \
47 || defined (TIM17)
48
49 /** @defgroup TIM_LL TIM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
56 * @{
57 */
58 static const uint8_t OFFSET_TAB_CCMRx[] =
59 {
60 0x00U, /* 0: TIMx_CH1 */
61 0x00U, /* 1: TIMx_CH1N */
62 0x00U, /* 2: TIMx_CH2 */
63 0x00U, /* 3: TIMx_CH2N */
64 0x04U, /* 4: TIMx_CH3 */
65 0x04U, /* 5: TIMx_CH3N */
66 0x04U, /* 6: TIMx_CH4 */
67 0x04U, /* 7: TIMx_CH4N */
68 0x38U, /* 8: TIMx_CH5 */
69 0x38U /* 9: TIMx_CH6 */
70
71 };
72
73 static const uint8_t SHIFT_TAB_OCxx[] =
74 {
75 0U, /* 0: OC1M, OC1FE, OC1PE */
76 0U, /* 1: - NA */
77 8U, /* 2: OC2M, OC2FE, OC2PE */
78 0U, /* 3: - NA */
79 0U, /* 4: OC3M, OC3FE, OC3PE */
80 0U, /* 5: - NA */
81 8U, /* 6: OC4M, OC4FE, OC4PE */
82 0U, /* 7: - NA */
83 0U, /* 8: OC5M, OC5FE, OC5PE */
84 8U /* 9: OC6M, OC6FE, OC6PE */
85 };
86
87 static const uint8_t SHIFT_TAB_ICxx[] =
88 {
89 0U, /* 0: CC1S, IC1PSC, IC1F */
90 0U, /* 1: - NA */
91 8U, /* 2: CC2S, IC2PSC, IC2F */
92 0U, /* 3: - NA */
93 0U, /* 4: CC3S, IC3PSC, IC3F */
94 0U, /* 5: - NA */
95 8U, /* 6: CC4S, IC4PSC, IC4F */
96 0U, /* 7: - NA */
97 0U, /* 8: - NA */
98 0U /* 9: - NA */
99 };
100
101 static const uint8_t SHIFT_TAB_CCxP[] =
102 {
103 0U, /* 0: CC1P */
104 2U, /* 1: CC1NP */
105 4U, /* 2: CC2P */
106 6U, /* 3: CC2NP */
107 8U, /* 4: CC3P */
108 10U, /* 5: CC3NP */
109 12U, /* 6: CC4P */
110 14U, /* 7: CC4NP */
111 16U, /* 8: CC5P */
112 20U /* 9: CC6P */
113 };
114
115 static const uint8_t SHIFT_TAB_OISx[] =
116 {
117 0U, /* 0: OIS1 */
118 1U, /* 1: OIS1N */
119 2U, /* 2: OIS2 */
120 3U, /* 3: OIS2N */
121 4U, /* 4: OIS3 */
122 5U, /* 5: OIS3N */
123 6U, /* 6: OIS4 */
124 7U, /* 7: OIS4N */
125 8U, /* 8: OIS5 */
126 10U /* 9: OIS6 */
127 };
128 /**
129 * @}
130 */
131
132 /* Private constants ---------------------------------------------------------*/
133 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
134 * @{
135 */
136
137 /* Defines used for the bit position in the register and perform offsets */
138 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
139
140 /* Generic bit definitions for TIMx_AF1 register */
141 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
142 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
143
144
145 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
146 #define DT_DELAY_1 ((uint8_t)0x7F)
147 #define DT_DELAY_2 ((uint8_t)0x3F)
148 #define DT_DELAY_3 ((uint8_t)0x1F)
149 #define DT_DELAY_4 ((uint8_t)0x1F)
150
151 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
152 #define DT_RANGE_1 ((uint8_t)0x00)
153 #define DT_RANGE_2 ((uint8_t)0x80)
154 #define DT_RANGE_3 ((uint8_t)0xC0)
155 #define DT_RANGE_4 ((uint8_t)0xE0)
156
157 /** Legacy definitions for compatibility purpose
158 @cond 0
159 */
160 /**
161 @endcond
162 */
163
164 #define OCREF_CLEAR_SELECT_POS (28U)
165 #define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */
166 /**
167 * @}
168 */
169
170 /* Private macros ------------------------------------------------------------*/
171 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
172 * @{
173 */
174 /** @brief Convert channel id into channel index.
175 * @param __CHANNEL__ This parameter can be one of the following values:
176 * @arg @ref LL_TIM_CHANNEL_CH1
177 * @arg @ref LL_TIM_CHANNEL_CH1N
178 * @arg @ref LL_TIM_CHANNEL_CH2
179 * @arg @ref LL_TIM_CHANNEL_CH2N
180 * @arg @ref LL_TIM_CHANNEL_CH3
181 * @arg @ref LL_TIM_CHANNEL_CH3N
182 * @arg @ref LL_TIM_CHANNEL_CH4
183 * @arg @ref LL_TIM_CHANNEL_CH4N
184 * @arg @ref LL_TIM_CHANNEL_CH5
185 * @arg @ref LL_TIM_CHANNEL_CH6
186 * @retval none
187 */
188 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
189 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
190 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
191 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
196 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
197 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
198
199 /** @brief Calculate the deadtime sampling period(in ps).
200 * @param __TIMCLK__ timer input clock frequency (in Hz).
201 * @param __CKD__ This parameter can be one of the following values:
202 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
203 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
204 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
205 * @retval none
206 */
207 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
208 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
209 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
210 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
211 /**
212 * @}
213 */
214
215
216 /* Exported types ------------------------------------------------------------*/
217 #if defined(USE_FULL_LL_DRIVER)
218 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
219 * @{
220 */
221
222 /**
223 * @brief TIM Time Base configuration structure definition.
224 */
225 typedef struct
226 {
227 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
228 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
229
230 This feature can be modified afterwards using unitary function
231 @ref LL_TIM_SetPrescaler().*/
232
233 uint32_t CounterMode; /*!< Specifies the counter mode.
234 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
235
236 This feature can be modified afterwards using unitary function
237 @ref LL_TIM_SetCounterMode().*/
238
239 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
240 Auto-Reload Register at the next update event.
241 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
242 Some timer instances may support 32 bits counters. In that case this parameter must
243 be a number between 0x0000 and 0xFFFFFFFF.
244
245 This feature can be modified afterwards using unitary function
246 @ref LL_TIM_SetAutoReload().*/
247
248 uint32_t ClockDivision; /*!< Specifies the clock division.
249 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
250
251 This feature can be modified afterwards using unitary function
252 @ref LL_TIM_SetClockDivision().*/
253
254 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
255 reaches zero, an update event is generated and counting restarts
256 from the RCR value (N).
257 This means in PWM mode that (N+1) corresponds to:
258 - the number of PWM periods in edge-aligned mode
259 - the number of half PWM period in center-aligned mode
260 GP timers: this parameter must be a number between Min_Data = 0x00 and
261 Max_Data = 0xFF.
262 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
263 Max_Data = 0xFFFF.
264
265 This feature can be modified afterwards using unitary function
266 @ref LL_TIM_SetRepetitionCounter().*/
267 } LL_TIM_InitTypeDef;
268
269 /**
270 * @brief TIM Output Compare configuration structure definition.
271 */
272 typedef struct
273 {
274 uint32_t OCMode; /*!< Specifies the output mode.
275 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
276
277 This feature can be modified afterwards using unitary function
278 @ref LL_TIM_OC_SetMode().*/
279
280 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
281 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
282
283 This feature can be modified afterwards using unitary functions
284 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
285
286 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
287 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
288
289 This feature can be modified afterwards using unitary functions
290 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
291
292 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
293 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
294
295 This feature can be modified afterwards using unitary function
296 LL_TIM_OC_SetCompareCHx (x=1..6).*/
297
298 uint32_t OCPolarity; /*!< Specifies the output polarity.
299 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
300
301 This feature can be modified afterwards using unitary function
302 @ref LL_TIM_OC_SetPolarity().*/
303
304 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
305 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
306
307 This feature can be modified afterwards using unitary function
308 @ref LL_TIM_OC_SetPolarity().*/
309
310
311 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
312 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
313
314 This feature can be modified afterwards using unitary function
315 @ref LL_TIM_OC_SetIdleState().*/
316
317 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
318 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
319
320 This feature can be modified afterwards using unitary function
321 @ref LL_TIM_OC_SetIdleState().*/
322 } LL_TIM_OC_InitTypeDef;
323
324 /**
325 * @brief TIM Input Capture configuration structure definition.
326 */
327
328 typedef struct
329 {
330
331 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
332 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
333
334 This feature can be modified afterwards using unitary function
335 @ref LL_TIM_IC_SetPolarity().*/
336
337 uint32_t ICActiveInput; /*!< Specifies the input.
338 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
339
340 This feature can be modified afterwards using unitary function
341 @ref LL_TIM_IC_SetActiveInput().*/
342
343 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
344 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
345
346 This feature can be modified afterwards using unitary function
347 @ref LL_TIM_IC_SetPrescaler().*/
348
349 uint32_t ICFilter; /*!< Specifies the input capture filter.
350 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_IC_SetFilter().*/
354 } LL_TIM_IC_InitTypeDef;
355
356
357 /**
358 * @brief TIM Encoder interface configuration structure definition.
359 */
360 typedef struct
361 {
362 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
363 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
364
365 This feature can be modified afterwards using unitary function
366 @ref LL_TIM_SetEncoderMode().*/
367
368 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
369 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
370
371 This feature can be modified afterwards using unitary function
372 @ref LL_TIM_IC_SetPolarity().*/
373
374 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
375 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
376
377 This feature can be modified afterwards using unitary function
378 @ref LL_TIM_IC_SetActiveInput().*/
379
380 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
381 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
382
383 This feature can be modified afterwards using unitary function
384 @ref LL_TIM_IC_SetPrescaler().*/
385
386 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
387 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
388
389 This feature can be modified afterwards using unitary function
390 @ref LL_TIM_IC_SetFilter().*/
391
392 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
393 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
394
395 This feature can be modified afterwards using unitary function
396 @ref LL_TIM_IC_SetPolarity().*/
397
398 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
399 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
400
401 This feature can be modified afterwards using unitary function
402 @ref LL_TIM_IC_SetActiveInput().*/
403
404 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
405 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
406
407 This feature can be modified afterwards using unitary function
408 @ref LL_TIM_IC_SetPrescaler().*/
409
410 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
411 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
412
413 This feature can be modified afterwards using unitary function
414 @ref LL_TIM_IC_SetFilter().*/
415
416 } LL_TIM_ENCODER_InitTypeDef;
417
418 /**
419 * @brief TIM Hall sensor interface configuration structure definition.
420 */
421 typedef struct
422 {
423
424 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
425 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
426
427 This feature can be modified afterwards using unitary function
428 @ref LL_TIM_IC_SetPolarity().*/
429
430 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
431 Prescaler must be set to get a maximum counter period longer than the
432 time interval between 2 consecutive changes on the Hall inputs.
433 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
434
435 This feature can be modified afterwards using unitary function
436 @ref LL_TIM_IC_SetPrescaler().*/
437
438 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
439 This parameter can be a value of
440 @ref TIM_LL_EC_IC_FILTER.
441
442 This feature can be modified afterwards using unitary function
443 @ref LL_TIM_IC_SetFilter().*/
444
445 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
446 A positive pulse (TRGO event) is generated with a programmable delay every time
447 a change occurs on the Hall inputs.
448 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
449
450 This feature can be modified afterwards using unitary function
451 @ref LL_TIM_OC_SetCompareCH2().*/
452 } LL_TIM_HALLSENSOR_InitTypeDef;
453
454 /**
455 * @brief BDTR (Break and Dead Time) structure definition
456 */
457 typedef struct
458 {
459 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
460 This parameter can be a value of @ref TIM_LL_EC_OSSR
461
462 This feature can be modified afterwards using unitary function
463 @ref LL_TIM_SetOffStates()
464
465 @note This bit-field cannot be modified as long as LOCK level 2 has been
466 programmed. */
467
468 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
469 This parameter can be a value of @ref TIM_LL_EC_OSSI
470
471 This feature can be modified afterwards using unitary function
472 @ref LL_TIM_SetOffStates()
473
474 @note This bit-field cannot be modified as long as LOCK level 2 has been
475 programmed. */
476
477 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
478 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
479
480 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
481 register has been written, their content is frozen until the next reset.*/
482
483 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
484 switching-on of the outputs.
485 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
486
487 This feature can be modified afterwards using unitary function
488 @ref LL_TIM_OC_SetDeadTime()
489
490 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
491 programmed. */
492
493 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
494 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
495
496 This feature can be modified afterwards using unitary functions
497 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
498
499 @note This bit-field can not be modified as long as LOCK level 1 has been
500 programmed. */
501
502 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
503 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
504
505 This feature can be modified afterwards using unitary function
506 @ref LL_TIM_ConfigBRK()
507
508 @note This bit-field can not be modified as long as LOCK level 1 has been
509 programmed. */
510
511 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
512 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
513
514 This feature can be modified afterwards using unitary function
515 @ref LL_TIM_ConfigBRK()
516
517 @note This bit-field can not be modified as long as LOCK level 1 has been
518 programmed. */
519
520 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
521 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
522
523 This feature can be modified afterwards using unitary functions
524 @ref LL_TIM_ConfigBRK()
525
526 @note Bidirectional break input is only supported by advanced timers instances.
527
528 @note This bit-field can not be modified as long as LOCK level 1 has been
529 programmed. */
530
531 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
532 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
533
534 This feature can be modified afterwards using unitary functions
535 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
536
537 @note This bit-field can not be modified as long as LOCK level 1 has been
538 programmed. */
539
540 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
541 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
542
543 This feature can be modified afterwards using unitary function
544 @ref LL_TIM_ConfigBRK2()
545
546 @note This bit-field can not be modified as long as LOCK level 1 has been
547 programmed. */
548
549 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
550 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
551
552 This feature can be modified afterwards using unitary function
553 @ref LL_TIM_ConfigBRK2()
554
555 @note This bit-field can not be modified as long as LOCK level 1 has been
556 programmed. */
557
558 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
559 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
560
561 This feature can be modified afterwards using unitary functions
562 @ref LL_TIM_ConfigBRK2()
563
564 @note Bidirectional break input is only supported by advanced timers instances.
565
566 @note This bit-field can not be modified as long as LOCK level 1 has been
567 programmed. */
568
569 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
570 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
571
572 This feature can be modified afterwards using unitary functions
573 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
574
575 @note This bit-field can not be modified as long as LOCK level 1 has been
576 programmed. */
577 } LL_TIM_BDTR_InitTypeDef;
578
579 /**
580 * @}
581 */
582 #endif /* USE_FULL_LL_DRIVER */
583
584 /* Exported constants --------------------------------------------------------*/
585 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
586 * @{
587 */
588
589 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
590 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
591 * @{
592 */
593 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
594 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
595 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
596 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
597 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
598 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
599 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
600 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
601 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
602 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
603 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
604 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
605 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
606 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
607 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
608 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
609 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
610 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
611 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
612 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
613 /**
614 * @}
615 */
616
617 #if defined(USE_FULL_LL_DRIVER)
618 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
619 * @{
620 */
621 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
622 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
623 /**
624 * @}
625 */
626
627 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
628 * @{
629 */
630 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
631 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
632 /**
633 * @}
634 */
635
636 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
637 * @{
638 */
639 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
640 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
641 /**
642 * @}
643 */
644 #endif /* USE_FULL_LL_DRIVER */
645
646 /** @defgroup TIM_LL_EC_IT IT Defines
647 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
648 * @{
649 */
650 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
651 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
652 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
653 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
654 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
655 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
656 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
657 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
658 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
659 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
660 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
661 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
662 /**
663 * @}
664 */
665
666 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
667 * @{
668 */
669 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
670 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
671 /**
672 * @}
673 */
674
675 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
676 * @{
677 */
678 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
679 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
680 /**
681 * @}
682 */
683
684 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
685 * @{
686 */
687 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
688 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
689 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
690 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
691 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
692 /**
693 * @}
694 */
695
696 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
697 * @{
698 */
699 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
700 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
701 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
702 /**
703 * @}
704 */
705
706 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
707 * @{
708 */
709 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
710 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
711 /**
712 * @}
713 */
714
715 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
716 * @{
717 */
718 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
719 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
720 /**
721 * @}
722 */
723
724 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
725 * @{
726 */
727 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
728 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
729 /**
730 * @}
731 */
732
733 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
734 * @{
735 */
736 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
737 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
738 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
739 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
740 /**
741 * @}
742 */
743
744 /** @defgroup TIM_LL_EC_CHANNEL Channel
745 * @{
746 */
747 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
748 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
749 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
750 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
751 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
752 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
753 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
754 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
755 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
756 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
757 /**
758 * @}
759 */
760
761 #if defined(USE_FULL_LL_DRIVER)
762 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
763 * @{
764 */
765 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
766 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
767 /**
768 * @}
769 */
770 #endif /* USE_FULL_LL_DRIVER */
771
772 /** Legacy definitions for compatibility purpose
773 @cond 0
774 */
775 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
776 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
777 /**
778 @endcond
779 */
780
781 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
782 * @{
783 */
784 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
785 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
786 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
787 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
788 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
789 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
790 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
791 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
792 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
793 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
794 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
795 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
796 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
797 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
798 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
799 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
800 /**
801 * @}
802 */
803
804 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
805 * @{
806 */
807 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
808 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
809 /**
810 * @}
811 */
812
813 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
814 * @{
815 */
816 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
817 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
823 * @{
824 */
825 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
826 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
827 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
828 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
829 /**
830 * @}
831 */
832
833 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
834 * @{
835 */
836 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
837 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
838 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
839 /**
840 * @}
841 */
842
843 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
844 * @{
845 */
846 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
847 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
848 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
849 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
850 /**
851 * @}
852 */
853
854 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
855 * @{
856 */
857 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
858 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
859 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
860 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
861 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
862 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
863 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
864 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
865 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
866 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
867 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
868 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
869 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
870 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
871 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
872 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
873 /**
874 * @}
875 */
876
877 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
878 * @{
879 */
880 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
881 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
882 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
883 /**
884 * @}
885 */
886
887 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
888 * @{
889 */
890 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
891 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
892 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
893 /**
894 * @}
895 */
896
897 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
898 * @{
899 */
900 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
901 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
902 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
903 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
904 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
905 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
906 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
907 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
908 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
909 /**
910 * @}
911 */
912
913 /** @defgroup TIM_LL_EC_TRGO Trigger Output
914 * @{
915 */
916 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
917 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
918 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
919 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
920 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
921 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
922 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
923 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
924 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
925 /**
926 * @}
927 */
928
929 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
930 * @{
931 */
932 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
933 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
934 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
935 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
936 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
937 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
938 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
939 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
940 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
941 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
942 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
943 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
944 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
945 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
946 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
947 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
948 /**
949 * @}
950 */
951
952 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
953 * @{
954 */
955 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
956 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
957 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
958 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
959 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
960 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
961 the counter are controlled. */
962 /**
963 * @}
964 */
965
966 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
967 * @{
968 */
969 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
970 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
971 /**
972 * @}
973 */
974
975 /** @defgroup TIM_LL_EC_TS Trigger Selection
976 * @{
977 */
978 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
979 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
980 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
981 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
982 #define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
983 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
984 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
985 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
986 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
987 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
988 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
989 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
990 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
991 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
992 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
993 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
994 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
995 /**
996 * @}
997 */
998
999 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
1000 * @{
1001 */
1002 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
1003 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
1009 * @{
1010 */
1011 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
1012 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
1013 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
1014 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
1015 /**
1016 * @}
1017 */
1018
1019 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
1020 * @{
1021 */
1022 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1023 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1024 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1025 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1026 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1027 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1028 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1029 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1030 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1031 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1032 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1033 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1034 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1035 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1036 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1037 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1038 /**
1039 * @}
1040 */
1041
1042 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1043 * @{
1044 */
1045 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1046 #if defined(COMP1)
1047 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1048 #endif /* COMP1 */
1049 #if defined(COMP2)
1050 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1051 #endif /* COMP2 */
1052 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */
1053 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC1 analog watchdog 2 */
1054 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */
1055 /**
1056 * @}
1057 */
1058
1059 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1060 * @{
1061 */
1062 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1063 #if defined(COMP1)
1064 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1065 #endif /* COMP1 */
1066 #if defined(COMP2)
1067 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1068 #endif /* COMP2 */
1069 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1070 #if defined(SAI1)
1071 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to SAI1_FSA */
1072 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to SAI1_FSB */
1073 #endif /* SAI1 */
1074 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
1075 #if defined(TIM4)
1076 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */
1077 #endif /* TIM4 */
1078 #if defined(TIM5)
1079 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1080 #endif /* TIM5 */
1081 #if defined(USB_DRD_FS)
1082 #define LL_TIM_TIM2_ETRSOURCE_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to USB SOF */
1083 #elif defined(USB_OTG_HS)
1084 #define LL_TIM_TIM2_ETRSOURCE_USBHS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ETR is connected to USBHS OTG SOF */
1085 #define LL_TIM_TIM2_ETRSOURCE_USBFS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR is connected to USBFS OTG SOF */
1086 #endif /* USB_DRD_FS */
1087 #if defined(ETH_NS)
1088 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ETH PPS */
1089 #endif /* ETH_NS */
1090 #if defined(PLAY1)
1091 #define LL_TIM_TIM2_ETRSOURCE_PLAY1_OUT0 TIM1_AF1_ETRSEL_Msk /*!< ETR input is connected to PLAY1 output 0 */
1092 #endif /* PLAY1 */
1093 /**
1094 * @}
1095 */
1096
1097 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1098 * @{
1099 */
1100 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1101 #if defined(COMP1)
1102 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1103 #endif /* COMP1 */
1104 #if defined(COMP2)
1105 #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1106 #endif /* COMP2 */
1107 #if defined(ADC2)
1108 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
1109 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC2 analog watchdog 2 */
1110 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
1111 #endif /* ADC2 */
1112 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1113 #if defined(TIM4)
1114 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */
1115 #endif /* TIM4 */
1116 #if defined(TIM5)
1117 #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1118 #endif /* TIM5 */
1119 #if defined(ETH_NS)
1120 #define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */
1121 #endif /* ETH_NS */
1122 #if defined(PLAY1)
1123 #define LL_TIM_TIM3_ETRSOURCE_PLAY1_OUT0 TIM1_AF1_ETRSEL_Msk /*!< ETR input is connected to PLAY1 output 0 */
1124 #endif /* PLAY1 */
1125 /**
1126 * @}
1127 */
1128
1129 #if defined(TIM4)
1130 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1131 * @{
1132 */
1133 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1134 #if defined(COMP1) && defined(COMP2)
1135 #define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1136 #define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1137 #endif /* COMP1 && COMP2 */
1138 #define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1139 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1140 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1141 /**
1142 * @}
1143 */
1144 #endif /* TIM4 */
1145
1146 #if defined(TIM5)
1147 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1148 * @{
1149 */
1150 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1151 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to SAI2_FSA */
1152 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to SAI2_FSB */
1153 #if defined(COMP1) && defined(COMP2)
1154 #define LL_TIM_TIM5_ETRSOURCE_COMP1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP1_OUT */
1155 #define LL_TIM_TIM5_ETRSOURCE_COMP2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP2_OUT */
1156 #endif /* COMP1 && COMP2 */
1157 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1158 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
1159 #define LL_TIM_TIM5_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */
1160 #if defined(USB_DRD_FS)
1161 #define LL_TIM_TIM5_ETRSOURCE_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to USB SOF */
1162 #elif defined(USB_OTG_HS)
1163 #define LL_TIM_TIM5_ETRSOURCE_USBHS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ETR is connected to USBHS OTG SOF */
1164 #define LL_TIM_TIM5_ETRSOURCE_USBFS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR is connected to USBFS OTG SOF */
1165 #endif /* USB_DRD_FS */
1166 /**
1167 * @}
1168 */
1169 #endif /* TIM5 */
1170
1171 #if defined(TIM8)
1172 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
1173 * @{
1174 */
1175 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1176 #if defined(COMP1) && defined(COMP2)
1177 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1178 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1179 #endif /* COMP1 && COMP2 */
1180 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
1181 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC2 analog watchdog 2 */
1182 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
1183 #if defined(ADC3)
1184 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 1 */
1185 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
1186 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 3 */
1187 #endif /* ADC3 */
1188 /**
1189 * @}
1190 */
1191 #endif /* TIM8 */
1192
1193 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1194 * @{
1195 */
1196 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1197 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1198 /**
1199 * @}
1200 */
1201
1202 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1203 * @{
1204 */
1205 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1206 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1207 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1208 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1209 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1210 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1211 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1212 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1213 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1214 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1215 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1216 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1217 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1218 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1219 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1220 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1221 /**
1222 * @}
1223 */
1224
1225 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1226 * @{
1227 */
1228 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1229 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1230 /**
1231 * @}
1232 */
1233
1234 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1235 * @{
1236 */
1237 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1238 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1239 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1240 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1241 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1242 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1243 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1244 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1245 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1246 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1247 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1248 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1249 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1250 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1251 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1252 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1253 /**
1254 * @}
1255 */
1256
1257 /** @defgroup TIM_LL_EC_OSSI OSSI
1258 * @{
1259 */
1260 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1261 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1262 /**
1263 * @}
1264 */
1265
1266 /** @defgroup TIM_LL_EC_OSSR OSSR
1267 * @{
1268 */
1269 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1270 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1271 /**
1272 * @}
1273 */
1274
1275 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1276 * @{
1277 */
1278 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1279 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1280 /**
1281 * @}
1282 */
1283
1284 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1285 * @{
1286 */
1287 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1288 #if defined(COMP1)
1289 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1290 #endif /* COMP1 */
1291 #if defined(COMP2)
1292 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1293 #endif /* COMP2 */
1294 #if defined(PLAY1)
1295 #define LL_TIM_BKIN_SOURCE_PLAY1 TIM1_AF1_BKCMP3E /*!< internal signal: PLAY1 output */
1296 #endif /* PLAY1 */
1297 #if defined(MDF1)
1298 #define LL_TIM_BKIN_SOURCE_MDF1 TIM1_AF1_BKDF1BK0E /*!< internal signal: Digital filter break output */
1299 #endif /* MDF1 */
1300 /**
1301 * @}
1302 */
1303
1304 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1305 * @{
1306 */
1307 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1308 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1309 /**
1310 * @}
1311 */
1312
1313 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1314 * @{
1315 */
1316 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1317 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1318 /**
1319 * @}
1320 */
1321
1322 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1323 * @{
1324 */
1325 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1326 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1327 /**
1328 * @}
1329 */
1330
1331 /** Legacy definitions for compatibility purpose
1332 @cond 0
1333 */
1334 #define LL_TIM_ReArmBRK(_PARAM_)
1335 #define LL_TIM_ReArmBRK2(_PARAM_)
1336 /**
1337 @endcond
1338 */
1339
1340 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1341 * @{
1342 */
1343 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1344 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1345 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1346 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1347 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1348 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1349 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1350 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1351 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1352 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1353 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1354 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1355 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1356 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1357 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1358 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1359 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1360 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1361 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1362 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1363 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1364 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1365 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1366 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1367 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1368 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1369 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1370 /**
1371 * @}
1372 */
1373
1374 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1375 * @{
1376 */
1377 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1378 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1379 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1380 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1381 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1382 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1383 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1384 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1385 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1386 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1387 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1388 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1389 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1390 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1391 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1392 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1393 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1394 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1395 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1396 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1397 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1398 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1399 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1400 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1401 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1402 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1403 /**
1404 * @}
1405 */
1406
1407 /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
1408 * @{
1409 */
1410 #define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
1411 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
1412 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
1413 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
1414 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
1415 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
1416 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
1417 /**
1418 * @}
1419 */
1420 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1421 * @{
1422 */
1423 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */
1424 #if defined(COMP1) && defined(COMP2)
1425 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP1 output */
1426 #define LL_TIM_TIM1_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1_TI1 is connected to COMP2 output */
1427 #elif defined(COMP1)
1428 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 output */
1429 #endif /* COMP1 && COMP2 */
1430 /**
1431 * @}
1432 */
1433
1434 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
1435 * @{
1436 */
1437 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */
1438 #if defined(STM32H503xx)
1439 #define LL_TIM_TIM2_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to LSI */
1440 #define LL_TIM_TIM2_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to LSE */
1441 #define LL_TIM_TIM2_TI1_RMP_RTC (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to RTC */
1442 #define LL_TIM_TIM2_TI1_RMP_TIM3_TI1 TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to TIM3 TI1 */
1443 #endif /* STM32H503xx */
1444 #if defined(ETH_NS)
1445 #define LL_TIM_TIM2_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH PPS */
1446 #endif /* ETH_NS */
1447 #if defined(COMP1) && defined(COMP2)
1448 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP1 output */
1449 #define LL_TIM_TIM2_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to COMP2 output */
1450 #define LL_TIM_TIM2_TI1_RMP_PLAY1_OUT3 TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to PLAY1 output 3 */
1451 #endif /* COMP1 && COMP2 */
1452 /**
1453 * @}
1454 */
1455
1456 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 External Input Ch2 Remap
1457 * @{
1458 */
1459 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */
1460 #if defined(STM32H503xx)
1461 #define LL_TIM_TIM2_TI2_RMP_HSI_1024 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to HSI_1024 */
1462 #define LL_TIM_TIM2_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to CSI_128 */
1463 #define LL_TIM_TIM2_TI2_RMP_MCO2 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM2_TI2 is connected to MCO2 */
1464 #define LL_TIM_TIM2_TI2_RMP_MCO1 TIM_TISEL_TI2SEL_2 /*!< TIM2_TI2 is connected to MCO1 */
1465 #endif /* STM32H503xx */
1466 #if defined(COMP1) && defined(COMP2)
1467 #define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 output */
1468 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 output */
1469 #endif /* COMP1 && COMP2 */
1470 /**
1471 * @}
1472 */
1473
1474 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1475 * @{
1476 */
1477 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */
1478 #if defined(STM32H503xx)
1479 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 output */
1480 #endif /* STM32H503xx */
1481 /**
1482 * @}
1483 */
1484
1485 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1486 * @{
1487 */
1488 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */
1489 #if defined(STM32H503xx)
1490 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 output */
1491 #define LL_TIM_TIM3_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to MCO1 */
1492 #define LL_TIM_TIM3_TI1_RMP_TIM2_TI1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3_TI1 is connected to TIM2 TI1 */
1493 #define LL_TIM_TIM3_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_2 /*!< TIM3_TI1 is connected to HSE 1MHZ */
1494 #endif /* STM32H503xx */
1495 #if defined(ETH_NS)
1496 #define LL_TIM_TIM3_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to ETH PPS */
1497 #endif /* ETH_NS */
1498 #if defined(COMP1) && defined(COMP2)
1499 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP1 output */
1500 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3_TI1 is connected to COMP2 output */
1501 #define LL_TIM_TIM3_TI1_RMP_PLAY1_OUT3 TIM_TISEL_TI1SEL_2 /*!< TIM3_TI1 is connected to PLAY1 output 3 */
1502 #endif /* COMP1 && COMP2 */
1503 /**
1504 * @}
1505 */
1506
1507 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 External Input Ch2 Remap
1508 * @{
1509 */
1510 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */
1511 #if defined(STM32H503xx)
1512 #define LL_TIM_TIM3_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to CSI 128 */
1513 #define LL_TIM_TIM3_TI2_RMP_MCO2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to MCO2 */
1514 #define LL_TIM_TIM3_TI2_RMP_HSI_1024 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM3_TI2 is connected to HSI 1024 */
1515 #endif /* STM32H503xx */
1516 #if defined(COMP1) && defined(COMP2)
1517 #define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 output */
1518 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 output */
1519 #endif /* COMP1 && COMP2 */
1520 /**
1521 * @}
1522 */
1523
1524 #if defined(TIM4)
1525 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 External Input Ch1 Remap
1526 * @{
1527 */
1528 #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */
1529 #if defined(COMP1) && defined(COMP2)
1530 #define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP1 output */
1531 #define LL_TIM_TIM4_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4_TI1 is connected to COMP2 output */
1532 #endif /* COMP1 && COMP2 */
1533 /**
1534 * @}
1535 */
1536 #endif /* TIM4 */
1537
1538 #if defined(TIM5)
1539 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 External Input Ch1 Remap
1540 * @{
1541 */
1542 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */
1543 #if defined(COMP1) && defined(COMP2)
1544 #define LL_TIM_TIM5_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to COMP1 output */
1545 #define LL_TIM_TIM5_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to COMP2 output */
1546 #endif /* COMP1 && COMP2 */
1547 /**
1548 * @}
1549 */
1550 #endif /* TIM5 */
1551
1552 #if defined(TIM8)
1553 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
1554 * @{
1555 */
1556 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000UL /*!< TIM8_TI1 is connected to GPIO */
1557 #if defined(COMP1) && defined(COMP2)
1558 #define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM8_TI1 is connected to COMP1 output */
1559 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8_TI1 is connected to COMP2 output */
1560 #endif /* COMP1 && COMP2 */
1561 /**
1562 * @}
1563 */
1564 #endif /* TIM8 */
1565
1566 #if defined(TIM12)
1567 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 External Input Ch1 Remap
1568 * @{
1569 */
1570 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */
1571 #if defined(COMP1) && defined(COMP2)
1572 #define LL_TIM_TIM12_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM12_TI1 is connected to COMP1 output */
1573 #define LL_TIM_TIM12_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to COMP2 output */
1574 #endif /* COMP1 && COMP2 */
1575 #define LL_TIM_TIM12_TI1_RMP_HSI_1024 TIM_TISEL_TI1SEL_2 /*!< TIM12_TI1 is connected to HSI 1024 */
1576 #define LL_TIM_TIM12_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI 128 */
1577 /**
1578 * @}
1579 */
1580
1581 /** @defgroup TIM_LL_EC_TIM12_TI2_RMP TIM12 External Input Ch2 Remap
1582 * @{
1583 */
1584 #define LL_TIM_TIM12_TI2_RMP_GPIO 0x00000000UL /*!< TIM12_TI2 is connected to GPIO */
1585 #if defined(COMP2)
1586 #define LL_TIM_TIM12_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM12_TI2 is connected to COMP2 output */
1587 #endif /* COMP2 */
1588 /**
1589 * @}
1590 */
1591 #endif /* TIM12 */
1592
1593 #if defined(TIM13)
1594 /** @defgroup TIM_LL_EC_TIM13_TI1_RMP TIM13 External Input Ch1 Remap
1595 * @{
1596 */
1597 #define LL_TIM_TIM13_TI1_RMP_GPIO 0x00000000UL /*!< TIM13_TI1 is connected to GPIO */
1598 #if defined(I3C1)
1599 #define LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM13_TI1 is connected to I3C1 IBI ACK */
1600 #endif /* I3C1 */
1601 #if defined(COMP1) && defined(COMP2)
1602 #define LL_TIM_TIM13_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM13_TI1 is connected to COMP1 output */
1603 #define LL_TIM_TIM13_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM13_TI1 is connected to COMP2 output */
1604 #endif /* COMP1 && COMP2 */
1605 /**
1606 * @}
1607 */
1608 #endif /* TIM13 */
1609
1610 #if defined(TIM14)
1611 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 External Input Ch1 Remap
1612 * @{
1613 */
1614 #define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000UL /*!< TIM14_TI1 is connected to GPIO */
1615 #if defined(I3C2)
1616 #define LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM14_TI1 is connected to I3C2 IBI ACK */
1617 #endif /* I3C1 */
1618 #if defined(COMP1) && defined(COMP2)
1619 #define LL_TIM_TIM14_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM14_TI1 is connected to COMP1 output */
1620 #define LL_TIM_TIM14_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM14_TI1 is connected to COMP2 output */
1621 #endif /* COMP1 && COMP2 */
1622 /**
1623 * @}
1624 */
1625 #endif /* TIM14 */
1626
1627 #if defined(TIM15)
1628 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1629 * @{
1630 */
1631 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
1632 #define LL_TIM_TIM15_TI1_RMP_TIM2 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 */
1633 #define LL_TIM_TIM15_TI1_RMP_TIM3 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 */
1634 #define LL_TIM_TIM15_TI1_RMP_TIM4 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM4 */
1635 #define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to LSE */
1636 #define LL_TIM_TIM15_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to CSI 128*/
1637 #define LL_TIM_TIM15_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to MCO2 */
1638 #if defined(COMP1) && defined(COMP2)
1639 #define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_3 /*!< TIM15_TI1 is connected to COMP1 output */
1640 #define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to COMP2 output */
1641 #endif /* COMP1 && COMP2 */
1642 /**
1643 * @}
1644 */
1645
1646 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 External Input Ch2 Remap
1647 * @{
1648 */
1649 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
1650 #define LL_TIM_TIM15_TI2_RMP_TIM2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 */
1651 #define LL_TIM_TIM15_TI2_RMP_TIM3 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 */
1652 #define LL_TIM_TIM15_TI2_RMP_TIM4 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 */
1653 #if defined(COMP1) && defined(COMP2)
1654 #define LL_TIM_TIM15_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_2 /*!< TIM15_TI2 is connected to COMP1 output */
1655 #define LL_TIM_TIM15_TI2_RMP_COMP2 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to COMP2 output */
1656 #endif /* COMP1 && COMP2 */
1657 /**
1658 * @}
1659 */
1660 #endif /* TIM15 */
1661
1662 #if defined(TIM16)
1663 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1664 * @{
1665 */
1666 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */
1667 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16_TI1 is connected to LSI */
1668 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to LSE */
1669 #define LL_TIM_TIM16_TI1_RMP_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC */
1670 #if defined(COMP1) && defined(COMP2)
1671 #define LL_TIM_TIM16_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_3 /*!< TIM16_TI1 is connected to COMP1 output */
1672 #define LL_TIM_TIM16_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to COMP2 output */
1673 #endif /* COMP1 && COMP2 */
1674 /**
1675 * @}
1676 */
1677 #endif /* TIM16 */
1678
1679 #if defined(TIM17)
1680 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1681 * @{
1682 */
1683 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */
1684 #define LL_TIM_TIM17_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to HSE 1MHZ */
1685 #define LL_TIM_TIM17_TI1_RMP_MCO1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MCO1 */
1686 #if defined(COMP1) && defined(COMP2)
1687 #define LL_TIM_TIM17_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM17_TI1 is connected to COMP1 output */
1688 #define LL_TIM_TIM17_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to COMP2 output */
1689 #endif /* COMP1 && COMP2 */
1690 /**
1691 * @}
1692 */
1693 #endif /* TIM17 */
1694
1695 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1696 * @{
1697 */
1698 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */
1699 #if defined(COMP1) && defined(COMP2)
1700 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1701 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
1702 #endif /* COMP1 && COMP2 */
1703 /**
1704 * @}
1705 */
1706
1707 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1708 * @{
1709 */
1710 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1711 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1712 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1713 /**
1714 * @}
1715 */
1716
1717 /** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
1718 * @{
1719 */
1720 #define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
1721 #define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
1722 #define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
1723 /**
1724 * @}
1725 */
1726
1727 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1728 * @{
1729 */
1730 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1731 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1732 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1733 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1734 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1735 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1736 /**
1737 * @}
1738 */
1739
1740 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1741 * @{
1742 */
1743 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1744 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1745 /**
1746 * @}
1747 */
1748 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1749 * @{
1750 */
1751 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1752 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1753 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1754 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1755 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1756 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1757 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1758 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1759 /**
1760 * @}
1761 */
1762
1763 /** Legacy definitions for compatibility purpose
1764 @cond 0
1765 */
1766 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1767 /**
1768 @endcond
1769 */
1770
1771 /**
1772 * @}
1773 */
1774
1775 /* Exported macro ------------------------------------------------------------*/
1776 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1777 * @{
1778 */
1779
1780 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1781 * @{
1782 */
1783 /**
1784 * @brief Write a value in TIM register.
1785 * @param __INSTANCE__ TIM Instance
1786 * @param __REG__ Register to be written
1787 * @param __VALUE__ Value to be written in the register
1788 * @retval None
1789 */
1790 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1791
1792 /**
1793 * @brief Read a value in TIM register.
1794 * @param __INSTANCE__ TIM Instance
1795 * @param __REG__ Register to be read
1796 * @retval Register value
1797 */
1798 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1799 /**
1800 * @}
1801 */
1802
1803 /**
1804 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1805 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1806 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1807 * to TIMx_CNT register bit 31)
1808 * @param __CNT__ Counter value
1809 * @retval UIF status bit
1810 */
1811 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1812 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1813
1814 /**
1815 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1816 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1817 * @param __TIMCLK__ timer input clock frequency (in Hz)
1818 * @param __CKD__ This parameter can be one of the following values:
1819 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1820 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1821 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1822 * @param __DT__ deadtime duration (in ns)
1823 * @retval DTG[0:7]
1824 */
1825 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1826 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1827 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1828 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1829 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1830 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1831 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1832 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1833 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1834 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1835 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1836 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1837 0U)
1838
1839 /**
1840 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1841 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1842 * @param __TIMCLK__ timer input clock frequency (in Hz)
1843 * @param __CNTCLK__ counter clock frequency (in Hz)
1844 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1845 */
1846 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1847 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1848
1849 /**
1850 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1851 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1852 * @param __TIMCLK__ timer input clock frequency (in Hz)
1853 * @param __PSC__ prescaler
1854 * @param __FREQ__ output signal frequency (in Hz)
1855 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1856 */
1857 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1858 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1859
1860 /**
1861 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1862 * output signal frequency.
1863 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1864 * @param __TIMCLK__ timer input clock frequency (in Hz)
1865 * @param __PSC__ prescaler
1866 * @param __FREQ__ output signal frequency (in Hz)
1867 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1868 */
1869 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1870 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1871 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1872
1873 /**
1874 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1875 * active/inactive delay.
1876 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1877 * @param __TIMCLK__ timer input clock frequency (in Hz)
1878 * @param __PSC__ prescaler
1879 * @param __DELAY__ timer output compare active/inactive delay (in us)
1880 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1881 */
1882 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1883 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1884 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1885
1886 /**
1887 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1888 * output compare active/inactive delay.
1889 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1890 * @param __TIMCLK__ timer input clock frequency (in Hz)
1891 * @param __PSC__ prescaler
1892 * @param __DELAY__ timer output compare active/inactive delay (in us)
1893 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1894 */
1895 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1896 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1897 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1898
1899 /**
1900 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1901 * (when the timer operates in one pulse mode).
1902 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1903 * @param __TIMCLK__ timer input clock frequency (in Hz)
1904 * @param __PSC__ prescaler
1905 * @param __DELAY__ timer output compare active/inactive delay (in us)
1906 * @param __PULSE__ pulse duration (in us)
1907 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1908 */
1909 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1910 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1911 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1912
1913 /**
1914 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1915 * pulse duration (when the timer operates in one pulse mode).
1916 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1917 * @param __TIMCLK__ timer input clock frequency (in Hz)
1918 * @param __PSC__ prescaler
1919 * @param __DELAY__ timer output compare active/inactive delay (in us)
1920 * @param __PULSE__ pulse duration (in us)
1921 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1922 */
1923 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1924 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1925 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1926
1927 /**
1928 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1929 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1930 * @param __ICPSC__ This parameter can be one of the following values:
1931 * @arg @ref LL_TIM_ICPSC_DIV1
1932 * @arg @ref LL_TIM_ICPSC_DIV2
1933 * @arg @ref LL_TIM_ICPSC_DIV4
1934 * @arg @ref LL_TIM_ICPSC_DIV8
1935 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1936 */
1937 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1938 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1939
1940
1941 /**
1942 * @}
1943 */
1944
1945 /* Exported functions --------------------------------------------------------*/
1946 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1947 * @{
1948 */
1949
1950 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1951 * @{
1952 */
1953 /**
1954 * @brief Enable timer counter.
1955 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1956 * @param TIMx Timer instance
1957 * @retval None
1958 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1959 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1960 {
1961 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1962 }
1963
1964 /**
1965 * @brief Disable timer counter.
1966 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1967 * @param TIMx Timer instance
1968 * @retval None
1969 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1970 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1971 {
1972 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1973 }
1974
1975 /**
1976 * @brief Indicates whether the timer counter is enabled.
1977 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1978 * @param TIMx Timer instance
1979 * @retval State of bit (1 or 0).
1980 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1981 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1982 {
1983 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1984 }
1985
1986 /**
1987 * @brief Enable update event generation.
1988 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1989 * @param TIMx Timer instance
1990 * @retval None
1991 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1992 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1993 {
1994 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1995 }
1996
1997 /**
1998 * @brief Disable update event generation.
1999 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
2000 * @param TIMx Timer instance
2001 * @retval None
2002 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)2003 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
2004 {
2005 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
2006 }
2007
2008 /**
2009 * @brief Indicates whether update event generation is enabled.
2010 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
2011 * @param TIMx Timer instance
2012 * @retval Inverted state of bit (0 or 1).
2013 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)2014 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
2015 {
2016 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
2017 }
2018
2019 /**
2020 * @brief Set update event source
2021 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
2022 * generate an update interrupt or DMA request if enabled:
2023 * - Counter overflow/underflow
2024 * - Setting the UG bit
2025 * - Update generation through the slave mode controller
2026 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
2027 * overflow/underflow generates an update interrupt or DMA request if enabled.
2028 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
2029 * @param TIMx Timer instance
2030 * @param UpdateSource This parameter can be one of the following values:
2031 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
2032 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
2033 * @retval None
2034 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)2035 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
2036 {
2037 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
2038 }
2039
2040 /**
2041 * @brief Get actual event update source
2042 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
2043 * @param TIMx Timer instance
2044 * @retval Returned value can be one of the following values:
2045 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
2046 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
2047 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)2048 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
2049 {
2050 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
2051 }
2052
2053 /**
2054 * @brief Set one pulse mode (one shot v.s. repetitive).
2055 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
2056 * @param TIMx Timer instance
2057 * @param OnePulseMode This parameter can be one of the following values:
2058 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2059 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2060 * @retval None
2061 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)2062 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
2063 {
2064 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
2065 }
2066
2067 /**
2068 * @brief Get actual one pulse mode.
2069 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
2070 * @param TIMx Timer instance
2071 * @retval Returned value can be one of the following values:
2072 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2073 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2074 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)2075 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
2076 {
2077 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
2078 }
2079
2080 /**
2081 * @brief Set the timer counter counting mode.
2082 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2083 * check whether or not the counter mode selection feature is supported
2084 * by a timer instance.
2085 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2086 * requires a timer reset to avoid unexpected direction
2087 * due to DIR bit readonly in center aligned mode.
2088 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
2089 * CR1 CMS LL_TIM_SetCounterMode
2090 * @param TIMx Timer instance
2091 * @param CounterMode This parameter can be one of the following values:
2092 * @arg @ref LL_TIM_COUNTERMODE_UP
2093 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2094 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2095 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2096 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2097 * @retval None
2098 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)2099 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
2100 {
2101 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
2102 }
2103
2104 /**
2105 * @brief Get actual counter mode.
2106 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2107 * check whether or not the counter mode selection feature is supported
2108 * by a timer instance.
2109 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
2110 * CR1 CMS LL_TIM_GetCounterMode
2111 * @param TIMx Timer instance
2112 * @retval Returned value can be one of the following values:
2113 * @arg @ref LL_TIM_COUNTERMODE_UP
2114 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2115 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2116 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2117 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2118 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)2119 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
2120 {
2121 uint32_t counter_mode;
2122
2123 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
2124
2125 if (counter_mode == 0U)
2126 {
2127 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2128 }
2129
2130 return counter_mode;
2131 }
2132
2133 /**
2134 * @brief Enable auto-reload (ARR) preload.
2135 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
2136 * @param TIMx Timer instance
2137 * @retval None
2138 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)2139 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
2140 {
2141 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
2142 }
2143
2144 /**
2145 * @brief Disable auto-reload (ARR) preload.
2146 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
2147 * @param TIMx Timer instance
2148 * @retval None
2149 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)2150 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
2151 {
2152 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
2153 }
2154
2155 /**
2156 * @brief Indicates whether auto-reload (ARR) preload is enabled.
2157 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
2158 * @param TIMx Timer instance
2159 * @retval State of bit (1 or 0).
2160 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)2161 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
2162 {
2163 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
2164 }
2165
2166 /**
2167 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
2168 * (when supported) and the digital filters.
2169 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2170 * whether or not the clock division feature is supported by the timer
2171 * instance.
2172 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
2173 * @param TIMx Timer instance
2174 * @param ClockDivision This parameter can be one of the following values:
2175 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2176 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2178 * @retval None
2179 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)2180 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
2181 {
2182 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
2183 }
2184
2185 /**
2186 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
2187 * generators (when supported) and the digital filters.
2188 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2189 * whether or not the clock division feature is supported by the timer
2190 * instance.
2191 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
2192 * @param TIMx Timer instance
2193 * @retval Returned value can be one of the following values:
2194 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2195 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2196 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2197 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)2198 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
2199 {
2200 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
2201 }
2202
2203 /**
2204 * @brief Set the counter value.
2205 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2206 * whether or not a timer instance supports a 32 bits counter.
2207 * @note If dithering is activated, pay attention to the Counter value interpretation
2208 * @rmtoll CNT CNT LL_TIM_SetCounter
2209 * @param TIMx Timer instance
2210 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2211 * @retval None
2212 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)2213 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
2214 {
2215 WRITE_REG(TIMx->CNT, Counter);
2216 }
2217
2218 /**
2219 * @brief Get the counter value.
2220 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2221 * whether or not a timer instance supports a 32 bits counter.
2222 * @note If dithering is activated, pay attention to the Counter value interpretation
2223 * @rmtoll CNT CNT LL_TIM_GetCounter
2224 * @param TIMx Timer instance
2225 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2226 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)2227 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
2228 {
2229 return (uint32_t)(READ_REG(TIMx->CNT));
2230 }
2231
2232 /**
2233 * @brief Get the current direction of the counter
2234 * @rmtoll CR1 DIR LL_TIM_GetDirection
2235 * @param TIMx Timer instance
2236 * @retval Returned value can be one of the following values:
2237 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
2238 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
2239 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)2240 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
2241 {
2242 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2243 }
2244
2245 /**
2246 * @brief Set the prescaler value.
2247 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
2248 * @note The prescaler can be changed on the fly as this control register is buffered. The new
2249 * prescaler ratio is taken into account at the next update event.
2250 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
2251 * @rmtoll PSC PSC LL_TIM_SetPrescaler
2252 * @param TIMx Timer instance
2253 * @param Prescaler between Min_Data=0 and Max_Data=65535
2254 * @retval None
2255 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)2256 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
2257 {
2258 WRITE_REG(TIMx->PSC, Prescaler);
2259 }
2260
2261 /**
2262 * @brief Get the prescaler value.
2263 * @rmtoll PSC PSC LL_TIM_GetPrescaler
2264 * @param TIMx Timer instance
2265 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
2266 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)2267 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
2268 {
2269 return (uint32_t)(READ_REG(TIMx->PSC));
2270 }
2271
2272 /**
2273 * @brief Set the auto-reload value.
2274 * @note The counter is blocked while the auto-reload value is null.
2275 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2276 * whether or not a timer instance supports a 32 bits counter.
2277 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
2278 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
2279 * parameter.
2280 * @rmtoll ARR ARR LL_TIM_SetAutoReload
2281 * @param TIMx Timer instance
2282 * @param AutoReload between Min_Data=0 and Max_Data=65535
2283 * @retval None
2284 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)2285 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
2286 {
2287 WRITE_REG(TIMx->ARR, AutoReload);
2288 }
2289
2290 /**
2291 * @brief Get the auto-reload value.
2292 * @rmtoll ARR ARR LL_TIM_GetAutoReload
2293 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2294 * whether or not a timer instance supports a 32 bits counter.
2295 * @note If dithering is activated, pay attention to the returned value interpretation
2296 * @param TIMx Timer instance
2297 * @retval Auto-reload value
2298 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)2299 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
2300 {
2301 return (uint32_t)(READ_REG(TIMx->ARR));
2302 }
2303
2304 /**
2305 * @brief Set the repetition counter value.
2306 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2307 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2308 * whether or not a timer instance supports a repetition counter.
2309 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2310 * @param TIMx Timer instance
2311 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2312 * @retval None
2313 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2314 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2315 {
2316 WRITE_REG(TIMx->RCR, RepetitionCounter);
2317 }
2318
2319 /**
2320 * @brief Get the repetition counter value.
2321 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2322 * whether or not a timer instance supports a repetition counter.
2323 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2324 * @param TIMx Timer instance
2325 * @retval Repetition counter value
2326 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2327 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2328 {
2329 return (uint32_t)(READ_REG(TIMx->RCR));
2330 }
2331
2332 /**
2333 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2334 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2335 * in an atomic way.
2336 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2337 * @param TIMx Timer instance
2338 * @retval None
2339 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2340 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2341 {
2342 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2343 }
2344
2345 /**
2346 * @brief Disable update interrupt flag (UIF) remapping.
2347 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2348 * @param TIMx Timer instance
2349 * @retval None
2350 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2351 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2352 {
2353 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2354 }
2355
2356 /**
2357 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2358 * @param Counter Counter value
2359 * @retval State of bit (1 or 0).
2360 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2361 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2362 {
2363 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2364 }
2365
2366 /**
2367 * @brief Enable dithering.
2368 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2369 * a timer instance provides dithering.
2370 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2371 * @param TIMx Timer instance
2372 * @retval None
2373 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2374 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2375 {
2376 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2377 }
2378
2379 /**
2380 * @brief Disable dithering.
2381 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2382 * a timer instance provides dithering.
2383 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2384 * @param TIMx Timer instance
2385 * @retval None
2386 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2387 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2388 {
2389 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2390 }
2391
2392 /**
2393 * @brief Indicates whether dithering is activated.
2394 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2395 * a timer instance provides dithering.
2396 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2397 * @param TIMx Timer instance
2398 * @retval State of bit (1 or 0).
2399 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2400 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2401 {
2402 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2403 }
2404
2405 /**
2406 * @}
2407 */
2408
2409 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2410 * @{
2411 */
2412 /**
2413 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2414 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2415 * they are updated only when a commutation event (COM) occurs.
2416 * @note Only on channels that have a complementary output.
2417 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2418 * whether or not a timer instance is able to generate a commutation event.
2419 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2420 * @param TIMx Timer instance
2421 * @retval None
2422 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2423 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2424 {
2425 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2426 }
2427
2428 /**
2429 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2430 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2431 * whether or not a timer instance is able to generate a commutation event.
2432 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2433 * @param TIMx Timer instance
2434 * @retval None
2435 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2436 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2437 {
2438 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2439 }
2440
2441 /**
2442 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
2443 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
2444 * @param TIMx Timer instance
2445 * @retval State of bit (1 or 0).
2446 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)2447 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
2448 {
2449 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
2450 }
2451
2452 /**
2453 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2454 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2455 * whether or not a timer instance is able to generate a commutation event.
2456 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2457 * @param TIMx Timer instance
2458 * @param CCUpdateSource This parameter can be one of the following values:
2459 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2460 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2461 * @retval None
2462 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2463 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2464 {
2465 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2466 }
2467
2468 /**
2469 * @brief Set the trigger of the capture/compare DMA request.
2470 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2471 * @param TIMx Timer instance
2472 * @param DMAReqTrigger This parameter can be one of the following values:
2473 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2474 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2475 * @retval None
2476 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2477 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2478 {
2479 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2480 }
2481
2482 /**
2483 * @brief Get actual trigger of the capture/compare DMA request.
2484 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2485 * @param TIMx Timer instance
2486 * @retval Returned value can be one of the following values:
2487 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2488 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2489 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2490 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2491 {
2492 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2493 }
2494
2495 /**
2496 * @brief Set the lock level to freeze the
2497 * configuration of several capture/compare parameters.
2498 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2499 * the lock mechanism is supported by a timer instance.
2500 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2501 * @param TIMx Timer instance
2502 * @param LockLevel This parameter can be one of the following values:
2503 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2504 * @arg @ref LL_TIM_LOCKLEVEL_1
2505 * @arg @ref LL_TIM_LOCKLEVEL_2
2506 * @arg @ref LL_TIM_LOCKLEVEL_3
2507 * @retval None
2508 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2509 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2510 {
2511 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2512 }
2513
2514 /**
2515 * @brief Enable capture/compare channels.
2516 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2517 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2518 * CCER CC2E LL_TIM_CC_EnableChannel\n
2519 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2520 * CCER CC3E LL_TIM_CC_EnableChannel\n
2521 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2522 * CCER CC4E LL_TIM_CC_EnableChannel\n
2523 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2524 * CCER CC5E LL_TIM_CC_EnableChannel\n
2525 * CCER CC6E LL_TIM_CC_EnableChannel
2526 * @param TIMx Timer instance
2527 * @param Channels This parameter can be a combination of the following values:
2528 * @arg @ref LL_TIM_CHANNEL_CH1
2529 * @arg @ref LL_TIM_CHANNEL_CH1N
2530 * @arg @ref LL_TIM_CHANNEL_CH2
2531 * @arg @ref LL_TIM_CHANNEL_CH2N
2532 * @arg @ref LL_TIM_CHANNEL_CH3
2533 * @arg @ref LL_TIM_CHANNEL_CH3N
2534 * @arg @ref LL_TIM_CHANNEL_CH4
2535 * @arg @ref LL_TIM_CHANNEL_CH4N
2536 * @arg @ref LL_TIM_CHANNEL_CH5
2537 * @arg @ref LL_TIM_CHANNEL_CH6
2538 * @retval None
2539 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2540 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2541 {
2542 SET_BIT(TIMx->CCER, Channels);
2543 }
2544
2545 /**
2546 * @brief Disable capture/compare channels.
2547 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2548 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2549 * CCER CC2E LL_TIM_CC_DisableChannel\n
2550 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2551 * CCER CC3E LL_TIM_CC_DisableChannel\n
2552 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2553 * CCER CC4E LL_TIM_CC_DisableChannel\n
2554 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2555 * CCER CC5E LL_TIM_CC_DisableChannel\n
2556 * CCER CC6E LL_TIM_CC_DisableChannel
2557 * @param TIMx Timer instance
2558 * @param Channels This parameter can be a combination of the following values:
2559 * @arg @ref LL_TIM_CHANNEL_CH1
2560 * @arg @ref LL_TIM_CHANNEL_CH1N
2561 * @arg @ref LL_TIM_CHANNEL_CH2
2562 * @arg @ref LL_TIM_CHANNEL_CH2N
2563 * @arg @ref LL_TIM_CHANNEL_CH3
2564 * @arg @ref LL_TIM_CHANNEL_CH3N
2565 * @arg @ref LL_TIM_CHANNEL_CH4
2566 * @arg @ref LL_TIM_CHANNEL_CH4N
2567 * @arg @ref LL_TIM_CHANNEL_CH5
2568 * @arg @ref LL_TIM_CHANNEL_CH6
2569 * @retval None
2570 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2571 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2572 {
2573 CLEAR_BIT(TIMx->CCER, Channels);
2574 }
2575
2576 /**
2577 * @brief Indicate whether channel(s) is(are) enabled.
2578 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2579 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2580 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2581 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2582 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2583 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2584 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2585 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2586 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2587 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2588 * @param TIMx Timer instance
2589 * @param Channels This parameter can be a combination of the following values:
2590 * @arg @ref LL_TIM_CHANNEL_CH1
2591 * @arg @ref LL_TIM_CHANNEL_CH1N
2592 * @arg @ref LL_TIM_CHANNEL_CH2
2593 * @arg @ref LL_TIM_CHANNEL_CH2N
2594 * @arg @ref LL_TIM_CHANNEL_CH3
2595 * @arg @ref LL_TIM_CHANNEL_CH3N
2596 * @arg @ref LL_TIM_CHANNEL_CH4
2597 * @arg @ref LL_TIM_CHANNEL_CH4N
2598 * @arg @ref LL_TIM_CHANNEL_CH5
2599 * @arg @ref LL_TIM_CHANNEL_CH6
2600 * @retval State of bit (1 or 0).
2601 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2602 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2603 {
2604 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2605 }
2606
2607 /**
2608 * @}
2609 */
2610
2611 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2612 * @{
2613 */
2614 /**
2615 * @brief Configure an output channel.
2616 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2617 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2618 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2619 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2620 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2621 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2622 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2623 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2624 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2625 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2626 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2627 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2628 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2629 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2630 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2631 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2632 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2633 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2634 * @param TIMx Timer instance
2635 * @param Channel This parameter can be one of the following values:
2636 * @arg @ref LL_TIM_CHANNEL_CH1
2637 * @arg @ref LL_TIM_CHANNEL_CH2
2638 * @arg @ref LL_TIM_CHANNEL_CH3
2639 * @arg @ref LL_TIM_CHANNEL_CH4
2640 * @arg @ref LL_TIM_CHANNEL_CH5
2641 * @arg @ref LL_TIM_CHANNEL_CH6
2642 * @param Configuration This parameter must be a combination of all the following values:
2643 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2644 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2645 * @retval None
2646 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2647 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2648 {
2649 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2650 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2651 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2652 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2653 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2654 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2655 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2656 }
2657
2658 /**
2659 * @brief Define the behavior of the output reference signal OCxREF from which
2660 * OCx and OCxN (when relevant) are derived.
2661 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2662 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2663 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2664 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2665 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2666 * CCMR3 OC6M LL_TIM_OC_SetMode
2667 * @param TIMx Timer instance
2668 * @param Channel This parameter can be one of the following values:
2669 * @arg @ref LL_TIM_CHANNEL_CH1
2670 * @arg @ref LL_TIM_CHANNEL_CH2
2671 * @arg @ref LL_TIM_CHANNEL_CH3
2672 * @arg @ref LL_TIM_CHANNEL_CH4
2673 * @arg @ref LL_TIM_CHANNEL_CH5
2674 * @arg @ref LL_TIM_CHANNEL_CH6
2675 * @param Mode This parameter can be one of the following values:
2676 * @arg @ref LL_TIM_OCMODE_FROZEN
2677 * @arg @ref LL_TIM_OCMODE_ACTIVE
2678 * @arg @ref LL_TIM_OCMODE_INACTIVE
2679 * @arg @ref LL_TIM_OCMODE_TOGGLE
2680 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2681 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2682 * @arg @ref LL_TIM_OCMODE_PWM1
2683 * @arg @ref LL_TIM_OCMODE_PWM2
2684 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2685 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2686 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2687 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2688 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2689 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2690 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2691 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2692 * @retval None
2693 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2694 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2695 {
2696 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2697 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2698 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2699 }
2700
2701 /**
2702 * @brief Get the output compare mode of an output channel.
2703 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2704 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2705 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2706 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2707 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2708 * CCMR3 OC6M LL_TIM_OC_GetMode
2709 * @param TIMx Timer instance
2710 * @param Channel This parameter can be one of the following values:
2711 * @arg @ref LL_TIM_CHANNEL_CH1
2712 * @arg @ref LL_TIM_CHANNEL_CH2
2713 * @arg @ref LL_TIM_CHANNEL_CH3
2714 * @arg @ref LL_TIM_CHANNEL_CH4
2715 * @arg @ref LL_TIM_CHANNEL_CH5
2716 * @arg @ref LL_TIM_CHANNEL_CH6
2717 * @retval Returned value can be one of the following values:
2718 * @arg @ref LL_TIM_OCMODE_FROZEN
2719 * @arg @ref LL_TIM_OCMODE_ACTIVE
2720 * @arg @ref LL_TIM_OCMODE_INACTIVE
2721 * @arg @ref LL_TIM_OCMODE_TOGGLE
2722 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2723 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2724 * @arg @ref LL_TIM_OCMODE_PWM1
2725 * @arg @ref LL_TIM_OCMODE_PWM2
2726 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2727 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2728 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2729 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2730 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2731 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2732 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2733 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2734 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2735 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2736 {
2737 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2738 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2739 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2740 }
2741
2742 /**
2743 * @brief Set the polarity of an output channel.
2744 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2745 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2746 * CCER CC2P LL_TIM_OC_SetPolarity\n
2747 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2748 * CCER CC3P LL_TIM_OC_SetPolarity\n
2749 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2750 * CCER CC4P LL_TIM_OC_SetPolarity\n
2751 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2752 * CCER CC5P LL_TIM_OC_SetPolarity\n
2753 * CCER CC6P LL_TIM_OC_SetPolarity
2754 * @param TIMx Timer instance
2755 * @param Channel This parameter can be one of the following values:
2756 * @arg @ref LL_TIM_CHANNEL_CH1
2757 * @arg @ref LL_TIM_CHANNEL_CH1N
2758 * @arg @ref LL_TIM_CHANNEL_CH2
2759 * @arg @ref LL_TIM_CHANNEL_CH2N
2760 * @arg @ref LL_TIM_CHANNEL_CH3
2761 * @arg @ref LL_TIM_CHANNEL_CH3N
2762 * @arg @ref LL_TIM_CHANNEL_CH4
2763 * @arg @ref LL_TIM_CHANNEL_CH4N
2764 * @arg @ref LL_TIM_CHANNEL_CH5
2765 * @arg @ref LL_TIM_CHANNEL_CH6
2766 * @param Polarity This parameter can be one of the following values:
2767 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2768 * @arg @ref LL_TIM_OCPOLARITY_LOW
2769 * @retval None
2770 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2771 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2772 {
2773 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2774 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2775 }
2776
2777 /**
2778 * @brief Get the polarity of an output channel.
2779 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2780 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2781 * CCER CC2P LL_TIM_OC_GetPolarity\n
2782 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2783 * CCER CC3P LL_TIM_OC_GetPolarity\n
2784 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2785 * CCER CC4P LL_TIM_OC_GetPolarity\n
2786 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2787 * CCER CC5P LL_TIM_OC_GetPolarity\n
2788 * CCER CC6P LL_TIM_OC_GetPolarity
2789 * @param TIMx Timer instance
2790 * @param Channel This parameter can be one of the following values:
2791 * @arg @ref LL_TIM_CHANNEL_CH1
2792 * @arg @ref LL_TIM_CHANNEL_CH1N
2793 * @arg @ref LL_TIM_CHANNEL_CH2
2794 * @arg @ref LL_TIM_CHANNEL_CH2N
2795 * @arg @ref LL_TIM_CHANNEL_CH3
2796 * @arg @ref LL_TIM_CHANNEL_CH3N
2797 * @arg @ref LL_TIM_CHANNEL_CH4
2798 * @arg @ref LL_TIM_CHANNEL_CH4N
2799 * @arg @ref LL_TIM_CHANNEL_CH5
2800 * @arg @ref LL_TIM_CHANNEL_CH6
2801 * @retval Returned value can be one of the following values:
2802 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2803 * @arg @ref LL_TIM_OCPOLARITY_LOW
2804 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2805 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2806 {
2807 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2808 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2809 }
2810
2811 /**
2812 * @brief Set the IDLE state of an output channel
2813 * @note This function is significant only for the timer instances
2814 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2815 * can be used to check whether or not a timer instance provides
2816 * a break input.
2817 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2818 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2819 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2820 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2821 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2822 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2823 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2824 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2825 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2826 * CR2 OIS6 LL_TIM_OC_SetIdleState
2827 * @param TIMx Timer instance
2828 * @param Channel This parameter can be one of the following values:
2829 * @arg @ref LL_TIM_CHANNEL_CH1
2830 * @arg @ref LL_TIM_CHANNEL_CH1N
2831 * @arg @ref LL_TIM_CHANNEL_CH2
2832 * @arg @ref LL_TIM_CHANNEL_CH2N
2833 * @arg @ref LL_TIM_CHANNEL_CH3
2834 * @arg @ref LL_TIM_CHANNEL_CH3N
2835 * @arg @ref LL_TIM_CHANNEL_CH4
2836 * @arg @ref LL_TIM_CHANNEL_CH4N
2837 * @arg @ref LL_TIM_CHANNEL_CH5
2838 * @arg @ref LL_TIM_CHANNEL_CH6
2839 * @param IdleState This parameter can be one of the following values:
2840 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2841 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2842 * @retval None
2843 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2844 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2845 {
2846 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2847 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2848 }
2849
2850 /**
2851 * @brief Get the IDLE state of an output channel
2852 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2853 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2854 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2855 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2856 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2857 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2858 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2859 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2860 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2861 * CR2 OIS6 LL_TIM_OC_GetIdleState
2862 * @param TIMx Timer instance
2863 * @param Channel This parameter can be one of the following values:
2864 * @arg @ref LL_TIM_CHANNEL_CH1
2865 * @arg @ref LL_TIM_CHANNEL_CH1N
2866 * @arg @ref LL_TIM_CHANNEL_CH2
2867 * @arg @ref LL_TIM_CHANNEL_CH2N
2868 * @arg @ref LL_TIM_CHANNEL_CH3
2869 * @arg @ref LL_TIM_CHANNEL_CH3N
2870 * @arg @ref LL_TIM_CHANNEL_CH4
2871 * @arg @ref LL_TIM_CHANNEL_CH4N
2872 * @arg @ref LL_TIM_CHANNEL_CH5
2873 * @arg @ref LL_TIM_CHANNEL_CH6
2874 * @retval Returned value can be one of the following values:
2875 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2876 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2877 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2878 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2879 {
2880 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2881 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2882 }
2883
2884 /**
2885 * @brief Enable fast mode for the output channel.
2886 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2887 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2888 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2889 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2890 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2891 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2892 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2893 * @param TIMx Timer instance
2894 * @param Channel This parameter can be one of the following values:
2895 * @arg @ref LL_TIM_CHANNEL_CH1
2896 * @arg @ref LL_TIM_CHANNEL_CH2
2897 * @arg @ref LL_TIM_CHANNEL_CH3
2898 * @arg @ref LL_TIM_CHANNEL_CH4
2899 * @arg @ref LL_TIM_CHANNEL_CH5
2900 * @arg @ref LL_TIM_CHANNEL_CH6
2901 * @retval None
2902 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2903 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2904 {
2905 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2906 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2907 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2908
2909 }
2910
2911 /**
2912 * @brief Disable fast mode for the output channel.
2913 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2914 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2915 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2916 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2917 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2918 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2919 * @param TIMx Timer instance
2920 * @param Channel This parameter can be one of the following values:
2921 * @arg @ref LL_TIM_CHANNEL_CH1
2922 * @arg @ref LL_TIM_CHANNEL_CH2
2923 * @arg @ref LL_TIM_CHANNEL_CH3
2924 * @arg @ref LL_TIM_CHANNEL_CH4
2925 * @arg @ref LL_TIM_CHANNEL_CH5
2926 * @arg @ref LL_TIM_CHANNEL_CH6
2927 * @retval None
2928 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2929 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2930 {
2931 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2932 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2933 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2934
2935 }
2936
2937 /**
2938 * @brief Indicates whether fast mode is enabled for the output channel.
2939 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2940 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2941 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2942 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2943 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2944 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2945 * @param TIMx Timer instance
2946 * @param Channel This parameter can be one of the following values:
2947 * @arg @ref LL_TIM_CHANNEL_CH1
2948 * @arg @ref LL_TIM_CHANNEL_CH2
2949 * @arg @ref LL_TIM_CHANNEL_CH3
2950 * @arg @ref LL_TIM_CHANNEL_CH4
2951 * @arg @ref LL_TIM_CHANNEL_CH5
2952 * @arg @ref LL_TIM_CHANNEL_CH6
2953 * @retval State of bit (1 or 0).
2954 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2955 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2956 {
2957 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2958 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2959 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2960 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2961 }
2962
2963 /**
2964 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2965 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2966 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2967 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2968 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2969 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2970 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2971 * @param TIMx Timer instance
2972 * @param Channel This parameter can be one of the following values:
2973 * @arg @ref LL_TIM_CHANNEL_CH1
2974 * @arg @ref LL_TIM_CHANNEL_CH2
2975 * @arg @ref LL_TIM_CHANNEL_CH3
2976 * @arg @ref LL_TIM_CHANNEL_CH4
2977 * @arg @ref LL_TIM_CHANNEL_CH5
2978 * @arg @ref LL_TIM_CHANNEL_CH6
2979 * @retval None
2980 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2981 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2982 {
2983 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2984 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2985 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2986 }
2987
2988 /**
2989 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2990 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2991 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2992 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2993 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2994 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2995 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2996 * @param TIMx Timer instance
2997 * @param Channel This parameter can be one of the following values:
2998 * @arg @ref LL_TIM_CHANNEL_CH1
2999 * @arg @ref LL_TIM_CHANNEL_CH2
3000 * @arg @ref LL_TIM_CHANNEL_CH3
3001 * @arg @ref LL_TIM_CHANNEL_CH4
3002 * @arg @ref LL_TIM_CHANNEL_CH5
3003 * @arg @ref LL_TIM_CHANNEL_CH6
3004 * @retval None
3005 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)3006 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
3007 {
3008 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3009 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3010 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
3011 }
3012
3013 /**
3014 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
3015 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
3016 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
3017 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
3018 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
3019 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
3020 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
3021 * @param TIMx Timer instance
3022 * @param Channel This parameter can be one of the following values:
3023 * @arg @ref LL_TIM_CHANNEL_CH1
3024 * @arg @ref LL_TIM_CHANNEL_CH2
3025 * @arg @ref LL_TIM_CHANNEL_CH3
3026 * @arg @ref LL_TIM_CHANNEL_CH4
3027 * @arg @ref LL_TIM_CHANNEL_CH5
3028 * @arg @ref LL_TIM_CHANNEL_CH6
3029 * @retval State of bit (1 or 0).
3030 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)3031 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
3032 {
3033 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3034 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3035 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
3036 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3037 }
3038
3039 /**
3040 * @brief Enable clearing the output channel on an external event.
3041 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3042 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3043 * or not a timer instance can clear the OCxREF signal on an external event.
3044 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
3045 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
3046 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
3047 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
3048 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
3049 * CCMR3 OC6CE LL_TIM_OC_EnableClear
3050 * @param TIMx Timer instance
3051 * @param Channel This parameter can be one of the following values:
3052 * @arg @ref LL_TIM_CHANNEL_CH1
3053 * @arg @ref LL_TIM_CHANNEL_CH2
3054 * @arg @ref LL_TIM_CHANNEL_CH3
3055 * @arg @ref LL_TIM_CHANNEL_CH4
3056 * @arg @ref LL_TIM_CHANNEL_CH5
3057 * @arg @ref LL_TIM_CHANNEL_CH6
3058 * @retval None
3059 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)3060 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3061 {
3062 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3063 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3064 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3065 }
3066
3067 /**
3068 * @brief Disable clearing the output channel on an external event.
3069 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3070 * or not a timer instance can clear the OCxREF signal on an external event.
3071 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
3072 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
3073 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
3074 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
3075 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
3076 * CCMR3 OC6CE LL_TIM_OC_DisableClear
3077 * @param TIMx Timer instance
3078 * @param Channel This parameter can be one of the following values:
3079 * @arg @ref LL_TIM_CHANNEL_CH1
3080 * @arg @ref LL_TIM_CHANNEL_CH2
3081 * @arg @ref LL_TIM_CHANNEL_CH3
3082 * @arg @ref LL_TIM_CHANNEL_CH4
3083 * @arg @ref LL_TIM_CHANNEL_CH5
3084 * @arg @ref LL_TIM_CHANNEL_CH6
3085 * @retval None
3086 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)3087 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3088 {
3089 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3090 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3091 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3092 }
3093
3094 /**
3095 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
3096 * @note This function enables clearing the output channel on an external event.
3097 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3098 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3099 * or not a timer instance can clear the OCxREF signal on an external event.
3100 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
3101 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
3102 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
3103 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
3104 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
3105 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
3106 * @param TIMx Timer instance
3107 * @param Channel This parameter can be one of the following values:
3108 * @arg @ref LL_TIM_CHANNEL_CH1
3109 * @arg @ref LL_TIM_CHANNEL_CH2
3110 * @arg @ref LL_TIM_CHANNEL_CH3
3111 * @arg @ref LL_TIM_CHANNEL_CH4
3112 * @arg @ref LL_TIM_CHANNEL_CH5
3113 * @arg @ref LL_TIM_CHANNEL_CH6
3114 * @retval State of bit (1 or 0).
3115 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)3116 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
3117 {
3118 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3119 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3120 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
3121 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3122 }
3123
3124 /**
3125 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
3126 * the Ocx and OCxN signals).
3127 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3128 * dead-time insertion feature is supported by a timer instance.
3129 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
3130 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
3131 * @param TIMx Timer instance
3132 * @param DeadTime between Min_Data=0 and Max_Data=255
3133 * @retval None
3134 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)3135 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
3136 {
3137 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
3138 }
3139
3140 /**
3141 * @brief Set compare value for output channel 1 (TIMx_CCR1).
3142 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3143 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3144 * whether or not a timer instance supports a 32 bits counter.
3145 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3146 * output channel 1 is supported by a timer instance.
3147 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3148 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
3149 * @param TIMx Timer instance
3150 * @param CompareValue between Min_Data=0 and Max_Data=65535
3151 * @retval None
3152 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)3153 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
3154 {
3155 WRITE_REG(TIMx->CCR1, CompareValue);
3156 }
3157
3158 /**
3159 * @brief Set compare value for output channel 2 (TIMx_CCR2).
3160 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3161 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3162 * whether or not a timer instance supports a 32 bits counter.
3163 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3164 * output channel 2 is supported by a timer instance.
3165 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3166 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
3167 * @param TIMx Timer instance
3168 * @param CompareValue between Min_Data=0 and Max_Data=65535
3169 * @retval None
3170 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)3171 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
3172 {
3173 WRITE_REG(TIMx->CCR2, CompareValue);
3174 }
3175
3176 /**
3177 * @brief Set compare value for output channel 3 (TIMx_CCR3).
3178 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3179 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3180 * whether or not a timer instance supports a 32 bits counter.
3181 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3182 * output channel is supported by a timer instance.
3183 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3184 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
3185 * @param TIMx Timer instance
3186 * @param CompareValue between Min_Data=0 and Max_Data=65535
3187 * @retval None
3188 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)3189 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
3190 {
3191 WRITE_REG(TIMx->CCR3, CompareValue);
3192 }
3193
3194 /**
3195 * @brief Set compare value for output channel 4 (TIMx_CCR4).
3196 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3197 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3198 * whether or not a timer instance supports a 32 bits counter.
3199 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3200 * output channel 4 is supported by a timer instance.
3201 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3202 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
3203 * @param TIMx Timer instance
3204 * @param CompareValue between Min_Data=0 and Max_Data=65535
3205 * @retval None
3206 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)3207 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
3208 {
3209 WRITE_REG(TIMx->CCR4, CompareValue);
3210 }
3211
3212 /**
3213 * @brief Set compare value for output channel 5 (TIMx_CCR5).
3214 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3215 * output channel 5 is supported by a timer instance.
3216 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3217 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
3218 * @param TIMx Timer instance
3219 * @param CompareValue between Min_Data=0 and Max_Data=65535
3220 * @retval None
3221 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)3222 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
3223 {
3224 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
3225 }
3226
3227 /**
3228 * @brief Set compare value for output channel 6 (TIMx_CCR6).
3229 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3230 * output channel 6 is supported by a timer instance.
3231 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3232 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
3233 * @param TIMx Timer instance
3234 * @param CompareValue between Min_Data=0 and Max_Data=65535
3235 * @retval None
3236 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)3237 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
3238 {
3239 WRITE_REG(TIMx->CCR6, CompareValue);
3240 }
3241
3242 /**
3243 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
3244 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3245 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3246 * whether or not a timer instance supports a 32 bits counter.
3247 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3248 * output channel 1 is supported by a timer instance.
3249 * @note If dithering is activated, pay attention to the returned value interpretation.
3250 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
3251 * @param TIMx Timer instance
3252 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3253 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)3254 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
3255 {
3256 return (uint32_t)(READ_REG(TIMx->CCR1));
3257 }
3258
3259 /**
3260 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
3261 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3262 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3263 * whether or not a timer instance supports a 32 bits counter.
3264 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3265 * output channel 2 is supported by a timer instance.
3266 * @note If dithering is activated, pay attention to the returned value interpretation.
3267 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
3268 * @param TIMx Timer instance
3269 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3270 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)3271 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
3272 {
3273 return (uint32_t)(READ_REG(TIMx->CCR2));
3274 }
3275
3276 /**
3277 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
3278 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3279 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3280 * whether or not a timer instance supports a 32 bits counter.
3281 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3282 * output channel 3 is supported by a timer instance.
3283 * @note If dithering is activated, pay attention to the returned value interpretation.
3284 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
3285 * @param TIMx Timer instance
3286 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3287 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)3288 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
3289 {
3290 return (uint32_t)(READ_REG(TIMx->CCR3));
3291 }
3292
3293 /**
3294 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
3295 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3296 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3297 * whether or not a timer instance supports a 32 bits counter.
3298 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3299 * output channel 4 is supported by a timer instance.
3300 * @note If dithering is activated, pay attention to the returned value interpretation.
3301 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3302 * @param TIMx Timer instance
3303 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3304 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)3305 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
3306 {
3307 return (uint32_t)(READ_REG(TIMx->CCR4));
3308 }
3309
3310 /**
3311 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3312 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3313 * output channel 5 is supported by a timer instance.
3314 * @note If dithering is activated, pay attention to the returned value interpretation.
3315 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3316 * @param TIMx Timer instance
3317 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3318 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)3319 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
3320 {
3321 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3322 }
3323
3324 /**
3325 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3326 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3327 * output channel 6 is supported by a timer instance.
3328 * @note If dithering is activated, pay attention to the returned value interpretation.
3329 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3330 * @param TIMx Timer instance
3331 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3332 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)3333 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
3334 {
3335 return (uint32_t)(READ_REG(TIMx->CCR6));
3336 }
3337
3338 /**
3339 * @brief Select on which reference signal the OC5REF is combined to.
3340 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3341 * whether or not a timer instance supports the combined 3-phase PWM mode.
3342 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3343 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3344 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3345 * @param TIMx Timer instance
3346 * @param GroupCH5 This parameter can be a combination of the following values:
3347 * @arg @ref LL_TIM_GROUPCH5_NONE
3348 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3349 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3350 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3351 * @retval None
3352 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3353 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3354 {
3355 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3356 }
3357
3358 /**
3359 * @brief Set the pulse on compare pulse width prescaler.
3360 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3361 * whether or not the pulse on compare feature is supported by the timer
3362 * instance.
3363 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3364 * @param TIMx Timer instance
3365 * @param PulseWidthPrescaler This parameter can be one of the following values:
3366 * @arg @ref LL_TIM_PWPRSC_X1
3367 * @arg @ref LL_TIM_PWPRSC_X2
3368 * @arg @ref LL_TIM_PWPRSC_X4
3369 * @arg @ref LL_TIM_PWPRSC_X8
3370 * @arg @ref LL_TIM_PWPRSC_X16
3371 * @arg @ref LL_TIM_PWPRSC_X32
3372 * @arg @ref LL_TIM_PWPRSC_X64
3373 * @arg @ref LL_TIM_PWPRSC_X128
3374 * @retval None
3375 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3376 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3377 {
3378 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3379 }
3380
3381 /**
3382 * @brief Get the pulse on compare pulse width prescaler.
3383 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3384 * whether or not the pulse on compare feature is supported by the timer
3385 * instance.
3386 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3387 * @param TIMx Timer instance
3388 * @retval Returned value can be one of the following values:
3389 * @arg @ref LL_TIM_PWPRSC_X1
3390 * @arg @ref LL_TIM_PWPRSC_X2
3391 * @arg @ref LL_TIM_PWPRSC_X4
3392 * @arg @ref LL_TIM_PWPRSC_X8
3393 * @arg @ref LL_TIM_PWPRSC_X16
3394 * @arg @ref LL_TIM_PWPRSC_X32
3395 * @arg @ref LL_TIM_PWPRSC_X64
3396 * @arg @ref LL_TIM_PWPRSC_X128
3397 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3398 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3399 {
3400 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3401 }
3402
3403 /**
3404 * @brief Set the pulse on compare pulse width duration.
3405 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3406 * whether or not the pulse on compare feature is supported by the timer
3407 * instance.
3408 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3409 * @param TIMx Timer instance
3410 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3411 * @retval None
3412 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3413 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3414 {
3415 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3416 }
3417
3418 /**
3419 * @brief Get the pulse on compare pulse width duration.
3420 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3421 * whether or not the pulse on compare feature is supported by the timer
3422 * instance.
3423 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3424 * @param TIMx Timer instance
3425 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3426 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3427 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3428 {
3429 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3430 }
3431
3432 /**
3433 * @}
3434 */
3435
3436 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3437 * @{
3438 */
3439 /**
3440 * @brief Configure input channel.
3441 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3442 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3443 * CCMR1 IC1F LL_TIM_IC_Config\n
3444 * CCMR1 CC2S LL_TIM_IC_Config\n
3445 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3446 * CCMR1 IC2F LL_TIM_IC_Config\n
3447 * CCMR2 CC3S LL_TIM_IC_Config\n
3448 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3449 * CCMR2 IC3F LL_TIM_IC_Config\n
3450 * CCMR2 CC4S LL_TIM_IC_Config\n
3451 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3452 * CCMR2 IC4F LL_TIM_IC_Config\n
3453 * CCER CC1P LL_TIM_IC_Config\n
3454 * CCER CC1NP LL_TIM_IC_Config\n
3455 * CCER CC2P LL_TIM_IC_Config\n
3456 * CCER CC2NP LL_TIM_IC_Config\n
3457 * CCER CC3P LL_TIM_IC_Config\n
3458 * CCER CC3NP LL_TIM_IC_Config\n
3459 * CCER CC4P LL_TIM_IC_Config\n
3460 * CCER CC4NP LL_TIM_IC_Config
3461 * @param TIMx Timer instance
3462 * @param Channel This parameter can be one of the following values:
3463 * @arg @ref LL_TIM_CHANNEL_CH1
3464 * @arg @ref LL_TIM_CHANNEL_CH2
3465 * @arg @ref LL_TIM_CHANNEL_CH3
3466 * @arg @ref LL_TIM_CHANNEL_CH4
3467 * @param Configuration This parameter must be a combination of all the following values:
3468 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3469 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3470 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3471 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3472 * @retval None
3473 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3474 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3475 {
3476 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3477 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3478 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3479 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3480 << SHIFT_TAB_ICxx[iChannel]);
3481 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3482 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3483 }
3484
3485 /**
3486 * @brief Set the active input.
3487 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3488 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3489 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3490 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3491 * @param TIMx Timer instance
3492 * @param Channel This parameter can be one of the following values:
3493 * @arg @ref LL_TIM_CHANNEL_CH1
3494 * @arg @ref LL_TIM_CHANNEL_CH2
3495 * @arg @ref LL_TIM_CHANNEL_CH3
3496 * @arg @ref LL_TIM_CHANNEL_CH4
3497 * @param ICActiveInput This parameter can be one of the following values:
3498 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3499 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3500 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3501 * @retval None
3502 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3503 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3504 {
3505 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3506 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3507 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3508 }
3509
3510 /**
3511 * @brief Get the current active input.
3512 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3513 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3514 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3515 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3516 * @param TIMx Timer instance
3517 * @param Channel This parameter can be one of the following values:
3518 * @arg @ref LL_TIM_CHANNEL_CH1
3519 * @arg @ref LL_TIM_CHANNEL_CH2
3520 * @arg @ref LL_TIM_CHANNEL_CH3
3521 * @arg @ref LL_TIM_CHANNEL_CH4
3522 * @retval Returned value can be one of the following values:
3523 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3524 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3525 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3526 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3527 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3528 {
3529 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3530 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3531 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3532 }
3533
3534 /**
3535 * @brief Set the prescaler of input channel.
3536 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3537 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3538 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3539 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3540 * @param TIMx Timer instance
3541 * @param Channel This parameter can be one of the following values:
3542 * @arg @ref LL_TIM_CHANNEL_CH1
3543 * @arg @ref LL_TIM_CHANNEL_CH2
3544 * @arg @ref LL_TIM_CHANNEL_CH3
3545 * @arg @ref LL_TIM_CHANNEL_CH4
3546 * @param ICPrescaler This parameter can be one of the following values:
3547 * @arg @ref LL_TIM_ICPSC_DIV1
3548 * @arg @ref LL_TIM_ICPSC_DIV2
3549 * @arg @ref LL_TIM_ICPSC_DIV4
3550 * @arg @ref LL_TIM_ICPSC_DIV8
3551 * @retval None
3552 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3553 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3554 {
3555 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3556 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3557 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3558 }
3559
3560 /**
3561 * @brief Get the current prescaler value acting on an input channel.
3562 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3563 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3564 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3565 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3566 * @param TIMx Timer instance
3567 * @param Channel This parameter can be one of the following values:
3568 * @arg @ref LL_TIM_CHANNEL_CH1
3569 * @arg @ref LL_TIM_CHANNEL_CH2
3570 * @arg @ref LL_TIM_CHANNEL_CH3
3571 * @arg @ref LL_TIM_CHANNEL_CH4
3572 * @retval Returned value can be one of the following values:
3573 * @arg @ref LL_TIM_ICPSC_DIV1
3574 * @arg @ref LL_TIM_ICPSC_DIV2
3575 * @arg @ref LL_TIM_ICPSC_DIV4
3576 * @arg @ref LL_TIM_ICPSC_DIV8
3577 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3578 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3579 {
3580 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3581 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3582 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3583 }
3584
3585 /**
3586 * @brief Set the input filter duration.
3587 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3588 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3589 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3590 * CCMR2 IC4F LL_TIM_IC_SetFilter
3591 * @param TIMx Timer instance
3592 * @param Channel This parameter can be one of the following values:
3593 * @arg @ref LL_TIM_CHANNEL_CH1
3594 * @arg @ref LL_TIM_CHANNEL_CH2
3595 * @arg @ref LL_TIM_CHANNEL_CH3
3596 * @arg @ref LL_TIM_CHANNEL_CH4
3597 * @param ICFilter This parameter can be one of the following values:
3598 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3599 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3600 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3601 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3602 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3603 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3604 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3605 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3606 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3607 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3608 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3609 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3610 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3611 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3612 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3613 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3614 * @retval None
3615 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3616 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3617 {
3618 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3619 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3620 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3621 }
3622
3623 /**
3624 * @brief Get the input filter duration.
3625 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3626 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3627 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3628 * CCMR2 IC4F LL_TIM_IC_GetFilter
3629 * @param TIMx Timer instance
3630 * @param Channel This parameter can be one of the following values:
3631 * @arg @ref LL_TIM_CHANNEL_CH1
3632 * @arg @ref LL_TIM_CHANNEL_CH2
3633 * @arg @ref LL_TIM_CHANNEL_CH3
3634 * @arg @ref LL_TIM_CHANNEL_CH4
3635 * @retval Returned value can be one of the following values:
3636 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3637 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3638 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3639 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3640 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3641 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3642 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3643 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3644 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3645 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3646 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3647 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3648 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3649 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3650 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3651 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3652 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3653 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3654 {
3655 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3656 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3657 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3658 }
3659
3660 /**
3661 * @brief Set the input channel polarity.
3662 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3663 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3664 * CCER CC2P LL_TIM_IC_SetPolarity\n
3665 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3666 * CCER CC3P LL_TIM_IC_SetPolarity\n
3667 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3668 * CCER CC4P LL_TIM_IC_SetPolarity\n
3669 * CCER CC4NP LL_TIM_IC_SetPolarity
3670 * @param TIMx Timer instance
3671 * @param Channel This parameter can be one of the following values:
3672 * @arg @ref LL_TIM_CHANNEL_CH1
3673 * @arg @ref LL_TIM_CHANNEL_CH2
3674 * @arg @ref LL_TIM_CHANNEL_CH3
3675 * @arg @ref LL_TIM_CHANNEL_CH4
3676 * @param ICPolarity This parameter can be one of the following values:
3677 * @arg @ref LL_TIM_IC_POLARITY_RISING
3678 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3679 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3680 * @retval None
3681 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3682 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3683 {
3684 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3685 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3686 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3687 }
3688
3689 /**
3690 * @brief Get the current input channel polarity.
3691 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3692 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3693 * CCER CC2P LL_TIM_IC_GetPolarity\n
3694 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3695 * CCER CC3P LL_TIM_IC_GetPolarity\n
3696 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3697 * CCER CC4P LL_TIM_IC_GetPolarity\n
3698 * CCER CC4NP LL_TIM_IC_GetPolarity
3699 * @param TIMx Timer instance
3700 * @param Channel This parameter can be one of the following values:
3701 * @arg @ref LL_TIM_CHANNEL_CH1
3702 * @arg @ref LL_TIM_CHANNEL_CH2
3703 * @arg @ref LL_TIM_CHANNEL_CH3
3704 * @arg @ref LL_TIM_CHANNEL_CH4
3705 * @retval Returned value can be one of the following values:
3706 * @arg @ref LL_TIM_IC_POLARITY_RISING
3707 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3708 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3709 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3710 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3711 {
3712 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3713 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3714 SHIFT_TAB_CCxP[iChannel]);
3715 }
3716
3717 /**
3718 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3719 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3720 * a timer instance provides an XOR input.
3721 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3722 * @param TIMx Timer instance
3723 * @retval None
3724 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3725 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3726 {
3727 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3728 }
3729
3730 /**
3731 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3732 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3733 * a timer instance provides an XOR input.
3734 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3735 * @param TIMx Timer instance
3736 * @retval None
3737 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3738 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3739 {
3740 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3741 }
3742
3743 /**
3744 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3745 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3746 * a timer instance provides an XOR input.
3747 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3748 * @param TIMx Timer instance
3749 * @retval State of bit (1 or 0).
3750 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3751 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3752 {
3753 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3754 }
3755
3756 /**
3757 * @brief Get captured value for input channel 1.
3758 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3759 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3760 * whether or not a timer instance supports a 32 bits counter.
3761 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3762 * input channel 1 is supported by a timer instance.
3763 * @note If dithering is activated, pay attention to the returned value interpretation.
3764 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3765 * @param TIMx Timer instance
3766 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3767 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3768 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3769 {
3770 return (uint32_t)(READ_REG(TIMx->CCR1));
3771 }
3772
3773 /**
3774 * @brief Get captured value for input channel 2.
3775 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3776 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3777 * whether or not a timer instance supports a 32 bits counter.
3778 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3779 * input channel 2 is supported by a timer instance.
3780 * @note If dithering is activated, pay attention to the returned value interpretation.
3781 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3782 * @param TIMx Timer instance
3783 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3784 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3785 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3786 {
3787 return (uint32_t)(READ_REG(TIMx->CCR2));
3788 }
3789
3790 /**
3791 * @brief Get captured value for input channel 3.
3792 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3793 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3794 * whether or not a timer instance supports a 32 bits counter.
3795 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3796 * input channel 3 is supported by a timer instance.
3797 * @note If dithering is activated, pay attention to the returned value interpretation.
3798 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3799 * @param TIMx Timer instance
3800 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3801 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3802 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3803 {
3804 return (uint32_t)(READ_REG(TIMx->CCR3));
3805 }
3806
3807 /**
3808 * @brief Get captured value for input channel 4.
3809 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3810 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3811 * whether or not a timer instance supports a 32 bits counter.
3812 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3813 * input channel 4 is supported by a timer instance.
3814 * @note If dithering is activated, pay attention to the returned value interpretation.
3815 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3816 * @param TIMx Timer instance
3817 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3818 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3819 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3820 {
3821 return (uint32_t)(READ_REG(TIMx->CCR4));
3822 }
3823
3824 /**
3825 * @}
3826 */
3827
3828 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3829 * @{
3830 */
3831 /**
3832 * @brief Enable external clock mode 2.
3833 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3834 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3835 * whether or not a timer instance supports external clock mode2.
3836 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3837 * @param TIMx Timer instance
3838 * @retval None
3839 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3840 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3841 {
3842 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3843 }
3844
3845 /**
3846 * @brief Disable external clock mode 2.
3847 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3848 * whether or not a timer instance supports external clock mode2.
3849 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3850 * @param TIMx Timer instance
3851 * @retval None
3852 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3853 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3854 {
3855 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3856 }
3857
3858 /**
3859 * @brief Indicate whether external clock mode 2 is enabled.
3860 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3861 * whether or not a timer instance supports external clock mode2.
3862 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3863 * @param TIMx Timer instance
3864 * @retval State of bit (1 or 0).
3865 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3866 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3867 {
3868 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3869 }
3870
3871 /**
3872 * @brief Set the clock source of the counter clock.
3873 * @note when selected clock source is external clock mode 1, the timer input
3874 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3875 * function. This timer input must be configured by calling
3876 * the @ref LL_TIM_IC_Config() function.
3877 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3878 * whether or not a timer instance supports external clock mode1.
3879 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3880 * whether or not a timer instance supports external clock mode2.
3881 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3882 * SMCR ECE LL_TIM_SetClockSource
3883 * @param TIMx Timer instance
3884 * @param ClockSource This parameter can be one of the following values:
3885 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3886 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3887 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3888 * @retval None
3889 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3890 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3891 {
3892 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3893 }
3894
3895 /**
3896 * @brief Set the encoder interface mode.
3897 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3898 * whether or not a timer instance supports the encoder mode.
3899 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3900 * @param TIMx Timer instance
3901 * @param EncoderMode This parameter can be one of the following values:
3902 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3903 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3904 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3905 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3906 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3907 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3908 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3909 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3910 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3911 * @retval None
3912 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3913 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3914 {
3915 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3916 }
3917
3918 /**
3919 * @}
3920 */
3921
3922 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3923 * @{
3924 */
3925 /**
3926 * @brief Set the trigger output (TRGO) used for timer synchronization .
3927 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3928 * whether or not a timer instance can operate as a master timer.
3929 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3930 * @param TIMx Timer instance
3931 * @param TimerSynchronization This parameter can be one of the following values:
3932 * @arg @ref LL_TIM_TRGO_RESET
3933 * @arg @ref LL_TIM_TRGO_ENABLE
3934 * @arg @ref LL_TIM_TRGO_UPDATE
3935 * @arg @ref LL_TIM_TRGO_CC1IF
3936 * @arg @ref LL_TIM_TRGO_OC1REF
3937 * @arg @ref LL_TIM_TRGO_OC2REF
3938 * @arg @ref LL_TIM_TRGO_OC3REF
3939 * @arg @ref LL_TIM_TRGO_OC4REF
3940 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3941 * @retval None
3942 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3943 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3944 {
3945 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3946 }
3947
3948 /**
3949 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3950 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3951 * whether or not a timer instance can be used for ADC synchronization.
3952 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3953 * @param TIMx Timer Instance
3954 * @param ADCSynchronization This parameter can be one of the following values:
3955 * @arg @ref LL_TIM_TRGO2_RESET
3956 * @arg @ref LL_TIM_TRGO2_ENABLE
3957 * @arg @ref LL_TIM_TRGO2_UPDATE
3958 * @arg @ref LL_TIM_TRGO2_CC1F
3959 * @arg @ref LL_TIM_TRGO2_OC1
3960 * @arg @ref LL_TIM_TRGO2_OC2
3961 * @arg @ref LL_TIM_TRGO2_OC3
3962 * @arg @ref LL_TIM_TRGO2_OC4
3963 * @arg @ref LL_TIM_TRGO2_OC5
3964 * @arg @ref LL_TIM_TRGO2_OC6
3965 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3966 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3967 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3968 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3969 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3970 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3971 * @retval None
3972 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3973 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3974 {
3975 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3976 }
3977
3978 /**
3979 * @brief Set the synchronization mode of a slave timer.
3980 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3981 * a timer instance can operate as a slave timer.
3982 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3983 * @param TIMx Timer instance
3984 * @param SlaveMode This parameter can be one of the following values:
3985 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3986 * @arg @ref LL_TIM_SLAVEMODE_RESET
3987 * @arg @ref LL_TIM_SLAVEMODE_GATED
3988 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3989 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3990 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3991 * @retval None
3992 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3993 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3994 {
3995 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3996 }
3997
3998 /**
3999 * @brief Set the selects the trigger input to be used to synchronize the counter.
4000 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4001 * a timer instance can operate as a slave timer.
4002 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
4003 * @param TIMx Timer instance
4004 * @param TriggerInput This parameter can be one of the following values:
4005 * @arg @ref LL_TIM_TS_ITR0
4006 * @arg @ref LL_TIM_TS_ITR1
4007 * @arg @ref LL_TIM_TS_ITR2
4008 * @arg @ref LL_TIM_TS_ITR3
4009 * @arg @ref LL_TIM_TS_ITR4
4010 * @arg @ref LL_TIM_TS_ITR5
4011 * @arg @ref LL_TIM_TS_ITR6
4012 * @arg @ref LL_TIM_TS_ITR7
4013 * @arg @ref LL_TIM_TS_ITR8
4014 * @arg @ref LL_TIM_TS_ITR9
4015 * @arg @ref LL_TIM_TS_ITR10
4016 * @arg @ref LL_TIM_TS_ITR11
4017 * @arg @ref LL_TIM_TS_ITR12
4018 * @arg @ref LL_TIM_TS_TI1F_ED
4019 * @arg @ref LL_TIM_TS_TI1FP1
4020 * @arg @ref LL_TIM_TS_TI2FP2
4021 * @arg @ref LL_TIM_TS_ETRF
4022 * @retval None
4023 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)4024 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
4025 {
4026 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
4027 }
4028
4029 /**
4030 * @brief Enable the Master/Slave mode.
4031 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4032 * a timer instance can operate as a slave timer.
4033 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
4034 * @param TIMx Timer instance
4035 * @retval None
4036 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)4037 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
4038 {
4039 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
4040 }
4041
4042 /**
4043 * @brief Disable the Master/Slave mode.
4044 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4045 * a timer instance can operate as a slave timer.
4046 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
4047 * @param TIMx Timer instance
4048 * @retval None
4049 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)4050 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
4051 {
4052 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
4053 }
4054
4055 /**
4056 * @brief Indicates whether the Master/Slave mode is enabled.
4057 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4058 * a timer instance can operate as a slave timer.
4059 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
4060 * @param TIMx Timer instance
4061 * @retval State of bit (1 or 0).
4062 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)4063 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
4064 {
4065 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
4066 }
4067
4068 /**
4069 * @brief Configure the external trigger (ETR) input.
4070 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
4071 * a timer instance provides an external trigger input.
4072 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
4073 * SMCR ETPS LL_TIM_ConfigETR\n
4074 * SMCR ETF LL_TIM_ConfigETR
4075 * @param TIMx Timer instance
4076 * @param ETRPolarity This parameter can be one of the following values:
4077 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
4078 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
4079 * @param ETRPrescaler This parameter can be one of the following values:
4080 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
4081 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
4082 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
4083 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
4084 * @param ETRFilter This parameter can be one of the following values:
4085 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
4086 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
4087 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
4088 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
4089 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
4090 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
4091 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
4092 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
4093 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
4094 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
4095 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
4096 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
4097 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
4098 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
4099 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
4100 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
4101 * @retval None
4102 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)4103 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
4104 uint32_t ETRFilter)
4105 {
4106 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
4107 }
4108
4109 /**
4110 * @brief Select the external trigger (ETR) input source.
4111 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
4112 * not a timer instance supports ETR source selection.
4113 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
4114 * @param TIMx Timer instance
4115 * @param ETRSource This parameter can be one of the following values:
4116 *
4117 * TIM1: any combination of ETR_RMP where
4118 *
4119 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
4120 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*)
4121 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*)
4122 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
4123 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
4124 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
4125 *
4126 * TIM2: any combination of ETR_RMP where
4127 *
4128 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
4129 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*)
4130 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*)
4131 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
4132 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA (*)
4133 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (*)
4134 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
4135 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (*)
4136 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
4137 * @arg @ref LL_TIM_TIM2_ETRSOURCE_USB_SOF (*)
4138 * @arg @ref LL_TIM_TIM2_ETRSOURCE_USBHS_SOF (*)
4139 * @arg @ref LL_TIM_TIM2_ETRSOURCE_USBFS_SOF (*)
4140 * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS (*)
4141 * @arg @ref LL_TIM_TIM2_ETRSOURCE_PLAY1_OUT0 (*)
4142 *
4143 * TIM3: any combination of ETR_RMP where
4144 *
4145 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
4146 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*)
4147 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*)
4148 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (*)
4149 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (*)
4150 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (*)
4151 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
4152 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (*)
4153 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (*)
4154 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS (*)
4155 * @arg @ref LL_TIM_TIM3_ETRSOURCE_PLAY1_OUT0 (*)
4156 *
4157 * TIM4: any combination of ETR_RMP where (**)
4158 *
4159 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
4160 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1 (*)
4161 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2 (*)
4162 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR
4163 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
4164 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
4165 *
4166 * TIM5: any combination of ETR_RMP where (**)
4167 *
4168 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
4169 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA
4170 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB
4171 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*)
4172 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
4173 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
4174 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
4175 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR
4176 * @arg @ref LL_TIM_TIM5_ETRSOURCE_USB_SOF (*)
4177 * @arg @ref LL_TIM_TIM5_ETRSOURCE_USBHS_SOF (*)
4178 * @arg @ref LL_TIM_TIM5_ETRSOURCE_USBFS_SOF (*)
4179 *
4180 * TIM8: any combination of ETR_RMP where (**)
4181 *
4182 * . . ETR_RMP can be one of the following values
4183 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
4184 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1 (*)
4185 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2 (*)
4186 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
4187 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
4188 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
4189 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*)
4190 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*)
4191 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*)
4192 *
4193 * (*) Value not defined in all devices. \n
4194 * (**) Timer instance not available on all devices. \n
4195 * @retval None
4196 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)4197 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
4198 {
4199 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
4200 }
4201
4202 /**
4203 * @brief Enable SMS preload.
4204 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4205 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4206 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
4207 * @param TIMx Timer instance
4208 * @retval None
4209 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)4210 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
4211 {
4212 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4213 }
4214
4215 /**
4216 * @brief Disable SMS preload.
4217 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4218 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4219 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
4220 * @param TIMx Timer instance
4221 * @retval None
4222 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)4223 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
4224 {
4225 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4226 }
4227
4228 /**
4229 * @brief Indicate whether SMS preload is enabled.
4230 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4231 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4232 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
4233 * @param TIMx Timer instance
4234 * @retval State of bit (1 or 0).
4235 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)4236 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
4237 {
4238 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
4239 }
4240
4241 /**
4242 * @brief Set the preload source of SMS.
4243 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4244 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4245 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
4246 * @param TIMx Timer instance
4247 * @param PreloadSource This parameter can be one of the following values:
4248 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4249 * @arg @ref LL_TIM_SMSPS_INDEX
4250 * @retval None
4251 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)4252 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
4253 {
4254 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
4255 }
4256
4257 /**
4258 * @brief Get the preload source of SMS.
4259 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4260 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4261 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
4262 * @param TIMx Timer instance
4263 * @retval Returned value can be one of the following values:
4264 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4265 * @arg @ref LL_TIM_SMSPS_INDEX
4266 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)4267 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
4268 {
4269 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
4270 }
4271
4272 /**
4273 * @}
4274 */
4275
4276 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
4277 * @{
4278 */
4279 /**
4280 * @brief Enable the break function.
4281 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4282 * a timer instance provides a break input.
4283 * @rmtoll BDTR BKE LL_TIM_EnableBRK
4284 * @param TIMx Timer instance
4285 * @retval None
4286 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)4287 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
4288 {
4289 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4290 }
4291
4292 /**
4293 * @brief Disable the break function.
4294 * @rmtoll BDTR BKE LL_TIM_DisableBRK
4295 * @param TIMx Timer instance
4296 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4297 * a timer instance provides a break input.
4298 * @retval None
4299 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)4300 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
4301 {
4302 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4303 }
4304
4305 /**
4306 * @brief Configure the break input.
4307 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4308 * a timer instance provides a break input.
4309 * @note Bidirectional mode is only supported by advanced timer instances.
4310 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4311 * a timer instance is an advanced-control timer.
4312 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4313 * in input mode and in open drain output mode. Any active Break event will
4314 * assert a low logic level on the Break input to indicate an internal break
4315 * event to external devices.
4316 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4317 * LL_TIM_BREAK_AFMODE_INPUT.
4318 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4319 * BDTR BKF LL_TIM_ConfigBRK\n
4320 * BDTR BKBID LL_TIM_ConfigBRK
4321 * @param TIMx Timer instance
4322 * @param BreakPolarity This parameter can be one of the following values:
4323 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4324 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4325 * @param BreakFilter This parameter can be one of the following values:
4326 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4327 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4328 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4329 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4330 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4331 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4332 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4333 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4334 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4335 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4336 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4337 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4338 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4339 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4340 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4341 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4342 * @param BreakAFMode This parameter can be one of the following values:
4343 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4344 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4345 * @retval None
4346 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)4347 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4348 uint32_t BreakAFMode)
4349 {
4350 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4351 }
4352
4353 /**
4354 * @brief Disarm the break input (when it operates in bidirectional mode).
4355 * @note The break input can be disarmed only when it is configured in
4356 * bidirectional mode and when when MOE is reset.
4357 * @note Purpose is to be able to have the input voltage back to high-state,
4358 * whatever the time constant on the output .
4359 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4360 * @param TIMx Timer instance
4361 * @retval None
4362 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)4363 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4364 {
4365 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4366 }
4367
4368 /**
4369 * @brief Enable the break 2 function.
4370 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4371 * a timer instance provides a second break input.
4372 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4373 * @param TIMx Timer instance
4374 * @retval None
4375 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4376 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4377 {
4378 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4379 }
4380
4381 /**
4382 * @brief Disable the break 2 function.
4383 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4384 * a timer instance provides a second break input.
4385 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4386 * @param TIMx Timer instance
4387 * @retval None
4388 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4389 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4390 {
4391 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4392 }
4393
4394 /**
4395 * @brief Configure the break 2 input.
4396 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4397 * a timer instance provides a second break input.
4398 * @note Bidirectional mode is only supported by advanced timer instances.
4399 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4400 * a timer instance is an advanced-control timer.
4401 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4402 * in input mode and in open drain output mode. Any active Break event will
4403 * assert a low logic level on the Break 2 input to indicate an internal break
4404 * event to external devices.
4405 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4406 * LL_TIM_BREAK2_AFMODE_INPUT.
4407 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4408 * BDTR BK2F LL_TIM_ConfigBRK2\n
4409 * BDTR BK2BID LL_TIM_ConfigBRK2
4410 * @param TIMx Timer instance
4411 * @param Break2Polarity This parameter can be one of the following values:
4412 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4413 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4414 * @param Break2Filter This parameter can be one of the following values:
4415 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4416 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4417 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4418 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4419 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4420 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4421 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4422 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4423 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4424 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4425 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4426 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4427 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4428 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4429 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4430 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4431 * @param Break2AFMode This parameter can be one of the following values:
4432 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4433 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4434 * @retval None
4435 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4436 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4437 uint32_t Break2AFMode)
4438 {
4439 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4440 }
4441
4442 /**
4443 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4444 * @note The break 2 input can be disarmed only when it is configured in
4445 * bidirectional mode and when when MOE is reset.
4446 * @note Purpose is to be able to have the input voltage back to high-state,
4447 * whatever the time constant on the output.
4448 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4449 * @param TIMx Timer instance
4450 * @retval None
4451 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4452 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4453 {
4454 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4455 }
4456
4457 /**
4458 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4459 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4460 * a timer instance provides a break input.
4461 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4462 * BDTR OSSR LL_TIM_SetOffStates
4463 * @param TIMx Timer instance
4464 * @param OffStateIdle This parameter can be one of the following values:
4465 * @arg @ref LL_TIM_OSSI_DISABLE
4466 * @arg @ref LL_TIM_OSSI_ENABLE
4467 * @param OffStateRun This parameter can be one of the following values:
4468 * @arg @ref LL_TIM_OSSR_DISABLE
4469 * @arg @ref LL_TIM_OSSR_ENABLE
4470 * @retval None
4471 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4472 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4473 {
4474 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4475 }
4476
4477 /**
4478 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4479 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4480 * a timer instance provides a break input.
4481 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4482 * @param TIMx Timer instance
4483 * @retval None
4484 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4485 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4486 {
4487 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4488 }
4489
4490 /**
4491 * @brief Disable automatic output (MOE can be set only by software).
4492 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4493 * a timer instance provides a break input.
4494 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4495 * @param TIMx Timer instance
4496 * @retval None
4497 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4498 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4499 {
4500 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4501 }
4502
4503 /**
4504 * @brief Indicate whether automatic output is enabled.
4505 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4506 * a timer instance provides a break input.
4507 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4508 * @param TIMx Timer instance
4509 * @retval State of bit (1 or 0).
4510 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4511 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4512 {
4513 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4514 }
4515
4516 /**
4517 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4518 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4519 * software and is reset in case of break or break2 event
4520 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4521 * a timer instance provides a break input.
4522 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4523 * @param TIMx Timer instance
4524 * @retval None
4525 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4526 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4527 {
4528 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4529 }
4530
4531 /**
4532 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4533 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4534 * software and is reset in case of break or break2 event.
4535 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4536 * a timer instance provides a break input.
4537 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4538 * @param TIMx Timer instance
4539 * @retval None
4540 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4541 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4542 {
4543 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4544 }
4545
4546 /**
4547 * @brief Indicates whether outputs are enabled.
4548 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4549 * a timer instance provides a break input.
4550 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4551 * @param TIMx Timer instance
4552 * @retval State of bit (1 or 0).
4553 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4554 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4555 {
4556 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4557 }
4558
4559 /**
4560 * @brief Enable the signals connected to the designated timer break input.
4561 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4562 * or not a timer instance allows for break input selection.
4563 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4564 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4565 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
4566 * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
4567 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
4568 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
4569 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4570 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
4571 * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n
4572 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
4573 * @param TIMx Timer instance
4574 * @param BreakInput This parameter can be one of the following values:
4575 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4576 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4577 * @param Source This parameter can be one of the following values:
4578 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4579 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4580 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
4581 * @arg @ref LL_TIM_BKIN_SOURCE_PLAY1 (*)
4582 * @arg @ref LL_TIM_BKIN_SOURCE_MDF1 (*)
4583 *
4584 * (*) Value not defined in all devices.
4585 * @retval None
4586 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4587 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4588 {
4589 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4590 SET_BIT(*pReg, Source);
4591 }
4592
4593 /**
4594 * @brief Disable the signals connected to the designated timer break input.
4595 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4596 * or not a timer instance allows for break input selection.
4597 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4598 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4599 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
4600 * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
4601 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
4602 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4603 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
4604 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
4605 * AF2 BK2CMP3E LL_TIM_DisableBreakInputSource\n
4606 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
4607 * @param TIMx Timer instance
4608 * @param BreakInput This parameter can be one of the following values:
4609 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4610 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4611 * @param Source This parameter can be one of the following values:
4612 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4613 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4614 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
4615 * @arg @ref LL_TIM_BKIN_SOURCE_PLAY1 (*)
4616 * @arg @ref LL_TIM_BKIN_SOURCE_MDF1 (*)
4617 *
4618 * (*) Value not defined in all devices.
4619 * @retval None
4620 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4621 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4622 {
4623 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4624 CLEAR_BIT(*pReg, Source);
4625 }
4626
4627 /**
4628 * @brief Set the polarity of the break signal for the timer break input.
4629 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4630 * or not a timer instance allows for break input selection.
4631 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4632 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4633 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
4634 * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
4635 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4636 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4637 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
4638 * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity
4639 * @param TIMx Timer instance
4640 * @param BreakInput This parameter can be one of the following values:
4641 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4642 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4643 * @param Source This parameter can be one of the following values:
4644 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4645 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4646 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
4647 * @arg @ref LL_TIM_BKIN_SOURCE_PLAY1 (*)
4648 * @param Polarity This parameter can be one of the following values:
4649 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4650 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4651 *
4652 * (*) Value not defined in all devices.
4653 * @retval None
4654 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4655 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4656 uint32_t Polarity)
4657 {
4658 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4659 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4660 }
4661 /**
4662 * @brief Enable asymmetrical deadtime.
4663 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4664 * a timer instance provides asymmetrical deadtime.
4665 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4666 * @param TIMx Timer instance
4667 * @retval None
4668 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4669 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4670 {
4671 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4672 }
4673
4674 /**
4675 * @brief Disable asymmetrical dead-time.
4676 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4677 * a timer instance provides asymmetrical deadtime.
4678 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4679 * @param TIMx Timer instance
4680 * @retval None
4681 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4682 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4683 {
4684 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4685 }
4686
4687 /**
4688 * @brief Indicates whether asymmetrical deadtime is activated.
4689 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4690 * a timer instance provides asymmetrical deadtime.
4691 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4692 * @param TIMx Timer instance
4693 * @retval State of bit (1 or 0).
4694 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4695 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4696 {
4697 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4698 }
4699
4700 /**
4701 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4702 * rising edge of OCxN signals).
4703 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4704 * asymmetrical dead-time insertion feature is supported by a timer instance.
4705 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4706 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4707 * (LOCK bits in TIMx_BDTR register).
4708 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4709 * @param TIMx Timer instance
4710 * @param DeadTime between Min_Data=0 and Max_Data=255
4711 * @retval None
4712 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4713 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4714 {
4715 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4716 }
4717
4718 /**
4719 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4720 * the rising edge of OCxN signals).
4721 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4722 * asymmetrical dead-time insertion feature is supported by a timer instance.
4723 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4724 * (LOCK bits in TIMx_BDTR register).
4725 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4726 * @param TIMx Timer instance
4727 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4728 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4729 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4730 {
4731 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4732 }
4733
4734 /**
4735 * @brief Enable deadtime preload.
4736 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4737 * a timer instance provides deadtime preload.
4738 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4739 * @param TIMx Timer instance
4740 * @retval None
4741 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4742 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4743 {
4744 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4745 }
4746
4747 /**
4748 * @brief Disable dead-time preload.
4749 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4750 * a timer instance provides deadtime preload.
4751 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4752 * @param TIMx Timer instance
4753 * @retval None
4754 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4755 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4756 {
4757 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4758 }
4759
4760 /**
4761 * @brief Indicates whether deadtime preload is activated.
4762 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4763 * a timer instance provides deadtime preload.
4764 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4765 * @param TIMx Timer instance
4766 * @retval State of bit (1 or 0).
4767 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4768 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4769 {
4770 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4771 }
4772
4773 /**
4774 * @}
4775 */
4776
4777 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4778 * @{
4779 */
4780 /**
4781 * @brief Configures the timer DMA burst feature.
4782 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4783 * not a timer instance supports the DMA burst mode.
4784 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4785 * DCR DBA LL_TIM_ConfigDMABurst
4786 * @param TIMx Timer instance
4787 * @param DMABurstBaseAddress This parameter can be one of the following values:
4788 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4789 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4790 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4791 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4792 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4793 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4794 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4795 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4796 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4797 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4798 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4799 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4800 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4801 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4802 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4803 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4804 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4805 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4806 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4807 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4808 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4809 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4810 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4811 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4812 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4813 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4814 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
4815 * @param DMABurstLength This parameter can be one of the following values:
4816 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4817 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4818 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4819 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4820 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4821 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4822 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4823 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4824 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4825 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4826 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4827 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4828 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4829 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4830 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4831 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4832 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4833 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4834 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4835 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4836 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4837 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4838 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4839 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4840 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4841 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4842 * @param DMABurstSource This parameter can be one of the following values:
4843 * @arg @ref LL_TIM_DMA_UPDATE
4844 * @arg @ref LL_TIM_DMA_CC1
4845 * @arg @ref LL_TIM_DMA_CC2
4846 * @arg @ref LL_TIM_DMA_CC3
4847 * @arg @ref LL_TIM_DMA_CC4
4848 * @arg @ref LL_TIM_DMA_COM
4849 * @arg @ref LL_TIM_DMA_TRIGGER
4850 * @retval None
4851 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength,uint32_t DMABurstSource)4852 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
4853 uint32_t DMABurstSource)
4854 {
4855 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
4856 (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
4857 }
4858
4859 /**
4860 * @}
4861 */
4862
4863 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4864 * @{
4865 */
4866
4867 /**
4868 * @brief Enable encoder index.
4869 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4870 * a timer instance provides an index input.
4871 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4872 * @param TIMx Timer instance
4873 * @retval None
4874 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4875 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4876 {
4877 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4878 }
4879
4880 /**
4881 * @brief Disable encoder index.
4882 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4883 * a timer instance provides an index input.
4884 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4885 * @param TIMx Timer instance
4886 * @retval None
4887 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4888 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4889 {
4890 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4891 }
4892
4893 /**
4894 * @brief Indicate whether encoder index is enabled.
4895 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4896 * a timer instance provides an index input.
4897 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4898 * @param TIMx Timer instance
4899 * @retval State of bit (1 or 0).
4900 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)4901 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
4902 {
4903 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4904 }
4905
4906 /**
4907 * @brief Set index direction
4908 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4909 * a timer instance provides an index input.
4910 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4911 * @param TIMx Timer instance
4912 * @param IndexDirection This parameter can be one of the following values:
4913 * @arg @ref LL_TIM_INDEX_UP_DOWN
4914 * @arg @ref LL_TIM_INDEX_UP
4915 * @arg @ref LL_TIM_INDEX_DOWN
4916 * @retval None
4917 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)4918 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4919 {
4920 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4921 }
4922
4923 /**
4924 * @brief Get actual index direction
4925 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4926 * a timer instance provides an index input.
4927 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4928 * @param TIMx Timer instance
4929 * @retval Returned value can be one of the following values:
4930 * @arg @ref LL_TIM_INDEX_UP_DOWN
4931 * @arg @ref LL_TIM_INDEX_UP
4932 * @arg @ref LL_TIM_INDEX_DOWN
4933 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)4934 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
4935 {
4936 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4937 }
4938
4939 /**
4940 * @brief Set index blanking
4941 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4942 * a timer instance provides an index input.
4943 * @rmtoll ECR IBLK LL_TIM_SetIndexblanking
4944 * @param TIMx Timer instance
4945 * @param Indexblanking This parameter can be one of the following values:
4946 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4947 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4948 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4949 * @retval None
4950 */
LL_TIM_SetIndexblanking(TIM_TypeDef * TIMx,uint32_t Indexblanking)4951 __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
4952 {
4953 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
4954 }
4955
4956 /**
4957 * @brief Get actual index blanking
4958 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4959 * a timer instance provides an index input.
4960 * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
4961 * @param TIMx Timer instance
4962 * @retval Returned value can be one of the following values:
4963 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4964 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4965 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4966 */
LL_TIM_GetIndexblanking(const TIM_TypeDef * TIMx)4967 __STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
4968 {
4969 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
4970 }
4971
4972
4973 /**
4974 * @brief Enable first index.
4975 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4976 * a timer instance provides an index input.
4977 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4978 * @param TIMx Timer instance
4979 * @retval None
4980 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)4981 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4982 {
4983 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
4984 }
4985
4986 /**
4987 * @brief Disable first index.
4988 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4989 * a timer instance provides an index input.
4990 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
4991 * @param TIMx Timer instance
4992 * @retval None
4993 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)4994 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
4995 {
4996 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
4997 }
4998
4999 /**
5000 * @brief Indicates whether first index is enabled.
5001 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5002 * a timer instance provides an index input.
5003 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
5004 * @param TIMx Timer instance
5005 * @retval State of bit (1 or 0).
5006 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)5007 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
5008 {
5009 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
5010 }
5011
5012 /**
5013 * @brief Set index positioning
5014 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5015 * a timer instance provides an index input.
5016 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
5017 * @param TIMx Timer instance
5018 * @param IndexPositionning This parameter can be one of the following values:
5019 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
5020 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
5021 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
5022 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
5023 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
5024 * @arg @ref LL_TIM_INDEX_POSITION_UP
5025 * @retval None
5026 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)5027 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
5028 {
5029 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
5030 }
5031
5032 /**
5033 * @brief Get actual index positioning
5034 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5035 * a timer instance provides an index input.
5036 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
5037 * @param TIMx Timer instance
5038 * @retval Returned value can be one of the following values:
5039 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
5040 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
5041 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
5042 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
5043 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
5044 * @arg @ref LL_TIM_INDEX_POSITION_UP
5045 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)5046 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
5047 {
5048 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
5049 }
5050
5051 /**
5052 * @brief Configure encoder index.
5053 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5054 * a timer instance provides an index input.
5055 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
5056 * ECR IBLK LL_TIM_ConfigIDX\n
5057 * ECR FIDX LL_TIM_ConfigIDX\n
5058 * ECR IPOS LL_TIM_ConfigIDX
5059 * @param TIMx Timer instance
5060 * @param Configuration This parameter must be a combination of all the following values:
5061 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
5062 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
5063 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
5064 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
5065 * @retval None
5066 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)5067 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
5068 {
5069 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
5070 }
5071
5072 /**
5073 * @}
5074 */
5075
5076 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
5077 * @{
5078 */
5079 /**
5080 * @brief Remap TIM inputs (input channel, internal/external triggers).
5081 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
5082 * a some timer inputs can be remapped.
5083 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
5084 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
5085 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
5086 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
5087 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
5088 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
5089 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
5090 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
5091 * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
5092 * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n
5093 * TIM12_TISEL TI2SEL LL_TIM_SetRemap\n
5094 * TIM13_TISEL TI1SEL LL_TIM_SetRemap\n
5095 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
5096 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
5097 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
5098 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
5099 * TIM17_TISEL TI1SEL LL_TIM_SetRemap
5100 *
5101 * @param TIMx Timer instance
5102 * @param Remap Remap param depends on the TIMx. Description available only
5103 * in CHM version of the User Manual (not in .pdf).
5104 * Otherwise see Reference Manual description of TISEL registers.
5105 *
5106 * Below description summarizes "Timer Instance" and "Remap" param combinations:
5107 *
5108 * TIM1: one of the following values:
5109 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
5110 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*)
5111 * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output (*)
5112 *
5113 * TIM2: one of the following values:
5114 * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO
5115 * @arg LL_TIM_TIM2_TI1_RMP_LSI: TIM2 TI1 is connected to LSI (*)
5116 * @arg LL_TIM_TIM2_TI1_RMP_LSE: TIM2 TI1 is connected to LSE (*)
5117 * @arg LL_TIM_TIM2_TI1_RMP_RTC: TIM2 TI1 is connected to RTC (*)
5118 * @arg LL_TIM_TIM2_TI1_RMP_TIM3_TI1: TIM2 TI1 is connected to TIM3 TI1 (*)
5119 * @arg LL_TIM_TIM2_TI1_RMP_ETH_PPS: TIM2 TI1 is connected to ETH PPS (*)
5120 * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI1 is connected to COMP1 output (*)
5121 * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI1 is connected to COMP2 output (*)
5122 * @arg LL_TIM_TIM2_TI1_RMP_PLAY1_OUT3: TIM2 TI1 is connected to PLAY1 output 3 (*)
5123 * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO
5124 * @arg LL_TIM_TIM2_TI2_RMP_HSI_1024: TIM2 TI2 is connected to HSI 1024 (*)
5125 * @arg LL_TIM_TIM2_TI2_RMP_CSI_128: TIM2 TI2 is connected to CSI 128 (*)
5126 * @arg LL_TIM_TIM2_TI2_RMP_MCO2: TIM2 TI2 is connected to MCO2 (*)
5127 * @arg LL_TIM_TIM2_TI2_RMP_MCO1: TIM2 TI2 is connected to MCO1 (*)
5128 * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI2 is connected to COMP1 output (*)
5129 * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI2 is connected to COMP2 output (*)
5130 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
5131 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 (*)
5132 *
5133 * TIM3: one of the following values:
5134 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
5135 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*)
5136 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output (*)
5137 * @arg LL_TIM_TIM3_TI1_RMP_MCO1: TIM3 TI1 is connected to MCO1 (*)
5138 * @arg LL_TIM_TIM3_TI1_RMP_TIM2_TI1: TIM3 TI1 is connected to TIM2 TI1 (*)
5139 * @arg LL_TIM_TIM3_TI1_RMP_HSE_1MHZ: TIM3 TI1 is connected to HSE_1MHZ (*)
5140 * @arg LL_TIM_TIM3_TI1_RMP_ETH_PPS: TIM3 TI1 is connected to ETH PPS (*)
5141 * @arg LL_TIM_TIM3_TI1_RMP_PLAY1_OUT3: TIM3 TI1 is connected to PLAY1 output 3 (*)
5142 * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO
5143 * @arg LL_TIM_TIM3_TI2_RMP_CSI_128: TIM3 TI2 is connected to CSI_128 (*)
5144 * @arg LL_TIM_TIM3_TI2_RMP_MCO2: TIM3 TI2 is connected to MCO2 (*)
5145 * @arg LL_TIM_TIM3_TI2_RMP_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*)
5146 * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output (*)
5147 * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output (*)
5148 *
5149 * TIM4: one of the following values: (**)
5150 * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO
5151 * @arg LL_TIM_TIM4_TI1_RMP_COMP1: TIM4 TI1 is connected to COMP1 output (*)
5152 * @arg LL_TIM_TIM4_TI1_RMP_COMP2: TIM4 TI1 is connected to COMP2 output (*)
5153 *
5154 * TIM5: one of the following values: (**)
5155 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
5156 * @arg LL_TIM_TIM5_TI1_RMP_COMP1: TIM5 TI1 is connected to COMP1 output (*)
5157 * @arg LL_TIM_TIM5_TI1_RMP_COMP2: TIM5 TI1 is connected to COMP2 output (*)
5158 *
5159 * TIM8: one of the following values: (**)
5160 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
5161 * @arg LL_TIM_TIM8_TI1_RMP_COMP1: TIM8 TI1 is connected to COMP1 output (*)
5162 * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output (*)
5163 *
5164 * TIM12: one of the following values: (**)
5165 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO
5166 * @arg LL_TIM_TIM12_TI1_RMP_COMP1: TIM12 TI1 is connected to COMP1 output (*)
5167 * @arg LL_TIM_TIM12_TI1_RMP_COMP2: TIM12 TI1 is connected to COMP2 output (*)
5168 * @arg LL_TIM_TIM12_TI1_RMP_HSI_1024: TIM12 TI1 is connected to HSI 1024
5169 * @arg LL_TIM_TIM12_TI1_RMP_CSI_128: TIM12 TI1 is connected to CSI 128
5170 *
5171 * TIM13: one of the following values: (**)
5172 * @arg LL_TIM_TIM13_TI1_RMP_GPIO: TIM13 TI1 is connected to GPIO
5173 * @arg LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK: TIM13 TI1 is connected to I3C1 IBI ACK (*)
5174 * @arg LL_TIM_TIM13_TI1_RMP_COMP1: TIM13 TI1 is connected to COMP1 output (*)
5175 * @arg LL_TIM_TIM13_TI1_RMP_COMP2: TIM13 TI1 is connected to COMP2 output (*)
5176 *
5177 * TIM14: one of the following values: (**)
5178 * @arg LL_TIM_TIM14_TI1_RMP_GPIO: TIM14 TI1 is connected to GPIO
5179 * @arg LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK: TIM14 TI1 is connected to I3C2 IBI ACK (*)
5180 * @arg LL_TIM_TIM14_TI1_RMP_COMP1: TIM14 TI1 is connected to COMP1 output (*)
5181 * @arg LL_TIM_TIM14_TI1_RMP_COMP2: TIM14 TI1 is connected to COMP2 output (*)
5182 *
5183 * TIM15: one of the following values: (**)
5184 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
5185 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2
5186 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3
5187 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4
5188 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
5189 * @arg LL_TIM_TIM15_TI1_RMP_CSI_128: TIM15 TI1 is connected to CSI/128
5190 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2
5191 * @arg LL_TIM_TIM15_TI1_RMP_COMP1: TIM15 TI1 is connected to COMP1 output (*)
5192 * @arg LL_TIM_TIM15_TI1_RMP_COMP2: TIM15 TI1 is connected to COMP2 output (*)
5193 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI1 is connected to GPIO
5194 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI1 is connected to TIM2
5195 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI1 is connected to TIM3
5196 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI1 is connected to TIM4
5197 * @arg LL_TIM_TIM15_TI2_RMP_COMP1: TIM15 TI2 is connected to COMP1 output (*)
5198 * @arg LL_TIM_TIM15_TI2_RMP_COMP2: TIM15 TI2 is connected to COMP2 output (*)
5199 *
5200 * TIM16: one of the following values: (**)
5201 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
5202 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
5203 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
5204 * @arg LL_TIM_TIM16_TI1_RMP_RTC_WKUP: TIM16 TI1 is connected to RTC_WKUP
5205 * @arg LL_TIM_TIM16_TI1_RMP_COMP1: TIM16 TI1 is connected to COMP1 output (*)
5206 * @arg LL_TIM_TIM16_TI1_RMP_COMP2: TIM16 TI1 is connected to COMP2 output (*)
5207 *
5208 * TIM17: one of the following values: (**)
5209 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
5210 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE_1MHZ
5211 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1
5212 * @arg LL_TIM_TIM17_TI1_RMP_COMP1: TIM17 TI1 is connected to COMP1 output (*)
5213 * @arg LL_TIM_TIM17_TI1_RMP_COMP2: TIM17 TI1 is connected to COMP2 output (*)
5214 *
5215 * (*) Value not defined in all devices. \n
5216 * (**) Timer instance not available on all devices. \n
5217 *
5218 * @retval None
5219 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)5220 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
5221 {
5222 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
5223 }
5224
5225 /**
5226 * @brief Enable request for HSE 1MHz clock used for TISEL remap.
5227 * @note Only TIM17 support HSE 1MHz remap
5228 * @rmtoll OR1 RTCPREEN LL_TIM_EnableRTCPRE
5229 * @param TIMx Timer instance
5230 * @retval None
5231 */
LL_TIM_EnableRTCPRE(TIM_TypeDef * TIMx)5232 __STATIC_INLINE void LL_TIM_EnableRTCPRE(TIM_TypeDef *TIMx)
5233 {
5234 SET_BIT(TIMx->OR1, TIM_OR1_RTCPREEN);
5235 }
5236
5237 /**
5238 * @brief Disable request for HSE 1MHz clock used for TISEL remap.
5239 * @note Only TIM17 support HSE 1MHz remap
5240 * @rmtoll OR1 RTCPREEN LL_TIM_DisableRTCPRE
5241 * @param TIMx Timer instance
5242 * @retval None
5243 */
LL_TIM_DisableRTCPRE(TIM_TypeDef * TIMx)5244 __STATIC_INLINE void LL_TIM_DisableRTCPRE(TIM_TypeDef *TIMx)
5245 {
5246 CLEAR_BIT(TIMx->OR1, TIM_OR1_RTCPREEN);
5247 }
5248
5249 /**
5250 * @brief Indicate whether request for HSE 1MHz clock is enabled.
5251 * @note Only TIM17 support HSE 1MHz remap
5252 * @rmtoll OR1 RTCPREEN LL_TIM_IsEnabledRTCPRE
5253 * @param TIMx Timer instance
5254 * @retval State of bit (1 or 0).
5255 */
LL_TIM_IsEnabledRTCPRE(const TIM_TypeDef * TIMx)5256 __STATIC_INLINE uint32_t LL_TIM_IsEnabledRTCPRE(const TIM_TypeDef *TIMx)
5257 {
5258 return ((READ_BIT(TIMx->OR1, TIM_OR1_RTCPREEN) == (TIM_OR1_RTCPREEN)) ? 1UL : 0UL);
5259 }
5260
5261 /**
5262 * @}
5263 */
5264
5265 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
5266 * @{
5267 */
5268 /**
5269 * @brief Set the OCREF clear input source
5270 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
5271 * @note This function can only be used in Output compare and PWM modes.
5272 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
5273 * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
5274 * @param TIMx Timer instance
5275 * @param OCRefClearInputSource This parameter can be one of the following values:
5276 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
5277 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 (*)
5278 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*)
5279 *
5280 * (*) Value not defined in all devices. \n
5281 * @retval None
5282 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)5283 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
5284 {
5285 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
5286 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
5287 MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
5288 }
5289 /**
5290 * @}
5291 */
5292
5293 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
5294 * @{
5295 */
5296 /**
5297 * @brief Clear the update interrupt flag (UIF).
5298 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
5299 * @param TIMx Timer instance
5300 * @retval None
5301 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)5302 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
5303 {
5304 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
5305 }
5306
5307 /**
5308 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
5309 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
5310 * @param TIMx Timer instance
5311 * @retval State of bit (1 or 0).
5312 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)5313 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
5314 {
5315 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
5316 }
5317
5318 /**
5319 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
5320 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
5321 * @param TIMx Timer instance
5322 * @retval None
5323 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)5324 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
5325 {
5326 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
5327 }
5328
5329 /**
5330 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
5331 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
5332 * @param TIMx Timer instance
5333 * @retval State of bit (1 or 0).
5334 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)5335 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
5336 {
5337 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
5338 }
5339
5340 /**
5341 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
5342 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
5343 * @param TIMx Timer instance
5344 * @retval None
5345 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)5346 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
5347 {
5348 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
5349 }
5350
5351 /**
5352 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
5353 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
5354 * @param TIMx Timer instance
5355 * @retval State of bit (1 or 0).
5356 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)5357 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
5358 {
5359 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
5360 }
5361
5362 /**
5363 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
5364 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
5365 * @param TIMx Timer instance
5366 * @retval None
5367 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)5368 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
5369 {
5370 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
5371 }
5372
5373 /**
5374 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
5375 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
5376 * @param TIMx Timer instance
5377 * @retval State of bit (1 or 0).
5378 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)5379 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
5380 {
5381 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
5382 }
5383
5384 /**
5385 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
5386 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
5387 * @param TIMx Timer instance
5388 * @retval None
5389 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)5390 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
5391 {
5392 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
5393 }
5394
5395 /**
5396 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
5397 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
5398 * @param TIMx Timer instance
5399 * @retval State of bit (1 or 0).
5400 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)5401 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
5402 {
5403 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
5404 }
5405
5406 /**
5407 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
5408 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
5409 * @param TIMx Timer instance
5410 * @retval None
5411 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)5412 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
5413 {
5414 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
5415 }
5416
5417 /**
5418 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
5419 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
5420 * @param TIMx Timer instance
5421 * @retval State of bit (1 or 0).
5422 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)5423 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
5424 {
5425 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
5426 }
5427
5428 /**
5429 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
5430 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
5431 * @param TIMx Timer instance
5432 * @retval None
5433 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)5434 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
5435 {
5436 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
5437 }
5438
5439 /**
5440 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
5441 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
5442 * @param TIMx Timer instance
5443 * @retval State of bit (1 or 0).
5444 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)5445 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
5446 {
5447 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
5448 }
5449
5450 /**
5451 * @brief Clear the commutation interrupt flag (COMIF).
5452 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
5453 * @param TIMx Timer instance
5454 * @retval None
5455 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)5456 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
5457 {
5458 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
5459 }
5460
5461 /**
5462 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5463 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5464 * @param TIMx Timer instance
5465 * @retval State of bit (1 or 0).
5466 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)5467 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
5468 {
5469 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5470 }
5471
5472 /**
5473 * @brief Clear the trigger interrupt flag (TIF).
5474 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5475 * @param TIMx Timer instance
5476 * @retval None
5477 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5478 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5479 {
5480 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5481 }
5482
5483 /**
5484 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5485 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5486 * @param TIMx Timer instance
5487 * @retval State of bit (1 or 0).
5488 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5489 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5490 {
5491 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5492 }
5493
5494 /**
5495 * @brief Clear the break interrupt flag (BIF).
5496 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5497 * @param TIMx Timer instance
5498 * @retval None
5499 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5500 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5501 {
5502 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5503 }
5504
5505 /**
5506 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5507 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5508 * @param TIMx Timer instance
5509 * @retval State of bit (1 or 0).
5510 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5511 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5512 {
5513 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5514 }
5515
5516 /**
5517 * @brief Clear the break 2 interrupt flag (B2IF).
5518 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5519 * @param TIMx Timer instance
5520 * @retval None
5521 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5522 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5523 {
5524 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5525 }
5526
5527 /**
5528 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5529 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5530 * @param TIMx Timer instance
5531 * @retval State of bit (1 or 0).
5532 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5533 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5534 {
5535 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5536 }
5537
5538 /**
5539 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5540 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5541 * @param TIMx Timer instance
5542 * @retval None
5543 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5544 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5545 {
5546 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5547 }
5548
5549 /**
5550 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5551 * (Capture/Compare 1 interrupt is pending).
5552 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5553 * @param TIMx Timer instance
5554 * @retval State of bit (1 or 0).
5555 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5556 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5557 {
5558 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5559 }
5560
5561 /**
5562 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5563 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5564 * @param TIMx Timer instance
5565 * @retval None
5566 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5567 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5568 {
5569 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5570 }
5571
5572 /**
5573 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5574 * (Capture/Compare 2 over-capture interrupt is pending).
5575 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5576 * @param TIMx Timer instance
5577 * @retval State of bit (1 or 0).
5578 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5579 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5580 {
5581 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5582 }
5583
5584 /**
5585 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5586 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5587 * @param TIMx Timer instance
5588 * @retval None
5589 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5590 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5591 {
5592 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5593 }
5594
5595 /**
5596 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5597 * (Capture/Compare 3 over-capture interrupt is pending).
5598 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5599 * @param TIMx Timer instance
5600 * @retval State of bit (1 or 0).
5601 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5602 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5603 {
5604 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5605 }
5606
5607 /**
5608 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5609 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5610 * @param TIMx Timer instance
5611 * @retval None
5612 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5613 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5614 {
5615 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5616 }
5617
5618 /**
5619 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5620 * (Capture/Compare 4 over-capture interrupt is pending).
5621 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5622 * @param TIMx Timer instance
5623 * @retval State of bit (1 or 0).
5624 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5625 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5626 {
5627 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5628 }
5629
5630 /**
5631 * @brief Clear the system break interrupt flag (SBIF).
5632 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5633 * @param TIMx Timer instance
5634 * @retval None
5635 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5636 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5637 {
5638 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5639 }
5640
5641 /**
5642 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5643 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5644 * @param TIMx Timer instance
5645 * @retval State of bit (1 or 0).
5646 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5647 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5648 {
5649 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5650 }
5651
5652 /**
5653 * @brief Clear the transition error interrupt flag (TERRF).
5654 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5655 * a timer instance provides encoder error management.
5656 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5657 * @param TIMx Timer instance
5658 * @retval None
5659 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5660 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5661 {
5662 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5663 }
5664
5665 /**
5666 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5667 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5668 * a timer instance provides encoder error management.
5669 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5670 * @param TIMx Timer instance
5671 * @retval State of bit (1 or 0).
5672 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5673 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5674 {
5675 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5676 }
5677
5678 /**
5679 * @brief Clear the index error interrupt flag (IERRF).
5680 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5681 * a timer instance provides encoder error management.
5682 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5683 * @param TIMx Timer instance
5684 * @retval None
5685 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5686 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5687 {
5688 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5689 }
5690
5691 /**
5692 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5693 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5694 * a timer instance provides encoder error management.
5695 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5696 * @param TIMx Timer instance
5697 * @retval State of bit (1 or 0).
5698 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5699 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5700 {
5701 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5702 }
5703
5704 /**
5705 * @brief Clear the direction change interrupt flag (DIRF).
5706 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5707 * a timer instance provides encoder interrupt management.
5708 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5709 * @param TIMx Timer instance
5710 * @retval None
5711 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5712 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5713 {
5714 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5715 }
5716
5717 /**
5718 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5719 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5720 * a timer instance provides encoder interrupt management.
5721 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5722 * @param TIMx Timer instance
5723 * @retval State of bit (1 or 0).
5724 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5725 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5726 {
5727 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5728 }
5729
5730 /**
5731 * @brief Clear the index interrupt flag (IDXF).
5732 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5733 * a timer instance provides encoder interrupt management.
5734 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5735 * @param TIMx Timer instance
5736 * @retval None
5737 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5738 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5739 {
5740 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5741 }
5742
5743 /**
5744 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5745 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5746 * a timer instance provides encoder interrupt management.
5747 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5748 * @param TIMx Timer instance
5749 * @retval State of bit (1 or 0).
5750 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5751 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5752 {
5753 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5754 }
5755 /**
5756 * @}
5757 */
5758
5759 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5760 * @{
5761 */
5762 /**
5763 * @brief Enable update interrupt (UIE).
5764 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5765 * @param TIMx Timer instance
5766 * @retval None
5767 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5768 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5769 {
5770 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5771 }
5772
5773 /**
5774 * @brief Disable update interrupt (UIE).
5775 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5776 * @param TIMx Timer instance
5777 * @retval None
5778 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5779 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5780 {
5781 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5782 }
5783
5784 /**
5785 * @brief Indicates whether the update interrupt (UIE) is enabled.
5786 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5787 * @param TIMx Timer instance
5788 * @retval State of bit (1 or 0).
5789 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5790 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5791 {
5792 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5793 }
5794
5795 /**
5796 * @brief Enable capture/compare 1 interrupt (CC1IE).
5797 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5798 * @param TIMx Timer instance
5799 * @retval None
5800 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5801 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5802 {
5803 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5804 }
5805
5806 /**
5807 * @brief Disable capture/compare 1 interrupt (CC1IE).
5808 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5809 * @param TIMx Timer instance
5810 * @retval None
5811 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5812 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5813 {
5814 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5815 }
5816
5817 /**
5818 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5819 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5820 * @param TIMx Timer instance
5821 * @retval State of bit (1 or 0).
5822 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5823 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5824 {
5825 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5826 }
5827
5828 /**
5829 * @brief Enable capture/compare 2 interrupt (CC2IE).
5830 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5831 * @param TIMx Timer instance
5832 * @retval None
5833 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5834 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5835 {
5836 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5837 }
5838
5839 /**
5840 * @brief Disable capture/compare 2 interrupt (CC2IE).
5841 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5842 * @param TIMx Timer instance
5843 * @retval None
5844 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5845 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5846 {
5847 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5848 }
5849
5850 /**
5851 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5852 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5853 * @param TIMx Timer instance
5854 * @retval State of bit (1 or 0).
5855 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)5856 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
5857 {
5858 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5859 }
5860
5861 /**
5862 * @brief Enable capture/compare 3 interrupt (CC3IE).
5863 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5864 * @param TIMx Timer instance
5865 * @retval None
5866 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)5867 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5868 {
5869 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5870 }
5871
5872 /**
5873 * @brief Disable capture/compare 3 interrupt (CC3IE).
5874 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5875 * @param TIMx Timer instance
5876 * @retval None
5877 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)5878 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5879 {
5880 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5881 }
5882
5883 /**
5884 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5885 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5886 * @param TIMx Timer instance
5887 * @retval State of bit (1 or 0).
5888 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)5889 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
5890 {
5891 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5892 }
5893
5894 /**
5895 * @brief Enable capture/compare 4 interrupt (CC4IE).
5896 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5897 * @param TIMx Timer instance
5898 * @retval None
5899 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)5900 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5901 {
5902 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5903 }
5904
5905 /**
5906 * @brief Disable capture/compare 4 interrupt (CC4IE).
5907 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5908 * @param TIMx Timer instance
5909 * @retval None
5910 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)5911 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5912 {
5913 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5914 }
5915
5916 /**
5917 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
5918 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
5919 * @param TIMx Timer instance
5920 * @retval State of bit (1 or 0).
5921 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)5922 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
5923 {
5924 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
5925 }
5926
5927 /**
5928 * @brief Enable commutation interrupt (COMIE).
5929 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
5930 * @param TIMx Timer instance
5931 * @retval None
5932 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)5933 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
5934 {
5935 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
5936 }
5937
5938 /**
5939 * @brief Disable commutation interrupt (COMIE).
5940 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
5941 * @param TIMx Timer instance
5942 * @retval None
5943 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)5944 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
5945 {
5946 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
5947 }
5948
5949 /**
5950 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
5951 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
5952 * @param TIMx Timer instance
5953 * @retval State of bit (1 or 0).
5954 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)5955 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
5956 {
5957 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
5958 }
5959
5960 /**
5961 * @brief Enable trigger interrupt (TIE).
5962 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
5963 * @param TIMx Timer instance
5964 * @retval None
5965 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)5966 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
5967 {
5968 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
5969 }
5970
5971 /**
5972 * @brief Disable trigger interrupt (TIE).
5973 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
5974 * @param TIMx Timer instance
5975 * @retval None
5976 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)5977 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
5978 {
5979 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
5980 }
5981
5982 /**
5983 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
5984 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
5985 * @param TIMx Timer instance
5986 * @retval State of bit (1 or 0).
5987 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)5988 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
5989 {
5990 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
5991 }
5992
5993 /**
5994 * @brief Enable break interrupt (BIE).
5995 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
5996 * @param TIMx Timer instance
5997 * @retval None
5998 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)5999 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
6000 {
6001 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
6002 }
6003
6004 /**
6005 * @brief Disable break interrupt (BIE).
6006 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
6007 * @param TIMx Timer instance
6008 * @retval None
6009 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)6010 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
6011 {
6012 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
6013 }
6014
6015 /**
6016 * @brief Indicates whether the break interrupt (BIE) is enabled.
6017 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
6018 * @param TIMx Timer instance
6019 * @retval State of bit (1 or 0).
6020 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)6021 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
6022 {
6023 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
6024 }
6025
6026 /**
6027 * @brief Enable transition error interrupt (TERRIE).
6028 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6029 * a timer instance provides encoder error management.
6030 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
6031 * @param TIMx Timer instance
6032 * @retval None
6033 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)6034 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
6035 {
6036 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
6037 }
6038
6039 /**
6040 * @brief Disable transition error interrupt (TERRIE).
6041 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6042 * a timer instance provides encoder error management.
6043 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
6044 * @param TIMx Timer instance
6045 * @retval None
6046 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)6047 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
6048 {
6049 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
6050 }
6051
6052 /**
6053 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
6054 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6055 * a timer instance provides encoder error management.
6056 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
6057 * @param TIMx Timer instance
6058 * @retval State of bit (1 or 0).
6059 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)6060 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
6061 {
6062 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
6063 }
6064
6065 /**
6066 * @brief Enable index error interrupt (IERRIE).
6067 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6068 * a timer instance provides encoder error management.
6069 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
6070 * @param TIMx Timer instance
6071 * @retval None
6072 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)6073 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
6074 {
6075 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6076 }
6077
6078 /**
6079 * @brief Disable index error interrupt (IERRIE).
6080 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6081 * a timer instance provides encoder error management.
6082 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
6083 * @param TIMx Timer instance
6084 * @retval None
6085 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)6086 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
6087 {
6088 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6089 }
6090
6091 /**
6092 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
6093 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6094 * a timer instance provides encoder error management.
6095 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
6096 * @param TIMx Timer instance
6097 * @retval State of bit (1 or 0).
6098 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)6099 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
6100 {
6101 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
6102 }
6103
6104 /**
6105 * @brief Enable direction change interrupt (DIRIE).
6106 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6107 * a timer instance provides encoder interrupt management.
6108 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
6109 * @param TIMx Timer instance
6110 * @retval None
6111 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)6112 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
6113 {
6114 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6115 }
6116
6117 /**
6118 * @brief Disable direction change interrupt (DIRIE).
6119 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6120 * a timer instance provides encoder interrupt management.
6121 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
6122 * @param TIMx Timer instance
6123 * @retval None
6124 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)6125 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
6126 {
6127 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6128 }
6129
6130 /**
6131 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
6132 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6133 * a timer instance provides encoder interrupt management.
6134 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
6135 * @param TIMx Timer instance
6136 * @retval State of bit (1 or 0).
6137 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)6138 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
6139 {
6140 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
6141 }
6142
6143 /**
6144 * @brief Enable index interrupt (IDXIE).
6145 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6146 * a timer instance provides encoder interrupt management.
6147 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
6148 * @param TIMx Timer instance
6149 * @retval None
6150 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)6151 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
6152 {
6153 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6154 }
6155
6156 /**
6157 * @brief Disable index interrupt (IDXIE).
6158 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6159 * a timer instance provides encoder interrupt management.
6160 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
6161 * @param TIMx Timer instance
6162 * @retval None
6163 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)6164 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
6165 {
6166 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6167 }
6168
6169 /**
6170 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
6171 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6172 * a timer instance provides encoder interrupt management.
6173 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
6174 * @param TIMx Timer instance
6175 * @retval State of bit (1 or 0).
6176 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)6177 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
6178 {
6179 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
6180 }
6181
6182 /**
6183 * @}
6184 */
6185
6186 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
6187 * @{
6188 */
6189 /**
6190 * @brief Enable update DMA request (UDE).
6191 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
6192 * @param TIMx Timer instance
6193 * @retval None
6194 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)6195 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6196 {
6197 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
6198 }
6199
6200 /**
6201 * @brief Disable update DMA request (UDE).
6202 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
6203 * @param TIMx Timer instance
6204 * @retval None
6205 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)6206 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6207 {
6208 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
6209 }
6210
6211 /**
6212 * @brief Indicates whether the update DMA request (UDE) is enabled.
6213 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
6214 * @param TIMx Timer instance
6215 * @retval State of bit (1 or 0).
6216 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)6217 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
6218 {
6219 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
6220 }
6221
6222 /**
6223 * @brief Enable capture/compare 1 DMA request (CC1DE).
6224 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
6225 * @param TIMx Timer instance
6226 * @retval None
6227 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)6228 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
6229 {
6230 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6231 }
6232
6233 /**
6234 * @brief Disable capture/compare 1 DMA request (CC1DE).
6235 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
6236 * @param TIMx Timer instance
6237 * @retval None
6238 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)6239 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
6240 {
6241 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6242 }
6243
6244 /**
6245 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
6246 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
6247 * @param TIMx Timer instance
6248 * @retval State of bit (1 or 0).
6249 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)6250 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
6251 {
6252 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
6253 }
6254
6255 /**
6256 * @brief Enable capture/compare 2 DMA request (CC2DE).
6257 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
6258 * @param TIMx Timer instance
6259 * @retval None
6260 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)6261 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
6262 {
6263 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6264 }
6265
6266 /**
6267 * @brief Disable capture/compare 2 DMA request (CC2DE).
6268 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
6269 * @param TIMx Timer instance
6270 * @retval None
6271 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)6272 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
6273 {
6274 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6275 }
6276
6277 /**
6278 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
6279 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
6280 * @param TIMx Timer instance
6281 * @retval State of bit (1 or 0).
6282 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)6283 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
6284 {
6285 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
6286 }
6287
6288 /**
6289 * @brief Enable capture/compare 3 DMA request (CC3DE).
6290 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
6291 * @param TIMx Timer instance
6292 * @retval None
6293 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)6294 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
6295 {
6296 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6297 }
6298
6299 /**
6300 * @brief Disable capture/compare 3 DMA request (CC3DE).
6301 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
6302 * @param TIMx Timer instance
6303 * @retval None
6304 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)6305 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
6306 {
6307 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6308 }
6309
6310 /**
6311 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
6312 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
6313 * @param TIMx Timer instance
6314 * @retval State of bit (1 or 0).
6315 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)6316 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
6317 {
6318 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
6319 }
6320
6321 /**
6322 * @brief Enable capture/compare 4 DMA request (CC4DE).
6323 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
6324 * @param TIMx Timer instance
6325 * @retval None
6326 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)6327 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
6328 {
6329 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6330 }
6331
6332 /**
6333 * @brief Disable capture/compare 4 DMA request (CC4DE).
6334 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
6335 * @param TIMx Timer instance
6336 * @retval None
6337 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)6338 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
6339 {
6340 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6341 }
6342
6343 /**
6344 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
6345 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
6346 * @param TIMx Timer instance
6347 * @retval State of bit (1 or 0).
6348 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)6349 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
6350 {
6351 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
6352 }
6353
6354 /**
6355 * @brief Enable commutation DMA request (COMDE).
6356 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
6357 * @param TIMx Timer instance
6358 * @retval None
6359 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)6360 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
6361 {
6362 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
6363 }
6364
6365 /**
6366 * @brief Disable commutation DMA request (COMDE).
6367 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
6368 * @param TIMx Timer instance
6369 * @retval None
6370 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)6371 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
6372 {
6373 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
6374 }
6375
6376 /**
6377 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
6378 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
6379 * @param TIMx Timer instance
6380 * @retval State of bit (1 or 0).
6381 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)6382 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
6383 {
6384 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
6385 }
6386
6387 /**
6388 * @brief Enable trigger interrupt (TDE).
6389 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
6390 * @param TIMx Timer instance
6391 * @retval None
6392 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)6393 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
6394 {
6395 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
6396 }
6397
6398 /**
6399 * @brief Disable trigger interrupt (TDE).
6400 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
6401 * @param TIMx Timer instance
6402 * @retval None
6403 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)6404 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
6405 {
6406 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
6407 }
6408
6409 /**
6410 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
6411 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
6412 * @param TIMx Timer instance
6413 * @retval State of bit (1 or 0).
6414 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)6415 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
6416 {
6417 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
6418 }
6419
6420 /**
6421 * @}
6422 */
6423
6424 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
6425 * @{
6426 */
6427 /**
6428 * @brief Generate an update event.
6429 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
6430 * @param TIMx Timer instance
6431 * @retval None
6432 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)6433 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
6434 {
6435 SET_BIT(TIMx->EGR, TIM_EGR_UG);
6436 }
6437
6438 /**
6439 * @brief Generate Capture/Compare 1 event.
6440 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
6441 * @param TIMx Timer instance
6442 * @retval None
6443 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)6444 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
6445 {
6446 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
6447 }
6448
6449 /**
6450 * @brief Generate Capture/Compare 2 event.
6451 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
6452 * @param TIMx Timer instance
6453 * @retval None
6454 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)6455 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
6456 {
6457 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
6458 }
6459
6460 /**
6461 * @brief Generate Capture/Compare 3 event.
6462 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6463 * @param TIMx Timer instance
6464 * @retval None
6465 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6466 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6467 {
6468 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6469 }
6470
6471 /**
6472 * @brief Generate Capture/Compare 4 event.
6473 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6474 * @param TIMx Timer instance
6475 * @retval None
6476 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6477 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6478 {
6479 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6480 }
6481
6482 /**
6483 * @brief Generate commutation event.
6484 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6485 * @param TIMx Timer instance
6486 * @retval None
6487 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6488 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6489 {
6490 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6491 }
6492
6493 /**
6494 * @brief Generate trigger event.
6495 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6496 * @param TIMx Timer instance
6497 * @retval None
6498 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6499 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6500 {
6501 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6502 }
6503
6504 /**
6505 * @brief Generate break event.
6506 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6507 * @param TIMx Timer instance
6508 * @retval None
6509 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6510 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6511 {
6512 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6513 }
6514
6515 /**
6516 * @brief Generate break 2 event.
6517 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6518 * @param TIMx Timer instance
6519 * @retval None
6520 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6521 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6522 {
6523 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6524 }
6525
6526 /**
6527 * @}
6528 */
6529
6530 #if defined(USE_FULL_LL_DRIVER)
6531 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6532 * @{
6533 */
6534
6535 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
6536 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6537 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6538 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6539 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6540 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6541 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6542 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6543 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6544 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6545 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6546 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6547 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6548 /**
6549 * @}
6550 */
6551 #endif /* USE_FULL_LL_DRIVER */
6552
6553 /**
6554 * @}
6555 */
6556
6557 /**
6558 * @}
6559 */
6560
6561 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
6562
6563 /**
6564 * @}
6565 */
6566
6567 #ifdef __cplusplus
6568 }
6569 #endif
6570
6571 #endif /* __STM32H5xx_LL_TIM_H */
6572
