1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_LL_SDMMC_H 21 #define STM32H5xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_Driver 31 * @{ 32 */ 33 #if defined (SDMMC1) || defined (SDMMC2) 34 /** @addtogroup SDMMC_LL 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SDMMC Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change. 49 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 50 51 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 52 disabled when the bus is idle. 53 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 54 55 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 56 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 57 58 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 59 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 60 61 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 62 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 63 64 #if (USE_SD_TRANSCEIVER != 0U) 65 uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. 66 This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ 67 #endif /* USE_SD_TRANSCEIVER */ 68 } SDMMC_InitTypeDef; 69 70 71 /** 72 * @brief SDMMC Command Control structure 73 */ 74 typedef struct 75 { 76 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 77 to a card as part of a command message. If a command 78 contains an argument, it must be loaded into this register 79 before writing the command to the command register. */ 80 81 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 82 Max_Data = 64 */ 83 84 uint32_t Response; /*!< Specifies the SDMMC response type. 85 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 86 87 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 88 enabled or disabled. 89 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 90 91 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 92 is enabled or disabled. 93 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 94 } SDMMC_CmdInitTypeDef; 95 96 97 /** 98 * @brief SDMMC Data Control structure 99 */ 100 typedef struct 101 { 102 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 103 104 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 105 106 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 107 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 108 109 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 110 is a read or write. 111 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 112 113 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 114 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 115 116 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 117 is enabled or disabled. 118 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 119 } SDMMC_DataInitTypeDef; 120 121 /** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure 122 * @{ 123 */ 124 typedef struct 125 { 126 __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list configuration register */ 127 __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register */ 128 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register */ 129 } SDMMC_DMALinkNodeTypeDef; 130 131 typedef struct 132 { 133 uint32_t BufferAddress; /*!< Node Buffer address */ 134 uint32_t BufferSize ; /*!< Node Buffer size */ 135 } SDMMC_DMALinkNodeConfTypeDef; 136 137 typedef struct 138 { 139 SDMMC_DMALinkNodeTypeDef *pHeadNode; /*!< Linked List Node Head */ 140 SDMMC_DMALinkNodeTypeDef *pTailNode; /*!< Linked List Node Head */ 141 uint32_t NodesCounter ; /*!< Node is ready for execution */ 142 } SDMMC_DMALinkedListTypeDef; 143 /** 144 * @} 145 */ 146 147 /* Exported constants --------------------------------------------------------*/ 148 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 149 * @{ 150 */ 151 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 152 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 153 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 154 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 155 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 156 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 157 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 158 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 159 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ 160 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 161 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 162 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 163 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ 164 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 165 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 166 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 167 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 168 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 169 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 170 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 171 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 172 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 173 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 174 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ 175 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 176 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 177 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 178 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 179 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 180 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 181 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 182 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 183 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 184 185 /** 186 * @brief SDMMC Commands Index 187 */ 188 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ 189 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ 190 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 191 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ 192 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ 193 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ 194 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 195 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ 196 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ 197 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 198 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ 199 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ 200 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ 201 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ 202 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ 203 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ 204 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ 205 /*!< for SDHS and SDXC. */ 206 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 207 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ 208 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 209 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ 210 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ 211 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 212 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 213 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ 214 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ 215 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ 216 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ 217 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ 218 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ 219 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ 220 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ 221 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ 222 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ 223 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ 224 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ 225 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ 226 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ 227 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ 228 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ 229 230 /** 231 * @brief Following commands are SD Card Specific commands. 232 * SDMMC_APP_CMD should be sent before sending these commands. 233 */ 234 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ 235 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ 236 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ 237 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ 238 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 239 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ 240 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ 241 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ 242 243 /** 244 * @brief Following commands are MMC Specific commands. 245 */ 246 #define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ 247 248 /** 249 * @brief Following commands are SD Card Specific security commands. 250 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 251 */ 252 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) 253 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) 254 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 255 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 256 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 257 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 258 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 259 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 260 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 261 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 262 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 263 264 /** 265 * @brief Masks for errors Card Status R1 (OCR Register) 266 */ 267 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 268 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 269 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 270 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 271 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 272 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 273 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 274 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 275 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 276 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 277 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 278 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 279 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 280 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 281 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 282 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 283 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 284 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 285 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 286 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 287 288 /** 289 * @brief Masks for R6 Response 290 */ 291 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 292 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 293 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 294 295 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 296 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 297 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 298 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 299 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 300 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) 301 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 302 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 303 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 304 #define SDMMC_SDR12_SWITCH_PATTERN ((uint32_t)0x80FFFF00U) 305 306 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 307 308 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 309 310 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 311 312 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 313 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 314 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 315 316 #ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ 317 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 318 #endif /* SDMMC_DATATIMEOUT */ 319 320 #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ 321 #define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT 322 #endif /* SDMMC_SWDATATIMEOUT */ 323 324 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 325 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 326 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 327 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 328 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 329 330 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 331 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 332 333 /* SDMMC FIFO Size */ 334 #define SDMMC_FIFO_SIZE 32U 335 /** 336 * @brief Command Class supported 337 */ 338 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 339 340 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 341 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 342 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 343 344 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 345 * @{ 346 */ 347 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 348 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 349 350 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 351 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 352 /** 353 * @} 354 */ 355 356 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 357 * @{ 358 */ 359 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 360 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 361 362 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 363 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 364 /** 365 * @} 366 */ 367 368 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 369 * @{ 370 */ 371 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 372 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 373 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 374 375 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 376 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 377 ((WIDE) == SDMMC_BUS_WIDE_8B)) 378 /** 379 * @} 380 */ 381 382 /** @defgroup SDMMC_LL_Speed_Mode 383 * @{ 384 */ 385 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) 386 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) 387 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) 388 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) 389 #define SDMMC_SPEED_MODE_ULTRA_SDR104 SDMMC_SPEED_MODE_ULTRA 390 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) 391 #define SDMMC_SPEED_MODE_ULTRA_SDR50 ((uint32_t)0x00000005U) 392 393 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ 394 ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ 395 ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ 396 ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ 397 ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50) || \ 398 ((MODE) == SDMMC_SPEED_MODE_DDR)) 399 400 /** 401 * @} 402 */ 403 404 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 405 * @{ 406 */ 407 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 408 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 409 410 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 411 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 412 /** 413 * @} 414 */ 415 416 /** @defgroup SDMMC_LL_Clock_Division Clock Division 417 * @{ 418 */ 419 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 420 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 421 /** 422 * @} 423 */ 424 425 /** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present 426 * @{ 427 */ 428 #define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U) 429 #define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U) 430 #define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U) 431 432 /** 433 * @} 434 */ 435 436 /** @defgroup SDMMC_LL_Command_Index Command Index 437 * @{ 438 */ 439 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 440 /** 441 * @} 442 */ 443 444 /** @defgroup SDMMC_LL_Response_Type Response Type 445 * @{ 446 */ 447 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 448 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 449 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 450 451 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 452 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 453 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 454 /** 455 * @} 456 */ 457 458 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 459 * @{ 460 */ 461 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 462 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 463 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 464 465 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 466 ((WAIT) == SDMMC_WAIT_IT) || \ 467 ((WAIT) == SDMMC_WAIT_PEND)) 468 /** 469 * @} 470 */ 471 472 /** @defgroup SDMMC_LL_CPSM_State CPSM State 473 * @{ 474 */ 475 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 476 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 477 478 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 479 ((CPSM) == SDMMC_CPSM_ENABLE)) 480 /** 481 * @} 482 */ 483 484 /** @defgroup SDMMC_LL_Response_Registers Response Register 485 * @{ 486 */ 487 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 488 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 489 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 490 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 491 492 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 493 ((RESP) == SDMMC_RESP2) || \ 494 ((RESP) == SDMMC_RESP3) || \ 495 ((RESP) == SDMMC_RESP4)) 496 497 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 498 * @{ 499 */ 500 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 501 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 502 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 503 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 504 505 /** 506 * @} 507 */ 508 509 /** @defgroup SDMMC_LL_Data_Length Data Length 510 * @{ 511 */ 512 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 513 /** 514 * @} 515 */ 516 517 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 518 * @{ 519 */ 520 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 521 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 522 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 523 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 524 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 525 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 526 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 527 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 528 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 529 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 530 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 531 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 532 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 533 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 534 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 535 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 536 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 537 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \ 538 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 539 540 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 541 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 542 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 543 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 544 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 545 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 546 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 547 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 548 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 549 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 550 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 551 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 552 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 553 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 554 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 555 /** 556 * @} 557 */ 558 559 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 560 * @{ 561 */ 562 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 563 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 564 565 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 566 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 567 /** 568 * @} 569 */ 570 571 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 572 * @{ 573 */ 574 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 575 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 576 577 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 578 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 579 /** 580 * @} 581 */ 582 583 /** @defgroup SDMMC_LL_DPSM_State DPSM State 584 * @{ 585 */ 586 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 587 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 588 589 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 590 ((DPSM) == SDMMC_DPSM_ENABLE)) 591 /** 592 * @} 593 */ 594 595 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 596 * @{ 597 */ 598 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 599 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 600 601 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 602 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 603 /** 604 * @} 605 */ 606 607 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 608 * @{ 609 */ 610 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 611 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 612 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 613 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 614 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 615 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 616 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 617 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 618 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 619 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 620 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 621 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 622 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 623 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 624 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 625 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 626 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 627 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 628 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 629 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 630 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 631 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 632 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 633 /** 634 * @} 635 */ 636 637 /** @defgroup SDMMC_LL_Flags Flags 638 * @{ 639 */ 640 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 641 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 642 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 643 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 644 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 645 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 646 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 647 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 648 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 649 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 650 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 651 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 652 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 653 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 654 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 655 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 656 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 657 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 658 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 659 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 660 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 661 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 662 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 663 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 664 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 665 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 666 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 667 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 668 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 669 670 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 671 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 672 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 673 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 674 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 675 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 676 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 677 678 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 679 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 680 681 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 682 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 683 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 684 SDMMC_FLAG_IDMABTC)) 685 /** 686 * @} 687 */ 688 689 /** 690 * @} 691 */ 692 693 /* Exported macro ------------------------------------------------------------*/ 694 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 695 * @{ 696 */ 697 698 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 699 * @brief SDMMC_LL registers bit address in the alias region 700 * @{ 701 */ 702 /* ---------------------- SDMMC registers bit mask --------------------------- */ 703 /* --- CLKCR Register ---*/ 704 /* CLKCR register clear mask */ 705 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 706 SDMMC_CLKCR_WIDBUS |\ 707 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ 708 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ 709 SDMMC_CLKCR_SELCLKRX)) 710 711 /* --- DCTRL Register ---*/ 712 /* SDMMC DCTRL Clear Mask */ 713 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 714 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 715 716 /* --- CMD Register ---*/ 717 /* CMD Register clear mask */ 718 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 719 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 720 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 721 722 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/ 723 #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA) 724 725 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/ 726 #define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4) 727 728 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/ 729 #define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2) 730 /** 731 * @} 732 */ 733 734 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 735 * @brief macros to handle interrupts and specific clock configurations 736 * @{ 737 */ 738 739 /** 740 * @brief Enable the SDMMC device interrupt. 741 * @param __INSTANCE__ Pointer to SDMMC register base 742 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. 743 * This parameter can be one or a combination of the following values: 744 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 745 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 746 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 747 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 748 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 749 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 750 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 751 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 752 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 753 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 754 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 755 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 756 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 757 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 758 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 759 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 760 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 761 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 762 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 763 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 764 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 765 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 766 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 767 * @retval None 768 */ 769 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 770 771 /** 772 * @brief Disable the SDMMC device interrupt. 773 * @param __INSTANCE__ Pointer to SDMMC register base 774 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. 775 * This parameter can be one or a combination of the following values: 776 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 777 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 778 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 779 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 780 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 781 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 782 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 783 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 784 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 785 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 786 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 787 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 788 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 789 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 790 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 791 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 792 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 793 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 794 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 795 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 796 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 797 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 798 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 799 * @retval None 800 */ 801 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 802 803 /** 804 * @brief Checks whether the specified SDMMC flag is set or not. 805 * @param __INSTANCE__ Pointer to SDMMC register base 806 * @param __FLAG__ specifies the flag to check. 807 * This parameter can be one of the following values: 808 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 809 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 810 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 811 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 812 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 813 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 814 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 815 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 816 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 817 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 818 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 819 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 820 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 821 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 822 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 823 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 824 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 825 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 826 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 827 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 828 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 829 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 830 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 831 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 832 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 833 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 834 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 835 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 836 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 837 * @retval The new state of SDMMC_FLAG (SET or RESET). 838 */ 839 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 840 841 842 /** 843 * @brief Clears the SDMMC pending flags. 844 * @param __INSTANCE__ Pointer to SDMMC register base 845 * @param __FLAG__ specifies the flag to clear. 846 * This parameter can be one or a combination of the following values: 847 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 848 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 849 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 850 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 851 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 852 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 853 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 854 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 855 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 856 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 857 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 858 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 859 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 860 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 861 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 862 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 863 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 864 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 865 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 866 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 867 * @retval None 868 */ 869 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 870 871 /** 872 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 873 * @param __INSTANCE__ Pointer to SDMMC register base 874 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 875 * This parameter can be one of the following values: 876 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 877 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 878 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 879 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 880 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 881 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 882 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 883 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 884 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 885 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 886 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 887 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 888 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 889 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 890 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 891 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 892 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 893 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 894 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 895 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 896 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 897 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 898 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 899 * @retval The new state of SDMMC_IT (SET or RESET). 900 */ 901 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 902 903 /** 904 * @brief Clears the SDMMC's interrupt pending bits. 905 * @param __INSTANCE__ Pointer to SDMMC register base 906 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 907 * This parameter can be one or a combination of the following values: 908 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 909 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 910 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 911 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 912 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 913 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 914 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 915 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 916 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 917 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 918 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 919 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 920 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 921 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 922 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 923 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 924 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 925 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 926 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 927 * @retval None 928 */ 929 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 930 931 /** 932 * @brief Enable Start the SD I/O Read Wait operation. 933 * @param __INSTANCE__ Pointer to SDMMC register base 934 * @retval None 935 */ 936 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 937 938 /** 939 * @brief Disable Start the SD I/O Read Wait operations. 940 * @param __INSTANCE__ Pointer to SDMMC register base 941 * @retval None 942 */ 943 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 944 945 /** 946 * @brief Enable Start the SD I/O Read Wait operation. 947 * @param __INSTANCE__ Pointer to SDMMC register base 948 * @retval None 949 */ 950 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 951 952 /** 953 * @brief Disable Stop the SD I/O Read Wait operations. 954 * @param __INSTANCE__ Pointer to SDMMC register base 955 * @retval None 956 */ 957 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 958 959 /** 960 * @brief Enable the SD I/O Mode Operation. 961 * @param __INSTANCE__ Pointer to SDMMC register base 962 * @retval None 963 */ 964 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 965 966 /** 967 * @brief Disable the SD I/O Mode Operation. 968 * @param __INSTANCE__ Pointer to SDMMC register base 969 * @retval None 970 */ 971 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 972 973 /** 974 * @brief Enable the SD I/O Suspend command sending. 975 * @param __INSTANCE__ Pointer to SDMMC register base 976 * @retval None 977 */ 978 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 979 980 /** 981 * @brief Disable the SD I/O Suspend command sending. 982 * @param __INSTANCE__ Pointer to SDMMC register base 983 * @retval None 984 */ 985 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 986 987 /** 988 * @brief Enable the CMDTRANS mode. 989 * @param __INSTANCE__ Pointer to SDMMC register base 990 * @retval None 991 */ 992 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 993 994 /** 995 * @brief Disable the CMDTRANS mode. 996 * @param __INSTANCE__ Pointer to SDMMC register base 997 * @retval None 998 */ 999 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 1000 1001 /** 1002 * @brief Enable the CMDSTOP mode. 1003 * @param __INSTANCE__ Pointer to SDMMC register base 1004 * @retval None 1005 */ 1006 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 1007 1008 /** 1009 * @brief Disable the CMDSTOP mode. 1010 * @param __INSTANCE__ Pointer to SDMMC register base 1011 * @retval None 1012 */ 1013 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 1014 1015 /** 1016 * @} 1017 */ 1018 1019 /** 1020 * @} 1021 */ 1022 1023 /* Exported functions --------------------------------------------------------*/ 1024 /** @addtogroup SDMMC_LL_Exported_Functions 1025 * @{ 1026 */ 1027 1028 /* Initialization/de-initialization functions **********************************/ 1029 /** @addtogroup HAL_SDMMC_LL_Group1 1030 * @{ 1031 */ 1032 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 1033 /** 1034 * @} 1035 */ 1036 1037 /* I/O operation functions *****************************************************/ 1038 /** @addtogroup HAL_SDMMC_LL_Group2 1039 * @{ 1040 */ 1041 uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx); 1042 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 1043 /** 1044 * @} 1045 */ 1046 1047 /* Peripheral Control functions ************************************************/ 1048 /** @addtogroup HAL_SDMMC_LL_Group3 1049 * @{ 1050 */ 1051 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 1052 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 1053 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1054 uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); 1055 1056 /* Command path state machine (CPSM) management functions */ 1057 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 1058 uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); 1059 uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); 1060 1061 /* Data path state machine (DPSM) management functions */ 1062 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); 1063 uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); 1064 uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); 1065 1066 /* SDMMC Cards mode management functions */ 1067 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1068 /** 1069 * @} 1070 */ 1071 1072 /* SDMMC Commands management functions ******************************************/ 1073 /** @addtogroup HAL_SDMMC_LL_Group4 1074 * @{ 1075 */ 1076 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1077 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1078 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1079 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1080 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1081 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1082 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1083 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1084 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1085 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); 1086 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1087 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr); 1088 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1089 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1090 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1091 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1092 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1093 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1094 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1095 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1096 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1097 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); 1098 uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1099 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1100 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1101 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1102 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1103 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1104 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1105 /** 1106 * @} 1107 */ 1108 1109 /* SDMMC Responses management functions *****************************************/ 1110 /** @addtogroup HAL_SDMMC_LL_Group5 1111 * @{ 1112 */ 1113 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); 1114 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); 1115 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); 1116 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); 1117 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); 1118 /** 1119 * @} 1120 */ 1121 1122 /* Linked List functions *******************************************************/ 1123 /** @addtogroup HAL_SDMMC_LL_Group6 1124 * @{ 1125 */ 1126 uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf); 1127 uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode, 1128 SDMMC_DMALinkNodeTypeDef *pNode); 1129 uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode); 1130 uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode); 1131 uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode); 1132 uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); 1133 uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); 1134 /** 1135 * @} 1136 */ 1137 1138 /** 1139 * @} 1140 */ 1141 1142 /** 1143 * @} 1144 */ 1145 1146 /** 1147 * @} 1148 */ 1149 1150 /** 1151 * @} 1152 */ 1153 #endif /* SDMMC1 || SDMMC2 */ 1154 /** 1155 * @} 1156 */ 1157 #ifdef __cplusplus 1158 } 1159 #endif 1160 1161 #endif /* STM32H5xx_LL_SDMMC_H */ 1162
