1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_PWR_H
21 #define STM32H5xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
44 * @{
45 */
46
47 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
48 * @brief Flags defines which can be used with LL_PWR_WriteReg function
49 * @{
50 */
51 /* Wake-Up Pins PWR register offsets */
52 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
53 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x7FU
54 /**
55 * @}
56 */
57 /**
58 * @}
59 */
60 /* Private macros ------------------------------------------------------------*/
61 /* Exported types ------------------------------------------------------------*/
62 /* Exported constants --------------------------------------------------------*/
63
64 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
65 * @{
66 */
67
68 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
69 * @brief Flags defines which can be used with LL_PWR_WriteReg function
70 * @{
71 */
72 #define LL_PWR_PMCR_CSSF PWR_PMCR_CSSF /*!< Clear STOP and STANDBY flags */
73 #define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */
74 #define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */
75 #define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */
76 #define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */
77 #define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */
78 #define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */
79 #define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */
80 #define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */
81 #define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */
82 /**
83 * @}
84 */
85
86 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
87 * @brief Flags defines which can be used with LL_PWR_ReadReg function
88 * @{
89 */
90 #define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */
91 #define LL_PWR_FLAG_ACTVOSRDY PWR_VOSR_ACTOVSRDY /*!< Currently applied VOS ready flag */
92 #define LL_PWR_FLAG_STOPF PWR_PMSR_STOPF /*!< STOP flag */
93 #define LL_PWR_FLAG_SBF PWR_PMSR_SBF /*!< STANDBY flag */
94 #define LL_PWR_FLAG_AVDO PWR_VMSR_AVDO /*!< Analog voltage detector output on VDDA flag */
95 #define LL_PWR_FLAG_VDDIO2RDY PWR_VMSR_VDDIO2RDY /*!< VDDIO2 ready flag */
96 #define LL_PWR_FLAG_PVDO PWR_VMSR_PVDO /*!< Programmable voltage detect output flag */
97 #define LL_PWR_FLAG_USB33RDY PWR_VMSR_USB33RDY /*!< VDDUSB ready flag */
98 #define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */
99 #define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */
100 #define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< VBAT level flag (versus high threshold) */
101 #define LL_PWR_FLAG_VBATL PWR_BDSR_VBATL /*!< VBAT level flag (versus low threshold) */
102
103
104 #define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */
105 #define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */
106 #define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */
107 #define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */
108 #define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */
109 #define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */
110 #define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */
111 #define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */
112 /**
113 * @}
114 */
115
116 /** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection
117 * @{
118 */
119 #define LL_PWR_STOP_MODE (0U) /*!< STOP 0 mode */
120 #define LL_PWR_STANDBY_MODE PWR_PMCR_LPMS /*!< STANDBY mode */
121
122
123 /**
124 * @}
125 */
126
127 /** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection
128 * @{
129 */
130 #define LL_PWR_REGU_VOLTAGE_SCALE0 PWR_VOSCR_VOS /*!< Voltage scaling range 0 */
131 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSCR_VOS_1 /*!< Voltage scaling range 1 */
132 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSCR_VOS_0 /*!< Voltage scaling range 2 */
133 #define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Voltage scaling range 3 */
134 /**
135 * @}
136 */
137
138 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
139 * @{
140 */
141 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_PMCR_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */
142 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_PMCR_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */
143 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_PMCR_SVOS_0 | PWR_PMCR_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
144 /**
145 * @}
146 */
147
148 /** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection
149 * @{
150 */
151 #define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 1.95 V */
152 #define LL_PWR_PVDLEVEL_1 PWR_VMCR_PLS_0 /*!< Voltage threshold detected by PVD 2.10 V */
153 #define LL_PWR_PVDLEVEL_2 PWR_VMCR_PLS_1 /*!< Voltage threshold detected by PVD 2.25 V */
154 #define LL_PWR_PVDLEVEL_3 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_1) /*!< Voltage threshold detected by PVD 2.40 V */
155 #define LL_PWR_PVDLEVEL_4 PWR_VMCR_PLS_2 /*!< Voltage threshold detected by PVD 2.55 V */
156 #define LL_PWR_PVDLEVEL_5 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_2) /*!< Voltage threshold detected by PVD 2.70 V */
157 #define LL_PWR_PVDLEVEL_6 (PWR_VMCR_PLS_1 | PWR_VMCR_PLS_2) /*!< Voltage threshold detected by PVD 2.85 V */
158 #define LL_PWR_PVDLEVEL_7 PWR_VMCR_PLS /*!< External input analog voltage on PVD_IN
159 pin, compared to internal VREFINT level */
160 /**
161 * @}
162 */
163
164 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
165 * @{
166 */
167 #define LL_PWR_AVDLEVEL_0 0U /*!< Analog Voltage threshold detected by AVD 1.7 V */
168 #define LL_PWR_AVDLEVEL_1 PWR_VMCR_ALS_0 /*!< Analog Voltage threshold detected by AVD 2.1 V */
169 #define LL_PWR_AVDLEVEL_2 PWR_VMCR_ALS_1 /*!< Analog Voltage threshold detected by AVD 2.5 V */
170 #define LL_PWR_AVDLEVEL_3 PWR_VMCR_ALS /*!< Analog Voltage threshold detected by AVD 2.8 V */
171
172 /**
173 * @}
174 */
175
176 /** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin
177 * @{
178 */
179 #define LL_PWR_WAKEUP_PIN1 PWR_WUCR_WUPEN1 /*!< Wakeup pin 1 enable */
180 #define LL_PWR_WAKEUP_PIN2 PWR_WUCR_WUPEN2 /*!< Wakeup pin 2 enable */
181 #define LL_PWR_WAKEUP_PIN3 PWR_WUCR_WUPEN3 /*!< Wakeup pin 3 enable */
182 #define LL_PWR_WAKEUP_PIN4 PWR_WUCR_WUPEN4 /*!< Wakeup pin 4 enable */
183 #define LL_PWR_WAKEUP_PIN5 PWR_WUCR_WUPEN5 /*!< Wakeup pin 5 enable */
184 #define LL_PWR_WAKEUP_PIN6 PWR_WUCR_WUPEN6 /*!< Wakeup pin 6 enable */
185 #define LL_PWR_WAKEUP_PIN7 PWR_WUCR_WUPEN7 /*!< Wakeup pin 7 enable */
186 #define LL_PWR_WAKEUP_PIN8 PWR_WUCR_WUPEN8 /*!< Wakeup pin 8 enable */
187 /**
188 * @}
189 */
190
191 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
192 * @{
193 */
194 #define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */
195 #define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */
196 #define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */
197 /**
198 * @}
199 */
200
201 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
202 * @{
203 */
204 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_SCCR_BYPASS /*!< The SMPS and the LDO are Bypassed.
205 The Core domains are supplied from an external source */
206 /**
207 * @}
208 */
209
210 /** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection
211 * @{
212 */
213 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */
214 #define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR_VBRS /*!< Charge the battery through a 1.5 kO resistor */
215 /**
216 * @}
217 */
218
219 /** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
220 * @{
221 */
222 #define LL_PWR_WAKEUP_PIN1_NSEC 0U /* Wake up pin 1 nsecure mode */
223 #define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /* Wake up pin 1 secure mode */
224 #define LL_PWR_WAKEUP_PIN2_NSEC 0U /* Wake up pin 2 nsecure mode */
225 #define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /* Wake up pin 2 secure mode */
226 #define LL_PWR_WAKEUP_PIN3_NSEC 0U /* Wake up pin 3 nsecure mode */
227 #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /* Wake up pin 3 secure mode */
228 #define LL_PWR_WAKEUP_PIN4_NSEC 0U /* Wake up pin 4 nsecure mode */
229 #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /* Wake up pin 4 secure mode */
230 #define LL_PWR_WAKEUP_PIN5_NSEC 0U /* Wake up pin 5 nsecure mode */
231 #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /* Wake up pin 5 secure mode */
232 #define LL_PWR_WAKEUP_PIN6_NSEC 0U /* Wake up pin 6 nsecure mode */
233 #define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /* Wake up pin 6 secure mode */
234 #define LL_PWR_WAKEUP_PIN7_NSEC 0U /* Wake up pin 7 nsecure mode */
235 #define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /* Wake up pin 7 secure mode */
236 #define LL_PWR_WAKEUP_PIN8_NSEC 0U /* Wake up pin 8 nsecure mode */
237 #define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /* Wake up pin 8 secure mode */
238
239 #define LL_PWR_RET_NSEC 0U /* Retention nsecure mode */
240 #define LL_PWR_RET_SEC PWR_SECCFGR_RETSEC /* Retention secure mode */
241 #define LL_PWR_LPM_NSEC 0U /* Low-power modes nsecure mode */
242 #define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /* Low-power modes secure mode */
243 #define LL_PWR_VDM_NSEC 0U /* Voltage detection and monitoring nsecure mode */
244 #define LL_PWR_VDM_SEC PWR_SECCFGR_SCMSEC /* Voltage detection and monitoring secure mode */
245 #define LL_PWR_VB_NSEC 0U /* Backup domain nsecure mode */
246 #define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /* Backup domain secure mode */
247 #define LL_PWR_APC_NSEC 0U /* Pull-up/pull-down nsecure mode */
248 #define LL_PWR_APC_SEC PWR_SECCFGR_VUSBSEC /* Pull-up/pull-down secure mode */
249 /**
250 * @}
251 */
252
253 /**
254 * @}
255 */
256
257 /* Exported macro ------------------------------------------------------------*/
258
259 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
260 * @{
261 */
262
263 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros
264 * @{
265 */
266
267 /**
268 * @brief Write a value in PWR register.
269 * @param __REG__ Register to be written.
270 * @param __VALUE__ Value to be written in the register.
271 * @retval None.
272 */
273 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
274
275 /**
276 * @brief Read a value in PWR register.
277 * @param __REG__ Register to be read.
278 * @retval Register value.
279 */
280 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
281 /**
282 * @}
283 */
284
285 /**
286 * @}
287 */
288
289 /* Exported functions --------------------------------------------------------*/
290
291 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
292 * @{
293 */
294
295 /** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration
296 * @{
297 */
298
299 /**
300 * @brief Set system power mode.
301 * @rmtoll PMCR LPMS LL_PWR_SetPowerMode
302 * @param Mode : This parameter can be one of the following values:
303 * @arg @ref LL_PWR_STOP_MODE
304 * @arg @ref LL_PWR_STANDBY_MODE
305 * @retval None
306 */
LL_PWR_SetPowerMode(uint32_t Mode)307 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode)
308 {
309 MODIFY_REG(PWR->PMCR, PWR_PMCR_LPMS, Mode);
310 }
311
312 /**
313 * @brief Get system power mode.
314 * @rmtoll PMCR LPMS LL_PWR_GetPowerMode
315 * @retval Returned value can be one of the following values:
316 * @arg @ref LL_PWR_STOP_MODE
317 * @arg @ref LL_PWR_STANDBY_MODE
318 */
LL_PWR_GetPowerMode(void)319 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
320 {
321 return (READ_BIT(PWR->PMCR, PWR_PMCR_LPMS));
322 }
323
324 /**
325 * @brief Set the internal Regulator output voltage in STOP mode
326 * @rmtoll PMCR SVOS LL_PWR_SetStopModeRegulVoltageScaling
327 * @param VoltageScaling This parameter can be one of the following values:
328 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
329 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
330 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
331 * @retval None
332 */
LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)333 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
334 {
335 MODIFY_REG(PWR->PMCR, PWR_PMCR_SVOS, VoltageScaling);
336 }
337
338 /**
339 * @brief Get the internal Regulator output voltage in STOP mode
340 * @rmtoll PMCR SVOS LL_PWR_GetStopModeRegulVoltageScaling
341 * @retval Returned value can be one of the following values:
342 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
343 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
344 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
345 */
LL_PWR_GetStopModeRegulVoltageScaling(void)346 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
347 {
348 return (uint32_t)(READ_BIT(PWR->PMCR, PWR_PMCR_SVOS));
349 }
350
351 /**
352 * @brief Enable the Flash Power Down in Stop Mode
353 * @rmtoll PMCR FLPS LL_PWR_EnableFlashPowerDown
354 * @retval None
355 */
LL_PWR_EnableFlashPowerDown(void)356 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
357 {
358 SET_BIT(PWR->PMCR, PWR_PMCR_FLPS);
359 }
360
361 /**
362 * @brief Disable the Flash Power Down in Stop Mode
363 * @rmtoll PMCR FLPS LL_PWR_DisableFlashPowerDown
364 * @retval None
365 */
LL_PWR_DisableFlashPowerDown(void)366 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
367 {
368 CLEAR_BIT(PWR->PMCR, PWR_PMCR_FLPS);
369 }
370
371 /**
372 * @brief Check if the Flash Power Down in Stop Mode is enabled
373 * @rmtoll PMCR FLPS LL_PWR_IsEnabledFlashPowerDown
374 * @retval State of bit (1 or 0).
375 */
LL_PWR_IsEnabledFlashPowerDown(void)376 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
377 {
378 return ((READ_BIT(PWR->PMCR, PWR_PMCR_FLPS) == (PWR_PMCR_FLPS)) ? 1UL : 0UL);
379 }
380
381 /**
382 * @brief Enable the Analog Voltage Booster (VDDA)
383 * @rmtoll PMCR BOOSTE LL_PWR_EnableAnalogBooster
384 * @retval None
385 */
LL_PWR_EnableAnalogBooster(void)386 __STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
387 {
388 SET_BIT(PWR->PMCR, PWR_PMCR_BOOSTE);
389 }
390
391 /**
392 * @brief Disable the Analog Voltage Booster (VDDA)
393 * @rmtoll PMCR BOOSTE LL_PWR_DisableAnalogBooster
394 * @retval None
395 */
LL_PWR_DisableAnalogBooster(void)396 __STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
397 {
398 CLEAR_BIT(PWR->PMCR, PWR_PMCR_BOOSTE);
399 }
400
401 /**
402 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
403 * @rmtoll PMCR BOOSTE LL_PWR_IsEnabledAnalogBooster
404 * @retval State of bit (1 or 0).
405 */
LL_PWR_IsEnabledAnalogBooster(void)406 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
407 {
408 return ((READ_BIT(PWR->PMCR, PWR_PMCR_BOOSTE) == (PWR_PMCR_BOOSTE)) ? 1UL : 0UL);
409 }
410
411 /**
412 * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready
413 * @rmtoll PMCR AVD_READY LL_PWR_EnableAnalogVoltageReady
414 * @retval None
415 */
LL_PWR_EnableAnalogVoltageReady(void)416 __STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
417 {
418 SET_BIT(PWR->PMCR, PWR_PMCR_AVD_READY);
419 }
420
421 /**
422 * @brief Disable the Analog Voltage Ready (VDDA)
423 * @rmtoll PMCR AVD_READY LL_PWR_DisableAnalogVoltageReady
424 * @retval None
425 */
LL_PWR_DisableAnalogVoltageReady(void)426 __STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
427 {
428 CLEAR_BIT(PWR->PMCR, PWR_PMCR_AVD_READY);
429 }
430
431 /**
432 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
433 * @rmtoll PMCR AVD_READY LL_PWR_IsEnabledAnalogVoltageReady
434 * @retval State of bit (1 or 0).
435 */
LL_PWR_IsEnabledAnalogVoltageReady(void)436 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
437 {
438 return ((READ_BIT(PWR->PMCR, PWR_PMCR_AVD_READY) == (PWR_PMCR_AVD_READY)) ? 1UL : 0UL);
439 }
440
441 /**
442 * @brief Enable the AHB RAM1 shut-off in Stop mode
443 * @rmtoll PMCR SRAM1SO LL_PWR_EnableAHBRAM1ShutOff
444 * @retval None
445 */
LL_PWR_EnableAHBRAM1ShutOff(void)446 __STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
447 {
448 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO);
449 }
450
451 /**
452 * @brief Disable the AHB RAM1 shut-off in Stop mode
453 * @rmtoll PMCR SRAM1SO LL_PWR_DisableAHBRAM1ShutOff
454 * @retval None
455 */
LL_PWR_DisableAHBRAM1ShutOff(void)456 __STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
457 {
458 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO);
459 }
460
461 /**
462 * @brief Check if the AHB RAM1 shut-off in Stop mode is enabled
463 * @rmtoll CR1 SRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff
464 * @retval State of bit (1 or 0).
465 */
LL_PWR_IsEnabledAHBRAM1ShutOff(void)466 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
467 {
468 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO) == (PWR_PMCR_SRAM1SO)) ? 1UL : 0UL);
469 }
470 #if defined (PWR_PMCR_SRAM2_48SO)
471 /**
472 * @brief Enable the AHB RAM2 48K Bytes shut-off in Stop mode
473 * @rmtoll PMCR SRAM2_48SO LL_PWR_EnableAHBRAM2_48K_ShutOff
474 * @retval None
475 */
LL_PWR_EnableAHBRAM2_48K_ShutOff(void)476 __STATIC_INLINE void LL_PWR_EnableAHBRAM2_48K_ShutOff(void)
477 {
478 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO);
479 }
480
481 /**
482 * @brief Disable the AHB RAM2 48K Bytes shut-off in Stop mode
483 * @rmtoll PMCR SRAM2_48SO LL_PWR_DisableAHBRAM2_48K_ShutOff
484 * @retval None
485 */
LL_PWR_DisableAHBRAM2_48K_ShutOff(void)486 __STATIC_INLINE void LL_PWR_DisableAHBRAM2_48K_ShutOff(void)
487 {
488 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO);
489 }
490
491 /**
492 * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled
493 * @rmtoll PMCR SRAM2_48SO LL_PWR_IsEnabledAHBRAM2_48K_ShutOff
494 * @retval State of bit (1 or 0).
495 */
LL_PWR_IsEnabledAHBRAM2_48K_ShutOff(void)496 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_48K_ShutOff(void)
497 {
498 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO) == (PWR_PMCR_SRAM2_48SO)) ? 1UL : 0UL);
499 }
500 #endif /* PWR_PMCR_SRAM2_48SO */
501
502 #if defined (PWR_PMCR_SRAM2_16SO)
503 /**
504 * @brief Enable the AHB RAM2 16K Bytes shut-off in Stop mode
505 * @rmtoll PMCR SRAM2_16SO LL_PWR_EnableAHBRAM2_16K_ShutOff
506 * @retval None
507 */
LL_PWR_EnableAHBRAM2_16K_ShutOff(void)508 __STATIC_INLINE void LL_PWR_EnableAHBRAM2_16K_ShutOff(void)
509 {
510 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO);
511 }
512
513 /**
514 * @brief Disable the AHB RAM2 16K Bytes shut-off in Stop mode
515 * @rmtoll PMCR SRAM2_16SO LL_PWR_DisableAHBRAM2_16K_ShutOff
516 * @retval None
517 */
LL_PWR_DisableAHBRAM2_16K_ShutOff(void)518 __STATIC_INLINE void LL_PWR_DisableAHBRAM2_16K_ShutOff(void)
519 {
520 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO);
521 }
522
523 /**
524 * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled
525 * @rmtoll PMCR SRAM2_16SO LL_PWR_IsEnabledAHBRAM2_16K_ShutOff
526 * @retval State of bit (1 or 0).
527 */
LL_PWR_IsEnabledAHBRAM2_16K_ShutOff(void)528 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_16K_ShutOff(void)
529 {
530 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO) == (PWR_PMCR_SRAM2_16SO)) ? 1UL : 0UL);
531 }
532 #endif /* PWR_PMCR_SRAM2_16SO */
533
534 #if defined(PWR_PMCR_SRAM2_16HSO)
535 /**
536 * @brief Enable the AHB RAM2 high 16K Bytes shut-off in Stop mode
537 * @rmtoll PMCR SRAM2_16HSO LL_PWR_EnableAHBRAM2_High_16K_ShutOff
538 * @retval None
539 */
LL_PWR_EnableAHBRAM2_High_16K_ShutOff(void)540 __STATIC_INLINE void LL_PWR_EnableAHBRAM2_High_16K_ShutOff(void)
541 {
542 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO);
543 }
544
545 /**
546 * @brief Disable the AHB RAM2 high 16K Bytes shut-off in Stop mode
547 * @rmtoll PMCR SRAM2_16HSO LL_PWR_DisableAHBRAM2_High_16K_ShutOff
548 * @retval None
549 */
LL_PWR_DisableAHBRAM2_High_16K_ShutOff(void)550 __STATIC_INLINE void LL_PWR_DisableAHBRAM2_High_16K_ShutOff(void)
551 {
552 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO);
553 }
554
555 /**
556 * @brief Check if the high AHB RAM2 shut-off in Stop mode is enabled
557 * @rmtoll PMCR SRAM2_16HSO LL_PWR_IsEnabledAHBRAM2_16K_ShutOff
558 * @retval State of bit (1 or 0).
559 */
LL_PWR_IsEnabledAHBRAM2_High_16K_ShutOff(void)560 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_High_16K_ShutOff(void)
561 {
562 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO) == (PWR_PMCR_SRAM2_16HSO)) ? 1UL : 0UL);
563 }
564 #endif /* PWR_PMCR_SRAM2_16HSO */
565
566 #if defined(PWR_PMCR_SRAM2_16LSO)
567 /**
568 * @brief Enable the AHB RAM2 low 16K Bytes shut-off in Stop mode
569 * @rmtoll PMCR SRAM2_16LSO LL_PWR_EnableAHBRAM2_Low_16K_ShutOff
570 * @retval None
571 */
LL_PWR_EnableAHBRAM2_Low_16K_ShutOff(void)572 __STATIC_INLINE void LL_PWR_EnableAHBRAM2_Low_16K_ShutOff(void)
573 {
574 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO);
575 }
576
577 /**
578 * @brief Disable the AHB RAM2 low 16K Bytes shut-off in Stop mode
579 * @rmtoll PMCR SRAM2_16LSO LL_PWR_DisableAHBRAM2_Low_16K_ShutOff
580 * @retval None
581 */
LL_PWR_DisableAHBRAM2_Low_16K_ShutOff(void)582 __STATIC_INLINE void LL_PWR_DisableAHBRAM2_Low_16K_ShutOff(void)
583 {
584 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO);
585 }
586
587 /**
588 * @brief Check if the low 16K AHB RAM2 shut-off in Stop mode is enabled
589 * @rmtoll PMCR SRAM2_16LSO LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff
590 * @retval State of bit (1 or 0).
591 */
LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff(void)592 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff(void)
593 {
594 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO) == (PWR_PMCR_SRAM2_16LSO)) ? 1UL : 0UL);
595 }
596 #endif /* PWR_PMCR_SRAM2_16LSO */
597
598 #if defined (PWR_PMCR_SRAM2SO)
599 /**
600 * @brief Enable the AHB RAM2 shut-off in Stop mode
601 * @rmtoll PMCR SRAM2SO LL_PWR_EnableAHBRAM2ShutOff
602 * @retval None
603 */
LL_PWR_EnableAHBRAM2ShutOff(void)604 __STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
605 {
606 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO);
607 }
608
609 /**
610 * @brief Disable the AHB RAM2 shut-off in Stop mode
611 * @rmtoll PMCR SRAM2SO LL_PWR_DisableAHBRAM2ShutOff
612 * @retval None
613 */
LL_PWR_DisableAHBRAM2ShutOff(void)614 __STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
615 {
616 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO);
617 }
618
619 /**
620 * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled
621 * @rmtoll PMCR SRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff
622 * @retval State of bit (1 or 0).
623 */
LL_PWR_IsEnabledAHBRAM2ShutOff(void)624 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
625 {
626 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO) == (PWR_PMCR_SRAM2SO)) ? 1UL : 0UL);
627 }
628 #endif /* PWR_PMCR_SRAM2SO */
629
630 #if defined (PWR_PMCR_SRAM3SO)
631 /**
632 * @brief Enable the AHB RAM3 shut-off in Stop mode
633 * @rmtoll PMCR SRAM3SO LL_PWR_EnableAHBRAM3ShutOff
634 * @retval None
635 */
LL_PWR_EnableAHBRAM3ShutOff(void)636 __STATIC_INLINE void LL_PWR_EnableAHBRAM3ShutOff(void)
637 {
638 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO);
639 }
640
641 /**
642 * @brief Disable the AHB RAM3 shut-off in Stop mode
643 * @rmtoll PMCR SRAM3SO LL_PWR_DisableAHBRAM3ShutOff
644 * @retval None
645 */
LL_PWR_DisableAHBRAM3ShutOff(void)646 __STATIC_INLINE void LL_PWR_DisableAHBRAM3ShutOff(void)
647 {
648 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO);
649 }
650
651 /**
652 * @brief Check if the AHB RAM3 shut-off in Stop mode is enabled
653 * @rmtoll PMCR SRAM3SO LL_PWR_IsEnabledAHBRAM3ShutOff
654 * @retval State of bit (1 or 0).
655 */
LL_PWR_IsEnabledAHBRAM3ShutOff(void)656 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM3ShutOff(void)
657 {
658 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO) == (PWR_PMCR_SRAM3SO)) ? 1UL : 0UL);
659 }
660 #endif /* PWR_PMCR_SRAM3SO */
661
662 #if defined (PWR_PMCR_ETHERNETSO)
663 /**
664 * @brief Enable the ETHERNET RAM shut-off in Stop mode
665 * @rmtoll PMCR ETHERNETSO LL_PWR_EnableETHERNETRAMShutOff
666 * @retval None
667 */
LL_PWR_EnableETHERNETRAMShutOff(void)668 __STATIC_INLINE void LL_PWR_EnableETHERNETRAMShutOff(void)
669 {
670 SET_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO);
671 }
672
673 /**
674 * @brief Disable the ETHERNET RAM shut-off in Stop mode
675 * @rmtoll PMCR ETHERNETSO LL_PWR_DisableETHERNETRAMShutOff
676 * @retval None
677 */
LL_PWR_DisableETHERNETRAMShutOff(void)678 __STATIC_INLINE void LL_PWR_DisableETHERNETRAMShutOff(void)
679 {
680 CLEAR_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO);
681 }
682
683 /**
684 * @brief Check if the ETHERNET RAM shut-off in Stop mode is enabled
685 * @rmtoll PMCR ETHERNETSO LL_PWR_IsEnabledETHERNETRAMShutOff
686 * @retval State of bit (1 or 0).
687 */
LL_PWR_IsEnabledETHERNETRAMShutOff(void)688 __STATIC_INLINE uint32_t LL_PWR_IsEnabledETHERNETRAMShutOff(void)
689 {
690 return ((READ_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO) == (PWR_PMCR_ETHERNETSO)) ? 1UL : 0UL);
691 }
692 #endif /* PWR_PMCR_ETHERNETSO */
693
694 /**
695 * @brief Set the regulator supply output voltage.
696 * @rmtoll VOSCR VOS LL_PWR_SetRegulVoltageScaling
697 * @param VoltageScaling This parameter can be one of the following values:
698 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
699 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
700 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
701 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
702 * @retval None
703 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)704 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
705 {
706 MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling);
707 }
708
709 /**
710 * @brief Get the regulator supply output voltage.
711 * @rmtoll VOSCR VOS LL_PWR_GetRegulVoltageScaling
712 * @retval Returned value can be one of the following values:
713 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
714 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
715 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
716 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
717 */
LL_PWR_GetRegulVoltageScaling(void)718 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
719 {
720 return (uint32_t)(READ_BIT(PWR->VOSCR, PWR_VOSCR_VOS));
721 }
722
723 /**
724 * @brief Get currently voltage scaling applied to VCORE.
725 * @rmtoll VOSSR ACTVOS[1:0] LL_PWR_GetCurrentVOS
726 * @retval Returned value can be one of the following values:
727 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
728 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
729 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
730 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
731 */
LL_PWR_GetCurrentVOS(void)732 __STATIC_INLINE uint32_t LL_PWR_GetCurrentVOS(void)
733 {
734 return (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOS));
735 }
736
737 /**
738 * @brief Enable Backup Regulator
739 * @rmtoll BDCR BREN LL_PWR_EnableBkUpRegulator
740 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
741 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
742 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
743 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
744 * the data written into the RAM will be maintained in the Standby and VBAT modes.
745 * @retval None
746 */
LL_PWR_EnableBkUpRegulator(void)747 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
748 {
749 SET_BIT(PWR->BDCR, PWR_BDCR_BREN);
750 }
751
752 /**
753 * @brief Disable Backup Regulator
754 * @rmtoll BDCR BREN LL_PWR_DisableBkUpRegulator
755 * @retval None
756 */
LL_PWR_DisableBkUpRegulator(void)757 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
758 {
759 CLEAR_BIT(PWR->BDCR, PWR_BDCR_BREN);
760 }
761
762 /**
763 * @brief Check if the backup Regulator is enabled
764 * @rmtoll BDCR BREN LL_PWR_IsEnabledBkUpRegulator
765 * @retval State of bit (1 or 0).
766 */
LL_PWR_IsEnabledBkUpRegulator(void)767 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
768 {
769 return ((READ_BIT(PWR->BDCR, PWR_BDCR_BREN) == (PWR_BDCR_BREN)) ? 1UL : 0UL);
770 }
771
772 /**
773 * @brief Enable VBAT and Temperature monitoring
774 * @rmtoll BDCR MONEN LL_PWR_EnableMonitoring
775 * @retval None
776 */
LL_PWR_EnableMonitoring(void)777 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
778 {
779 SET_BIT(PWR->BDCR, PWR_BDCR_MONEN);
780 }
781
782 /**
783 * @brief Disable VBAT and Temperature monitoring
784 * @rmtoll BDCR MONEN LL_PWR_DisableMonitoring
785 * @retval None
786 */
LL_PWR_DisableMonitoring(void)787 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
788 {
789 CLEAR_BIT(PWR->BDCR, PWR_BDCR_MONEN);
790 }
791
792 /**
793 * @brief Check if the VBAT and Temperature monitoring is enabled
794 * @rmtoll BDCR MONEN LL_PWR_IsEnabledMonitoring
795 * @retval State of bit (1 or 0).
796 */
LL_PWR_IsEnabledMonitoring(void)797 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
798 {
799 return ((READ_BIT(PWR->BDCR, PWR_BDCR_MONEN) == (PWR_BDCR_MONEN)) ? 1UL : 0UL);
800 }
801
802 /**
803 * @brief Enable battery charging
804 * @rmtoll BDCR VBE LL_PWR_EnableBatteryCharging
805 * @retval None
806 */
LL_PWR_EnableBatteryCharging(void)807 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
808 {
809 SET_BIT(PWR->BDCR, PWR_BDCR_VBE);
810 }
811
812 /**
813 * @brief Disable battery charging
814 * @rmtoll BDCR VBE LL_PWR_DisableBatteryCharging
815 * @retval None
816 */
LL_PWR_DisableBatteryCharging(void)817 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
818 {
819 CLEAR_BIT(PWR->BDCR, PWR_BDCR_VBE);
820 }
821
822 /**
823 * @brief Check if battery charging is enabled
824 * @rmtoll BDCR VBE LL_PWR_IsEnabledBatteryCharging
825 * @retval State of bit (1 or 0).
826 */
LL_PWR_IsEnabledBatteryCharging(void)827 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
828 {
829 return ((READ_BIT(PWR->BDCR, PWR_BDCR_VBE) == (PWR_BDCR_VBE)) ? 1UL : 0UL);
830 }
831
832 /**
833 * @brief Set the Battery charge resistor impedance
834 * @rmtoll BDCR VBRS LL_PWR_SetBattChargResistor
835 * @param Resistor This parameter can be one of the following values:
836 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
837 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
838 * @retval None
839 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)840 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
841 {
842 MODIFY_REG(PWR->BDCR, PWR_BDCR_VBRS, Resistor);
843 }
844
845 /**
846 * @brief Get the Battery charge resistor impedance
847 * @rmtoll BDCR VBRS LL_PWR_GetBattChargResistor
848 * @retval Returned value can be one of the following values:
849 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
850 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
851 */
LL_PWR_GetBattChargResistor(void)852 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
853 {
854 return (uint32_t)(READ_BIT(PWR->BDCR, PWR_BDCR_VBRS));
855 }
856
857 /**
858 * @brief Enable access to the backup domain
859 * @rmtoll DBPCR DBP LL_PWR_EnableBkUpAccess
860 * @retval None
861 */
LL_PWR_EnableBkUpAccess(void)862 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
863 {
864 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
865 }
866
867 /**
868 * @brief Disable access to the backup domain
869 * @rmtoll DBPCR DBP LL_PWR_DisableBkUpAccess
870 * @retval None
871 */
LL_PWR_DisableBkUpAccess(void)872 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
873 {
874 CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
875 }
876
877 /**
878 * @brief Check if the backup domain is enabled
879 * @rmtoll DBPCR DBP LL_PWR_IsEnabledBkUpAccess
880 * @retval State of bit (1 or 0).
881 */
LL_PWR_IsEnabledBkUpAccess(void)882 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
883 {
884 return ((READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == (PWR_DBPCR_DBP)) ? 1UL : 0UL);
885 }
886
887 #if defined (PWR_UCPDR_UCPD_STBY)
888 /**
889 * @brief Enable the USB type-C and power delivery memorization in Standby
890 * mode.
891 * @note This function must be called just before entering Standby mode.
892 * @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
893 * @retval None
894 */
LL_PWR_EnableUCPDStandbyMode(void)895 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
896 {
897 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY);
898 }
899
900 /**
901 * @brief Disable the USB type-C and power delivery memorization in Standby
902 * mode.
903 * @note This function must be called after exiting Standby mode and before
904 * any UCPD configuration update.
905 * @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
906 * @retval None
907 */
LL_PWR_DisableUCPDStandbyMode(void)908 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
909 {
910 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY);
911 }
912
913 /**
914 * @brief Check if the USB Type-C and Power Delivery Standby mode memorization
915 * is enabled.
916 * @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
917 * @retval State of bit (1 or 0).
918 */
LL_PWR_IsEnabledUCPDStandbyMode(void)919 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
920 {
921 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY) == (PWR_UCPDR_UCPD_STBY)) ? 1UL : 0UL);
922 }
923 #endif /* PWR_UCPDR_UCPD_STBY */
924
925 #if defined (PWR_UCPDR_UCPD_DBDIS)
926 /**
927 * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
928 * on UCPD CC1 and CC2 pins.
929 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
930 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
931 * to disable it in all cases, either to stop this pull-down or to hand over
932 * control to the UCPD (which should therefore be initialized before doing the disable).
933 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
934 * @retval None
935 */
LL_PWR_EnableUCPDDeadBattery(void)936 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
937 {
938 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
939 }
940
941 /**
942 * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
943 * on UCPD CC1 and CC2 pins.
944 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
945 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
946 * to disable it in all cases, either to stop this pull-down or to hand over
947 * control to the UCPD (which should therefore be initialized before doing the disable).
948 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
949 * @retval None
950 */
LL_PWR_DisableUCPDDeadBattery(void)951 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
952 {
953 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
954 }
955
956 /**
957 * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
958 * on UCPD CC1 and CC2 pins.
959 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
960 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
961 * to disable it in all cases, either to stop this pull-down or to hand over
962 * control to the UCPD (which should therefore be initialized before doing the disable).
963 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
964 * @retval State of feature (1 : enabled; 0 : disabled).
965 */
LL_PWR_IsEnabledUCPDDeadBattery(void)966 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
967 {
968 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL);
969 }
970 #endif /* PWR_UCPDR_UCPD_DBDIS */
971
972 /**
973 * @brief Configure the PWR supply
974 * @rmtoll SCCR BYPASS LL_PWR_ConfigSupply
975 * @param SupplySource This parameter can be one of the following values:
976 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
977 * @retval None
978 */
LL_PWR_ConfigSupply(uint32_t SupplySource)979 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
980 {
981 /* Set the power supply configuration */
982 MODIFY_REG(PWR->SCCR, (PWR_SCCR_BYPASS), SupplySource);
983 }
984
985 /**
986 * @brief Get the PWR supply
987 * @rmtoll SCCR BYPASS LL_PWR_GetSupply
988 * @retval The supply configuration.
989 */
LL_PWR_GetSupply(void)990 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
991 {
992 #if defined (PWR_SCCR_SMPSEN)
993 /* Get the power supply configuration */
994 return (uint32_t)(READ_BIT(PWR->SCCR, (PWR_SCCR_SMPSEN | PWR_SCCR_LDOEN | PWR_SCCR_BYPASS)));
995 #else
996 /* Get the power supply configuration */
997 return (uint32_t)(READ_BIT(PWR->SCCR, (PWR_SCCR_LDOEN | PWR_SCCR_BYPASS)));
998 #endif /* PWR_SCCR_SMPSEN */
999 }
1000
1001 /**
1002 * @brief Enable Power Voltage Detector
1003 * @rmtoll VMCR PVDEN LL_PWR_EnablePVD
1004 * @retval None
1005 */
LL_PWR_EnablePVD(void)1006 __STATIC_INLINE void LL_PWR_EnablePVD(void)
1007 {
1008 SET_BIT(PWR->VMCR, PWR_VMCR_PVDEN);
1009 }
1010
1011 /**
1012 * @brief Disable Power Voltage Detector
1013 * @rmtoll VMCR PVDEN LL_PWR_DisablePVD
1014 * @retval None
1015 */
LL_PWR_DisablePVD(void)1016 __STATIC_INLINE void LL_PWR_DisablePVD(void)
1017 {
1018 CLEAR_BIT(PWR->VMCR, PWR_VMCR_PVDEN);
1019 }
1020
1021 /**
1022 * @brief Check if Power Voltage Detector is enabled
1023 * @rmtoll VMCR PVDEN LL_PWR_IsEnabledPVD
1024 * @retval State of bit (1 or 0).
1025 */
LL_PWR_IsEnabledPVD(void)1026 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
1027 {
1028 return ((READ_BIT(PWR->VMCR, PWR_VMCR_PVDEN) == (PWR_VMCR_PVDEN)) ? 1UL : 0UL);
1029 }
1030
1031 /**
1032 * @brief Configure the voltage threshold detected by the Power Voltage Detector
1033 * @rmtoll VMCR PLS LL_PWR_SetPVDLevel
1034 * @param PVDLevel This parameter can be one of the following values:
1035 * @arg @ref LL_PWR_PVDLEVEL_0
1036 * @arg @ref LL_PWR_PVDLEVEL_1
1037 * @arg @ref LL_PWR_PVDLEVEL_2
1038 * @arg @ref LL_PWR_PVDLEVEL_3
1039 * @arg @ref LL_PWR_PVDLEVEL_4
1040 * @arg @ref LL_PWR_PVDLEVEL_5
1041 * @arg @ref LL_PWR_PVDLEVEL_6
1042 * @arg @ref LL_PWR_PVDLEVEL_7
1043 * @retval None
1044 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)1045 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
1046 {
1047 MODIFY_REG(PWR->VMCR, PWR_VMCR_PLS, PVDLevel);
1048 }
1049
1050 /**
1051 * @brief Get the voltage threshold detection
1052 * @rmtoll VMCR PLS LL_PWR_GetPVDLevel
1053 * @retval Returned value can be one of the following values:
1054 * @arg @ref LL_PWR_PVDLEVEL_0
1055 * @arg @ref LL_PWR_PVDLEVEL_1
1056 * @arg @ref LL_PWR_PVDLEVEL_2
1057 * @arg @ref LL_PWR_PVDLEVEL_3
1058 * @arg @ref LL_PWR_PVDLEVEL_4
1059 * @arg @ref LL_PWR_PVDLEVEL_5
1060 * @arg @ref LL_PWR_PVDLEVEL_6
1061 * @arg @ref LL_PWR_PVDLEVEL_7
1062 */
LL_PWR_GetPVDLevel(void)1063 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
1064 {
1065 return (uint32_t)(READ_BIT(PWR->VMCR, PWR_VMCR_PLS));
1066 }
1067
1068
1069 /**
1070 * @brief Enable Analog Power Voltage Detector
1071 * @rmtoll VMCR AVDEN LL_PWR_EnableAVD
1072 * @retval None
1073 */
LL_PWR_EnableAVD(void)1074 __STATIC_INLINE void LL_PWR_EnableAVD(void)
1075 {
1076 SET_BIT(PWR->VMCR, PWR_VMCR_AVDEN);
1077 }
1078
1079 /**
1080 * @brief Disable Analog Power Voltage Detector
1081 * @rmtoll VMCR AVDEN LL_PWR_DisableAVD
1082 * @retval None
1083 */
LL_PWR_DisableAVD(void)1084 __STATIC_INLINE void LL_PWR_DisableAVD(void)
1085 {
1086 CLEAR_BIT(PWR->VMCR, PWR_VMCR_AVDEN);
1087 }
1088
1089 /**
1090 * @brief Check if Analog Power Voltage Detector is enabled
1091 * @rmtoll VMCR AVDEN LL_PWR_IsEnabledAVD
1092 * @retval State of bit (1 or 0).
1093 */
LL_PWR_IsEnabledAVD(void)1094 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
1095 {
1096 return ((READ_BIT(PWR->VMCR, PWR_VMCR_AVDEN) == (PWR_VMCR_AVDEN)) ? 1UL : 0UL);
1097 }
1098
1099 /**
1100 * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector
1101 * @rmtoll VMCR ALS LL_PWR_SetAVDLevel
1102 * @param AVDLevel This parameter can be one of the following values:
1103 * @arg @ref LL_PWR_AVDLEVEL_0
1104 * @arg @ref LL_PWR_AVDLEVEL_1
1105 * @arg @ref LL_PWR_AVDLEVEL_2
1106 * @arg @ref LL_PWR_AVDLEVEL_3
1107 * @retval None
1108 */
LL_PWR_SetAVDLevel(uint32_t AVDLevel)1109 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
1110 {
1111 MODIFY_REG(PWR->VMCR, PWR_VMCR_ALS, AVDLevel);
1112 }
1113
1114 /**
1115 * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
1116 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel
1117 * @retval Returned value can be one of the following values:
1118 * @arg @ref LL_PWR_AVDLEVEL_0
1119 * @arg @ref LL_PWR_AVDLEVEL_1
1120 * @arg @ref LL_PWR_AVDLEVEL_2
1121 * @arg @ref LL_PWR_AVDLEVEL_3
1122 */
LL_PWR_GetAVDLevel(void)1123 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
1124 {
1125 return (uint32_t)(READ_BIT(PWR->VMCR, PWR_VMCR_ALS));
1126 }
1127
1128 #if defined (PWR_USBSCR_USB33DEN)
1129 /**
1130 * @brief Enable the USB voltage detector
1131 * @rmtoll USBSCR USB33DEN LL_PWR_EnableUSBVoltageDetector
1132 * @retval None
1133 */
LL_PWR_EnableUSBVoltageDetector(void)1134 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
1135 {
1136 SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN);
1137 }
1138
1139 /**
1140 * @brief Disable the USB voltage detector
1141 * @rmtoll USBSCR USB33DEN LL_PWR_DisableUSBVoltageDetector
1142 * @retval None
1143 */
LL_PWR_DisableUSBVoltageDetector(void)1144 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
1145 {
1146 CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN);
1147 }
1148
1149 /**
1150 * @brief Check if the USB voltage detector is enabled
1151 * @rmtoll USBSCR USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
1152 * @retval State of bit (1 or 0).
1153 */
LL_PWR_IsEnabledUSBVoltageDetector(void)1154 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
1155 {
1156 return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN) == (PWR_USBSCR_USB33DEN)) ? 1UL : 0UL);
1157 }
1158
1159 /**
1160 * @brief Enable the independent USB supply.
1161 * @rmtoll USBSCR USB33SV LL_PWR_EnableVddUSB
1162 * @retval None
1163 */
LL_PWR_EnableVddUSB(void)1164 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
1165 {
1166 SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV);
1167 }
1168 #define LL_PWR_EnableVDDUSB LL_PWR_EnableVddUSB /* for API backward compatibility */
1169
1170 /**
1171 * @brief Disable the independent USB supply.
1172 * @rmtoll USBSCR USB33SV LL_PWR_DisableVddUSB
1173 * @retval None
1174 */
LL_PWR_DisableVddUSB(void)1175 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
1176 {
1177 CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV);
1178 }
1179 #define LL_PWR_DisableVDDUSB LL_PWR_DisableVddUSB /* for API backward compatibility */
1180
1181 /**
1182 * @brief Check if the independent USB supply is enabled.
1183 * @rmtoll USBSCR USB33SV LL_PWR_IsEnabledVddUSB
1184 * @retval State of bit (1 or 0).
1185 */
LL_PWR_IsEnabledVddUSB(void)1186 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
1187 {
1188 return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV) == (PWR_USBSCR_USB33SV)) ? 1UL : 0UL);
1189 }
1190 #define LL_PWR_IsEnabledVDDUSB LL_PWR_IsEnabledVddUSB /* for API backward compatibility */
1191 #endif /* PWR_USBSCR_USB33DEN */
1192
1193 /**
1194 * @brief Enable the wake up pin_x.
1195 * @rmtoll WUCR WUPENx LL_PWR_EnableWakeUpPin
1196 * @param WakeUpPin This parameter can be a combination of the following values:
1197 * @arg @ref LL_PWR_WAKEUP_PIN1
1198 * @arg @ref LL_PWR_WAKEUP_PIN2
1199 * @arg @ref LL_PWR_WAKEUP_PIN3
1200 * @arg @ref LL_PWR_WAKEUP_PIN4
1201 * @arg @ref LL_PWR_WAKEUP_PIN5
1202 * @arg @ref LL_PWR_WAKEUP_PIN6
1203 * @arg @ref LL_PWR_WAKEUP_PIN7
1204 * @arg @ref LL_PWR_WAKEUP_PIN8
1205 * @retval None
1206 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)1207 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1208 {
1209 SET_BIT(PWR->WUCR, WakeUpPin);
1210 }
1211
1212 /**
1213 * @brief Disable the wake up pin_x.
1214 * @rmtoll WUCR WUPENx LL_PWR_DisableWakeUpPin
1215 * @param WakeUpPin This parameter can be a combination of the following values:
1216 * @arg @ref LL_PWR_WAKEUP_PIN1
1217 * @arg @ref LL_PWR_WAKEUP_PIN2
1218 * @arg @ref LL_PWR_WAKEUP_PIN3
1219 * @arg @ref LL_PWR_WAKEUP_PIN4
1220 * @arg @ref LL_PWR_WAKEUP_PIN5
1221 * @arg @ref LL_PWR_WAKEUP_PIN6
1222 * @arg @ref LL_PWR_WAKEUP_PIN7
1223 * @arg @ref LL_PWR_WAKEUP_PIN8
1224 * @retval None
1225 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1226 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1227 {
1228 CLEAR_BIT(PWR->WUCR, WakeUpPin);
1229 }
1230
1231 /**
1232 * @brief Check if the wake up pin_x is enabled.
1233 * @rmtoll WUCR WUPPx LL_PWR_IsEnabledWakeUpPin
1234 * @param WakeUpPin This parameter can be one of the following values:
1235 * @arg @ref LL_PWR_WAKEUP_PIN1
1236 * @arg @ref LL_PWR_WAKEUP_PIN2
1237 * @arg @ref LL_PWR_WAKEUP_PIN3
1238 * @arg @ref LL_PWR_WAKEUP_PIN4
1239 * @arg @ref LL_PWR_WAKEUP_PIN5
1240 * @arg @ref LL_PWR_WAKEUP_PIN6
1241 * @arg @ref LL_PWR_WAKEUP_PIN7
1242 * @arg @ref LL_PWR_WAKEUP_PIN8
1243 * @retval State of bit (1 or 0).
1244 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1245 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1246 {
1247 return ((READ_BIT(PWR->WUCR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1248 }
1249
1250 /**
1251 * @brief Set the Wake-Up pin polarity low for the event detection
1252 * @rmtoll WUCR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1253 * WUCR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1254 * WUCR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1255 * WUCR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1256 * WUCR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
1257 * WUCR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow\n
1258 * WUCR WKUPP7 LL_PWR_SetWakeUpPinPolarityLow\n
1259 * WUCR WKUPP8 LL_PWR_SetWakeUpPinPolarityLow
1260 * @param WakeUpPin This parameter can be one of the following values:
1261 * @arg @ref LL_PWR_WAKEUP_PIN1
1262 * @arg @ref LL_PWR_WAKEUP_PIN2
1263 * @arg @ref LL_PWR_WAKEUP_PIN3
1264 * @arg @ref LL_PWR_WAKEUP_PIN4
1265 * @arg @ref LL_PWR_WAKEUP_PIN5
1266 * @arg @ref LL_PWR_WAKEUP_PIN6
1267 * @arg @ref LL_PWR_WAKEUP_PIN7
1268 * @arg @ref LL_PWR_WAKEUP_PIN8
1269 * @retval None
1270 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1271 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1272 {
1273 SET_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos));
1274 }
1275
1276 /**
1277 * @brief Set the Wake-Up pin polarity high for the event detection
1278 * @rmtoll WUCR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1279 * WUCR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1280 * WUCR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1281 * WUCR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1282 * WUCR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
1283 * WUCR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh\n
1284 * WUCR WKUPP7 LL_PWR_SetWakeUpPinPolarityHigh\n
1285 * WUCR WKUPP8 LL_PWR_SetWakeUpPinPolarityHigh
1286 * @param WakeUpPin This parameter can be one of the following values:
1287 * @arg @ref LL_PWR_WAKEUP_PIN1
1288 * @arg @ref LL_PWR_WAKEUP_PIN2
1289 * @arg @ref LL_PWR_WAKEUP_PIN3
1290 * @arg @ref LL_PWR_WAKEUP_PIN4
1291 * @arg @ref LL_PWR_WAKEUP_PIN5
1292 * @arg @ref LL_PWR_WAKEUP_PIN6
1293 * @arg @ref LL_PWR_WAKEUP_PIN7
1294 * @arg @ref LL_PWR_WAKEUP_PIN8
1295 * @retval None
1296 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1297 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1298 {
1299 CLEAR_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos));
1300 }
1301
1302 /**
1303 * @brief Get the Wake-Up pin polarity for the event detection
1304 * @rmtoll WUCR WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1305 * WUCR WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1306 * WUCR WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1307 * WUCR WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1308 * WUCR WUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
1309 * WUCR WUPP6 LL_PWR_SetWakeUpPinPolarityLow\n
1310 * WUCR WUPP7 LL_PWR_SetWakeUpPinPolarityLow\n
1311 * WUCR WUPP8 LL_PWR_SetWakeUpPinPolarityLow
1312 * @param WakeUpPin This parameter can be one of the following values:
1313 * @arg @ref LL_PWR_WAKEUP_PIN1
1314 * @arg @ref LL_PWR_WAKEUP_PIN2
1315 * @arg @ref LL_PWR_WAKEUP_PIN3
1316 * @arg @ref LL_PWR_WAKEUP_PIN4
1317 * @arg @ref LL_PWR_WAKEUP_PIN5
1318 * @arg @ref LL_PWR_WAKEUP_PIN6
1319 * @arg @ref LL_PWR_WAKEUP_PIN7
1320 * @arg @ref LL_PWR_WAKEUP_PIN8
1321 * @retval State of bit (1 or 0).
1322 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1323 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1324 {
1325 return ((READ_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos)) == (WakeUpPin << PWR_WUCR_WUPP1_Pos)) ? 1UL : 0UL);
1326 }
1327
1328 /**
1329 * @brief Set the Wake-Up pin Pull None
1330 * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
1331 * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
1332 * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
1333 * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n
1334 * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n
1335 * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullNone\n
1336 * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullNone\n
1337 * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullNone
1338 * @param WakeUpPin This parameter can be one of the following values:
1339 * @arg @ref LL_PWR_WAKEUP_PIN1
1340 * @arg @ref LL_PWR_WAKEUP_PIN2
1341 * @arg @ref LL_PWR_WAKEUP_PIN3
1342 * @arg @ref LL_PWR_WAKEUP_PIN4
1343 * @arg @ref LL_PWR_WAKEUP_PIN5
1344 * @arg @ref LL_PWR_WAKEUP_PIN6
1345 * @arg @ref LL_PWR_WAKEUP_PIN7
1346 * @arg @ref LL_PWR_WAKEUP_PIN8
1347 *
1348 * @retval None
1349 */
LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)1350 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
1351 {
1352 MODIFY_REG(PWR->WUCR,
1353 (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \
1354 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)),
1355 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1356 POSITION_VAL(WakeUpPin)) & 0xFU)) & \
1357 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1358 }
1359
1360 /**
1361 * @brief Set the Wake-Up pin Pull Up
1362 * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
1363 * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
1364 * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
1365 * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n
1366 * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n
1367 * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullUp\n
1368 * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullUp\n
1369 * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullUp
1370 * @param WakeUpPin This parameter can be one of the following values:
1371 * @arg @ref LL_PWR_WAKEUP_PIN1
1372 * @arg @ref LL_PWR_WAKEUP_PIN2
1373 * @arg @ref LL_PWR_WAKEUP_PIN3
1374 * @arg @ref LL_PWR_WAKEUP_PIN4
1375 * @arg @ref LL_PWR_WAKEUP_PIN5
1376 * @arg @ref LL_PWR_WAKEUP_PIN6
1377 * @arg @ref LL_PWR_WAKEUP_PIN7
1378 * @arg @ref LL_PWR_WAKEUP_PIN8
1379 *
1380 *
1381 * @retval None
1382 */
LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)1383 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
1384 {
1385 MODIFY_REG(PWR->WUCR,
1386 (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \
1387 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)),
1388 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1389 POSITION_VAL(WakeUpPin)) & 0xFU)) & \
1390 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1391 }
1392
1393 /**
1394 * @brief Set the Wake-Up pin Pull Down
1395 * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
1396 * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
1397 * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
1398 * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n
1399 * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n
1400 * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullDown\n
1401 * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullDown\n
1402 * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullDown
1403 * @param WakeUpPin This parameter can be one of the following values:
1404 * @arg @ref LL_PWR_WAKEUP_PIN1
1405 * @arg @ref LL_PWR_WAKEUP_PIN2
1406 * @arg @ref LL_PWR_WAKEUP_PIN3
1407 * @arg @ref LL_PWR_WAKEUP_PIN4
1408 * @arg @ref LL_PWR_WAKEUP_PIN5
1409 * @arg @ref LL_PWR_WAKEUP_PIN6
1410 * @arg @ref LL_PWR_WAKEUP_PIN7
1411 * @arg @ref LL_PWR_WAKEUP_PIN8
1412 *
1413 * @retval None
1414 */
LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)1415 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
1416 {
1417 MODIFY_REG(PWR->WUCR,
1418 (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \
1419 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)),
1420 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1421 POSITION_VAL(WakeUpPin)) & 0xFU)) & \
1422 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1423 }
1424
1425 /**
1426 * @brief Get the Wake-Up pin pull
1427 * @rmtoll WUCR WUPPUPD1 LL_PWR_GetWakeUpPinPull\n
1428 * WUCR WUPPUPD2 LL_PWR_GetWakeUpPinPull\n
1429 * WUCR WUPPUPD3 LL_PWR_GetWakeUpPinPull\n
1430 * WUCR WUPPUPD4 LL_PWR_GetWakeUpPinPull\n
1431 * WUCR WUPPUPD5 LL_PWR_GetWakeUpPinPull\n
1432 * WUCR WUPPUPD7 LL_PWR_GetWakeUpPinPull\n
1433 * WUCR WUPPUPD7 LL_PWR_GetWakeUpPinPull\n
1434 * WUCR WUPPUPD8 LL_PWR_GetWakeUpPinPull
1435 * @param WakeUpPin This parameter can be one of the following values:
1436 * @arg @ref LL_PWR_WAKEUP_PIN1
1437 * @arg @ref LL_PWR_WAKEUP_PIN2
1438 * @arg @ref LL_PWR_WAKEUP_PIN3
1439 * @arg @ref LL_PWR_WAKEUP_PIN4
1440 * @arg @ref LL_PWR_WAKEUP_PIN5
1441 * @arg @ref LL_PWR_WAKEUP_PIN6
1442 * @arg @ref LL_PWR_WAKEUP_PIN7
1443 * @arg @ref LL_PWR_WAKEUP_PIN8
1444 *
1445 * @retval Returned value can be one of the following values:
1446 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
1447 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
1448 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
1449 */
LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)1450 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
1451 {
1452 uint32_t regValue = READ_BIT(PWR->WUCR, (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1453 (POSITION_VAL(WakeUpPin) & 0xFU)) & \
1454 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1455
1456 return (uint32_t)(regValue >> ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1457 POSITION_VAL(WakeUpPin)) & 0xFU)) & \
1458 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
1459 }
1460
1461 /**
1462 * @brief Enable IO Retention
1463 * @rmtoll IORETR IORETEN LL_PWR_EnableIORetention
1464 * @retval None
1465 */
LL_PWR_EnableIORetention(void)1466 __STATIC_INLINE void LL_PWR_EnableIORetention(void)
1467 {
1468 SET_BIT(PWR->IORETR, PWR_IORETR_IORETEN);
1469 }
1470
1471 /**
1472 * @brief Disable IO Retention
1473 * @rmtoll IORETR IORETEN LL_PWR_DisableIORetention
1474 * @retval None
1475 */
LL_PWR_DisableIORetention(void)1476 __STATIC_INLINE void LL_PWR_DisableIORetention(void)
1477 {
1478 CLEAR_BIT(PWR->IORETR, PWR_IORETR_IORETEN);
1479 }
1480
1481 /**
1482 * @brief Check if IO Retention is enabled
1483 * @rmtoll IORETR IORETEN LL_PWR_IsEnabledIORetention
1484 * @retval State of bit (1 or 0).
1485 */
LL_PWR_IsEnabledIORetention(void)1486 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIORetention(void)
1487 {
1488 return ((READ_BIT(PWR->IORETR, PWR_IORETR_IORETEN) == (PWR_IORETR_IORETEN)) ? 1UL : 0UL);
1489 }
1490
1491 /**
1492 * @brief Enable JTAGIO Retention
1493 * @rmtoll JTAGIORETR JTAGIORETEN LL_PWR_EnableJTAGIORetention
1494 * @retval None
1495 */
LL_PWR_EnableJTAGIORetention(void)1496 __STATIC_INLINE void LL_PWR_EnableJTAGIORetention(void)
1497 {
1498 SET_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN);
1499 }
1500
1501 /**
1502 * @brief Disable JTAGIO Retention
1503 * @rmtoll JTAGIORETR JTAGIORETEN LL_PWR_DisableJTAGIORetention
1504 * @retval None
1505 */
LL_PWR_DisableJTAGIORetention(void)1506 __STATIC_INLINE void LL_PWR_DisableJTAGIORetention(void)
1507 {
1508 CLEAR_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN);
1509 }
1510
1511 /**
1512 * @brief Check if JTAGIO Retention is enabled
1513 * @rmtoll IORETR JTAGIORETEN LL_PWR_IsEnabledJTAGIORetention
1514 * @retval State of bit (1 or 0).
1515 */
LL_PWR_IsEnabledJTAGIORetention(void)1516 __STATIC_INLINE uint32_t LL_PWR_IsEnabledJTAGIORetention(void)
1517 {
1518 return ((READ_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN) == (PWR_IORETR_JTAGIORETEN)) ? 1UL : 0UL);
1519 }
1520 /**
1521 * @}
1522 */
1523
1524 /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
1525 * @{
1526 */
1527
1528 /**
1529 * @brief Indicate whether the regulator voltage output is above voltage
1530 * scaling range or not.
1531 * @rmtoll VOSSR VOSRDY LL_PWR_IsActiveFlag_VOS
1532 * @retval State of bit (1 or 0).
1533 */
LL_PWR_IsActiveFlag_VOS(void)1534 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1535 {
1536 return ((READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == (PWR_VOSSR_VOSRDY)) ? 1UL : 0UL);
1537 }
1538
1539 /**
1540 * @brief Indicate whether the system was in standby mode or not.
1541 * @rmtoll PMSR SBF LL_PWR_IsActiveFlag_SB
1542 * @retval State of bit (1 or 0).
1543 */
LL_PWR_IsActiveFlag_SB(void)1544 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1545 {
1546 return ((READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == (PWR_PMSR_SBF)) ? 1UL : 0UL);
1547 }
1548
1549 /**
1550 * @brief Indicate whether the system was in stop mode or not.
1551 * @rmtoll PMSR STOPF LL_PWR_IsActiveFlag_STOP
1552 * @retval State of bit (1 or 0).
1553 */
LL_PWR_IsActiveFlag_STOP(void)1554 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
1555 {
1556 return ((READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == (PWR_PMSR_STOPF)) ? 1UL : 0UL);
1557 }
1558
1559 /**
1560 * @brief Indicate whether the VDD voltage is below the threshold or not.
1561 * @rmtoll VMSR PVDO LL_PWR_IsActiveFlag_PVDO
1562 * @retval State of bit (1 or 0).
1563 */
LL_PWR_IsActiveFlag_PVDO(void)1564 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1565 {
1566 return ((READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == (PWR_VMSR_PVDO)) ? 1UL : 0UL);
1567 }
1568
1569 /**
1570 * @brief Indicate whether the VDDA voltage is below the threshold or not.
1571 * @rmtoll VMSR AVDO LL_PWR_IsActiveFlag_AVDO
1572 * @retval State of bit (1 or 0).
1573 */
LL_PWR_IsActiveFlag_AVDO(void)1574 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
1575 {
1576 return ((READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == (PWR_VMSR_AVDO)) ? 1UL : 0UL);
1577 }
1578
1579 /**
1580 * @brief Indicate whether the regulator voltage output is equal to current
1581 * used voltage scaling range or not.
1582 * @rmtoll VOSSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
1583 * @retval State of bit (1 or 0).
1584 */
LL_PWR_IsActiveFlag_ACTVOS(void)1585 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
1586 {
1587 return ((READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == (PWR_VOSSR_ACTVOSRDY)) ? 1UL : 0UL);
1588 }
1589
1590 #if defined (PWR_VMSR_USB33RDY)
1591 /**
1592 * @brief Indicate whether the VDDUSB is below the threshold of monitor or not.
1593 * @rmtoll VMSR USB33RDY LL_PWR_IsActiveFlag_VDDUSB
1594 * @retval State of bit (1 or 0).
1595 */
LL_PWR_IsActiveFlag_VDDUSB(void)1596 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void)
1597 {
1598 return ((READ_BIT(PWR->VMSR, PWR_VMSR_USB33RDY) == (PWR_VMSR_USB33RDY)) ? 1UL : 0UL);
1599 }
1600 #endif /* PWR_VMSR_USB33RDY */
1601
1602 /**
1603 * @brief Indicate whether VDDMMC voltage is below 1V2
1604 * @rmtoll VMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2
1605 * @retval State of bit (1 or 0).
1606 */
LL_PWR_IsActiveFlag_VDDIO2(void)1607 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void)
1608 {
1609 return ((READ_BIT(PWR->VMCR, PWR_VMSR_VDDIO2RDY) == (PWR_VMSR_VDDIO2RDY)) ? 1UL : 0UL);
1610 }
1611
1612 /**
1613 * @brief Get Backup Regulator ready Flag
1614 * @rmtoll BDSR BRRDY LL_PWR_IsActiveFlag_BRR
1615 * @retval State of bit (1 or 0).
1616 */
LL_PWR_IsActiveFlag_BRR(void)1617 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
1618 {
1619 return ((READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == (PWR_BDSR_BRRDY)) ? 1UL : 0UL);
1620 }
1621
1622 /**
1623 * @brief Indicate whether the VBAT level is below high threshold or not.
1624 * @rmtoll BDSR VBATL LL_PWR_IsActiveFlag_VBATL
1625 * @retval State of bit (1 or 0).
1626 */
LL_PWR_IsActiveFlag_VBATL(void)1627 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
1628 {
1629 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == (PWR_BDSR_VBATL)) ? 1UL : 0UL);
1630 }
1631
1632 /**
1633 * @brief Indicate whether the VBAT level is below high threshold or not.
1634 * @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH
1635 * @retval State of bit (1 or 0).
1636 */
LL_PWR_IsActiveFlag_VBATH(void)1637 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
1638 {
1639 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL);
1640 }
1641
1642 /**
1643 * @brief Indicate whether the CPU temperature level is above low threshold or
1644 * not.
1645 * @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL
1646 * @retval State of bit (1 or 0).
1647 */
LL_PWR_IsActiveFlag_TEMPL(void)1648 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
1649 {
1650 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL);
1651 }
1652
1653 /**
1654 * @brief Indicate whether the CPU temperature level is below high threshold
1655 * or not.
1656 * @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH
1657 * @retval State of bit (1 or 0).
1658 */
LL_PWR_IsActiveFlag_TEMPH(void)1659 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
1660 {
1661 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL);
1662 }
1663
1664 /**
1665 * @brief Indicate whether a wakeup event is detected on wake up pin 1.
1666 * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1
1667 * @retval State of bit (1 or 0).
1668 */
LL_PWR_IsActiveFlag_WU1(void)1669 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1670 {
1671 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL);
1672 }
1673
1674 /**
1675 * @brief Indicate whether a wakeup event is detected on wake up pin 2.
1676 * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2
1677 * @retval State of bit (1 or 0).
1678 */
LL_PWR_IsActiveFlag_WU2(void)1679 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1680 {
1681 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL);
1682 }
1683
1684 /**
1685 * @brief Indicate whether a wakeup event is detected on wake up pin 3.
1686 * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3
1687 * @retval State of bit (1 or 0).
1688 */
LL_PWR_IsActiveFlag_WU3(void)1689 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1690 {
1691 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL);
1692 }
1693
1694 /**
1695 * @brief Indicate whether a wakeup event is detected on wake up pin 4.
1696 * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4
1697 * @retval State of bit (1 or 0).
1698 */
LL_PWR_IsActiveFlag_WU4(void)1699 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1700 {
1701 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL);
1702 }
1703
1704 /**
1705 * @brief Indicate whether a wakeup event is detected on wake up pin 5.
1706 * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5
1707 * @retval State of bit (1 or 0).
1708 */
LL_PWR_IsActiveFlag_WU5(void)1709 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1710 {
1711 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL);
1712 }
1713
1714 #if defined (PWR_WUSR_WUF6)
1715 /**
1716 * @brief Indicate whether a wakeup event is detected on wake up pin 6.
1717 * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6
1718 * @retval State of bit (1 or 0).
1719 */
LL_PWR_IsActiveFlag_WU6(void)1720 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
1721 {
1722 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL);
1723 }
1724 #endif /* PWR_WUSR_WUF6 */
1725
1726 #if defined (PWR_WUSR_WUF7)
1727 /**
1728 * @brief Indicate whether a wakeup event is detected on wake up pin 7.
1729 * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7
1730 * @retval State of bit (1 or 0).
1731 */
LL_PWR_IsActiveFlag_WU7(void)1732 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
1733 {
1734 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL);
1735 }
1736 #endif /* PWR_WUSR_WUF7 */
1737
1738 #if defined (PWR_WUSR_WUF8)
1739 /**
1740 * @brief Indicate whether a wakeup event is detected on wake up pin 8.
1741 * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8
1742 * @retval State of bit (1 or 0).
1743 */
LL_PWR_IsActiveFlag_WU8(void)1744 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
1745 {
1746 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL);
1747 }
1748 #endif /* PWR_WUSR_WUF8 */
1749
1750 /**
1751 * @brief Clear stop flag.
1752 * @rmtoll PMCR CSSF LL_PWR_ClearFlag_STOP
1753 * @retval None
1754 */
LL_PWR_ClearFlag_STOP(void)1755 __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void)
1756 {
1757 WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF);
1758 }
1759
1760 /**
1761 * @brief Clear standby flag.
1762 * @rmtoll PMCR CSSF LL_PWR_ClearFlag_SB
1763 * @retval None
1764 */
LL_PWR_ClearFlag_SB(void)1765 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1766 {
1767 WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF);
1768 }
1769
1770 /**
1771 * @brief Clear wake up flag 1.
1772 * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1
1773 * @retval None
1774 */
LL_PWR_ClearFlag_WU1(void)1775 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1776 {
1777 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1);
1778 }
1779
1780 /**
1781 * @brief Clear wake up flag 2.
1782 * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2
1783 * @retval None
1784 */
LL_PWR_ClearFlag_WU2(void)1785 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1786 {
1787 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2);
1788 }
1789
1790 /**
1791 * @brief Clear wake up flag 3.
1792 * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3
1793 * @retval None
1794 */
LL_PWR_ClearFlag_WU3(void)1795 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1796 {
1797 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3);
1798 }
1799
1800 /**
1801 * @brief Clear wake up flag 4.
1802 * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4
1803 * @retval None
1804 */
LL_PWR_ClearFlag_WU4(void)1805 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1806 {
1807 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4);
1808 }
1809
1810 /**
1811 * @brief Clear wake up flag 5.
1812 * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5
1813 * @retval None
1814 */
LL_PWR_ClearFlag_WU5(void)1815 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1816 {
1817 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5);
1818 }
1819
1820 #if defined (PWR_WUSCR_CWUF6)
1821 /**
1822 * @brief Clear wake up flag 6.
1823 * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6
1824 * @retval None
1825 */
LL_PWR_ClearFlag_WU6(void)1826 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
1827 {
1828 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6);
1829 }
1830 #endif /* PWR_WUSCR_CWUF6 */
1831
1832 #if defined (PWR_WUSCR_CWUF7)
1833 /**
1834 * @brief Clear wake up flag 7.
1835 * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7
1836 * @retval None
1837 */
LL_PWR_ClearFlag_WU7(void)1838 __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
1839 {
1840 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7);
1841 }
1842 #endif /* PWR_WUSCR_CWUF7 */
1843
1844 #if defined (PWR_WUSCR_CWUF8)
1845 /**
1846 * @brief Clear wake up flag 8.
1847 * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8
1848 * @retval None
1849 */
LL_PWR_ClearFlag_WU8(void)1850 __STATIC_INLINE void LL_PWR_ClearFlag_WU8(void)
1851 {
1852 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8);
1853 }
1854 #endif /* PWR_WUSCR_CWUF8 */
1855
1856 /**
1857 * @brief Clear all wake up flags.
1858 * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU
1859 * @retval None
1860 */
LL_PWR_ClearFlag_WU(void)1861 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1862 {
1863 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF);
1864 }
1865 /**
1866 * @}
1867 */
1868
1869 /** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
1870 * @{
1871 */
1872
1873 #if defined(PWR_PRIVCFGR_NSPRIV)
1874 /**
1875 * @brief Enable privileged mode for nsecure items.
1876 * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
1877 * @retval None
1878 */
LL_PWR_EnableNSecurePrivilege(void)1879 __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
1880 {
1881 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
1882 }
1883
1884 /**
1885 * @brief Disable privileged mode for nsecure items.
1886 * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
1887 * @retval None
1888 */
LL_PWR_DisableNSecurePrivilege(void)1889 __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
1890 {
1891 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
1892 }
1893
1894 /**
1895 * @brief Check if privileged mode for nsecure items is enabled.
1896 * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
1897 * @retval State of bit (1 or 0).
1898 */
LL_PWR_IsEnabledNSecurePrivilege(void)1899 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
1900 {
1901 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
1902 }
1903 #else
1904 /**
1905 * @brief Enable privileged mode for nsecure items.
1906 * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
1907 * @retval None
1908 */
LL_PWR_EnableNSecurePrivilege(void)1909 __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
1910 {
1911 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
1912 }
1913
1914 /**
1915 * @brief Disable privileged mode for nsecure items.
1916 * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
1917 * @retval None
1918 */
LL_PWR_DisableNSecurePrivilege(void)1919 __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
1920 {
1921 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
1922 }
1923
1924 /**
1925 * @brief Check if privileged mode for nsecure items is enabled.
1926 * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
1927 * @retval State of bit (1 or 0).
1928 */
LL_PWR_IsEnabledNSecurePrivilege(void)1929 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
1930 {
1931 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) == PWR_PRIVCFGR_PRIV) ? 1UL : 0UL);
1932 }
1933 #endif /* RCC_PRIVCFGR_NSPRIV */
1934
1935 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1936 /**
1937 * @brief Enable privileged mode for secure items.
1938 * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege
1939 * @retval None
1940 */
LL_PWR_EnableSecurePrivilege(void)1941 __STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void)
1942 {
1943 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
1944 }
1945
1946 /**
1947 * @brief Disable privileged mode for secure items.
1948 * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege
1949 * @retval None
1950 */
LL_PWR_DisableSecurePrivilege(void)1951 __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void)
1952 {
1953 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
1954 }
1955 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1956
1957 #if defined (PWR_PRIVCFGR_SPRIV)
1958 /**
1959 * @brief Check if privileged mode for secure items is enabled.
1960 * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege
1961 * @retval State of bit (1 or 0).
1962 */
LL_PWR_IsEnabledSecurePrivilege(void)1963 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void)
1964 {
1965 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL);
1966 }
1967 #endif /* PWR_PRIVCFGR_SPRIV */
1968
1969 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1970 /**
1971 * @brief Configure secure attribute mode.
1972 * @note This API can be executed only by CPU in secure mode.
1973 * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
1974 * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
1975 * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
1976 * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
1977 * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
1978 * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n
1979 * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n
1980 * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n
1981 * SECCFGR RETSEC LL_PWR_ConfigSecure\n
1982 * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
1983 * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
1984 * SECCFGR VBSEC LL_PWR_ConfigSecure\n
1985 * SECCFGR APCSEC LL_PWR_ConfigSecure
1986 * @param SecureConfig This parameter can be the full combination
1987 * of the following values:
1988 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1989 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1990 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1991 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1992 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
1993 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
1994 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
1995 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
1996 * @arg @ref LL_PWR_RET_NSEC or LL_PWR_RET_SEC
1997 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
1998 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
1999 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
2000 * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
2001 * @retval None.
2002 */
LL_PWR_ConfigSecure(uint32_t SecureConfig)2003 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
2004 {
2005 WRITE_REG(PWR->SECCFGR, SecureConfig);
2006 }
2007
2008 /**
2009 * @brief Get secure attribute configuration.
2010 * @note This API can be executed only by CPU in secure mode.
2011 * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
2012 * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
2013 * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
2014 * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
2015 * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
2016 * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n
2017 * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n
2018 * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n
2019 * SECCFGR RETSEC LL_PWR_ConfigSecure\n
2020 * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
2021 * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
2022 * SECCFGR VBSEC LL_PWR_GetConfigSecure\n
2023 * SECCFGR APCSEC LL_PWR_GetConfigSecure
2024 * @retval Returned value is the combination of the following values:
2025 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
2026 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
2027 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
2028 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
2029 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
2030 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
2031 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
2032 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
2033 * @arg @ref LL_PWR_RET_NSEC or LL_PWR_RET_SEC
2034 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
2035 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
2036 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
2037 * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
2038 */
LL_PWR_GetConfigSecure(void)2039 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
2040 {
2041 return (READ_REG(PWR->SECCFGR));
2042 }
2043 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2044 /**
2045 * @}
2046 */
2047
2048 #if defined (USE_FULL_LL_DRIVER)
2049 /** @defgroup PWR_LL_EF_Init De-initialization function
2050 * @{
2051 */
2052 ErrorStatus LL_PWR_DeInit(void);
2053 /**
2054 * @}
2055 */
2056 #endif /* defined (USE_FULL_LL_DRIVER) */
2057
2058
2059 /**
2060 * @}
2061 */
2062
2063 /**
2064 * @}
2065 */
2066
2067 #endif /* defined (PWR) */
2068
2069 /**
2070 * @}
2071 */
2072
2073 #ifdef __cplusplus
2074 }
2075 #endif /* __cplusplus */
2076
2077 #endif /* STM32H5xx_LL_PWR_H */
2078
