1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_LL_FMC_H 21 #define STM32H5xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FMC_BANK1) 42 43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FMC_NORSRAM_BANK4)) 47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 59 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 60 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 61 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 62 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 63 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 64 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 65 ((__MODE__) == FMC_ACCESS_MODE_D)) 66 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 67 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 68 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 69 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 70 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 71 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 72 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 73 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 74 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 75 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 76 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 77 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 78 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 79 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 80 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 81 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 82 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 83 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 84 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 85 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 86 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 87 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 88 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 89 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 90 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 91 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 92 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 93 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 94 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 95 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 96 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 97 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 98 99 #endif /* FMC_BANK1 */ 100 #if defined(FMC_BANK3) 101 102 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 103 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 104 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 105 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 106 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 107 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 108 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 109 110 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 111 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 112 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 113 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 114 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 115 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 116 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 117 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 118 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 119 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 120 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 121 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 122 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 123 124 #endif /* FMC_BANK3 */ 125 #if defined(FMC_Bank5_6_R) 126 127 #define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ 128 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16)) 129 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ 130 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) 131 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ 132 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ 133 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) 134 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ 135 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) 136 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ 137 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ 138 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) 139 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ 140 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ 141 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ 142 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ 143 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ 144 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ 145 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) 146 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ 147 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ 148 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 149 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 150 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 151 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 152 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 153 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) 154 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 155 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) 156 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) 157 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) 158 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) 159 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) 160 #define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ 161 ((__BANK__) == FMC_SDRAM_BANK2)) 162 #define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ 163 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ 164 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ 165 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) 166 #define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ 167 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ 168 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) 169 #define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ 170 ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) 171 #define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ 172 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ 173 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) 174 175 #endif /* FMC_Bank5_6_R */ 176 177 /** 178 * @} 179 */ 180 181 /* Exported typedef ----------------------------------------------------------*/ 182 183 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 184 * @{ 185 */ 186 187 #if defined(FMC_BANK1) 188 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 189 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 190 #endif /* FMC_BANK1 */ 191 #if defined(FMC_BANK3) 192 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 193 #endif /* FMC_BANK3 */ 194 #if defined(FMC_Bank5_6_R) 195 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef 196 #endif /* FMC_Bank5_6_R */ 197 198 #if defined(FMC_BANK1) 199 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 200 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 201 #endif /* FMC_BANK1 */ 202 #if defined(FMC_BANK3) 203 #define FMC_NAND_DEVICE FMC_Bank3_R 204 #endif /* FMC_BANK3 */ 205 #if defined(FMC_Bank5_6_R) 206 #define FMC_SDRAM_DEVICE FMC_Bank5_6_R 207 #endif /* FMC_Bank5_6_R */ 208 209 #if defined(FMC_BANK1) 210 /** 211 * @brief FMC NORSRAM Configuration Structure definition 212 */ 213 typedef struct 214 { 215 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 216 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 217 218 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 219 multiplexed on the data bus or not. 220 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ 221 222 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 223 the corresponding memory device. 224 This parameter can be a value of @ref FMC_Memory_Type */ 225 226 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 227 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 228 229 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 230 valid only with synchronous burst Flash memories. 231 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 232 233 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 234 the Flash memory in burst mode. 235 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 236 237 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 238 clock cycle before the wait state or during the wait state, 239 valid only when accessing memories in burst mode. 240 This parameter can be a value of @ref FMC_Wait_Timing */ 241 242 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device 243 by the FMC. 244 This parameter can be a value of @ref FMC_Write_Operation */ 245 246 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 247 signal, valid for Flash memory access in burst mode. 248 This parameter can be a value of @ref FMC_Wait_Signal */ 249 250 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 251 This parameter can be a value of @ref FMC_Extended_Mode */ 252 253 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 254 valid only with asynchronous Flash memories. 255 This parameter can be a value of @ref FMC_AsynchronousWait */ 256 257 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 258 This parameter can be a value of @ref FMC_Write_Burst */ 259 260 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 261 This parameter is only enabled through the FMC_BCR1 register, 262 and don't care through FMC_BCR2..4 registers. 263 This parameter can be a value of @ref FMC_Continous_Clock */ 264 265 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 266 This parameter is only enabled through the FMC_BCR1 register, 267 and don't care through FMC_BCR2..4 registers. 268 This parameter can be a value of @ref FMC_Write_FIFO */ 269 270 uint32_t PageSize; /*!< Specifies the memory page size. 271 This parameter can be a value of @ref FMC_Page_Size */ 272 273 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 274 This parameter can be a value of @ref FMC_Byte_Lane */ 275 276 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this 277 NSBank for PSRAM refresh. 278 This parameter can be set to ENABLE or DISABLE */ 279 280 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for 281 synchronous accesses and in HCLK cycles for asynchronous accesses, 282 valid only if MaxChipSelectPulse is ENABLE. 283 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 284 @note: This parameter is common to all NSBank. */ 285 } FMC_NORSRAM_InitTypeDef; 286 287 /** 288 * @brief FMC NORSRAM Timing parameters structure definition 289 */ 290 typedef struct 291 { 292 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 293 the duration of the address setup time. 294 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 295 @note This parameter is not used with synchronous NOR Flash memories. */ 296 297 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 298 the duration of the address hold time. 299 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 300 @note This parameter is not used with synchronous NOR Flash memories. */ 301 302 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 303 the duration of the data setup time. 304 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 305 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 306 NOR Flash memories. */ 307 308 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 309 the duration of the data hold time. 310 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 311 @note This parameter is used for used in asynchronous accesses. */ 312 313 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 314 the duration of the bus turnaround. 315 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 316 @note This parameter is only used for multiplexed NOR Flash memories. */ 317 318 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 319 HCLK cycles. This parameter can be a value between Min_Data = 2 and 320 Max_Data = 16. 321 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 322 accesses. */ 323 324 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 325 to the memory before getting the first data. 326 The parameter value depends on the memory type as shown below: 327 - It must be set to 0 in case of a CRAM 328 - It is don't care in asynchronous NOR, SRAM or ROM accesses 329 - It may assume a value between Min_Data = 2 and Max_Data = 17 330 in NOR Flash memories with synchronous burst mode enable */ 331 332 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 333 This parameter can be a value of @ref FMC_Access_Mode */ 334 } FMC_NORSRAM_TimingTypeDef; 335 #endif /* FMC_BANK1 */ 336 337 #if defined(FMC_BANK3) 338 /** 339 * @brief FMC NAND Configuration Structure definition 340 */ 341 typedef struct 342 { 343 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 344 This parameter can be a value of @ref FMC_NAND_Bank */ 345 346 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 347 This parameter can be any value of @ref FMC_Wait_feature */ 348 349 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 350 This parameter can be any value of @ref FMC_NAND_Data_Width */ 351 352 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 353 This parameter can be any value of @ref FMC_ECC */ 354 355 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 356 This parameter can be any value of @ref FMC_ECC_Page_Size */ 357 358 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 359 delay between CLE low and RE low. 360 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 361 362 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 363 delay between ALE low and RE low. 364 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 365 } FMC_NAND_InitTypeDef; 366 #endif /* FMC_BANK3 */ 367 368 #if defined(FMC_BANK3) 369 /** 370 * @brief FMC NAND Timing parameters structure definition 371 */ 372 typedef struct 373 { 374 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 375 the command assertion for NAND-Flash read or write access 376 to common/Attribute or I/O memory space (depending on 377 the memory space timing to be configured). 378 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 379 380 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 381 command for NAND-Flash read or write access to 382 common/Attribute or I/O memory space (depending on the 383 memory space timing to be configured). 384 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 385 386 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 387 (and data for write access) after the command de-assertion 388 for NAND-Flash read or write access to common/Attribute 389 or I/O memory space (depending on the memory space timing 390 to be configured). 391 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 392 393 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 394 data bus is kept in HiZ after the start of a NAND-Flash 395 write access to common/Attribute or I/O memory space (depending 396 on the memory space timing to be configured). 397 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 398 } FMC_NAND_PCC_TimingTypeDef; 399 #endif /* FMC_BANK3 */ 400 401 402 #if defined(FMC_Bank5_6_R) 403 /** 404 * @brief FMC SDRAM Configuration Structure definition 405 */ 406 typedef struct 407 { 408 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. 409 This parameter can be a value of @ref FMC_SDRAM_Bank */ 410 411 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. 412 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ 413 414 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. 415 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ 416 417 uint32_t MemoryDataWidth; /*!< Defines the memory device width. 418 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ 419 420 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. 421 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ 422 423 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. 424 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ 425 426 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. 427 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ 428 429 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow 430 to disable the clock before changing frequency. 431 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ 432 433 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read 434 commands during the CAS latency and stores data in the Read FIFO. 435 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ 436 437 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. 438 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ 439 } FMC_SDRAM_InitTypeDef; 440 441 /** 442 * @brief FMC SDRAM Timing parameters structure definition 443 */ 444 typedef struct 445 { 446 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and 447 an active or Refresh command in number of memory clock cycles. 448 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 449 450 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to 451 issuing the Activate command in number of memory clock cycles. 452 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 453 454 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock 455 cycles. 456 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 457 458 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command 459 and the delay between two consecutive Refresh commands in number of 460 memory clock cycles. 461 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 462 463 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. 464 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 465 466 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command 467 in number of memory clock cycles. 468 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 469 470 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write 471 command in number of memory clock cycles. 472 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 473 } FMC_SDRAM_TimingTypeDef; 474 475 /** 476 * @brief SDRAM command parameters structure definition 477 */ 478 typedef struct 479 { 480 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. 481 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ 482 483 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. 484 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ 485 486 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued 487 in auto refresh mode. 488 This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ 489 490 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ 491 } FMC_SDRAM_CommandTypeDef; 492 #endif /* FMC_Bank5_6_R */ 493 /** 494 * @} 495 */ 496 497 /* Exported constants --------------------------------------------------------*/ 498 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 499 * @{ 500 */ 501 #if defined(FMC_BANK1) 502 503 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 504 * @{ 505 */ 506 507 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 508 * @{ 509 */ 510 #define FMC_NORSRAM_BANK1 (0x00000000U) 511 #define FMC_NORSRAM_BANK2 (0x00000002U) 512 #define FMC_NORSRAM_BANK3 (0x00000004U) 513 #define FMC_NORSRAM_BANK4 (0x00000006U) 514 /** 515 * @} 516 */ 517 518 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 519 * @{ 520 */ 521 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 522 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 523 /** 524 * @} 525 */ 526 527 /** @defgroup FMC_Memory_Type FMC Memory Type 528 * @{ 529 */ 530 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 531 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 532 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 533 /** 534 * @} 535 */ 536 537 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 538 * @{ 539 */ 540 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 541 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 542 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 543 /** 544 * @} 545 */ 546 547 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 548 * @{ 549 */ 550 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 551 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 552 /** 553 * @} 554 */ 555 556 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 557 * @{ 558 */ 559 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 560 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 561 /** 562 * @} 563 */ 564 565 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 566 * @{ 567 */ 568 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 569 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 570 /** 571 * @} 572 */ 573 574 /** @defgroup FMC_Wait_Timing FMC Wait Timing 575 * @{ 576 */ 577 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 578 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 579 /** 580 * @} 581 */ 582 583 /** @defgroup FMC_Write_Operation FMC Write Operation 584 * @{ 585 */ 586 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 587 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 588 /** 589 * @} 590 */ 591 592 /** @defgroup FMC_Wait_Signal FMC Wait Signal 593 * @{ 594 */ 595 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 596 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 597 /** 598 * @} 599 */ 600 601 /** @defgroup FMC_Extended_Mode FMC Extended Mode 602 * @{ 603 */ 604 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 605 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 606 /** 607 * @} 608 */ 609 610 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 611 * @{ 612 */ 613 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 614 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 615 /** 616 * @} 617 */ 618 619 /** @defgroup FMC_Page_Size FMC Page Size 620 * @{ 621 */ 622 #define FMC_PAGE_SIZE_NONE (0x00000000U) 623 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 624 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 625 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 626 | FMC_BCRx_CPSIZE_1) 627 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 628 /** 629 * @} 630 */ 631 632 /** @defgroup FMC_Write_Burst FMC Write Burst 633 * @{ 634 */ 635 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 636 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 637 /** 638 * @} 639 */ 640 641 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 642 * @{ 643 */ 644 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 645 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 646 /** 647 * @} 648 */ 649 650 #if defined(FMC_BCR1_WFDIS) 651 /** @defgroup FMC_Write_FIFO FMC Write FIFO 652 * @{ 653 */ 654 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 655 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 656 #endif /* FMC_BCR1_WFDIS */ 657 /** 658 * @} 659 */ 660 661 /** @defgroup FMC_Access_Mode FMC Access Mode 662 * @{ 663 */ 664 #define FMC_ACCESS_MODE_A (0x00000000U) 665 #define FMC_ACCESS_MODE_B (0x10000000U) 666 #define FMC_ACCESS_MODE_C (0x20000000U) 667 #define FMC_ACCESS_MODE_D (0x30000000U) 668 /** 669 * @} 670 */ 671 672 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 673 * @{ 674 */ 675 #define FMC_NBL_SETUPTIME_0 (0x00000000U) 676 #define FMC_NBL_SETUPTIME_1 (0x00400000U) 677 #define FMC_NBL_SETUPTIME_2 (0x00800000U) 678 #define FMC_NBL_SETUPTIME_3 (0x00C00000U) 679 /** 680 * @} 681 */ 682 683 /** 684 * @} 685 */ 686 #endif /* FMC_BANK1 */ 687 688 #if defined(FMC_BANK3) 689 690 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 691 * @{ 692 */ 693 /** @defgroup FMC_NAND_Bank FMC NAND Bank 694 * @{ 695 */ 696 #define FMC_NAND_BANK3 (0x00000100U) 697 /** 698 * @} 699 */ 700 701 /** @defgroup FMC_Wait_feature FMC Wait feature 702 * @{ 703 */ 704 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 705 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 706 /** 707 * @} 708 */ 709 710 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 711 * @{ 712 */ 713 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 714 /** 715 * @} 716 */ 717 718 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 719 * @{ 720 */ 721 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 722 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 723 /** 724 * @} 725 */ 726 727 /** @defgroup FMC_ECC FMC ECC 728 * @{ 729 */ 730 #define FMC_NAND_ECC_DISABLE (0x00000000U) 731 #define FMC_NAND_ECC_ENABLE (0x00000040U) 732 /** 733 * @} 734 */ 735 736 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 737 * @{ 738 */ 739 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 740 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 741 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 742 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 743 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 744 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 745 /** 746 * @} 747 */ 748 749 /** 750 * @} 751 */ 752 #endif /* FMC_BANK3 */ 753 754 #if defined(FMC_Bank5_6_R) 755 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller 756 * @{ 757 */ 758 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank 759 * @{ 760 */ 761 #define FMC_SDRAM_BANK1 (0x00000000U) 762 #define FMC_SDRAM_BANK2 (0x00000001U) 763 /** 764 * @} 765 */ 766 767 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number 768 * @{ 769 */ 770 #define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) 771 #define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) 772 #define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) 773 #define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) 774 /** 775 * @} 776 */ 777 778 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number 779 * @{ 780 */ 781 #define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) 782 #define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) 783 #define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) 784 /** 785 * @} 786 */ 787 788 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width 789 * @{ 790 */ 791 #define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) 792 #define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) 793 /** 794 * @} 795 */ 796 797 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number 798 * @{ 799 */ 800 #define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) 801 #define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) 802 /** 803 * @} 804 */ 805 806 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency 807 * @{ 808 */ 809 #define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) 810 #define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) 811 #define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) 812 /** 813 * @} 814 */ 815 816 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection 817 * @{ 818 */ 819 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) 820 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) 821 /** 822 * @} 823 */ 824 825 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period 826 * @{ 827 */ 828 #define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) 829 #define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) 830 #define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) 831 /** 832 * @} 833 */ 834 835 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst 836 * @{ 837 */ 838 #define FMC_SDRAM_RBURST_DISABLE (0x00000000U) 839 #define FMC_SDRAM_RBURST_ENABLE (0x00001000U) 840 /** 841 * @} 842 */ 843 844 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay 845 * @{ 846 */ 847 #define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) 848 #define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) 849 #define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) 850 /** 851 * @} 852 */ 853 854 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode 855 * @{ 856 */ 857 #define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) 858 #define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) 859 #define FMC_SDRAM_CMD_PALL (0x00000002U) 860 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) 861 #define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) 862 #define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) 863 #define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) 864 /** 865 * @} 866 */ 867 868 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target 869 * @{ 870 */ 871 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 872 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 873 #define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) 874 /** 875 * @} 876 */ 877 878 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status 879 * @{ 880 */ 881 #define FMC_SDRAM_NORMAL_MODE (0x00000000U) 882 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 883 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 884 /** 885 * @} 886 */ 887 888 /** 889 * @} 890 */ 891 892 #endif /* FMC_Bank5_6_R */ 893 894 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 895 * @{ 896 */ 897 #if defined(FMC_BANK3) 898 #define FMC_IT_RISING_EDGE (0x00000008U) 899 #define FMC_IT_LEVEL (0x00000010U) 900 #define FMC_IT_FALLING_EDGE (0x00000020U) 901 #endif /* FMC_BANK3 */ 902 #if defined(FMC_Bank5_6_R) 903 #define FMC_IT_REFRESH_ERROR (0x00004000U) 904 #endif /* FMC_Bank5_6_R */ 905 /** 906 * @} 907 */ 908 909 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 910 * @{ 911 */ 912 #if defined(FMC_BANK3) 913 #define FMC_FLAG_RISING_EDGE (0x00000001U) 914 #define FMC_FLAG_LEVEL (0x00000002U) 915 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 916 #define FMC_FLAG_FEMPT (0x00000040U) 917 #endif /* FMC_BANK3 */ 918 #if defined(FMC_Bank5_6_R) 919 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE 920 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY 921 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE 922 #endif /* FMC_Bank5_6_R */ 923 /** 924 * @} 925 */ 926 927 /** 928 * @} 929 */ 930 931 /** 932 * @} 933 */ 934 935 /* Private macro -------------------------------------------------------------*/ 936 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 937 * @{ 938 */ 939 /** 940 * @brief Enable the FMC Peripheral. 941 * @retval None 942 */ 943 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN) 944 945 /** 946 * @brief Disable the FMC Peripheral. 947 * @retval None 948 */ 949 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) 950 #if defined(FMC_BANK1) 951 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 952 * @brief macros to handle NOR device enable/disable and read/write operations 953 * @{ 954 */ 955 956 /** 957 * @brief Enable the NORSRAM device access. 958 * @param __INSTANCE__ FMC_NORSRAM Instance 959 * @param __BANK__ FMC_NORSRAM Bank 960 * @retval None 961 */ 962 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 963 |= FMC_BCRx_MBKEN) 964 965 /** 966 * @brief Disable the NORSRAM device access. 967 * @param __INSTANCE__ FMC_NORSRAM Instance 968 * @param __BANK__ FMC_NORSRAM Bank 969 * @retval None 970 */ 971 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 972 &= ~FMC_BCRx_MBKEN) 973 974 /** 975 * @} 976 */ 977 #endif /* FMC_BANK1 */ 978 979 #if defined(FMC_BANK3) 980 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 981 * @brief macros to handle NAND device enable/disable 982 * @{ 983 */ 984 985 /** 986 * @brief Enable the NAND device access. 987 * @param __INSTANCE__ FMC_NAND Instance 988 * @retval None 989 */ 990 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 991 992 /** 993 * @brief Disable the NAND device access. 994 * @param __INSTANCE__ FMC_NAND Instance 995 * @param __BANK__ FMC_NAND Bank 996 * @retval None 997 */ 998 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 999 1000 /** 1001 * @} 1002 */ 1003 #endif /* FMC_BANK3 */ 1004 1005 #if defined(FMC_BANK3) 1006 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 1007 * @brief macros to handle NAND interrupts 1008 * @{ 1009 */ 1010 1011 /** 1012 * @brief Enable the NAND device interrupt. 1013 * @param __INSTANCE__ FMC_NAND instance 1014 * @param __INTERRUPT__ FMC_NAND interrupt 1015 * This parameter can be any combination of the following values: 1016 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 1017 * @arg FMC_IT_LEVEL: Interrupt level. 1018 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 1019 * @retval None 1020 */ 1021 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 1022 1023 /** 1024 * @brief Disable the NAND device interrupt. 1025 * @param __INSTANCE__ FMC_NAND Instance 1026 * @param __INTERRUPT__ FMC_NAND interrupt 1027 * This parameter can be any combination of the following values: 1028 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 1029 * @arg FMC_IT_LEVEL: Interrupt level. 1030 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 1031 * @retval None 1032 */ 1033 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 1034 1035 /** 1036 * @brief Get flag status of the NAND device. 1037 * @param __INSTANCE__ FMC_NAND Instance 1038 * @param __BANK__ FMC_NAND Bank 1039 * @param __FLAG__ FMC_NAND flag 1040 * This parameter can be any combination of the following values: 1041 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1042 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1043 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1044 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1045 * @retval The state of FLAG (SET or RESET). 1046 */ 1047 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 1048 1049 /** 1050 * @brief Clear flag status of the NAND device. 1051 * @param __INSTANCE__ FMC_NAND Instance 1052 * @param __FLAG__ FMC_NAND flag 1053 * This parameter can be any combination of the following values: 1054 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1055 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1056 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1057 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1058 * @retval None 1059 */ 1060 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 1061 1062 /** 1063 * @} 1064 */ 1065 #endif /* FMC_BANK3 */ 1066 1067 1068 #if defined(FMC_Bank5_6_R) 1069 /** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt 1070 * @brief macros to handle SDRAM interrupts 1071 * @{ 1072 */ 1073 1074 /** 1075 * @brief Enable the SDRAM device interrupt. 1076 * @param __INSTANCE__ FMC_SDRAM instance 1077 * @param __INTERRUPT__ FMC_SDRAM interrupt 1078 * This parameter can be any combination of the following values: 1079 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1080 * @retval None 1081 */ 1082 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) 1083 1084 /** 1085 * @brief Disable the SDRAM device interrupt. 1086 * @param __INSTANCE__ FMC_SDRAM instance 1087 * @param __INTERRUPT__ FMC_SDRAM interrupt 1088 * This parameter can be any combination of the following values: 1089 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1090 * @retval None 1091 */ 1092 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) 1093 1094 /** 1095 * @brief Get flag status of the SDRAM device. 1096 * @param __INSTANCE__ FMC_SDRAM instance 1097 * @param __FLAG__ FMC_SDRAM flag 1098 * This parameter can be any combination of the following values: 1099 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. 1100 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. 1101 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. 1102 * @retval The state of FLAG (SET or RESET). 1103 */ 1104 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) 1105 1106 /** 1107 * @brief Clear flag status of the SDRAM device. 1108 * @param __INSTANCE__ FMC_SDRAM instance 1109 * @param __FLAG__ FMC_SDRAM flag 1110 * This parameter can be any combination of the following values: 1111 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR 1112 * @retval None 1113 */ 1114 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) 1115 1116 /** 1117 * @} 1118 */ 1119 #endif /* FMC_Bank5_6_R */ 1120 /** 1121 * @} 1122 */ 1123 1124 /** 1125 * @} 1126 */ 1127 1128 /* Private functions ---------------------------------------------------------*/ 1129 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 1130 * @{ 1131 */ 1132 1133 #if defined(FMC_BANK1) 1134 /** @defgroup FMC_LL_NORSRAM NOR SRAM 1135 * @{ 1136 */ 1137 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 1138 * @{ 1139 */ 1140 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 1141 const FMC_NORSRAM_InitTypeDef *Init); 1142 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 1143 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 1144 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 1145 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 1146 uint32_t ExtendedMode); 1147 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 1148 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 1149 /** 1150 * @} 1151 */ 1152 1153 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 1154 * @{ 1155 */ 1156 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1157 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1158 /** 1159 * @} 1160 */ 1161 /** 1162 * @} 1163 */ 1164 #endif /* FMC_BANK1 */ 1165 1166 #if defined(FMC_BANK3) 1167 /** @defgroup FMC_LL_NAND NAND 1168 * @{ 1169 */ 1170 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 1171 * @{ 1172 */ 1173 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); 1174 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1175 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1176 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 1177 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1178 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 1179 /** 1180 * @} 1181 */ 1182 1183 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 1184 * @{ 1185 */ 1186 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1187 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1188 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 1189 uint32_t Timeout); 1190 /** 1191 * @} 1192 */ 1193 /** 1194 * @} 1195 */ 1196 #endif /* FMC_BANK3 */ 1197 1198 1199 #if defined(FMC_Bank5_6_R) 1200 /** @defgroup FMC_LL_SDRAM SDRAM 1201 * @{ 1202 */ 1203 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions 1204 * @{ 1205 */ 1206 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init); 1207 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, 1208 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); 1209 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1210 /** 1211 * @} 1212 */ 1213 1214 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions 1215 * @{ 1216 */ 1217 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1218 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1219 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, 1220 const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); 1221 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); 1222 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, 1223 uint32_t AutoRefreshNumber); 1224 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1225 /** 1226 * @} 1227 */ 1228 /** 1229 * @} 1230 */ 1231 #endif /* FMC_Bank5_6_R */ 1232 1233 /** 1234 * @} 1235 */ 1236 1237 /** 1238 * @} 1239 */ 1240 1241 /** 1242 * @} 1243 */ 1244 1245 #ifdef __cplusplus 1246 } 1247 #endif 1248 1249 #endif /* STM32H5xx_LL_FMC_H */ 1250
