1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2022 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND memory controller
31 (+) The Synchronous DRAM (SDRAM) controller
32
33 [..] The FMC functional block makes the interface with synchronous and asynchronous static
34 memories and SDRAM memories. Its main purposes are:
35 (+) to translate AHB transactions into the appropriate external device protocol
36 (+) to meet the access time requirements of the external memory devices
37
38 [..] All external memories share the addresses, data and control signals with the controller.
39 Each external device is accessed by means of a unique Chip Select. The FMC performs
40 only one access at a time to an external device.
41 The main features of the FMC controller are the following:
42 (+) Interface with static-memory mapped devices including:
43 (++) Static random access memory (SRAM)
44 (++) Read-only memory (ROM)
45 (++) NOR Flash memory/OneNAND Flash memory
46 (++) PSRAM (4 memory banks)
47 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48 data
49 (+) Interface with synchronous DRAM (SDRAM) memories
50 (+) Independent Chip Select control for each memory bank
51 (+) Independent configuration for each memory bank
52
53 @endverbatim
54 ******************************************************************************
55 */
56
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32h5xx_hal.h"
59
60 /** @addtogroup STM32H5xx_HAL_Driver
61 * @{
62 */
63 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
64 || defined(HAL_SRAM_MODULE_ENABLED)
65
66 /** @defgroup FMC_LL FMC Low Layer
67 * @brief FMC driver modules
68 * @{
69 */
70
71 /* Private typedef -----------------------------------------------------------*/
72 /* Private define ------------------------------------------------------------*/
73
74 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
75 * @{
76 */
77
78 /* ----------------------- FMC registers bit mask --------------------------- */
79
80 /* --- BCR Register ---*/
81 /* BCR register clear mask */
82
83 /* --- BTR Register ---*/
84 /* BTR register clear mask */
85 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
86 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
87 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
88 FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD))
89
90 /* --- BWTR Register ---*/
91 /* BWTR register clear mask */
92 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
93 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
94 FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
95
96 /* --- PCR Register ---*/
97 /* PCR register clear mask */
98 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
99 FMC_PCR_PTYP | FMC_PCR_PWID | \
100 FMC_PCR_ECCEN | FMC_PCR_TCLR | \
101 FMC_PCR_TAR | FMC_PCR_ECCPS))
102 /* --- PMEM Register ---*/
103 /* PMEM register clear mask */
104 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
105 FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
106
107 /* --- PATT Register ---*/
108 /* PATT register clear mask */
109 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
110 FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
111
112
113 /* --- SDCR Register ---*/
114 /* SDCR register clear mask */
115 #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCRx_NC | FMC_SDCRx_NR | \
116 FMC_SDCRx_MWID | FMC_SDCRx_NB | \
117 FMC_SDCRx_CAS | FMC_SDCRx_WP | \
118 FMC_SDCRx_SDCLK | FMC_SDCRx_RBURST | \
119 FMC_SDCRx_RPIPE))
120
121 /* --- SDTR Register ---*/
122 /* SDTR register clear mask */
123 #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTRx_TMRD | FMC_SDTRx_TXSR | \
124 FMC_SDTRx_TRAS | FMC_SDTRx_TRC | \
125 FMC_SDTRx_TWR | FMC_SDTRx_TRP | \
126 FMC_SDTRx_TRCD))
127
128 /**
129 * @}
130 */
131
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135 /* Exported functions --------------------------------------------------------*/
136
137 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
138 * @{
139 */
140
141
142 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
143 * @brief NORSRAM Controller functions
144 *
145 @verbatim
146 ==============================================================================
147 ##### How to use NORSRAM device driver #####
148 ==============================================================================
149
150 [..]
151 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
152 to run the NORSRAM external devices.
153
154 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
155 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
156 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
157 (+) FMC NORSRAM bank extended timing configuration using the function
158 FMC_NORSRAM_Extended_Timing_Init()
159 (+) FMC NORSRAM bank enable/disable write operation using the functions
160 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
161
162 @endverbatim
163 * @{
164 */
165
166 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
167 * @brief Initialization and Configuration functions
168 *
169 @verbatim
170 ==============================================================================
171 ##### Initialization and de_initialization functions #####
172 ==============================================================================
173 [..]
174 This section provides functions allowing to:
175 (+) Initialize and configure the FMC NORSRAM interface
176 (+) De-initialize the FMC NORSRAM interface
177 (+) Configure the FMC clock and associated GPIOs
178
179 @endverbatim
180 * @{
181 */
182
183 /**
184 * @brief Initialize the FMC_NORSRAM device according to the specified
185 * control parameters in the FMC_NORSRAM_InitTypeDef
186 * @param Device Pointer to NORSRAM device instance
187 * @param Init Pointer to NORSRAM Initialization structure
188 * @retval HAL status
189 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_InitTypeDef * Init)190 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
191 FMC_NORSRAM_InitTypeDef *Init)
192 {
193 uint32_t flashaccess;
194 uint32_t btcr_reg;
195 uint32_t mask;
196
197 /* Check the parameters */
198 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
199 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
200 assert_param(IS_FMC_MUX(Init->DataAddressMux));
201 assert_param(IS_FMC_MEMORY(Init->MemoryType));
202 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
203 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
204 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
205 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
206 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
207 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
208 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
209 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
210 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
211 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
212 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
213 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
214 assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
215 assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse));
216
217 /* Disable NORSRAM Device */
218 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
219
220 /* Set NORSRAM device control parameters */
221 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
222 {
223 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
224 }
225 else
226 {
227 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
228 }
229
230 btcr_reg = (flashaccess | \
231 Init->DataAddressMux | \
232 Init->MemoryType | \
233 Init->MemoryDataWidth | \
234 Init->BurstAccessMode | \
235 Init->WaitSignalPolarity | \
236 Init->WaitSignalActive | \
237 Init->WriteOperation | \
238 Init->WaitSignal | \
239 Init->ExtendedMode | \
240 Init->AsynchronousWait | \
241 Init->WriteBurst);
242
243 btcr_reg |= Init->ContinuousClock;
244 btcr_reg |= Init->WriteFifo;
245 btcr_reg |= Init->NBLSetupTime;
246 btcr_reg |= Init->PageSize;
247
248 mask = (FMC_BCRx_MBKEN |
249 FMC_BCRx_MUXEN |
250 FMC_BCRx_MTYP |
251 FMC_BCRx_MWID |
252 FMC_BCRx_FACCEN |
253 FMC_BCRx_BURSTEN |
254 FMC_BCRx_WAITPOL |
255 FMC_BCRx_WAITCFG |
256 FMC_BCRx_WREN |
257 FMC_BCRx_WAITEN |
258 FMC_BCRx_EXTMOD |
259 FMC_BCRx_ASYNCWAIT |
260 FMC_BCRx_CBURSTRW);
261
262 mask |= FMC_BCR1_CCLKEN;
263 mask |= FMC_BCR1_WFDIS;
264 mask |= FMC_BCRx_NBLSET;
265 mask |= FMC_BCRx_CPSIZE;
266
267 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
268
269 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
270 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
271 {
272 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
273 }
274
275 if (Init->NSBank != FMC_NORSRAM_BANK1)
276 {
277 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
278 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
279 }
280
281 /* Check PSRAM chip select counter state */
282 if (Init->MaxChipSelectPulse == ENABLE)
283 {
284 /* Check the parameters */
285 assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime));
286
287 /* Configure PSRAM chip select counter value */
288 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));
289
290 /* Enable PSRAM chip select counter for the bank */
291 switch (Init->NSBank)
292 {
293 case FMC_NORSRAM_BANK1 :
294 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
295 break;
296
297 case FMC_NORSRAM_BANK2 :
298 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
299 break;
300
301 case FMC_NORSRAM_BANK3 :
302 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
303 break;
304
305 default :
306 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
307 break;
308 }
309 }
310
311 return HAL_OK;
312 }
313
314 /**
315 * @brief DeInitialize the FMC_NORSRAM peripheral
316 * @param Device Pointer to NORSRAM device instance
317 * @param ExDevice Pointer to NORSRAM extended mode device instance
318 * @param Bank NORSRAM bank number
319 * @retval HAL status
320 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)321 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
322 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
323 {
324 /* Check the parameters */
325 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
326 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
327 assert_param(IS_FMC_NORSRAM_BANK(Bank));
328
329 /* Disable the FMC_NORSRAM device */
330 __FMC_NORSRAM_DISABLE(Device, Bank);
331
332 /* De-initialize the FMC_NORSRAM device */
333 /* FMC_NORSRAM_BANK1 */
334 if (Bank == FMC_NORSRAM_BANK1)
335 {
336 Device->BTCR[Bank] = 0x000030DBU;
337 }
338 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
339 else
340 {
341 Device->BTCR[Bank] = 0x000030D2U;
342 }
343
344 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
345 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
346
347 /* De-initialize PSRAM chip select counter */
348 switch (Bank)
349 {
350 case FMC_NORSRAM_BANK1 :
351 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
352 break;
353
354 case FMC_NORSRAM_BANK2 :
355 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
356 break;
357
358 case FMC_NORSRAM_BANK3 :
359 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
360 break;
361
362 default :
363 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
364 break;
365 }
366
367 return HAL_OK;
368 }
369
370 /**
371 * @brief Initialize the FMC_NORSRAM Timing according to the specified
372 * parameters in the FMC_NORSRAM_TimingTypeDef
373 * @param Device Pointer to NORSRAM device instance
374 * @param Timing Pointer to NORSRAM Timing structure
375 * @param Bank NORSRAM bank number
376 * @retval HAL status
377 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)378 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
379 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
380 {
381 uint32_t tmpr;
382
383 /* Check the parameters */
384 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
385 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
386 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
387 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
388 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
389 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
390 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
391 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
392 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
393 assert_param(IS_FMC_NORSRAM_BANK(Bank));
394
395 /* Set FMC_NORSRAM device timing parameters */
396 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
397 ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
398 ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
399 ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
400 ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
401 (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
402 (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
403 (Timing->AccessMode)));
404
405 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
406 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
407 {
408 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
409 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
410 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
411 }
412
413 return HAL_OK;
414 }
415
416 /**
417 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
418 * parameters in the FMC_NORSRAM_TimingTypeDef
419 * @param Device Pointer to NORSRAM device instance
420 * @param Timing Pointer to NORSRAM Timing structure
421 * @param Bank NORSRAM bank number
422 * @param ExtendedMode FMC Extended Mode
423 * This parameter can be one of the following values:
424 * @arg FMC_EXTENDED_MODE_DISABLE
425 * @arg FMC_EXTENDED_MODE_ENABLE
426 * @retval HAL status
427 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)428 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
429 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
430 uint32_t ExtendedMode)
431 {
432 /* Check the parameters */
433 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
434
435 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
436 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
437 {
438 /* Check the parameters */
439 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
440 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
441 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
442 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
443 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
444 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
445 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
446 assert_param(IS_FMC_NORSRAM_BANK(Bank));
447
448 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
449 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
450 ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
451 ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
452 ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) |
453 Timing->AccessMode |
454 ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
455 }
456 else
457 {
458 Device->BWTR[Bank] = 0x0FFFFFFFU;
459 }
460
461 return HAL_OK;
462 }
463 /**
464 * @}
465 */
466
467 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
468 * @brief management functions
469 *
470 @verbatim
471 ==============================================================================
472 ##### FMC_NORSRAM Control functions #####
473 ==============================================================================
474 [..]
475 This subsection provides a set of functions allowing to control dynamically
476 the FMC NORSRAM interface.
477
478 @endverbatim
479 * @{
480 */
481
482 /**
483 * @brief Enables dynamically FMC_NORSRAM write operation.
484 * @param Device Pointer to NORSRAM device instance
485 * @param Bank NORSRAM bank number
486 * @retval HAL status
487 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)488 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
489 {
490 /* Check the parameters */
491 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
492 assert_param(IS_FMC_NORSRAM_BANK(Bank));
493
494 /* Enable write operation */
495 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
496
497 return HAL_OK;
498 }
499
500 /**
501 * @brief Disables dynamically FMC_NORSRAM write operation.
502 * @param Device Pointer to NORSRAM device instance
503 * @param Bank NORSRAM bank number
504 * @retval HAL status
505 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)506 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
507 {
508 /* Check the parameters */
509 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
510 assert_param(IS_FMC_NORSRAM_BANK(Bank));
511
512 /* Disable write operation */
513 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
514
515 return HAL_OK;
516 }
517
518 /**
519 * @}
520 */
521
522 /**
523 * @}
524 */
525
526
527 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
528 * @brief NAND Controller functions
529 *
530 @verbatim
531 ==============================================================================
532 ##### How to use NAND device driver #####
533 ==============================================================================
534 [..]
535 This driver contains a set of APIs to interface with the FMC NAND banks in order
536 to run the NAND external devices.
537
538 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
539 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
540 (+) FMC NAND bank common space timing configuration using the function
541 FMC_NAND_CommonSpace_Timing_Init()
542 (+) FMC NAND bank attribute space timing configuration using the function
543 FMC_NAND_AttributeSpace_Timing_Init()
544 (+) FMC NAND bank enable/disable ECC correction feature using the functions
545 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
546 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
547
548 @endverbatim
549 * @{
550 */
551
552 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
553 * @brief Initialization and Configuration functions
554 *
555 @verbatim
556 ==============================================================================
557 ##### Initialization and de_initialization functions #####
558 ==============================================================================
559 [..]
560 This section provides functions allowing to:
561 (+) Initialize and configure the FMC NAND interface
562 (+) De-initialize the FMC NAND interface
563 (+) Configure the FMC clock and associated GPIOs
564
565 @endverbatim
566 * @{
567 */
568
569 /**
570 * @brief Initializes the FMC_NAND device according to the specified
571 * control parameters in the FMC_NAND_HandleTypeDef
572 * @param Device Pointer to NAND device instance
573 * @param Init Pointer to NAND Initialization structure
574 * @retval HAL status
575 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,FMC_NAND_InitTypeDef * Init)576 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
577 {
578 /* Check the parameters */
579 assert_param(IS_FMC_NAND_DEVICE(Device));
580 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
581 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
582 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
583 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
584 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
585 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
586 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
587
588 /* NAND bank 3 registers configuration */
589 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
590 FMC_PCR_MEMORY_TYPE_NAND |
591 Init->MemoryDataWidth |
592 Init->EccComputation |
593 Init->ECCPageSize |
594 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
595 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
596
597 return HAL_OK;
598 }
599
600 /**
601 * @brief Initializes the FMC_NAND Common space Timing according to the specified
602 * parameters in the FMC_NAND_PCC_TimingTypeDef
603 * @param Device Pointer to NAND device instance
604 * @param Timing Pointer to NAND timing structure
605 * @param Bank NAND bank number
606 * @retval HAL status
607 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)608 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
609 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
610 {
611 /* Check the parameters */
612 assert_param(IS_FMC_NAND_DEVICE(Device));
613 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
614 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
615 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
616 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
617 assert_param(IS_FMC_NAND_BANK(Bank));
618
619 /* Prevent unused argument(s) compilation warning if no assert_param check */
620 UNUSED(Bank);
621
622 /* NAND bank 3 registers configuration */
623 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
624 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
625 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
626 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)));
627
628 return HAL_OK;
629 }
630
631 /**
632 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
633 * parameters in the FMC_NAND_PCC_TimingTypeDef
634 * @param Device Pointer to NAND device instance
635 * @param Timing Pointer to NAND timing structure
636 * @param Bank NAND bank number
637 * @retval HAL status
638 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)639 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
640 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
641 {
642 /* Check the parameters */
643 assert_param(IS_FMC_NAND_DEVICE(Device));
644 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
645 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
646 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
647 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
648 assert_param(IS_FMC_NAND_BANK(Bank));
649
650 /* Prevent unused argument(s) compilation warning if no assert_param check */
651 UNUSED(Bank);
652
653 /* NAND bank 3 registers configuration */
654 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
655 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
656 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
657 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)));
658
659 return HAL_OK;
660 }
661
662 /**
663 * @brief DeInitializes the FMC_NAND device
664 * @param Device Pointer to NAND device instance
665 * @param Bank NAND bank number
666 * @retval HAL status
667 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)668 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
669 {
670 /* Check the parameters */
671 assert_param(IS_FMC_NAND_DEVICE(Device));
672 assert_param(IS_FMC_NAND_BANK(Bank));
673
674 /* Disable the NAND Bank */
675 __FMC_NAND_DISABLE(Device, Bank);
676
677 /* De-initialize the NAND Bank */
678 /* Prevent unused argument(s) compilation warning if no assert_param check */
679 UNUSED(Bank);
680
681 /* Set the FMC_NAND_BANK3 registers to their reset values */
682 WRITE_REG(Device->PCR, 0x00000018U);
683 WRITE_REG(Device->SR, 0x00000040U);
684 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
685 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
686
687 return HAL_OK;
688 }
689
690 /**
691 * @}
692 */
693
694 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
695 * @brief management functions
696 *
697 @verbatim
698 ==============================================================================
699 ##### FMC_NAND Control functions #####
700 ==============================================================================
701 [..]
702 This subsection provides a set of functions allowing to control dynamically
703 the FMC NAND interface.
704
705 @endverbatim
706 * @{
707 */
708
709
710 /**
711 * @brief Enables dynamically FMC_NAND ECC feature.
712 * @param Device Pointer to NAND device instance
713 * @param Bank NAND bank number
714 * @retval HAL status
715 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)716 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
717 {
718 /* Check the parameters */
719 assert_param(IS_FMC_NAND_DEVICE(Device));
720 assert_param(IS_FMC_NAND_BANK(Bank));
721
722 /* Enable ECC feature */
723 /* Prevent unused argument(s) compilation warning if no assert_param check */
724 UNUSED(Bank);
725
726 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
727
728 return HAL_OK;
729 }
730
731
732 /**
733 * @brief Disables dynamically FMC_NAND ECC feature.
734 * @param Device Pointer to NAND device instance
735 * @param Bank NAND bank number
736 * @retval HAL status
737 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)738 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
739 {
740 /* Check the parameters */
741 assert_param(IS_FMC_NAND_DEVICE(Device));
742 assert_param(IS_FMC_NAND_BANK(Bank));
743
744 /* Disable ECC feature */
745 /* Prevent unused argument(s) compilation warning if no assert_param check */
746 UNUSED(Bank);
747
748 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
749
750 return HAL_OK;
751 }
752
753 /**
754 * @brief Disables dynamically FMC_NAND ECC feature.
755 * @param Device Pointer to NAND device instance
756 * @param ECCval Pointer to ECC value
757 * @param Bank NAND bank number
758 * @param Timeout Timeout wait value
759 * @retval HAL status
760 */
FMC_NAND_GetECC(FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)761 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
762 uint32_t Timeout)
763 {
764 uint32_t tickstart;
765
766 /* Check the parameters */
767 assert_param(IS_FMC_NAND_DEVICE(Device));
768 assert_param(IS_FMC_NAND_BANK(Bank));
769
770 /* Get tick */
771 tickstart = HAL_GetTick();
772
773 /* Wait until FIFO is empty */
774 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
775 {
776 /* Check for the Timeout */
777 if (Timeout != HAL_MAX_DELAY)
778 {
779 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
780 {
781 return HAL_TIMEOUT;
782 }
783 }
784 }
785
786 /* Prevent unused argument(s) compilation warning if no assert_param check */
787 UNUSED(Bank);
788
789 /* Get the ECCR register value */
790 *ECCval = (uint32_t)Device->ECCR;
791
792 return HAL_OK;
793 }
794
795 /**
796 * @}
797 */
798
799
800
801 /** @defgroup FMC_LL_SDRAM
802 * @brief SDRAM Controller functions
803 *
804 @verbatim
805 ==============================================================================
806 ##### How to use SDRAM device driver #####
807 ==============================================================================
808 [..]
809 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
810 to run the SDRAM external devices.
811
812 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
813 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
814 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
815 (+) FMC SDRAM bank enable/disable write operation using the functions
816 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
817 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
818
819 @endverbatim
820 * @{
821 */
822
823 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
824 * @brief Initialization and Configuration functions
825 *
826 @verbatim
827 ==============================================================================
828 ##### Initialization and de_initialization functions #####
829 ==============================================================================
830 [..]
831 This section provides functions allowing to:
832 (+) Initialize and configure the FMC SDRAM interface
833 (+) De-initialize the FMC SDRAM interface
834 (+) Configure the FMC clock and associated GPIOs
835
836 @endverbatim
837 * @{
838 */
839
840 /**
841 * @brief Initializes the FMC_SDRAM device according to the specified
842 * control parameters in the FMC_SDRAM_InitTypeDef
843 * @param Device Pointer to SDRAM device instance
844 * @param Init Pointer to SDRAM Initialization structure
845 * @retval HAL status
846 */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_InitTypeDef * Init)847 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
848 {
849 /* Check the parameters */
850 assert_param(IS_FMC_SDRAM_DEVICE(Device));
851 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
852 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
853 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
854 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
855 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
856 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
857 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
858 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
859 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
860 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
861
862 /* Set SDRAM bank configuration parameters */
863 if (Init->SDBank == FMC_SDRAM_BANK1)
864 {
865 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
866 SDCR_CLEAR_MASK,
867 (Init->ColumnBitsNumber |
868 Init->RowBitsNumber |
869 Init->MemoryDataWidth |
870 Init->InternalBankNumber |
871 Init->CASLatency |
872 Init->WriteProtection |
873 Init->SDClockPeriod |
874 Init->ReadBurst |
875 Init->ReadPipeDelay));
876 }
877 else /* FMC_Bank2_SDRAM */
878 {
879 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
880 FMC_SDCRx_SDCLK |
881 FMC_SDCRx_RBURST |
882 FMC_SDCRx_RPIPE,
883 (Init->SDClockPeriod |
884 Init->ReadBurst |
885 Init->ReadPipeDelay));
886
887 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
888 SDCR_CLEAR_MASK,
889 (Init->ColumnBitsNumber |
890 Init->RowBitsNumber |
891 Init->MemoryDataWidth |
892 Init->InternalBankNumber |
893 Init->CASLatency |
894 Init->WriteProtection));
895 }
896
897 return HAL_OK;
898 }
899
900
901 /**
902 * @brief Initializes the FMC_SDRAM device timing according to the specified
903 * parameters in the FMC_SDRAM_TimingTypeDef
904 * @param Device Pointer to SDRAM device instance
905 * @param Timing Pointer to SDRAM Timing structure
906 * @param Bank SDRAM bank number
907 * @retval HAL status
908 */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)909 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
910 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
911 {
912 /* Check the parameters */
913 assert_param(IS_FMC_SDRAM_DEVICE(Device));
914 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
915 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
916 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
917 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
918 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
919 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
920 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
921 assert_param(IS_FMC_SDRAM_BANK(Bank));
922
923 /* Set SDRAM device timing parameters */
924 if (Bank == FMC_SDRAM_BANK1)
925 {
926 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
927 SDTR_CLEAR_MASK,
928 (((Timing->LoadToActiveDelay) - 1U) |
929 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
930 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) |
931 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) |
932 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) |
933 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) |
934 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos)));
935 }
936 else /* FMC_Bank2_SDRAM */
937 {
938 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
939 FMC_SDTRx_TRC |
940 FMC_SDTRx_TRP,
941 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) |
942 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos));
943
944 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
945 SDTR_CLEAR_MASK,
946 (((Timing->LoadToActiveDelay) - 1U) |
947 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
948 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) |
949 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) |
950 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos)));
951 }
952
953 return HAL_OK;
954 }
955
956 /**
957 * @brief DeInitializes the FMC_SDRAM peripheral
958 * @param Device Pointer to SDRAM device instance
959 * @retval HAL status
960 */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)961 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
962 {
963 /* Check the parameters */
964 assert_param(IS_FMC_SDRAM_DEVICE(Device));
965 assert_param(IS_FMC_SDRAM_BANK(Bank));
966
967 /* De-initialize the SDRAM device */
968 Device->SDCR[Bank] = 0x000002D0U;
969 Device->SDTR[Bank] = 0x0FFFFFFFU;
970 Device->SDCMR = 0x00000000U;
971 Device->SDRTR = 0x00000000U;
972 Device->SDSR = 0x00000000U;
973
974 return HAL_OK;
975 }
976
977 /**
978 * @}
979 */
980
981 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
982 * @brief management functions
983 *
984 @verbatim
985 ==============================================================================
986 ##### FMC_SDRAM Control functions #####
987 ==============================================================================
988 [..]
989 This subsection provides a set of functions allowing to control dynamically
990 the FMC SDRAM interface.
991
992 @endverbatim
993 * @{
994 */
995
996 /**
997 * @brief Enables dynamically FMC_SDRAM write protection.
998 * @param Device Pointer to SDRAM device instance
999 * @param Bank SDRAM bank number
1000 * @retval HAL status
1001 */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1002 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1003 {
1004 /* Check the parameters */
1005 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1006 assert_param(IS_FMC_SDRAM_BANK(Bank));
1007
1008 /* Enable write protection */
1009 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1010
1011 return HAL_OK;
1012 }
1013
1014 /**
1015 * @brief Disables dynamically FMC_SDRAM write protection.
1016 * @param hsdram FMC_SDRAM handle
1017 * @retval HAL status
1018 */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1019 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1020 {
1021 /* Check the parameters */
1022 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1023 assert_param(IS_FMC_SDRAM_BANK(Bank));
1024
1025 /* Disable write protection */
1026 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1027
1028 return HAL_OK;
1029 }
1030
1031 /**
1032 * @brief Send Command to the FMC SDRAM bank
1033 * @param Device Pointer to SDRAM device instance
1034 * @param Command Pointer to SDRAM command structure
1035 * @param Timing Pointer to SDRAM Timing structure
1036 * @param Timeout Timeout wait value
1037 * @retval HAL state
1038 */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1039 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
1040 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
1041 {
1042 /* Check the parameters */
1043 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1044 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1045 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1046 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1047 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1048
1049 /* Set command register */
1050 MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
1051 ((Command->CommandMode) | (Command->CommandTarget) |
1052 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
1053 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
1054 /* Prevent unused argument(s) compilation warning */
1055 UNUSED(Timeout);
1056 return HAL_OK;
1057 }
1058
1059 /**
1060 * @brief Program the SDRAM Memory Refresh rate.
1061 * @param Device Pointer to SDRAM device instance
1062 * @param RefreshRate The SDRAM refresh rate value.
1063 * @retval HAL state
1064 */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)1065 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1066 {
1067 /* Check the parameters */
1068 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1069 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1070
1071 /* Set the refresh rate in command register */
1072 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1073
1074 return HAL_OK;
1075 }
1076
1077 /**
1078 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1079 * @param Device Pointer to SDRAM device instance
1080 * @param AutoRefreshNumber Specifies the auto Refresh number.
1081 * @retval None
1082 */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)1083 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1084 uint32_t AutoRefreshNumber)
1085 {
1086 /* Check the parameters */
1087 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1088 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1089
1090 /* Set the Auto-refresh number in command register */
1091 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1092
1093 return HAL_OK;
1094 }
1095
1096 /**
1097 * @brief Returns the indicated FMC SDRAM bank mode status.
1098 * @param Device Pointer to SDRAM device instance
1099 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1100 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1101 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1102 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1103 * FMC_SDRAM_POWER_DOWN_MODE.
1104 */
FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1105 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1106 {
1107 uint32_t tmpreg;
1108
1109 /* Check the parameters */
1110 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1111 assert_param(IS_FMC_SDRAM_BANK(Bank));
1112
1113 /* Get the corresponding bank mode */
1114 if (Bank == FMC_SDRAM_BANK1)
1115 {
1116 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1117 }
1118 else
1119 {
1120 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1121 }
1122
1123 /* Return the mode status */
1124 return tmpreg;
1125 }
1126
1127 /**
1128 * @}
1129 */
1130
1131 /**
1132 * @}
1133 */
1134
1135
1136 /**
1137 * @}
1138 */
1139
1140 /**
1141 * @}
1142 */
1143
1144 #endif /* HAL_NOR_MODULE_ENABLED */
1145 /**
1146 * @}
1147 */
1148 /**
1149 * @}
1150 */
1151
