1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_DAC_H
21 #define STM32H5xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60
61 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
62 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64
65 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
66 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
67 DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 24 bits) */
70
71 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
72 DHR12Rx channel 1 (shifted left of 28 bits) */
73 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77
78 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
79 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
80 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
81 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
82 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83
84 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
85
86 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
87 DORx channel 2 (shifted left of 5 bits) */
88 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
89
90 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
91 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
92 SHSRx channel 2 (shifted left of 6 bits) */
93 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
94
95
96 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
97 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
98 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
99 to position 0 */
100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
101 to position 0 */
102
103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
104 channel 1 or 2 versus DHR12Rx channel 1
105 (shifted left of 28 bits) */
106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 20 bits) */
109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 24 bits) */
112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
113 channel 1 or 2 versus DORx channel 1
114 (shifted left of 5 bits) */
115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
116 channel 1 or 2 versus SHSRx channel 1
117 (shifted left of 6 bits) */
118
119 /* DAC registers bits positions */
120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
123
124 /* Miscellaneous data */
125 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
126 bits (voltage range determined by analog voltage
127 references Vref+ and Vref-, refer to reference manual) */
128
129 /**
130 * @}
131 */
132
133
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
136 * @{
137 */
138
139 /**
140 * @brief Driver macro reserved for internal use: set a pointer to
141 * a register from a register basis from which an offset
142 * is applied.
143 * @param __REG__ Register basis from which the offset is applied.
144 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
145 * @retval Pointer to register address
146 */
147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
148 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
149
150 /**
151 * @}
152 */
153
154
155 /* Exported types ------------------------------------------------------------*/
156 #if defined(USE_FULL_LL_DRIVER)
157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
158 * @{
159 */
160
161 /**
162 * @brief Structure definition of some features of DAC instance.
163 */
164 typedef struct
165 {
166 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
167 internal (SW start) or from external peripheral
168 (timer event, external interrupt line).
169 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
170
171 This feature can be modified afterwards using unitary
172 function @ref LL_DAC_SetTriggerSource(). */
173
174 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
175 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
176
177 This feature can be modified afterwards using unitary
178 function @ref LL_DAC_SetWaveAutoGeneration(). */
179
180 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
181 If waveform automatic generation mode is set to noise, this parameter
182 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
183 If waveform automatic generation mode is set to triangle,
184 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
185 @note If waveform automatic generation mode is disabled,
186 this parameter is discarded.
187
188 This feature can be modified afterwards using unitary
189 function @ref LL_DAC_SetWaveNoiseLFSR(),
190 @ref LL_DAC_SetWaveTriangleAmplitude()
191 depending on the wave automatic generation selected. */
192
193 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
194 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
195
196 This feature can be modified afterwards using unitary
197 function @ref LL_DAC_SetOutputBuffer(). */
198
199 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
200 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
201
202 This feature can be modified afterwards using unitary
203 function @ref LL_DAC_SetOutputConnection(). */
204
205 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
206 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
207
208 This feature can be modified afterwards using unitary
209 function @ref LL_DAC_SetOutputMode(). */
210 } LL_DAC_InitTypeDef;
211
212 /**
213 * @}
214 */
215 #endif /* USE_FULL_LL_DRIVER */
216
217 /* Exported constants --------------------------------------------------------*/
218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
219 * @{
220 */
221
222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
223 * @brief Flags defines which can be used with LL_DAC_ReadReg function
224 * @{
225 */
226 /* DAC channel 1 flags */
227 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
228 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
229 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
230 #define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) /*!< DAC channel 1 flag ready */
231 #define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1) /*!< DAC channel 1 flag output register */
232
233 /* DAC channel 2 flags */
234 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
235 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
236 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
237 #define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */
238 #define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */
239
240 /**
241 * @}
242 */
243
244 /** @defgroup DAC_LL_EC_IT DAC interruptions
245 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
246 * @{
247 */
248 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
249
250 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
251
252 /**
253 * @}
254 */
255
256 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
257 * @{
258 */
259 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
260 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
261 /**
262 * @}
263 */
264
265 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
266 * @brief High frequency interface mode defines that can be used
267 * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
268 * @{
269 */
270 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
271 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
272 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
273 /**
274 * @}
275 */
276
277 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
278 * @{
279 */
280 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
281 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
282 /**
283 * @}
284 */
285
286 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
287 * @{
288 */
289 /* Triggers common to all devices of STM32H5 series */
290 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
291 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
292 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
293 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
294 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
295 #define LL_DAC_TRIG_EXT_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */
296 #define LL_DAC_TRIG_EXT_LPTIM2_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 CH1. */
297 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
298
299 /* Triggers specific to some devices of STM32H5 series */
300 #if defined(TIM8)
301 /* Devices STM32H563/H573xx */
302 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
303 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
304 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
305 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
306 #else
307 /* Devices STM32H503xx */
308 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */
309 #endif /* Devices STM32H563/H573xx or STM32H503xx */
310
311 #define LL_DAC_TRIG_EXT_LPTIM1_OUT LL_DAC_TRIG_EXT_LPTIM1_CH1 /*!< Keep old definition for compatibility */
312 #define LL_DAC_TRIG_EXT_LPTIM2_OUT LL_DAC_TRIG_EXT_LPTIM2_CH1 /*!< Keep old definition for compatibility */
313 /**
314 * @}
315 */
316
317 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
318 * @{
319 */
320 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
321 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
322 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
323 /**
324 * @}
325 */
326
327 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
328 * @{
329 */
330 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
331 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
332 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
333 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
334 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
335 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
336 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
337 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
338 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
339 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
340 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
341 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
342 /**
343 * @}
344 */
345
346 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
347 * @{
348 */
349 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
350 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
351 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
352 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
353 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
354 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
355 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
356 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
357 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
358 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
359 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
360 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
361 /**
362 * @}
363 */
364
365 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
366 * @{
367 */
368 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
369 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
370 /**
371 * @}
372 */
373
374 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
375 * @{
376 */
377 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
378 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
379 /**
380 * @}
381 */
382
383 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
384 * @{
385 */
386 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
387 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
388 /**
389 * @}
390 */
391
392 /** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
393 * @{
394 */
395 #define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */
396 #define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
397 /**
398 * @}
399 */
400
401 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
402 * @{
403 */
404 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
405 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
406 /**
407 * @}
408 */
409
410 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
411 * @{
412 */
413 /* List of DAC registers intended to be used (most commonly) with */
414 /* DMA transfer. */
415 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
416 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
417 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
418 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
419 /**
420 * @}
421 */
422
423 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
424 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
425 * not timeout values.
426 * For details on delays values, refer to descriptions in source code
427 * above each literal definition.
428 * @{
429 */
430
431 /* Delay for DAC channel voltage settling time from DAC channel startup */
432 /* (transition from disable to enable). */
433 /* Note: DAC channel startup time depends on board application environment: */
434 /* impedance connected to DAC channel output. */
435 /* The delay below is specified under conditions: */
436 /* - voltage maximum transition (lowest to highest value) */
437 /* - until voltage reaches final value +-1LSB */
438 /* - DAC channel output buffer enabled */
439 /* - load impedance of 5kOhm (min), 50pF (max) */
440 /* Literal set to maximum value (refer to device datasheet, */
441 /* parameter "tWAKEUP"). */
442 /* Unit: us */
443 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
444
445 /* Delay for DAC channel voltage settling time. */
446 /* Note: DAC channel startup time depends on board application environment: */
447 /* impedance connected to DAC channel output. */
448 /* The delay below is specified under conditions: */
449 /* - voltage maximum transition (lowest to highest value) */
450 /* - until voltage reaches final value +-1LSB */
451 /* - DAC channel output buffer enabled */
452 /* - load impedance of 5kOhm min, 50pF max */
453 /* Literal set to maximum value (refer to device datasheet, */
454 /* parameter "tSETTLING"). */
455 /* Unit: us */
456 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
457
458 /**
459 * @}
460 */
461
462 /**
463 * @}
464 */
465
466 /* Exported macro ------------------------------------------------------------*/
467 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
468 * @{
469 */
470
471 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
472 * @{
473 */
474
475 /**
476 * @brief Write a value in DAC register
477 * @param __INSTANCE__ DAC Instance
478 * @param __REG__ Register to be written
479 * @param __VALUE__ Value to be written in the register
480 * @retval None
481 */
482 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
483
484 /**
485 * @brief Read a value in DAC register
486 * @param __INSTANCE__ DAC Instance
487 * @param __REG__ Register to be read
488 * @retval Register value
489 */
490 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
491
492 /**
493 * @}
494 */
495
496 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
497 * @{
498 */
499
500 /**
501 * @brief Helper macro to get DAC channel number in decimal format
502 * from literals LL_DAC_CHANNEL_x.
503 * Example:
504 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
505 * will return decimal number "1".
506 * @note The input can be a value from functions where a channel
507 * number is returned.
508 * @param __CHANNEL__ This parameter can be one of the following values:
509 * @arg @ref LL_DAC_CHANNEL_1
510 * @arg @ref LL_DAC_CHANNEL_2
511 * @retval 1...2
512 */
513 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
514 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
515
516 /**
517 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
518 * from number in decimal format.
519 * Example:
520 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
521 * will return a data equivalent to "LL_DAC_CHANNEL_1".
522 * @note If the input parameter does not correspond to a DAC channel,
523 * this macro returns value '0'.
524 * @param __DECIMAL_NB__ 1...2
525 * @retval Returned value can be one of the following values:
526 * @arg @ref LL_DAC_CHANNEL_1
527 * @arg @ref LL_DAC_CHANNEL_2
528 */
529 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
530 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
531
532 /**
533 * @brief Helper macro to define the DAC conversion data full-scale digital
534 * value corresponding to the selected DAC resolution.
535 * @note DAC conversion data full-scale corresponds to voltage range
536 * determined by analog voltage references Vref+ and Vref-
537 * (refer to reference manual).
538 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
539 * @arg @ref LL_DAC_RESOLUTION_12B
540 * @arg @ref LL_DAC_RESOLUTION_8B
541 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
542 */
543 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
544 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
545
546 /**
547 * @brief Helper macro to calculate the DAC conversion data (unit: digital
548 * value) corresponding to a voltage (unit: mVolt).
549 * @note This helper macro is intended to provide input data in voltage
550 * rather than digital value,
551 * to be used with LL DAC functions such as
552 * @ref LL_DAC_ConvertData12RightAligned().
553 * @note Analog reference voltage (Vref+) must be either known from
554 * user board environment or can be calculated using ADC measurement
555 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
556 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
557 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
558 * (unit: mVolt).
559 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
560 * @arg @ref LL_DAC_RESOLUTION_12B
561 * @arg @ref LL_DAC_RESOLUTION_8B
562 * @retval DAC conversion data (unit: digital value)
563 */
564 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
565 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
566 / (__VREFANALOG_VOLTAGE__) \
567 )
568
569 /**
570 * @}
571 */
572
573 /**
574 * @}
575 */
576
577
578 /* Exported functions --------------------------------------------------------*/
579 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
580 * @{
581 */
582 /** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
583 * @{
584 */
585 /**
586 * @brief Set the high frequency interface mode for the selected DAC instance
587 * @rmtoll MCR HFSEL LL_DAC_SetHighFrequencyMode
588 * @param DACx DAC instance
589 * @param HighFreqMode This parameter can be one of the following values:
590 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
591 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
592 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
593 * @retval None
594 */
LL_DAC_SetHighFrequencyMode(DAC_TypeDef * DACx,uint32_t HighFreqMode)595 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
596 {
597 MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
598 }
599
600 /**
601 * @brief Get the high frequency interface mode for the selected DAC instance
602 * @rmtoll MCR HFSEL LL_DAC_GetHighFrequencyMode
603 * @param DACx DAC instance
604 * @retval Returned value can be one of the following values:
605 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
606 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
607 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
608 */
LL_DAC_GetHighFrequencyMode(const DAC_TypeDef * DACx)609 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx)
610 {
611 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
612 }
613 /**
614 * @}
615 */
616
617
618 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
619 * @{
620 */
621
622 /**
623 * @brief Set the operating mode for the selected DAC channel:
624 * calibration or normal operating mode.
625 * @rmtoll CR CEN1 LL_DAC_SetMode\n
626 * CR CEN2 LL_DAC_SetMode
627 * @param DACx DAC instance
628 * @param DAC_Channel This parameter can be one of the following values:
629 * @arg @ref LL_DAC_CHANNEL_1
630 * @arg @ref LL_DAC_CHANNEL_2
631 * @param ChannelMode This parameter can be one of the following values:
632 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
633 * @arg @ref LL_DAC_MODE_CALIBRATION
634 * @retval None
635 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)636 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
637 {
638 MODIFY_REG(DACx->CR,
639 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
640 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
641 }
642
643 /**
644 * @brief Get the operating mode for the selected DAC channel:
645 * calibration or normal operating mode.
646 * @rmtoll CR CEN1 LL_DAC_GetMode\n
647 * CR CEN2 LL_DAC_GetMode
648 * @param DACx DAC instance
649 * @param DAC_Channel This parameter can be one of the following values:
650 * @arg @ref LL_DAC_CHANNEL_1
651 * @arg @ref LL_DAC_CHANNEL_2
652 * @retval Returned value can be one of the following values:
653 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
654 * @arg @ref LL_DAC_MODE_CALIBRATION
655 */
LL_DAC_GetMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)656 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
657 {
658 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
659 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
660 );
661 }
662
663 /**
664 * @brief Set the offset trimming value for the selected DAC channel.
665 * Trimming has an impact when output buffer is enabled
666 * and is intended to replace factory calibration default values.
667 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
668 * CCR OTRIM2 LL_DAC_SetTrimmingValue
669 * @param DACx DAC instance
670 * @param DAC_Channel This parameter can be one of the following values:
671 * @arg @ref LL_DAC_CHANNEL_1
672 * @arg @ref LL_DAC_CHANNEL_2
673 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
674 * @retval None
675 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)676 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
677 {
678 MODIFY_REG(DACx->CCR,
679 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
680 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
681 }
682
683 /**
684 * @brief Get the offset trimming value for the selected DAC channel.
685 * Trimming has an impact when output buffer is enabled
686 * and is intended to replace factory calibration default values.
687 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
688 * CCR OTRIM2 LL_DAC_GetTrimmingValue
689 * @param DACx DAC instance
690 * @param DAC_Channel This parameter can be one of the following values:
691 * @arg @ref LL_DAC_CHANNEL_1
692 * @arg @ref LL_DAC_CHANNEL_2
693 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
694 */
LL_DAC_GetTrimmingValue(const DAC_TypeDef * DACx,uint32_t DAC_Channel)695 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
696 {
697 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
698 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
699 );
700 }
701
702 /**
703 * @brief Set the conversion trigger source for the selected DAC channel.
704 * @note For conversion trigger source to be effective, DAC trigger
705 * must be enabled using function @ref LL_DAC_EnableTrigger().
706 * @note To set conversion trigger source, DAC channel must be disabled.
707 * Otherwise, the setting is discarded.
708 * @note Availability of parameters of trigger sources from timer
709 * depends on timers availability on the selected device.
710 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
711 * CR TSEL2 LL_DAC_SetTriggerSource
712 * @param DACx DAC instance
713 * @param DAC_Channel This parameter can be one of the following values:
714 * @arg @ref LL_DAC_CHANNEL_1
715 * @arg @ref LL_DAC_CHANNEL_2
716 * @param TriggerSource This parameter can be one of the following values:
717 * @arg @ref LL_DAC_TRIG_SOFTWARE
718 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
719 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
720 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
721 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (2)
722 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (2)
723 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRG
724 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
725 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
726 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (2)
727 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
728 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_CH1
729 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
730 *
731 * (1) On this STM32 series, parameter not available on all devices.
732 * Only available on STM32H503xx (refer to device reference manual for supported features list)
733 * (2) On this STM32 series, parameter not available on all devices.
734 * Only available on STM32H563/H573xx (refer to device reference manual for supported features list)
735 * @retval None
736 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)737 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
738 {
739 MODIFY_REG(DACx->CR,
740 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
741 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
742 }
743
744 /**
745 * @brief Get the conversion trigger source for the selected DAC channel.
746 * @note For conversion trigger source to be effective, DAC trigger
747 * must be enabled using function @ref LL_DAC_EnableTrigger().
748 * @note Availability of parameters of trigger sources from timer
749 * depends on timers availability on the selected device.
750 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
751 * CR TSEL2 LL_DAC_GetTriggerSource
752 * @param DACx DAC instance
753 * @param DAC_Channel This parameter can be one of the following values:
754 * @arg @ref LL_DAC_CHANNEL_1
755 * @arg @ref LL_DAC_CHANNEL_2
756 * @retval Returned value can be one of the following values:
757 * @arg @ref LL_DAC_TRIG_SOFTWARE
758 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
759 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
760 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
761 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (2)
762 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (2)
763 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRG
764 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
765 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
766 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (2)
767 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
768 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_CH1
769 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
770 *
771 * (1) On this STM32 series, parameter not available on all devices.
772 * Only available on STM32H503xx (refer to device reference manual for supported features list)
773 * (2) On this STM32 series, parameter not available on all devices.
774 * Only available on STM32H563/H573xx (refer to device reference manual for supported features list)
775 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)776 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
777 {
778 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
779 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
780 );
781 }
782
783 /**
784 * @brief Set the waveform automatic generation mode
785 * for the selected DAC channel.
786 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
787 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
788 * @param DACx DAC instance
789 * @param DAC_Channel This parameter can be one of the following values:
790 * @arg @ref LL_DAC_CHANNEL_1
791 * @arg @ref LL_DAC_CHANNEL_2
792 * @param WaveAutoGeneration This parameter can be one of the following values:
793 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
794 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
795 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
796 * @retval None
797 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)798 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
799 {
800 MODIFY_REG(DACx->CR,
801 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
802 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
803 }
804
805 /**
806 * @brief Get the waveform automatic generation mode
807 * for the selected DAC channel.
808 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
809 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
810 * @param DACx DAC instance
811 * @param DAC_Channel This parameter can be one of the following values:
812 * @arg @ref LL_DAC_CHANNEL_1
813 * @arg @ref LL_DAC_CHANNEL_2
814 * @retval Returned value can be one of the following values:
815 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
816 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
817 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
818 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)819 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
820 {
821 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
822 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
823 );
824 }
825
826 /**
827 * @brief Set the noise waveform generation for the selected DAC channel:
828 * Noise mode and parameters LFSR (linear feedback shift register).
829 * @note For wave generation to be effective, DAC channel
830 * wave generation mode must be enabled using
831 * function @ref LL_DAC_SetWaveAutoGeneration().
832 * @note This setting can be set when the selected DAC channel is disabled
833 * (otherwise, the setting operation is ignored).
834 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
835 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
836 * @param DACx DAC instance
837 * @param DAC_Channel This parameter can be one of the following values:
838 * @arg @ref LL_DAC_CHANNEL_1
839 * @arg @ref LL_DAC_CHANNEL_2
840 * @param NoiseLFSRMask This parameter can be one of the following values:
841 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
842 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
843 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
844 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
845 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
846 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
847 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
848 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
849 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
850 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
851 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
852 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
853 * @retval None
854 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)855 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
856 {
857 MODIFY_REG(DACx->CR,
858 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
859 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
860 }
861
862 /**
863 * @brief Get the noise waveform generation for the selected DAC channel:
864 * Noise mode and parameters LFSR (linear feedback shift register).
865 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
866 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
867 * @param DACx DAC instance
868 * @param DAC_Channel This parameter can be one of the following values:
869 * @arg @ref LL_DAC_CHANNEL_1
870 * @arg @ref LL_DAC_CHANNEL_2
871 * @retval Returned value can be one of the following values:
872 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
873 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
874 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
875 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
876 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
877 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
878 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
879 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
880 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
881 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
882 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
883 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
884 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)885 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
886 {
887 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
888 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
889 );
890 }
891
892 /**
893 * @brief Set the triangle waveform generation for the selected DAC channel:
894 * triangle mode and amplitude.
895 * @note For wave generation to be effective, DAC channel
896 * wave generation mode must be enabled using
897 * function @ref LL_DAC_SetWaveAutoGeneration().
898 * @note This setting can be set when the selected DAC channel is disabled
899 * (otherwise, the setting operation is ignored).
900 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
901 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
902 * @param DACx DAC instance
903 * @param DAC_Channel This parameter can be one of the following values:
904 * @arg @ref LL_DAC_CHANNEL_1
905 * @arg @ref LL_DAC_CHANNEL_2
906 * @param TriangleAmplitude This parameter can be one of the following values:
907 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
908 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
909 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
910 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
911 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
912 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
913 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
914 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
915 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
916 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
917 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
919 * @retval None
920 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)921 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
922 uint32_t TriangleAmplitude)
923 {
924 MODIFY_REG(DACx->CR,
925 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
926 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
927 }
928
929 /**
930 * @brief Get the triangle waveform generation for the selected DAC channel:
931 * triangle mode and amplitude.
932 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
933 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
934 * @param DACx DAC instance
935 * @param DAC_Channel This parameter can be one of the following values:
936 * @arg @ref LL_DAC_CHANNEL_1
937 * @arg @ref LL_DAC_CHANNEL_2
938 * @retval Returned value can be one of the following values:
939 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
940 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
941 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
942 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
943 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
944 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
945 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
946 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
947 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
948 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
949 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
950 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
951 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)952 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
953 {
954 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
955 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
956 );
957 }
958
959 /**
960 * @brief Set the output for the selected DAC channel.
961 * @note This function set several features:
962 * - mode normal or sample-and-hold
963 * - buffer
964 * - connection to GPIO or internal path.
965 * These features can also be set individually using
966 * dedicated functions:
967 * - @ref LL_DAC_SetOutputBuffer()
968 * - @ref LL_DAC_SetOutputMode()
969 * - @ref LL_DAC_SetOutputConnection()
970 * @note On this STM32 series, output connection depends on output mode
971 * (normal or sample and hold) and output buffer state.
972 * - if output connection is set to internal path and output buffer
973 * is enabled (whatever output mode):
974 * output connection is also connected to GPIO pin
975 * (both connections to GPIO pin and internal path).
976 * - if output connection is set to GPIO pin, output buffer
977 * is disabled, output mode set to sample and hold:
978 * output connection is also connected to internal path
979 * (both connections to GPIO pin and internal path).
980 * @note Mode sample-and-hold requires an external capacitor
981 * to be connected between DAC channel output and ground.
982 * Capacitor value depends on load on DAC channel output and
983 * sample-and-hold timings configured.
984 * As indication, capacitor typical value is 100nF
985 * (refer to device datasheet, parameter "CSH").
986 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
987 * CR MODE2 LL_DAC_ConfigOutput
988 * @param DACx DAC instance
989 * @param DAC_Channel This parameter can be one of the following values:
990 * @arg @ref LL_DAC_CHANNEL_1
991 * @arg @ref LL_DAC_CHANNEL_2
992 * @param OutputMode This parameter can be one of the following values:
993 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
994 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
995 * @param OutputBuffer This parameter can be one of the following values:
996 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
997 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
998 * @param OutputConnection This parameter can be one of the following values:
999 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1000 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1001 * @retval None
1002 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)1003 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
1004 uint32_t OutputBuffer, uint32_t OutputConnection)
1005 {
1006 MODIFY_REG(DACx->MCR,
1007 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1008 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1009 }
1010
1011 /**
1012 * @brief Set the output mode normal or sample-and-hold
1013 * for the selected DAC channel.
1014 * @note Mode sample-and-hold requires an external capacitor
1015 * to be connected between DAC channel output and ground.
1016 * Capacitor value depends on load on DAC channel output and
1017 * sample-and-hold timings configured.
1018 * As indication, capacitor typical value is 100nF
1019 * (refer to device datasheet, parameter "CSH").
1020 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
1021 * CR MODE2 LL_DAC_SetOutputMode
1022 * @param DACx DAC instance
1023 * @param DAC_Channel This parameter can be one of the following values:
1024 * @arg @ref LL_DAC_CHANNEL_1
1025 * @arg @ref LL_DAC_CHANNEL_2
1026 * @param OutputMode This parameter can be one of the following values:
1027 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1028 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1029 * @retval None
1030 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)1031 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1032 {
1033 MODIFY_REG(DACx->MCR,
1034 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1035 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1036 }
1037
1038 /**
1039 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1040 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1041 * CR MODE2 LL_DAC_GetOutputMode
1042 * @param DACx DAC instance
1043 * @param DAC_Channel This parameter can be one of the following values:
1044 * @arg @ref LL_DAC_CHANNEL_1
1045 * @arg @ref LL_DAC_CHANNEL_2
1046 * @retval Returned value can be one of the following values:
1047 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1048 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1049 */
LL_DAC_GetOutputMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1050 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1051 {
1052 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1053 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1054 );
1055 }
1056
1057 /**
1058 * @brief Set the output buffer for the selected DAC channel.
1059 * @note On this STM32 series, when buffer is enabled, its offset can be
1060 * trimmed: factory calibration default values can be
1061 * replaced by user trimming values, using function
1062 * @ref LL_DAC_SetTrimmingValue().
1063 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1064 * CR MODE2 LL_DAC_SetOutputBuffer
1065 * @param DACx DAC instance
1066 * @param DAC_Channel This parameter can be one of the following values:
1067 * @arg @ref LL_DAC_CHANNEL_1
1068 * @arg @ref LL_DAC_CHANNEL_2
1069 * @param OutputBuffer This parameter can be one of the following values:
1070 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1071 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1072 * @retval None
1073 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1074 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1075 {
1076 MODIFY_REG(DACx->MCR,
1077 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1078 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1079 }
1080
1081 /**
1082 * @brief Get the output buffer state for the selected DAC channel.
1083 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1084 * CR MODE2 LL_DAC_GetOutputBuffer
1085 * @param DACx DAC instance
1086 * @param DAC_Channel This parameter can be one of the following values:
1087 * @arg @ref LL_DAC_CHANNEL_1
1088 * @arg @ref LL_DAC_CHANNEL_2
1089 * @retval Returned value can be one of the following values:
1090 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1091 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1092 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1093 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1094 {
1095 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1096 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1097 );
1098 }
1099
1100 /**
1101 * @brief Set the output connection for the selected DAC channel.
1102 * @note On this STM32 series, output connection depends on output mode (normal or
1103 * sample and hold) and output buffer state.
1104 * - if output connection is set to internal path and output buffer
1105 * is enabled (whatever output mode):
1106 * output connection is also connected to GPIO pin
1107 * (both connections to GPIO pin and internal path).
1108 * - if output connection is set to GPIO pin, output buffer
1109 * is disabled, output mode set to sample and hold:
1110 * output connection is also connected to internal path
1111 * (both connections to GPIO pin and internal path).
1112 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1113 * CR MODE2 LL_DAC_SetOutputConnection
1114 * @param DACx DAC instance
1115 * @param DAC_Channel This parameter can be one of the following values:
1116 * @arg @ref LL_DAC_CHANNEL_1
1117 * @arg @ref LL_DAC_CHANNEL_2
1118 * @param OutputConnection This parameter can be one of the following values:
1119 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1120 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1121 * @retval None
1122 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1123 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1124 {
1125 MODIFY_REG(DACx->MCR,
1126 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1127 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1128 }
1129
1130 /**
1131 * @brief Get the output connection for the selected DAC channel.
1132 * @note On this STM32 series, output connection depends on output mode (normal or
1133 * sample and hold) and output buffer state.
1134 * - if output connection is set to internal path and output buffer
1135 * is enabled (whatever output mode):
1136 * output connection is also connected to GPIO pin
1137 * (both connections to GPIO pin and internal path).
1138 * - if output connection is set to GPIO pin, output buffer
1139 * is disabled, output mode set to sample and hold:
1140 * output connection is also connected to internal path
1141 * (both connections to GPIO pin and internal path).
1142 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1143 * CR MODE2 LL_DAC_GetOutputConnection
1144 * @param DACx DAC instance
1145 * @param DAC_Channel This parameter can be one of the following values:
1146 * @arg @ref LL_DAC_CHANNEL_1
1147 * @arg @ref LL_DAC_CHANNEL_2
1148 * @retval Returned value can be one of the following values:
1149 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1150 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1151 */
LL_DAC_GetOutputConnection(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1152 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1153 {
1154 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1155 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1156 );
1157 }
1158
1159 /**
1160 * @brief Set the sample-and-hold timing for the selected DAC channel:
1161 * sample time
1162 * @note Sample time must be set when DAC channel is disabled
1163 * or during DAC operation when DAC channel flag BWSTx is reset,
1164 * otherwise the setting is ignored.
1165 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1166 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1167 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1168 * @param DACx DAC instance
1169 * @param DAC_Channel This parameter can be one of the following values:
1170 * @arg @ref LL_DAC_CHANNEL_1
1171 * @arg @ref LL_DAC_CHANNEL_2
1172 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1173 * @retval None
1174 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1175 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1176 {
1177 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1178 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1179
1180 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1181 }
1182
1183 /**
1184 * @brief Get the sample-and-hold timing for the selected DAC channel:
1185 * sample time
1186 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1187 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1188 * @param DACx DAC instance
1189 * @param DAC_Channel This parameter can be one of the following values:
1190 * @arg @ref LL_DAC_CHANNEL_1
1191 * @arg @ref LL_DAC_CHANNEL_2
1192 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1193 */
LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1194 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1195 {
1196 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1197 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1198
1199 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1200 }
1201
1202 /**
1203 * @brief Set the sample-and-hold timing for the selected DAC channel:
1204 * hold time
1205 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1206 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1207 * @param DACx DAC instance
1208 * @param DAC_Channel This parameter can be one of the following values:
1209 * @arg @ref LL_DAC_CHANNEL_1
1210 * @arg @ref LL_DAC_CHANNEL_2
1211 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1212 * @retval None
1213 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1214 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1215 {
1216 MODIFY_REG(DACx->SHHR,
1217 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1218 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1219 }
1220
1221 /**
1222 * @brief Get the sample-and-hold timing for the selected DAC channel:
1223 * hold time
1224 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1225 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1226 * @param DACx DAC instance
1227 * @param DAC_Channel This parameter can be one of the following values:
1228 * @arg @ref LL_DAC_CHANNEL_1
1229 * @arg @ref LL_DAC_CHANNEL_2
1230 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1231 */
LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1232 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1233 {
1234 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1235 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1236 );
1237 }
1238
1239 /**
1240 * @brief Set the sample-and-hold timing for the selected DAC channel:
1241 * refresh time
1242 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1243 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1244 * @param DACx DAC instance
1245 * @param DAC_Channel This parameter can be one of the following values:
1246 * @arg @ref LL_DAC_CHANNEL_1
1247 * @arg @ref LL_DAC_CHANNEL_2
1248 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1249 * @retval None
1250 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1251 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1252 {
1253 MODIFY_REG(DACx->SHRR,
1254 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1255 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1256 }
1257
1258 /**
1259 * @brief Get the sample-and-hold timing for the selected DAC channel:
1260 * refresh time
1261 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1262 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1263 * @param DACx DAC instance
1264 * @param DAC_Channel This parameter can be one of the following values:
1265 * @arg @ref LL_DAC_CHANNEL_1
1266 * @arg @ref LL_DAC_CHANNEL_2
1267 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1268 */
LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1269 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1270 {
1271 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1272 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1273 );
1274 }
1275
1276 /**
1277 * @brief Set the signed format for the selected DAC channel.
1278 * @note On this STM32 series, signed format can be used to inject
1279 * Q1.15, Q1.11, Q1.7 signed format data to DAC.
1280 * Ex when using 12bits data format (Q1.11 is used):
1281 * 0x800 will output 0v level
1282 * 0xFFF will output mid-scale level
1283 * 0x000 will output mid-scale level
1284 * 0x7FF will output full-scale level
1285 * @rmtoll MCR SINFORMAT1 LL_DAC_SetSignedFormat\n
1286 * MCR SINFORMAT2 LL_DAC_SetSignedFormat
1287 * @param DACx DAC instance
1288 * @param DAC_Channel This parameter can be one of the following values:
1289 * @arg @ref LL_DAC_CHANNEL_1
1290 * @arg @ref LL_DAC_CHANNEL_2
1291 * @param SignedFormat This parameter can be one of the following values:
1292 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1293 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1294 * @retval None
1295 */
LL_DAC_SetSignedFormat(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SignedFormat)1296 __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
1297 {
1298 MODIFY_REG(DACx->MCR,
1299 DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1300 SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1301 }
1302
1303 /**
1304 * @brief Get the signed format state for the selected DAC channel.
1305 * @rmtoll MCR SINFORMAT1 LL_DAC_GetSignedFormat\n
1306 * MCR SINFORMAT2 LL_DAC_GetSignedFormat
1307 * @param DACx DAC instance
1308 * @param DAC_Channel This parameter can be one of the following values:
1309 * @arg @ref LL_DAC_CHANNEL_1
1310 * @arg @ref LL_DAC_CHANNEL_2
1311 * @retval Returned value can be one of the following values:
1312 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1313 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1314 */
LL_DAC_GetSignedFormat(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1315 __STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1316 {
1317 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1318 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1319 );
1320 }
1321
1322 /**
1323 * @}
1324 */
1325
1326 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1327 * @{
1328 */
1329
1330 /**
1331 * @brief Enable DAC DMA transfer request of the selected channel.
1332 * @note To configure DMA source address (peripheral address),
1333 * use function @ref LL_DAC_DMA_GetRegAddr().
1334 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1335 * CR DMAEN2 LL_DAC_EnableDMAReq
1336 * @param DACx DAC instance
1337 * @param DAC_Channel This parameter can be one of the following values:
1338 * @arg @ref LL_DAC_CHANNEL_1
1339 * @arg @ref LL_DAC_CHANNEL_2
1340 * @retval None
1341 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1342 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1343 {
1344 SET_BIT(DACx->CR,
1345 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1346 }
1347
1348 /**
1349 * @brief Disable DAC DMA transfer request of the selected channel.
1350 * @note To configure DMA source address (peripheral address),
1351 * use function @ref LL_DAC_DMA_GetRegAddr().
1352 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1353 * CR DMAEN2 LL_DAC_DisableDMAReq
1354 * @param DACx DAC instance
1355 * @param DAC_Channel This parameter can be one of the following values:
1356 * @arg @ref LL_DAC_CHANNEL_1
1357 * @arg @ref LL_DAC_CHANNEL_2
1358 * @retval None
1359 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1360 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1361 {
1362 CLEAR_BIT(DACx->CR,
1363 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1364 }
1365
1366 /**
1367 * @brief Get DAC DMA transfer request state of the selected channel.
1368 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1369 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1370 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1371 * @param DACx DAC instance
1372 * @param DAC_Channel This parameter can be one of the following values:
1373 * @arg @ref LL_DAC_CHANNEL_1
1374 * @arg @ref LL_DAC_CHANNEL_2
1375 * @retval State of bit (1 or 0).
1376 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1377 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1378 {
1379 return ((READ_BIT(DACx->CR,
1380 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1381 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1382 }
1383
1384 /**
1385 * @brief Enable DAC DMA Double data mode of the selected channel.
1386 * @rmtoll MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode\n
1387 * MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
1388 * @param DACx DAC instance
1389 * @param DAC_Channel This parameter can be one of the following values:
1390 * @arg @ref LL_DAC_CHANNEL_1
1391 * @arg @ref LL_DAC_CHANNEL_2
1392 * @retval None
1393 */
LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1394 __STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1395 {
1396 SET_BIT(DACx->MCR,
1397 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1398 }
1399
1400 /**
1401 * @brief Disable DAC DMA Double data mode of the selected channel.
1402 * @rmtoll MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode\n
1403 * MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
1404 * @param DACx DAC instance
1405 * @param DAC_Channel This parameter can be one of the following values:
1406 * @arg @ref LL_DAC_CHANNEL_1
1407 * @arg @ref LL_DAC_CHANNEL_2
1408 * @retval None
1409 */
LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1410 __STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1411 {
1412 CLEAR_BIT(DACx->MCR,
1413 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1414 }
1415
1416 /**
1417 * @brief Get DAC DMA double data mode state of the selected channel.
1418 * (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
1419 * @rmtoll MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled\n
1420 * MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
1421 * @param DACx DAC instance
1422 * @param DAC_Channel This parameter can be one of the following values:
1423 * @arg @ref LL_DAC_CHANNEL_1
1424 * @arg @ref LL_DAC_CHANNEL_2
1425 * @retval State of bit (1 or 0).
1426 */
LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1427 __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1428 {
1429 return ((READ_BIT(DACx->MCR,
1430 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1431 == (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1432 }
1433
1434 /**
1435 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1436 * DAC register address from DAC instance and a list of DAC registers
1437 * intended to be used (most commonly) with DMA transfer.
1438 * @note These DAC registers are data holding registers:
1439 * when DAC conversion is requested, DAC generates a DMA transfer
1440 * request to have data available in DAC data holding registers.
1441 * @note This macro is intended to be used with LL DMA driver, refer to
1442 * function "LL_DMA_ConfigAddresses()".
1443 * Example:
1444 * LL_DMA_ConfigAddresses(DMA1,
1445 * LL_DMA_CHANNEL_1,
1446 * (uint32_t)&< array or variable >,
1447 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1448 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1449 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1450 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1451 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1452 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1453 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1454 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1455 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1456 * @param DACx DAC instance
1457 * @param DAC_Channel This parameter can be one of the following values:
1458 * @arg @ref LL_DAC_CHANNEL_1
1459 * @arg @ref LL_DAC_CHANNEL_2
1460 * @param Register This parameter can be one of the following values:
1461 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1462 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1463 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1464 * @retval DAC register address
1465 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1466 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1467 {
1468 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1469 /* DAC channel selected. */
1470 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1471 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1472 }
1473 /**
1474 * @}
1475 */
1476
1477 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1478 * @{
1479 */
1480
1481 /**
1482 * @brief Enable DAC selected channel.
1483 * @rmtoll CR EN1 LL_DAC_Enable\n
1484 * CR EN2 LL_DAC_Enable
1485 * @note After enable from off state, DAC channel requires a delay
1486 * for output voltage to reach accuracy +/- 1 LSB.
1487 * Refer to device datasheet, parameter "tWAKEUP".
1488 * @param DACx DAC instance
1489 * @param DAC_Channel This parameter can be one of the following values:
1490 * @arg @ref LL_DAC_CHANNEL_1
1491 * @arg @ref LL_DAC_CHANNEL_2
1492 * @retval None
1493 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1494 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1495 {
1496 SET_BIT(DACx->CR,
1497 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1498 }
1499
1500 /**
1501 * @brief Disable DAC selected channel.
1502 * @rmtoll CR EN1 LL_DAC_Disable\n
1503 * CR EN2 LL_DAC_Disable
1504 * @param DACx DAC instance
1505 * @param DAC_Channel This parameter can be one of the following values:
1506 * @arg @ref LL_DAC_CHANNEL_1
1507 * @arg @ref LL_DAC_CHANNEL_2
1508 * @retval None
1509 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1510 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1511 {
1512 CLEAR_BIT(DACx->CR,
1513 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1514 }
1515
1516 /**
1517 * @brief Get DAC enable state of the selected channel.
1518 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1519 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1520 * CR EN2 LL_DAC_IsEnabled
1521 * @param DACx DAC instance
1522 * @param DAC_Channel This parameter can be one of the following values:
1523 * @arg @ref LL_DAC_CHANNEL_1
1524 * @arg @ref LL_DAC_CHANNEL_2
1525 * @retval State of bit (1 or 0).
1526 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1527 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1528 {
1529 return ((READ_BIT(DACx->CR,
1530 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1531 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1532 }
1533
1534 /**
1535 * @brief Get DAC ready for conversion state of the selected channel.
1536 * (0: DAC channel is not ready, 1: DAC channel is ready)
1537 * @rmtoll SR DAC1RDY LL_DAC_IsReady\n
1538 * SR DAC2RDY LL_DAC_IsReady
1539 * @param DACx DAC instance
1540 * @param DAC_Channel This parameter can be one of the following values:
1541 * @arg @ref LL_DAC_CHANNEL_1
1542 * @arg @ref LL_DAC_CHANNEL_2
1543 * @retval State of bit (1 or 0).
1544 */
LL_DAC_IsReady(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1545 __STATIC_INLINE uint32_t LL_DAC_IsReady(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1546 {
1547 return ((READ_BIT(DACx->SR,
1548 DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1549 == (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1550 }
1551
1552 /**
1553 * @brief Enable DAC trigger of the selected channel.
1554 * @note - If DAC trigger is disabled, DAC conversion is performed
1555 * automatically once the data holding register is updated,
1556 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1557 * @ref LL_DAC_ConvertData12RightAligned(), ...
1558 * - If DAC trigger is enabled, DAC conversion is performed
1559 * only when a hardware of software trigger event is occurring.
1560 * Select trigger source using
1561 * function @ref LL_DAC_SetTriggerSource().
1562 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1563 * CR TEN2 LL_DAC_EnableTrigger
1564 * @param DACx DAC instance
1565 * @param DAC_Channel This parameter can be one of the following values:
1566 * @arg @ref LL_DAC_CHANNEL_1
1567 * @arg @ref LL_DAC_CHANNEL_2
1568 * @retval None
1569 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1570 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1571 {
1572 SET_BIT(DACx->CR,
1573 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1574 }
1575
1576 /**
1577 * @brief Disable DAC trigger of the selected channel.
1578 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1579 * CR TEN2 LL_DAC_DisableTrigger
1580 * @param DACx DAC instance
1581 * @param DAC_Channel This parameter can be one of the following values:
1582 * @arg @ref LL_DAC_CHANNEL_1
1583 * @arg @ref LL_DAC_CHANNEL_2
1584 * @retval None
1585 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1586 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1587 {
1588 CLEAR_BIT(DACx->CR,
1589 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1590 }
1591
1592 /**
1593 * @brief Get DAC trigger state of the selected channel.
1594 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1595 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1596 * CR TEN2 LL_DAC_IsTriggerEnabled
1597 * @param DACx DAC instance
1598 * @param DAC_Channel This parameter can be one of the following values:
1599 * @arg @ref LL_DAC_CHANNEL_1
1600 * @arg @ref LL_DAC_CHANNEL_2
1601 * @retval State of bit (1 or 0).
1602 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1603 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1604 {
1605 return ((READ_BIT(DACx->CR,
1606 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1607 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1608 }
1609
1610 /**
1611 * @brief Trig DAC conversion by software for the selected DAC channel.
1612 * @note Preliminarily, DAC trigger must be set to software trigger
1613 * using function
1614 * @ref LL_DAC_Init()
1615 * @ref LL_DAC_SetTriggerSource()
1616 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1617 * and DAC trigger must be enabled using
1618 * function @ref LL_DAC_EnableTrigger().
1619 * @note For devices featuring DAC with 2 channels: this function
1620 * can perform a SW start of both DAC channels simultaneously.
1621 * Two channels can be selected as parameter.
1622 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1623 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1624 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1625 * @param DACx DAC instance
1626 * @param DAC_Channel This parameter can a combination of the following values:
1627 * @arg @ref LL_DAC_CHANNEL_1
1628 * @arg @ref LL_DAC_CHANNEL_2
1629 * @retval None
1630 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1631 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1632 {
1633 SET_BIT(DACx->SWTRIGR,
1634 (DAC_Channel & DAC_SWTR_CHX_MASK));
1635 }
1636
1637 /**
1638 * @brief Set the data to be loaded in the data holding register
1639 * in format 12 bits left alignment (LSB aligned on bit 0),
1640 * for the selected DAC channel.
1641 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1642 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1643 * @param DACx DAC instance
1644 * @param DAC_Channel This parameter can be one of the following values:
1645 * @arg @ref LL_DAC_CHANNEL_1
1646 * @arg @ref LL_DAC_CHANNEL_2
1647 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1648 * @retval None
1649 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1650 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1651 {
1652 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1653 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1654
1655 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1656 }
1657
1658 /**
1659 * @brief Set the data to be loaded in the data holding register
1660 * in format 12 bits left alignment (MSB aligned on bit 15),
1661 * for the selected DAC channel.
1662 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1663 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1664 * @param DACx DAC instance
1665 * @param DAC_Channel This parameter can be one of the following values:
1666 * @arg @ref LL_DAC_CHANNEL_1
1667 * @arg @ref LL_DAC_CHANNEL_2
1668 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1669 * @retval None
1670 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1671 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1672 {
1673 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1674 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1675
1676 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1677 }
1678
1679 /**
1680 * @brief Set the data to be loaded in the data holding register
1681 * in format 8 bits left alignment (LSB aligned on bit 0),
1682 * for the selected DAC channel.
1683 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1684 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1685 * @param DACx DAC instance
1686 * @param DAC_Channel This parameter can be one of the following values:
1687 * @arg @ref LL_DAC_CHANNEL_1
1688 * @arg @ref LL_DAC_CHANNEL_2
1689 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1690 * @retval None
1691 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1692 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1693 {
1694 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1695 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1696
1697 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1698 }
1699
1700
1701 /**
1702 * @brief Set the data to be loaded in the data holding register
1703 * in format 12 bits left alignment (LSB aligned on bit 0),
1704 * for both DAC channels.
1705 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1706 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1707 * @param DACx DAC instance
1708 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1709 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1710 * @retval None
1711 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1712 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1713 uint32_t DataChannel2)
1714 {
1715 MODIFY_REG(DACx->DHR12RD,
1716 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1717 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1718 }
1719
1720 /**
1721 * @brief Set the data to be loaded in the data holding register
1722 * in format 12 bits left alignment (MSB aligned on bit 15),
1723 * for both DAC channels.
1724 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1725 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1726 * @param DACx DAC instance
1727 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1728 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1729 * @retval None
1730 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1731 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1732 uint32_t DataChannel2)
1733 {
1734 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1735 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1736 /* the 4 LSB must be taken into account for the shift value. */
1737 MODIFY_REG(DACx->DHR12LD,
1738 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1739 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1740 }
1741
1742 /**
1743 * @brief Set the data to be loaded in the data holding register
1744 * in format 8 bits left alignment (LSB aligned on bit 0),
1745 * for both DAC channels.
1746 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1747 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1748 * @param DACx DAC instance
1749 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1750 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1751 * @retval None
1752 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1753 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1754 uint32_t DataChannel2)
1755 {
1756 MODIFY_REG(DACx->DHR8RD,
1757 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1758 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1759 }
1760
1761
1762 /**
1763 * @brief Retrieve output data currently generated for the selected DAC channel.
1764 * @note Whatever alignment and resolution settings
1765 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1766 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1767 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1768 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1769 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1770 * @param DACx DAC instance
1771 * @param DAC_Channel This parameter can be one of the following values:
1772 * @arg @ref LL_DAC_CHANNEL_1
1773 * @arg @ref LL_DAC_CHANNEL_2
1774 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1775 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1776 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1777 {
1778 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1779 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1780
1781 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1782 }
1783
1784 /**
1785 * @}
1786 */
1787
1788 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1789 * @{
1790 */
1791
1792 /**
1793 * @brief Get DAC calibration offset flag for DAC channel 1
1794 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1795 * @param DACx DAC instance
1796 * @retval State of bit (1 or 0).
1797 */
LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef * DACx)1798 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
1799 {
1800 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1801 }
1802
1803
1804 /**
1805 * @brief Get DAC calibration offset flag for DAC channel 2
1806 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1807 * @param DACx DAC instance
1808 * @retval State of bit (1 or 0).
1809 */
LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef * DACx)1810 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
1811 {
1812 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1813 }
1814
1815
1816 /**
1817 * @brief Get DAC busy writing sample time flag for DAC channel 1
1818 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1819 * @param DACx DAC instance
1820 * @retval State of bit (1 or 0).
1821 */
LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef * DACx)1822 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
1823 {
1824 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1825 }
1826
1827 /**
1828 * @brief Get DAC busy writing sample time flag for DAC channel 2
1829 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1830 * @param DACx DAC instance
1831 * @retval State of bit (1 or 0).
1832 */
LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef * DACx)1833 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
1834 {
1835 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1836 }
1837
1838
1839 /**
1840 * @brief Get DAC ready status flag for DAC channel 1
1841 * @rmtoll SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
1842 * @param DACx DAC instance
1843 * @retval State of bit (1 or 0).
1844 */
LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef * DACx)1845 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef *DACx)
1846 {
1847 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
1848 }
1849
1850
1851 /**
1852 * @brief Get DAC ready status flag for DAC channel 2
1853 * @rmtoll SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
1854 * @param DACx DAC instance
1855 * @retval State of bit (1 or 0).
1856 */
LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef * DACx)1857 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef *DACx)
1858 {
1859 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
1860 }
1861
1862
1863 /**
1864 * @brief Get DAC output register status flag for DAC channel 1
1865 * @rmtoll SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
1866 * @param DACx DAC instance
1867 * @retval State of bit (1 or 0).
1868 */
LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef * DACx)1869 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef *DACx)
1870 {
1871 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
1872 }
1873
1874
1875 /**
1876 * @brief Get DAC output register status flag for DAC channel 2
1877 * @rmtoll SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
1878 * @param DACx DAC instance
1879 * @retval State of bit (1 or 0).
1880 */
LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef * DACx)1881 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef *DACx)
1882 {
1883 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
1884 }
1885
1886 /**
1887 * @brief Get DAC underrun flag for DAC channel 1
1888 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1889 * @param DACx DAC instance
1890 * @retval State of bit (1 or 0).
1891 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1892 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1893 {
1894 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1895 }
1896
1897
1898 /**
1899 * @brief Get DAC underrun flag for DAC channel 2
1900 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1901 * @param DACx DAC instance
1902 * @retval State of bit (1 or 0).
1903 */
LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef * DACx)1904 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1905 {
1906 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1907 }
1908
1909
1910 /**
1911 * @brief Clear DAC underrun flag for DAC channel 1
1912 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1913 * @param DACx DAC instance
1914 * @retval None
1915 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1916 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1917 {
1918 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1919 }
1920
1921
1922 /**
1923 * @brief Clear DAC underrun flag for DAC channel 2
1924 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1925 * @param DACx DAC instance
1926 * @retval None
1927 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1928 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1929 {
1930 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1931 }
1932
1933
1934 /**
1935 * @}
1936 */
1937
1938 /** @defgroup DAC_LL_EF_IT_Management IT management
1939 * @{
1940 */
1941
1942 /**
1943 * @brief Enable DMA underrun interrupt for DAC channel 1
1944 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1945 * @param DACx DAC instance
1946 * @retval None
1947 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1948 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1949 {
1950 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1951 }
1952
1953
1954 /**
1955 * @brief Enable DMA underrun interrupt for DAC channel 2
1956 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1957 * @param DACx DAC instance
1958 * @retval None
1959 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1960 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1961 {
1962 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1963 }
1964
1965
1966 /**
1967 * @brief Disable DMA underrun interrupt for DAC channel 1
1968 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1969 * @param DACx DAC instance
1970 * @retval None
1971 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1972 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1973 {
1974 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1975 }
1976
1977
1978 /**
1979 * @brief Disable DMA underrun interrupt for DAC channel 2
1980 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1981 * @param DACx DAC instance
1982 * @retval None
1983 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1984 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1985 {
1986 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1987 }
1988
1989
1990 /**
1991 * @brief Get DMA underrun interrupt for DAC channel 1
1992 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1993 * @param DACx DAC instance
1994 * @retval State of bit (1 or 0).
1995 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1996 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1997 {
1998 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1999 }
2000
2001
2002 /**
2003 * @brief Get DMA underrun interrupt for DAC channel 2
2004 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
2005 * @param DACx DAC instance
2006 * @retval State of bit (1 or 0).
2007 */
LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef * DACx)2008 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
2009 {
2010 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
2011 }
2012
2013
2014 /**
2015 * @}
2016 */
2017
2018 #if defined(USE_FULL_LL_DRIVER)
2019 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
2020 * @{
2021 */
2022
2023 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
2024 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
2025 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
2026
2027 /**
2028 * @}
2029 */
2030 #endif /* USE_FULL_LL_DRIVER */
2031
2032 /**
2033 * @}
2034 */
2035
2036 /**
2037 * @}
2038 */
2039
2040 #endif /* DAC1 */
2041
2042 /**
2043 * @}
2044 */
2045
2046 #ifdef __cplusplus
2047 }
2048 #endif
2049
2050 #endif /* STM32H5xx_LL_DAC_H */
2051
