1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick with
25 HCLK source or @ref LL_Init1msTick_HCLK_Div8, @ref LL_Init1msTick_LSI or
26 @ref LL_Init1msTick_LSE with external source
27 functions
28 (+) Low power mode configuration (SCB register of Cortex-MCU)
29 (+) API to access to MCU info (CPUID register)
30 (+) API to enable fault handler (SHCSR accesses)
31 (+) API to enable and disable the MPU secure and non-secure
32 (+) API to configure the region of MPU secure and non-secure
33 (+) API to configure the attributes region of MPU secure and non-secure
34
35 @endverbatim
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef STM32H5xx_LL_CORTEX_H
40 #define STM32H5xx_LL_CORTEX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32h5xx.h"
48
49 /** @addtogroup STM32H5xx_LL_Driver
50 * @{
51 */
52
53 /** @defgroup CORTEX_LL CORTEX
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
61 * @{
62 */
63 /* Register MPU_RBAR (Cortex-M33) : bits [4:0] */
64 #define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
65 /**
66 * @}
67 */
68
69 /* Private macros ------------------------------------------------------------*/
70 /* Exported types ------------------------------------------------------------*/
71 /* Exported constants --------------------------------------------------------*/
72 /** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
73 * @{
74 */
75
76 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
77 * @{
78 */
79 #define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as SysTick
80 clock source */
81 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
82 clock source */
83 /** Legacy definitions for backward compatibility purpose
84 */
85 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL
86 /**
87 */
88 /**
89 * @}
90 */
91
92 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
93 * @{
94 */
95 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
96 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
97 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
98 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
99 /**
100 * @}
101 */
102
103 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
104 * @{
105 */
106 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
107 #define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
108 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
109 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
110 /**
111 * @}
112 */
113
114 /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
115 * @{
116 */
117 /* Device memory attributes */
118 #define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */
119 #define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */
120 #define LL_MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */
121 #define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */
122
123 /* Normal memory attributes */
124 /* Non-cacheable memory attribute */
125 #define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */
126
127 /* Cacheable memory attributes: combination of cache write policy, transient and allocation */
128 /* - cache write policy */
129 #define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */
130 #define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */
131 /* - transient mode attribute */
132 #define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */
133 #define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */
134 /* - allocation attribute */
135 #define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */
136 #define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */
137 #define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */
138 #define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */
139 /**
140 * @}
141 */
142
143 /** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
144 * @{
145 */
146 #define LL_MPU_REGION_ENABLE 1U /*!< MPU region enabled */
147 #define LL_MPU_REGION_DISABLE 0U /*!< MPU region disabled */
148 /**
149 * @}
150 */
151
152 /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
153 * @{
154 */
155 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */
156 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */
157 /**
158 * @}
159 */
160
161 /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
162 * @{
163 */
164 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */
165 #define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */
166 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */
167 /**
168 * @}
169 */
170
171 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
172 * @{
173 */
174 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */
175 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */
176 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */
177 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */
178 /**
179 * @}
180 */
181
182 /** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
183 * @{
184 */
185 #define LL_MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */
186 #define LL_MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */
187 #define LL_MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */
188 #define LL_MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */
189 #define LL_MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */
190 #define LL_MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */
191 #define LL_MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */
192 #define LL_MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */
193 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
194 #define LL_MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */
195 #define LL_MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */
196 #define LL_MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */
197 #define LL_MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */
198 #endif /* __ARM_FEATURE_CMSE */
199 /**
200 * @}
201 */
202
203 /** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
204 * @{
205 */
206 #define LL_MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */
207 #define LL_MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */
208 #define LL_MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */
209 #define LL_MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */
210 #define LL_MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */
211 #define LL_MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */
212 #define LL_MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */
213 #define LL_MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */
214 /**
215 * @}
216 */
217
218 /**
219 * @}
220 */
221
222 /* Exported macro ------------------------------------------------------------*/
223
224 /* Exported functions --------------------------------------------------------*/
225 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
226 * @{
227 */
228
229 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
230 * @brief CORTEX SYSTICK LL module driver
231 * @{
232 */
233
234 /**
235 * @brief This function checks if the Systick counter flag is active or not.
236 * @note It can be used in timeout function on application side.
237 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
238 * @retval State of bit (1 or 0).
239 */
LL_SYSTICK_IsActiveCounterFlag(void)240 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
241 {
242 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
243 }
244
245 /**
246 * @brief Configures the SysTick clock source
247 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
248 * @param Source This parameter can be one of the following values:
249 * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL
250 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
251 * @retval None
252 */
LL_SYSTICK_SetClkSource(uint32_t Source)253 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
254 {
255 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
256 {
257 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
258 }
259 else
260 {
261 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
262 }
263 }
264
265 /**
266 * @brief Get the SysTick clock source
267 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
268 * @retval Returned value can be one of the following values:
269 * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL
270 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
271 */
LL_SYSTICK_GetClkSource(void)272 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
273 {
274 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
275 }
276
277 /**
278 * @brief Enable SysTick exception request
279 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
280 * @retval None
281 */
LL_SYSTICK_EnableIT(void)282 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
283 {
284 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
285 }
286
287 /**
288 * @brief Disable SysTick exception request
289 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
290 * @retval None
291 */
LL_SYSTICK_DisableIT(void)292 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
293 {
294 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
295 }
296
297 /**
298 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
299 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
300 * @retval State of bit (1 or 0).
301 */
LL_SYSTICK_IsEnabledIT(void)302 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
303 {
304 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
305 }
306
307 /**
308 * @}
309 */
310
311 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
312 * @{
313 */
314
315 /**
316 * @brief Processor uses sleep as its low power mode
317 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
318 * @retval None
319 */
LL_LPM_EnableSleep(void)320 __STATIC_INLINE void LL_LPM_EnableSleep(void)
321 {
322 /* Clear SLEEPDEEP bit of Cortex System Control Register */
323 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
324 }
325
326 /**
327 * @brief Processor uses deep sleep as its low power mode
328 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
329 * @retval None
330 */
LL_LPM_EnableDeepSleep(void)331 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
332 {
333 /* Set SLEEPDEEP bit of Cortex System Control Register */
334 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
335 }
336
337 /**
338 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
339 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
340 * empty main application.
341 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
342 * @retval None
343 */
LL_LPM_EnableSleepOnExit(void)344 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
345 {
346 /* Set SLEEPONEXIT bit of Cortex System Control Register */
347 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
348 }
349
350 /**
351 * @brief Do not sleep when returning to Thread mode.
352 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
353 * @retval None
354 */
LL_LPM_DisableSleepOnExit(void)355 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
356 {
357 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
358 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
359 }
360
361 /**
362 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
363 * processor.
364 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
365 * @retval None
366 */
LL_LPM_EnableEventOnPend(void)367 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
368 {
369 /* Set SEVEONPEND bit of Cortex System Control Register */
370 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
371 }
372
373 /**
374 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
375 * excluded
376 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
377 * @retval None
378 */
LL_LPM_DisableEventOnPend(void)379 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
380 {
381 /* Clear SEVEONPEND bit of Cortex System Control Register */
382 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
383 }
384
385 /**
386 * @}
387 */
388
389 /** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
390 * @{
391 */
392
393 /**
394 * @brief Enable a fault in System handler control register (SHCSR)
395 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
396 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
397 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
398 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
399 * @param Fault This parameter can be a combination of the following values:
400 * @arg @ref LL_HANDLER_FAULT_USG
401 * @arg @ref LL_HANDLER_FAULT_BUS
402 * @arg @ref LL_HANDLER_FAULT_MEM
403 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
404 *
405 * (*) value applicable in secure when the system implements the security.
406 * @retval None
407 */
LL_HANDLER_EnableFault(uint32_t Fault)408 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
409 {
410 /* Enable the system handler fault */
411 SET_BIT(SCB->SHCSR, Fault);
412 }
413
414 /**
415 * @brief Disable a fault in System handler control register (SHCSR)
416 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
417 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
418 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
419 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
420 * @param Fault This parameter can be a combination of the following values:
421 * @arg @ref LL_HANDLER_FAULT_USG
422 * @arg @ref LL_HANDLER_FAULT_BUS
423 * @arg @ref LL_HANDLER_FAULT_MEM
424 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
425 *
426 * (*) value applicable in secure when the system implements the security.
427 * @retval None
428 */
LL_HANDLER_DisableFault(uint32_t Fault)429 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
430 {
431 /* Disable the system handler fault */
432 CLEAR_BIT(SCB->SHCSR, Fault);
433 }
434
435 /**
436 * @}
437 */
438
439 /** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
440 * @{
441 */
442
443 /**
444 * @brief Get Implementer code
445 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
446 * @retval Value should be equal to 0x41 for ARM
447 */
LL_CPUID_GetImplementer(void)448 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
449 {
450 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
451 }
452
453 /**
454 * @brief Get Variant number (The r value in the rnpn product revision identifier)
455 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
456 * @retval Value between 0 and 255 (0x0: revision 0)
457 */
LL_CPUID_GetVariant(void)458 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
459 {
460 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
461 }
462
463 /**
464 * @brief Get Architecture version
465 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
466 * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension")
467 */
LL_CPUID_GetArchitecture(void)468 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
469 {
470 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
471 }
472
473 /**
474 * @brief Get Part number
475 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
476 * @retval Value should be equal to 0xD21 for Cortex-M33
477 */
LL_CPUID_GetParNo(void)478 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
479 {
480 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
481 }
482
483 /**
484 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
485 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
486 * @retval Value between 0 and 255 (0x1: patch 1)
487 */
LL_CPUID_GetRevision(void)488 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
489 {
490 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
491 }
492
493 /**
494 * @}
495 */
496
497 /** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
498 * @{
499 */
500
501 /**
502 * @brief Enable MPU with input options
503 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
504 * @param MPU_Control This parameter can be one of the following values:
505 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
506 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
507 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
508 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
509 * @retval None
510 */
LL_MPU_Enable(uint32_t MPU_Control)511 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
512 {
513 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
514
515 /* Enable the MPU*/
516 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
517
518 /* Follow ARM recommendation with */
519 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
520 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
521 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
522 }
523
524 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
525 /**
526 * @brief Enable non-secure MPU with input options
527 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
528 * @param MPU_Control This parameter can be one of the following values:
529 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
530 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
531 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
532 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
533 * @retval None
534 */
LL_MPU_Enable_NS(uint32_t MPU_Control)535 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
536 {
537 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
538
539 /* Enable the MPU*/
540 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
541
542 /* Follow ARM recommendation with */
543 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
544 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
545 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
546 }
547 #endif /* __ARM_FEATURE_CMSE */
548
549 /**
550 * @brief Disable MPU
551 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
552 * @retval None
553 */
LL_MPU_Disable(void)554 __STATIC_INLINE void LL_MPU_Disable(void)
555 {
556 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
557
558 /* Disable MPU */
559 WRITE_REG(MPU->CTRL, 0U);
560
561 /* Follow ARM recommendation with */
562 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
563 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
564 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
565 }
566
567 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
568 /**
569 * @brief Disable the non-secure MPU
570 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
571 * @retval None
572 */
LL_MPU_Disable_NS(void)573 __STATIC_INLINE void LL_MPU_Disable_NS(void)
574 {
575 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
576
577 /* Disable MPU*/
578 WRITE_REG(MPU_NS->CTRL, 0U);
579
580 /* Follow ARM recommendation with */
581 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
582 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
583 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
584 }
585 #endif /* __ARM_FEATURE_CMSE */
586
587
588 /**
589 * @brief Check if MPU is enabled or not
590 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
591 * @retval State of bit (1 or 0).
592 */
LL_MPU_IsEnabled(void)593 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
594 {
595 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
596 }
597
598 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
599 /**
600 * @brief Check if non-secure MPU is enabled or not
601 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
602 * @retval State of bit (1 or 0).
603 */
LL_MPU_IsEnabled_NS(void)604 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
605 {
606 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
607 }
608 #endif /* __ARM_FEATURE_CMSE */
609
610 /**
611 * @brief Enable a MPU region
612 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion
613 * @param Region This parameter can be one of the following values:
614 * @arg @ref LL_MPU_REGION_NUMBER0
615 * @arg @ref LL_MPU_REGION_NUMBER1
616 * @arg @ref LL_MPU_REGION_NUMBER2
617 * @arg @ref LL_MPU_REGION_NUMBER3
618 * @arg @ref LL_MPU_REGION_NUMBER4
619 * @arg @ref LL_MPU_REGION_NUMBER5
620 * @arg @ref LL_MPU_REGION_NUMBER6
621 * @arg @ref LL_MPU_REGION_NUMBER7
622 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
623 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
624 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
625 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
626 * @note cortex-M33 supports 12 secure and 8 non secure regions.
627 * (*) : For MPU_S only
628 * @retval None
629 */
LL_MPU_EnableRegion(uint32_t Region)630 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
631 {
632 /* Set Region number */
633 WRITE_REG(MPU->RNR, Region);
634
635 /* Enable the MPU region */
636 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
637 }
638
639 /**
640 * @brief Check if MPU region is enabled or not
641 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region
642 * @param Region This parameter can be one of the following values:
643 * @arg @ref LL_MPU_REGION_NUMBER0
644 * @arg @ref LL_MPU_REGION_NUMBER1
645 * @arg @ref LL_MPU_REGION_NUMBER2
646 * @arg @ref LL_MPU_REGION_NUMBER3
647 * @arg @ref LL_MPU_REGION_NUMBER4
648 * @arg @ref LL_MPU_REGION_NUMBER5
649 * @arg @ref LL_MPU_REGION_NUMBER6
650 * @arg @ref LL_MPU_REGION_NUMBER7
651 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
652 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
653 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
654 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
655 * @note cortex-M33 supports 12 secure and 8 non secure regions.
656 * (*) : For MPU_S only
657 * @retval State of bit (1 or 0).
658 */
LL_MPU_IsEnabled_Region(uint32_t Region)659 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
660 {
661 /* Set region index */
662 WRITE_REG(MPU->RNR, Region);
663
664 /* Return MPU region status */
665 return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
666 }
667
668 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
669 /**
670 * @brief Enable a non-secure MPU region
671 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS
672 * @param Region This parameter can be one of the following values:
673 * @arg @ref LL_MPU_REGION_NUMBER0
674 * @arg @ref LL_MPU_REGION_NUMBER1
675 * @arg @ref LL_MPU_REGION_NUMBER2
676 * @arg @ref LL_MPU_REGION_NUMBER3
677 * @arg @ref LL_MPU_REGION_NUMBER4
678 * @arg @ref LL_MPU_REGION_NUMBER5
679 * @arg @ref LL_MPU_REGION_NUMBER6
680 * @arg @ref LL_MPU_REGION_NUMBER7
681 * @note cortex-M33 supports 8 non secure regions.
682 * @retval None
683 */
LL_MPU_EnableRegion_NS(uint32_t Region)684 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
685 {
686 /* Set Region number */
687 WRITE_REG(MPU_NS->RNR, Region);
688
689 /* Enable the MPU region */
690 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
691 }
692
693 /**
694 * @brief Check if non-secure MPU region is enabled or not
695 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS
696 * @param Region This parameter can be one of the following values:
697 * @arg @ref LL_MPU_REGION_NUMBER0
698 * @arg @ref LL_MPU_REGION_NUMBER1
699 * @arg @ref LL_MPU_REGION_NUMBER2
700 * @arg @ref LL_MPU_REGION_NUMBER3
701 * @arg @ref LL_MPU_REGION_NUMBER4
702 * @arg @ref LL_MPU_REGION_NUMBER5
703 * @arg @ref LL_MPU_REGION_NUMBER6
704 * @arg @ref LL_MPU_REGION_NUMBER7
705 * @note cortex-M33 supports 8 non secure regions.
706 * @retval State of bit (1 or 0).
707 */
LL_MPU_IsEnabled_Region_NS(uint32_t Region)708 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region)
709 {
710 /* Set region index */
711 WRITE_REG(MPU_NS->RNR, Region);
712
713 /* Return non-secure MPU region status */
714 return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
715 }
716 #endif /* __ARM_FEATURE_CMSE */
717
718 /**
719 * @brief Disable a MPU region
720 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
721 * MPU_RLAR ENABLE LL_MPU_DisableRegion
722 * @param Region This parameter can be one of the following values:
723 * @arg @ref LL_MPU_REGION_NUMBER0
724 * @arg @ref LL_MPU_REGION_NUMBER1
725 * @arg @ref LL_MPU_REGION_NUMBER2
726 * @arg @ref LL_MPU_REGION_NUMBER3
727 * @arg @ref LL_MPU_REGION_NUMBER4
728 * @arg @ref LL_MPU_REGION_NUMBER5
729 * @arg @ref LL_MPU_REGION_NUMBER6
730 * @arg @ref LL_MPU_REGION_NUMBER7
731 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
732 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
733 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
734 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
735 * @note cortex-M33 supports 12 secure and 8 non secure regions.
736 * (*) : For MPU_S only
737 * @retval None
738 */
LL_MPU_DisableRegion(uint32_t Region)739 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
740 {
741 /* Set Region number */
742 WRITE_REG(MPU->RNR, Region);
743
744 /* Disable the MPU region */
745 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
746 }
747
748 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
749 /**
750 * @brief Disable a non-secure MPU region
751 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
752 * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n
753 * @param Region This parameter can be one of the following values:
754 * @arg @ref LL_MPU_REGION_NUMBER0
755 * @arg @ref LL_MPU_REGION_NUMBER1
756 * @arg @ref LL_MPU_REGION_NUMBER2
757 * @arg @ref LL_MPU_REGION_NUMBER3
758 * @arg @ref LL_MPU_REGION_NUMBER4
759 * @arg @ref LL_MPU_REGION_NUMBER5
760 * @arg @ref LL_MPU_REGION_NUMBER6
761 * @arg @ref LL_MPU_REGION_NUMBER7
762 * @note cortex-M33 supports 8 non secure regions.
763 * @retval None
764 */
LL_MPU_DisableRegion_NS(uint32_t Region)765 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
766 {
767 /* Set Region number */
768 WRITE_REG(MPU_NS->RNR, Region);
769
770 /* Disable the MPU region */
771 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
772 }
773 #endif /* __ARM_FEATURE_CMSE */
774
775 /**
776 * @brief Configure and enable a MPU region
777 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
778 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
779 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
780 * MPU_RBAR XN LL_MPU_ConfigRegion\n
781 * MPU_RBAR AP LL_MPU_ConfigRegion\n
782 * MPU_RBAR SH LL_MPU_ConfigRegion\n
783 * MPU_RLAR EN LL_MPU_ConfigRegion\n
784 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n
785 * @param Region This parameter can be one of the following values:
786 * @arg @ref LL_MPU_REGION_NUMBER0
787 * @arg @ref LL_MPU_REGION_NUMBER1
788 * @arg @ref LL_MPU_REGION_NUMBER2
789 * @arg @ref LL_MPU_REGION_NUMBER3
790 * @arg @ref LL_MPU_REGION_NUMBER4
791 * @arg @ref LL_MPU_REGION_NUMBER5
792 * @arg @ref LL_MPU_REGION_NUMBER6
793 * @arg @ref LL_MPU_REGION_NUMBER7
794 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
795 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
796 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
797 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
798 * @param Attributes This parameter can be a combination of the following values:
799 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
800 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
801 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
802 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
803 * or @ref LL_MPU_REGION_ALL_RO
804 * @param AttrIndx This parameter can be one of the following values:
805 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
806 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
807 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
808 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
809 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
810 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
811 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
812 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
813 * @param BaseAddress Value of region base address
814 * @param LimitAddress Value of region limit address
815 * @note cortex-M33 supports 12 secure and 8 non secure regions.
816 * (*) : For MPU_S only
817 * @retval None
818 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)819 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
820 uint32_t LimitAddress)
821 {
822 /* Set region index */
823 WRITE_REG(MPU->RNR, Region);
824
825 /* Set region base address and region access attributes */
826 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
827
828 /* Set region limit address, memory attributes index and enable region */
829 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
830 }
831
832 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
833 /**
834 * @brief Configure and enable a non-secure MPU region
835 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
836 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
837 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
838 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
839 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
840 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
841 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
842 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n
843 * @param Region This parameter can be one of the following values:
844 * @arg @ref LL_MPU_REGION_NUMBER0
845 * @arg @ref LL_MPU_REGION_NUMBER1
846 * @arg @ref LL_MPU_REGION_NUMBER2
847 * @arg @ref LL_MPU_REGION_NUMBER3
848 * @arg @ref LL_MPU_REGION_NUMBER4
849 * @arg @ref LL_MPU_REGION_NUMBER5
850 * @arg @ref LL_MPU_REGION_NUMBER6
851 * @arg @ref LL_MPU_REGION_NUMBER7
852 * @param Attributes This parameter can be a combination of the following values:
853 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
854 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
855 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
856 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
857 * or @ref LL_MPU_REGION_ALL_RO
858 * @param AttrIndx This parameter can be one of the following values:
859 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
860 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
861 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
862 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
863 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
864 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
865 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
866 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
867 * @param BaseAddress Value of region base address
868 * @param LimitAddress Value of region limit address
869 * @note cortex-M33 supports 12 secure and 8 non secure regions.
870 * @retval None
871 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)872 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
873 uint32_t BaseAddress, uint32_t LimitAddress)
874 {
875 /* Set Region number */
876 WRITE_REG(MPU_NS->RNR, Region);
877
878 /* Set region base address and region access attributes */
879 WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
880
881 /* Set region limit address, memory attributes index and enable region */
882 WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
883 }
884 #endif /* __ARM_FEATURE_CMSE */
885
886 /**
887 * @brief Configure a MPU region address range
888 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
889 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
890 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
891 * @param Region This parameter can be one of the following values:
892 * @arg @ref LL_MPU_REGION_NUMBER0
893 * @arg @ref LL_MPU_REGION_NUMBER1
894 * @arg @ref LL_MPU_REGION_NUMBER2
895 * @arg @ref LL_MPU_REGION_NUMBER3
896 * @arg @ref LL_MPU_REGION_NUMBER4
897 * @arg @ref LL_MPU_REGION_NUMBER5
898 * @arg @ref LL_MPU_REGION_NUMBER6
899 * @arg @ref LL_MPU_REGION_NUMBER7
900 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
901 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
902 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
903 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
904 * @param BaseAddress Value of region base address
905 * @param LimitAddress Value of region limit address
906 * @note cortex-M33 supports 12 secure and 8 non secure regions.
907 * (*) : For MPU_S only
908 * @retval None
909 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)910 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
911 {
912 /* Set Region number */
913 WRITE_REG(MPU->RNR, Region);
914
915 /* Modify region base address */
916 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
917
918 /* Modify region limit address */
919 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
920 }
921
922 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
923 /**
924 * @brief Configure a non-secure MPU region address range
925 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
926 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
927 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
928 * @param Region This parameter can be one of the following values:
929 * @arg @ref LL_MPU_REGION_NUMBER0
930 * @arg @ref LL_MPU_REGION_NUMBER1
931 * @arg @ref LL_MPU_REGION_NUMBER2
932 * @arg @ref LL_MPU_REGION_NUMBER3
933 * @arg @ref LL_MPU_REGION_NUMBER4
934 * @arg @ref LL_MPU_REGION_NUMBER5
935 * @arg @ref LL_MPU_REGION_NUMBER6
936 * @arg @ref LL_MPU_REGION_NUMBER7
937 * @param BaseAddress Value of region base address
938 * @param LimitAddress Value of region limit address
939 * @note cortex-M33 supports 12 secure and 8 non secure regions.
940 * @retval None
941 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)942 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
943 {
944 /* Set Region number */
945 WRITE_REG(MPU_NS->RNR, Region);
946
947 /* Set base address */
948 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
949
950 /* Set limit address */
951 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
952 }
953 #endif /* __ARM_FEATURE_CMSE */
954
955 /**
956 * @brief Configure a MPU attributes index
957 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n
958 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n
959 * @param AttIndex This parameter can be one of the following values:
960 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
961 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
962 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
963 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
964 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
965 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
966 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
967 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
968 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
969 * @retval None
970 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)971 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
972 {
973 /* When selected index is in range [0;3] */
974 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
975 {
976 /* Modify Attr<i> field of MPU_MAIR0 accordingly */
977 MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
978 }
979 /* When selected index is in range [4;7] */
980 else
981 {
982 /* Modify Attr<i> field of MPU_MAIR1 accordingly */
983 MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
984 }
985 }
986
987 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
988 /**
989 * @brief Configure a non-secure MPU attributes index
990 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n
991 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n
992 * @param AttIndex This parameter can be one of the following values:
993 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
994 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
995 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
996 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
997 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
998 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
999 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
1000 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
1001 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
1002 * @retval None
1003 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)1004 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
1005 {
1006 /* When selected index is in range [0;3] */
1007 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
1008 {
1009 /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
1010 MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
1011 }
1012 /* When selected index is in range [4;7] */
1013 else
1014 {
1015 /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
1016 MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
1017 }
1018 }
1019 #endif /* __ARM_FEATURE_CMSE */
1020
1021 /**
1022 * @brief Configure a MPU region limit address
1023 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
1024 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n
1025 * @param Region This parameter can be one of the following values:
1026 * @arg @ref LL_MPU_REGION_NUMBER0
1027 * @arg @ref LL_MPU_REGION_NUMBER1
1028 * @arg @ref LL_MPU_REGION_NUMBER2
1029 * @arg @ref LL_MPU_REGION_NUMBER3
1030 * @arg @ref LL_MPU_REGION_NUMBER4
1031 * @arg @ref LL_MPU_REGION_NUMBER5
1032 * @arg @ref LL_MPU_REGION_NUMBER6
1033 * @arg @ref LL_MPU_REGION_NUMBER7
1034 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1035 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1036 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1037 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1038 * @param LimitAddress Value of region limit address
1039 * @note cortex-M33 supports 12 secure and 8 non secure regions.
1040 * (*) : For MPU_S only
1041 * @retval None
1042 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)1043 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
1044 {
1045 /* Set Region number */
1046 WRITE_REG(MPU->RNR, Region);
1047
1048 /* Set limit address */
1049 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1050 }
1051
1052 /**
1053 * @brief Get a MPU region limit address
1054 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
1055 * @param Region This parameter can be one of the following values:
1056 * @arg @ref LL_MPU_REGION_NUMBER0
1057 * @arg @ref LL_MPU_REGION_NUMBER1
1058 * @arg @ref LL_MPU_REGION_NUMBER2
1059 * @arg @ref LL_MPU_REGION_NUMBER3
1060 * @arg @ref LL_MPU_REGION_NUMBER4
1061 * @arg @ref LL_MPU_REGION_NUMBER5
1062 * @arg @ref LL_MPU_REGION_NUMBER6
1063 * @arg @ref LL_MPU_REGION_NUMBER7
1064 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1065 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1066 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1067 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1068 * (*) : For MPU_S only
1069 * @retval Value of the region limit address
1070 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)1071 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
1072 {
1073 /* Set Region number */
1074 WRITE_REG(MPU->RNR, Region);
1075 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
1076 }
1077
1078 /**
1079 * @brief Configure a MPU region base address
1080 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
1081 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n
1082 * @param Region This parameter can be one of the following values:
1083 * @arg @ref LL_MPU_REGION_NUMBER0
1084 * @arg @ref LL_MPU_REGION_NUMBER1
1085 * @arg @ref LL_MPU_REGION_NUMBER2
1086 * @arg @ref LL_MPU_REGION_NUMBER3
1087 * @arg @ref LL_MPU_REGION_NUMBER4
1088 * @arg @ref LL_MPU_REGION_NUMBER5
1089 * @arg @ref LL_MPU_REGION_NUMBER6
1090 * @arg @ref LL_MPU_REGION_NUMBER7
1091 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1092 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1093 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1094 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1095 * @param BaseAddress Value of region base address
1096 * @note cortex-M33 supports 12 secure and 8 non secure regions.
1097 * (*) : For MPU_S only
1098 * @retval None
1099 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)1100 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
1101 {
1102 /* Set Region number */
1103 WRITE_REG(MPU->RNR, Region);
1104 /* Set base address */
1105 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1106 }
1107
1108 /**
1109 * @brief Get a MPU region base address
1110 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
1111 * @param Region This parameter can be one of the following values:
1112 * @arg @ref LL_MPU_REGION_NUMBER0
1113 * @arg @ref LL_MPU_REGION_NUMBER1
1114 * @arg @ref LL_MPU_REGION_NUMBER2
1115 * @arg @ref LL_MPU_REGION_NUMBER3
1116 * @arg @ref LL_MPU_REGION_NUMBER4
1117 * @arg @ref LL_MPU_REGION_NUMBER5
1118 * @arg @ref LL_MPU_REGION_NUMBER6
1119 * @arg @ref LL_MPU_REGION_NUMBER7
1120 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1121 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1122 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1123 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1124 * @note cortex-M33 supports 12 secure and 8 non secure regions.
1125 * (*) : For MPU_S only
1126 * @retval Value of the region base address
1127 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)1128 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
1129 {
1130 /* Set Region number */
1131 WRITE_REG(MPU->RNR, Region);
1132 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
1133 }
1134
1135 /**
1136 * @brief Configure a MPU region access attributes and enable a region
1137 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
1138 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
1139 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
1140 * MPU_RBAR SH LL_MPU_SetRegionAccess\n
1141 * @param Region This parameter can be one of the following values:
1142 * @arg @ref LL_MPU_REGION_NUMBER0
1143 * @arg @ref LL_MPU_REGION_NUMBER1
1144 * @arg @ref LL_MPU_REGION_NUMBER2
1145 * @arg @ref LL_MPU_REGION_NUMBER3
1146 * @arg @ref LL_MPU_REGION_NUMBER4
1147 * @arg @ref LL_MPU_REGION_NUMBER5
1148 * @arg @ref LL_MPU_REGION_NUMBER6
1149 * @arg @ref LL_MPU_REGION_NUMBER7
1150 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1151 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1152 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1153 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1154 * @param Attributes This parameter can be a combination of the following values:
1155 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1156 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1157 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1158 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1159 * or @ref LL_MPU_REGION_ALL_RO
1160 * @note cortex-M33 supports 12 secure and 8 non secure regions.
1161 * (*) : For MPU_S only
1162 * @retval None
1163 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)1164 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
1165 {
1166 /* Set Region number */
1167 WRITE_REG(MPU->RNR, Region);
1168
1169 /* Set base address */
1170 MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1171 }
1172
1173 /**
1174 * @brief Get a MPU region access attributes
1175 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
1176 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
1177 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
1178 * MPU_RBAR SH LL_MPU_GetRegionAccess\n
1179 * @param Region This parameter can be one of the following values:
1180 * @arg @ref LL_MPU_REGION_NUMBER0
1181 * @arg @ref LL_MPU_REGION_NUMBER1
1182 * @arg @ref LL_MPU_REGION_NUMBER2
1183 * @arg @ref LL_MPU_REGION_NUMBER3
1184 * @arg @ref LL_MPU_REGION_NUMBER4
1185 * @arg @ref LL_MPU_REGION_NUMBER5
1186 * @arg @ref LL_MPU_REGION_NUMBER6
1187 * @arg @ref LL_MPU_REGION_NUMBER7
1188 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1189 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1190 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1191 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1192 * (*) : For MPU_S only
1193 * @retval return a combination of the following values:
1194 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1195 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1196 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1197 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1198 * or @ref LL_MPU_REGION_ALL_RO
1199 */
LL_MPU_GetRegionAccess(uint32_t Region)1200 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
1201 {
1202 /* Set Region number */
1203 WRITE_REG(MPU->RNR, Region);
1204 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1205 }
1206
1207 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1208 /**
1209 * @brief Configure a non-secure MPU region limit address
1210 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1211 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n
1212 * @param Region This parameter can be one of the following values:
1213 * @arg @ref LL_MPU_REGION_NUMBER0
1214 * @arg @ref LL_MPU_REGION_NUMBER1
1215 * @arg @ref LL_MPU_REGION_NUMBER2
1216 * @arg @ref LL_MPU_REGION_NUMBER3
1217 * @arg @ref LL_MPU_REGION_NUMBER4
1218 * @arg @ref LL_MPU_REGION_NUMBER5
1219 * @arg @ref LL_MPU_REGION_NUMBER6
1220 * @arg @ref LL_MPU_REGION_NUMBER7
1221 * @param LimitAddress Value of region limit address
1222 * @note cortex-M33 supports 8 non secure regions.
1223 * @retval None
1224 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1225 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1226 {
1227 /* Set Region number */
1228 WRITE_REG(MPU_NS->RNR, Region);
1229
1230 /* Set limit address */
1231 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1232 }
1233
1234 /**
1235 * @brief Get a non-secure MPU region limit address
1236 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1237 * @param Region This parameter can be one of the following values:
1238 * @arg @ref LL_MPU_REGION_NUMBER0
1239 * @arg @ref LL_MPU_REGION_NUMBER1
1240 * @arg @ref LL_MPU_REGION_NUMBER2
1241 * @arg @ref LL_MPU_REGION_NUMBER3
1242 * @arg @ref LL_MPU_REGION_NUMBER4
1243 * @arg @ref LL_MPU_REGION_NUMBER5
1244 * @arg @ref LL_MPU_REGION_NUMBER6
1245 * @arg @ref LL_MPU_REGION_NUMBER7
1246 * @retval Value of the region limit address.
1247 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1248 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1249 {
1250 /* Set Region number */
1251 WRITE_REG(MPU_NS->RNR, Region);
1252 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1253 }
1254
1255 /**
1256 * @brief Configure a non-secure MPU region base address
1257 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1258 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n
1259 * @param Region This parameter can be one of the following values:
1260 * @arg @ref LL_MPU_REGION_NUMBER0
1261 * @arg @ref LL_MPU_REGION_NUMBER1
1262 * @arg @ref LL_MPU_REGION_NUMBER2
1263 * @arg @ref LL_MPU_REGION_NUMBER3
1264 * @arg @ref LL_MPU_REGION_NUMBER4
1265 * @arg @ref LL_MPU_REGION_NUMBER5
1266 * @arg @ref LL_MPU_REGION_NUMBER6
1267 * @arg @ref LL_MPU_REGION_NUMBER7
1268 * @param BaseAddress Value of region base address
1269 * @note cortex-M33 supports 8 non secure regions.
1270 * @retval None
1271 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1272 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1273 {
1274 /* Set Region number */
1275 WRITE_REG(MPU_NS->RNR, Region);
1276
1277 /* Set base address */
1278 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1279 }
1280
1281 /**
1282 * @brief Get a non-secure MPU region base address
1283 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1284 * @param Region This parameter can be one of the following values:
1285 * @arg @ref LL_MPU_REGION_NUMBER0
1286 * @arg @ref LL_MPU_REGION_NUMBER1
1287 * @arg @ref LL_MPU_REGION_NUMBER2
1288 * @arg @ref LL_MPU_REGION_NUMBER3
1289 * @arg @ref LL_MPU_REGION_NUMBER4
1290 * @arg @ref LL_MPU_REGION_NUMBER5
1291 * @arg @ref LL_MPU_REGION_NUMBER6
1292 * @arg @ref LL_MPU_REGION_NUMBER7
1293 * @retval Value of the region base address.
1294 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1295 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1296 {
1297 /* Set Region number */
1298 WRITE_REG(MPU_NS->RNR, Region);
1299
1300 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1301 }
1302
1303 /**
1304 * @brief Configure a non-secure MPU region access attributes and enable a region
1305 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1306 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1307 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1308 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n
1309 * @param Region This parameter can be one of the following values:
1310 * @arg @ref LL_MPU_REGION_NUMBER0
1311 * @arg @ref LL_MPU_REGION_NUMBER1
1312 * @arg @ref LL_MPU_REGION_NUMBER2
1313 * @arg @ref LL_MPU_REGION_NUMBER3
1314 * @arg @ref LL_MPU_REGION_NUMBER4
1315 * @arg @ref LL_MPU_REGION_NUMBER5
1316 * @arg @ref LL_MPU_REGION_NUMBER6
1317 * @arg @ref LL_MPU_REGION_NUMBER7
1318 * @param Attributes This parameter can be a combination of the following values:
1319 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1320 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1321 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1322 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1323 * or @ref LL_MPU_REGION_ALL_RO
1324 * @note cortex-M33 supports 8 non secure regions.
1325 * @retval None
1326 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1327 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1328 {
1329 /* Set Region number */
1330 WRITE_REG(MPU_NS->RNR, Region);
1331
1332 /* Set base address Attributes */
1333 MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1334 }
1335
1336 /**
1337 * @brief Get a non-secure MPU region access attributes
1338 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1339 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1340 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1341 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n
1342 * @param Region This parameter can be one of the following values:
1343 * @arg @ref LL_MPU_REGION_NUMBER0
1344 * @arg @ref LL_MPU_REGION_NUMBER1
1345 * @arg @ref LL_MPU_REGION_NUMBER2
1346 * @arg @ref LL_MPU_REGION_NUMBER3
1347 * @arg @ref LL_MPU_REGION_NUMBER4
1348 * @arg @ref LL_MPU_REGION_NUMBER5
1349 * @arg @ref LL_MPU_REGION_NUMBER6
1350 * @arg @ref LL_MPU_REGION_NUMBER7
1351 * @retval return a combination of the following values:
1352 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1353 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1354 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1355 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1356 * or @ref LL_MPU_REGION_ALL_RO
1357 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1358 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1359 {
1360 /* Set Region number */
1361 WRITE_REG(MPU_NS->RNR, Region);
1362
1363 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1364 }
1365 #endif /* __ARM_FEATURE_CMSE */
1366
1367 /**
1368 * @}
1369 */
1370
1371 /**
1372 * @}
1373 */
1374
1375 /**
1376 * @}
1377 */
1378
1379 /**
1380 * @}
1381 */
1382
1383 #ifdef __cplusplus
1384 }
1385 #endif
1386
1387 #endif /* STM32H5xx_LL_CORTEX_H */
1388
