1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) API to access to MCU info (CPUID register)
28 (+) API to enable fault handler (SHCSR accesses)
29 (+) API to enable and disable the MPU secure and non-secure
30 (+) API to configure the region of MPU secure and non-secure
31 (+) API to configure the attributes region of MPU secure and non-secure
32
33 @endverbatim
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32H5xx_LL_CORTEX_H
38 #define STM32H5xx_LL_CORTEX_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32h5xx.h"
46
47 /** @addtogroup STM32H5xx_LL_Driver
48 * @{
49 */
50
51 /** @defgroup CORTEX_LL CORTEX
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
59 * @{
60 */
61 /* Register MPU_RBAR (Cortex-M33) : bits [4:0] */
62 #define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
63 /**
64 * @}
65 */
66
67 /* Private macros ------------------------------------------------------------*/
68 /* Exported types ------------------------------------------------------------*/
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
71 * @{
72 */
73
74 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
75 * @{
76 */
77 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick
78 clock source */
79 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
80 clock source */
81 /**
82 * @}
83 */
84
85 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
86 * @{
87 */
88 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
89 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
90 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
91 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
92 /**
93 * @}
94 */
95
96 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
97 * @{
98 */
99 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers,
100 privileged software access to the default memory map is disabled */
101 #define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers,
102 privileged software access to the default memory map is disabled */
103 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers,
104 privileged software access to the default memory map is enabled */
105 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers,
106 privileged software access to the default memory map is enabled */
107 /**
108 * @}
109 */
110
111 /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
112 * @{
113 */
114 #define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */
115 #define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */
116 #define LL_MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */
117 #define LL_MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */
118
119 #define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */
120 #define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */
121 #define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */
122
123 #define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */
124 #define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */
125
126 #define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */
127 #define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */
128 #define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */
129 #define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */
130 /**
131 * @}
132 */
133
134 /** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
135 * @{
136 */
137 #define LL_MPU_REGION_ENABLE 1U /*!< MPU region enabled */
138 #define LL_MPU_REGION_DISABLE 0U /*!< MPU region disabled */
139 /**
140 * @}
141 */
142
143 /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
144 * @{
145 */
146 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< MPU region execution permitted
147 if read permitted */
148 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< MPU region execution not permitted */
149 /**
150 * @}
151 */
152
153 /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
154 * @{
155 */
156 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< MPU region not shareable */
157 #define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos) /*!< MPU region outer shareable */
158 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< MPU region inner shareable */
159 /**
160 * @}
161 */
162
163 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
164 * @{
165 */
166 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< MPU region Read/write by privileged code only */
167 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< MPU region Read/write by any privilege level */
168 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< MPU region Read-only by privileged code only */
169 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< MPU region Read-only by any privilege level */
170 /**
171 * @}
172 */
173
174 /** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
175 * @{
176 */
177 #define LL_MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */
178 #define LL_MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */
179 #define LL_MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */
180 #define LL_MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */
181 #define LL_MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */
182 #define LL_MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */
183 #define LL_MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */
184 #define LL_MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */
185 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
186 #define LL_MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */
187 #define LL_MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */
188 #define LL_MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */
189 #define LL_MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */
190 #endif /* __ARM_FEATURE_CMSE */
191 /**
192 * @}
193 */
194
195 /** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
196 * @{
197 */
198 #define LL_MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */
199 #define LL_MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */
200 #define LL_MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */
201 #define LL_MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */
202 #define LL_MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */
203 #define LL_MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */
204 #define LL_MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */
205 #define LL_MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */
206 /**
207 * @}
208 */
209
210 /**
211 * @}
212 */
213
214 /* Exported macro ------------------------------------------------------------*/
215
216 /* Exported functions --------------------------------------------------------*/
217 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
218 * @{
219 */
220
221 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
222 * @brief CORTEX SYSTICK LL module driver
223 * @{
224 */
225
226 /**
227 * @brief This function checks if the Systick counter flag is active or not.
228 * @note It can be used in timeout function on application side.
229 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
230 * @retval State of bit (1 or 0).
231 */
LL_SYSTICK_IsActiveCounterFlag(void)232 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
233 {
234 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
235 }
236
237 /**
238 * @brief Configures the SysTick clock source
239 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
240 * @param Source This parameter can be one of the following values:
241 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
242 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
243 * @retval None
244 */
LL_SYSTICK_SetClkSource(uint32_t Source)245 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
246 {
247 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
248 {
249 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
250 }
251 else
252 {
253 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
254 }
255 }
256
257 /**
258 * @brief Get the SysTick clock source
259 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
260 * @retval Returned value can be one of the following values:
261 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
262 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
263 */
LL_SYSTICK_GetClkSource(void)264 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
265 {
266 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
267 }
268
269 /**
270 * @brief Enable SysTick exception request
271 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
272 * @retval None
273 */
LL_SYSTICK_EnableIT(void)274 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
275 {
276 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
277 }
278
279 /**
280 * @brief Disable SysTick exception request
281 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
282 * @retval None
283 */
LL_SYSTICK_DisableIT(void)284 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
285 {
286 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
287 }
288
289 /**
290 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
291 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
292 * @retval State of bit (1 or 0).
293 */
LL_SYSTICK_IsEnabledIT(void)294 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
295 {
296 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
297 }
298
299 /**
300 * @}
301 */
302
303 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
304 * @{
305 */
306
307 /**
308 * @brief Processor uses sleep as its low power mode
309 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
310 * @retval None
311 */
LL_LPM_EnableSleep(void)312 __STATIC_INLINE void LL_LPM_EnableSleep(void)
313 {
314 /* Clear SLEEPDEEP bit of Cortex System Control Register */
315 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
316 }
317
318 /**
319 * @brief Processor uses deep sleep as its low power mode
320 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
321 * @retval None
322 */
LL_LPM_EnableDeepSleep(void)323 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
324 {
325 /* Set SLEEPDEEP bit of Cortex System Control Register */
326 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
327 }
328
329 /**
330 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
331 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
332 * empty main application.
333 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
334 * @retval None
335 */
LL_LPM_EnableSleepOnExit(void)336 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
337 {
338 /* Set SLEEPONEXIT bit of Cortex System Control Register */
339 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
340 }
341
342 /**
343 * @brief Do not sleep when returning to Thread mode.
344 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
345 * @retval None
346 */
LL_LPM_DisableSleepOnExit(void)347 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
348 {
349 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
350 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
351 }
352
353 /**
354 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
355 * processor.
356 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
357 * @retval None
358 */
LL_LPM_EnableEventOnPend(void)359 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
360 {
361 /* Set SEVEONPEND bit of Cortex System Control Register */
362 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
363 }
364
365 /**
366 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
367 * excluded
368 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
369 * @retval None
370 */
LL_LPM_DisableEventOnPend(void)371 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
372 {
373 /* Clear SEVEONPEND bit of Cortex System Control Register */
374 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
375 }
376
377 /**
378 * @}
379 */
380
381 /** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
382 * @{
383 */
384
385 /**
386 * @brief Enable a fault in System handler control register (SHCSR)
387 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
388 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
389 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
390 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
391 * @param Fault This parameter can be a combination of the following values:
392 * @arg @ref LL_HANDLER_FAULT_USG
393 * @arg @ref LL_HANDLER_FAULT_BUS
394 * @arg @ref LL_HANDLER_FAULT_MEM
395 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
396 *
397 * (*) value applicable in secure when the system implements the security.
398 * @retval None
399 */
LL_HANDLER_EnableFault(uint32_t Fault)400 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
401 {
402 /* Enable the system handler fault */
403 SET_BIT(SCB->SHCSR, Fault);
404 }
405
406 /**
407 * @brief Disable a fault in System handler control register (SHCSR)
408 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
409 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
410 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
411 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
412 * @param Fault This parameter can be a combination of the following values:
413 * @arg @ref LL_HANDLER_FAULT_USG
414 * @arg @ref LL_HANDLER_FAULT_BUS
415 * @arg @ref LL_HANDLER_FAULT_MEM
416 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
417 *
418 * (*) value applicable in secure when the system implements the security.
419 * @retval None
420 */
LL_HANDLER_DisableFault(uint32_t Fault)421 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
422 {
423 /* Disable the system handler fault */
424 CLEAR_BIT(SCB->SHCSR, Fault);
425 }
426
427 /**
428 * @}
429 */
430
431 /** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
432 * @{
433 */
434
435 /**
436 * @brief Get Implementer code
437 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
438 * @retval Value should be equal to 0x41 for ARM
439 */
LL_CPUID_GetImplementer(void)440 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
441 {
442 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
443 }
444
445 /**
446 * @brief Get Variant number (The r value in the rnpn product revision identifier)
447 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
448 * @retval Value between 0 and 255 (0x0: revision 0)
449 */
LL_CPUID_GetVariant(void)450 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
451 {
452 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
453 }
454
455 /**
456 * @brief Get Architecture version
457 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
458 * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension")
459 */
LL_CPUID_GetArchitecture(void)460 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
461 {
462 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
463 }
464
465 /**
466 * @brief Get Part number
467 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
468 * @retval Value should be equal to 0xD21 for Cortex-M33
469 */
LL_CPUID_GetParNo(void)470 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
471 {
472 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
473 }
474
475 /**
476 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
477 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
478 * @retval Value between 0 and 255 (0x1: patch 1)
479 */
LL_CPUID_GetRevision(void)480 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
481 {
482 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
483 }
484
485 /**
486 * @}
487 */
488
489 /** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
490 * @{
491 */
492
493 /**
494 * @brief Enable MPU with input options
495 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
496 * @param MPU_Control This parameter can be one of the following values:
497 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
498 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
499 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
500 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
501 * @retval None
502 */
LL_MPU_Enable(uint32_t MPU_Control)503 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
504 {
505 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
506
507 /* Enable the MPU*/
508 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
509
510 /* Follow ARM recommendation with */
511 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
512 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
513 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
514 }
515
516 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
517 /**
518 * @brief Enable non-secure MPU with input options
519 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
520 * @param MPU_Control This parameter can be one of the following values:
521 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
522 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
523 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
524 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
525 * @retval None
526 */
LL_MPU_Enable_NS(uint32_t MPU_Control)527 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
528 {
529 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
530
531 /* Enable the MPU*/
532 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
533
534 /* Follow ARM recommendation with */
535 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
536 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
537 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
538 }
539 #endif /* __ARM_FEATURE_CMSE */
540
541 /**
542 * @brief Disable MPU
543 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
544 * @retval None
545 */
LL_MPU_Disable(void)546 __STATIC_INLINE void LL_MPU_Disable(void)
547 {
548 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
549
550 /* Disable MPU */
551 WRITE_REG(MPU->CTRL, 0U);
552
553 /* Follow ARM recommendation with */
554 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
555 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
556 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
557 }
558
559 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
560 /**
561 * @brief Disable the non-secure MPU
562 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
563 * @retval None
564 */
LL_MPU_Disable_NS(void)565 __STATIC_INLINE void LL_MPU_Disable_NS(void)
566 {
567 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
568
569 /* Disable MPU*/
570 WRITE_REG(MPU_NS->CTRL, 0U);
571
572 /* Follow ARM recommendation with */
573 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
574 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
575 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
576 }
577 #endif /* __ARM_FEATURE_CMSE */
578
579
580 /**
581 * @brief Check if MPU is enabled or not
582 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
583 * @retval State of bit (1 or 0).
584 */
LL_MPU_IsEnabled(void)585 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
586 {
587 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
588 }
589
590 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
591 /**
592 * @brief Check if non-secure MPU is enabled or not
593 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
594 * @retval State of bit (1 or 0).
595 */
LL_MPU_IsEnabled_NS(void)596 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
597 {
598 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
599 }
600 #endif /* __ARM_FEATURE_CMSE */
601
602 /**
603 * @brief Enable a MPU region
604 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion
605 * @param Region This parameter can be one of the following values:
606 * @arg @ref LL_MPU_REGION_NUMBER0
607 * @arg @ref LL_MPU_REGION_NUMBER1
608 * @arg @ref LL_MPU_REGION_NUMBER2
609 * @arg @ref LL_MPU_REGION_NUMBER3
610 * @arg @ref LL_MPU_REGION_NUMBER4
611 * @arg @ref LL_MPU_REGION_NUMBER5
612 * @arg @ref LL_MPU_REGION_NUMBER6
613 * @arg @ref LL_MPU_REGION_NUMBER7
614 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
615 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
616 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
617 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
618 * @note cortex-M33 supports 12 secure and 8 non secure regions.
619 * (*) : For MPU_S only
620 * @retval None
621 */
LL_MPU_EnableRegion(uint32_t Region)622 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
623 {
624 /* Set Region number */
625 WRITE_REG(MPU->RNR, Region);
626
627 /* Enable the MPU region */
628 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
629 }
630
631 /**
632 * @brief Check if MPU region is enabled or not
633 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabledRegion
634 * @param Region This parameter can be one of the following values:
635 * @arg @ref LL_MPU_REGION_NUMBER0
636 * @arg @ref LL_MPU_REGION_NUMBER1
637 * @arg @ref LL_MPU_REGION_NUMBER2
638 * @arg @ref LL_MPU_REGION_NUMBER3
639 * @arg @ref LL_MPU_REGION_NUMBER4
640 * @arg @ref LL_MPU_REGION_NUMBER5
641 * @arg @ref LL_MPU_REGION_NUMBER6
642 * @arg @ref LL_MPU_REGION_NUMBER7
643 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
644 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
645 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
646 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
647 * @note cortex-M33 supports 12 secure and 8 non secure regions.
648 * (*) : For MPU_S only
649 * @retval State of bit (1 or 0).
650 */
LL_MPU_IsEnabled_Region(uint32_t Region)651 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
652 {
653 /* Set region index */
654 WRITE_REG(MPU->RNR, Region);
655
656 /* Return MPU region status */
657 return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
658 }
659
660 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
661 /**
662 * @brief Enable a non-secure MPU region
663 * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS
664 * @param Region This parameter can be one of the following values:
665 * @arg @ref LL_MPU_REGION_NUMBER0
666 * @arg @ref LL_MPU_REGION_NUMBER1
667 * @arg @ref LL_MPU_REGION_NUMBER2
668 * @arg @ref LL_MPU_REGION_NUMBER3
669 * @arg @ref LL_MPU_REGION_NUMBER4
670 * @arg @ref LL_MPU_REGION_NUMBER5
671 * @arg @ref LL_MPU_REGION_NUMBER6
672 * @arg @ref LL_MPU_REGION_NUMBER7
673 * @note cortex-M33 supports 8 non secure regions.
674 * @retval None
675 */
LL_MPU_EnableRegion_NS(uint32_t Region)676 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
677 {
678 /* Set Region number */
679 WRITE_REG(MPU_NS->RNR, Region);
680
681 /* Enable the MPU region */
682 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
683 }
684
685 /**
686 * @brief Check if non-secure MPU region is enabled or not
687 * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnableRegion_NS
688 * @param Region This parameter can be one of the following values:
689 * @arg @ref LL_MPU_REGION_NUMBER0
690 * @arg @ref LL_MPU_REGION_NUMBER1
691 * @arg @ref LL_MPU_REGION_NUMBER2
692 * @arg @ref LL_MPU_REGION_NUMBER3
693 * @arg @ref LL_MPU_REGION_NUMBER4
694 * @arg @ref LL_MPU_REGION_NUMBER5
695 * @arg @ref LL_MPU_REGION_NUMBER6
696 * @arg @ref LL_MPU_REGION_NUMBER7
697 * @note cortex-M33 supports 8 non secure regions.
698 * @retval State of bit (1 or 0).
699 */
LL_MPU_IsEnabled_Region_NS(uint32_t Region)700 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region)
701 {
702 /* Set region index */
703 WRITE_REG(MPU_NS->RNR, Region);
704
705 /* Return non-secure MPU region status */
706 return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
707 }
708 #endif /* __ARM_FEATURE_CMSE */
709
710 /**
711 * @brief Disable a MPU region
712 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
713 * MPU_RLAR ENABLE LL_MPU_DisableRegion
714 * @param Region This parameter can be one of the following values:
715 * @arg @ref LL_MPU_REGION_NUMBER0
716 * @arg @ref LL_MPU_REGION_NUMBER1
717 * @arg @ref LL_MPU_REGION_NUMBER2
718 * @arg @ref LL_MPU_REGION_NUMBER3
719 * @arg @ref LL_MPU_REGION_NUMBER4
720 * @arg @ref LL_MPU_REGION_NUMBER5
721 * @arg @ref LL_MPU_REGION_NUMBER6
722 * @arg @ref LL_MPU_REGION_NUMBER7
723 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
724 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
725 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
726 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
727 * @note cortex-M33 supports 12 secure and 8 non secure regions.
728 * (*) : For MPU_S only
729 * @retval None
730 */
LL_MPU_DisableRegion(uint32_t Region)731 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
732 {
733 /* Set Region number */
734 WRITE_REG(MPU->RNR, Region);
735
736 /* Disable the MPU region */
737 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
738 }
739
740 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
741 /**
742 * @brief Disable a non-secure MPU region
743 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
744 * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n
745 * @param Region This parameter can be one of the following values:
746 * @arg @ref LL_MPU_REGION_NUMBER0
747 * @arg @ref LL_MPU_REGION_NUMBER1
748 * @arg @ref LL_MPU_REGION_NUMBER2
749 * @arg @ref LL_MPU_REGION_NUMBER3
750 * @arg @ref LL_MPU_REGION_NUMBER4
751 * @arg @ref LL_MPU_REGION_NUMBER5
752 * @arg @ref LL_MPU_REGION_NUMBER6
753 * @arg @ref LL_MPU_REGION_NUMBER7
754 * @note cortex-M33 supports 8 non secure regions.
755 * @retval None
756 */
LL_MPU_DisableRegion_NS(uint32_t Region)757 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
758 {
759 /* Set Region number */
760 WRITE_REG(MPU_NS->RNR, Region);
761
762 /* Disable the MPU region */
763 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
764 }
765 #endif /* __ARM_FEATURE_CMSE */
766
767 /**
768 * @brief Configure and enable a MPU region
769 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
770 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
771 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
772 * MPU_RBAR XN LL_MPU_ConfigRegion\n
773 * MPU_RBAR AP LL_MPU_ConfigRegion\n
774 * MPU_RBAR SH LL_MPU_ConfigRegion\n
775 * MPU_RLAR EN LL_MPU_ConfigRegion\n
776 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n
777 * @param Region This parameter can be one of the following values:
778 * @arg @ref LL_MPU_REGION_NUMBER0
779 * @arg @ref LL_MPU_REGION_NUMBER1
780 * @arg @ref LL_MPU_REGION_NUMBER2
781 * @arg @ref LL_MPU_REGION_NUMBER3
782 * @arg @ref LL_MPU_REGION_NUMBER4
783 * @arg @ref LL_MPU_REGION_NUMBER5
784 * @arg @ref LL_MPU_REGION_NUMBER6
785 * @arg @ref LL_MPU_REGION_NUMBER7
786 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
787 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
788 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
789 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
790 * @param Attributes This parameter can be a combination of the following values:
791 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
792 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
793 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
794 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
795 * or @ref LL_MPU_REGION_ALL_RO
796 * @param AttrIndx This parameter can be one of the following values:
797 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
798 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
799 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
800 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
801 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
802 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
803 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
804 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
805 * @param BaseAddress Value of region base address
806 * @param LimitAddress Value of region limit address
807 * @note cortex-M33 supports 12 secure and 8 non secure regions.
808 * (*) : For MPU_S only
809 * @retval None
810 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)811 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
812 uint32_t LimitAddress)
813 {
814 /* Set region index */
815 WRITE_REG(MPU->RNR, Region);
816
817 /* Set base address */
818 MPU->RBAR |= Attributes;
819
820 /* Set region base address and region access attributes */
821 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
822
823 /* Set region limit address, memory attributes index and enable region */
824 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
825 }
826
827 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
828 /**
829 * @brief Configure and enable a non-secure MPU region
830 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
831 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
832 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
833 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
834 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
835 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
836 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
837 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n
838 * @param Region This parameter can be one of the following values:
839 * @arg @ref LL_MPU_REGION_NUMBER0
840 * @arg @ref LL_MPU_REGION_NUMBER1
841 * @arg @ref LL_MPU_REGION_NUMBER2
842 * @arg @ref LL_MPU_REGION_NUMBER3
843 * @arg @ref LL_MPU_REGION_NUMBER4
844 * @arg @ref LL_MPU_REGION_NUMBER5
845 * @arg @ref LL_MPU_REGION_NUMBER6
846 * @arg @ref LL_MPU_REGION_NUMBER7
847 * @param Attributes This parameter can be a combination of the following values:
848 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
849 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
850 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
851 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
852 * or @ref LL_MPU_REGION_ALL_RO
853 * @param AttrIndx This parameter can be one of the following values:
854 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
855 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
856 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
857 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
858 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
859 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
860 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
861 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
862 * @param BaseAddress Value of region base address
863 * @param LimitAddress Value of region limit address
864 * @note cortex-M33 supports 12 secure and 8 non secure regions.
865 * @retval None
866 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)867 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
868 uint32_t BaseAddress, uint32_t LimitAddress)
869 {
870 /* Set Region number */
871 WRITE_REG(MPU_NS->RNR, Region);
872
873 /* Set region base address and region access attributes */
874 WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
875
876 /* Set region limit address, memory attributes index and enable region */
877 WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
878 }
879 #endif /* __ARM_FEATURE_CMSE */
880
881 /**
882 * @brief Configure a MPU region address range
883 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
884 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
885 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
886 * @param Region This parameter can be one of the following values:
887 * @arg @ref LL_MPU_REGION_NUMBER0
888 * @arg @ref LL_MPU_REGION_NUMBER1
889 * @arg @ref LL_MPU_REGION_NUMBER2
890 * @arg @ref LL_MPU_REGION_NUMBER3
891 * @arg @ref LL_MPU_REGION_NUMBER4
892 * @arg @ref LL_MPU_REGION_NUMBER5
893 * @arg @ref LL_MPU_REGION_NUMBER6
894 * @arg @ref LL_MPU_REGION_NUMBER7
895 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
896 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
897 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
898 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
899 * @param BaseAddress Value of region base address
900 * @param LimitAddress Value of region limit address
901 * @note cortex-M33 supports 12 secure and 8 non secure regions.
902 * (*) : For MPU_S only
903 * @retval None
904 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)905 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
906 {
907 /* Set Region number */
908 WRITE_REG(MPU->RNR, Region);
909
910 /* Modify region base address */
911 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
912
913 /* Modify region limit address */
914 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
915 }
916
917 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
918 /**
919 * @brief Configure a non-secure MPU region address range
920 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
921 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
922 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
923 * @param Region This parameter can be one of the following values:
924 * @arg @ref LL_MPU_REGION_NUMBER0
925 * @arg @ref LL_MPU_REGION_NUMBER1
926 * @arg @ref LL_MPU_REGION_NUMBER2
927 * @arg @ref LL_MPU_REGION_NUMBER3
928 * @arg @ref LL_MPU_REGION_NUMBER4
929 * @arg @ref LL_MPU_REGION_NUMBER5
930 * @arg @ref LL_MPU_REGION_NUMBER6
931 * @arg @ref LL_MPU_REGION_NUMBER7
932 * @param BaseAddress Value of region base address
933 * @param LimitAddress Value of region limit address
934 * @note cortex-M33 supports 12 secure and 8 non secure regions.
935 * @retval None
936 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)937 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
938 {
939 /* Set Region number */
940 WRITE_REG(MPU_NS->RNR, Region);
941
942 /* Set base address */
943 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
944
945 /* Set limit address */
946 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
947 }
948 #endif /* __ARM_FEATURE_CMSE */
949
950 /**
951 * @brief Configure a MPU attributes index
952 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n
953 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n
954 * @param AttIndex This parameter can be one of the following values:
955 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
956 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
957 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
958 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
959 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
960 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
961 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
962 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
963 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
964 * @retval None
965 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)966 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
967 {
968 /* When selected index is in range [0;3] */
969 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
970 {
971 /* Modify Attr<i> field of MPU_MAIR0 accordingly */
972 MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
973 }
974 /* When selected index is in range [4;7] */
975 else
976 {
977 /* Modify Attr<i> field of MPU_MAIR1 accordingly */
978 MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
979 }
980 }
981
982 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
983 /**
984 * @brief Configure a non-secure MPU attributes index
985 * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n
986 * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n
987 * @param AttIndex This parameter can be one of the following values:
988 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
989 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
990 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
991 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
992 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
993 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
994 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
995 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
996 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
997 * @retval None
998 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)999 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
1000 {
1001 /* When selected index is in range [0;3] */
1002 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
1003 {
1004 /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
1005 MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
1006 }
1007 /* When selected index is in range [4;7] */
1008 else
1009 {
1010 /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
1011 MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
1012 }
1013 }
1014 #endif /* __ARM_FEATURE_CMSE */
1015
1016 /**
1017 * @brief Configure a MPU region limit address
1018 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
1019 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n
1020 * @param Region This parameter can be one of the following values:
1021 * @arg @ref LL_MPU_REGION_NUMBER0
1022 * @arg @ref LL_MPU_REGION_NUMBER1
1023 * @arg @ref LL_MPU_REGION_NUMBER2
1024 * @arg @ref LL_MPU_REGION_NUMBER3
1025 * @arg @ref LL_MPU_REGION_NUMBER4
1026 * @arg @ref LL_MPU_REGION_NUMBER5
1027 * @arg @ref LL_MPU_REGION_NUMBER6
1028 * @arg @ref LL_MPU_REGION_NUMBER7
1029 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1030 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1031 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1032 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1033 * @param LimitAddress Value of region limit address
1034 * @note cortex-M33 supports 12 secure and 8 non secure regions.
1035 * (*) : For MPU_S only
1036 * @retval None
1037 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)1038 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
1039 {
1040 /* Set Region number */
1041 WRITE_REG(MPU->RNR, Region);
1042
1043 /* Set limit address */
1044 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1045 }
1046
1047 /**
1048 * @brief Get a MPU region limit address
1049 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
1050 * @param Region This parameter can be one of the following values:
1051 * @arg @ref LL_MPU_REGION_NUMBER0
1052 * @arg @ref LL_MPU_REGION_NUMBER1
1053 * @arg @ref LL_MPU_REGION_NUMBER2
1054 * @arg @ref LL_MPU_REGION_NUMBER3
1055 * @arg @ref LL_MPU_REGION_NUMBER4
1056 * @arg @ref LL_MPU_REGION_NUMBER5
1057 * @arg @ref LL_MPU_REGION_NUMBER6
1058 * @arg @ref LL_MPU_REGION_NUMBER7
1059 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1060 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1061 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1062 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1063 * (*) : For MPU_S only
1064 * @retval Value of the region limit address
1065 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)1066 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
1067 {
1068 /* Set Region number */
1069 WRITE_REG(MPU->RNR, Region);
1070 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
1071 }
1072
1073 /**
1074 * @brief Configure a MPU region base address
1075 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
1076 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n
1077 * @param Region This parameter can be one of the following values:
1078 * @arg @ref LL_MPU_REGION_NUMBER0
1079 * @arg @ref LL_MPU_REGION_NUMBER1
1080 * @arg @ref LL_MPU_REGION_NUMBER2
1081 * @arg @ref LL_MPU_REGION_NUMBER3
1082 * @arg @ref LL_MPU_REGION_NUMBER4
1083 * @arg @ref LL_MPU_REGION_NUMBER5
1084 * @arg @ref LL_MPU_REGION_NUMBER6
1085 * @arg @ref LL_MPU_REGION_NUMBER7
1086 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1087 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1088 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1089 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1090 * @param BaseAddress Value of region base address
1091 * @note cortex-M33 supports 12 secure and 8 non secure regions.
1092 * (*) : For MPU_S only
1093 * @retval None
1094 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)1095 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
1096 {
1097 /* Set Region number */
1098 WRITE_REG(MPU->RNR, Region);
1099 /* Set base address */
1100 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1101 }
1102
1103 /**
1104 * @brief Get a MPU region base address
1105 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
1106 * @param Region This parameter can be one of the following values:
1107 * @arg @ref LL_MPU_REGION_NUMBER0
1108 * @arg @ref LL_MPU_REGION_NUMBER1
1109 * @arg @ref LL_MPU_REGION_NUMBER2
1110 * @arg @ref LL_MPU_REGION_NUMBER3
1111 * @arg @ref LL_MPU_REGION_NUMBER4
1112 * @arg @ref LL_MPU_REGION_NUMBER5
1113 * @arg @ref LL_MPU_REGION_NUMBER6
1114 * @arg @ref LL_MPU_REGION_NUMBER7
1115 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1116 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1117 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1118 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1119 * @note cortex-M33 supports 12 secure and 8 non secure regions.
1120 * (*) : For MPU_S only
1121 * @retval Value of the region base address
1122 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)1123 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
1124 {
1125 /* Set Region number */
1126 WRITE_REG(MPU->RNR, Region);
1127 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
1128 }
1129
1130 /**
1131 * @brief Configure a MPU region access attributes and enable a region
1132 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
1133 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
1134 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
1135 * MPU_RBAR SH LL_MPU_SetRegionAccess\n
1136 * @param Region This parameter can be one of the following values:
1137 * @arg @ref LL_MPU_REGION_NUMBER0
1138 * @arg @ref LL_MPU_REGION_NUMBER1
1139 * @arg @ref LL_MPU_REGION_NUMBER2
1140 * @arg @ref LL_MPU_REGION_NUMBER3
1141 * @arg @ref LL_MPU_REGION_NUMBER4
1142 * @arg @ref LL_MPU_REGION_NUMBER5
1143 * @arg @ref LL_MPU_REGION_NUMBER6
1144 * @arg @ref LL_MPU_REGION_NUMBER7
1145 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1146 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1147 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1148 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1149 * @param Attributes This parameter can be a combination of the following values:
1150 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1151 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1152 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1153 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1154 * or @ref LL_MPU_REGION_ALL_RO
1155 * @note cortex-M33 supports 12 secure and 8 non secure regions.
1156 * (*) : For MPU_S only
1157 * @retval None
1158 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)1159 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
1160 {
1161 /* Set Region number */
1162 WRITE_REG(MPU->RNR, Region);
1163
1164 /* Set base address */
1165 MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1166 }
1167
1168 /**
1169 * @brief Get a MPU region access attributes
1170 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
1171 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
1172 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
1173 * MPU_RBAR SH LL_MPU_GetRegionAccess\n
1174 * @param Region This parameter can be one of the following values:
1175 * @arg @ref LL_MPU_REGION_NUMBER0
1176 * @arg @ref LL_MPU_REGION_NUMBER1
1177 * @arg @ref LL_MPU_REGION_NUMBER2
1178 * @arg @ref LL_MPU_REGION_NUMBER3
1179 * @arg @ref LL_MPU_REGION_NUMBER4
1180 * @arg @ref LL_MPU_REGION_NUMBER5
1181 * @arg @ref LL_MPU_REGION_NUMBER6
1182 * @arg @ref LL_MPU_REGION_NUMBER7
1183 * @arg @ref LL_MPU_REGION_NUMBER8 (*)
1184 * @arg @ref LL_MPU_REGION_NUMBER9 (*)
1185 * @arg @ref LL_MPU_REGION_NUMBER10 (*)
1186 * @arg @ref LL_MPU_REGION_NUMBER11 (*)
1187 * (*) : For MPU_S only
1188 * @retval return a combination of the following values:
1189 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1190 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1191 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1192 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1193 * or @ref LL_MPU_REGION_ALL_RO
1194 */
LL_MPU_GetRegionAccess(uint32_t Region)1195 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
1196 {
1197 /* Set Region number */
1198 WRITE_REG(MPU->RNR, Region);
1199 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1200 }
1201
1202 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1203 /**
1204 * @brief Configure a non-secure MPU region limit address
1205 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1206 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n
1207 * @param Region This parameter can be one of the following values:
1208 * @arg @ref LL_MPU_REGION_NUMBER0
1209 * @arg @ref LL_MPU_REGION_NUMBER1
1210 * @arg @ref LL_MPU_REGION_NUMBER2
1211 * @arg @ref LL_MPU_REGION_NUMBER3
1212 * @arg @ref LL_MPU_REGION_NUMBER4
1213 * @arg @ref LL_MPU_REGION_NUMBER5
1214 * @arg @ref LL_MPU_REGION_NUMBER6
1215 * @arg @ref LL_MPU_REGION_NUMBER7
1216 * @param LimitAddress Value of region limit address
1217 * @note cortex-M33 supports 8 non secure regions.
1218 * @retval None
1219 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1220 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1221 {
1222 /* Set Region number */
1223 WRITE_REG(MPU_NS->RNR, Region);
1224
1225 /* Set limit address */
1226 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1227 }
1228
1229 /**
1230 * @brief Get a non-secure MPU region limit address
1231 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1232 * @param Region This parameter can be one of the following values:
1233 * @arg @ref LL_MPU_REGION_NUMBER0
1234 * @arg @ref LL_MPU_REGION_NUMBER1
1235 * @arg @ref LL_MPU_REGION_NUMBER2
1236 * @arg @ref LL_MPU_REGION_NUMBER3
1237 * @arg @ref LL_MPU_REGION_NUMBER4
1238 * @arg @ref LL_MPU_REGION_NUMBER5
1239 * @arg @ref LL_MPU_REGION_NUMBER6
1240 * @arg @ref LL_MPU_REGION_NUMBER7
1241 * @retval Value of the region limit address.
1242 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1243 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1244 {
1245 /* Set Region number */
1246 WRITE_REG(MPU_NS->RNR, Region);
1247 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1248 }
1249
1250 /**
1251 * @brief Configure a non-secure MPU region base address
1252 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1253 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n
1254 * @param Region This parameter can be one of the following values:
1255 * @arg @ref LL_MPU_REGION_NUMBER0
1256 * @arg @ref LL_MPU_REGION_NUMBER1
1257 * @arg @ref LL_MPU_REGION_NUMBER2
1258 * @arg @ref LL_MPU_REGION_NUMBER3
1259 * @arg @ref LL_MPU_REGION_NUMBER4
1260 * @arg @ref LL_MPU_REGION_NUMBER5
1261 * @arg @ref LL_MPU_REGION_NUMBER6
1262 * @arg @ref LL_MPU_REGION_NUMBER7
1263 * @param BaseAddress Value of region base address
1264 * @note cortex-M33 supports 8 non secure regions.
1265 * @retval None
1266 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1267 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1268 {
1269 /* Set Region number */
1270 WRITE_REG(MPU_NS->RNR, Region);
1271
1272 /* Set base address */
1273 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1274 }
1275
1276 /**
1277 * @brief Get a non-secure MPU region base address
1278 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1279 * @param Region This parameter can be one of the following values:
1280 * @arg @ref LL_MPU_REGION_NUMBER0
1281 * @arg @ref LL_MPU_REGION_NUMBER1
1282 * @arg @ref LL_MPU_REGION_NUMBER2
1283 * @arg @ref LL_MPU_REGION_NUMBER3
1284 * @arg @ref LL_MPU_REGION_NUMBER4
1285 * @arg @ref LL_MPU_REGION_NUMBER5
1286 * @arg @ref LL_MPU_REGION_NUMBER6
1287 * @arg @ref LL_MPU_REGION_NUMBER7
1288 * @retval Value of the region base address.
1289 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1290 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1291 {
1292 /* Set Region number */
1293 WRITE_REG(MPU_NS->RNR, Region);
1294
1295 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1296 }
1297
1298 /**
1299 * @brief Configure a non-secure MPU region access attributes and enable a region
1300 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1301 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1302 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1303 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n
1304 * @param Region This parameter can be one of the following values:
1305 * @arg @ref LL_MPU_REGION_NUMBER0
1306 * @arg @ref LL_MPU_REGION_NUMBER1
1307 * @arg @ref LL_MPU_REGION_NUMBER2
1308 * @arg @ref LL_MPU_REGION_NUMBER3
1309 * @arg @ref LL_MPU_REGION_NUMBER4
1310 * @arg @ref LL_MPU_REGION_NUMBER5
1311 * @arg @ref LL_MPU_REGION_NUMBER6
1312 * @arg @ref LL_MPU_REGION_NUMBER7
1313 * @param Attributes This parameter can be a combination of the following values:
1314 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1315 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1316 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1317 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1318 * or @ref LL_MPU_REGION_ALL_RO
1319 * @note cortex-M33 supports 8 non secure regions.
1320 * @retval None
1321 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1322 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1323 {
1324 /* Set Region number */
1325 WRITE_REG(MPU_NS->RNR, Region);
1326
1327 /* Set base address Attributes */
1328 MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1329 }
1330
1331 /**
1332 * @brief Get a non-secure MPU region access attributes
1333 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1334 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1335 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1336 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n
1337 * @param Region This parameter can be one of the following values:
1338 * @arg @ref LL_MPU_REGION_NUMBER0
1339 * @arg @ref LL_MPU_REGION_NUMBER1
1340 * @arg @ref LL_MPU_REGION_NUMBER2
1341 * @arg @ref LL_MPU_REGION_NUMBER3
1342 * @arg @ref LL_MPU_REGION_NUMBER4
1343 * @arg @ref LL_MPU_REGION_NUMBER5
1344 * @arg @ref LL_MPU_REGION_NUMBER6
1345 * @arg @ref LL_MPU_REGION_NUMBER7
1346 * @retval return a combination of the following values:
1347 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1348 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1349 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1350 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1351 * or @ref LL_MPU_REGION_ALL_RO
1352 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1353 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1354 {
1355 /* Set Region number */
1356 WRITE_REG(MPU_NS->RNR, Region);
1357
1358 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1359 }
1360 #endif /* __ARM_FEATURE_CMSE */
1361
1362 /**
1363 * @}
1364 */
1365
1366 /**
1367 * @}
1368 */
1369
1370 /**
1371 * @}
1372 */
1373
1374 /**
1375 * @}
1376 */
1377
1378 #ifdef __cplusplus
1379 }
1380 #endif
1381
1382 #endif /* STM32H5xx_LL_CORTEX_H */
1383
