1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32H5xx_HAL_RCC_H 22 #define __STM32H5xx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_def.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCC_Exported_Types RCC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC PLL1 configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLLState; /*!< The new state of the PLL1. 50 This parameter can be a value of @ref RCC_PLL1_Config */ 51 52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 53 This parameter must be a value of @ref RCC_PLL1_Clock_Source */ 54 55 uint32_t PLLM; /*!< PLLM: Division factor for PLL1 VCO input clock. 56 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 57 58 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL1 VCO output clock. 59 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 60 61 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 62 This parameter must be a number between Min_Data = 2 and Max_Data = 128 63 odd division factors are not allowed */ 64 65 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 66 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 67 68 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 69 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 70 71 uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range 72 This parameter must be a value of @ref RCC_PLL1_VCI_Range */ 73 74 uint32_t PLLVCOSEL; /*!< PLLVCOSEL: PLL1 clock Output range 75 This parameter must be a value of @ref RCC_PLL1_VCO_Range */ 76 77 uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 78 PLL1 VCO It should be a value between 0 and 8191 */ 79 80 } RCC_PLLInitTypeDef; 81 82 /** 83 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition 84 */ 85 typedef struct 86 { 87 uint32_t OscillatorType; /*!< The oscillators to be configured. 88 This parameter can be a value of @ref RCC_Oscillator_Type */ 89 90 uint32_t HSEState; /*!< The new state of the HSE. 91 This parameter can be a value of @ref RCC_HSE_Config */ 92 93 uint32_t LSEState; /*!< The new state of the LSE. 94 This parameter can be a value of @ref RCC_LSE_Config */ 95 96 uint32_t HSIState; /*!< The new state of the HSI. 97 This parameter can be a value of @ref RCC_HSI_Config */ 98 99 uint32_t HSIDiv; /*!< The division factor of the HSI. 100 This parameter can be a value of @ref RCC_HSI_Div */ 101 102 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 103 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 104 on the other devices */ 105 106 uint32_t LSIState; /*!< The new state of the LSI. 107 This parameter can be a value of @ref RCC_LSI_Config */ 108 109 uint32_t CSIState; /*!< The new state of the CSI. 110 This parameter can be a value of @ref RCC_CSI_Config */ 111 112 uint32_t CSICalibrationValue; /*!< The calibration trimming value (default is RCC_CSICALIBRATION_DEFAULT). 113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F */ 114 115 uint32_t HSI48State; /*!< The new state of the HSI48. 116 This parameter can be a value of @ref RCC_HSI48_Config */ 117 118 RCC_PLLInitTypeDef PLL; /*!< PLL1 structure parameters */ 119 120 } RCC_OscInitTypeDef; 121 122 /** 123 * @brief RCC System, AHB and APB busses clock configuration structure definition 124 */ 125 typedef struct 126 { 127 uint32_t ClockType; /*!< The clock to be configured. 128 This parameter can be a value of @ref RCC_System_Clock_Type */ 129 130 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 131 This parameter can be a value of @ref RCC_System_Clock_Source */ 132 133 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 134 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 135 136 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 137 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 138 139 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 140 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 141 142 uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). 143 This parameter can be a value of @ref RCC_APB3_Clock_Source */ 144 } RCC_ClkInitTypeDef; 145 146 /** 147 * @} 148 */ 149 150 /* Exported constants --------------------------------------------------------*/ 151 /** @defgroup RCC_Exported_Constants RCC Exported Constants 152 * @{ 153 */ 154 155 /** @defgroup RCC_Peripheral_Memory_Mapping Peripheral Memory Mapping 156 * @{ 157 */ 158 159 /** 160 * @} 161 */ 162 163 /** @defgroup RCC_Timeout_Value Timeout Values 164 * @{ 165 */ 166 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 167 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 168 /** 169 * @} 170 */ 171 172 /** @defgroup RCC_Oscillator_Type Oscillator Type 173 * @{ 174 */ 175 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) /*!< Oscillator configuration unchanged */ 176 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) /*!< HSE to configure */ 177 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) /*!< HSI to configure */ 178 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) /*!< LSE to configure */ 179 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) /*!< LSI to configure */ 180 #define RCC_OSCILLATORTYPE_CSI (0x00000010U) /*!< CSI to configure */ 181 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) /*!< HSI48 to configure */ 182 /** 183 * @} 184 */ 185 186 /** @defgroup RCC_HSE_Config HSE Config 187 * @{ 188 */ 189 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ 190 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 191 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External Analog clock source for HSE clock */ 192 #define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External Digital clock source for HSE clock */ 193 /** 194 * @} 195 */ 196 197 /** @defgroup RCC_LSE_Config LSE Config 198 * @{ 199 */ 200 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 201 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 202 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Analog clock source for LSE clock */ 203 #define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Digital clock source for LSE clock */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup RCC_HSI_Config HSI Config 209 * @{ 210 */ 211 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 212 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 213 214 #define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup RCC_HSI_Div HSI Div 220 * @{ 221 */ 222 #define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ 223 #define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ 224 #define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ 225 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ 226 /** 227 * @} 228 */ 229 230 /** @defgroup RCC_LSI_Config LSI Config 231 * @{ 232 */ 233 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ 234 #define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup RCC_CSI_Config CSI Config 240 * @{ 241 */ 242 #define RCC_CSI_OFF (0x00000000U) /*!< CSI clock deactivation */ 243 #define RCC_CSI_ON RCC_CR_CSION /*!< CSI clock activation */ 244 245 #define RCC_CSICALIBRATION_DEFAULT (0x20U) /*!< Default CSI calibration trimming value */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_HSI48_Config HSI48 Config 251 * @{ 252 */ 253 #define RCC_HSI48_OFF (0x00000000U) /*!< HSI48 clock deactivation */ 254 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 255 /** 256 * @} 257 */ 258 259 /** @defgroup RCC_PLL1_Config RCC PLL1 Config 260 * @{ 261 */ 262 #define RCC_PLL_NONE (0x00000000U) 263 #define RCC_PLL_OFF (0x00000001U) 264 #define RCC_PLL_ON (0x00000002U) 265 /** 266 * @} 267 */ 268 269 /** @defgroup RCC_PLL1_Clock_Output RCC PLL1 Clock Output 270 * @{ 271 */ 272 #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN 273 #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN 274 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN 275 /** 276 * @} 277 */ 278 279 /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range 280 * @{ 281 */ 282 #define RCC_PLL1_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 283 #define RCC_PLL1_VCIRANGE_1 RCC_PLL1CFGR_PLL1RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 284 #define RCC_PLL1_VCIRANGE_2 RCC_PLL1CFGR_PLL1RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 285 #define RCC_PLL1_VCIRANGE_3 (RCC_PLL1CFGR_PLL1RGE_0 | RCC_PLL1CFGR_PLL1RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range 291 * @{ 292 */ 293 #define RCC_PLL1_VCORANGE_WIDE (0x00000000U) /*!< Clock range frequency between 192 and 836 MHz */ 294 #define RCC_PLL1_VCORANGE_MEDIUM RCC_PLL1CFGR_PLL1VCOSEL /*!< Clock range frequency between 150 and 420 MHz */ 295 296 /** 297 * @} 298 */ 299 300 /** @defgroup RCC_PLL1_Clock_Source RCC PLL1 Clock Source 301 * @{ 302 */ 303 #define RCC_PLL1_SOURCE_NONE (0x00000000U) 304 #define RCC_PLL1_SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_0 305 #define RCC_PLL1_SOURCE_CSI RCC_PLL1CFGR_PLL1SRC_1 306 #define RCC_PLL1_SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) 307 /** 308 * @} 309 */ 310 311 312 /** @defgroup RCC_System_Clock_Type System Clock Type 313 * @{ 314 */ 315 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ 316 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ 317 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ 318 #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ 319 #define RCC_CLOCKTYPE_PCLK3 (0x00000010U) /*!< PCLK3 to configure */ 320 /** 321 * @} 322 */ 323 324 /** @defgroup RCC_System_Clock_Source System Clock Source 325 * @{ 326 */ 327 #define RCC_SYSCLKSOURCE_HSI (0x00000000U) /*!< HSI selection as system clock */ 328 #define RCC_SYSCLKSOURCE_CSI RCC_CFGR1_SW_0 /*!< CSI selection as system clock */ 329 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ 330 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 336 * @{ 337 */ 338 #define RCC_SYSCLKSOURCE_STATUS_HSI (0x00000000U) /*!< HSI used as system clock */ 339 #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR1_SWS_0 /*!< CSI used as system clock */ 340 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ 341 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 347 * @{ 348 */ 349 #define RCC_SYSCLK_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 350 #define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ 351 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ 352 #define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ 353 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ 354 #define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ 355 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ 356 #define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ 357 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ 358 /** 359 * @} 360 */ 361 362 /** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source 363 * @{ 364 */ 365 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 366 #define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 367 #define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ 368 #define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ 369 #define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ 370 /** 371 * @} 372 */ 373 374 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler 375 * @{ 376 */ 377 #define RCC_RTC_HSE_NOCLOCK (0x00000000U) 378 #define RCC_RTC_HSE_DIV2 (0x00000200U) 379 #define RCC_RTC_HSE_DIV3 (0x00000300U) 380 #define RCC_RTC_HSE_DIV4 (0x00000400U) 381 #define RCC_RTC_HSE_DIV5 (0x00000500U) 382 #define RCC_RTC_HSE_DIV6 (0x00000600U) 383 #define RCC_RTC_HSE_DIV7 (0x00000700U) 384 #define RCC_RTC_HSE_DIV8 (0x00000800U) 385 #define RCC_RTC_HSE_DIV9 (0x00000900U) 386 #define RCC_RTC_HSE_DIV10 (0x00000A00U) 387 #define RCC_RTC_HSE_DIV11 (0x00000B00U) 388 #define RCC_RTC_HSE_DIV12 (0x00000C00U) 389 #define RCC_RTC_HSE_DIV13 (0x00000D00U) 390 #define RCC_RTC_HSE_DIV14 (0x00000E00U) 391 #define RCC_RTC_HSE_DIV15 (0x00000F00U) 392 #define RCC_RTC_HSE_DIV16 (0x00001000U) 393 #define RCC_RTC_HSE_DIV17 (0x00001100U) 394 #define RCC_RTC_HSE_DIV18 (0x00001200U) 395 #define RCC_RTC_HSE_DIV19 (0x00001300U) 396 #define RCC_RTC_HSE_DIV20 (0x00001400U) 397 #define RCC_RTC_HSE_DIV21 (0x00001500U) 398 #define RCC_RTC_HSE_DIV22 (0x00001600U) 399 #define RCC_RTC_HSE_DIV23 (0x00001700U) 400 #define RCC_RTC_HSE_DIV24 (0x00001800U) 401 #define RCC_RTC_HSE_DIV25 (0x00001900U) 402 #define RCC_RTC_HSE_DIV26 (0x00001A00U) 403 #define RCC_RTC_HSE_DIV27 (0x00001B00U) 404 #define RCC_RTC_HSE_DIV28 (0x00001C00U) 405 #define RCC_RTC_HSE_DIV29 (0x00001D00U) 406 #define RCC_RTC_HSE_DIV30 (0x00001E00U) 407 #define RCC_RTC_HSE_DIV31 (0x00001F00U) 408 #define RCC_RTC_HSE_DIV32 (0x00002000U) 409 #define RCC_RTC_HSE_DIV33 (0x00002100U) 410 #define RCC_RTC_HSE_DIV34 (0x00002200U) 411 #define RCC_RTC_HSE_DIV35 (0x00002300U) 412 #define RCC_RTC_HSE_DIV36 (0x00002400U) 413 #define RCC_RTC_HSE_DIV37 (0x00002500U) 414 #define RCC_RTC_HSE_DIV38 (0x00002600U) 415 #define RCC_RTC_HSE_DIV39 (0x00002700U) 416 #define RCC_RTC_HSE_DIV40 (0x00002800U) 417 #define RCC_RTC_HSE_DIV41 (0x00002900U) 418 #define RCC_RTC_HSE_DIV42 (0x00002A00U) 419 #define RCC_RTC_HSE_DIV43 (0x00002B00U) 420 #define RCC_RTC_HSE_DIV44 (0x00002C00U) 421 #define RCC_RTC_HSE_DIV45 (0x00002D00U) 422 #define RCC_RTC_HSE_DIV46 (0x00002E00U) 423 #define RCC_RTC_HSE_DIV47 (0x00002F00U) 424 #define RCC_RTC_HSE_DIV48 (0x00003000U) 425 #define RCC_RTC_HSE_DIV49 (0x00003100U) 426 #define RCC_RTC_HSE_DIV50 (0x00003200U) 427 #define RCC_RTC_HSE_DIV51 (0x00003300U) 428 #define RCC_RTC_HSE_DIV52 (0x00003400U) 429 #define RCC_RTC_HSE_DIV53 (0x00003500U) 430 #define RCC_RTC_HSE_DIV54 (0x00003600U) 431 #define RCC_RTC_HSE_DIV55 (0x00003700U) 432 #define RCC_RTC_HSE_DIV56 (0x00003800U) 433 #define RCC_RTC_HSE_DIV57 (0x00003900U) 434 #define RCC_RTC_HSE_DIV58 (0x00003A00U) 435 #define RCC_RTC_HSE_DIV59 (0x00003B00U) 436 #define RCC_RTC_HSE_DIV60 (0x00003C00U) 437 #define RCC_RTC_HSE_DIV61 (0x00003D00U) 438 #define RCC_RTC_HSE_DIV62 (0x00003E00U) 439 #define RCC_RTC_HSE_DIV63 (0x00003F00U) 440 /** 441 * @} 442 */ 443 444 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 445 * @{ 446 */ 447 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock used as RTC clock source */ 448 #define RCC_RTCCLKSOURCE_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock source */ 449 #define RCC_RTCCLKSOURCE_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock source */ 450 #define RCC_RTCCLKSOURCE_HSE_DIVx (0x00000300U) /*!< HSE oscillator clock divided by X used as RTC clock source */ 451 #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) 452 #define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U) 453 #define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U) 454 #define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U) 455 #define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U) 456 #define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U) 457 #define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U) 458 #define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U) 459 #define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U) 460 #define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U) 461 #define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U) 462 #define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U) 463 #define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U) 464 #define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U) 465 #define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U) 466 #define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U) 467 #define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U) 468 #define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U) 469 #define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U) 470 #define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U) 471 #define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U) 472 #define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U) 473 #define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U) 474 #define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U) 475 #define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U) 476 #define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U) 477 #define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U) 478 #define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U) 479 #define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U) 480 #define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U) 481 #define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U) 482 #define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U) 483 #define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U) 484 #define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U) 485 #define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U) 486 #define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U) 487 #define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U) 488 #define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U) 489 #define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U) 490 #define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U) 491 #define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U) 492 #define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U) 493 #define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U) 494 #define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U) 495 #define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U) 496 #define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U) 497 #define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U) 498 #define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U) 499 #define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U) 500 #define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U) 501 #define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U) 502 #define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U) 503 #define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U) 504 #define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U) 505 #define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U) 506 #define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U) 507 #define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U) 508 #define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U) 509 #define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U) 510 #define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U) 511 #define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U) 512 #define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U) 513 /** 514 * @} 515 */ 516 517 /** @defgroup RCC_MCO_Index MCO Index 518 * @{ 519 */ 520 #define RCC_MCO1 (0x00000000U) 521 #define RCC_MCO2 (0x00000001U) 522 /** 523 * @} 524 */ 525 526 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source 527 * @{ 528 */ 529 #define RCC_MCO1SOURCE_HSI (0x00000000U) 530 #define RCC_MCO1SOURCE_LSE RCC_CFGR1_MCO1SEL_0 531 #define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCO1SEL_1 532 #define RCC_MCO1SOURCE_PLL1Q ((uint32_t)RCC_CFGR1_MCO1SEL_0 | RCC_CFGR1_MCO1SEL_1) 533 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCO1SEL_2 534 535 /** 536 * @} 537 */ 538 539 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source 540 * @{ 541 */ 542 #define RCC_MCO2SOURCE_SYSCLK (0x00000000U) 543 #define RCC_MCO2SOURCE_PLL2P RCC_CFGR1_MCO2SEL_0 544 #define RCC_MCO2SOURCE_HSE RCC_CFGR1_MCO2SEL_1 545 #define RCC_MCO2SOURCE_PLL1P ((uint32_t)RCC_CFGR1_MCO2SEL_0 | RCC_CFGR1_MCO2SEL_1) 546 #define RCC_MCO2SOURCE_CSI RCC_CFGR1_MCO2SEL_2 547 #define RCC_MCO2SOURCE_LSI ((uint32_t)RCC_CFGR1_MCO2SEL_0 | RCC_CFGR1_MCO2SEL_2) 548 549 /** 550 * @} 551 */ 552 553 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler 554 * @{ 555 */ 556 #define RCC_MCODIV_1 RCC_CFGR1_MCO1PRE_0 557 #define RCC_MCODIV_2 RCC_CFGR1_MCO1PRE_1 558 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1) 559 #define RCC_MCODIV_4 RCC_CFGR1_MCO1PRE_2 560 #define RCC_MCODIV_5 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2) 561 #define RCC_MCODIV_6 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) 562 #define RCC_MCODIV_7 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) 563 #define RCC_MCODIV_8 RCC_CFGR1_MCO1PRE_3 564 #define RCC_MCODIV_9 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_3) 565 #define RCC_MCODIV_10 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) 566 #define RCC_MCODIV_11 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) 567 #define RCC_MCODIV_12 ((uint32_t)RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 568 #define RCC_MCODIV_13 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 569 #define RCC_MCODIV_14 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 570 #define RCC_MCODIV_15 RCC_CFGR1_MCO1PRE 571 /** 572 * @} 573 */ 574 575 /** @defgroup RCC_Interrupt Interrupts 576 * @{ 577 */ 578 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 579 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 580 #define RCC_IT_CSIRDY RCC_CIFR_CSIRDYF /*!< CSI Ready Interrupt flag */ 581 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 582 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 583 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 584 #define RCC_IT_PLL1RDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ 585 #define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 586 #if defined(RCC_CR_PLL3ON) 587 #define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ 588 #endif /* RCC_CR_PLL3ON */ 589 #define RCC_IT_HSECSS RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt flag */ 590 591 /** 592 * @} 593 */ 594 595 /** @defgroup RCC_Flag Flags 596 * Elements values convention: XXXYYYYYb 597 * - YYYYY : Flag position in the register 598 * - XXX : Register index 599 * - 001: CR register 600 * - 010: BDCR register 601 * - 011: RSR register 602 * @{ 603 */ 604 /* Flags in the CR register */ 605 #define RCC_FLAG_CSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_CSIRDY_Pos)) /*!< CSI Ready flag */ 606 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ 607 #define RCC_FLAG_HSIDIVF ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIDIVF_Pos)) /*!< HSI divider flag */ 608 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ 609 #define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL1 Ready flag */ 610 #define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ 611 #if defined(RCC_CR_PLL3ON) 612 #define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ 613 #endif /* RCC_CR_PLL3ON */ 614 #define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ 615 616 /* Flags in the BDCR register */ 617 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ 618 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ 619 #define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ 620 621 /* Flags in the RSR register */ 622 #define RCC_FLAG_RMVF ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_RMVF_Pos)) /*!< Remove reset flag */ 623 #define RCC_FLAG_PINRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos)) /*!< PIN reset flag */ 624 #define RCC_FLAG_BORRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos)) /*!< BOR reset flag */ 625 #define RCC_FLAG_SFTRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 626 #define RCC_FLAG_IWDGRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 627 #define RCC_FLAG_WWDGRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 628 #define RCC_FLAG_LPWRRST ((uint32_t)((RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 629 630 /** 631 * @} 632 */ 633 634 /** @defgroup RCC_Reset_Flag Reset Flag 635 * @{ 636 */ 637 #define RCC_RESET_FLAG_PIN RCC_RSR_PINRSTF /*!< PIN reset flag */ 638 #define RCC_RESET_FLAG_PWR RCC_RSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 639 #define RCC_RESET_FLAG_SW RCC_RSR_SFTRSTF /*!< Software Reset flag */ 640 #define RCC_RESET_FLAG_IWDG RCC_RSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 641 #define RCC_RESET_FLAG_WWDG RCC_RSR_WWDGRSTF /*!< Window watchdog reset flag */ 642 #define RCC_RESET_FLAG_LPWR RCC_RSR_LPWRRSTF /*!< Low power reset flag */ 643 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | RCC_RESET_FLAG_SW | \ 644 RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | RCC_RESET_FLAG_LPWR) 645 /** 646 * @} 647 */ 648 649 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 650 * @{ 651 */ 652 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */ 653 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 654 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 655 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 661 * @{ 662 */ 663 #define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U) /*!< HSI selection after wake-up from STOP */ 664 #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR1_STOPWUCK /*!< CSI selection after wake-up from STOP */ 665 /** 666 * @} 667 */ 668 669 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 670 * @{ 671 */ 672 #define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U) /*!< HSI kernel clock selection after wake-up from STOP */ 673 #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR1_STOPKERWUCK /*!< CSI kernel clock selection after wake-up from STOP */ 674 675 /** 676 * @} 677 */ 678 679 #if defined(RCC_SECCFGR_HSISEC) 680 /** @defgroup RCC_items RCC items 681 * @brief RCC items to configure attributes on 682 * @{ 683 */ 684 #define RCC_HSI RCC_SECCFGR_HSISEC 685 #define RCC_HSE RCC_SECCFGR_HSESEC 686 #define RCC_CSI RCC_SECCFGR_CSISEC 687 #define RCC_LSI RCC_SECCFGR_LSISEC 688 #define RCC_LSE RCC_SECCFGR_LSESEC 689 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 690 #define RCC_PRESC RCC_SECCFGR_PRESCSEC 691 #define RCC_PLL1 RCC_SECCFGR_PLL1SEC 692 #define RCC_PLL2 RCC_SECCFGR_PLL2SEC 693 #define RCC_PLL3 RCC_SECCFGR_PLL3SEC 694 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 695 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 696 #define RCC_CKPERSEL RCC_SECCFGR_CKPERSELSEC 697 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_CSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 698 RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ 699 RCC_PLL3|RCC_CKPERSEL|RCC_RMVF) 700 /** 701 * @} 702 */ 703 #endif /* RCC_SECCFGR_HSISEC */ 704 705 /** @defgroup RCC_attributes RCC attributes 706 * @brief RCC privilege/non-privilege and secure/non-secure attributes 707 * @{ 708 */ 709 #if defined(RCC_PRIVCFGR_NSPRIV) 710 #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ 711 #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ 712 #else 713 #define RCC_PRIV 0x00000001U /*!< Privilege attribute item */ 714 #define RCC_NPRIV 0x00000002U /*!< Non-privilege attribute item */ 715 #endif /* RCC_PRIVCFGR_NSPRIV */ 716 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 717 #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ 718 #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ 719 #endif /* __ARM_FEATURE_CMSE */ 720 /** 721 * @} 722 */ 723 724 /** 725 * @} 726 */ 727 728 /* Exported macros -----------------------------------------------------------*/ 729 730 /** @defgroup RCC_Exported_Macros RCC Exported Macros 731 * @{ 732 */ 733 734 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 735 * @brief Enable or disable the AHB1 peripheral clock. 736 * @note After reset, the peripheral clock (used for registers read/write access) 737 * is disabled and the application software has to enable this clock before 738 * using it. 739 * @{ 740 */ 741 742 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 743 __IO uint32_t tmpreg; \ 744 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 745 /* Delay after an RCC peripheral clock enabling */ \ 746 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 747 UNUSED(tmpreg); \ 748 } while(0) 749 750 #define __HAL_RCC_GPDMA2_CLK_ENABLE() do { \ 751 __IO uint32_t tmpreg; \ 752 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 753 /* Delay after an RCC peripheral clock enabling */ \ 754 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 755 UNUSED(tmpreg); \ 756 } while(0) 757 758 #if defined(CORDIC) 759 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 760 __IO uint32_t tmpreg; \ 761 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 762 /* Delay after an RCC peripheral clock enabling */ \ 763 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 764 UNUSED(tmpreg); \ 765 } while(0) 766 #endif /* CORDIC */ 767 768 #if defined(FMAC) 769 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 770 __IO uint32_t tmpreg; \ 771 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 772 /* Delay after an RCC peripheral clock enabling */ \ 773 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 774 UNUSED(tmpreg); \ 775 } while(0) 776 #endif /* FMAC */ 777 778 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 779 __IO uint32_t tmpreg; \ 780 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 781 /* Delay after an RCC peripheral clock enabling */ \ 782 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 783 UNUSED(tmpreg); \ 784 } while(0) 785 786 #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ 787 __IO uint32_t tmpreg; \ 788 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 789 /* Delay after an RCC peripheral clock enabling */ \ 790 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 791 UNUSED(tmpreg); \ 792 } while(0) 793 794 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 795 __IO uint32_t tmpreg; \ 796 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ 797 /* Delay after an RCC peripheral clock enabling */ \ 798 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ 799 UNUSED(tmpreg); \ 800 } while(0) 801 802 #if defined(ETH) 803 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 804 __IO uint32_t tmpreg; \ 805 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ 806 /* Delay after an RCC peripheral clock enabling */ \ 807 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ 808 UNUSED(tmpreg); \ 809 } while(0) 810 811 #define __HAL_RCC_ETHTX_CLK_ENABLE() do { \ 812 __IO uint32_t tmpreg; \ 813 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ 814 /* Delay after an RCC peripheral clock enabling */ \ 815 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ 816 UNUSED(tmpreg); \ 817 } while(0) 818 819 #define __HAL_RCC_ETHRX_CLK_ENABLE() do { \ 820 __IO uint32_t tmpreg; \ 821 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ 822 /* Delay after an RCC peripheral clock enabling */ \ 823 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ 824 UNUSED(tmpreg); \ 825 } while(0) 826 #endif /*ETH*/ 827 828 #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ 829 __IO uint32_t tmpreg; \ 830 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ 831 /* Delay after an RCC peripheral clock enabling */ \ 832 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ 833 UNUSED(tmpreg); \ 834 } while(0) 835 836 #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ 837 __IO uint32_t tmpreg; \ 838 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ 839 /* Delay after an RCC peripheral clock enabling */ \ 840 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ 841 UNUSED(tmpreg); \ 842 } while(0) 843 844 #if defined(DCACHE1) 845 #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ 846 __IO uint32_t tmpreg; \ 847 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 848 /* Delay after an RCC peripheral clock enabling */ \ 849 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 850 UNUSED(tmpreg); \ 851 } while(0) 852 #endif /* DCACHE1 */ 853 854 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 855 __IO uint32_t tmpreg; \ 856 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 857 /* Delay after an RCC peripheral clock enabling */ \ 858 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 859 UNUSED(tmpreg); \ 860 } while(0) 861 862 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 863 864 #define __HAL_RCC_GPDMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) 865 866 #if defined(CORDIC) 867 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) 868 #endif /* CORDIC */ 869 870 #if defined(FMAC) 871 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) 872 #endif /* FMAC */ 873 874 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) 875 876 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 877 878 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) 879 880 #if defined(ETH) 881 #define __HAL_RCC_ETH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) 882 883 #define __HAL_RCC_ETHTX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) 884 885 #define __HAL_RCC_ETHRX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) 886 #endif /*ETH*/ 887 888 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) 889 890 #define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) 891 892 #if defined(DCACHE1) 893 #define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) 894 #endif /* DCACHE1 */ 895 896 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) 897 /** 898 * @} 899 */ 900 901 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 902 * @brief Enable or disable the AHB2 peripheral clock. 903 * @note After reset, the peripheral clock (used for registers read/write access) 904 * is disabled and the application software has to enable this clock before 905 * using it. 906 * @{ 907 */ 908 909 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 910 __IO uint32_t tmpreg; \ 911 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 912 /* Delay after an RCC peripheral clock enabling */ \ 913 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 914 UNUSED(tmpreg); \ 915 } while(0) 916 917 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 918 __IO uint32_t tmpreg; \ 919 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 920 /* Delay after an RCC peripheral clock enabling */ \ 921 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 922 UNUSED(tmpreg); \ 923 } while(0) 924 925 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 926 __IO uint32_t tmpreg; \ 927 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 928 /* Delay after an RCC peripheral clock enabling */ \ 929 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 930 UNUSED(tmpreg); \ 931 } while(0) 932 933 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 934 __IO uint32_t tmpreg; \ 935 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 936 /* Delay after an RCC peripheral clock enabling */ \ 937 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 938 UNUSED(tmpreg); \ 939 } while(0) 940 941 #if defined(GPIOE) 942 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 943 __IO uint32_t tmpreg; \ 944 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 945 /* Delay after an RCC peripheral clock enabling */ \ 946 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 947 UNUSED(tmpreg); \ 948 } while(0) 949 #endif /* GPIOE */ 950 951 #if defined(GPIOF) 952 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 953 __IO uint32_t tmpreg; \ 954 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 955 /* Delay after an RCC peripheral clock enabling */ \ 956 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 957 UNUSED(tmpreg); \ 958 } while(0) 959 #endif /* GPIOF */ 960 961 #if defined(GPIOG) 962 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 963 __IO uint32_t tmpreg; \ 964 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 965 /* Delay after an RCC peripheral clock enabling */ \ 966 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 967 UNUSED(tmpreg); \ 968 } while(0) 969 #endif /* GPIOG */ 970 971 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 972 __IO uint32_t tmpreg; \ 973 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 974 /* Delay after an RCC peripheral clock enabling */ \ 975 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 976 UNUSED(tmpreg); \ 977 } while(0) 978 979 #if defined(GPIOI) 980 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 981 __IO uint32_t tmpreg; \ 982 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 983 /* Delay after an RCC peripheral clock enabling */ \ 984 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 985 UNUSED(tmpreg); \ 986 } while(0) 987 #endif /* GPIOI */ 988 989 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 990 __IO uint32_t tmpreg; \ 991 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ 992 /* Delay after an RCC peripheral clock enabling */ \ 993 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ 994 UNUSED(tmpreg); \ 995 } while(0) 996 997 #define __HAL_RCC_DAC12_CLK_ENABLE() do { \ 998 __IO uint32_t tmpreg; \ 999 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC12EN); \ 1000 /* Delay after an RCC peripheral clock enabling */ \ 1001 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC12EN); \ 1002 UNUSED(tmpreg); \ 1003 } while(0) 1004 1005 #if defined(DCMI) 1006 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 1007 __IO uint32_t tmpreg; \ 1008 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 1009 /* Delay after an RCC peripheral clock enabling */ \ 1010 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 1011 UNUSED(tmpreg); \ 1012 } while(0) 1013 1014 #define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility */ 1015 #endif /* DCMI */ 1016 1017 #if defined(AES) 1018 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 1019 __IO uint32_t tmpreg; \ 1020 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 1021 /* Delay after an RCC peripheral clock enabling */ \ 1022 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 1023 UNUSED(tmpreg); \ 1024 } while(0) 1025 #endif /* AES */ 1026 1027 #if defined(HASH) 1028 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1029 __IO uint32_t tmpreg; \ 1030 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 1031 /* Delay after an RCC peripheral clock enabling */ \ 1032 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 1033 UNUSED(tmpreg); \ 1034 } while(0) 1035 #endif /* HASH */ 1036 1037 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1038 __IO uint32_t tmpreg; \ 1039 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 1040 /* Delay after an RCC peripheral clock enabling */ \ 1041 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 1042 UNUSED(tmpreg); \ 1043 } while(0) 1044 1045 #if defined(PKA) 1046 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 1047 __IO uint32_t tmpreg; \ 1048 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 1049 /* Delay after an RCC peripheral clock enabling */ \ 1050 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 1051 UNUSED(tmpreg); \ 1052 } while(0) 1053 #endif /* PKA */ 1054 1055 #if defined(SAES) 1056 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 1057 __IO uint32_t tmpreg; \ 1058 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ 1059 /* Delay after an RCC peripheral clock enabling */ \ 1060 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ 1061 UNUSED(tmpreg); \ 1062 } while(0) 1063 #endif /* SAES */ 1064 1065 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 1066 __IO uint32_t tmpreg; \ 1067 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ 1068 /* Delay after an RCC peripheral clock enabling */ \ 1069 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ 1070 UNUSED(tmpreg); \ 1071 } while(0) 1072 #if defined(SRAM3_BASE) 1073 #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ 1074 __IO uint32_t tmpreg; \ 1075 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ 1076 /* Delay after an RCC peripheral clock enabling */ \ 1077 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ 1078 UNUSED(tmpreg); \ 1079 } while(0) 1080 #endif /* SRAM3_BASE */ 1081 1082 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 1083 1084 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 1085 1086 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 1087 1088 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 1089 1090 #if defined(GPIOE) 1091 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 1092 #endif /* GPIOE */ 1093 1094 #if defined(GPIOF) 1095 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 1096 #endif /* GPIOF */ 1097 1098 #if defined(GPIOG) 1099 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 1100 #endif /* GPIOG */ 1101 1102 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 1103 1104 #if defined(GPIOI) 1105 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) 1106 #endif /* GPIOI */ 1107 1108 #define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) 1109 1110 #define __HAL_RCC_DAC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC12EN) 1111 1112 #if defined(DCMI) 1113 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) 1114 #define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ 1115 #endif /* DCMI */ 1116 1117 #if defined(AES) 1118 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 1119 #endif /* AES */ 1120 1121 #if defined(HASH) 1122 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 1123 #endif /* HASH */ 1124 1125 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 1126 1127 #if defined(PKA) 1128 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 1129 #endif /* PKA */ 1130 1131 #if defined(SAES) 1132 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) 1133 #endif /* SAES */ 1134 1135 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) 1136 1137 #if defined(SRAM3_BASE) 1138 #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) 1139 #endif /* SRAM3_BASE */ 1140 /** 1141 * @} 1142 */ 1143 1144 /** @defgroup RCC_AHB4_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable 1145 * @brief Enable or disable the AHB4 peripheral clock. 1146 * @note After reset, the peripheral clock (used for registers read/write access) 1147 * is disabled and the application software has to enable this clock before 1148 * using it. 1149 * @{ 1150 */ 1151 1152 #if defined(OTFDEC1) 1153 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 1154 __IO uint32_t tmpreg; \ 1155 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \ 1156 /* Delay after an RCC peripheral clock enabling */ \ 1157 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \ 1158 UNUSED(tmpreg); \ 1159 } while(0) 1160 #endif /* OTFDEC1 */ 1161 1162 #if defined(SDMMC1) 1163 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1164 __IO uint32_t tmpreg; \ 1165 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ 1166 /* Delay after an RCC peripheral clock enabling */ \ 1167 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ 1168 UNUSED(tmpreg); \ 1169 } while(0) 1170 #endif /* SDMMC1 */ 1171 1172 #if defined(SDMMC2) 1173 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 1174 __IO uint32_t tmpreg; \ 1175 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ 1176 /* Delay after an RCC peripheral clock enabling */ \ 1177 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ 1178 UNUSED(tmpreg); \ 1179 } while(0) 1180 #endif /* SDMMC2 */ 1181 1182 #if defined(FMC_BASE) 1183 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1184 __IO uint32_t tmpreg; \ 1185 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ 1186 /* Delay after an RCC peripheral clock enabling */ \ 1187 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ 1188 UNUSED(tmpreg); \ 1189 } while(0) 1190 #endif /* FMC_BASE */ 1191 1192 #if defined(OCTOSPI1) 1193 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1194 __IO uint32_t tmpreg; \ 1195 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ 1196 /* Delay after an RCC peripheral clock enabling */ \ 1197 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ 1198 UNUSED(tmpreg); \ 1199 } while(0) 1200 #endif /* OCTOSPI1 */ 1201 1202 #if defined(OTFDEC1) 1203 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) 1204 #endif /* OTFDEC1 */ 1205 1206 #if defined(SDMMC1) 1207 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) 1208 #endif /* SDMMC1 */ 1209 1210 #if defined(SDMMC2) 1211 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) 1212 #endif /* SDMMC2 */ 1213 1214 #if defined(FMC_BASE) 1215 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) 1216 #endif /* FMC_BASE */ 1217 1218 #if defined(OCTOSPI1) 1219 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) 1220 #endif /* OCTOSPI1 */ 1221 1222 /** 1223 * @} 1224 */ 1225 1226 1227 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1228 * @brief Enable or disable the APB1 peripheral clock. 1229 * @note After reset, the peripheral clock (used for registers read/write access) 1230 * is disabled and the application software has to enable this clock before 1231 * using it. 1232 * @{ 1233 */ 1234 1235 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1236 __IO uint32_t tmpreg; \ 1237 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \ 1238 /* Delay after an RCC peripheral clock enabling */ \ 1239 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \ 1240 UNUSED(tmpreg); \ 1241 } while(0) 1242 1243 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1244 __IO uint32_t tmpreg; \ 1245 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \ 1246 /* Delay after an RCC peripheral clock enabling */ \ 1247 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \ 1248 UNUSED(tmpreg); \ 1249 } while(0) 1250 1251 #if defined(TIM4) 1252 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1253 __IO uint32_t tmpreg; \ 1254 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \ 1255 /* Delay after an RCC peripheral clock enabling */ \ 1256 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \ 1257 UNUSED(tmpreg); \ 1258 } while(0) 1259 #endif /* TIM4 */ 1260 1261 #if defined(TIM5) 1262 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1263 __IO uint32_t tmpreg; \ 1264 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \ 1265 /* Delay after an RCC peripheral clock enabling */ \ 1266 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \ 1267 UNUSED(tmpreg); \ 1268 } while(0) 1269 #endif /* TIM5 */ 1270 1271 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1272 __IO uint32_t tmpreg; \ 1273 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \ 1274 /* Delay after an RCC peripheral clock enabling */ \ 1275 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \ 1276 UNUSED(tmpreg); \ 1277 } while(0) 1278 1279 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1280 __IO uint32_t tmpreg; \ 1281 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \ 1282 /* Delay after an RCC peripheral clock enabling */ \ 1283 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \ 1284 UNUSED(tmpreg); \ 1285 } while(0) 1286 1287 #if defined(TIM12) 1288 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1289 __IO uint32_t tmpreg; \ 1290 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ 1291 /* Delay after an RCC peripheral clock enabling */ \ 1292 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ 1293 UNUSED(tmpreg); \ 1294 } while(0) 1295 1296 #endif /* TIM12 */ 1297 1298 #if defined(TIM13) 1299 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1300 __IO uint32_t tmpreg; \ 1301 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ 1302 /* Delay after an RCC peripheral clock enabling */ \ 1303 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ 1304 UNUSED(tmpreg); \ 1305 } while(0) 1306 #endif /* TIM13 */ 1307 1308 #if defined(TIM14) 1309 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1310 __IO uint32_t tmpreg; \ 1311 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ 1312 /* Delay after an RCC peripheral clock enabling */ \ 1313 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ 1314 UNUSED(tmpreg); \ 1315 } while(0) 1316 #endif /* TIM14 */ 1317 1318 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1319 __IO uint32_t tmpreg; \ 1320 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \ 1321 /* Delay after an RCC peripheral clock enabling */ \ 1322 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \ 1323 UNUSED(tmpreg); \ 1324 } while(0) 1325 1326 #if defined(OPAMP1) 1327 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1328 __IO uint32_t tmpreg; \ 1329 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ 1330 /* Delay after an RCC peripheral clock enabling */ \ 1331 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ 1332 UNUSED(tmpreg); \ 1333 } while(0) 1334 #endif /* OPAMP1 */ 1335 1336 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1337 __IO uint32_t tmpreg; \ 1338 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \ 1339 /* Delay after an RCC peripheral clock enabling */ \ 1340 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \ 1341 UNUSED(tmpreg); \ 1342 } while(0) 1343 1344 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1345 __IO uint32_t tmpreg; \ 1346 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \ 1347 /* Delay after an RCC peripheral clock enabling */ \ 1348 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \ 1349 UNUSED(tmpreg); \ 1350 } while(0) 1351 1352 #if defined(COMP1) 1353 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 1354 __IO uint32_t tmpreg; \ 1355 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \ 1356 /* Delay after an RCC peripheral clock enabling */ \ 1357 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \ 1358 UNUSED(tmpreg); \ 1359 } while(0) 1360 #endif /* COMP1 */ 1361 1362 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1363 __IO uint32_t tmpreg; \ 1364 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ 1365 /* Delay after an RCC peripheral clock enabling */ \ 1366 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ 1367 UNUSED(tmpreg); \ 1368 } while(0) 1369 1370 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1371 __IO uint32_t tmpreg; \ 1372 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ 1373 /* Delay after an RCC peripheral clock enabling */ \ 1374 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ 1375 UNUSED(tmpreg); \ 1376 } while(0) 1377 1378 #if defined(UART4) 1379 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1380 __IO uint32_t tmpreg; \ 1381 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ 1382 /* Delay after an RCC peripheral clock enabling */ \ 1383 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ 1384 UNUSED(tmpreg); \ 1385 } while(0) 1386 #endif /* UART4 */ 1387 1388 #if defined(UART5) 1389 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1390 __IO uint32_t tmpreg; \ 1391 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ 1392 /* Delay after an RCC peripheral clock enabling */ \ 1393 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ 1394 UNUSED(tmpreg); \ 1395 } while(0) 1396 #endif /* UART5 */ 1397 1398 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1399 __IO uint32_t tmpreg; \ 1400 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ 1401 /* Delay after an RCC peripheral clock enabling */ \ 1402 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ 1403 UNUSED(tmpreg); \ 1404 } while(0) 1405 1406 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1407 __IO uint32_t tmpreg; \ 1408 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ 1409 /* Delay after an RCC peripheral clock enabling */ \ 1410 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ 1411 UNUSED(tmpreg); \ 1412 } while(0) 1413 1414 #define __HAL_RCC_I3C1_CLK_ENABLE() do { \ 1415 __IO uint32_t tmpreg; \ 1416 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ 1417 /* Delay after an RCC peripheral clock enabling */ \ 1418 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ 1419 UNUSED(tmpreg); \ 1420 } while(0) 1421 1422 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1423 __IO uint32_t tmpreg; \ 1424 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ 1425 /* Delay after an RCC peripheral clock enabling */ \ 1426 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ 1427 UNUSED(tmpreg); \ 1428 } while(0) 1429 1430 #if defined(USART6) 1431 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 1432 __IO uint32_t tmpreg; \ 1433 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ 1434 /* Delay after an RCC peripheral clock enabling */ \ 1435 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ 1436 UNUSED(tmpreg); \ 1437 } while(0) 1438 #endif /* USART6 */ 1439 1440 #if defined(USART10) 1441 #define __HAL_RCC_USART10_CLK_ENABLE() do { \ 1442 __IO uint32_t tmpreg; \ 1443 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ 1444 /* Delay after an RCC peripheral clock enabling */ \ 1445 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ 1446 UNUSED(tmpreg); \ 1447 } while(0) 1448 #endif /* USART10 */ 1449 1450 #if defined(USART11) 1451 #define __HAL_RCC_USART11_CLK_ENABLE() do { \ 1452 __IO uint32_t tmpreg; \ 1453 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ 1454 /* Delay after an RCC peripheral clock enabling */ \ 1455 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ 1456 UNUSED(tmpreg); \ 1457 } while(0) 1458 #endif /* USART11 */ 1459 1460 #if defined(CEC) 1461 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 1462 __IO uint32_t tmpreg; \ 1463 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ 1464 /* Delay after an RCC peripheral clock enabling */ \ 1465 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ 1466 UNUSED(tmpreg); \ 1467 } while(0) 1468 #endif /* CEC */ 1469 1470 #if defined(UART7) 1471 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1472 __IO uint32_t tmpreg; \ 1473 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ 1474 /* Delay after an RCC peripheral clock enabling */ \ 1475 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ 1476 UNUSED(tmpreg); \ 1477 } while(0) 1478 #endif /* UART7 */ 1479 1480 #if defined(UART8) 1481 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1482 __IO uint32_t tmpreg; \ 1483 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ 1484 /* Delay after an RCC peripheral clock enabling */ \ 1485 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ 1486 UNUSED(tmpreg); \ 1487 } while(0) 1488 #endif /* UART8 */ 1489 1490 #if defined(UART9) 1491 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 1492 __IO uint32_t tmpreg; \ 1493 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ 1494 /* Delay after an RCC peripheral clock enabling */ \ 1495 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ 1496 UNUSED(tmpreg); \ 1497 } while(0) 1498 #endif /* UART9 */ 1499 1500 #if defined(UART12) 1501 #define __HAL_RCC_UART12_CLK_ENABLE() do { \ 1502 __IO uint32_t tmpreg; \ 1503 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ 1504 /* Delay after an RCC peripheral clock enabling */ \ 1505 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ 1506 UNUSED(tmpreg); \ 1507 } while(0) 1508 #endif /* UART12 */ 1509 1510 #define __HAL_RCC_DTS_CLK_ENABLE() do { \ 1511 __IO uint32_t tmpreg; \ 1512 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ 1513 /* Delay after an RCC peripheral clock enabling */ \ 1514 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ 1515 UNUSED(tmpreg); \ 1516 } while(0) 1517 1518 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1519 __IO uint32_t tmpreg; \ 1520 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ 1521 /* Delay after an RCC peripheral clock enabling */ \ 1522 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ 1523 UNUSED(tmpreg); \ 1524 } while(0) 1525 1526 1527 #if defined(FDCAN2) 1528 #define __HAL_RCC_FDCAN12_CLK_ENABLE() do { \ 1529 __IO uint32_t tmpreg; \ 1530 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN12EN); \ 1531 /* Delay after an RCC peripheral clock enabling */ \ 1532 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN12EN); \ 1533 UNUSED(tmpreg); \ 1534 } while(0) 1535 #else 1536 #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ 1537 __IO uint32_t tmpreg; \ 1538 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN1EN); \ 1539 /* Delay after an RCC peripheral clock enabling */ \ 1540 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN1EN); \ 1541 UNUSED(tmpreg); \ 1542 } while(0) 1543 #endif /* FDCAN2*/ 1544 1545 #if defined(UCPD1) 1546 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ 1547 __IO uint32_t tmpreg; \ 1548 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \ 1549 /* Delay after an RCC peripheral clock enabling */ \ 1550 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \ 1551 UNUSED(tmpreg); \ 1552 } while(0) 1553 #endif /* UCPD1 */ 1554 1555 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) 1556 1557 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) 1558 1559 #if defined(TIM4) 1560 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) 1561 #endif /* TIM4 */ 1562 1563 #if defined(TIM5) 1564 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) 1565 #endif /* TIM5 */ 1566 1567 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) 1568 1569 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) 1570 1571 #if defined(TIM12) 1572 #define __HAL_RCC_TIM12_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) 1573 #endif /* TIM12 */ 1574 1575 #if defined(TIM13) 1576 #define __HAL_RCC_TIM13_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) 1577 #endif /* TIM13 */ 1578 1579 #if defined(TIM14) 1580 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) 1581 #endif /* TIM14 */ 1582 1583 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) 1584 1585 #if defined(OPAMP1) 1586 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) 1587 #endif /* OPAMP1 */ 1588 1589 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) 1590 1591 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) 1592 1593 #if defined(COMP1) 1594 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) 1595 #endif /* COMP1 */ 1596 1597 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) 1598 1599 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) 1600 1601 #if defined(UART4) 1602 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) 1603 #endif /* UART4 */ 1604 1605 #if defined(UART5) 1606 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) 1607 #endif /* UART5 */ 1608 1609 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) 1610 1611 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) 1612 1613 #define __HAL_RCC_I3C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) 1614 1615 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) 1616 1617 #if defined(USART6) 1618 #define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) 1619 #endif /* USART6 */ 1620 1621 #if defined(USART10) 1622 #define __HAL_RCC_USART10_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) 1623 #endif /* USART10 */ 1624 1625 #if defined(USART11) 1626 #define __HAL_RCC_USART11_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) 1627 #endif /* USART11 */ 1628 1629 #if defined(CEC) 1630 #define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) 1631 #endif /* CEC */ 1632 1633 #if defined(UART7) 1634 #define __HAL_RCC_UART7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) 1635 #endif /* UART7 */ 1636 1637 #if defined(UART8) 1638 #define __HAL_RCC_UART8_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) 1639 #endif /* UART8 */ 1640 1641 1642 #if defined(UART9) 1643 #define __HAL_RCC_UART9_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) 1644 #endif /* UART9 */ 1645 1646 #if defined(UART12) 1647 #define __HAL_RCC_UART12_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) 1648 #endif /* UART12 */ 1649 1650 #define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR , RCC_APB1HENR_DTSEN) 1651 1652 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) 1653 1654 #if defined(FDCAN2) 1655 #define __HAL_RCC_FDCAN12_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN12EN) 1656 #else 1657 #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN1EN) 1658 #endif /* FDCAN2 */ 1659 1660 #if defined(UCPD1) 1661 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) 1662 #endif /* UCPD1 */ 1663 1664 /** 1665 * @} 1666 */ 1667 1668 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1669 * @brief Enable or disable the APB2 peripheral clock. 1670 * @note After reset, the peripheral clock (used for registers read/write access) 1671 * is disabled and the application software has to enable this clock before 1672 * using it. 1673 * @{ 1674 */ 1675 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1676 __IO uint32_t tmpreg; \ 1677 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1678 /* Delay after an RCC peripheral clock enabling */ \ 1679 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1680 UNUSED(tmpreg); \ 1681 } while(0) 1682 1683 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1684 __IO uint32_t tmpreg; \ 1685 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1686 /* Delay after an RCC peripheral clock enabling */ \ 1687 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1688 UNUSED(tmpreg); \ 1689 } while(0) 1690 1691 #if defined(TIM8) 1692 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1693 __IO uint32_t tmpreg; \ 1694 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1695 /* Delay after an RCC peripheral clock enabling */ \ 1696 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1697 UNUSED(tmpreg); \ 1698 } while(0) 1699 #endif /* TIM8 */ 1700 1701 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1702 __IO uint32_t tmpreg; \ 1703 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1704 /* Delay after an RCC peripheral clock enabling */ \ 1705 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1706 UNUSED(tmpreg); \ 1707 } while(0) 1708 1709 #if defined(TIM15) 1710 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1711 __IO uint32_t tmpreg; \ 1712 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1713 /* Delay after an RCC peripheral clock enabling */ \ 1714 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1715 UNUSED(tmpreg); \ 1716 } while(0) 1717 #endif /* TIM15 */ 1718 1719 #if defined(TIM16) 1720 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1721 __IO uint32_t tmpreg; \ 1722 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1723 /* Delay after an RCC peripheral clock enabling */ \ 1724 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1725 UNUSED(tmpreg); \ 1726 } while(0) 1727 #endif /* TIM16 */ 1728 1729 #if defined(TIM17) 1730 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1731 __IO uint32_t tmpreg; \ 1732 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1733 /* Delay after an RCC peripheral clock enabling */ \ 1734 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1735 UNUSED(tmpreg); \ 1736 } while(0) 1737 #endif /* TIM17 */ 1738 1739 #if defined(SPI4) 1740 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1741 __IO uint32_t tmpreg; \ 1742 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ 1743 /* Delay after an RCC peripheral clock enabling */ \ 1744 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ 1745 UNUSED(tmpreg); \ 1746 } while(0) 1747 #endif /* SPI4 */ 1748 1749 #if defined(SPI6) 1750 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 1751 __IO uint32_t tmpreg; \ 1752 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \ 1753 /* Delay after an RCC peripheral clock enabling */ \ 1754 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \ 1755 UNUSED(tmpreg); \ 1756 } while(0) 1757 #endif /* SPI6 */ 1758 1759 #if defined(SAI1) 1760 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1761 __IO uint32_t tmpreg; \ 1762 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1763 /* Delay after an RCC peripheral clock enabling */ \ 1764 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1765 UNUSED(tmpreg); \ 1766 } while(0) 1767 #endif /* SAI1 */ 1768 1769 #if defined(SAI2) 1770 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1771 __IO uint32_t tmpreg; \ 1772 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1773 /* Delay after an RCC peripheral clock enabling */ \ 1774 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1775 UNUSED(tmpreg); \ 1776 } while(0) 1777 #endif /* SAI2 */ 1778 1779 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1780 __IO uint32_t tmpreg; \ 1781 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1782 /* Delay after an RCC peripheral clock enabling */ \ 1783 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1784 UNUSED(tmpreg); \ 1785 } while(0) 1786 1787 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1788 1789 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1790 1791 #if defined(TIM8) 1792 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1793 #endif /* TIM8 */ 1794 1795 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1796 1797 #if defined(TIM15) 1798 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1799 #endif /* TIM15 */ 1800 1801 #if defined(TIM16) 1802 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1803 #endif /* TIM16 */ 1804 1805 #if defined(TIM17) 1806 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1807 #endif /* TIM17 */ 1808 1809 #if defined(SPI4) 1810 #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) 1811 #endif /* SPI4 */ 1812 1813 #if defined(SPI6) 1814 #define __HAL_RCC_SPI6_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) 1815 #endif /* SPI6 */ 1816 1817 #if defined(SAI1) 1818 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1819 #endif /* SAI1 */ 1820 1821 #if defined(SAI2) 1822 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1823 #endif /* SAI2 */ 1824 1825 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) 1826 1827 /** 1828 * @} 1829 */ 1830 1831 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1832 * @brief Enable or disable the APB3 peripheral clock. 1833 * @note After reset, the peripheral clock (used for registers read/write access) 1834 * is disabled and the application software has to enable this clock before 1835 * using it. 1836 * @{ 1837 */ 1838 #define __HAL_RCC_SBS_CLK_ENABLE() do { \ 1839 __IO uint32_t tmpreg; \ 1840 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \ 1841 /* Delay after an RCC peripheral clock enabling */ \ 1842 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \ 1843 UNUSED(tmpreg); \ 1844 } while(0) 1845 1846 #if defined(SPI5) 1847 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 1848 __IO uint32_t tmpreg; \ 1849 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \ 1850 /* Delay after an RCC peripheral clock enabling */ \ 1851 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \ 1852 UNUSED(tmpreg); \ 1853 } while(0) 1854 #endif /* SPI5 */ 1855 1856 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1857 __IO uint32_t tmpreg; \ 1858 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1859 /* Delay after an RCC peripheral clock enabling */ \ 1860 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1861 UNUSED(tmpreg); \ 1862 } while(0) 1863 1864 #if defined(I2C3) 1865 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1866 __IO uint32_t tmpreg; \ 1867 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1868 /* Delay after an RCC peripheral clock enabling */ \ 1869 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1870 UNUSED(tmpreg); \ 1871 } while(0) 1872 #endif /* I2C3 */ 1873 1874 #if defined(I2C4) 1875 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1876 __IO uint32_t tmpreg; \ 1877 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \ 1878 /* Delay after an RCC peripheral clock enabling */ \ 1879 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \ 1880 UNUSED(tmpreg); \ 1881 } while(0) 1882 #endif /* I2C4 */ 1883 1884 #if defined(I3C2) 1885 #define __HAL_RCC_I3C2_CLK_ENABLE() do { \ 1886 __IO uint32_t tmpreg; \ 1887 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \ 1888 /* Delay after an RCC peripheral clock enabling */ \ 1889 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \ 1890 UNUSED(tmpreg); \ 1891 } while(0) 1892 #endif /* I3C2 */ 1893 1894 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1895 __IO uint32_t tmpreg; \ 1896 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1897 /* Delay after an RCC peripheral clock enabling */ \ 1898 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1899 UNUSED(tmpreg); \ 1900 } while(0) 1901 1902 #if defined(LPTIM3) 1903 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1904 __IO uint32_t tmpreg; \ 1905 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1906 /* Delay after an RCC peripheral clock enabling */ \ 1907 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1908 UNUSED(tmpreg); \ 1909 } while(0) 1910 #endif /* LPTIM3 */ 1911 1912 #if defined(LPTIM4) 1913 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 1914 __IO uint32_t tmpreg; \ 1915 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1916 /* Delay after an RCC peripheral clock enabling */ \ 1917 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1918 UNUSED(tmpreg); \ 1919 } while(0) 1920 #endif /* LPTIM4 */ 1921 1922 #if defined(LPTIM5) 1923 #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ 1924 __IO uint32_t tmpreg; \ 1925 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \ 1926 /* Delay after an RCC peripheral clock enabling */ \ 1927 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \ 1928 UNUSED(tmpreg); \ 1929 } while(0) 1930 #endif /* LPTIM5 */ 1931 1932 #if defined(LPTIM6) 1933 #define __HAL_RCC_LPTIM6_CLK_ENABLE() do { \ 1934 __IO uint32_t tmpreg; \ 1935 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \ 1936 /* Delay after an RCC peripheral clock enabling */ \ 1937 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \ 1938 UNUSED(tmpreg); \ 1939 } while(0) 1940 #endif /* LPTIM6 */ 1941 1942 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 1943 __IO uint32_t tmpreg; \ 1944 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1945 /* Delay after an RCC peripheral clock enabling */ \ 1946 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1947 UNUSED(tmpreg); \ 1948 } while(0) 1949 1950 #define __HAL_RCC_RTC_CLK_ENABLE() do { \ 1951 __IO uint32_t tmpreg; \ 1952 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1953 /* Delay after an RCC peripheral clock enabling */ \ 1954 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1955 UNUSED(tmpreg); \ 1956 } while(0) 1957 1958 #define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) 1959 1960 #if defined(SPI5) 1961 #define __HAL_RCC_SPI5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) 1962 #endif /* SPI5 */ 1963 1964 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) 1965 1966 #if defined(I2C3) 1967 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) 1968 #endif /* I2C3 */ 1969 1970 #if defined(I2C4) 1971 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) 1972 #endif /* I2C4 */ 1973 1974 #if defined(I3C2) 1975 #define __HAL_RCC_I3C2_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) 1976 #endif /* I3C2 */ 1977 1978 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) 1979 1980 #if defined(LPTIM3) 1981 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) 1982 #endif /* LPTIM3 */ 1983 1984 #if defined(LPTIM4) 1985 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) 1986 #endif /* LPTIM4 */ 1987 1988 #if defined(LPTIM5) 1989 #define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) 1990 #endif /* LPTIM5 */ 1991 1992 #if defined(LPTIM6) 1993 #define __HAL_RCC_LPTIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) 1994 #endif /* LPTIM6 */ 1995 1996 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) 1997 1998 #define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) 1999 2000 /** 2001 * @} 2002 */ 2003 2004 /** @defgroup RCC_AHB_APB_Branch_Clock_Disable AHB APB Branch Clock Disable Clear Disable 2005 * @brief Disable or clear Disable the AHBx/APBx branch clock for all AHBx/APBx peripherals. 2006 * @note It is recommended to disable the clock of all peripherals (by writing 0 in 2007 * the AHBxENR/APBxENR register) before Disabling the corresponding Bus Branch clock. 2008 * Some peripheral bus clocks are not affected by branch clock disabling as IWDG (APB1), 2009 * SRAM2/SRAM3 (AHB2) and FLITF/BKRAM/ICACHE/DCACHE/SRAM1 (AHB1). 2010 * @{ 2011 */ 2012 2013 #define __HAL_RCC_AHB1_CLK_DISABLE() do { \ 2014 __IO uint32_t tmpreg; \ 2015 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 2016 /* Delay after AHB peripherals bus clocks branch disable */ \ 2017 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 2018 UNUSED(tmpreg); \ 2019 } while(0) 2020 2021 #define __HAL_RCC_AHB2_CLK_DISABLE() do { \ 2022 __IO uint32_t tmpreg; \ 2023 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \ 2024 /* Delay after AHB peripherals bus clocks branch disable */ \ 2025 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \ 2026 UNUSED(tmpreg); \ 2027 } while(0) 2028 2029 #if defined(AHB4PERIPH_BASE) 2030 #define __HAL_RCC_AHB4_CLK_DISABLE() do { \ 2031 __IO uint32_t tmpreg; \ 2032 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \ 2033 /* Delay after AHB peripherals bus clocks branch disable */ \ 2034 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \ 2035 UNUSED(tmpreg); \ 2036 } while(0) 2037 #endif /* AHB4PERIPH_BASE */ 2038 2039 #define __HAL_RCC_APB1_CLK_DISABLE() do { \ 2040 __IO uint32_t tmpreg; \ 2041 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 2042 /* Delay after APB peripherals bus clocks branch disable */ \ 2043 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 2044 UNUSED(tmpreg); \ 2045 } while(0) 2046 2047 #define __HAL_RCC_APB2_CLK_DISABLE() do { \ 2048 __IO uint32_t tmpreg; \ 2049 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 2050 /* Delay after APB peripherals bus clocks branch disable */ \ 2051 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 2052 UNUSED(tmpreg); \ 2053 } while(0) 2054 2055 #define __HAL_RCC_APB3_CLK_DISABLE() do { \ 2056 __IO uint32_t tmpreg; \ 2057 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \ 2058 /* Delay after APB peripherals bus clocks branch disable */ \ 2059 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \ 2060 UNUSED(tmpreg); \ 2061 } while(0) 2062 2063 2064 #define __HAL_RCC_AHB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) 2065 2066 #define __HAL_RCC_AHB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) 2067 2068 #if defined(AHB4PERIPH_BASE) 2069 #define __HAL_RCC_AHB4_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) 2070 #endif /* AHB4PERIPH_BASE */ 2071 2072 #define __HAL_RCC_APB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) 2073 2074 #define __HAL_RCC_APB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) 2075 2076 #define __HAL_RCC_APB3_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) 2077 2078 /** 2079 * @} 2080 */ 2081 2082 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 2083 * @brief Check whether the AHB1 peripheral clock is enabled or not. 2084 * @note After reset, the peripheral clock (used for registers read/write access) 2085 * is disabled and the application software has to enable this clock before 2086 * using it. 2087 * @{ 2088 */ 2089 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 2090 2091 #define __HAL_RCC_GPDMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) != 0U) 2092 2093 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) != 0U) 2094 2095 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 2096 2097 #if defined(CORDIC) 2098 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) 2099 #endif /* CORDIC */ 2100 2101 #if defined(FMAC) 2102 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) 2103 #endif /* FMAC */ 2104 2105 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) 2106 2107 #if defined(ETH) 2108 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) != 0U) 2109 2110 #define __HAL_RCC_ETHTX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) != 0U) 2111 2112 #define __HAL_RCC_ETHRX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) != 0U) 2113 #endif /*ETH*/ 2114 2115 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) != 0U) 2116 2117 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) != 0U) 2118 2119 #if defined(DCACHE1) 2120 #define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) 2121 #endif /* DCACHE1 */ 2122 2123 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) 2124 2125 2126 #define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) 2127 2128 #define __HAL_RCC_GPDMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) == 0U) 2129 2130 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) == 0U) 2131 2132 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 2133 2134 #if defined(CORDIC) 2135 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) 2136 #endif /* CORDIC */ 2137 2138 #if defined(FMAC) 2139 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) 2140 #endif /* FMAC */ 2141 2142 #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) 2143 2144 #if defined(ETH) 2145 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) == 0U) 2146 2147 #define __HAL_RCC_ETHTX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) == 0U) 2148 2149 #define __HAL_RCC_ETHRX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) == 0U) 2150 #endif /*ETH*/ 2151 2152 #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) == 0U) 2153 2154 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) == 0U) 2155 2156 #if defined(DCACHE1) 2157 #define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) 2158 #endif /* DCACHE1 */ 2159 2160 #define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) 2161 /** 2162 * @} 2163 */ 2164 2165 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 2166 * @brief Check whether the AHB2 peripheral clock is enabled or not. 2167 * @note After reset, the peripheral clock (used for registers read/write access) 2168 * is disabled and the application software has to enable this clock before 2169 * using it. 2170 * @{ 2171 */ 2172 2173 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 2174 2175 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 2176 2177 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 2178 2179 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 2180 2181 #if defined(GPIOE) 2182 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 2183 #endif /* GPIOE */ 2184 2185 #if defined(GPIOF) 2186 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 2187 #endif /* GPIOF */ 2188 2189 #if defined(GPIOG) 2190 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 2191 #endif /* GPIOG */ 2192 2193 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 2194 2195 #if defined(GPIOI) 2196 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) 2197 #endif /* GPIOI */ 2198 2199 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U) 2200 2201 #define __HAL_RCC_DAC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC12EN) != 0U) 2202 2203 #if defined(DCMI) 2204 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) != 0U) 2205 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility */ 2206 #endif /* DCMI */ 2207 2208 #if defined(AES) 2209 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 2210 #endif /* AES */ 2211 2212 #if defined(HASH) 2213 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 2214 #endif /* HASH */ 2215 2216 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 2217 2218 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 2219 2220 #if defined(SAES) 2221 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U) 2222 #endif /*SAES*/ 2223 2224 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) 2225 2226 #if defined(SRAM3_BASE) 2227 #define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) != 0U) 2228 #endif /* SRAM3_BASE */ 2229 2230 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 2231 2232 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 2233 2234 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 2235 2236 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 2237 2238 #if defined(GPIOE) 2239 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 2240 #endif /* GPIOE */ 2241 2242 #if defined(GPIOF) 2243 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 2244 #endif /* GPIOF */ 2245 2246 #if defined(GPIOG) 2247 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 2248 #endif /* GPIOG */ 2249 2250 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 2251 2252 #if defined(GPIOI) 2253 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) 2254 #endif /* GPIOI */ 2255 2256 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U) 2257 2258 #define __HAL_RCC_DAC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC12EN) == 0U) 2259 2260 #if defined(DCMI) 2261 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) == 0U) 2262 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility */ 2263 #endif /* DCMI */ 2264 2265 #if defined(AES) 2266 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 2267 #endif /* AES */ 2268 2269 #if defined(HASH) 2270 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 2271 #endif /* HASH */ 2272 2273 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 2274 2275 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) 2276 2277 #if defined(SAES) 2278 #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) == 0U) 2279 #endif /* SAES */ 2280 2281 #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) == 0U) 2282 2283 #if defined(SRAM3_BASE) 2284 #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) == 0U) 2285 #endif /* SRAM3_BASE */ 2286 /** 2287 * @} 2288 */ 2289 2290 /** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable_Status AHB4 Peripheral Clock Enabled or Disabled Status 2291 * @brief Check whether the AHB4 peripheral clock is enabled or not. 2292 * @note After reset, the peripheral clock (used for registers read/write access) 2293 * is disabled and the application software has to enable this clock before 2294 * using it. 2295 * @{ 2296 */ 2297 2298 #if defined(OTFDEC1) 2299 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) != 0U) 2300 #endif /* OTFDEC1 */ 2301 2302 #if defined(OCTOSPI1) 2303 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) != 0U) 2304 #endif /* OCTOSPI1 */ 2305 2306 #if defined(SDMMC1) 2307 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) != 0U) 2308 #endif /* SDMMC1 */ 2309 2310 #if defined(SDMMC2) 2311 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) != 0U) 2312 #endif /* SDMMC2 */ 2313 2314 #if defined(FMC_BASE) 2315 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) != 0U) 2316 #endif /* FMC_BASE */ 2317 2318 2319 #if defined(OTFDEC1) 2320 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) == 0U) 2321 #endif /* OTFDEC1 */ 2322 2323 #if defined(OCTOSPI1) 2324 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) == 0U) 2325 #endif /* OCTOSPI1 */ 2326 2327 #if defined(SDMMC1) 2328 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == 0U) 2329 #endif /* SDMMC1 */ 2330 2331 #if defined(SDMMC2) 2332 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) == 0U) 2333 #endif /* SDMMC2 */ 2334 2335 #if defined(FMC_BASE) 2336 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) == 0U) 2337 #endif /* FMC_BASE */ 2338 2339 /** 2340 * @} 2341 */ 2342 2343 2344 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 2345 * @brief Check whether the APB1 peripheral clock is enabled or not. 2346 * @note After reset, the peripheral clock (used for registers read/write access) 2347 * is disabled and the application software has to enable this clock before 2348 * using it. 2349 * @{ 2350 */ 2351 2352 2353 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) != 0U) 2354 2355 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) != 0U) 2356 2357 #if defined(TIM4) 2358 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) != 0U) 2359 #endif /* TIM4 */ 2360 2361 #if defined(TIM5) 2362 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) != 0U) 2363 #endif /* TIM5 */ 2364 2365 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) != 0U) 2366 2367 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) != 0U) 2368 2369 #if defined(TIM12) 2370 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) != 0U) 2371 #endif /* TIM12 */ 2372 2373 #if defined(TIM13) 2374 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) != 0U) 2375 #endif /* TIM13 */ 2376 2377 #if defined(TIM14) 2378 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) != 0U) 2379 #endif /* TIM14 */ 2380 2381 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) != 0U) 2382 2383 #if defined(OPAMP1) 2384 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) != 0U) 2385 #endif /* OPAMP1 */ 2386 2387 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) != 0U) 2388 2389 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) != 0U) 2390 2391 #if defined(COMP1) 2392 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) != 0U) 2393 #endif /* COMP1 */ 2394 2395 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) != 0U) 2396 2397 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) != 0U) 2398 2399 #if defined(UART4) 2400 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) != 0U) 2401 #endif /* UART4 */ 2402 2403 #if defined(UART5) 2404 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) != 0U) 2405 #endif /* UART5 */ 2406 2407 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) != 0U) 2408 2409 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) != 0U) 2410 2411 #define __HAL_RCC_I3C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) != 0U) 2412 2413 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) != 0U) 2414 2415 #if defined(USART6) 2416 #define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) != 0U) 2417 #endif /* USART6 */ 2418 2419 #if defined(USART10) 2420 #define __HAL_RCC_USART10_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) != 0U) 2421 #endif /* USART10 */ 2422 2423 #if defined(USART11) 2424 #define __HAL_RCC_USART11_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) != 0U) 2425 #endif /* USART11 */ 2426 2427 #if defined(CEC) 2428 #define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) != 0U) 2429 #endif /* CEC */ 2430 2431 #if defined(UART7) 2432 #define __HAL_RCC_UART7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) != 0U) 2433 #endif /* UART7 */ 2434 2435 #if defined(UART8) 2436 #define __HAL_RCC_UART8_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) != 0U) 2437 #endif /* UART8 */ 2438 2439 2440 #if defined(UART9) 2441 #define __HAL_RCC_UART9_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) != 0U) 2442 #endif /* UART9 */ 2443 2444 #if defined(UART12) 2445 #define __HAL_RCC_UART12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) != 0U) 2446 #endif /* UART12 */ 2447 2448 #define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) != 0U) 2449 2450 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) != 0U) 2451 2452 #if defined (FDCAN2) 2453 #define __HAL_RCC_FDCAN12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN12EN) != 0U) 2454 #else 2455 #define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN1EN) != 0U) 2456 #endif /*FDCAN2*/ 2457 2458 #if defined(UCPD1) 2459 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) != 0U) 2460 #endif /* UCPD1 */ 2461 2462 2463 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) == 0U) 2464 2465 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) == 0U) 2466 2467 #if defined(TIM4) 2468 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) == 0U) 2469 #endif /* TIM4 */ 2470 2471 #if defined(TIM5) 2472 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) == 0U) 2473 #endif /* TIM5 */ 2474 2475 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) == 0U) 2476 2477 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) == 0U) 2478 2479 #if defined(TIM12) 2480 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) == 0U) 2481 #endif /* TIM12 */ 2482 2483 #if defined(TIM13) 2484 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) == 0U) 2485 #endif /* TIM13 */ 2486 2487 #if defined(TIM14) 2488 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) == 0U) 2489 #endif /* TIM14 */ 2490 2491 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) == 0U) 2492 2493 #if defined(OPAMP1) 2494 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) == 0U) 2495 #endif /* OPAMP1 */ 2496 2497 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) == 0U) 2498 2499 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) == 0U) 2500 2501 #if defined(COMP1) 2502 #define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) == 0U) 2503 #endif /* COMP1 */ 2504 2505 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) == 0U) 2506 2507 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) == 0U) 2508 2509 #if defined(UART4) 2510 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) == 0U) 2511 #endif /* UART4 */ 2512 2513 #if defined(UART5) 2514 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) == 0U) 2515 #endif /* UART5 */ 2516 2517 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) == 0U) 2518 2519 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) == 0U) 2520 2521 #define __HAL_RCC_I3C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) == 0U) 2522 2523 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) == 0U) 2524 2525 #if defined(USART6) 2526 #define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) == 0U) 2527 #endif /* USART6 */ 2528 2529 #if defined(USART10) 2530 #define __HAL_RCC_USART10_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) == 0U) 2531 #endif /* USART10 */ 2532 2533 #if defined(USART11) 2534 #define __HAL_RCC_USART11_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) == 0U) 2535 #endif /* USART11 */ 2536 2537 #if defined(CEC) 2538 #define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) == 0U) 2539 #endif /* CEC */ 2540 2541 #if defined(UART7) 2542 #define __HAL_RCC_UART7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) == 0U) 2543 #endif /* UART7 */ 2544 2545 #if defined(UART8) 2546 #define __HAL_RCC_UART8_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) == 0U) 2547 #endif /* UART8 */ 2548 2549 2550 #if defined(UART9) 2551 #define __HAL_RCC_UART9_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) == 0U) 2552 #endif /* UART9 */ 2553 2554 #if defined(UART12) 2555 #define __HAL_RCC_UART12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) == 0U) 2556 #endif /* UART12 */ 2557 2558 #define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) == 0U) 2559 2560 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) == 0U) 2561 2562 #if defined(FDCAN2) 2563 #define __HAL_RCC_FDCAN12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN12EN) == 0U) 2564 #else 2565 #define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCAN1EN) == 0U) 2566 #endif /*FDCAN2*/ 2567 2568 #if defined(UCPD1) 2569 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) == 0U) 2570 #endif /* UCPD1 */ 2571 /** 2572 * @} 2573 */ 2574 2575 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2576 * @brief Check whether the APB2 peripheral clock is enabled or not. 2577 * @note After reset, the peripheral clock (used for registers read/write access) 2578 * is disabled and the application software has to enable this clock before 2579 * using it. 2580 * @{ 2581 */ 2582 2583 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2584 2585 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2586 2587 #if defined(TIM8) 2588 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2589 #endif /* TIM8 */ 2590 2591 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2592 2593 #if defined(TIM15) 2594 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2595 #endif /* TIM15 */ 2596 2597 #if defined(TIM16) 2598 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2599 #endif /* TIM16 */ 2600 2601 #if defined(TIM17) 2602 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2603 #endif /* TIM17 */ 2604 2605 #if defined(SPI4) 2606 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) 2607 #endif /* SPI4 */ 2608 2609 #if defined(SPI6) 2610 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) != 0U) 2611 #endif /* SPI6 */ 2612 2613 #if defined(SAI1) 2614 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2615 #endif /* SAI1 */ 2616 2617 #if defined(SAI2) 2618 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2619 #endif /* SAI2 */ 2620 2621 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) 2622 2623 2624 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2625 2626 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2627 2628 #if defined(TIM8) 2629 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2630 #endif /* TIM8 */ 2631 2632 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2633 2634 #if defined(TIM15) 2635 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2636 #endif /* TIM15 */ 2637 2638 #if defined(TIM16) 2639 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2640 #endif /* TIM16 */ 2641 2642 #if defined(TIM17) 2643 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2644 #endif /* TIM17 */ 2645 2646 #if defined(SPI4) 2647 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) 2648 #endif /* SPI4 */ 2649 2650 #if defined(SPI6) 2651 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) == 0U) 2652 #endif /* SPI6 */ 2653 2654 #if defined(SAI1) 2655 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2656 #endif /* SAI1 */ 2657 2658 #if defined(SAI2) 2659 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2660 #endif /* SAI2 */ 2661 2662 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) 2663 /** 2664 * @} 2665 */ 2666 2667 /** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 2668 * @brief Check whether the APB3 peripheral clock is enabled or not. 2669 * @note After reset, the peripheral clock (used for registers read/write access) 2670 * is disabled and the application software has to enable this clock before 2671 * using it. 2672 * @{ 2673 */ 2674 2675 #define __HAL_RCC_SBS_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) != 0U) 2676 2677 #if defined(SPI5) 2678 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) != 0U) 2679 #endif /* SPI5 */ 2680 2681 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) 2682 2683 #if defined(I2C3) 2684 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) 2685 #endif /* I2C3 */ 2686 2687 #if defined(I2C4) 2688 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) != 0U) 2689 #endif /* I2C4 */ 2690 2691 #if defined(I3C2) 2692 #define __HAL_RCC_I3C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) != 0U) 2693 #endif /* I3C2 */ 2694 2695 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) 2696 2697 #if defined(LPTIM3) 2698 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) 2699 #endif /* LPTIM3 */ 2700 2701 #if defined(LPTIM4) 2702 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) 2703 #endif /* LPTIM4 */ 2704 2705 #if defined(LPTIM5) 2706 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) != 0U) 2707 #endif /* LPTIM5 */ 2708 2709 #if defined(LPTIM6) 2710 #define __HAL_RCC_LPTIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) != 0U) 2711 #endif /* LPTIM6 */ 2712 2713 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) 2714 2715 #define __HAL_RCC_RTC_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) 2716 2717 2718 #define __HAL_RCC_SBS_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) == 0U) 2719 2720 #if defined(SPI5) 2721 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) == 0U) 2722 #endif /* SPI5 */ 2723 2724 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) 2725 2726 #if defined(I2C3) 2727 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) 2728 #endif /* I2C3 */ 2729 2730 #if defined(I2C4) 2731 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) == 0U) 2732 #endif /* I2C4 */ 2733 2734 #if defined(I3C2) 2735 #define __HAL_RCC_I3C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) == 0U) 2736 #endif /* I3C2 */ 2737 2738 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) 2739 2740 #if defined(LPTIM3) 2741 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) 2742 #endif /* LPTIM3 */ 2743 2744 #if defined(LPTIM4) 2745 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) 2746 #endif /* LPTIM4 */ 2747 2748 #if defined(LPTIM5) 2749 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) == 0U) 2750 #endif /* LPTIM5 */ 2751 2752 #if defined(LPTIM6) 2753 #define __HAL_RCC_LPTIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) == 0U) 2754 #endif /* LPTIM6 */ 2755 2756 #define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) 2757 2758 #define __HAL_RCC_RTC_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) 2759 2760 /** 2761 * @} 2762 */ 2763 2764 /** @defgroup RCC_AHB_APB_Branch_Clock_Disable_Status AHB APB Branch Clock Disabled Status 2765 * @brief Check whether the AHBx/APBx branch clock for all AHBx/APBx peripherals is disabled or not. 2766 * @note It is recommended to disable the clock of all peripherals (by writing 0 in 2767 * the AHBxENR/APBxENR register) before Disabling the corresponding Bus Branch clock. 2768 * Some peripheral bus clocks are not affected by branch clock disabling as IWDG (APB1), 2769 * SRAM2/SRAM3 (AHB2) and FLITF/BKRAM/ICACHE/DCACHE/SRAM1 (AHB1). 2770 * @{ 2771 */ 2772 2773 #define __HAL_RCC_AHB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) != 0U) 2774 2775 #define __HAL_RCC_AHB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) != 0U) 2776 2777 #if defined(AHB4PERIPH_BASE) 2778 #define __HAL_RCC_AHB4_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) != 0U) 2779 #endif /* AHB4PERIPH_BASE */ 2780 2781 #define __HAL_RCC_APB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) != 0U) 2782 2783 #define __HAL_RCC_APB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) != 0U) 2784 2785 #define __HAL_RCC_APB3_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) != 0U) 2786 2787 /** 2788 * @} 2789 */ 2790 2791 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2792 * @brief Force or release AHB1 peripheral reset. 2793 * @{ 2794 */ 2795 2796 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x010AD003U) 2797 2798 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2799 2800 #define __HAL_RCC_GPDMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) 2801 2802 #if defined(CORDIC) 2803 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2804 #endif /* CORDIC */ 2805 2806 #if defined(FMAC) 2807 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2808 #endif /* FMAC */ 2809 2810 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2811 2812 #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2813 2814 #if defined(ETH) 2815 #define __HAL_RCC_ETH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) 2816 #endif /* ETH */ 2817 2818 #define __HAL_RCC_GTZC1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) 2819 2820 2821 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2822 2823 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2824 2825 #define __HAL_RCC_GPDMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) 2826 2827 #if defined(CORDIC) 2828 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2829 #endif /* CORDIC */ 2830 2831 #if defined(FMAC) 2832 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2833 #endif /* FMAC */ 2834 2835 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2836 2837 #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2838 2839 #if defined(ETH) 2840 #define __HAL_RCC_ETH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) 2841 #endif /* ETH */ 2842 2843 #define __HAL_RCC_GTZC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) 2844 2845 /** 2846 * @} 2847 */ 2848 2849 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2850 * @brief Force or release AHB2 peripheral reset. 2851 * @{ 2852 */ 2853 2854 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x001F1DFFU) 2855 2856 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2857 2858 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2859 2860 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2861 2862 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2863 2864 #if defined(GPIOE) 2865 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2866 #endif /* GPIOE */ 2867 2868 #if defined(GPIOF) 2869 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2870 #endif /* GPIOF */ 2871 2872 #if defined(GPIOG) 2873 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2874 #endif /* GPIOG */ 2875 2876 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2877 2878 #if defined(GPIOI) 2879 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2880 #endif /* GPIOI */ 2881 2882 #define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) 2883 2884 #define __HAL_RCC_DAC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC12RST) 2885 2886 #if defined(DCMI) 2887 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST) 2888 #define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility */ 2889 #endif /* DCMI */ 2890 2891 #if defined(AES) 2892 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2893 #endif /* AES */ 2894 2895 #if defined(HASH) 2896 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2897 #endif /* HASH */ 2898 2899 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2900 2901 #if defined(PKA) 2902 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2903 #endif /* PKA */ 2904 2905 #if defined(SAES) 2906 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) 2907 #endif /* SAES*/ 2908 2909 2910 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 2911 2912 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2913 2914 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2915 2916 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2917 2918 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2919 2920 #if defined(GPIOE) 2921 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2922 #endif /* GPIOE */ 2923 2924 #if defined(GPIOF) 2925 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2926 #endif /* GPIOF */ 2927 2928 #if defined(GPIOG) 2929 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2930 #endif /* GPIOG */ 2931 2932 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2933 2934 #if defined(GPIOG) 2935 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2936 #endif /* GPIOI */ 2937 2938 #define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) 2939 2940 #define __HAL_RCC_DAC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC12RST) 2941 2942 #if defined(DCMI) 2943 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST) 2944 #define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility */ 2945 #endif /* DCMI */ 2946 2947 #if defined(AES) 2948 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2949 #endif /* AES */ 2950 2951 #if defined(HASH) 2952 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2953 #endif /* HASH */ 2954 2955 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2956 2957 #if defined(PKA) 2958 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2959 #endif /* PKA */ 2960 2961 #if defined(SAES) 2962 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) 2963 #endif /* SAES*/ 2964 2965 /** 2966 * @} 2967 */ 2968 2969 /** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset 2970 * @brief Force or release AHB4 peripheral reset. 2971 * @{ 2972 */ 2973 2974 #if defined(FMC_BASE) 2975 #define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00111880U) 2976 #endif /* FMC_BASE */ 2977 2978 #if defined(OTFDEC1) 2979 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST) 2980 #endif /* OTFDEC1 */ 2981 2982 #if defined(SDMMC1) 2983 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) 2984 #endif /* SDMMC1 */ 2985 2986 #if defined(SDMMC2) 2987 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) 2988 #endif /* SDMMC2 */ 2989 2990 #if defined(FMC_BASE) 2991 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST) 2992 #endif /* FMC_BASE */ 2993 2994 #if defined(OCTOSPI1) 2995 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) 2996 #endif /* OCTOSPI1 */ 2997 2998 2999 #if defined(FMC_BASE) 3000 #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) 3001 #endif /* FMC_BASE */ 3002 3003 #if defined(OTFDEC1) 3004 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST) 3005 #endif /* OTFDEC1 */ 3006 3007 #if defined(SDMMC1) 3008 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) 3009 #endif /* SDMMC1 */ 3010 3011 #if defined(SDMMC2) 3012 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) 3013 #endif /* SDMMC2 */ 3014 3015 #if defined(FMC_BASE) 3016 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST) 3017 #endif /* FMC_BASE */ 3018 3019 #if defined(OCTOSPI1) 3020 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) 3021 #endif /* OCTOSPI1 */ 3022 3023 /** 3024 * @} 3025 */ 3026 3027 3028 3029 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 3030 * @brief Force or release APB1 peripheral reset. 3031 * @{ 3032 */ 3033 3034 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 3035 WRITE_REG(RCC->APB1LRSTR, 0xDFFEC1FFU); \ 3036 WRITE_REG(RCC->APB1HRSTR, 0x4080062BU); \ 3037 } while(0) 3038 3039 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST) 3040 3041 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST) 3042 3043 #if defined(TIM4) 3044 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST) 3045 #endif /* TIM4 */ 3046 3047 #if defined(TIM5) 3048 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST) 3049 #endif /* TIM5 */ 3050 3051 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST) 3052 3053 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) 3054 3055 #if defined(TIM12) 3056 #define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) 3057 #endif /* TIM12 */ 3058 3059 #if defined(TIM13) 3060 #define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) 3061 #endif /* TIM13 */ 3062 3063 #if defined(TIM14) 3064 #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) 3065 #endif /* TIM14 */ 3066 3067 #if defined(OPAMP1) 3068 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) 3069 #endif /* OPAMP1 */ 3070 3071 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) 3072 3073 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST) 3074 3075 #if defined(COMP1) 3076 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST) 3077 #endif /* COMP1 */ 3078 3079 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST) 3080 3081 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST) 3082 3083 #if defined(UART4) 3084 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST) 3085 #endif /* UART4 */ 3086 3087 #if defined(UART5) 3088 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST) 3089 #endif /* UART5 */ 3090 3091 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST) 3092 3093 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST) 3094 3095 #define __HAL_RCC_I3C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST) 3096 3097 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST) 3098 3099 #if defined(USART6) 3100 #define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST) 3101 #endif /* USART6 */ 3102 3103 #if defined(USART10) 3104 #define __HAL_RCC_USART10_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST) 3105 #endif /* USART10 */ 3106 3107 #if defined(USART11) 3108 #define __HAL_RCC_USART11_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST) 3109 #endif /* USART11 */ 3110 3111 #if defined(CEC) 3112 #define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST) 3113 #endif /* CEC */ 3114 3115 #if defined(UART7) 3116 #define __HAL_RCC_UART7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST) 3117 #endif /* UART7 */ 3118 3119 #if defined(UART8) 3120 #define __HAL_RCC_UART8_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST) 3121 #endif /* UART8 */ 3122 3123 3124 #if defined(UART9) 3125 #define __HAL_RCC_UART9_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST) 3126 #endif /* UART9 */ 3127 3128 #if defined(UART12) 3129 #define __HAL_RCC_UART12_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST) 3130 #endif /* UART12 */ 3131 3132 #define __HAL_RCC_DTS_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST) 3133 3134 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST) 3135 3136 #if defined(FDCAN2) 3137 #define __HAL_RCC_FDCAN12_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCAN12RST) 3138 #else 3139 #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCAN1RST) 3140 #endif /* FDCAN2 */ 3141 3142 #if defined(UCPD1) 3143 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST) 3144 #endif /* UCPD1 */ 3145 3146 3147 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 3148 WRITE_REG(RCC->APB1LRSTR, 0x00000000U); \ 3149 WRITE_REG(RCC->APB1HRSTR, 0x00000000U); \ 3150 } while(0) 3151 3152 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST) 3153 3154 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST) 3155 3156 #if defined(TIM4) 3157 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST) 3158 #endif /* TIM4 */ 3159 3160 #if defined(TIM5) 3161 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST) 3162 #endif /* TIM5 */ 3163 3164 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST) 3165 3166 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) 3167 3168 #if defined(TIM12) 3169 #define __HAL_RCC_TIM12_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) 3170 #endif /* TIM12 */ 3171 3172 #if defined(TIM13) 3173 #define __HAL_RCC_TIM13_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) 3174 #endif /* TIM13 */ 3175 3176 #if defined(TIM14) 3177 #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) 3178 #endif /* TIM14 */ 3179 3180 #if defined(OPAMP1) 3181 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) 3182 #endif /* OPAMP1 */ 3183 3184 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) 3185 3186 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST) 3187 3188 #if defined(COMP1) 3189 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST) 3190 #endif /* COMP1 */ 3191 3192 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST) 3193 3194 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST) 3195 3196 #if defined(UART4) 3197 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST) 3198 #endif /* UART4 */ 3199 3200 #if defined(UART5) 3201 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST) 3202 #endif /* UART5 */ 3203 3204 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST) 3205 3206 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST) 3207 3208 #define __HAL_RCC_I3C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST) 3209 3210 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST) 3211 3212 #if defined(USART6) 3213 #define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST) 3214 #endif /* USART6 */ 3215 3216 #if defined(USART10) 3217 #define __HAL_RCC_USART10_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST) 3218 #endif /* USART10 */ 3219 3220 #if defined(USART11) 3221 #define __HAL_RCC_USART11_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST) 3222 #endif /* USART11 */ 3223 3224 #if defined(CEC) 3225 #define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST) 3226 #endif /* CEC */ 3227 3228 #if defined(UART7) 3229 #define __HAL_RCC_UART7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST) 3230 #endif /* UART7 */ 3231 3232 #if defined(UART8) 3233 #define __HAL_RCC_UART8_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST) 3234 #endif /* UART8 */ 3235 3236 3237 #if defined(UART9) 3238 #define __HAL_RCC_UART9_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST) 3239 #endif /* UART9 */ 3240 3241 #if defined(UART12) 3242 #define __HAL_RCC_UART12_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST) 3243 #endif /* UART12 */ 3244 3245 #define __HAL_RCC_DTS_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST) 3246 3247 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST) 3248 3249 #if defined(FDCAN2) 3250 #define __HAL_RCC_FDCAN12_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCAN12RST) 3251 #else 3252 #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCAN1RST) 3253 #endif /* FDCAN2 */ 3254 3255 #if defined(UCPD1) 3256 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST) 3257 #endif /* UCPD1 */ 3258 3259 /** 3260 * @} 3261 */ 3262 3263 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 3264 * @brief Force or release APB2 peripheral reset. 3265 * @{ 3266 */ 3267 3268 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x017F7800U) 3269 3270 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3271 3272 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3273 3274 #if defined(TIM8) 3275 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3276 #endif /* TIM8 */ 3277 3278 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3279 3280 #if defined(TIM15) 3281 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3282 #endif /* TIM15 */ 3283 3284 #if defined(TIM16) 3285 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3286 #endif /* TIM16 */ 3287 3288 #if defined(TIM17) 3289 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3290 #endif /* TIM17 */ 3291 3292 #if defined(SPI4) 3293 #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 3294 #endif /* SPI4 */ 3295 3296 #if defined(SPI6) 3297 #define __HAL_RCC_SPI6_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST) 3298 #endif /* SPI6 */ 3299 3300 #if defined(SAI1) 3301 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3302 #endif /* SAI1 */ 3303 3304 #if defined(SAI2) 3305 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3306 #endif /* SAI2 */ 3307 3308 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3309 3310 3311 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 3312 3313 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3314 3315 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3316 3317 #if defined(TIM8) 3318 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3319 #endif /* TIM8 */ 3320 3321 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3322 3323 #if defined(TIM15) 3324 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3325 #endif /* TIM15 */ 3326 3327 #if defined(TIM16) 3328 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3329 #endif /* TIM16 */ 3330 3331 #if defined(TIM17) 3332 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3333 #endif /* TIM17 */ 3334 3335 #if defined(SPI4) 3336 #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 3337 #endif /* SPI4 */ 3338 3339 #if defined(SPI6) 3340 #define __HAL_RCC_SPI6_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST) 3341 #endif /* SPI6 */ 3342 3343 #if defined(SAI1) 3344 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3345 #endif /* SAI1 */ 3346 3347 #if defined(SAI2) 3348 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3349 #endif /* SAI2 */ 3350 3351 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3352 3353 /** 3354 * @} 3355 */ 3356 3357 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 3358 * @brief Force or release APB3 peripheral reset. 3359 * @{ 3360 */ 3361 3362 #define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x001008E2U) 3363 3364 #define __HAL_RCC_SBS_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SBSRST) 3365 3366 #if defined(SPI5) 3367 #define __HAL_RCC_SPI5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST) 3368 #endif /* SPI5 */ 3369 3370 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3371 3372 #if defined(I2C3) 3373 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3374 #endif /* I2C3 */ 3375 3376 #if defined(I2C4) 3377 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST) 3378 #endif /* I2C4 */ 3379 3380 #if defined(I3C2) 3381 #define __HAL_RCC_I3C2_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST) 3382 #endif /* I3C2 */ 3383 3384 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3385 3386 #if defined(LPTIM3) 3387 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3388 #endif /* LPTIM3 */ 3389 3390 #if defined(LPTIM4) 3391 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3392 #endif /* LPTIM4 */ 3393 3394 #if defined(LPTIM5) 3395 #define __HAL_RCC_LPTIM5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST) 3396 #endif /* LPTIM5 */ 3397 3398 #if defined(LPTIM6) 3399 #define __HAL_RCC_LPTIM6_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST) 3400 #endif /* LPTIM6 */ 3401 3402 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3403 3404 #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) 3405 3406 #define __HAL_RCC_SBS_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SBSRST) 3407 3408 #if defined(SPI5) 3409 #define __HAL_RCC_SPI5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST) 3410 #endif /* SPI5 */ 3411 3412 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3413 3414 #if defined(I2C3) 3415 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3416 #endif /* I2C3 */ 3417 3418 #if defined(I2C4) 3419 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST) 3420 #endif /* I2C4 */ 3421 3422 #if defined(I3C2) 3423 #define __HAL_RCC_I3C2_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST) 3424 #endif /* I3C2 */ 3425 3426 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3427 3428 #if defined(LPTIM3) 3429 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3430 #endif /* LPTIM3 */ 3431 3432 #if defined(LPTIM4) 3433 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3434 #endif /* LPTIM4 */ 3435 3436 #if defined(LPTIM5) 3437 #define __HAL_RCC_LPTIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST) 3438 #endif /* LPTIM5 */ 3439 3440 #if defined(LPTIM6) 3441 #define __HAL_RCC_LPTIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST) 3442 #endif /* LPTIM6 */ 3443 3444 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3445 3446 /** 3447 * @} 3448 */ 3449 3450 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 3451 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3452 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3453 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3454 * @{ 3455 */ 3456 3457 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) 3458 3459 #define __HAL_RCC_GPDMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPEN) 3460 3461 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN) 3462 3463 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN) 3464 3465 #if defined(CORDIC) 3466 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPEN) 3467 #endif /* CORDIC */ 3468 3469 #if defined(FMAC) 3470 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN) 3471 #endif /* FMAC */ 3472 3473 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPEN) 3474 3475 #if defined(ETH) 3476 #define __HAL_RCC_ETH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN) 3477 3478 #define __HAL_RCC_ETHTX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) 3479 3480 #define __HAL_RCC_ETHRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) 3481 #endif /* ETH */ 3482 3483 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) 3484 3485 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPEN) 3486 3487 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPEN) 3488 3489 #if defined(DCACHE1) 3490 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LPEN) 3491 #endif /* DCACHE1 */ 3492 3493 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN) 3494 3495 3496 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) 3497 3498 #define __HAL_RCC_GPDMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPEN) 3499 3500 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN) 3501 3502 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN) 3503 3504 #if defined(CORDIC) 3505 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPEN) 3506 #endif /* CORDIC */ 3507 3508 #if defined(FMAC) 3509 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN) 3510 #endif /* FMAC */ 3511 3512 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPEN) 3513 3514 #if defined(ETH) 3515 #define __HAL_RCC_ETH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN) 3516 3517 #define __HAL_RCC_ETHTX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) 3518 3519 #define __HAL_RCC_ETHRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) 3520 #endif /* ETH */ 3521 3522 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) 3523 3524 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPEN) 3525 3526 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPEN) 3527 3528 #if defined(DCACHE1) 3529 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LPEN) 3530 #endif /* DCACHE1 */ 3531 3532 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN) 3533 3534 /** 3535 * @} 3536 */ 3537 3538 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 3539 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3540 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3541 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3542 * @{ 3543 */ 3544 3545 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN) 3546 3547 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN) 3548 3549 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN) 3550 3551 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN) 3552 3553 #if defined(GPIOE) 3554 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN) 3555 #endif /* GPIOE */ 3556 3557 #if defined(GPIOF) 3558 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN) 3559 #endif /* GPIOF */ 3560 3561 #if defined(GPIOG) 3562 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN) 3563 #endif /* GPIOG */ 3564 3565 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN) 3566 3567 #if defined(GPIOI) 3568 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN) 3569 #endif /* GPIOI */ 3570 3571 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADC12LPEN) 3572 3573 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC12LPEN) 3574 3575 #if defined(DCMI) 3576 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSILPEN) 3577 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility */ 3578 #endif /* DCMI */ 3579 3580 #if defined(AES) 3581 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); 3582 #endif /* AES */ 3583 3584 #if defined(HASH) 3585 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN) 3586 #endif /* HASH */ 3587 3588 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN) 3589 3590 #if defined(PKA) 3591 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN) 3592 #endif /*PKA*/ 3593 3594 #if defined(SAES) 3595 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN) 3596 #endif /* AES */ 3597 3598 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) 3599 3600 #if defined(SRAM3_BASE) 3601 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN) 3602 #endif /* SRAM3_BASE */ 3603 3604 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN) 3605 3606 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN) 3607 3608 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN) 3609 3610 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN) 3611 3612 #if defined(GPIOE) 3613 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN) 3614 #endif /* GPIOE */ 3615 3616 #if defined(GPIOF) 3617 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN) 3618 #endif /* GPIOF */ 3619 3620 #if defined(GPIOG) 3621 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN) 3622 #endif /* GPIOG */ 3623 3624 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN) 3625 3626 #if defined(GPIOI) 3627 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN) 3628 #endif /* GPIOI */ 3629 3630 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADC12LPEN) 3631 3632 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC12LPEN) 3633 3634 #if defined(DCMI) 3635 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSILPEN) 3636 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility */ 3637 #endif /* DCMI */ 3638 3639 #if defined(AES) 3640 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); 3641 #endif /* AES */ 3642 3643 #if defined(HASH) 3644 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN) 3645 #endif /* HASH */ 3646 3647 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN) 3648 3649 #if defined(PKA) 3650 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN) 3651 #endif /*PKA*/ 3652 3653 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN) 3654 3655 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) 3656 3657 #if defined(SRAM3_BASE) 3658 #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN) 3659 #endif /* SRAM3_BASE */ 3660 /** 3661 * @} 3662 */ 3663 3664 /** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable 3665 * @brief Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 3666 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3667 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3668 * @{ 3669 */ 3670 3671 #if defined(OTFDEC1) 3672 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) 3673 #endif /* OTFDEC1 */ 3674 3675 #if defined(SDMMC1) 3676 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) 3677 #endif /* SDMMC1*/ 3678 3679 #if defined(SDMMC2) 3680 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPEN) 3681 #endif /* SDMMC2*/ 3682 3683 #if defined(FMC_BASE) 3684 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN) 3685 #endif /* FMC_BASE */ 3686 3687 #if defined(OCTOSPI1) 3688 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) 3689 #endif /* OCTOSPI1 */ 3690 3691 #if defined(OTFDEC1) 3692 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) 3693 #endif /* OTFDEC1 */ 3694 3695 #if defined(SDMMC1) 3696 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) 3697 #endif /* SDMMC1*/ 3698 3699 #if defined(SDMMC2) 3700 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPEN) 3701 #endif /* SDMMC2*/ 3702 3703 #if defined(FMC_BASE) 3704 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN) 3705 #endif /* FMC_BASE */ 3706 3707 #if defined(OCTOSPI1) 3708 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) 3709 #endif /* OCTOSPI1 */ 3710 3711 /** 3712 * @} 3713 */ 3714 3715 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 3716 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3717 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3718 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3719 * @{ 3720 */ 3721 3722 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN) 3723 3724 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN) 3725 3726 #if defined(TIM4) 3727 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN) 3728 #endif /* TIM4 */ 3729 3730 #if defined(TIM5) 3731 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN) 3732 #endif /* TIM5 */ 3733 3734 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN) 3735 3736 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN) 3737 3738 #if defined(TIM12) 3739 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN) 3740 #endif /* TIM12 */ 3741 3742 #if defined(TIM13) 3743 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN) 3744 #endif /* TIM13 */ 3745 3746 #if defined(TIM14) 3747 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN) 3748 #endif /* TIM14 */ 3749 3750 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN) 3751 3752 #if defined(OPAMP1) 3753 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN) 3754 #endif /* OPAMP1 */ 3755 3756 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN) 3757 3758 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) 3759 3760 #if defined(COMP1) 3761 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) 3762 #endif /* COMP1 */ 3763 3764 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) 3765 3766 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN) 3767 3768 #if defined(UART4) 3769 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN) 3770 #endif /* UART4 */ 3771 3772 #if defined(UART5) 3773 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN) 3774 #endif /* UART5 */ 3775 3776 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN) 3777 3778 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN) 3779 3780 #define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN) 3781 3782 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN) 3783 3784 #if defined(USART6) 3785 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN) 3786 #endif /* USART6 */ 3787 3788 #if defined(USART10) 3789 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPEN) 3790 #endif /* USART10 */ 3791 3792 #if defined(USART11) 3793 #define __HAL_RCC_USART11_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPEN) 3794 #endif /* USART11 */ 3795 3796 #if defined(CEC) 3797 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN) 3798 #endif /* CEC */ 3799 3800 #if defined(UART7) 3801 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN) 3802 #endif /* UART7 */ 3803 3804 #if defined(UART8) 3805 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN) 3806 #endif /* UART8 */ 3807 3808 3809 #if defined(UART9) 3810 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN) 3811 #endif /* UART9 */ 3812 3813 #if defined(UART12) 3814 #define __HAL_RCC_UART12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) 3815 #endif /* UART12 */ 3816 3817 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) 3818 3819 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN) 3820 3821 #if defined(FDCAN2) 3822 #define __HAL_RCC_FDCAN12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCAN12LPEN) 3823 #else 3824 #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCAN1LPEN) 3825 #endif /* FDCAN2*/ 3826 3827 #if defined(UCPD1) 3828 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN) 3829 #endif /* UCPD1 */ 3830 3831 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN) 3832 3833 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN) 3834 3835 #if defined(TIM4) 3836 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN) 3837 #endif /* TIM4 */ 3838 3839 #if defined(TIM5) 3840 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN) 3841 #endif /* TIM5 */ 3842 3843 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN) 3844 3845 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN) 3846 3847 #if defined(TIM12) 3848 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN) 3849 #endif /* TIM12 */ 3850 3851 #if defined(TIM13) 3852 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN) 3853 #endif /* TIM12 */ 3854 3855 #if defined(TIM14) 3856 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN) 3857 #endif /* TIM14 */ 3858 3859 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN) 3860 3861 #if defined(OPAMP1) 3862 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN) 3863 #endif /* OPAMP1 */ 3864 3865 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN) 3866 3867 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) 3868 3869 #if defined(COMP1) 3870 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) 3871 #endif /* COMP1 */ 3872 3873 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) 3874 3875 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN) 3876 3877 #if defined(UART4) 3878 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN) 3879 #endif /* UART4 */ 3880 3881 #if defined(UART5) 3882 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN) 3883 #endif /* UART5 */ 3884 3885 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN) 3886 3887 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN) 3888 3889 #define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN) 3890 3891 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN) 3892 3893 #if defined(USART6) 3894 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN) 3895 #endif /* USART6 */ 3896 3897 #if defined(USART10) 3898 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPEN) 3899 #endif /* USART10 */ 3900 3901 #if defined(USART11) 3902 #define __HAL_RCC_USART11_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPEN) 3903 #endif /* USART11 */ 3904 3905 #if defined(CEC) 3906 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN) 3907 #endif /* CEC */ 3908 3909 #if defined(UART7) 3910 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN) 3911 #endif /* UART7 */ 3912 3913 #if defined(UART8) 3914 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN) 3915 #endif /* UART8 */ 3916 3917 3918 #if defined(UART9) 3919 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN) 3920 #endif /* UART9 */ 3921 3922 #if defined(UART12) 3923 #define __HAL_RCC_UART12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) 3924 #endif /* UART12 */ 3925 3926 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) 3927 3928 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN) 3929 3930 #if defined(FDCAN2) 3931 #define __HAL_RCC_FDCAN12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCAN12LPEN) 3932 #else 3933 #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCAN1LPEN) 3934 #endif /* FDCAN2*/ 3935 3936 #if defined(UCPD1) 3937 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN) 3938 #endif /* UCPD1 */ 3939 3940 /** 3941 * @} 3942 */ 3943 3944 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3945 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3946 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3947 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3948 * @{ 3949 */ 3950 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) 3951 3952 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) 3953 3954 #if defined(TIM8) 3955 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN) 3956 #endif /* TIM8 */ 3957 3958 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) 3959 3960 #if defined(TIM15) 3961 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) 3962 #endif /* TIM15 */ 3963 3964 #if defined(TIM16) 3965 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) 3966 #endif /* TIM16 */ 3967 3968 #if defined(TIM17) 3969 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) 3970 #endif /* TIM17 */ 3971 3972 #if defined(SPI4) 3973 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) 3974 #endif /* SPI4 */ 3975 3976 #if defined(SPI6) 3977 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN) 3978 #endif /* SPI6 */ 3979 3980 #if defined(SAI1) 3981 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) 3982 #endif /* SAI1 */ 3983 3984 #if defined(SAI2) 3985 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) 3986 #endif /* SAI2 */ 3987 3988 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) 3989 3990 3991 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) 3992 3993 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) 3994 3995 #if defined(TIM8) 3996 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN) 3997 #endif /* TIM8 */ 3998 3999 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) 4000 4001 #if defined(TIM15) 4002 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) 4003 #endif /* TIM15 */ 4004 4005 #if defined(TIM16) 4006 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) 4007 #endif /* TIM16 */ 4008 4009 #if defined(TIM17) 4010 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) 4011 #endif /* TIM17 */ 4012 4013 #if defined(SPI4) 4014 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) 4015 #endif /* SPI4 */ 4016 4017 #if defined(SPI6) 4018 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN) 4019 #endif /* SPI6 */ 4020 4021 #if defined(SAI1) 4022 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) 4023 #endif /* SAI1 */ 4024 4025 #if defined(SAI2) 4026 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) 4027 #endif /* SAI2 */ 4028 4029 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) 4030 4031 /** 4032 * @} 4033 */ 4034 4035 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 4036 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. 4037 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4038 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4039 * @{ 4040 */ 4041 #define __HAL_RCC_SBS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) 4042 4043 #if defined(SPI5) 4044 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN) 4045 #endif /* SPI5 */ 4046 4047 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LPEN) 4048 4049 #if defined(I2C3) 4050 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN) 4051 #endif /* I2C3 */ 4052 4053 #if defined(I2C4) 4054 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN) 4055 #endif /* I2C4 */ 4056 4057 #if defined(I3C2) 4058 #define __HAL_RCC_I3C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN) 4059 #endif /* I3C2 */ 4060 4061 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPEN) 4062 4063 #if defined(LPTIM3) 4064 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPEN) 4065 #endif /* LPTIM3 */ 4066 4067 #if defined(LPTIM4) 4068 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPEN) 4069 #endif /* LPTIM4 */ 4070 4071 #if defined(LPTIM5) 4072 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPEN) 4073 #endif /* LPTIM5 */ 4074 4075 #if defined(LPTIM6) 4076 #define __HAL_RCC_LPTIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPEN) 4077 #endif /* LPTIM6 */ 4078 4079 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN) 4080 4081 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) 4082 4083 4084 #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) 4085 4086 #if defined(SPI5) 4087 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN) 4088 #endif /* SPI5 */ 4089 4090 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LPEN) 4091 4092 #if defined(I2C3) 4093 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN) 4094 #endif /* I2C3 */ 4095 4096 #if defined(I2C4) 4097 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN) 4098 #endif /* I2C4 */ 4099 4100 #if defined(I3C2) 4101 #define __HAL_RCC_I3C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN) 4102 #endif /* I3C2 */ 4103 4104 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPEN) 4105 4106 #if defined(LPTIM3) 4107 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPEN) 4108 #endif /* LPTIM3 */ 4109 4110 #if defined(LPTIM4) 4111 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPEN) 4112 #endif /* LPTIM4 */ 4113 4114 #if defined(LPTIM5) 4115 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPEN) 4116 #endif /* LPTIM5 */ 4117 4118 #if defined(LPTIM6) 4119 #define __HAL_RCC_LPTIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPEN) 4120 #endif /* LPTIM6 */ 4121 4122 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN) 4123 4124 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) 4125 4126 /** 4127 * @} 4128 */ 4129 4130 4131 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 4132 * @{ 4133 */ 4134 4135 /** @brief Macros to force or release the Backup domain reset. 4136 * @note This function resets the RTC peripheral (including the backup registers) 4137 * and the RTC clock source selection in RCC_BDCR register. 4138 * @note The BKPSRAM is not affected by this reset. 4139 * @retval None 4140 */ 4141 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 4142 4143 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 4144 4145 /** 4146 * @} 4147 */ 4148 4149 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 4150 * @{ 4151 */ 4152 4153 /** @brief Macros to enable or disable the RTC clock. 4154 * @note As the RTC is in the Backup domain and write access is denied to 4155 * this domain after reset, you have to enable write access using 4156 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 4157 * (to be done once after reset). 4158 * @note These macros must be used after the RTC clock source was selected. 4159 * @retval None 4160 */ 4161 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 4162 4163 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 4164 4165 /** 4166 * @} 4167 */ 4168 4169 /** @brief Macro to configure the Internal High Speed oscillator (HSI). 4170 * @param __HSIDIV__ specifies the HSI division factor. 4171 * This parameter can be one of the following values: 4172 * @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset) 4173 * @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2 4174 * @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4 4175 * @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8 4176 */ 4177 #define __HAL_RCC_HSI_DIVIDER_CONFIG(__HSIDIV__) \ 4178 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV , (uint32_t)(__HSIDIV__)) 4179 4180 4181 /** @brief Macro to get the HSI divider. 4182 * @retval The HSI divider. The returned value can be one 4183 * of the following: 4184 * - RCC_HSI_DIV1 HSI oscillator divided by 1 4185 * - RCC_HSI_DIV2 HSI oscillator divided by 2 4186 * - RCC_HSI_DIV4 HSI oscillator divided by 4 4187 * - RCC_HSI_DIV8 HSI oscillator divided by 8 4188 */ 4189 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) 4190 4191 /** @brief Macros to enable or disable the Internal High Speed 64MHz oscillator (HSI). 4192 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 4193 * It is used (enabled by hardware) as system clock source after startup 4194 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 4195 * of the HSE used directly or indirectly as system clock (if the HSE Clock 4196 * Security System HSECSS is enabled). 4197 * @note HSI can not be stopped if it is used as system clock source. In this case, 4198 * you have to select another source of the system clock then stop the HSI. 4199 * @note After enabling the HSI, the application software should wait on HSIRDY 4200 * flag to be set indicating that HSI clock is stable and can be used as 4201 * system clock source. 4202 * This parameter can be: ENABLE or DISABLE. 4203 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 4204 * clock cycles. 4205 * @retval None 4206 */ 4207 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 4208 4209 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 4210 4211 /** @brief Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value. 4212 * @note The calibration is used to compensate for the variations in voltage 4213 * and temperature that influence the frequency of the internal HSI RC. 4214 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 4215 * (default is RCC_HSICALIBRATION_DEFAULT). 4216 * This parameter must be a number between 0 and 0x7F. 4217 * @retval None 4218 */ 4219 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 4220 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_HSICFGR_HSITRIM_Pos) 4221 4222 /** 4223 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 4224 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 4225 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 4226 * speed because of the HSI startup time. 4227 * @note The enable of this function has not effect on the HSION bit. 4228 * This parameter can be: ENABLE or DISABLE. 4229 * @retval None 4230 */ 4231 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 4232 4233 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 4234 4235 /** 4236 * @brief Macros to enable or disable the Internal Low-power oscillator (CSI). 4237 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. 4238 * It is used (enabled by hardware) as system clock source after 4239 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 4240 * of failure of the HSE used directly or indirectly as system clock 4241 * (if the HSE Clock Security System HSECSS is enabled and CSI is selected 4242 * as system clock after wake up from system stop). 4243 * @note CSI can not be stopped if it is used as system clock source. 4244 * In this case, you have to select another source of the system 4245 * clock then stop the CSI. 4246 * @note After enabling the CSI, the application software should wait on 4247 * CSIRDY flag to be set indicating that CSI clock is stable and can 4248 * be used as system clock source. 4249 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator 4250 * clock cycles. 4251 * @retval None 4252 */ 4253 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) 4254 4255 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) 4256 4257 /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. 4258 * @note The calibration is used to compensate for the variations in voltage 4259 * and temperature that influence the frequency of the internal CSI RC. 4260 * @param __CSICalibrationValue__: specifies the calibration trimming value. 4261 * This parameter must be a number between 0 and 0x3F. 4262 */ 4263 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 4264 do { \ 4265 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ 4266 } while(0) 4267 4268 /** 4269 * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) 4270 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 4271 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication 4272 * speed because of the CSI start-up time. 4273 * @note The enable of this function has not effect on the CSION bit. 4274 * This parameter can be: ENABLE or DISABLE. 4275 * @retval None 4276 */ 4277 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) 4278 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) 4279 4280 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 4281 * @note After enabling the LSI, the application software should wait on 4282 * LSIRDY flag to be set indicating that LSI clock is stable and can 4283 * be used to clock the IWDG and/or the RTC. 4284 * @note LSI can not be disabled if the IWDG is running. 4285 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 4286 * clock cycles. 4287 * @retval None 4288 */ 4289 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) 4290 4291 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION) 4292 4293 /** 4294 * @brief Macro to configure the External High Speed oscillator (HSE). 4295 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 4296 * supported by this macro. User should request a transition to HSE Off 4297 * first and then HSE On or HSE Bypass. 4298 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 4299 * software should wait on HSERDY flag to be set indicating that HSE clock 4300 * is stable and can be used to clock the PLLs and/or system clock. 4301 * @note HSE state can not be changed if it is used directly or through the 4302 * PLL1 as system clock. In this case, you have to select another source 4303 * of the system clock then change the HSE state (ex. disable it). 4304 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 4305 * @param __STATE__: specifies the new state of the HSE. 4306 * This parameter can be one of the following values: 4307 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 4308 * 6 HSE oscillator clock cycles. 4309 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 4310 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 4311 * @arg @ref RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. 4312 * @retval None 4313 */ 4314 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 4315 do { \ 4316 if ((__STATE__) == RCC_HSE_ON) \ 4317 { \ 4318 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4319 } \ 4320 else if ((__STATE__) == RCC_HSE_OFF) \ 4321 { \ 4322 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4323 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4324 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4325 } \ 4326 else if ((__STATE__) == RCC_HSE_BYPASS) \ 4327 { \ 4328 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4329 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4330 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4331 } \ 4332 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 4333 { \ 4334 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4335 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4336 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4337 } \ 4338 else \ 4339 { \ 4340 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4341 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4342 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4343 } \ 4344 } while(0) 4345 4346 /** 4347 * @brief Macro to configure the External Low Speed oscillator (LSE). 4348 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 4349 * supported by this macro. User should request a transition to LSE Off 4350 * first and then LSE On or LSE Bypass. 4351 * @note As the LSE is in the Backup domain and write access is denied to 4352 * this domain after reset, you have to enable write access using 4353 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4354 * (to be done once after reset). 4355 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 4356 * software should wait on LSERDY flag to be set indicating that LSE clock 4357 * is stable and can be used to clock the RTC. 4358 * @param __STATE__: specifies the new state of the LSE. 4359 * This parameter can be one of the following values: 4360 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 4361 * 6 LSE oscillator clock cycles. 4362 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 4363 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 4364 * @arg @ref RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. 4365 * @retval None 4366 */ 4367 4368 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 4369 do { \ 4370 if((__STATE__) == RCC_LSE_ON) \ 4371 { \ 4372 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4373 } \ 4374 else if((__STATE__) == RCC_LSE_OFF) \ 4375 { \ 4376 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4377 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4378 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4379 } \ 4380 else if((__STATE__) == RCC_LSE_BYPASS) \ 4381 { \ 4382 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4383 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4384 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4385 } \ 4386 else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ 4387 { \ 4388 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4389 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4390 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4391 } \ 4392 else \ 4393 { \ 4394 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4395 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4396 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4397 } \ 4398 } while(0) 4399 4400 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 4401 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 4402 * @note After enabling the HSI48, the application software should wait on HSI48RDY 4403 * flag to be set indicating that HSI48 clock is stable. 4404 * This parameter can be: ENABLE or DISABLE. 4405 * @retval None 4406 */ 4407 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) 4408 4409 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) 4410 4411 /** @brief Macros to configure the RTC clock (RTCCLK). 4412 * @note As the RTC clock configuration bits are in the Backup domain and write 4413 * access is denied to this domain after reset, you have to enable write 4414 * access using the Power Backup Access macro before to configure 4415 * the RTC clock source (to be done once after reset). 4416 * @note Once the RTC clock is configured it cannot be changed unless the 4417 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 4418 * a Power On Reset (POR). 4419 * @param __RTCCLKSource__: specifies the RTC clock source. 4420 * This parameter can be one of the following values: 4421 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 4422 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 4423 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected 4424 * as RTC clock, where x can be between 2 and 63 4425 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 4426 * work in STOP and STANDBY modes, and can be used as wakeup source. 4427 * However, when the HSE clock is used as RTC clock source, the RTC 4428 * cannot be used in STOP and STANDBY modes. 4429 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 4430 * RTC clock source). 4431 */ 4432 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 4433 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, \ 4434 (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE) 4435 4436 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 4437 RCC->BDCR &= ~RCC_BDCR_RTCSEL; \ 4438 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ 4439 } while (0) 4440 4441 /** @brief Macro to get the RTC clock source. 4442 * @retval The returned value can be one of the following: 4443 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 4444 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4445 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4446 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected as 4447 * RTC clock, where x can be between 2 and 63 4448 (x can be retrieved with @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()) 4449 */ 4450 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 4451 4452 /** @brief Macro to get the HSE division factor for RTC clock. 4453 * 4454 * @retval The HSE division factor for RTC clock. The returned value can be one 4455 * of the following: 4456 * @arg @ref RCC_RTC_HSE_NOCLOCK : No HSE Clock selected as RTC clock 4457 * @arg @ref RCC_RTC_HSE_DIV2 : HSE Divided by 2 selected as RTC clock 4458 * @arg @ref RCC_RTC_HSE_DIV3 : HSE Divided by 3 selected as RTC clock 4459 * @arg @ref RCC_RTC_HSE_DIV4 : HSE Divided by 4 selected as RTC clock 4460 * @arg @ref RCC_RTC_HSE_DIV5 : HSE Divided by 5 selected as RTC clock 4461 * @arg @ref RCC_RTC_HSE_DIV6 : HSE Divided by 6 selected as RTC clock 4462 * @arg @ref RCC_RTC_HSE_DIV7 : HSE Divided by 7 selected as RTC clock 4463 * @arg @ref RCC_RTC_HSE_DIV8 : HSE Divided by 8 selected as RTC clock 4464 * @arg @ref RCC_RTC_HSE_DIV9 : HSE Divided by 9 selected as RTC clock 4465 * @arg @ref RCC_RTC_HSE_DIV10 : HSE Divided by 10 selected as RTC clock 4466 * @arg @ref RCC_RTC_HSE_DIV11 : HSE Divided by 11 selected as RTC clock 4467 * @arg @ref RCC_RTC_HSE_DIV12 : HSE Divided by 12 selected as RTC clock 4468 * @arg @ref RCC_RTC_HSE_DIV13 : HSE Divided by 13 selected as RTC clock 4469 * @arg @ref RCC_RTC_HSE_DIV14 : HSE Divided by 14 selected as RTC clock 4470 * @arg @ref RCC_RTC_HSE_DIV15 : HSE Divided by 15 selected as RTC clock 4471 * @arg @ref RCC_RTC_HSE_DIV16 : HSE Divided by 16 selected as RTC clock 4472 * @arg @ref RCC_RTC_HSE_DIV17 : HSE Divided by 17 selected as RTC clock 4473 * @arg @ref RCC_RTC_HSE_DIV18 : HSE Divided by 18 selected as RTC clock 4474 * @arg @ref RCC_RTC_HSE_DIV19 : HSE Divided by 19 selected as RTC clock 4475 * @arg @ref RCC_RTC_HSE_DIV20 : HSE Divided by 20 selected as RTC clock 4476 * @arg @ref RCC_RTC_HSE_DIV21 : HSE Divided by 21 selected as RTC clock 4477 * @arg @ref RCC_RTC_HSE_DIV22 : HSE Divided by 22 selected as RTC clock 4478 * @arg @ref RCC_RTC_HSE_DIV23 : HSE Divided by 23 selected as RTC clock 4479 * @arg @ref RCC_RTC_HSE_DIV24 : HSE Divided by 24 selected as RTC clock 4480 * @arg @ref RCC_RTC_HSE_DIV25 : HSE Divided by 25 selected as RTC clock 4481 * @arg @ref RCC_RTC_HSE_DIV26 : HSE Divided by 26 selected as RTC clock 4482 * @arg @ref RCC_RTC_HSE_DIV27 : HSE Divided by 27 selected as RTC clock 4483 * @arg @ref RCC_RTC_HSE_DIV28 : HSE Divided by 28 selected as RTC clock 4484 * @arg @ref RCC_RTC_HSE_DIV29 : HSE Divided by 29 selected as RTC clock 4485 * @arg @ref RCC_RTC_HSE_DIV30 : HSE Divided by 30 selected as RTC clock 4486 * @arg @ref RCC_RTC_HSE_DIV31 : HSE Divided by 31 selected as RTC clock 4487 * @arg @ref RCC_RTC_HSE_DIV32 : HSE Divided by 32 selected as RTC clock 4488 * @arg @ref RCC_RTC_HSE_DIV33 : HSE Divided by 33 selected as RTC clock 4489 * @arg @ref RCC_RTC_HSE_DIV34 : HSE Divided by 34 selected as RTC clock 4490 * @arg @ref RCC_RTC_HSE_DIV35 : HSE Divided by 35 selected as RTC clock 4491 * @arg @ref RCC_RTC_HSE_DIV36 : HSE Divided by 36 selected as RTC clock 4492 * @arg @ref RCC_RTC_HSE_DIV37 : HSE Divided by 37 selected as RTC clock 4493 * @arg @ref RCC_RTC_HSE_DIV38 : HSE Divided by 38 selected as RTC clock 4494 * @arg @ref RCC_RTC_HSE_DIV39 : HSE Divided by 39 selected as RTC clock 4495 * @arg @ref RCC_RTC_HSE_DIV40 : HSE Divided by 40 selected as RTC clock 4496 * @arg @ref RCC_RTC_HSE_DIV41 : HSE Divided by 41 selected as RTC clock 4497 * @arg @ref RCC_RTC_HSE_DIV42 : HSE Divided by 42 selected as RTC clock 4498 * @arg @ref RCC_RTC_HSE_DIV43 : HSE Divided by 43 selected as RTC clock 4499 * @arg @ref RCC_RTC_HSE_DIV44 : HSE Divided by 44 selected as RTC clock 4500 * @arg @ref RCC_RTC_HSE_DIV45 : HSE Divided by 45 selected as RTC clock 4501 * @arg @ref RCC_RTC_HSE_DIV46 : HSE Divided by 46 selected as RTC clock 4502 * @arg @ref RCC_RTC_HSE_DIV47 : HSE Divided by 47 selected as RTC clock 4503 * @arg @ref RCC_RTC_HSE_DIV48 : HSE Divided by 48 selected as RTC clock 4504 * @arg @ref RCC_RTC_HSE_DIV49 : HSE Divided by 49 selected as RTC clock 4505 * @arg @ref RCC_RTC_HSE_DIV50 : HSE Divided by 50 selected as RTC clock 4506 * @arg @ref RCC_RTC_HSE_DIV51 : HSE Divided by 51 selected as RTC clock 4507 * @arg @ref RCC_RTC_HSE_DIV52 : HSE Divided by 52 selected as RTC clock 4508 * @arg @ref RCC_RTC_HSE_DIV53 : HSE Divided by 53 selected as RTC clock 4509 * @arg @ref RCC_RTC_HSE_DIV54 : HSE Divided by 54 selected as RTC clock 4510 * @arg @ref RCC_RTC_HSE_DIV55 : HSE Divided by 55 selected as RTC clock 4511 * @arg @ref RCC_RTC_HSE_DIV56 : HSE Divided by 56 selected as RTC clock 4512 * @arg @ref RCC_RTC_HSE_DIV57 : HSE Divided by 57 selected as RTC clock 4513 * @arg @ref RCC_RTC_HSE_DIV58 : HSE Divided by 58 selected as RTC clock 4514 * @arg @ref RCC_RTC_HSE_DIV59 : HSE Divided by 59 selected as RTC clock 4515 * @arg @ref RCC_RTC_HSE_DIV60 : HSE Divided by 60 selected as RTC clock 4516 * @arg @ref RCC_RTC_HSE_DIV61 : HSE Divided by 61 selected as RTC clock 4517 * @arg @ref RCC_RTC_HSE_DIV62 : HSE Divided by 62 selected as RTC clock 4518 * @arg @ref RCC_RTC_HSE_DIV63 : HSE Divided by 63 selected as RTC clock 4519 */ 4520 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE))) 4521 4522 /** @brief Macros to enable or disable the main PLL. 4523 * @note After enabling the main PLL, the application software should wait on 4524 * PLLRDY flag to be set indicating that PLL clock is stable and can 4525 * be used as system clock source. 4526 * @note The main PLL can not be disabled if it is used as system clock source 4527 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 4528 */ 4529 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 4530 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 4531 4532 /** 4533 * @brief Enables or disables each clock output (PLL1P_CLK, PLL1Q_CLK, PLL1R_CLK) 4534 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL1, 4535 * (except the ck_pll_p of the System PLL that cannot be stopped if used as System 4536 * Clock. This is mainly used to save Power. 4537 * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted 4538 * This parameter can be one of the following values: 4539 * @arg RCC_PLL1_DIVP: This Clock is used to generate the high speed system clock (up to 240MHz) 4540 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for USB (48 MHz), RNG (<=48 MHz), 4541 * OCTOSPI, SPI, SAI and Ethernet 4542 * @arg RCC_PLL1_DIVR: This Clock is used to generate an accurate clock 4543 * @retval None 4544 * 4545 */ 4546 #define __HAL_RCC_PLL1_CLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4547 4548 #define __HAL_RCC_PLL1_CLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4549 4550 /** 4551 * @brief Macro to get the PLL clock output enable status. 4552 * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. 4553 * This parameter can be one of the following values: 4554 * @arg RCC_PLL1_DIVP: This Clock is used to generate the high speed system clock (up to 240MHz) 4555 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for USB (48 MHz), RNG (<=48 MHz), 4556 * OCTOSPI, SPI, SAI and Ethernet 4557 * @arg RCC_PLL1_DIVR: This Clock is used to generate an accurate clock 4558 * @retval SET / RESET 4559 */ 4560 #define __HAL_RCC_GET_PLL1_CLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4561 4562 /** 4563 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 4564 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 4565 * @retval None 4566 */ 4567 #define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4568 4569 #define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4570 4571 /** 4572 * @brief Macro to configures the main PLL (PLL1) clock source, multiplication and division factors. 4573 * @note This function must be used only when the main PLL1 is disabled. 4574 * 4575 * @param __PLLSOURCE__: specifies the PLL entry clock source. 4576 * This parameter can be one of the following values: 4577 * @arg RCC_PLL1_SOURCE_CSI: CSI oscillator clock selected as PLL1 clock entry 4578 * @arg RCC_PLL1_SOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry 4579 * @arg RCC_PLL1_SOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry 4580 * @note This clock source (__PLLSource__) is the clock source for PLL1 (main PLL) and is different 4581 from PLL2 & PLL3 clock sources. 4582 * 4583 * @param __PLL1M__: specifies the division factor for PLL VCO input clock 4584 * This parameter must be a number between 1 and 63. 4585 * @note You have to set the PLL1M parameter correctly to ensure that the VCO input 4586 * frequency ranges from 1 to 16 MHz. 4587 * 4588 * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock 4589 * This parameter must be a number between 4 and 512. 4590 * @note You have to set the PLL1N parameter correctly to ensure that the VCO 4591 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 4592 * between 192 and 836 MHZ (when in wide VCO range) 4593 * 4594 * @param __PLL1P__: specifies the division factor for system clock. 4595 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 4596 * 4597 * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks 4598 * This parameter must be a number between 1 and 128 4599 * 4600 * @param __PLL1R__: specifies the division factor for peripheral kernel clocks 4601 * This parameter must be a number between 1 and 128 4602 * 4603 * @retval None 4604 */ 4605 #define __HAL_RCC_PLL1_CONFIG(__PLL1SOURCE__, __PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ 4606 do{ WRITE_REG(RCC->PLL1CFGR, ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) | \ 4607 ((__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos));\ 4608 WRITE_REG(RCC->PLL1DIVR , ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) | \ 4609 ((((__PLL1P__) - 1U ) << RCC_PLL1DIVR_PLL1P_Pos) & RCC_PLL1DIVR_PLL1P) | \ 4610 ((((__PLL1Q__) - 1U) << RCC_PLL1DIVR_PLL1Q_Pos) & RCC_PLL1DIVR_PLL1Q) | \ 4611 ((((__PLL1R__) - 1U) << RCC_PLL1DIVR_PLL1R_Pos) & RCC_PLL1DIVR_PLL1R))); \ 4612 } while(0) 4613 4614 /** @brief Macro to configure the PLL1 clock source. 4615 * @note This function must be used only when PLL1 is disabled. 4616 * @param __PLLSOURCE__: specifies the PLL1 entry clock source. 4617 * This parameter can be one of the following values: 4618 * @arg RCC_PLL1_SOURCE_CSI: CSI oscillator clock selected as PLL1 clock entry 4619 * @arg RCC_PLL1_SOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry 4620 * @arg RCC_PLL1_SOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry 4621 * 4622 */ 4623 #define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLLSOURCE__)) 4624 4625 /** @brief Macro to configure the PLL1 input clock division factor M. 4626 * 4627 * @note This function must be used only when the PLL1 is disabled. 4628 * @note PLL1 clock source is common with the main PLL (configured through 4629 * __HAL_RCC_PLL1_CONFIG() macro) 4630 * 4631 * @param __PLL1M__ specifies the division factor for PLL1 clock. 4632 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 4633 * In order to save power when PLL1 is not used, the value of PLL1M must be set to 0. 4634 * 4635 * @retval None 4636 */ 4637 #define __HAL_RCC_PLL1_DIVM_CONFIG(__PLL1M__) \ 4638 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos) 4639 4640 /** 4641 * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor 4642 * 4643 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 4644 * 4645 * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 4646 * It should be a value between 0 and 8191 4647 * @note Warning: The software has to set correctly these bits to insure that the VCO 4648 * output frequency is between its valid frequency range, which is: 4649 * 192 to 836 MHz if PLL1VCOSEL = 0 4650 * 150 to 420 MHz if PLL1VCOSEL = 1. 4651 * 4652 * 4653 * @retval None 4654 */ 4655 #define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ 4656 (uint32_t)(__PLL1FRACN__) << RCC_PLL1FRACR_PLL1FRACN_Pos) 4657 4658 /** @brief Macro to select the PLL1 reference frequency range. 4659 * @param __PLL1VCIRange__: specifies the PLL1 input frequency range 4660 * This parameter can be one of the following values: 4661 * @arg RCC_PLL1_VCIRANGE_0: Range frequency is between 1 and 2 MHz 4662 * @arg RCC_PLL1_VCIRANGE_1: Range frequency is between 2 and 4 MHz 4663 * @arg RCC_PLL1_VCIRANGE_2: Range frequency is between 4 and 8 MHz 4664 * @arg RCC_PLL1_VCIRANGE_3: Range frequency is between 8 and 16 MHz 4665 * @retval None 4666 */ 4667 #define __HAL_RCC_PLL1_VCIRANGE(__PLL1VCIRange__) \ 4668 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) 4669 4670 /** @brief Macro to select the PLL1 reference frequency range. 4671 * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range 4672 * This parameter can be one of the following values: 4673 * @arg RCC_PLL1_VCORANGE_WIDE: Range frequency is between 192 and 836 MHz 4674 * @arg RCC_PLL1_VCORANGE_MEDIUM: Range frequency is between 150 and 420 MHz 4675 * 4676 * 4677 * @retval None 4678 */ 4679 #define __HAL_RCC_PLL1_VCORANGE(__RCC_PLL1VCORange__) \ 4680 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) 4681 4682 /** @brief Macro to get the oscillator used as PLL1 clock source. 4683 * @retval The oscillator used as PLL1 clock source. The returned value can be one 4684 * of the following: 4685 * - RCC_PLL1_SOURCE_NONE: No oscillator is used as PLL clock source. 4686 * - RCC_PLL1_SOURCE_CSI: CSI oscillator is used as PLL clock source. 4687 * - RCC_PLL1_SOURCE_HSI: HSI oscillator is used as PLL clock source. 4688 * - RCC_PLL1_SOURCE_HSE: HSE oscillator is used as PLL clock source. 4689 */ 4690 #define __HAL_RCC_GET_PLL1_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) 4691 4692 /** 4693 * @brief Macro to configure the system clock source. 4694 * @param __SYSCLKSOURCE__: specifies the system clock source. 4695 * This parameter can be one of the following values: 4696 * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. 4697 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 4698 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 4699 * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1P output is used as system clock source. 4700 * @retval None 4701 */ 4702 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4703 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) 4704 4705 /** @brief Macro to get the clock source used as system clock. 4706 * @retval The clock source used as system clock. The returned value can be one 4707 * of the following: 4708 * - RCC_SYSCLKSOURCE_STATUS_CSI: CSI used as system clock. 4709 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 4710 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 4711 * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1P used as system clock. 4712 */ 4713 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) 4714 4715 /** 4716 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4717 * @note As the LSE is in the Backup domain and write access is denied to 4718 * this domain after reset, you have to enable the write access using 4719 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4720 * (to be done once after reset). 4721 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 4722 * This parameter can be one of the following values: 4723 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4724 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4725 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4726 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4727 * @retval None 4728 */ 4729 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4730 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 4731 4732 /** 4733 * @brief Macro to configure the wake up from stop clock. 4734 * @note The configured clock is also used as emergency clock for the Clock Security System on HSE (HSECSS). 4735 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 4736 * This parameter can be one of the following values: 4737 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 4738 * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI selected as system clock source 4739 * @retval None 4740 */ 4741 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4742 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) 4743 4744 #define __HAL_RCC_HSECSS_RECOVCLK_CONFIG __HAL_RCC_WAKEUPSTOP_CLK_CONFIG 4745 4746 /** 4747 * @brief Macro to configure the Kernel wake up from stop clock. 4748 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 4749 * This parameter can be one of the following values: 4750 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source 4751 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 4752 * @retval None 4753 */ 4754 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 4755 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 4756 4757 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 4758 * @{ 4759 */ 4760 4761 /** @brief Macro to configure the MCO1 clock. 4762 * @param __MCOCLKSOURCE__ specifies the MCO1 clock source. 4763 * This parameter can be one of the following values: 4764 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 4765 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 4766 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 4767 * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source 4768 * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source 4769 * @param __MCODIV__ specifies the MCO clock prescaler. 4770 * This parameter can be one of the following values: 4771 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock 4772 */ 4773 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4774 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO1SEL | RCC_CFGR1_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4775 4776 /** @brief Macro to configure the MCO2 clock. 4777 * @param __MCOCLKSOURCE__ specifies the MCO2 clock source. 4778 * This parameter can be one of the following values: 4779 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 4780 * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source 4781 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 4782 * @arg RCC_MCO2SOURCE_PLL1PCLK: PLL1P clock selected as MCO2 source 4783 * @arg RCC_MCO2SOURCE_CSI: CSI clock selected as MCO2 source 4784 * @arg RCC_MCO2SOURCE_LSI: LSI clock selected as MCO2 source 4785 * @param __MCODIV__ specifies the MCO clock prescaler. 4786 * This parameter can be one of the following values: 4787 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock 4788 */ 4789 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4790 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO2SEL | RCC_CFGR1_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); 4791 4792 /** 4793 * @} 4794 */ 4795 4796 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4797 * @brief macros to manage the specified RCC Flags and interrupts. 4798 * @{ 4799 */ 4800 4801 /** @brief Enable RCC interrupt (Perform access to RCC_CIER[8:0] bits to enable 4802 * the selected interrupts). 4803 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 4804 * This parameter can be any combination of the following values: 4805 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4806 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4807 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4808 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4809 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4810 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4811 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4812 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4813 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4814 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4815 * @retval None 4816 * 4817 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4818 */ 4819 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4820 4821 /** @brief Disable RCC interrupt (Perform access to RCC_CIER[8:0] bits to disable 4822 * the selected interrupts). 4823 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 4824 * This parameter can be any combination of the following values: 4825 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4826 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4827 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4828 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4829 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4830 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4831 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4832 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4833 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 4834 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4835 * @retval None 4836 * 4837 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4838 */ 4839 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4840 4841 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CICR[10:0] 4842 * bits to clear the selected interrupt pending bits. 4843 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 4844 * This parameter can be any combination of the following values: 4845 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4846 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4847 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4848 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4849 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4850 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4851 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4852 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4853 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt 4854 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4855 * @retval None 4856 * 4857 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4858 */ 4859 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4860 4861 /** @brief Check whether the RCC interrupt has occurred or not. 4862 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 4863 * This parameter can be one of the following values: 4864 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4865 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4866 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4867 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4868 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4869 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4870 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4871 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4872 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt 4873 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4874 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4875 * 4876 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4877 */ 4878 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4879 4880 /** @brief Set RMVF bit to clear the reset flags. 4881 * The reset flags are: RCC_FLAG_SFTRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 4882 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4883 * @retval None 4884 */ 4885 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) 4886 4887 /** @brief Check whether the selected RCC flag is set or not. 4888 * @param __FLAG__: specifies the flag to check. 4889 * This parameter can be one of the following values: 4890 * @arg @ref RCC_FLAG_CSIRDY CSI oscillator clock ready 4891 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4892 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4893 * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready 4894 * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready 4895 * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready (*) 4896 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 4897 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4898 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4899 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4900 * @arg @ref RCC_FLAG_HSIDIV HSI Divider 4901 * @arg @ref RCC_FLAG_BORRST BOR reset 4902 * @arg @ref RCC_FLAG_PINRST Pin reset 4903 * @arg @ref RCC_FLAG_RMVF Remove reset Flag 4904 * @arg @ref RCC_FLAG_SFTRST Software reset 4905 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4906 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4907 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4908 * @retval The new state of __FLAG__ (TRUE or FALSE). 4909 * 4910 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4911 */ 4912 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4913 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4914 ((((__FLAG__) >> 5U) == 3U) ? RCC->RSR : RCC->CIFR))) & \ 4915 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4916 /** 4917 * @} 4918 */ 4919 4920 /** 4921 * @} 4922 */ 4923 4924 /* Private constants ---------------------------------------------------------*/ 4925 /** @defgroup RCC_Private_Constants RCC Private Constants 4926 * @{ 4927 */ 4928 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 4929 #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4930 #define CSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4931 #define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4932 #define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4933 #define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4934 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */ 4935 4936 /* Defines used for Flags */ 4937 #define CR_REG_INDEX (1U) 4938 #define BDCR_REG_INDEX (2U) 4939 #define RSR_REG_INDEX (3U) 4940 4941 #define RCC_FLAG_MASK (0x1FU) 4942 4943 /* Defines Oscillator Masks */ 4944 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | \ 4945 RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) 4946 /*!< All Oscillator to configure */ 4947 4948 4949 /** 4950 * @} 4951 */ 4952 4953 /* Private macros ------------------------------------------------------------*/ 4954 /** @addtogroup RCC_Private_Macros 4955 * @{ 4956 */ 4957 4958 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4959 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 4960 4961 4962 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 4963 ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) 4964 4965 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 4966 ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL)) 4967 4968 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 4969 4970 #define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ 4971 ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8)) 4972 4973 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 4974 <= (uint32_t)( RCC_HSICFGR_HSITRIM >> RCC_HSICFGR_HSITRIM_Pos)) 4975 4976 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 4977 4978 #define IS_RCC_CSI(__CSI__) (((__CSI__) == RCC_CSI_OFF) || ((__CSI__) == RCC_CSI_ON)) 4979 4980 #define IS_RCC_CSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 4981 <= (uint32_t)( RCC_CSICFGR_CSITRIM >> RCC_CSICFGR_CSITRIM_Pos)) 4982 4983 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 4984 4985 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ 4986 ((PLL) == RCC_PLL_ON)) 4987 4988 #define IS_RCC_PLL1_SOURCE(SOURCE) (((SOURCE) == RCC_PLL1_SOURCE_CSI) || \ 4989 ((SOURCE) == RCC_PLL1_SOURCE_HSI) || \ 4990 ((SOURCE) == RCC_PLL1_SOURCE_HSE)) 4991 4992 #define IS_RCC_PLL1_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 4993 #define IS_RCC_PLL1_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4994 #define IS_RCC_PLL1_DIVP_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 128U)) 4995 #define IS_RCC_PLL1_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4996 #define IS_RCC_PLL1_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4997 4998 #define IS_RCC_PLL1_CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ 4999 ((VALUE) == RCC_PLL1_DIVQ) || \ 5000 ((VALUE) == RCC_PLL1_DIVR)) 5001 5002 #define IS_RCC_PLL1_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1_VCIRANGE_0) || \ 5003 ((VALUE) == RCC_PLL1_VCIRANGE_1) || \ 5004 ((VALUE) == RCC_PLL1_VCIRANGE_2) || \ 5005 ((VALUE) == RCC_PLL1_VCIRANGE_3)) 5006 5007 #define IS_RCC_PLL1_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL1_VCORANGE_WIDE) || ((VALUE) == RCC_PLL1_VCORANGE_MEDIUM)) 5008 5009 #define IS_RCC_PLL1_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 5010 5011 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) 5012 5013 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_CSI) || \ 5014 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 5015 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 5016 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 5017 5018 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 5019 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 5020 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 5021 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 5022 ((__HCLK__) == RCC_SYSCLK_DIV512)) 5023 5024 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 5025 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 5026 ((__PCLK__) == RCC_HCLK_DIV16)) 5027 5028 #define IS_RCC_RTCCLKSOURCE(SOURCE) \ 5029 (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ 5030 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 5031 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 5032 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 5033 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 5034 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 5035 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 5036 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 5037 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 5038 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 5039 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 5040 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 5041 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 5042 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 5043 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 5044 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ 5045 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ 5046 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ 5047 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ 5048 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ 5049 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ 5050 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ 5051 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ 5052 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ 5053 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ 5054 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ 5055 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ 5056 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ 5057 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ 5058 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ 5059 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ 5060 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63) || \ 5061 ((SOURCE) == RCC_RTCCLKSOURCE_NO_CLK)) 5062 5063 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 5064 5065 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 5066 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1Q) || \ 5067 ((SOURCE) == RCC_MCO1SOURCE_HSI48)) 5068 5069 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2P) || \ 5070 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLL1P) || \ 5071 ((SOURCE) == RCC_MCO2SOURCE_CSI) || ((SOURCE) == RCC_MCO2SOURCE_LSI)) 5072 5073 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 5074 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 5075 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ 5076 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ 5077 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ 5078 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ 5079 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ 5080 ((DIV) == RCC_MCODIV_15)) 5081 5082 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 5083 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 5084 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 5085 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 5086 5087 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ 5088 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 5089 5090 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ 5091 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 5092 5093 #if defined(RCC_SECCFGR_HSISEC) 5094 5095 #define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((((ITEM) & RCC_ALL) != 0U) && (((ITEM) & ~RCC_ALL) == 0U)) 5096 5097 #define IS_RCC_SINGLE_ITEM_ATTRIBUTES(ITEM) (((ITEM) == RCC_HSI) || \ 5098 ((ITEM) == RCC_HSE) || \ 5099 ((ITEM) == RCC_CSI) || \ 5100 ((ITEM) == RCC_LSI) || \ 5101 ((ITEM) == RCC_LSE) || \ 5102 ((ITEM) == RCC_SYSCLK) || \ 5103 ((ITEM) == RCC_PRESC) || \ 5104 ((ITEM) == RCC_PLL1) || \ 5105 ((ITEM) == RCC_PLL2) || \ 5106 ((ITEM) == RCC_PLL3) || \ 5107 ((ITEM) == RCC_HSI48) || \ 5108 ((ITEM) == RCC_RMVF) || \ 5109 ((ITEM) == RCC_CKPERSEL)) 5110 #endif /* RCC_SECCFGR_HSISEC */ 5111 5112 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5113 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \ 5114 ((ATTRIBUTES) == RCC_SEC_NPRIV) || \ 5115 ((ATTRIBUTES) == RCC_NSEC_PRIV) || \ 5116 ((ATTRIBUTES) == RCC_NSEC_NPRIV)) 5117 #elif defined(RCC_PRIVCFGR_NSPRIV) 5118 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV)) 5119 #else 5120 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NPRIV) || ((ATTRIBUTES) == RCC_PRIV)) 5121 #endif /* __ARM_FEATURE_CMSE */ 5122 /** 5123 * @} 5124 */ 5125 5126 /* Include RCC HAL Extended module */ 5127 #include "stm32h5xx_hal_rcc_ex.h" 5128 5129 /* Exported functions --------------------------------------------------------*/ 5130 /** @addtogroup RCC_Exported_Functions 5131 * @{ 5132 */ 5133 5134 /** @addtogroup RCC_Exported_Functions_Group1 5135 * @{ 5136 */ 5137 5138 /* Initialization and de-initialization functions ******************************/ 5139 HAL_StatusTypeDef HAL_RCC_DeInit(void); 5140 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pOscInitStruct); 5141 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *pClkInitStruct, uint32_t FLatency); 5142 5143 /** 5144 * @} 5145 */ 5146 5147 /** @addtogroup RCC_Exported_Functions_Group2 5148 * @{ 5149 */ 5150 5151 /* Peripheral Control functions **********************************************/ 5152 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 5153 void HAL_RCC_EnableCSS(void); 5154 uint32_t HAL_RCC_GetSysClockFreq(void); 5155 uint32_t HAL_RCC_GetHCLKFreq(void); 5156 uint32_t HAL_RCC_GetPCLK1Freq(void); 5157 uint32_t HAL_RCC_GetPCLK2Freq(void); 5158 uint32_t HAL_RCC_GetPCLK3Freq(void); 5159 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pOscInitStruct); 5160 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pClkInitStruct, uint32_t *pFLatency); 5161 /* CSS NMI IRQ handler */ 5162 void HAL_RCC_NMI_IRQHandler(void); 5163 /* User Callbacks in non blocking mode (IT mode) */ 5164 void HAL_RCC_CSSCallback(void); 5165 uint32_t HAL_RCC_GetResetSource(void); 5166 5167 /** 5168 * @} 5169 */ 5170 5171 /** @addtogroup RCC_Exported_Functions_Group3 5172 * @{ 5173 */ 5174 5175 /* Attributes management functions ********************************************/ 5176 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 5177 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 5178 5179 /** 5180 * @} 5181 */ 5182 5183 /** 5184 * @} 5185 */ 5186 5187 /** 5188 * @} 5189 */ 5190 5191 /** 5192 * @} 5193 */ 5194 5195 #ifdef __cplusplus 5196 } 5197 #endif 5198 5199 #endif /* __STM32H5xx_HAL_RCC_H */ 5200 5201
