1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_pwr.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H5xx_HAL_PWR_H 22 #define STM32H5xx_HAL_PWR_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_def.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup PWR 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup PWR_Exported_Types PWR Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief PWR PVD configuration structure definition 47 */ 48 typedef struct 49 { 50 uint32_t PVDLevel; /*!< Specifies the PVD detection level. 51 This parameter can be a value of 52 @ref PWR_PVD_Detection_Level. */ 53 54 uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 55 This parameter can be a value of @ref PWR_PVD_Mode. */ 56 } PWR_PVDTypeDef; 57 /** 58 * @} 59 */ 60 61 /* Exported constants --------------------------------------------------------*/ 62 63 /** @defgroup PWR_Exported_Constants PWR Exported Constants 64 * @{ 65 */ 66 67 /** @defgroup PWR_PVD_Detection_Level Programmable Voltage Detection Level 68 * @{ 69 */ 70 #define PWR_PVDLEVEL_0 0x00000000UL /*!< PVD threshold around 2.0 V */ 71 #define PWR_PVDLEVEL_1 (PWR_VMCR_PLS_0) /*!< PVD threshold around 2.2 V */ 72 #define PWR_PVDLEVEL_2 (PWR_VMCR_PLS_1) /*!< PVD threshold around 2.4 V */ 73 #define PWR_PVDLEVEL_3 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_1) /*!< PVD threshold around 2.5 V */ 74 #define PWR_PVDLEVEL_4 (PWR_VMCR_PLS_2) /*!< PVD threshold around 2.6 V */ 75 #define PWR_PVDLEVEL_5 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_2) /*!< PVD threshold around 2.8 V */ 76 #define PWR_PVDLEVEL_6 (PWR_VMCR_PLS_1 | PWR_VMCR_PLS_2) /*!< PVD threshold around 2.9 V */ 77 #define PWR_PVDLEVEL_7 (PWR_VMCR_PLS) /*!< External input analog voltage 78 (compared internally to VREFINT) */ 79 /** 80 * @} 81 */ 82 83 /** @defgroup PWR_PVD_Mode PWR PVD Mode 84 * @{ 85 */ 86 #define PWR_PVD_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ 87 #define PWR_PVD_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ 88 #define PWR_PVD_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ 89 #define PWR_PVD_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 90 #define PWR_PVD_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ 91 #define PWR_PVD_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ 92 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ 93 /** 94 * @} 95 */ 96 97 /** @defgroup PWR_Regulator_In_LowPower_Mode PWR Regulator State in SLEEP/STOP Mode 98 * @{ 99 */ 100 #define PWR_MAINREGULATOR_ON (0x00U) /*!< Main Regulator ON in Run Mode */ 101 #define PWR_LOWPOWERREGULATOR_ON (0x00U) /*!< Main Regulator ON in Low Power Mode */ 102 /** 103 * @} 104 */ 105 106 /** @defgroup PWR_SLEEP_Mode_Entry PWR SLEEP Mode Entry 107 * @{ 108 */ 109 #define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ 110 #define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ 111 /** 112 * @} 113 */ 114 115 /** @defgroup PWR_STOP_Mode_Entry PWR STOP Mode Entry 116 * @{ 117 */ 118 #define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ 119 #define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ 120 /** 121 * @} 122 */ 123 124 /** @defgroup PWR_Flags PWR Flags 125 * @{ 126 */ 127 #define PWR_FLAG_STOPF (0x01U) /*!< STOP flag */ 128 #define PWR_FLAG_SBF (0x02U) /*!< STANDBY flag */ 129 #define PWR_FLAG_VOSRDY (0x03U) /*!< Voltage scaling ready flag */ 130 #define PWR_FLAG_ACTVOSRDY (0x04U) /*!< Currently applied VOS ready flag */ 131 #define PWR_FLAG_BRR (0x05U) /*!< Backup regulator ready flag */ 132 #define PWR_FLAG_VBATL (0x06U) /*!< Backup domain voltage level flag (versus low threshold) */ 133 #define PWR_FLAG_VBATH (0x07U) /*!< Backup domain voltage level flag (versus high threshold) */ 134 #define PWR_FLAG_TEMPL (0x08U) /*!< Temperature level flag (versus low threshold) */ 135 #define PWR_FLAG_TEMPH (0x09U) /*!< Temperature level flag (versus high threshold) */ 136 #define PWR_FLAG_AVDO (0x0AU) /*!< VDDA voltage detector output flag */ 137 #define PWR_FLAG_VDDIO2RDY (0x0BU) /*!< VDDIO2 voltage detector output flag */ 138 #define PWR_FLAG_PVDO (0x0CU) /*!< VDD voltage detector output flag */ 139 #define PWR_FLAG_USB33RDY (0x0DU) /*!< VDDUSB33 ready flag */ 140 141 #define PWR_WAKEUP_FLAG1 (0x10U) /*!< Wake up line 1 flag */ 142 #define PWR_WAKEUP_FLAG2 (0x20U) /*!< Wake up line 2 flag */ 143 #define PWR_WAKEUP_FLAG3 (0x30U) /*!< Wake up line 3 flag */ 144 #define PWR_WAKEUP_FLAG4 (0x40U) /*!< Wake up line 4 flag */ 145 #define PWR_WAKEUP_FLAG5 (0x50U) /*!< Wake up line 5 flag */ 146 #define PWR_WAKEUP_FLAG6 (0x60U) /*!< Wake up line 6 flag */ 147 #define PWR_WAKEUP_FLAG7 (0x70U) /*!< Wake up line 7 flag */ 148 #define PWR_WAKEUP_FLAG8 (0x80U) /*!< Wake up line 8 flag */ 149 #define PWR_WAKEUP_ALL_FLAG (0x90U) /*!< Wakeup flag all */ 150 151 152 /** 153 * @} 154 */ 155 156 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins 157 * @{ 158 */ 159 /* High level and No pull (default configuration) */ 160 #define PWR_WAKEUP_PIN1 PWR_WUCR_WUPEN1 161 #define PWR_WAKEUP_PIN2 PWR_WUCR_WUPEN2 162 #define PWR_WAKEUP_PIN3 PWR_WUCR_WUPEN3 163 #define PWR_WAKEUP_PIN4 PWR_WUCR_WUPEN4 164 #define PWR_WAKEUP_PIN5 PWR_WUCR_WUPEN5 165 #if defined (PWR_WUCR_WUPEN6) 166 #define PWR_WAKEUP_PIN6 PWR_WUCR_WUPEN6 167 #define PWR_WAKEUP_PIN7 PWR_WUCR_WUPEN7 168 #define PWR_WAKEUP_PIN8 PWR_WUCR_WUPEN8 169 #endif /* PWR_WUCR_WUPEN6 */ 170 171 /* High level and No pull */ 172 #define PWR_WAKEUP_PIN1_HIGH PWR_WUCR_WUPEN1 173 #define PWR_WAKEUP_PIN2_HIGH PWR_WUCR_WUPEN2 174 #define PWR_WAKEUP_PIN3_HIGH PWR_WUCR_WUPEN3 175 #define PWR_WAKEUP_PIN4_HIGH PWR_WUCR_WUPEN4 176 #define PWR_WAKEUP_PIN5_HIGH PWR_WUCR_WUPEN5 177 #if defined (PWR_WUCR_WUPEN6) 178 #define PWR_WAKEUP_PIN6_HIGH PWR_WUCR_WUPEN6 179 #define PWR_WAKEUP_PIN7_HIGH PWR_WUCR_WUPEN7 180 #define PWR_WAKEUP_PIN8_HIGH PWR_WUCR_WUPEN8 181 #endif /* PWR_WUCR_WUPEN6 */ 182 183 /* Low level and No pull */ 184 #define PWR_WAKEUP_PIN1_LOW (PWR_WUCR_WUPP1 | PWR_WUCR_WUPEN1) 185 #define PWR_WAKEUP_PIN2_LOW (PWR_WUCR_WUPP2 | PWR_WUCR_WUPEN2) 186 #define PWR_WAKEUP_PIN3_LOW (PWR_WUCR_WUPP3 | PWR_WUCR_WUPEN3) 187 #define PWR_WAKEUP_PIN4_LOW (PWR_WUCR_WUPP4 | PWR_WUCR_WUPEN4) 188 #define PWR_WAKEUP_PIN5_LOW (PWR_WUCR_WUPP5 | PWR_WUCR_WUPEN5) 189 #if defined (PWR_WUCR_WUPEN6) 190 #define PWR_WAKEUP_PIN6_LOW (PWR_WUCR_WUPP6 | PWR_WUCR_WUPEN6) 191 #define PWR_WAKEUP_PIN7_LOW (PWR_WUCR_WUPP7 | PWR_WUCR_WUPEN7) 192 #define PWR_WAKEUP_PIN8_LOW (PWR_WUCR_WUPP8 | PWR_WUCR_WUPEN8) 193 #endif /* PWR_WUCR_WUPEN6 */ 194 195 /** 196 * @} 197 */ 198 199 #if defined(PWR_SECCFGR_WUP1SEC) 200 /** @defgroup PWR_Items PWR Items 201 * @{ 202 */ 203 #define PWR_WKUP1 (PWR_SECCFGR_WUP1SEC) /*!< WUP1 secure protection */ 204 #define PWR_WKUP2 (PWR_SECCFGR_WUP2SEC) /*!< WUP2 secure protection */ 205 #define PWR_WKUP3 (PWR_SECCFGR_WUP3SEC) /*!< WUP3 secure protection */ 206 #define PWR_WKUP4 (PWR_SECCFGR_WUP4SEC) /*!< WUP4 secure protection */ 207 #define PWR_WKUP5 (PWR_SECCFGR_WUP5SEC) /*!< WUP5 secure protection */ 208 #define PWR_WKUP6 (PWR_SECCFGR_WUP6SEC) /*!< WUP6 secure protection */ 209 #define PWR_WKUP7 (PWR_SECCFGR_WUP7SEC) /*!< WUP7 secure protection */ 210 #define PWR_WKUP8 (PWR_SECCFGR_WUP8SEC) /*!< WUP8 secure protection */ 211 #define PWR_RET (PWR_SECCFGR_RETSEC) /*!< IO Retention secure protection */ 212 #define PWR_LPM (PWR_SECCFGR_LPMSEC) /*!< Low power modes secure protection */ 213 #define PWR_SCM (PWR_SECCFGR_SCMSEC) /*!< Voltage detection and monitoring secure protection */ 214 #define PWR_VB (PWR_SECCFGR_VBSEC) /*!< Backup domain secure protection */ 215 #define PWR_VUSB (PWR_SECCFGR_VUSBSEC) /*!< Backup domain secure protection */ 216 #define PWR_ALL (PWR_WKUP1 | PWR_WKUP2 | PWR_WKUP3 | PWR_WKUP4 | \ 217 PWR_WKUP5 | PWR_WKUP6 | PWR_WKUP7 | PWR_WKUP8 | \ 218 PWR_LPM | PWR_SCM | PWR_VB | PWR_VUSB | \ 219 PWR_RET) 220 /** 221 * @} 222 */ 223 #endif /* PWR_SECCFGR_WUP1SEC */ 224 225 /** @defgroup PWR_Attributes PWR Attributes 226 * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes 227 * @{ 228 */ 229 #if defined(RCC_PRIVCFGR_NSPRIV) 230 #define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */ 231 #define PWR_NSEC_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NSecure and NPrivileged attribute */ 232 #else 233 #define PWR_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< Privileged attribute */ 234 #define PWR_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NPrivileged attribute */ 235 #endif /* RCC_PRIVCFGR_NSPRIV */ 236 #define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */ 237 #define PWR_SEC_NPRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK) /*!< Secure and NPrivileged attribute */ 238 /** 239 * @} 240 */ 241 242 /** 243 * @} 244 */ 245 246 /* Exported macros -----------------------------------------------------------*/ 247 248 /** @defgroup PWR_Exported_Macros PWR Exported Macros 249 * @{ 250 */ 251 252 /** @brief Check PWR flags are set or not. 253 * @param __FLAG__ : Specifies the flag to check. 254 * This parameter can be one of the following values : 255 * @arg @ref PWR_FLAG_STOPF : Voltage scaling ready flag. 256 * Indicates that the Vcore level at or above VOS selected level. 257 * @arg @ref PWR_FLAG_SBF : EPOD booster ready flag. 258 * Indicates that EPOD booster ready, frequency could be higher than 259 * 50 MHz. 260 * @arg @ref PWR_FLAG_VOSRDY : STOP flag. 261 * Indicates that the device was resumed from STOP mode. 262 * @arg @ref PWR_FLAG_ACTVOSRDY : STANDBY flag. 263 * Indicates that the device was resumed from STANDBY mode. 264 * @arg @ref PWR_FLAG_BRR : VDDA2 ready flag (versus 1.8 V threshold). 265 * Indicates that VDDA is equal or above the threshold of the VDDA 266 * voltage monitor 2 (around 1.8 V). 267 * @arg @ref PWR_FLAG_VBATL : VDDA1 ready flag (versus 1.6 V threshold). 268 * Indicates that VDDA is equal or above the threshold of the VDDA 269 * voltage monitor 1 (around 1.6 V). 270 * @arg @ref PWR_FLAG_VBATH : VDDIO2 ready flag (versus 0.9 V threshold). 271 * Indicates that VDDIO2 is equal or above the threshold of the 272 * VDDIO2 voltage monitor (around 0.9 V). 273 * @arg @ref PWR_FLAG_TEMPL : VDDUSB ready flag (versus 1.2 V threshold). 274 * Indicates that VDDUSB is equal or above the threshold of the 275 * VDDUSB voltage monitor (around 1.2 V). 276 * @arg @ref PWR_FLAG_TEMPH : Currently applied VOS ready flag. 277 * Indicates that Vcore is equal to the current voltage scaling 278 * provided by ACTVOS. 279 * @arg @ref PWR_FLAG_SMPSEXTRDY: Voltage detector output flag. 280 * Indicates that Vdd is equal or above the PVD threshold selected 281 * by PVDLS. 282 * @arg @ref PWR_FLAG_AVDO : Regulator selection flag. 283 * Indicates the regulator selected. 284 * @arg @ref PWR_FLAG_MMCVDO : Temperature level flag (versus high threshold). 285 * Indicates the temperature is equal or above high threshold. 286 * @arg @ref PWR_FLAG_PVDO : Temperature level flag (versus low threshold). 287 * Indicates the temperature is equal or above low threshold. 288 * @arg @ref PWR_FLAG_USB33RDY : Backup domain voltage level flag (versus high threshold). 289 * Indicates the backup domain voltage level is equal or above high 290 * threshold. 291 * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. 292 * Indicates that a wakeup event was received from the WKUP line 1. 293 * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. 294 * Indicates that a wakeup event was received from the WKUP line 2. 295 * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. 296 * Indicates that a wakeup event was received from the WKUP line 3. 297 * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. 298 * Indicates that a wakeup event was received from the WKUP line 4. 299 * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. 300 * Indicates that a wakeup event was received from the WKUP line 5. 301 * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. 302 * Indicates that a wakeup event was received from the WKUP line 6. 303 * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. 304 * Indicates that a wakeup event was received from the WKUP line 7. 305 * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. 306 * Indicates that a wakeup event was received from the WKUP line 8. 307 * @note The PWR_WAKEUP_FLAG6, PWR_WAKEUP_FLAG7 AND PWR_WAKEUP_FLAG8 are not available for STM32H503xx devices. 308 * @retval The state of __FLAG__ (TRUE or FALSE). 309 */ 310 #if defined (PWR_WUSR_WUF6) 311 #define __HAL_PWR_GET_FLAG(__FLAG__) ( \ 312 ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) \ 313 == PWR_PMSR_STOPF) : \ 314 ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_SBF) \ 315 == PWR_PMSR_SBF) : \ 316 ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) \ 317 == PWR_VOSSR_VOSRDY) : \ 318 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY)\ 319 == PWR_VOSSR_ACTVOSRDY) : \ 320 ((__FLAG__) == PWR_FLAG_BRR) ? (READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) \ 321 == PWR_BDSR_BRRDY) : \ 322 ((__FLAG__) == PWR_FLAG_VBATL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) \ 323 == PWR_BDSR_VBATL) : \ 324 ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) \ 325 == PWR_BDSR_VBATH) : \ 326 ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) \ 327 == PWR_BDSR_TEMPL) : \ 328 ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) \ 329 == PWR_BDSR_TEMPH) : \ 330 ((__FLAG__) == PWR_FLAG_AVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) \ 331 == PWR_VMSR_AVDO) : \ 332 ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_VDDIO2RDY) \ 333 == PWR_VMSR_VDDIO2RDY) : \ 334 ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) \ 335 == PWR_VMSR_PVDO) : \ 336 ((__FLAG__) == PWR_FLAG_USB33RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_USB33RDY) \ 337 == PWR_VMSR_USB33RDY) : \ 338 \ 339 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) \ 340 == PWR_WUSR_WUF1) : \ 341 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) \ 342 == PWR_WUSR_WUF2) : \ 343 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) \ 344 == PWR_WUSR_WUF3) : \ 345 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) \ 346 == PWR_WUSR_WUF4) : \ 347 ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) \ 348 == PWR_WUSR_WUF5) : \ 349 ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) \ 350 == PWR_WUSR_WUF6) : \ 351 ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) \ 352 == PWR_WUSR_WUF7) : \ 353 (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) 354 #else 355 #define __HAL_PWR_GET_FLAG(__FLAG__) ( \ 356 ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) \ 357 == PWR_PMSR_STOPF) : \ 358 ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_SBF) \ 359 == PWR_PMSR_SBF) : \ 360 ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) \ 361 == PWR_VOSSR_VOSRDY) : \ 362 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY)\ 363 == PWR_VOSSR_ACTVOSRDY) : \ 364 ((__FLAG__) == PWR_FLAG_BRR) ? (READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) \ 365 == PWR_BDSR_BRRDY) : \ 366 ((__FLAG__) == PWR_FLAG_VBATL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) \ 367 == PWR_BDSR_VBATL) : \ 368 ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) \ 369 == PWR_BDSR_VBATH) : \ 370 ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) \ 371 == PWR_BDSR_TEMPL) : \ 372 ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) \ 373 == PWR_BDSR_TEMPH) : \ 374 ((__FLAG__) == PWR_FLAG_AVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) \ 375 == PWR_VMSR_AVDO) : \ 376 ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_VDDIO2RDY) \ 377 == PWR_VMSR_VDDIO2RDY) : \ 378 ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) \ 379 == PWR_VMSR_PVDO) : \ 380 \ 381 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) \ 382 == PWR_WUSR_WUF1) : \ 383 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) \ 384 == PWR_WUSR_WUF2) : \ 385 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) \ 386 == PWR_WUSR_WUF3) : \ 387 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) \ 388 == PWR_WUSR_WUF4) : \ 389 (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5)) 390 #endif /* PWR_WUSR_WUF6 */ 391 392 393 /** @brief Clear PWR flags. 394 * @param __FLAG__ : Specifies the flag to clear. 395 * This parameter can be one of the following values : 396 * @arg @ref PWR_FLAG_STOPF : STOP flag. 397 * Indicates that the device was resumed from STOP mode. 398 * @arg @ref PWR_FLAG_STANDBY : STANDBY flag. 399 * Indicates that the device was resumed from STANDBY mode. 400 * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. 401 * Indicates that a wakeup event was received from the WKUP line 1. 402 * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. 403 * Indicates that a wakeup event was received from the WKUP line 2. 404 * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. 405 * Indicates that a wakeup event was received from the WKUP line 3. 406 * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. 407 * Indicates that a wakeup event was received from the WKUP line 4. 408 * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. 409 * Indicates that a wakeup event was received from the WKUP line 5. 410 * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. 411 * Indicates that a wakeup event was received from the WKUP line 6. 412 * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. 413 * Indicates that a wakeup event was received from the WKUP line 7. 414 * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. 415 * Indicates that a wakeup event was received from the WKUP line 8. 416 * @note The PWR_WAKEUP_FLAG6, PWR_WAKEUP_FLAG7 AND PWR_WAKEUP_FLAG8 are not available for STM32H503xx devices. 417 * @retval None. 418 */ 419 #if defined (PWR_WUSCR_CWUF6) 420 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ 421 ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ 422 ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ 423 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ 424 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ 425 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ 426 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ 427 ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ 428 ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ 429 ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ 430 ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ 431 (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) 432 #else 433 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ 434 ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ 435 ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ 436 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ 437 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ 438 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ 439 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ 440 ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ 441 (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) 442 #endif /* PWR_WUSCR_CWUF6 */ 443 444 /** 445 * @brief Enable the PVD Extended Interrupt Line. 446 * @retval None. 447 */ 448 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 449 450 /** 451 * @brief Disable the PVD Extended Interrupt Line. 452 * @retval None. 453 */ 454 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 455 456 /** 457 * @brief Enable the PVD Event Line. 458 * @retval None. 459 */ 460 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) 461 462 /** 463 * @brief Disable the PVD Event Line. 464 * @retval None. 465 */ 466 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) 467 468 /** 469 * @brief Enable the PVD Extended Interrupt Rising Trigger. 470 * @retval None. 471 */ 472 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 473 474 /** 475 * @brief Disable the PVD Extended Interrupt Rising Trigger. 476 * @retval None. 477 */ 478 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 479 480 /** 481 * @brief Enable the PVD Extended Interrupt Falling Trigger. 482 * @retval None. 483 */ 484 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 485 486 /** 487 * @brief Disable the PVD Extended Interrupt Falling Trigger. 488 * @retval None. 489 */ 490 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 491 492 /** 493 * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. 494 * @retval None. 495 */ 496 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 497 do \ 498 { \ 499 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ 500 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ 501 } while(0) 502 503 /** 504 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 505 * @retval None. 506 */ 507 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 508 do \ 509 { \ 510 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 511 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 512 } while(0) 513 514 /** 515 * @brief Generate a Software Interrupt on selected EXTI line. 516 * @retval None 517 */ 518 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) 519 520 /** 521 * @brief Check whether the specified PVD EXTI Rising interrupt flag is set or not. 522 * @retval EXTI PVD Line Status. 523 */ 524 525 #define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() ((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVD)\ 526 == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) 527 528 /** 529 * @brief Check whether the specified PVD EXTI Falling interrupt flag is set or not. 530 * @retval EXTI PVD Line Status. 531 */ 532 533 #define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() ((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVD)\ 534 == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) 535 536 /** 537 * @brief Clear the PVD EXTI Interrupt flag. 538 * @retval None. 539 */ 540 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() \ 541 do \ 542 { \ 543 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); \ 544 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); \ 545 } while(0) 546 /** 547 * @} 548 */ 549 550 /* Private constants ---------------------------------------------------------*/ 551 552 /** @addtogroup PWR_Private_Constants PWR Private Constants 553 * @{ 554 */ 555 /* Define PVD extended interrupts and event line */ 556 #define PWR_EXTI_LINE_PVD (0x00010000UL) /*!< PVD EXTI Line */ 557 558 /* Defines wake up lines shift */ 559 #define PWR_EWUP_MASK (0x0FFF3F3FU) 560 561 /* Defines attribute */ 562 #define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */ 563 #define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */ 564 /** 565 * @} 566 */ 567 568 /* Private macros ------------------------------------------------------------*/ 569 570 /** @addtogroup PWR_Private_Macros PWR Private Macros 571 * @{ 572 */ 573 #if defined(PWR_WUCR_WUPEN6) 574 /* Check wake up pin parameter */ 575 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ 576 ((PIN) == PWR_WAKEUP_PIN2) ||\ 577 ((PIN) == PWR_WAKEUP_PIN3) ||\ 578 ((PIN) == PWR_WAKEUP_PIN4) ||\ 579 ((PIN) == PWR_WAKEUP_PIN5) ||\ 580 ((PIN) == PWR_WAKEUP_PIN6) ||\ 581 ((PIN) == PWR_WAKEUP_PIN7) ||\ 582 ((PIN) == PWR_WAKEUP_PIN8) ||\ 583 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 584 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 585 ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ 586 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 587 ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ 588 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ 589 ((PIN) == PWR_WAKEUP_PIN7_HIGH) ||\ 590 ((PIN) == PWR_WAKEUP_PIN8_HIGH) ||\ 591 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ 592 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 593 ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ 594 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 595 ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\ 596 ((PIN) == PWR_WAKEUP_PIN6_LOW) ||\ 597 ((PIN) == PWR_WAKEUP_PIN7_LOW) ||\ 598 ((PIN) == PWR_WAKEUP_PIN8_LOW)) 599 #else 600 /* Check wake up pin parameter */ 601 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ 602 ((PIN) == PWR_WAKEUP_PIN2) ||\ 603 ((PIN) == PWR_WAKEUP_PIN3) ||\ 604 ((PIN) == PWR_WAKEUP_PIN4) ||\ 605 ((PIN) == PWR_WAKEUP_PIN5) ||\ 606 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 607 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 608 ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ 609 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 610 ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ 611 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ 612 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 613 ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ 614 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 615 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 616 #endif /* PWR_WUCR_WUPEN6 */ 617 618 /* PVD level check macro */ 619 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || \ 620 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || \ 621 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) || \ 622 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 623 624 /* PVD mode check macro */ 625 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ 626 ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ 627 ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ 628 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ 629 ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ 630 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ 631 ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) 632 633 /* SLEEP mode entry check macro */ 634 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 635 636 /* STOP mode entry check macro */ 637 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 638 639 #if defined (PWR_SECCFGR_WUP1SEC) 640 /* PWR items check macro */ 641 #define IS_PWR_ITEMS_ATTRIBUTES(ITEM) ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U)) 642 #endif /* PWR_SECCFGR_WUP1SEC */ 643 644 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 645 /* PWR attribute check macro (Secure) */ 646 #define IS_PWR_ATTRIBUTES(ATTRIBUTES) ((((~(((ATTRIBUTES) &\ 647 0xF0U) >> 4U)) & \ 648 ((ATTRIBUTES) & 0x0FU)) == 0U) && (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U)) 649 #elif defined(PWR_PRIVCFGR_NSPRIV) 650 /* PWR attribute check macro (NSecure) */ 651 #define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV)) 652 #else 653 /* PWR attribute check macro (NSecure) */ 654 #define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NPRIV) || ((ATTRIBUTES) == PWR_PRIV)) 655 #endif /* __ARM_FEATURE_CMSE */ 656 /** 657 * @} 658 */ 659 660 /* Include PWR HAL Extended module */ 661 #include "stm32h5xx_hal_pwr_ex.h" 662 663 /* Exported functions --------------------------------------------------------*/ 664 665 /** @addtogroup PWR_Exported_Functions PWR Exported Functions 666 * @{ 667 */ 668 669 /** @addtogroup PWR_Exported_Functions_Group1 670 * @{ 671 */ 672 /* Initialization and de-initialization functions *****************************/ 673 void HAL_PWR_DeInit(void); 674 void HAL_PWR_EnableBkUpAccess(void); 675 void HAL_PWR_DisableBkUpAccess(void); 676 /** 677 * @} 678 */ 679 680 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 681 * @{ 682 */ 683 /* Programmable voltage detector functions ************************************/ 684 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); 685 void HAL_PWR_EnablePVD(void); 686 void HAL_PWR_DisablePVD(void); 687 688 /* Wake up pins configuration functions ***************************************/ 689 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); 690 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 691 692 /* Low power modes configuration functions ************************************/ 693 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 694 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 695 void HAL_PWR_EnterSTANDBYMode(void); 696 697 /* Sleep on exit and sev on pending configuration functions *******************/ 698 void HAL_PWR_EnableSleepOnExit(void); 699 void HAL_PWR_DisableSleepOnExit(void); 700 void HAL_PWR_EnableSEVOnPend(void); 701 void HAL_PWR_DisableSEVOnPend(void); 702 703 /* Interrupt handler functions ************************************************/ 704 void HAL_PWR_PVD_IRQHandler(void); 705 void HAL_PWR_PVDCallback(void); 706 /** 707 * @} 708 */ 709 710 /** @addtogroup PWR_Exported_Functions_Group3 Peripheral Security functions 711 * @{ 712 */ 713 /* Privileges and security configuration functions ****************************/ 714 void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes); 715 HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 716 /** 717 * @} 718 */ 719 720 /** 721 * @} 722 */ 723 724 /** 725 * @} 726 */ 727 728 /** 729 * @} 730 */ 731 732 /** 733 * @} 734 */ 735 736 #ifdef __cplusplus 737 } 738 #endif /* __cplusplus */ 739 740 #endif /* STM32H5xx_HAL_PWR_H */ 741
