1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32h5xx_hal.h"
324
325 /** @addtogroup STM32H5xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macro -------------------------------------------------------------*/
404 #if defined(HAL_DMA_MODULE_ENABLED)
405 /* Macro to get remaining data to transfer on DMA side */
406 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
407 #endif /* HAL_DMA_MODULE_ENABLED */
408
409 /* Private variables ---------------------------------------------------------*/
410 /* Private function prototypes -----------------------------------------------*/
411
412 /** @defgroup I2C_Private_Functions I2C Private Functions
413 * @{
414 */
415 #if defined(HAL_DMA_MODULE_ENABLED)
416 /* Private functions to handle DMA transfer */
417 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
418 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
419 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
420 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
421 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
422 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
423
424 #endif /* HAL_DMA_MODULE_ENABLED */
425
426 /* Private functions to handle IT transfer */
427 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
428 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
429 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
430 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
431 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
432 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
433 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
434
435 /* Private functions to handle IT transfer */
436 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
437 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
438 uint32_t Tickstart);
439 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
440 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
441 uint32_t Tickstart);
442
443 /* Private functions for I2C transfer IRQ handler */
444 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
445 uint32_t ITSources);
446 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
447 uint32_t ITSources);
448 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
449 uint32_t ITSources);
450 #if defined(HAL_DMA_MODULE_ENABLED)
451 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
452 uint32_t ITSources);
453 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
454 uint32_t ITSources);
455 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
456 uint32_t ITSources);
457 #endif /* HAL_DMA_MODULE_ENABLED */
458
459 /* Private functions to handle flags during polling transfer */
460 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
461 uint32_t Timeout, uint32_t Tickstart);
462 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
463 uint32_t Tickstart);
464 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
465 uint32_t Tickstart);
466 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
467 uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470
471 /* Private functions to centralize the enable/disable of Interrupts */
472 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
473 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
474
475 /* Private function to treat different error callback */
476 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
477
478 /* Private function to flush TXDR register */
479 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
480
481 /* Private function to handle start, restart or stop a transfer */
482 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
483 uint32_t Request);
484
485 /* Private function to Convert Specific options */
486 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
487 /**
488 * @}
489 */
490
491 /* Exported functions --------------------------------------------------------*/
492
493 /** @defgroup I2C_Exported_Functions I2C Exported Functions
494 * @{
495 */
496
497 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
498 * @brief Initialization and Configuration functions
499 *
500 @verbatim
501 ===============================================================================
502 ##### Initialization and de-initialization functions #####
503 ===============================================================================
504 [..] This subsection provides a set of functions allowing to initialize and
505 deinitialize the I2Cx peripheral:
506
507 (+) User must Implement HAL_I2C_MspInit() function in which he configures
508 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
509
510 (+) Call the function HAL_I2C_Init() to configure the selected device with
511 the selected configuration:
512 (++) Clock Timing
513 (++) Own Address 1
514 (++) Addressing mode (Master, Slave)
515 (++) Dual Addressing mode
516 (++) Own Address 2
517 (++) Own Address 2 Mask
518 (++) General call mode
519 (++) Nostretch mode
520
521 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
522 of the selected I2Cx peripheral.
523
524 @endverbatim
525 * @{
526 */
527
528 /**
529 * @brief Initializes the I2C according to the specified parameters
530 * in the I2C_InitTypeDef and initialize the associated handle.
531 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
532 * the configuration information for the specified I2C.
533 * @retval HAL status
534 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)535 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
536 {
537 /* Check the I2C handle allocation */
538 if (hi2c == NULL)
539 {
540 return HAL_ERROR;
541 }
542
543 /* Check the parameters */
544 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
545 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
546 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
547 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
548 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
549 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
550 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
551 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
552
553 if (hi2c->State == HAL_I2C_STATE_RESET)
554 {
555 /* Allocate lock resource and initialize it */
556 hi2c->Lock = HAL_UNLOCKED;
557
558 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
559 /* Init the I2C Callback settings */
560 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
561 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
562 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
563 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
564 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
565 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
566 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
567 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
568 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
569 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
570
571 if (hi2c->MspInitCallback == NULL)
572 {
573 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
574 }
575
576 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
577 hi2c->MspInitCallback(hi2c);
578 #else
579 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
580 HAL_I2C_MspInit(hi2c);
581 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
582 }
583
584 hi2c->State = HAL_I2C_STATE_BUSY;
585
586 /* Disable the selected I2C peripheral */
587 __HAL_I2C_DISABLE(hi2c);
588
589 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
590 /* Configure I2Cx: Frequency range */
591 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
592
593 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
594 /* Disable Own Address1 before set the Own Address1 configuration */
595 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
596
597 /* Configure I2Cx: Own Address1 and ack own address1 mode */
598 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
599 {
600 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
601 }
602 else /* I2C_ADDRESSINGMODE_10BIT */
603 {
604 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
605 }
606
607 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
608 /* Configure I2Cx: Addressing Master mode */
609 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
610 {
611 SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
612 }
613 else
614 {
615 /* Clear the I2C ADD10 bit */
616 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
617 }
618 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
619 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
620
621 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
622 /* Disable Own Address2 before set the Own Address2 configuration */
623 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
624
625 /* Configure I2Cx: Dual mode and Own Address2 */
626 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
627 (hi2c->Init.OwnAddress2Masks << 8));
628
629 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
630 /* Configure I2Cx: Generalcall and NoStretch mode */
631 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
632
633 /* Enable the selected I2C peripheral */
634 __HAL_I2C_ENABLE(hi2c);
635
636 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
637 hi2c->State = HAL_I2C_STATE_READY;
638 hi2c->PreviousState = I2C_STATE_NONE;
639 hi2c->Mode = HAL_I2C_MODE_NONE;
640
641 return HAL_OK;
642 }
643
644 /**
645 * @brief DeInitialize the I2C peripheral.
646 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
647 * the configuration information for the specified I2C.
648 * @retval HAL status
649 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)650 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
651 {
652 /* Check the I2C handle allocation */
653 if (hi2c == NULL)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Check the parameters */
659 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
660
661 hi2c->State = HAL_I2C_STATE_BUSY;
662
663 /* Disable the I2C Peripheral Clock */
664 __HAL_I2C_DISABLE(hi2c);
665
666 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
667 if (hi2c->MspDeInitCallback == NULL)
668 {
669 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
670 }
671
672 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
673 hi2c->MspDeInitCallback(hi2c);
674 #else
675 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
676 HAL_I2C_MspDeInit(hi2c);
677 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
678
679 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
680 hi2c->State = HAL_I2C_STATE_RESET;
681 hi2c->PreviousState = I2C_STATE_NONE;
682 hi2c->Mode = HAL_I2C_MODE_NONE;
683
684 /* Release Lock */
685 __HAL_UNLOCK(hi2c);
686
687 return HAL_OK;
688 }
689
690 /**
691 * @brief Initialize the I2C MSP.
692 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
693 * the configuration information for the specified I2C.
694 * @retval None
695 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)696 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
697 {
698 /* Prevent unused argument(s) compilation warning */
699 UNUSED(hi2c);
700
701 /* NOTE : This function should not be modified, when the callback is needed,
702 the HAL_I2C_MspInit could be implemented in the user file
703 */
704 }
705
706 /**
707 * @brief DeInitialize the I2C MSP.
708 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
709 * the configuration information for the specified I2C.
710 * @retval None
711 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)712 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
713 {
714 /* Prevent unused argument(s) compilation warning */
715 UNUSED(hi2c);
716
717 /* NOTE : This function should not be modified, when the callback is needed,
718 the HAL_I2C_MspDeInit could be implemented in the user file
719 */
720 }
721
722 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
723 /**
724 * @brief Register a User I2C Callback
725 * To be used instead of the weak predefined callback
726 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
727 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
728 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
729 * the configuration information for the specified I2C.
730 * @param CallbackID ID of the callback to be registered
731 * This parameter can be one of the following values:
732 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
733 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
734 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
735 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
736 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
737 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
738 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
739 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
740 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
741 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
742 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
743 * @param pCallback pointer to the Callback function
744 * @retval HAL status
745 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)746 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
747 pI2C_CallbackTypeDef pCallback)
748 {
749 HAL_StatusTypeDef status = HAL_OK;
750
751 if (pCallback == NULL)
752 {
753 /* Update the error code */
754 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
755
756 return HAL_ERROR;
757 }
758
759 if (HAL_I2C_STATE_READY == hi2c->State)
760 {
761 switch (CallbackID)
762 {
763 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
764 hi2c->MasterTxCpltCallback = pCallback;
765 break;
766
767 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
768 hi2c->MasterRxCpltCallback = pCallback;
769 break;
770
771 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
772 hi2c->SlaveTxCpltCallback = pCallback;
773 break;
774
775 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
776 hi2c->SlaveRxCpltCallback = pCallback;
777 break;
778
779 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
780 hi2c->ListenCpltCallback = pCallback;
781 break;
782
783 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
784 hi2c->MemTxCpltCallback = pCallback;
785 break;
786
787 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
788 hi2c->MemRxCpltCallback = pCallback;
789 break;
790
791 case HAL_I2C_ERROR_CB_ID :
792 hi2c->ErrorCallback = pCallback;
793 break;
794
795 case HAL_I2C_ABORT_CB_ID :
796 hi2c->AbortCpltCallback = pCallback;
797 break;
798
799 case HAL_I2C_MSPINIT_CB_ID :
800 hi2c->MspInitCallback = pCallback;
801 break;
802
803 case HAL_I2C_MSPDEINIT_CB_ID :
804 hi2c->MspDeInitCallback = pCallback;
805 break;
806
807 default :
808 /* Update the error code */
809 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
810
811 /* Return error status */
812 status = HAL_ERROR;
813 break;
814 }
815 }
816 else if (HAL_I2C_STATE_RESET == hi2c->State)
817 {
818 switch (CallbackID)
819 {
820 case HAL_I2C_MSPINIT_CB_ID :
821 hi2c->MspInitCallback = pCallback;
822 break;
823
824 case HAL_I2C_MSPDEINIT_CB_ID :
825 hi2c->MspDeInitCallback = pCallback;
826 break;
827
828 default :
829 /* Update the error code */
830 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
831
832 /* Return error status */
833 status = HAL_ERROR;
834 break;
835 }
836 }
837 else
838 {
839 /* Update the error code */
840 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
841
842 /* Return error status */
843 status = HAL_ERROR;
844 }
845
846 return status;
847 }
848
849 /**
850 * @brief Unregister an I2C Callback
851 * I2C callback is redirected to the weak predefined callback
852 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
853 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
854 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
855 * the configuration information for the specified I2C.
856 * @param CallbackID ID of the callback to be unregistered
857 * This parameter can be one of the following values:
858 * This parameter can be one of the following values:
859 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
860 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
861 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
862 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
863 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
864 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
865 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
866 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
867 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
868 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
869 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
870 * @retval HAL status
871 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)872 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
873 {
874 HAL_StatusTypeDef status = HAL_OK;
875
876 if (HAL_I2C_STATE_READY == hi2c->State)
877 {
878 switch (CallbackID)
879 {
880 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
881 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
882 break;
883
884 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
885 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
886 break;
887
888 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
889 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
890 break;
891
892 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
893 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
894 break;
895
896 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
897 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
898 break;
899
900 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
901 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
902 break;
903
904 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
905 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
906 break;
907
908 case HAL_I2C_ERROR_CB_ID :
909 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
910 break;
911
912 case HAL_I2C_ABORT_CB_ID :
913 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
914 break;
915
916 case HAL_I2C_MSPINIT_CB_ID :
917 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
918 break;
919
920 case HAL_I2C_MSPDEINIT_CB_ID :
921 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
922 break;
923
924 default :
925 /* Update the error code */
926 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
927
928 /* Return error status */
929 status = HAL_ERROR;
930 break;
931 }
932 }
933 else if (HAL_I2C_STATE_RESET == hi2c->State)
934 {
935 switch (CallbackID)
936 {
937 case HAL_I2C_MSPINIT_CB_ID :
938 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
939 break;
940
941 case HAL_I2C_MSPDEINIT_CB_ID :
942 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
943 break;
944
945 default :
946 /* Update the error code */
947 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
948
949 /* Return error status */
950 status = HAL_ERROR;
951 break;
952 }
953 }
954 else
955 {
956 /* Update the error code */
957 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
958
959 /* Return error status */
960 status = HAL_ERROR;
961 }
962
963 return status;
964 }
965
966 /**
967 * @brief Register the Slave Address Match I2C Callback
968 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
969 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
970 * the configuration information for the specified I2C.
971 * @param pCallback pointer to the Address Match Callback function
972 * @retval HAL status
973 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)974 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
975 {
976 HAL_StatusTypeDef status = HAL_OK;
977
978 if (pCallback == NULL)
979 {
980 /* Update the error code */
981 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
982
983 return HAL_ERROR;
984 }
985
986 if (HAL_I2C_STATE_READY == hi2c->State)
987 {
988 hi2c->AddrCallback = pCallback;
989 }
990 else
991 {
992 /* Update the error code */
993 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
994
995 /* Return error status */
996 status = HAL_ERROR;
997 }
998
999 return status;
1000 }
1001
1002 /**
1003 * @brief UnRegister the Slave Address Match I2C Callback
1004 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1005 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1006 * the configuration information for the specified I2C.
1007 * @retval HAL status
1008 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1009 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1010 {
1011 HAL_StatusTypeDef status = HAL_OK;
1012
1013 if (HAL_I2C_STATE_READY == hi2c->State)
1014 {
1015 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1016 }
1017 else
1018 {
1019 /* Update the error code */
1020 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1021
1022 /* Return error status */
1023 status = HAL_ERROR;
1024 }
1025
1026 return status;
1027 }
1028
1029 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1030
1031 /**
1032 * @}
1033 */
1034
1035 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1036 * @brief Data transfers functions
1037 *
1038 @verbatim
1039 ===============================================================================
1040 ##### IO operation functions #####
1041 ===============================================================================
1042 [..]
1043 This subsection provides a set of functions allowing to manage the I2C data
1044 transfers.
1045
1046 (#) There are two modes of transfer:
1047 (++) Blocking mode : The communication is performed in the polling mode.
1048 The status of all data processing is returned by the same function
1049 after finishing transfer.
1050 (++) No-Blocking mode : The communication is performed using Interrupts
1051 or DMA. These functions return the status of the transfer startup.
1052 The end of the data processing will be indicated through the
1053 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1054 using DMA mode.
1055
1056 (#) Blocking mode functions are :
1057 (++) HAL_I2C_Master_Transmit()
1058 (++) HAL_I2C_Master_Receive()
1059 (++) HAL_I2C_Slave_Transmit()
1060 (++) HAL_I2C_Slave_Receive()
1061 (++) HAL_I2C_Mem_Write()
1062 (++) HAL_I2C_Mem_Read()
1063 (++) HAL_I2C_IsDeviceReady()
1064
1065 (#) No-Blocking mode functions with Interrupt are :
1066 (++) HAL_I2C_Master_Transmit_IT()
1067 (++) HAL_I2C_Master_Receive_IT()
1068 (++) HAL_I2C_Slave_Transmit_IT()
1069 (++) HAL_I2C_Slave_Receive_IT()
1070 (++) HAL_I2C_Mem_Write_IT()
1071 (++) HAL_I2C_Mem_Read_IT()
1072 (++) HAL_I2C_Master_Seq_Transmit_IT()
1073 (++) HAL_I2C_Master_Seq_Receive_IT()
1074 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1075 (++) HAL_I2C_Slave_Seq_Receive_IT()
1076 (++) HAL_I2C_EnableListen_IT()
1077 (++) HAL_I2C_DisableListen_IT()
1078 (++) HAL_I2C_Master_Abort_IT()
1079
1080 (#) No-Blocking mode functions with DMA are :
1081 (++) HAL_I2C_Master_Transmit_DMA()
1082 (++) HAL_I2C_Master_Receive_DMA()
1083 (++) HAL_I2C_Slave_Transmit_DMA()
1084 (++) HAL_I2C_Slave_Receive_DMA()
1085 (++) HAL_I2C_Mem_Write_DMA()
1086 (++) HAL_I2C_Mem_Read_DMA()
1087 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1088 (++) HAL_I2C_Master_Seq_Receive_DMA()
1089 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1090 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1091
1092 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1093 (++) HAL_I2C_MasterTxCpltCallback()
1094 (++) HAL_I2C_MasterRxCpltCallback()
1095 (++) HAL_I2C_SlaveTxCpltCallback()
1096 (++) HAL_I2C_SlaveRxCpltCallback()
1097 (++) HAL_I2C_MemTxCpltCallback()
1098 (++) HAL_I2C_MemRxCpltCallback()
1099 (++) HAL_I2C_AddrCallback()
1100 (++) HAL_I2C_ListenCpltCallback()
1101 (++) HAL_I2C_ErrorCallback()
1102 (++) HAL_I2C_AbortCpltCallback()
1103
1104 @endverbatim
1105 * @{
1106 */
1107
1108 /**
1109 * @brief Transmits in master mode an amount of data in blocking mode.
1110 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1111 * the configuration information for the specified I2C.
1112 * @param DevAddress Target device address: The device 7 bits address value
1113 * in datasheet must be shifted to the left before calling the interface
1114 * @param pData Pointer to data buffer
1115 * @param Size Amount of data to be sent
1116 * @param Timeout Timeout duration
1117 * @retval HAL status
1118 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1119 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1120 uint16_t Size, uint32_t Timeout)
1121 {
1122 uint32_t tickstart;
1123
1124 if (hi2c->State == HAL_I2C_STATE_READY)
1125 {
1126 /* Process Locked */
1127 __HAL_LOCK(hi2c);
1128
1129 /* Init tickstart for timeout management*/
1130 tickstart = HAL_GetTick();
1131
1132 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1133 {
1134 return HAL_ERROR;
1135 }
1136
1137 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1138 hi2c->Mode = HAL_I2C_MODE_MASTER;
1139 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1140
1141 /* Prepare transfer parameters */
1142 hi2c->pBuffPtr = pData;
1143 hi2c->XferCount = Size;
1144 hi2c->XferISR = NULL;
1145
1146 /* Send Slave Address */
1147 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1148 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1149 {
1150 hi2c->XferSize = MAX_NBYTE_SIZE;
1151 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1152 I2C_GENERATE_START_WRITE);
1153 }
1154 else
1155 {
1156 hi2c->XferSize = hi2c->XferCount;
1157 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1158 I2C_GENERATE_START_WRITE);
1159 }
1160
1161 while (hi2c->XferCount > 0U)
1162 {
1163 /* Wait until TXIS flag is set */
1164 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1165 {
1166 return HAL_ERROR;
1167 }
1168 /* Write data to TXDR */
1169 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1170
1171 /* Increment Buffer pointer */
1172 hi2c->pBuffPtr++;
1173
1174 hi2c->XferCount--;
1175 hi2c->XferSize--;
1176
1177 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1178 {
1179 /* Wait until TCR flag is set */
1180 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1181 {
1182 return HAL_ERROR;
1183 }
1184
1185 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1186 {
1187 hi2c->XferSize = MAX_NBYTE_SIZE;
1188 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1189 I2C_NO_STARTSTOP);
1190 }
1191 else
1192 {
1193 hi2c->XferSize = hi2c->XferCount;
1194 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1195 I2C_NO_STARTSTOP);
1196 }
1197 }
1198 }
1199
1200 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1201 /* Wait until STOPF flag is set */
1202 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1203 {
1204 return HAL_ERROR;
1205 }
1206
1207 /* Clear STOP Flag */
1208 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1209
1210 /* Clear Configuration Register 2 */
1211 I2C_RESET_CR2(hi2c);
1212
1213 hi2c->State = HAL_I2C_STATE_READY;
1214 hi2c->Mode = HAL_I2C_MODE_NONE;
1215
1216 /* Process Unlocked */
1217 __HAL_UNLOCK(hi2c);
1218
1219 return HAL_OK;
1220 }
1221 else
1222 {
1223 return HAL_BUSY;
1224 }
1225 }
1226
1227 /**
1228 * @brief Receives in master mode an amount of data in blocking mode.
1229 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1230 * the configuration information for the specified I2C.
1231 * @param DevAddress Target device address: The device 7 bits address value
1232 * in datasheet must be shifted to the left before calling the interface
1233 * @param pData Pointer to data buffer
1234 * @param Size Amount of data to be sent
1235 * @param Timeout Timeout duration
1236 * @retval HAL status
1237 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1238 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1239 uint16_t Size, uint32_t Timeout)
1240 {
1241 uint32_t tickstart;
1242
1243 if (hi2c->State == HAL_I2C_STATE_READY)
1244 {
1245 /* Process Locked */
1246 __HAL_LOCK(hi2c);
1247
1248 /* Init tickstart for timeout management*/
1249 tickstart = HAL_GetTick();
1250
1251 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1252 {
1253 return HAL_ERROR;
1254 }
1255
1256 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1257 hi2c->Mode = HAL_I2C_MODE_MASTER;
1258 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1259
1260 /* Prepare transfer parameters */
1261 hi2c->pBuffPtr = pData;
1262 hi2c->XferCount = Size;
1263 hi2c->XferISR = NULL;
1264
1265 /* Send Slave Address */
1266 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1267 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1268 {
1269 hi2c->XferSize = MAX_NBYTE_SIZE;
1270 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1271 I2C_GENERATE_START_READ);
1272 }
1273 else
1274 {
1275 hi2c->XferSize = hi2c->XferCount;
1276 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1277 I2C_GENERATE_START_READ);
1278 }
1279
1280 while (hi2c->XferCount > 0U)
1281 {
1282 /* Wait until RXNE flag is set */
1283 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1284 {
1285 return HAL_ERROR;
1286 }
1287
1288 /* Read data from RXDR */
1289 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1290
1291 /* Increment Buffer pointer */
1292 hi2c->pBuffPtr++;
1293
1294 hi2c->XferSize--;
1295 hi2c->XferCount--;
1296
1297 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1298 {
1299 /* Wait until TCR flag is set */
1300 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1301 {
1302 return HAL_ERROR;
1303 }
1304
1305 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1306 {
1307 hi2c->XferSize = MAX_NBYTE_SIZE;
1308 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1309 I2C_NO_STARTSTOP);
1310 }
1311 else
1312 {
1313 hi2c->XferSize = hi2c->XferCount;
1314 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1315 I2C_NO_STARTSTOP);
1316 }
1317 }
1318 }
1319
1320 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1321 /* Wait until STOPF flag is set */
1322 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1323 {
1324 return HAL_ERROR;
1325 }
1326
1327 /* Clear STOP Flag */
1328 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1329
1330 /* Clear Configuration Register 2 */
1331 I2C_RESET_CR2(hi2c);
1332
1333 hi2c->State = HAL_I2C_STATE_READY;
1334 hi2c->Mode = HAL_I2C_MODE_NONE;
1335
1336 /* Process Unlocked */
1337 __HAL_UNLOCK(hi2c);
1338
1339 return HAL_OK;
1340 }
1341 else
1342 {
1343 return HAL_BUSY;
1344 }
1345 }
1346
1347 /**
1348 * @brief Transmits in slave mode an amount of data in blocking mode.
1349 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1350 * the configuration information for the specified I2C.
1351 * @param pData Pointer to data buffer
1352 * @param Size Amount of data to be sent
1353 * @param Timeout Timeout duration
1354 * @retval HAL status
1355 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1356 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1357 uint32_t Timeout)
1358 {
1359 uint32_t tickstart;
1360
1361 if (hi2c->State == HAL_I2C_STATE_READY)
1362 {
1363 if ((pData == NULL) || (Size == 0U))
1364 {
1365 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1366 return HAL_ERROR;
1367 }
1368 /* Process Locked */
1369 __HAL_LOCK(hi2c);
1370
1371 /* Init tickstart for timeout management*/
1372 tickstart = HAL_GetTick();
1373
1374 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1375 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1376 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1377
1378 /* Prepare transfer parameters */
1379 hi2c->pBuffPtr = pData;
1380 hi2c->XferCount = Size;
1381 hi2c->XferISR = NULL;
1382
1383 /* Enable Address Acknowledge */
1384 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1385
1386 /* Wait until ADDR flag is set */
1387 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1388 {
1389 /* Disable Address Acknowledge */
1390 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1391 return HAL_ERROR;
1392 }
1393
1394 /* Preload TX data if no stretch enable */
1395 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1396 {
1397 /* Preload TX register */
1398 /* Write data to TXDR */
1399 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1400
1401 /* Increment Buffer pointer */
1402 hi2c->pBuffPtr++;
1403
1404 hi2c->XferCount--;
1405 }
1406
1407 /* Clear ADDR flag */
1408 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1409
1410 /* If 10bit addressing mode is selected */
1411 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1412 {
1413 /* Wait until ADDR flag is set */
1414 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1415 {
1416 /* Disable Address Acknowledge */
1417 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1418 return HAL_ERROR;
1419 }
1420
1421 /* Clear ADDR flag */
1422 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1423 }
1424
1425 /* Wait until DIR flag is set Transmitter mode */
1426 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1427 {
1428 /* Disable Address Acknowledge */
1429 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1430 return HAL_ERROR;
1431 }
1432
1433 while (hi2c->XferCount > 0U)
1434 {
1435 /* Wait until TXIS flag is set */
1436 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1437 {
1438 /* Disable Address Acknowledge */
1439 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1440 return HAL_ERROR;
1441 }
1442
1443 /* Write data to TXDR */
1444 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1445
1446 /* Increment Buffer pointer */
1447 hi2c->pBuffPtr++;
1448
1449 hi2c->XferCount--;
1450 }
1451
1452 /* Wait until AF flag is set */
1453 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1454 {
1455 /* Disable Address Acknowledge */
1456 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1457 return HAL_ERROR;
1458 }
1459
1460 /* Flush TX register */
1461 I2C_Flush_TXDR(hi2c);
1462
1463 /* Clear AF flag */
1464 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1465
1466 /* Wait until STOP flag is set */
1467 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1468 {
1469 /* Disable Address Acknowledge */
1470 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1471
1472 return HAL_ERROR;
1473 }
1474
1475 /* Clear STOP flag */
1476 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1477
1478 /* Wait until BUSY flag is reset */
1479 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1480 {
1481 /* Disable Address Acknowledge */
1482 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1483 return HAL_ERROR;
1484 }
1485
1486 /* Disable Address Acknowledge */
1487 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1488
1489 hi2c->State = HAL_I2C_STATE_READY;
1490 hi2c->Mode = HAL_I2C_MODE_NONE;
1491
1492 /* Process Unlocked */
1493 __HAL_UNLOCK(hi2c);
1494
1495 return HAL_OK;
1496 }
1497 else
1498 {
1499 return HAL_BUSY;
1500 }
1501 }
1502
1503 /**
1504 * @brief Receive in slave mode an amount of data in blocking mode
1505 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1506 * the configuration information for the specified I2C.
1507 * @param pData Pointer to data buffer
1508 * @param Size Amount of data to be sent
1509 * @param Timeout Timeout duration
1510 * @retval HAL status
1511 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1512 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1513 uint32_t Timeout)
1514 {
1515 uint32_t tickstart;
1516
1517 if (hi2c->State == HAL_I2C_STATE_READY)
1518 {
1519 if ((pData == NULL) || (Size == 0U))
1520 {
1521 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1522 return HAL_ERROR;
1523 }
1524 /* Process Locked */
1525 __HAL_LOCK(hi2c);
1526
1527 /* Init tickstart for timeout management*/
1528 tickstart = HAL_GetTick();
1529
1530 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1531 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1532 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1533
1534 /* Prepare transfer parameters */
1535 hi2c->pBuffPtr = pData;
1536 hi2c->XferCount = Size;
1537 hi2c->XferSize = hi2c->XferCount;
1538 hi2c->XferISR = NULL;
1539
1540 /* Enable Address Acknowledge */
1541 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1542
1543 /* Wait until ADDR flag is set */
1544 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1545 {
1546 /* Disable Address Acknowledge */
1547 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1548 return HAL_ERROR;
1549 }
1550
1551 /* Clear ADDR flag */
1552 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1553
1554 /* Wait until DIR flag is reset Receiver mode */
1555 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1556 {
1557 /* Disable Address Acknowledge */
1558 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1559 return HAL_ERROR;
1560 }
1561
1562 while (hi2c->XferCount > 0U)
1563 {
1564 /* Wait until RXNE flag is set */
1565 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1566 {
1567 /* Disable Address Acknowledge */
1568 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1569
1570 /* Store Last receive data if any */
1571 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1572 {
1573 /* Read data from RXDR */
1574 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1575
1576 /* Increment Buffer pointer */
1577 hi2c->pBuffPtr++;
1578
1579 hi2c->XferCount--;
1580 hi2c->XferSize--;
1581 }
1582
1583 return HAL_ERROR;
1584 }
1585
1586 /* Read data from RXDR */
1587 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1588
1589 /* Increment Buffer pointer */
1590 hi2c->pBuffPtr++;
1591
1592 hi2c->XferCount--;
1593 hi2c->XferSize--;
1594 }
1595
1596 /* Wait until STOP flag is set */
1597 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1598 {
1599 /* Disable Address Acknowledge */
1600 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1601 return HAL_ERROR;
1602 }
1603
1604 /* Clear STOP flag */
1605 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1606
1607 /* Wait until BUSY flag is reset */
1608 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1609 {
1610 /* Disable Address Acknowledge */
1611 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1612 return HAL_ERROR;
1613 }
1614
1615 /* Disable Address Acknowledge */
1616 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1617
1618 hi2c->State = HAL_I2C_STATE_READY;
1619 hi2c->Mode = HAL_I2C_MODE_NONE;
1620
1621 /* Process Unlocked */
1622 __HAL_UNLOCK(hi2c);
1623
1624 return HAL_OK;
1625 }
1626 else
1627 {
1628 return HAL_BUSY;
1629 }
1630 }
1631
1632 /**
1633 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1634 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1635 * the configuration information for the specified I2C.
1636 * @param DevAddress Target device address: The device 7 bits address value
1637 * in datasheet must be shifted to the left before calling the interface
1638 * @param pData Pointer to data buffer
1639 * @param Size Amount of data to be sent
1640 * @retval HAL status
1641 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1642 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1643 uint16_t Size)
1644 {
1645 uint32_t xfermode;
1646
1647 if (hi2c->State == HAL_I2C_STATE_READY)
1648 {
1649 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1650 {
1651 return HAL_BUSY;
1652 }
1653
1654 /* Process Locked */
1655 __HAL_LOCK(hi2c);
1656
1657 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1658 hi2c->Mode = HAL_I2C_MODE_MASTER;
1659 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1660
1661 /* Prepare transfer parameters */
1662 hi2c->pBuffPtr = pData;
1663 hi2c->XferCount = Size;
1664 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1665 hi2c->XferISR = I2C_Master_ISR_IT;
1666
1667 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1668 {
1669 hi2c->XferSize = MAX_NBYTE_SIZE;
1670 xfermode = I2C_RELOAD_MODE;
1671 }
1672 else
1673 {
1674 hi2c->XferSize = hi2c->XferCount;
1675 xfermode = I2C_AUTOEND_MODE;
1676 }
1677
1678 /* Send Slave Address */
1679 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1680 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1681
1682 /* Process Unlocked */
1683 __HAL_UNLOCK(hi2c);
1684
1685 /* Note : The I2C interrupts must be enabled after unlocking current process
1686 to avoid the risk of I2C interrupt handle execution before current
1687 process unlock */
1688
1689 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1690 /* possible to enable all of these */
1691 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1692 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1693 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1694
1695 return HAL_OK;
1696 }
1697 else
1698 {
1699 return HAL_BUSY;
1700 }
1701 }
1702
1703 /**
1704 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1705 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1706 * the configuration information for the specified I2C.
1707 * @param DevAddress Target device address: The device 7 bits address value
1708 * in datasheet must be shifted to the left before calling the interface
1709 * @param pData Pointer to data buffer
1710 * @param Size Amount of data to be sent
1711 * @retval HAL status
1712 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1713 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1714 uint16_t Size)
1715 {
1716 uint32_t xfermode;
1717
1718 if (hi2c->State == HAL_I2C_STATE_READY)
1719 {
1720 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1721 {
1722 return HAL_BUSY;
1723 }
1724
1725 /* Process Locked */
1726 __HAL_LOCK(hi2c);
1727
1728 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1729 hi2c->Mode = HAL_I2C_MODE_MASTER;
1730 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1731
1732 /* Prepare transfer parameters */
1733 hi2c->pBuffPtr = pData;
1734 hi2c->XferCount = Size;
1735 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1736 hi2c->XferISR = I2C_Master_ISR_IT;
1737
1738 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1739 {
1740 hi2c->XferSize = MAX_NBYTE_SIZE;
1741 xfermode = I2C_RELOAD_MODE;
1742 }
1743 else
1744 {
1745 hi2c->XferSize = hi2c->XferCount;
1746 xfermode = I2C_AUTOEND_MODE;
1747 }
1748
1749 /* Send Slave Address */
1750 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1751 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1752
1753 /* Process Unlocked */
1754 __HAL_UNLOCK(hi2c);
1755
1756 /* Note : The I2C interrupts must be enabled after unlocking current process
1757 to avoid the risk of I2C interrupt handle execution before current
1758 process unlock */
1759
1760 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1761 /* possible to enable all of these */
1762 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1763 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1764 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1765
1766 return HAL_OK;
1767 }
1768 else
1769 {
1770 return HAL_BUSY;
1771 }
1772 }
1773
1774 /**
1775 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1776 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1777 * the configuration information for the specified I2C.
1778 * @param pData Pointer to data buffer
1779 * @param Size Amount of data to be sent
1780 * @retval HAL status
1781 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1782 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1783 {
1784 if (hi2c->State == HAL_I2C_STATE_READY)
1785 {
1786 /* Process Locked */
1787 __HAL_LOCK(hi2c);
1788
1789 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1790 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1791 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1792
1793 /* Enable Address Acknowledge */
1794 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1795
1796 /* Prepare transfer parameters */
1797 hi2c->pBuffPtr = pData;
1798 hi2c->XferCount = Size;
1799 hi2c->XferSize = hi2c->XferCount;
1800 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1801 hi2c->XferISR = I2C_Slave_ISR_IT;
1802
1803 /* Preload TX data if no stretch enable */
1804 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1805 {
1806 /* Preload TX register */
1807 /* Write data to TXDR */
1808 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1809
1810 /* Increment Buffer pointer */
1811 hi2c->pBuffPtr++;
1812
1813 hi2c->XferCount--;
1814 hi2c->XferSize--;
1815 }
1816
1817 /* Process Unlocked */
1818 __HAL_UNLOCK(hi2c);
1819
1820 /* Note : The I2C interrupts must be enabled after unlocking current process
1821 to avoid the risk of I2C interrupt handle execution before current
1822 process unlock */
1823
1824 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1825 /* possible to enable all of these */
1826 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1827 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1828 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1829
1830 return HAL_OK;
1831 }
1832 else
1833 {
1834 return HAL_BUSY;
1835 }
1836 }
1837
1838 /**
1839 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1840 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1841 * the configuration information for the specified I2C.
1842 * @param pData Pointer to data buffer
1843 * @param Size Amount of data to be sent
1844 * @retval HAL status
1845 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1846 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1847 {
1848 if (hi2c->State == HAL_I2C_STATE_READY)
1849 {
1850 /* Process Locked */
1851 __HAL_LOCK(hi2c);
1852
1853 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1854 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1855 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1856
1857 /* Enable Address Acknowledge */
1858 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1859
1860 /* Prepare transfer parameters */
1861 hi2c->pBuffPtr = pData;
1862 hi2c->XferCount = Size;
1863 hi2c->XferSize = hi2c->XferCount;
1864 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1865 hi2c->XferISR = I2C_Slave_ISR_IT;
1866
1867 /* Process Unlocked */
1868 __HAL_UNLOCK(hi2c);
1869
1870 /* Note : The I2C interrupts must be enabled after unlocking current process
1871 to avoid the risk of I2C interrupt handle execution before current
1872 process unlock */
1873
1874 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1875 /* possible to enable all of these */
1876 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1877 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1878 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1879
1880 return HAL_OK;
1881 }
1882 else
1883 {
1884 return HAL_BUSY;
1885 }
1886 }
1887
1888 #if defined(HAL_DMA_MODULE_ENABLED)
1889 /**
1890 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1891 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1892 * the configuration information for the specified I2C.
1893 * @param DevAddress Target device address: The device 7 bits address value
1894 * in datasheet must be shifted to the left before calling the interface
1895 * @param pData Pointer to data buffer
1896 * @param Size Amount of data to be sent
1897 * @retval HAL status
1898 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1899 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1900 uint16_t Size)
1901 {
1902 uint32_t xfermode;
1903 HAL_StatusTypeDef dmaxferstatus;
1904
1905 if (hi2c->State == HAL_I2C_STATE_READY)
1906 {
1907 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1908 {
1909 return HAL_BUSY;
1910 }
1911
1912 /* Process Locked */
1913 __HAL_LOCK(hi2c);
1914
1915 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1916 hi2c->Mode = HAL_I2C_MODE_MASTER;
1917 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1918
1919 /* Prepare transfer parameters */
1920 hi2c->pBuffPtr = pData;
1921 hi2c->XferCount = Size;
1922 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1923 hi2c->XferISR = I2C_Master_ISR_DMA;
1924
1925 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1926 {
1927 hi2c->XferSize = MAX_NBYTE_SIZE;
1928 xfermode = I2C_RELOAD_MODE;
1929 }
1930 else
1931 {
1932 hi2c->XferSize = hi2c->XferCount;
1933 xfermode = I2C_AUTOEND_MODE;
1934 }
1935
1936 if (hi2c->XferSize > 0U)
1937 {
1938 if (hi2c->hdmatx != NULL)
1939 {
1940 /* Set the I2C DMA transfer complete callback */
1941 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1942
1943 /* Set the DMA error callback */
1944 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1945
1946 /* Set the unused DMA callbacks to NULL */
1947 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1948 hi2c->hdmatx->XferAbortCallback = NULL;
1949
1950 /* Enable the DMA channel */
1951 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1952 {
1953 if (hi2c->hdmatx->LinkedListQueue != NULL)
1954 {
1955 /* Set DMA data size */
1956 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
1957
1958 /* Set DMA source address */
1959 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
1960
1961 /* Set DMA destination address */
1962 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
1963 = (uint32_t)&hi2c->Instance->TXDR;
1964
1965 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
1966 }
1967 else
1968 {
1969 /* Update I2C state */
1970 hi2c->State = HAL_I2C_STATE_READY;
1971 hi2c->Mode = HAL_I2C_MODE_NONE;
1972
1973 /* Update I2C error code */
1974 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1975
1976 /* Process Unlocked */
1977 __HAL_UNLOCK(hi2c);
1978
1979 return HAL_ERROR;
1980 }
1981 }
1982 else
1983 {
1984 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
1985 hi2c->XferSize);
1986 }
1987 }
1988 else
1989 {
1990 /* Update I2C state */
1991 hi2c->State = HAL_I2C_STATE_READY;
1992 hi2c->Mode = HAL_I2C_MODE_NONE;
1993
1994 /* Update I2C error code */
1995 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1996
1997 /* Process Unlocked */
1998 __HAL_UNLOCK(hi2c);
1999
2000 return HAL_ERROR;
2001 }
2002
2003 if (dmaxferstatus == HAL_OK)
2004 {
2005 /* Send Slave Address */
2006 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2007 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
2008
2009 /* Update XferCount value */
2010 hi2c->XferCount -= hi2c->XferSize;
2011
2012 /* Process Unlocked */
2013 __HAL_UNLOCK(hi2c);
2014
2015 /* Note : The I2C interrupts must be enabled after unlocking current process
2016 to avoid the risk of I2C interrupt handle execution before current
2017 process unlock */
2018 /* Enable ERR and NACK interrupts */
2019 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2020
2021 /* Enable DMA Request */
2022 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2023 }
2024 else
2025 {
2026 /* Update I2C state */
2027 hi2c->State = HAL_I2C_STATE_READY;
2028 hi2c->Mode = HAL_I2C_MODE_NONE;
2029
2030 /* Update I2C error code */
2031 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2032
2033 /* Process Unlocked */
2034 __HAL_UNLOCK(hi2c);
2035
2036 return HAL_ERROR;
2037 }
2038 }
2039 else
2040 {
2041 /* Update Transfer ISR function pointer */
2042 hi2c->XferISR = I2C_Master_ISR_IT;
2043
2044 /* Send Slave Address */
2045 /* Set NBYTES to write and generate START condition */
2046 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2047 I2C_GENERATE_START_WRITE);
2048
2049 /* Process Unlocked */
2050 __HAL_UNLOCK(hi2c);
2051
2052 /* Note : The I2C interrupts must be enabled after unlocking current process
2053 to avoid the risk of I2C interrupt handle execution before current
2054 process unlock */
2055 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2056 /* possible to enable all of these */
2057 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2058 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2059 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2060 }
2061
2062 return HAL_OK;
2063 }
2064 else
2065 {
2066 return HAL_BUSY;
2067 }
2068 }
2069
2070 /**
2071 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2072 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2073 * the configuration information for the specified I2C.
2074 * @param DevAddress Target device address: The device 7 bits address value
2075 * in datasheet must be shifted to the left before calling the interface
2076 * @param pData Pointer to data buffer
2077 * @param Size Amount of data to be sent
2078 * @retval HAL status
2079 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2080 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2081 uint16_t Size)
2082 {
2083 uint32_t xfermode;
2084 HAL_StatusTypeDef dmaxferstatus;
2085
2086 if (hi2c->State == HAL_I2C_STATE_READY)
2087 {
2088 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2089 {
2090 return HAL_BUSY;
2091 }
2092
2093 /* Process Locked */
2094 __HAL_LOCK(hi2c);
2095
2096 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2097 hi2c->Mode = HAL_I2C_MODE_MASTER;
2098 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2099
2100 /* Prepare transfer parameters */
2101 hi2c->pBuffPtr = pData;
2102 hi2c->XferCount = Size;
2103 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2104 hi2c->XferISR = I2C_Master_ISR_DMA;
2105
2106 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2107 {
2108 hi2c->XferSize = MAX_NBYTE_SIZE;
2109 xfermode = I2C_RELOAD_MODE;
2110 }
2111 else
2112 {
2113 hi2c->XferSize = hi2c->XferCount;
2114 xfermode = I2C_AUTOEND_MODE;
2115 }
2116
2117 if (hi2c->XferSize > 0U)
2118 {
2119 if (hi2c->hdmarx != NULL)
2120 {
2121 /* Set the I2C DMA transfer complete callback */
2122 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2123
2124 /* Set the DMA error callback */
2125 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2126
2127 /* Set the unused DMA callbacks to NULL */
2128 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2129 hi2c->hdmarx->XferAbortCallback = NULL;
2130
2131 /* Enable the DMA channel */
2132 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2133 {
2134 if (hi2c->hdmarx->LinkedListQueue != NULL)
2135 {
2136 /* Set DMA data size */
2137 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2138
2139 /* Set DMA source address */
2140 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2141 = (uint32_t)&hi2c->Instance->RXDR;
2142
2143 /* Set DMA destination address */
2144 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2145
2146 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2147 }
2148 else
2149 {
2150 /* Update I2C state */
2151 hi2c->State = HAL_I2C_STATE_READY;
2152 hi2c->Mode = HAL_I2C_MODE_NONE;
2153
2154 /* Update I2C error code */
2155 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2156
2157 /* Process Unlocked */
2158 __HAL_UNLOCK(hi2c);
2159
2160 return HAL_ERROR;
2161 }
2162 }
2163 else
2164 {
2165 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2166 hi2c->XferSize);
2167 }
2168 }
2169 else
2170 {
2171 /* Update I2C state */
2172 hi2c->State = HAL_I2C_STATE_READY;
2173 hi2c->Mode = HAL_I2C_MODE_NONE;
2174
2175 /* Update I2C error code */
2176 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2177
2178 /* Process Unlocked */
2179 __HAL_UNLOCK(hi2c);
2180
2181 return HAL_ERROR;
2182 }
2183
2184 if (dmaxferstatus == HAL_OK)
2185 {
2186 /* Send Slave Address */
2187 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2188 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2189
2190 /* Update XferCount value */
2191 hi2c->XferCount -= hi2c->XferSize;
2192
2193 /* Process Unlocked */
2194 __HAL_UNLOCK(hi2c);
2195
2196 /* Note : The I2C interrupts must be enabled after unlocking current process
2197 to avoid the risk of I2C interrupt handle execution before current
2198 process unlock */
2199 /* Enable ERR and NACK interrupts */
2200 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2201
2202 /* Enable DMA Request */
2203 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2204 }
2205 else
2206 {
2207 /* Update I2C state */
2208 hi2c->State = HAL_I2C_STATE_READY;
2209 hi2c->Mode = HAL_I2C_MODE_NONE;
2210
2211 /* Update I2C error code */
2212 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2213
2214 /* Process Unlocked */
2215 __HAL_UNLOCK(hi2c);
2216
2217 return HAL_ERROR;
2218 }
2219 }
2220 else
2221 {
2222 /* Update Transfer ISR function pointer */
2223 hi2c->XferISR = I2C_Master_ISR_IT;
2224
2225 /* Send Slave Address */
2226 /* Set NBYTES to read and generate START condition */
2227 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2228 I2C_GENERATE_START_READ);
2229
2230 /* Process Unlocked */
2231 __HAL_UNLOCK(hi2c);
2232
2233 /* Note : The I2C interrupts must be enabled after unlocking current process
2234 to avoid the risk of I2C interrupt handle execution before current
2235 process unlock */
2236 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2237 /* possible to enable all of these */
2238 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2239 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2240 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2241 }
2242
2243 return HAL_OK;
2244 }
2245 else
2246 {
2247 return HAL_BUSY;
2248 }
2249 }
2250
2251 /**
2252 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2253 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2254 * the configuration information for the specified I2C.
2255 * @param pData Pointer to data buffer
2256 * @param Size Amount of data to be sent
2257 * @retval HAL status
2258 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2259 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2260 {
2261 HAL_StatusTypeDef dmaxferstatus;
2262
2263 if (hi2c->State == HAL_I2C_STATE_READY)
2264 {
2265 if ((pData == NULL) || (Size == 0U))
2266 {
2267 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2268 return HAL_ERROR;
2269 }
2270 /* Process Locked */
2271 __HAL_LOCK(hi2c);
2272
2273 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2274 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2275 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2276
2277 /* Prepare transfer parameters */
2278 hi2c->pBuffPtr = pData;
2279 hi2c->XferCount = Size;
2280 hi2c->XferSize = hi2c->XferCount;
2281 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2282 hi2c->XferISR = I2C_Slave_ISR_DMA;
2283
2284 /* Preload TX data if no stretch enable */
2285 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2286 {
2287 /* Preload TX register */
2288 /* Write data to TXDR */
2289 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2290
2291 /* Increment Buffer pointer */
2292 hi2c->pBuffPtr++;
2293
2294 hi2c->XferCount--;
2295 hi2c->XferSize--;
2296 }
2297
2298 if (hi2c->XferCount != 0U)
2299 {
2300 if (hi2c->hdmatx != NULL)
2301 {
2302 /* Set the I2C DMA transfer complete callback */
2303 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2304
2305 /* Set the DMA error callback */
2306 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2307
2308 /* Set the unused DMA callbacks to NULL */
2309 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2310 hi2c->hdmatx->XferAbortCallback = NULL;
2311
2312 /* Enable the DMA channel */
2313 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2314 {
2315 if (hi2c->hdmatx->LinkedListQueue != NULL)
2316 {
2317 /* Set DMA data size */
2318 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2319
2320 /* Set DMA source address */
2321 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
2322
2323 /* Set DMA destination address */
2324 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
2325 = (uint32_t)&hi2c->Instance->TXDR;
2326
2327 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
2328 }
2329 else
2330 {
2331 /* Update I2C state */
2332 hi2c->State = HAL_I2C_STATE_LISTEN;
2333 hi2c->Mode = HAL_I2C_MODE_NONE;
2334
2335 /* Update I2C error code */
2336 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2337
2338 /* Process Unlocked */
2339 __HAL_UNLOCK(hi2c);
2340
2341 return HAL_ERROR;
2342 }
2343 }
2344 else
2345 {
2346 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2347 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2348 hi2c->XferSize);
2349 }
2350 }
2351 else
2352 {
2353 /* Update I2C state */
2354 hi2c->State = HAL_I2C_STATE_LISTEN;
2355 hi2c->Mode = HAL_I2C_MODE_NONE;
2356
2357 /* Update I2C error code */
2358 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2359
2360 /* Process Unlocked */
2361 __HAL_UNLOCK(hi2c);
2362
2363 return HAL_ERROR;
2364 }
2365
2366 if (dmaxferstatus == HAL_OK)
2367 {
2368 /* Enable Address Acknowledge */
2369 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2370
2371 /* Process Unlocked */
2372 __HAL_UNLOCK(hi2c);
2373
2374 /* Note : The I2C interrupts must be enabled after unlocking current process
2375 to avoid the risk of I2C interrupt handle execution before current
2376 process unlock */
2377 /* Enable ERR, STOP, NACK, ADDR interrupts */
2378 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2379
2380 /* Enable DMA Request */
2381 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2382 }
2383 else
2384 {
2385 /* Update I2C state */
2386 hi2c->State = HAL_I2C_STATE_LISTEN;
2387 hi2c->Mode = HAL_I2C_MODE_NONE;
2388
2389 /* Update I2C error code */
2390 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2391
2392 /* Process Unlocked */
2393 __HAL_UNLOCK(hi2c);
2394
2395 return HAL_ERROR;
2396 }
2397 }
2398 else
2399 {
2400 /* Enable Address Acknowledge */
2401 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2402
2403 /* Process Unlocked */
2404 __HAL_UNLOCK(hi2c);
2405
2406 /* Note : The I2C interrupts must be enabled after unlocking current process
2407 to avoid the risk of I2C interrupt handle execution before current
2408 process unlock */
2409 /* Enable ERR, STOP, NACK, ADDR interrupts */
2410 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2411 }
2412
2413 return HAL_OK;
2414 }
2415 else
2416 {
2417 return HAL_BUSY;
2418 }
2419 }
2420
2421 /**
2422 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2423 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2424 * the configuration information for the specified I2C.
2425 * @param pData Pointer to data buffer
2426 * @param Size Amount of data to be sent
2427 * @retval HAL status
2428 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2429 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2430 {
2431 HAL_StatusTypeDef dmaxferstatus;
2432
2433 if (hi2c->State == HAL_I2C_STATE_READY)
2434 {
2435 if ((pData == NULL) || (Size == 0U))
2436 {
2437 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2438 return HAL_ERROR;
2439 }
2440 /* Process Locked */
2441 __HAL_LOCK(hi2c);
2442
2443 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2444 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2445 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2446
2447 /* Prepare transfer parameters */
2448 hi2c->pBuffPtr = pData;
2449 hi2c->XferCount = Size;
2450 hi2c->XferSize = hi2c->XferCount;
2451 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2452 hi2c->XferISR = I2C_Slave_ISR_DMA;
2453
2454 if (hi2c->hdmarx != NULL)
2455 {
2456 /* Set the I2C DMA transfer complete callback */
2457 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2458
2459 /* Set the DMA error callback */
2460 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2461
2462 /* Set the unused DMA callbacks to NULL */
2463 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2464 hi2c->hdmarx->XferAbortCallback = NULL;
2465
2466 /* Enable the DMA channel */
2467 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2468 {
2469 if (hi2c->hdmarx->LinkedListQueue != NULL)
2470 {
2471 /* Set DMA data size */
2472 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2473
2474 /* Set DMA source address */
2475 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2476 = (uint32_t)&hi2c->Instance->RXDR;
2477
2478 /* Set DMA destination address */
2479 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2480
2481 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2482 }
2483 else
2484 {
2485 /* Update I2C state */
2486 hi2c->State = HAL_I2C_STATE_LISTEN;
2487 hi2c->Mode = HAL_I2C_MODE_NONE;
2488
2489 /* Update I2C error code */
2490 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2491
2492 /* Process Unlocked */
2493 __HAL_UNLOCK(hi2c);
2494
2495 return HAL_ERROR;
2496 }
2497 }
2498 else
2499 {
2500 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2501 hi2c->XferSize);
2502 }
2503 }
2504 else
2505 {
2506 /* Update I2C state */
2507 hi2c->State = HAL_I2C_STATE_LISTEN;
2508 hi2c->Mode = HAL_I2C_MODE_NONE;
2509
2510 /* Update I2C error code */
2511 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2512
2513 /* Process Unlocked */
2514 __HAL_UNLOCK(hi2c);
2515
2516 return HAL_ERROR;
2517 }
2518
2519 if (dmaxferstatus == HAL_OK)
2520 {
2521 /* Enable Address Acknowledge */
2522 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2523
2524 /* Process Unlocked */
2525 __HAL_UNLOCK(hi2c);
2526
2527 /* Note : The I2C interrupts must be enabled after unlocking current process
2528 to avoid the risk of I2C interrupt handle execution before current
2529 process unlock */
2530 /* Enable ERR, STOP, NACK, ADDR interrupts */
2531 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2532
2533 /* Enable DMA Request */
2534 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2535 }
2536 else
2537 {
2538 /* Update I2C state */
2539 hi2c->State = HAL_I2C_STATE_LISTEN;
2540 hi2c->Mode = HAL_I2C_MODE_NONE;
2541
2542 /* Update I2C error code */
2543 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2544
2545 /* Process Unlocked */
2546 __HAL_UNLOCK(hi2c);
2547
2548 return HAL_ERROR;
2549 }
2550
2551 return HAL_OK;
2552 }
2553 else
2554 {
2555 return HAL_BUSY;
2556 }
2557 }
2558 #endif /* HAL_DMA_MODULE_ENABLED */
2559
2560 /**
2561 * @brief Write an amount of data in blocking mode to a specific memory address
2562 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2563 * the configuration information for the specified I2C.
2564 * @param DevAddress Target device address: The device 7 bits address value
2565 * in datasheet must be shifted to the left before calling the interface
2566 * @param MemAddress Internal memory address
2567 * @param MemAddSize Size of internal memory address
2568 * @param pData Pointer to data buffer
2569 * @param Size Amount of data to be sent
2570 * @param Timeout Timeout duration
2571 * @retval HAL status
2572 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2573 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2574 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2575 {
2576 uint32_t tickstart;
2577
2578 /* Check the parameters */
2579 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2580
2581 if (hi2c->State == HAL_I2C_STATE_READY)
2582 {
2583 if ((pData == NULL) || (Size == 0U))
2584 {
2585 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2586 return HAL_ERROR;
2587 }
2588
2589 /* Process Locked */
2590 __HAL_LOCK(hi2c);
2591
2592 /* Init tickstart for timeout management*/
2593 tickstart = HAL_GetTick();
2594
2595 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2596 {
2597 return HAL_ERROR;
2598 }
2599
2600 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2601 hi2c->Mode = HAL_I2C_MODE_MEM;
2602 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2603
2604 /* Prepare transfer parameters */
2605 hi2c->pBuffPtr = pData;
2606 hi2c->XferCount = Size;
2607 hi2c->XferISR = NULL;
2608
2609 /* Send Slave Address and Memory Address */
2610 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2611 {
2612 /* Process Unlocked */
2613 __HAL_UNLOCK(hi2c);
2614 return HAL_ERROR;
2615 }
2616
2617 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2618 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2619 {
2620 hi2c->XferSize = MAX_NBYTE_SIZE;
2621 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2622 }
2623 else
2624 {
2625 hi2c->XferSize = hi2c->XferCount;
2626 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2627 }
2628
2629 do
2630 {
2631 /* Wait until TXIS flag is set */
2632 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2633 {
2634 return HAL_ERROR;
2635 }
2636
2637 /* Write data to TXDR */
2638 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2639
2640 /* Increment Buffer pointer */
2641 hi2c->pBuffPtr++;
2642
2643 hi2c->XferCount--;
2644 hi2c->XferSize--;
2645
2646 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2647 {
2648 /* Wait until TCR flag is set */
2649 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2650 {
2651 return HAL_ERROR;
2652 }
2653
2654 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2655 {
2656 hi2c->XferSize = MAX_NBYTE_SIZE;
2657 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2658 I2C_NO_STARTSTOP);
2659 }
2660 else
2661 {
2662 hi2c->XferSize = hi2c->XferCount;
2663 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2664 I2C_NO_STARTSTOP);
2665 }
2666 }
2667
2668 } while (hi2c->XferCount > 0U);
2669
2670 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2671 /* Wait until STOPF flag is reset */
2672 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2673 {
2674 return HAL_ERROR;
2675 }
2676
2677 /* Clear STOP Flag */
2678 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2679
2680 /* Clear Configuration Register 2 */
2681 I2C_RESET_CR2(hi2c);
2682
2683 hi2c->State = HAL_I2C_STATE_READY;
2684 hi2c->Mode = HAL_I2C_MODE_NONE;
2685
2686 /* Process Unlocked */
2687 __HAL_UNLOCK(hi2c);
2688
2689 return HAL_OK;
2690 }
2691 else
2692 {
2693 return HAL_BUSY;
2694 }
2695 }
2696
2697 /**
2698 * @brief Read an amount of data in blocking mode from a specific memory address
2699 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2700 * the configuration information for the specified I2C.
2701 * @param DevAddress Target device address: The device 7 bits address value
2702 * in datasheet must be shifted to the left before calling the interface
2703 * @param MemAddress Internal memory address
2704 * @param MemAddSize Size of internal memory address
2705 * @param pData Pointer to data buffer
2706 * @param Size Amount of data to be sent
2707 * @param Timeout Timeout duration
2708 * @retval HAL status
2709 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2710 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2711 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2712 {
2713 uint32_t tickstart;
2714
2715 /* Check the parameters */
2716 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2717
2718 if (hi2c->State == HAL_I2C_STATE_READY)
2719 {
2720 if ((pData == NULL) || (Size == 0U))
2721 {
2722 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2723 return HAL_ERROR;
2724 }
2725
2726 /* Process Locked */
2727 __HAL_LOCK(hi2c);
2728
2729 /* Init tickstart for timeout management*/
2730 tickstart = HAL_GetTick();
2731
2732 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2733 {
2734 return HAL_ERROR;
2735 }
2736
2737 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2738 hi2c->Mode = HAL_I2C_MODE_MEM;
2739 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2740
2741 /* Prepare transfer parameters */
2742 hi2c->pBuffPtr = pData;
2743 hi2c->XferCount = Size;
2744 hi2c->XferISR = NULL;
2745
2746 /* Send Slave Address and Memory Address */
2747 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2748 {
2749 /* Process Unlocked */
2750 __HAL_UNLOCK(hi2c);
2751 return HAL_ERROR;
2752 }
2753
2754 /* Send Slave Address */
2755 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2756 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2757 {
2758 hi2c->XferSize = MAX_NBYTE_SIZE;
2759 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2760 I2C_GENERATE_START_READ);
2761 }
2762 else
2763 {
2764 hi2c->XferSize = hi2c->XferCount;
2765 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2766 I2C_GENERATE_START_READ);
2767 }
2768
2769 do
2770 {
2771 /* Wait until RXNE flag is set */
2772 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2773 {
2774 return HAL_ERROR;
2775 }
2776
2777 /* Read data from RXDR */
2778 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2779
2780 /* Increment Buffer pointer */
2781 hi2c->pBuffPtr++;
2782
2783 hi2c->XferSize--;
2784 hi2c->XferCount--;
2785
2786 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2787 {
2788 /* Wait until TCR flag is set */
2789 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2790 {
2791 return HAL_ERROR;
2792 }
2793
2794 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2795 {
2796 hi2c->XferSize = MAX_NBYTE_SIZE;
2797 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2798 I2C_NO_STARTSTOP);
2799 }
2800 else
2801 {
2802 hi2c->XferSize = hi2c->XferCount;
2803 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2804 I2C_NO_STARTSTOP);
2805 }
2806 }
2807 } while (hi2c->XferCount > 0U);
2808
2809 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2810 /* Wait until STOPF flag is reset */
2811 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2812 {
2813 return HAL_ERROR;
2814 }
2815
2816 /* Clear STOP Flag */
2817 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2818
2819 /* Clear Configuration Register 2 */
2820 I2C_RESET_CR2(hi2c);
2821
2822 hi2c->State = HAL_I2C_STATE_READY;
2823 hi2c->Mode = HAL_I2C_MODE_NONE;
2824
2825 /* Process Unlocked */
2826 __HAL_UNLOCK(hi2c);
2827
2828 return HAL_OK;
2829 }
2830 else
2831 {
2832 return HAL_BUSY;
2833 }
2834 }
2835 /**
2836 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2837 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2838 * the configuration information for the specified I2C.
2839 * @param DevAddress Target device address: The device 7 bits address value
2840 * in datasheet must be shifted to the left before calling the interface
2841 * @param MemAddress Internal memory address
2842 * @param MemAddSize Size of internal memory address
2843 * @param pData Pointer to data buffer
2844 * @param Size Amount of data to be sent
2845 * @retval HAL status
2846 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2847 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2848 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2849 {
2850 /* Check the parameters */
2851 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2852
2853 if (hi2c->State == HAL_I2C_STATE_READY)
2854 {
2855 if ((pData == NULL) || (Size == 0U))
2856 {
2857 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2858 return HAL_ERROR;
2859 }
2860
2861 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2862 {
2863 return HAL_BUSY;
2864 }
2865
2866 /* Process Locked */
2867 __HAL_LOCK(hi2c);
2868
2869 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2870 hi2c->Mode = HAL_I2C_MODE_MEM;
2871 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2872
2873 /* Prepare transfer parameters */
2874 hi2c->XferSize = 0U;
2875 hi2c->pBuffPtr = pData;
2876 hi2c->XferCount = Size;
2877 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2878 hi2c->XferISR = I2C_Mem_ISR_IT;
2879 hi2c->Devaddress = DevAddress;
2880
2881 /* If Memory address size is 8Bit */
2882 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2883 {
2884 /* Prefetch Memory Address */
2885 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2886
2887 /* Reset Memaddress content */
2888 hi2c->Memaddress = 0xFFFFFFFFU;
2889 }
2890 /* If Memory address size is 16Bit */
2891 else
2892 {
2893 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2894 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2895
2896 /* Prepare Memaddress buffer for LSB part */
2897 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2898 }
2899 /* Send Slave Address and Memory Address */
2900 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2901
2902 /* Process Unlocked */
2903 __HAL_UNLOCK(hi2c);
2904
2905 /* Note : The I2C interrupts must be enabled after unlocking current process
2906 to avoid the risk of I2C interrupt handle execution before current
2907 process unlock */
2908
2909 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2910 /* possible to enable all of these */
2911 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2912 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2913 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2914
2915 return HAL_OK;
2916 }
2917 else
2918 {
2919 return HAL_BUSY;
2920 }
2921 }
2922
2923 /**
2924 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2925 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2926 * the configuration information for the specified I2C.
2927 * @param DevAddress Target device address: The device 7 bits address value
2928 * in datasheet must be shifted to the left before calling the interface
2929 * @param MemAddress Internal memory address
2930 * @param MemAddSize Size of internal memory address
2931 * @param pData Pointer to data buffer
2932 * @param Size Amount of data to be sent
2933 * @retval HAL status
2934 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2935 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2936 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2937 {
2938 /* Check the parameters */
2939 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2940
2941 if (hi2c->State == HAL_I2C_STATE_READY)
2942 {
2943 if ((pData == NULL) || (Size == 0U))
2944 {
2945 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2946 return HAL_ERROR;
2947 }
2948
2949 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2950 {
2951 return HAL_BUSY;
2952 }
2953
2954 /* Process Locked */
2955 __HAL_LOCK(hi2c);
2956
2957 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2958 hi2c->Mode = HAL_I2C_MODE_MEM;
2959 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2960
2961 /* Prepare transfer parameters */
2962 hi2c->pBuffPtr = pData;
2963 hi2c->XferCount = Size;
2964 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2965 hi2c->XferISR = I2C_Mem_ISR_IT;
2966 hi2c->Devaddress = DevAddress;
2967
2968 /* If Memory address size is 8Bit */
2969 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2970 {
2971 /* Prefetch Memory Address */
2972 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2973
2974 /* Reset Memaddress content */
2975 hi2c->Memaddress = 0xFFFFFFFFU;
2976 }
2977 /* If Memory address size is 16Bit */
2978 else
2979 {
2980 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2981 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2982
2983 /* Prepare Memaddress buffer for LSB part */
2984 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2985 }
2986 /* Send Slave Address and Memory Address */
2987 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
2988
2989 /* Process Unlocked */
2990 __HAL_UNLOCK(hi2c);
2991
2992 /* Note : The I2C interrupts must be enabled after unlocking current process
2993 to avoid the risk of I2C interrupt handle execution before current
2994 process unlock */
2995
2996 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2997 /* possible to enable all of these */
2998 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2999 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3000 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3001
3002 return HAL_OK;
3003 }
3004 else
3005 {
3006 return HAL_BUSY;
3007 }
3008 }
3009
3010 #if defined(HAL_DMA_MODULE_ENABLED)
3011 /**
3012 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3013 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3014 * the configuration information for the specified I2C.
3015 * @param DevAddress Target device address: The device 7 bits address value
3016 * in datasheet must be shifted to the left before calling the interface
3017 * @param MemAddress Internal memory address
3018 * @param MemAddSize Size of internal memory address
3019 * @param pData Pointer to data buffer
3020 * @param Size Amount of data to be sent
3021 * @retval HAL status
3022 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3023 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3024 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3025 {
3026 HAL_StatusTypeDef dmaxferstatus;
3027
3028 /* Check the parameters */
3029 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3030
3031 if (hi2c->State == HAL_I2C_STATE_READY)
3032 {
3033 if ((pData == NULL) || (Size == 0U))
3034 {
3035 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3036 return HAL_ERROR;
3037 }
3038
3039 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3040 {
3041 return HAL_BUSY;
3042 }
3043
3044 /* Process Locked */
3045 __HAL_LOCK(hi2c);
3046
3047 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3048 hi2c->Mode = HAL_I2C_MODE_MEM;
3049 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3050
3051 /* Prepare transfer parameters */
3052 hi2c->pBuffPtr = pData;
3053 hi2c->XferCount = Size;
3054 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3055 hi2c->XferISR = I2C_Mem_ISR_DMA;
3056 hi2c->Devaddress = DevAddress;
3057
3058 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3059 {
3060 hi2c->XferSize = MAX_NBYTE_SIZE;
3061 }
3062 else
3063 {
3064 hi2c->XferSize = hi2c->XferCount;
3065 }
3066
3067 /* If Memory address size is 8Bit */
3068 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3069 {
3070 /* Prefetch Memory Address */
3071 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3072
3073 /* Reset Memaddress content */
3074 hi2c->Memaddress = 0xFFFFFFFFU;
3075 }
3076 /* If Memory address size is 16Bit */
3077 else
3078 {
3079 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3080 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3081
3082 /* Prepare Memaddress buffer for LSB part */
3083 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3084 }
3085
3086 if (hi2c->hdmatx != NULL)
3087 {
3088 /* Set the I2C DMA transfer complete callback */
3089 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3090
3091 /* Set the DMA error callback */
3092 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3093
3094 /* Set the unused DMA callbacks to NULL */
3095 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3096 hi2c->hdmatx->XferAbortCallback = NULL;
3097
3098 /* Enable the DMA channel */
3099 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3100 {
3101 if (hi2c->hdmatx->LinkedListQueue != NULL)
3102 {
3103 /* Set DMA data size */
3104 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3105
3106 /* Set DMA source address */
3107 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3108
3109 /* Set DMA destination address */
3110 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3111 = (uint32_t)&hi2c->Instance->TXDR;
3112
3113 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3114 }
3115 else
3116 {
3117 /* Update I2C state */
3118 hi2c->State = HAL_I2C_STATE_READY;
3119 hi2c->Mode = HAL_I2C_MODE_NONE;
3120
3121 /* Update I2C error code */
3122 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3123
3124 /* Process Unlocked */
3125 __HAL_UNLOCK(hi2c);
3126
3127 return HAL_ERROR;
3128 }
3129 }
3130 else
3131 {
3132 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3133 hi2c->XferSize);
3134 }
3135 }
3136 else
3137 {
3138 /* Update I2C state */
3139 hi2c->State = HAL_I2C_STATE_READY;
3140 hi2c->Mode = HAL_I2C_MODE_NONE;
3141
3142 /* Update I2C error code */
3143 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3144
3145 /* Process Unlocked */
3146 __HAL_UNLOCK(hi2c);
3147
3148 return HAL_ERROR;
3149 }
3150
3151 if (dmaxferstatus == HAL_OK)
3152 {
3153 /* Send Slave Address and Memory Address */
3154 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3155
3156 /* Process Unlocked */
3157 __HAL_UNLOCK(hi2c);
3158
3159 /* Note : The I2C interrupts must be enabled after unlocking current process
3160 to avoid the risk of I2C interrupt handle execution before current
3161 process unlock */
3162 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3163 /* possible to enable all of these */
3164 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3165 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3166 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3167 }
3168 else
3169 {
3170 /* Update I2C state */
3171 hi2c->State = HAL_I2C_STATE_READY;
3172 hi2c->Mode = HAL_I2C_MODE_NONE;
3173
3174 /* Update I2C error code */
3175 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3176
3177 /* Process Unlocked */
3178 __HAL_UNLOCK(hi2c);
3179
3180 return HAL_ERROR;
3181 }
3182
3183 return HAL_OK;
3184 }
3185 else
3186 {
3187 return HAL_BUSY;
3188 }
3189 }
3190
3191 /**
3192 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3193 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3194 * the configuration information for the specified I2C.
3195 * @param DevAddress Target device address: The device 7 bits address value
3196 * in datasheet must be shifted to the left before calling the interface
3197 * @param MemAddress Internal memory address
3198 * @param MemAddSize Size of internal memory address
3199 * @param pData Pointer to data buffer
3200 * @param Size Amount of data to be read
3201 * @retval HAL status
3202 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3203 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3204 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3205 {
3206 HAL_StatusTypeDef dmaxferstatus;
3207
3208 /* Check the parameters */
3209 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3210
3211 if (hi2c->State == HAL_I2C_STATE_READY)
3212 {
3213 if ((pData == NULL) || (Size == 0U))
3214 {
3215 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3216 return HAL_ERROR;
3217 }
3218
3219 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3220 {
3221 return HAL_BUSY;
3222 }
3223
3224 /* Process Locked */
3225 __HAL_LOCK(hi2c);
3226
3227 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3228 hi2c->Mode = HAL_I2C_MODE_MEM;
3229 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3230
3231 /* Prepare transfer parameters */
3232 hi2c->pBuffPtr = pData;
3233 hi2c->XferCount = Size;
3234 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3235 hi2c->XferISR = I2C_Mem_ISR_DMA;
3236 hi2c->Devaddress = DevAddress;
3237
3238 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3239 {
3240 hi2c->XferSize = MAX_NBYTE_SIZE;
3241 }
3242 else
3243 {
3244 hi2c->XferSize = hi2c->XferCount;
3245 }
3246
3247 /* If Memory address size is 8Bit */
3248 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3249 {
3250 /* Prefetch Memory Address */
3251 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3252
3253 /* Reset Memaddress content */
3254 hi2c->Memaddress = 0xFFFFFFFFU;
3255 }
3256 /* If Memory address size is 16Bit */
3257 else
3258 {
3259 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3260 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3261
3262 /* Prepare Memaddress buffer for LSB part */
3263 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3264 }
3265
3266 if (hi2c->hdmarx != NULL)
3267 {
3268 /* Set the I2C DMA transfer complete callback */
3269 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3270
3271 /* Set the DMA error callback */
3272 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3273
3274 /* Set the unused DMA callbacks to NULL */
3275 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3276 hi2c->hdmarx->XferAbortCallback = NULL;
3277
3278 /* Enable the DMA channel */
3279 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3280 {
3281 if (hi2c->hdmarx->LinkedListQueue != NULL)
3282 {
3283 /* Set DMA data size */
3284 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3285
3286 /* Set DMA source address */
3287 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
3288 = (uint32_t)&hi2c->Instance->RXDR;
3289
3290 /* Set DMA destination address */
3291 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
3292
3293 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
3294 }
3295 else
3296 {
3297 /* Update I2C state */
3298 hi2c->State = HAL_I2C_STATE_READY;
3299 hi2c->Mode = HAL_I2C_MODE_NONE;
3300
3301 /* Update I2C error code */
3302 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3303
3304 /* Process Unlocked */
3305 __HAL_UNLOCK(hi2c);
3306
3307 return HAL_ERROR;
3308 }
3309 }
3310 else
3311 {
3312 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3313 hi2c->XferSize);
3314 }
3315 }
3316 else
3317 {
3318 /* Update I2C state */
3319 hi2c->State = HAL_I2C_STATE_READY;
3320 hi2c->Mode = HAL_I2C_MODE_NONE;
3321
3322 /* Update I2C error code */
3323 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3324
3325 /* Process Unlocked */
3326 __HAL_UNLOCK(hi2c);
3327
3328 return HAL_ERROR;
3329 }
3330
3331 if (dmaxferstatus == HAL_OK)
3332 {
3333 /* Send Slave Address and Memory Address */
3334 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3335
3336 /* Process Unlocked */
3337 __HAL_UNLOCK(hi2c);
3338
3339 /* Note : The I2C interrupts must be enabled after unlocking current process
3340 to avoid the risk of I2C interrupt handle execution before current
3341 process unlock */
3342 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3343 /* possible to enable all of these */
3344 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3345 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3346 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3347 }
3348 else
3349 {
3350 /* Update I2C state */
3351 hi2c->State = HAL_I2C_STATE_READY;
3352 hi2c->Mode = HAL_I2C_MODE_NONE;
3353
3354 /* Update I2C error code */
3355 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3356
3357 /* Process Unlocked */
3358 __HAL_UNLOCK(hi2c);
3359
3360 return HAL_ERROR;
3361 }
3362
3363 return HAL_OK;
3364 }
3365 else
3366 {
3367 return HAL_BUSY;
3368 }
3369 }
3370 #endif /* HAL_DMA_MODULE_ENABLED */
3371
3372 /**
3373 * @brief Checks if target device is ready for communication.
3374 * @note This function is used with Memory devices
3375 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3376 * the configuration information for the specified I2C.
3377 * @param DevAddress Target device address: The device 7 bits address value
3378 * in datasheet must be shifted to the left before calling the interface
3379 * @param Trials Number of trials
3380 * @param Timeout Timeout duration
3381 * @retval HAL status
3382 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3383 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3384 uint32_t Timeout)
3385 {
3386 uint32_t tickstart;
3387
3388 __IO uint32_t I2C_Trials = 0UL;
3389
3390 FlagStatus tmp1;
3391 FlagStatus tmp2;
3392
3393 if (hi2c->State == HAL_I2C_STATE_READY)
3394 {
3395 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3396 {
3397 return HAL_BUSY;
3398 }
3399
3400 /* Process Locked */
3401 __HAL_LOCK(hi2c);
3402
3403 hi2c->State = HAL_I2C_STATE_BUSY;
3404 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3405
3406 do
3407 {
3408 /* Generate Start */
3409 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3410
3411 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3412 /* Wait until STOPF flag is set or a NACK flag is set*/
3413 tickstart = HAL_GetTick();
3414
3415 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3416 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3417
3418 while ((tmp1 == RESET) && (tmp2 == RESET))
3419 {
3420 if (Timeout != HAL_MAX_DELAY)
3421 {
3422 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3423 {
3424 /* Update I2C state */
3425 hi2c->State = HAL_I2C_STATE_READY;
3426
3427 /* Update I2C error code */
3428 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3429
3430 /* Process Unlocked */
3431 __HAL_UNLOCK(hi2c);
3432
3433 return HAL_ERROR;
3434 }
3435 }
3436
3437 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3438 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3439 }
3440
3441 /* Check if the NACKF flag has not been set */
3442 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3443 {
3444 /* Wait until STOPF flag is reset */
3445 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3446 {
3447 return HAL_ERROR;
3448 }
3449
3450 /* Clear STOP Flag */
3451 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3452
3453 /* Device is ready */
3454 hi2c->State = HAL_I2C_STATE_READY;
3455
3456 /* Process Unlocked */
3457 __HAL_UNLOCK(hi2c);
3458
3459 return HAL_OK;
3460 }
3461 else
3462 {
3463 /* Wait until STOPF flag is reset */
3464 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3465 {
3466 return HAL_ERROR;
3467 }
3468
3469 /* Clear NACK Flag */
3470 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3471
3472 /* Clear STOP Flag, auto generated with autoend*/
3473 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3474 }
3475
3476 /* Increment Trials */
3477 I2C_Trials++;
3478 } while (I2C_Trials < Trials);
3479
3480 /* Update I2C state */
3481 hi2c->State = HAL_I2C_STATE_READY;
3482
3483 /* Update I2C error code */
3484 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3485
3486 /* Process Unlocked */
3487 __HAL_UNLOCK(hi2c);
3488
3489 return HAL_ERROR;
3490 }
3491 else
3492 {
3493 return HAL_BUSY;
3494 }
3495 }
3496
3497 /**
3498 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3499 * @note This interface allow to manage repeated start condition when a direction change during transfer
3500 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3501 * the configuration information for the specified I2C.
3502 * @param DevAddress Target device address: The device 7 bits address value
3503 * in datasheet must be shifted to the left before calling the interface
3504 * @param pData Pointer to data buffer
3505 * @param Size Amount of data to be sent
3506 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3507 * @retval HAL status
3508 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3509 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3510 uint16_t Size, uint32_t XferOptions)
3511 {
3512 uint32_t xfermode;
3513 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3514
3515 /* Check the parameters */
3516 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3517
3518 if (hi2c->State == HAL_I2C_STATE_READY)
3519 {
3520 /* Process Locked */
3521 __HAL_LOCK(hi2c);
3522
3523 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3524 hi2c->Mode = HAL_I2C_MODE_MASTER;
3525 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3526
3527 /* Prepare transfer parameters */
3528 hi2c->pBuffPtr = pData;
3529 hi2c->XferCount = Size;
3530 hi2c->XferOptions = XferOptions;
3531 hi2c->XferISR = I2C_Master_ISR_IT;
3532
3533 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3534 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3535 {
3536 hi2c->XferSize = MAX_NBYTE_SIZE;
3537 xfermode = I2C_RELOAD_MODE;
3538 }
3539 else
3540 {
3541 hi2c->XferSize = hi2c->XferCount;
3542 xfermode = hi2c->XferOptions;
3543 }
3544
3545 /* If transfer direction not change and there is no request to start another frame,
3546 do not generate Restart Condition */
3547 /* Mean Previous state is same as current state */
3548 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3549 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3550 {
3551 xferrequest = I2C_NO_STARTSTOP;
3552 }
3553 else
3554 {
3555 /* Convert OTHER_xxx XferOptions if any */
3556 I2C_ConvertOtherXferOptions(hi2c);
3557
3558 /* Update xfermode accordingly if no reload is necessary */
3559 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3560 {
3561 xfermode = hi2c->XferOptions;
3562 }
3563 }
3564
3565 /* Send Slave Address and set NBYTES to write */
3566 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3567
3568 /* Process Unlocked */
3569 __HAL_UNLOCK(hi2c);
3570
3571 /* Note : The I2C interrupts must be enabled after unlocking current process
3572 to avoid the risk of I2C interrupt handle execution before current
3573 process unlock */
3574 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3575 /* possible to enable all of these */
3576 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3577 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3578 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3579
3580 return HAL_OK;
3581 }
3582 else
3583 {
3584 return HAL_BUSY;
3585 }
3586 }
3587
3588 #if defined(HAL_DMA_MODULE_ENABLED)
3589 /**
3590 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3591 * @note This interface allow to manage repeated start condition when a direction change during transfer
3592 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3593 * the configuration information for the specified I2C.
3594 * @param DevAddress Target device address: The device 7 bits address value
3595 * in datasheet must be shifted to the left before calling the interface
3596 * @param pData Pointer to data buffer
3597 * @param Size Amount of data to be sent
3598 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3599 * @retval HAL status
3600 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3601 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3602 uint16_t Size, uint32_t XferOptions)
3603 {
3604 uint32_t xfermode;
3605 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3606 HAL_StatusTypeDef dmaxferstatus;
3607
3608 /* Check the parameters */
3609 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3610
3611 if (hi2c->State == HAL_I2C_STATE_READY)
3612 {
3613 /* Process Locked */
3614 __HAL_LOCK(hi2c);
3615
3616 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3617 hi2c->Mode = HAL_I2C_MODE_MASTER;
3618 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3619
3620 /* Prepare transfer parameters */
3621 hi2c->pBuffPtr = pData;
3622 hi2c->XferCount = Size;
3623 hi2c->XferOptions = XferOptions;
3624 hi2c->XferISR = I2C_Master_ISR_DMA;
3625
3626 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3627 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3628 {
3629 hi2c->XferSize = MAX_NBYTE_SIZE;
3630 xfermode = I2C_RELOAD_MODE;
3631 }
3632 else
3633 {
3634 hi2c->XferSize = hi2c->XferCount;
3635 xfermode = hi2c->XferOptions;
3636 }
3637
3638 /* If transfer direction not change and there is no request to start another frame,
3639 do not generate Restart Condition */
3640 /* Mean Previous state is same as current state */
3641 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3642 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3643 {
3644 xferrequest = I2C_NO_STARTSTOP;
3645 }
3646 else
3647 {
3648 /* Convert OTHER_xxx XferOptions if any */
3649 I2C_ConvertOtherXferOptions(hi2c);
3650
3651 /* Update xfermode accordingly if no reload is necessary */
3652 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3653 {
3654 xfermode = hi2c->XferOptions;
3655 }
3656 }
3657
3658 if (hi2c->XferSize > 0U)
3659 {
3660 if (hi2c->hdmatx != NULL)
3661 {
3662 /* Set the I2C DMA transfer complete callback */
3663 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3664
3665 /* Set the DMA error callback */
3666 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3667
3668 /* Set the unused DMA callbacks to NULL */
3669 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3670 hi2c->hdmatx->XferAbortCallback = NULL;
3671
3672 /* Enable the DMA channel */
3673 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3674 {
3675 if (hi2c->hdmatx->LinkedListQueue != NULL)
3676 {
3677 /* Set DMA data size */
3678 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3679
3680 /* Set DMA source address */
3681 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3682
3683 /* Set DMA destination address */
3684 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3685 = (uint32_t)&hi2c->Instance->TXDR;
3686
3687 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3688 }
3689 else
3690 {
3691 /* Update I2C state */
3692 hi2c->State = HAL_I2C_STATE_READY;
3693 hi2c->Mode = HAL_I2C_MODE_NONE;
3694
3695 /* Update I2C error code */
3696 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3697
3698 /* Process Unlocked */
3699 __HAL_UNLOCK(hi2c);
3700
3701 return HAL_ERROR;
3702 }
3703 }
3704 else
3705 {
3706 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3707 hi2c->XferSize);
3708 }
3709 }
3710 else
3711 {
3712 /* Update I2C state */
3713 hi2c->State = HAL_I2C_STATE_READY;
3714 hi2c->Mode = HAL_I2C_MODE_NONE;
3715
3716 /* Update I2C error code */
3717 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3718
3719 /* Process Unlocked */
3720 __HAL_UNLOCK(hi2c);
3721
3722 return HAL_ERROR;
3723 }
3724
3725 if (dmaxferstatus == HAL_OK)
3726 {
3727 /* Send Slave Address and set NBYTES to write */
3728 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3729
3730 /* Update XferCount value */
3731 hi2c->XferCount -= hi2c->XferSize;
3732
3733 /* Process Unlocked */
3734 __HAL_UNLOCK(hi2c);
3735
3736 /* Note : The I2C interrupts must be enabled after unlocking current process
3737 to avoid the risk of I2C interrupt handle execution before current
3738 process unlock */
3739 /* Enable ERR and NACK interrupts */
3740 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3741
3742 /* Enable DMA Request */
3743 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3744 }
3745 else
3746 {
3747 /* Update I2C state */
3748 hi2c->State = HAL_I2C_STATE_READY;
3749 hi2c->Mode = HAL_I2C_MODE_NONE;
3750
3751 /* Update I2C error code */
3752 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3753
3754 /* Process Unlocked */
3755 __HAL_UNLOCK(hi2c);
3756
3757 return HAL_ERROR;
3758 }
3759 }
3760 else
3761 {
3762 /* Update Transfer ISR function pointer */
3763 hi2c->XferISR = I2C_Master_ISR_IT;
3764
3765 /* Send Slave Address */
3766 /* Set NBYTES to write and generate START condition */
3767 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3768 I2C_GENERATE_START_WRITE);
3769
3770 /* Process Unlocked */
3771 __HAL_UNLOCK(hi2c);
3772
3773 /* Note : The I2C interrupts must be enabled after unlocking current process
3774 to avoid the risk of I2C interrupt handle execution before current
3775 process unlock */
3776 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3777 /* possible to enable all of these */
3778 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3779 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3780 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3781 }
3782
3783 return HAL_OK;
3784 }
3785 else
3786 {
3787 return HAL_BUSY;
3788 }
3789 }
3790 #endif /* HAL_DMA_MODULE_ENABLED */
3791
3792 /**
3793 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3794 * @note This interface allow to manage repeated start condition when a direction change during transfer
3795 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3796 * the configuration information for the specified I2C.
3797 * @param DevAddress Target device address: The device 7 bits address value
3798 * in datasheet must be shifted to the left before calling the interface
3799 * @param pData Pointer to data buffer
3800 * @param Size Amount of data to be sent
3801 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3802 * @retval HAL status
3803 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3804 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3805 uint16_t Size, uint32_t XferOptions)
3806 {
3807 uint32_t xfermode;
3808 uint32_t xferrequest = I2C_GENERATE_START_READ;
3809
3810 /* Check the parameters */
3811 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3812
3813 if (hi2c->State == HAL_I2C_STATE_READY)
3814 {
3815 /* Process Locked */
3816 __HAL_LOCK(hi2c);
3817
3818 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3819 hi2c->Mode = HAL_I2C_MODE_MASTER;
3820 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3821
3822 /* Prepare transfer parameters */
3823 hi2c->pBuffPtr = pData;
3824 hi2c->XferCount = Size;
3825 hi2c->XferOptions = XferOptions;
3826 hi2c->XferISR = I2C_Master_ISR_IT;
3827
3828 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3829 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3830 {
3831 hi2c->XferSize = MAX_NBYTE_SIZE;
3832 xfermode = I2C_RELOAD_MODE;
3833 }
3834 else
3835 {
3836 hi2c->XferSize = hi2c->XferCount;
3837 xfermode = hi2c->XferOptions;
3838 }
3839
3840 /* If transfer direction not change and there is no request to start another frame,
3841 do not generate Restart Condition */
3842 /* Mean Previous state is same as current state */
3843 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3844 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3845 {
3846 xferrequest = I2C_NO_STARTSTOP;
3847 }
3848 else
3849 {
3850 /* Convert OTHER_xxx XferOptions if any */
3851 I2C_ConvertOtherXferOptions(hi2c);
3852
3853 /* Update xfermode accordingly if no reload is necessary */
3854 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3855 {
3856 xfermode = hi2c->XferOptions;
3857 }
3858 }
3859
3860 /* Send Slave Address and set NBYTES to read */
3861 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3862
3863 /* Process Unlocked */
3864 __HAL_UNLOCK(hi2c);
3865
3866 /* Note : The I2C interrupts must be enabled after unlocking current process
3867 to avoid the risk of I2C interrupt handle execution before current
3868 process unlock */
3869 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3870
3871 return HAL_OK;
3872 }
3873 else
3874 {
3875 return HAL_BUSY;
3876 }
3877 }
3878
3879 #if defined(HAL_DMA_MODULE_ENABLED)
3880 /**
3881 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3882 * @note This interface allow to manage repeated start condition when a direction change during transfer
3883 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3884 * the configuration information for the specified I2C.
3885 * @param DevAddress Target device address: The device 7 bits address value
3886 * in datasheet must be shifted to the left before calling the interface
3887 * @param pData Pointer to data buffer
3888 * @param Size Amount of data to be sent
3889 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3890 * @retval HAL status
3891 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3892 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3893 uint16_t Size, uint32_t XferOptions)
3894 {
3895 uint32_t xfermode;
3896 uint32_t xferrequest = I2C_GENERATE_START_READ;
3897 HAL_StatusTypeDef dmaxferstatus;
3898
3899 /* Check the parameters */
3900 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3901
3902 if (hi2c->State == HAL_I2C_STATE_READY)
3903 {
3904 /* Process Locked */
3905 __HAL_LOCK(hi2c);
3906
3907 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3908 hi2c->Mode = HAL_I2C_MODE_MASTER;
3909 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3910
3911 /* Prepare transfer parameters */
3912 hi2c->pBuffPtr = pData;
3913 hi2c->XferCount = Size;
3914 hi2c->XferOptions = XferOptions;
3915 hi2c->XferISR = I2C_Master_ISR_DMA;
3916
3917 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3918 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3919 {
3920 hi2c->XferSize = MAX_NBYTE_SIZE;
3921 xfermode = I2C_RELOAD_MODE;
3922 }
3923 else
3924 {
3925 hi2c->XferSize = hi2c->XferCount;
3926 xfermode = hi2c->XferOptions;
3927 }
3928
3929 /* If transfer direction not change and there is no request to start another frame,
3930 do not generate Restart Condition */
3931 /* Mean Previous state is same as current state */
3932 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3933 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3934 {
3935 xferrequest = I2C_NO_STARTSTOP;
3936 }
3937 else
3938 {
3939 /* Convert OTHER_xxx XferOptions if any */
3940 I2C_ConvertOtherXferOptions(hi2c);
3941
3942 /* Update xfermode accordingly if no reload is necessary */
3943 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3944 {
3945 xfermode = hi2c->XferOptions;
3946 }
3947 }
3948
3949 if (hi2c->XferSize > 0U)
3950 {
3951 if (hi2c->hdmarx != NULL)
3952 {
3953 /* Set the I2C DMA transfer complete callback */
3954 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3955
3956 /* Set the DMA error callback */
3957 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3958
3959 /* Set the unused DMA callbacks to NULL */
3960 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3961 hi2c->hdmarx->XferAbortCallback = NULL;
3962
3963 /* Enable the DMA channel */
3964 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3965 {
3966 if (hi2c->hdmarx->LinkedListQueue != NULL)
3967 {
3968 /* Set DMA data size */
3969 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3970
3971 /* Set DMA source address */
3972 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
3973 = (uint32_t)&hi2c->Instance->RXDR;
3974
3975 /* Set DMA destination address */
3976 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
3977
3978 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
3979 }
3980 else
3981 {
3982 hi2c->State = HAL_I2C_STATE_READY;
3983 hi2c->Mode = HAL_I2C_MODE_NONE;
3984
3985 /* Update I2C error code */
3986 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3987
3988 /* Process Unlocked */
3989 __HAL_UNLOCK(hi2c);
3990
3991 return HAL_ERROR;
3992 }
3993 }
3994 else
3995 {
3996 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3997 hi2c->XferSize);
3998 }
3999 }
4000 else
4001 {
4002 /* Update I2C state */
4003 hi2c->State = HAL_I2C_STATE_READY;
4004 hi2c->Mode = HAL_I2C_MODE_NONE;
4005
4006 /* Update I2C error code */
4007 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4008
4009 /* Process Unlocked */
4010 __HAL_UNLOCK(hi2c);
4011
4012 return HAL_ERROR;
4013 }
4014
4015 if (dmaxferstatus == HAL_OK)
4016 {
4017 /* Send Slave Address and set NBYTES to read */
4018 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
4019
4020 /* Update XferCount value */
4021 hi2c->XferCount -= hi2c->XferSize;
4022
4023 /* Process Unlocked */
4024 __HAL_UNLOCK(hi2c);
4025
4026 /* Note : The I2C interrupts must be enabled after unlocking current process
4027 to avoid the risk of I2C interrupt handle execution before current
4028 process unlock */
4029 /* Enable ERR and NACK interrupts */
4030 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
4031
4032 /* Enable DMA Request */
4033 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4034 }
4035 else
4036 {
4037 /* Update I2C state */
4038 hi2c->State = HAL_I2C_STATE_READY;
4039 hi2c->Mode = HAL_I2C_MODE_NONE;
4040
4041 /* Update I2C error code */
4042 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4043
4044 /* Process Unlocked */
4045 __HAL_UNLOCK(hi2c);
4046
4047 return HAL_ERROR;
4048 }
4049 }
4050 else
4051 {
4052 /* Update Transfer ISR function pointer */
4053 hi2c->XferISR = I2C_Master_ISR_IT;
4054
4055 /* Send Slave Address */
4056 /* Set NBYTES to read and generate START condition */
4057 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
4058 I2C_GENERATE_START_READ);
4059
4060 /* Process Unlocked */
4061 __HAL_UNLOCK(hi2c);
4062
4063 /* Note : The I2C interrupts must be enabled after unlocking current process
4064 to avoid the risk of I2C interrupt handle execution before current
4065 process unlock */
4066 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
4067 /* possible to enable all of these */
4068 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
4069 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
4070 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
4071 }
4072
4073 return HAL_OK;
4074 }
4075 else
4076 {
4077 return HAL_BUSY;
4078 }
4079 }
4080 #endif /* HAL_DMA_MODULE_ENABLED */
4081
4082 /**
4083 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4084 * @note This interface allow to manage repeated start condition when a direction change during transfer
4085 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4086 * the configuration information for the specified I2C.
4087 * @param pData Pointer to data buffer
4088 * @param Size Amount of data to be sent
4089 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4090 * @retval HAL status
4091 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4092 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4093 uint32_t XferOptions)
4094 {
4095 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4096 FlagStatus tmp;
4097
4098 /* Check the parameters */
4099 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4100
4101 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4102 {
4103 if ((pData == NULL) || (Size == 0U))
4104 {
4105 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4106 return HAL_ERROR;
4107 }
4108
4109 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4110 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4111
4112 /* Process Locked */
4113 __HAL_LOCK(hi2c);
4114
4115 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4116 /* and then toggle the HAL slave RX state to TX state */
4117 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4118 {
4119 /* Disable associated Interrupts */
4120 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4121
4122 #if defined(HAL_DMA_MODULE_ENABLED)
4123 /* Abort DMA Xfer if any */
4124 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4125 {
4126 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4127
4128 if (hi2c->hdmarx != NULL)
4129 {
4130 /* Set the I2C DMA Abort callback :
4131 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4132 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4133
4134 /* Abort DMA RX */
4135 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4136 {
4137 /* Call Directly XferAbortCallback function in case of error */
4138 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4139 }
4140 }
4141 }
4142 #endif /* HAL_DMA_MODULE_ENABLED */
4143 }
4144
4145 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4146 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4147 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4148
4149 /* Enable Address Acknowledge */
4150 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4151
4152 /* Prepare transfer parameters */
4153 hi2c->pBuffPtr = pData;
4154 hi2c->XferCount = Size;
4155 hi2c->XferSize = hi2c->XferCount;
4156 hi2c->XferOptions = XferOptions;
4157 hi2c->XferISR = I2C_Slave_ISR_IT;
4158
4159 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4160 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4161 {
4162 /* Clear ADDR flag after prepare the transfer parameters */
4163 /* This action will generate an acknowledge to the Master */
4164 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4165 }
4166
4167 /* Process Unlocked */
4168 __HAL_UNLOCK(hi2c);
4169
4170 /* Note : The I2C interrupts must be enabled after unlocking current process
4171 to avoid the risk of I2C interrupt handle execution before current
4172 process unlock */
4173 /* REnable ADDR interrupt */
4174 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4175
4176 return HAL_OK;
4177 }
4178 else
4179 {
4180 return HAL_ERROR;
4181 }
4182 }
4183
4184 #if defined(HAL_DMA_MODULE_ENABLED)
4185 /**
4186 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4187 * @note This interface allow to manage repeated start condition when a direction change during transfer
4188 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4189 * the configuration information for the specified I2C.
4190 * @param pData Pointer to data buffer
4191 * @param Size Amount of data to be sent
4192 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4193 * @retval HAL status
4194 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4195 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4196 uint32_t XferOptions)
4197 {
4198 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4199 FlagStatus tmp;
4200 HAL_StatusTypeDef dmaxferstatus;
4201
4202 /* Check the parameters */
4203 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4204
4205 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4206 {
4207 if ((pData == NULL) || (Size == 0U))
4208 {
4209 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4210 return HAL_ERROR;
4211 }
4212
4213 /* Process Locked */
4214 __HAL_LOCK(hi2c);
4215
4216 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4217 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4218
4219 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4220 /* and then toggle the HAL slave RX state to TX state */
4221 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4222 {
4223 /* Disable associated Interrupts */
4224 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4225
4226 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4227 {
4228 /* Abort DMA Xfer if any */
4229 if (hi2c->hdmarx != NULL)
4230 {
4231 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4232
4233 /* Set the I2C DMA Abort callback :
4234 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4235 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4236
4237 /* Abort DMA RX */
4238 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4239 {
4240 /* Call Directly XferAbortCallback function in case of error */
4241 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4242 }
4243 }
4244 }
4245 }
4246 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4247 {
4248 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4249 {
4250 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4251
4252 /* Abort DMA Xfer if any */
4253 if (hi2c->hdmatx != NULL)
4254 {
4255 /* Set the I2C DMA Abort callback :
4256 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4257 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4258
4259 /* Abort DMA TX */
4260 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4261 {
4262 /* Call Directly XferAbortCallback function in case of error */
4263 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4264 }
4265 }
4266 }
4267 }
4268 else
4269 {
4270 /* Nothing to do */
4271 }
4272
4273 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4274 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4275 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4276
4277 /* Enable Address Acknowledge */
4278 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4279
4280 /* Prepare transfer parameters */
4281 hi2c->pBuffPtr = pData;
4282 hi2c->XferCount = Size;
4283 hi2c->XferSize = hi2c->XferCount;
4284 hi2c->XferOptions = XferOptions;
4285 hi2c->XferISR = I2C_Slave_ISR_DMA;
4286
4287 if (hi2c->hdmatx != NULL)
4288 {
4289 /* Set the I2C DMA transfer complete callback */
4290 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4291
4292 /* Set the DMA error callback */
4293 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4294
4295 /* Set the unused DMA callbacks to NULL */
4296 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4297 hi2c->hdmatx->XferAbortCallback = NULL;
4298
4299 /* Enable the DMA channel */
4300 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4301 {
4302 if (hi2c->hdmatx->LinkedListQueue != NULL)
4303 {
4304 /* Set DMA data size */
4305 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4306
4307 /* Set DMA source address */
4308 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
4309
4310 /* Set DMA destination address */
4311 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
4312 = (uint32_t)&hi2c->Instance->TXDR;
4313
4314 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
4315 }
4316 else
4317 {
4318 /* Update I2C state */
4319 hi2c->State = HAL_I2C_STATE_LISTEN;
4320 hi2c->Mode = HAL_I2C_MODE_NONE;
4321
4322 /* Update I2C error code */
4323 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4324
4325 /* Process Unlocked */
4326 __HAL_UNLOCK(hi2c);
4327
4328 return HAL_ERROR;
4329 }
4330 }
4331 else
4332 {
4333 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4334 hi2c->XferSize);
4335 }
4336 }
4337 else
4338 {
4339 /* Update I2C state */
4340 hi2c->State = HAL_I2C_STATE_LISTEN;
4341 hi2c->Mode = HAL_I2C_MODE_NONE;
4342
4343 /* Update I2C error code */
4344 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4345
4346 /* Process Unlocked */
4347 __HAL_UNLOCK(hi2c);
4348
4349 return HAL_ERROR;
4350 }
4351
4352 if (dmaxferstatus == HAL_OK)
4353 {
4354 /* Update XferCount value */
4355 hi2c->XferCount -= hi2c->XferSize;
4356
4357 /* Reset XferSize */
4358 hi2c->XferSize = 0;
4359 }
4360 else
4361 {
4362 /* Update I2C state */
4363 hi2c->State = HAL_I2C_STATE_LISTEN;
4364 hi2c->Mode = HAL_I2C_MODE_NONE;
4365
4366 /* Update I2C error code */
4367 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4368
4369 /* Process Unlocked */
4370 __HAL_UNLOCK(hi2c);
4371
4372 return HAL_ERROR;
4373 }
4374
4375 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4376 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4377 {
4378 /* Clear ADDR flag after prepare the transfer parameters */
4379 /* This action will generate an acknowledge to the Master */
4380 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4381 }
4382
4383 /* Process Unlocked */
4384 __HAL_UNLOCK(hi2c);
4385
4386 /* Enable DMA Request */
4387 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4388
4389 /* Note : The I2C interrupts must be enabled after unlocking current process
4390 to avoid the risk of I2C interrupt handle execution before current
4391 process unlock */
4392 /* Enable ERR, STOP, NACK, ADDR interrupts */
4393 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4394
4395 return HAL_OK;
4396 }
4397 else
4398 {
4399 return HAL_ERROR;
4400 }
4401 }
4402 #endif /* HAL_DMA_MODULE_ENABLED */
4403
4404 /**
4405 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4406 * @note This interface allow to manage repeated start condition when a direction change during transfer
4407 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4408 * the configuration information for the specified I2C.
4409 * @param pData Pointer to data buffer
4410 * @param Size Amount of data to be sent
4411 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4412 * @retval HAL status
4413 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4414 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4415 uint32_t XferOptions)
4416 {
4417 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4418 FlagStatus tmp;
4419
4420 /* Check the parameters */
4421 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4422
4423 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4424 {
4425 if ((pData == NULL) || (Size == 0U))
4426 {
4427 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4428 return HAL_ERROR;
4429 }
4430
4431 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4432 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4433
4434 /* Process Locked */
4435 __HAL_LOCK(hi2c);
4436
4437 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4438 /* and then toggle the HAL slave TX state to RX state */
4439 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4440 {
4441 /* Disable associated Interrupts */
4442 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4443
4444 #if defined(HAL_DMA_MODULE_ENABLED)
4445 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4446 {
4447 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4448
4449 /* Abort DMA Xfer if any */
4450 if (hi2c->hdmatx != NULL)
4451 {
4452 /* Set the I2C DMA Abort callback :
4453 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4454 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4455
4456 /* Abort DMA TX */
4457 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4458 {
4459 /* Call Directly XferAbortCallback function in case of error */
4460 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4461 }
4462 }
4463 }
4464 #endif /* HAL_DMA_MODULE_ENABLED */
4465 }
4466
4467 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4468 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4469 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4470
4471 /* Enable Address Acknowledge */
4472 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4473
4474 /* Prepare transfer parameters */
4475 hi2c->pBuffPtr = pData;
4476 hi2c->XferCount = Size;
4477 hi2c->XferSize = hi2c->XferCount;
4478 hi2c->XferOptions = XferOptions;
4479 hi2c->XferISR = I2C_Slave_ISR_IT;
4480
4481 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4482 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4483 {
4484 /* Clear ADDR flag after prepare the transfer parameters */
4485 /* This action will generate an acknowledge to the Master */
4486 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4487 }
4488
4489 /* Process Unlocked */
4490 __HAL_UNLOCK(hi2c);
4491
4492 /* Note : The I2C interrupts must be enabled after unlocking current process
4493 to avoid the risk of I2C interrupt handle execution before current
4494 process unlock */
4495 /* REnable ADDR interrupt */
4496 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4497
4498 return HAL_OK;
4499 }
4500 else
4501 {
4502 return HAL_ERROR;
4503 }
4504 }
4505
4506 #if defined(HAL_DMA_MODULE_ENABLED)
4507 /**
4508 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4509 * @note This interface allow to manage repeated start condition when a direction change during transfer
4510 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4511 * the configuration information for the specified I2C.
4512 * @param pData Pointer to data buffer
4513 * @param Size Amount of data to be sent
4514 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4515 * @retval HAL status
4516 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4517 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4518 uint32_t XferOptions)
4519 {
4520 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4521 FlagStatus tmp;
4522 HAL_StatusTypeDef dmaxferstatus;
4523
4524 /* Check the parameters */
4525 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4526
4527 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4528 {
4529 if ((pData == NULL) || (Size == 0U))
4530 {
4531 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4532 return HAL_ERROR;
4533 }
4534
4535 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4536 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4537
4538 /* Process Locked */
4539 __HAL_LOCK(hi2c);
4540
4541 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4542 /* and then toggle the HAL slave TX state to RX state */
4543 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4544 {
4545 /* Disable associated Interrupts */
4546 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4547
4548 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4549 {
4550 /* Abort DMA Xfer if any */
4551 if (hi2c->hdmatx != NULL)
4552 {
4553 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4554
4555 /* Set the I2C DMA Abort callback :
4556 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4557 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4558
4559 /* Abort DMA TX */
4560 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4561 {
4562 /* Call Directly XferAbortCallback function in case of error */
4563 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4564 }
4565 }
4566 }
4567 }
4568 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4569 {
4570 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4571 {
4572 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4573
4574 /* Abort DMA Xfer if any */
4575 if (hi2c->hdmarx != NULL)
4576 {
4577 /* Set the I2C DMA Abort callback :
4578 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4579 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4580
4581 /* Abort DMA RX */
4582 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4583 {
4584 /* Call Directly XferAbortCallback function in case of error */
4585 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4586 }
4587 }
4588 }
4589 }
4590 else
4591 {
4592 /* Nothing to do */
4593 }
4594
4595 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4596 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4597 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4598
4599 /* Enable Address Acknowledge */
4600 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4601
4602 /* Prepare transfer parameters */
4603 hi2c->pBuffPtr = pData;
4604 hi2c->XferCount = Size;
4605 hi2c->XferSize = hi2c->XferCount;
4606 hi2c->XferOptions = XferOptions;
4607 hi2c->XferISR = I2C_Slave_ISR_DMA;
4608
4609 if (hi2c->hdmarx != NULL)
4610 {
4611 /* Set the I2C DMA transfer complete callback */
4612 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4613
4614 /* Set the DMA error callback */
4615 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4616
4617 /* Set the unused DMA callbacks to NULL */
4618 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4619 hi2c->hdmarx->XferAbortCallback = NULL;
4620
4621 /* Enable the DMA channel */
4622 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4623 {
4624 if (hi2c->hdmarx->LinkedListQueue != NULL)
4625 {
4626 /* Set DMA data size */
4627 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4628
4629 /* Set DMA source address */
4630 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4631 = (uint32_t)&hi2c->Instance->RXDR;
4632
4633 /* Set DMA destination address */
4634 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4635
4636 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4637 }
4638 else
4639 {
4640 /* Update I2C state */
4641 hi2c->State = HAL_I2C_STATE_LISTEN;
4642 hi2c->Mode = HAL_I2C_MODE_NONE;
4643
4644 /* Update I2C error code */
4645 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4646
4647 /* Process Unlocked */
4648 __HAL_UNLOCK(hi2c);
4649
4650 return HAL_ERROR;
4651 }
4652 }
4653 else
4654 {
4655 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4656 hi2c->XferSize);
4657 }
4658 }
4659 else
4660 {
4661 /* Update I2C state */
4662 hi2c->State = HAL_I2C_STATE_LISTEN;
4663 hi2c->Mode = HAL_I2C_MODE_NONE;
4664
4665 /* Update I2C error code */
4666 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4667
4668 /* Process Unlocked */
4669 __HAL_UNLOCK(hi2c);
4670
4671 return HAL_ERROR;
4672 }
4673
4674 if (dmaxferstatus == HAL_OK)
4675 {
4676 /* Update XferCount value */
4677 hi2c->XferCount -= hi2c->XferSize;
4678
4679 /* Reset XferSize */
4680 hi2c->XferSize = 0;
4681 }
4682 else
4683 {
4684 /* Update I2C state */
4685 hi2c->State = HAL_I2C_STATE_LISTEN;
4686 hi2c->Mode = HAL_I2C_MODE_NONE;
4687
4688 /* Update I2C error code */
4689 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4690
4691 /* Process Unlocked */
4692 __HAL_UNLOCK(hi2c);
4693
4694 return HAL_ERROR;
4695 }
4696
4697 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4698 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4699 {
4700 /* Clear ADDR flag after prepare the transfer parameters */
4701 /* This action will generate an acknowledge to the Master */
4702 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4703 }
4704
4705 /* Process Unlocked */
4706 __HAL_UNLOCK(hi2c);
4707
4708 /* Enable DMA Request */
4709 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4710
4711 /* Note : The I2C interrupts must be enabled after unlocking current process
4712 to avoid the risk of I2C interrupt handle execution before current
4713 process unlock */
4714 /* REnable ADDR interrupt */
4715 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4716
4717 return HAL_OK;
4718 }
4719 else
4720 {
4721 return HAL_ERROR;
4722 }
4723 }
4724 #endif /* HAL_DMA_MODULE_ENABLED */
4725
4726 /**
4727 * @brief Enable the Address listen mode with Interrupt.
4728 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4729 * the configuration information for the specified I2C.
4730 * @retval HAL status
4731 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4732 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4733 {
4734 if (hi2c->State == HAL_I2C_STATE_READY)
4735 {
4736 hi2c->State = HAL_I2C_STATE_LISTEN;
4737 hi2c->XferISR = I2C_Slave_ISR_IT;
4738
4739 /* Enable the Address Match interrupt */
4740 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4741
4742 return HAL_OK;
4743 }
4744 else
4745 {
4746 return HAL_BUSY;
4747 }
4748 }
4749
4750 /**
4751 * @brief Disable the Address listen mode with Interrupt.
4752 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4753 * the configuration information for the specified I2C
4754 * @retval HAL status
4755 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4756 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4757 {
4758 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4759 uint32_t tmp;
4760
4761 /* Disable Address listen mode only if a transfer is not ongoing */
4762 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4763 {
4764 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4765 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4766 hi2c->State = HAL_I2C_STATE_READY;
4767 hi2c->Mode = HAL_I2C_MODE_NONE;
4768 hi2c->XferISR = NULL;
4769
4770 /* Disable the Address Match interrupt */
4771 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4772
4773 return HAL_OK;
4774 }
4775 else
4776 {
4777 return HAL_BUSY;
4778 }
4779 }
4780
4781 /**
4782 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4783 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4784 * the configuration information for the specified I2C.
4785 * @param DevAddress Target device address: The device 7 bits address value
4786 * in datasheet must be shifted to the left before calling the interface
4787 * @retval HAL status
4788 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4789 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4790 {
4791 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4792 {
4793 /* Process Locked */
4794 __HAL_LOCK(hi2c);
4795
4796 /* Disable Interrupts and Store Previous state */
4797 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4798 {
4799 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4800 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4801 }
4802 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4803 {
4804 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4805 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4806 }
4807 else
4808 {
4809 /* Do nothing */
4810 }
4811
4812 /* Set State at HAL_I2C_STATE_ABORT */
4813 hi2c->State = HAL_I2C_STATE_ABORT;
4814
4815 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4816 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4817 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4818
4819 /* Process Unlocked */
4820 __HAL_UNLOCK(hi2c);
4821
4822 /* Note : The I2C interrupts must be enabled after unlocking current process
4823 to avoid the risk of I2C interrupt handle execution before current
4824 process unlock */
4825 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4826
4827 return HAL_OK;
4828 }
4829 else
4830 {
4831 /* Wrong usage of abort function */
4832 /* This function should be used only in case of abort monitored by master device */
4833 return HAL_ERROR;
4834 }
4835 }
4836
4837 /**
4838 * @}
4839 */
4840
4841 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4842 * @{
4843 */
4844
4845 /**
4846 * @brief This function handles I2C event interrupt request.
4847 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4848 * the configuration information for the specified I2C.
4849 * @retval None
4850 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4851 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4852 {
4853 /* Get current IT Flags and IT sources value */
4854 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4855 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4856
4857 /* I2C events treatment -------------------------------------*/
4858 if (hi2c->XferISR != NULL)
4859 {
4860 hi2c->XferISR(hi2c, itflags, itsources);
4861 }
4862 }
4863
4864 /**
4865 * @brief This function handles I2C error interrupt request.
4866 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4867 * the configuration information for the specified I2C.
4868 * @retval None
4869 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4870 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4871 {
4872 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4873 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4874 uint32_t tmperror;
4875
4876 /* I2C Bus error interrupt occurred ------------------------------------*/
4877 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4878 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4879 {
4880 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4881
4882 /* Clear BERR flag */
4883 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4884 }
4885
4886 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4887 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4888 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4889 {
4890 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4891
4892 /* Clear OVR flag */
4893 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4894 }
4895
4896 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4897 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4898 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4899 {
4900 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4901
4902 /* Clear ARLO flag */
4903 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4904 }
4905
4906 /* Store current volatile hi2c->ErrorCode, misra rule */
4907 tmperror = hi2c->ErrorCode;
4908
4909 /* Call the Error Callback in case of Error detected */
4910 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4911 {
4912 I2C_ITError(hi2c, tmperror);
4913 }
4914 }
4915
4916 /**
4917 * @brief Master Tx Transfer completed callback.
4918 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4919 * the configuration information for the specified I2C.
4920 * @retval None
4921 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4922 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4923 {
4924 /* Prevent unused argument(s) compilation warning */
4925 UNUSED(hi2c);
4926
4927 /* NOTE : This function should not be modified, when the callback is needed,
4928 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4929 */
4930 }
4931
4932 /**
4933 * @brief Master Rx Transfer completed callback.
4934 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4935 * the configuration information for the specified I2C.
4936 * @retval None
4937 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4938 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4939 {
4940 /* Prevent unused argument(s) compilation warning */
4941 UNUSED(hi2c);
4942
4943 /* NOTE : This function should not be modified, when the callback is needed,
4944 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4945 */
4946 }
4947
4948 /** @brief Slave Tx Transfer completed callback.
4949 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4950 * the configuration information for the specified I2C.
4951 * @retval None
4952 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4953 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4954 {
4955 /* Prevent unused argument(s) compilation warning */
4956 UNUSED(hi2c);
4957
4958 /* NOTE : This function should not be modified, when the callback is needed,
4959 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4960 */
4961 }
4962
4963 /**
4964 * @brief Slave Rx Transfer completed callback.
4965 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4966 * the configuration information for the specified I2C.
4967 * @retval None
4968 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4969 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4970 {
4971 /* Prevent unused argument(s) compilation warning */
4972 UNUSED(hi2c);
4973
4974 /* NOTE : This function should not be modified, when the callback is needed,
4975 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4976 */
4977 }
4978
4979 /**
4980 * @brief Slave Address Match callback.
4981 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4982 * the configuration information for the specified I2C.
4983 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4984 * @param AddrMatchCode Address Match Code
4985 * @retval None
4986 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4987 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4988 {
4989 /* Prevent unused argument(s) compilation warning */
4990 UNUSED(hi2c);
4991 UNUSED(TransferDirection);
4992 UNUSED(AddrMatchCode);
4993
4994 /* NOTE : This function should not be modified, when the callback is needed,
4995 the HAL_I2C_AddrCallback() could be implemented in the user file
4996 */
4997 }
4998
4999 /**
5000 * @brief Listen Complete callback.
5001 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5002 * the configuration information for the specified I2C.
5003 * @retval None
5004 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5005 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5006 {
5007 /* Prevent unused argument(s) compilation warning */
5008 UNUSED(hi2c);
5009
5010 /* NOTE : This function should not be modified, when the callback is needed,
5011 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5012 */
5013 }
5014
5015 /**
5016 * @brief Memory Tx Transfer completed callback.
5017 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5018 * the configuration information for the specified I2C.
5019 * @retval None
5020 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5021 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5022 {
5023 /* Prevent unused argument(s) compilation warning */
5024 UNUSED(hi2c);
5025
5026 /* NOTE : This function should not be modified, when the callback is needed,
5027 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5028 */
5029 }
5030
5031 /**
5032 * @brief Memory Rx Transfer completed callback.
5033 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5034 * the configuration information for the specified I2C.
5035 * @retval None
5036 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5037 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5038 {
5039 /* Prevent unused argument(s) compilation warning */
5040 UNUSED(hi2c);
5041
5042 /* NOTE : This function should not be modified, when the callback is needed,
5043 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5044 */
5045 }
5046
5047 /**
5048 * @brief I2C error callback.
5049 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5050 * the configuration information for the specified I2C.
5051 * @retval None
5052 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5053 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5054 {
5055 /* Prevent unused argument(s) compilation warning */
5056 UNUSED(hi2c);
5057
5058 /* NOTE : This function should not be modified, when the callback is needed,
5059 the HAL_I2C_ErrorCallback could be implemented in the user file
5060 */
5061 }
5062
5063 /**
5064 * @brief I2C abort callback.
5065 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5066 * the configuration information for the specified I2C.
5067 * @retval None
5068 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5069 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5070 {
5071 /* Prevent unused argument(s) compilation warning */
5072 UNUSED(hi2c);
5073
5074 /* NOTE : This function should not be modified, when the callback is needed,
5075 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5076 */
5077 }
5078
5079 /**
5080 * @}
5081 */
5082
5083 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5084 * @brief Peripheral State, Mode and Error functions
5085 *
5086 @verbatim
5087 ===============================================================================
5088 ##### Peripheral State, Mode and Error functions #####
5089 ===============================================================================
5090 [..]
5091 This subsection permit to get in run-time the status of the peripheral
5092 and the data flow.
5093
5094 @endverbatim
5095 * @{
5096 */
5097
5098 /**
5099 * @brief Return the I2C handle state.
5100 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5101 * the configuration information for the specified I2C.
5102 * @retval HAL state
5103 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)5104 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5105 {
5106 /* Return I2C handle state */
5107 return hi2c->State;
5108 }
5109
5110 /**
5111 * @brief Returns the I2C Master, Slave, Memory or no mode.
5112 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5113 * the configuration information for I2C module
5114 * @retval HAL mode
5115 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)5116 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5117 {
5118 return hi2c->Mode;
5119 }
5120
5121 /**
5122 * @brief Return the I2C error code.
5123 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5124 * the configuration information for the specified I2C.
5125 * @retval I2C Error Code
5126 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)5127 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5128 {
5129 return hi2c->ErrorCode;
5130 }
5131
5132 /**
5133 * @}
5134 */
5135
5136 /**
5137 * @}
5138 */
5139
5140 /** @addtogroup I2C_Private_Functions
5141 * @{
5142 */
5143
5144 /**
5145 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
5146 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5147 * the configuration information for the specified I2C.
5148 * @param ITFlags Interrupt flags to handle.
5149 * @param ITSources Interrupt sources enabled.
5150 * @retval HAL status
5151 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5152 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5153 uint32_t ITSources)
5154 {
5155 uint16_t devaddress;
5156 uint32_t tmpITFlags = ITFlags;
5157
5158 /* Process Locked */
5159 __HAL_LOCK(hi2c);
5160
5161 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5162 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5163 {
5164 /* Clear NACK Flag */
5165 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5166
5167 /* Set corresponding Error Code */
5168 /* No need to generate STOP, it is automatically done */
5169 /* Error callback will be send during stop flag treatment */
5170 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5171
5172 /* Flush TX register */
5173 I2C_Flush_TXDR(hi2c);
5174 }
5175 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5176 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5177 {
5178 /* Remove RXNE flag on temporary variable as read done */
5179 tmpITFlags &= ~I2C_FLAG_RXNE;
5180
5181 /* Read data from RXDR */
5182 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5183
5184 /* Increment Buffer pointer */
5185 hi2c->pBuffPtr++;
5186
5187 hi2c->XferSize--;
5188 hi2c->XferCount--;
5189 }
5190 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5191 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5192 {
5193 /* Write data to TXDR */
5194 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5195
5196 /* Increment Buffer pointer */
5197 hi2c->pBuffPtr++;
5198
5199 hi2c->XferSize--;
5200 hi2c->XferCount--;
5201 }
5202 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5203 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5204 {
5205 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5206 {
5207 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5208
5209 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5210 {
5211 hi2c->XferSize = MAX_NBYTE_SIZE;
5212 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5213 }
5214 else
5215 {
5216 hi2c->XferSize = hi2c->XferCount;
5217 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5218 {
5219 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5220 hi2c->XferOptions, I2C_NO_STARTSTOP);
5221 }
5222 else
5223 {
5224 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5225 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5226 }
5227 }
5228 }
5229 else
5230 {
5231 /* Call TxCpltCallback() if no stop mode is set */
5232 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5233 {
5234 /* Call I2C Master Sequential complete process */
5235 I2C_ITMasterSeqCplt(hi2c);
5236 }
5237 else
5238 {
5239 /* Wrong size Status regarding TCR flag event */
5240 /* Call the corresponding callback to inform upper layer of End of Transfer */
5241 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5242 }
5243 }
5244 }
5245 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5246 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5247 {
5248 if (hi2c->XferCount == 0U)
5249 {
5250 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5251 {
5252 /* Generate a stop condition in case of no transfer option */
5253 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5254 {
5255 /* Generate Stop */
5256 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5257 }
5258 else
5259 {
5260 /* Call I2C Master Sequential complete process */
5261 I2C_ITMasterSeqCplt(hi2c);
5262 }
5263 }
5264 }
5265 else
5266 {
5267 /* Wrong size Status regarding TC flag event */
5268 /* Call the corresponding callback to inform upper layer of End of Transfer */
5269 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5270 }
5271 }
5272 else
5273 {
5274 /* Nothing to do */
5275 }
5276
5277 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5278 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5279 {
5280 /* Call I2C Master complete process */
5281 I2C_ITMasterCplt(hi2c, tmpITFlags);
5282 }
5283
5284 /* Process Unlocked */
5285 __HAL_UNLOCK(hi2c);
5286
5287 return HAL_OK;
5288 }
5289
5290 /**
5291 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
5292 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5293 * the configuration information for the specified I2C.
5294 * @param ITFlags Interrupt flags to handle.
5295 * @param ITSources Interrupt sources enabled.
5296 * @retval HAL status
5297 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5298 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5299 uint32_t ITSources)
5300 {
5301 uint32_t direction = I2C_GENERATE_START_WRITE;
5302 uint32_t tmpITFlags = ITFlags;
5303
5304 /* Process Locked */
5305 __HAL_LOCK(hi2c);
5306
5307 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5308 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5309 {
5310 /* Clear NACK Flag */
5311 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5312
5313 /* Set corresponding Error Code */
5314 /* No need to generate STOP, it is automatically done */
5315 /* Error callback will be send during stop flag treatment */
5316 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5317
5318 /* Flush TX register */
5319 I2C_Flush_TXDR(hi2c);
5320 }
5321 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5322 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5323 {
5324 /* Remove RXNE flag on temporary variable as read done */
5325 tmpITFlags &= ~I2C_FLAG_RXNE;
5326
5327 /* Read data from RXDR */
5328 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5329
5330 /* Increment Buffer pointer */
5331 hi2c->pBuffPtr++;
5332
5333 hi2c->XferSize--;
5334 hi2c->XferCount--;
5335 }
5336 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5337 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5338 {
5339 if (hi2c->Memaddress == 0xFFFFFFFFU)
5340 {
5341 /* Write data to TXDR */
5342 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5343
5344 /* Increment Buffer pointer */
5345 hi2c->pBuffPtr++;
5346
5347 hi2c->XferSize--;
5348 hi2c->XferCount--;
5349 }
5350 else
5351 {
5352 /* Write LSB part of Memory Address */
5353 hi2c->Instance->TXDR = hi2c->Memaddress;
5354
5355 /* Reset Memaddress content */
5356 hi2c->Memaddress = 0xFFFFFFFFU;
5357 }
5358 }
5359 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5360 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5361 {
5362 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5363 {
5364 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5365 {
5366 hi2c->XferSize = MAX_NBYTE_SIZE;
5367 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5368 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5369 }
5370 else
5371 {
5372 hi2c->XferSize = hi2c->XferCount;
5373 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5374 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5375 }
5376 }
5377 else
5378 {
5379 /* Wrong size Status regarding TCR flag event */
5380 /* Call the corresponding callback to inform upper layer of End of Transfer */
5381 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5382 }
5383 }
5384 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5385 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5386 {
5387 /* Disable Interrupt related to address step */
5388 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5389
5390 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
5391 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
5392
5393 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5394 {
5395 direction = I2C_GENERATE_START_READ;
5396 }
5397
5398 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5399 {
5400 hi2c->XferSize = MAX_NBYTE_SIZE;
5401
5402 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5403 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5404 I2C_RELOAD_MODE, direction);
5405 }
5406 else
5407 {
5408 hi2c->XferSize = hi2c->XferCount;
5409
5410 /* Set NBYTES to write and generate RESTART */
5411 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5412 I2C_AUTOEND_MODE, direction);
5413 }
5414 }
5415 else
5416 {
5417 /* Nothing to do */
5418 }
5419
5420 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5421 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5422 {
5423 /* Call I2C Master complete process */
5424 I2C_ITMasterCplt(hi2c, tmpITFlags);
5425 }
5426
5427 /* Process Unlocked */
5428 __HAL_UNLOCK(hi2c);
5429
5430 return HAL_OK;
5431 }
5432
5433 /**
5434 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5435 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5436 * the configuration information for the specified I2C.
5437 * @param ITFlags Interrupt flags to handle.
5438 * @param ITSources Interrupt sources enabled.
5439 * @retval HAL status
5440 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5441 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5442 uint32_t ITSources)
5443 {
5444 uint32_t tmpoptions = hi2c->XferOptions;
5445 uint32_t tmpITFlags = ITFlags;
5446
5447 /* Process locked */
5448 __HAL_LOCK(hi2c);
5449
5450 /* Check if STOPF is set */
5451 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5452 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5453 {
5454 /* Call I2C Slave complete process */
5455 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5456 }
5457
5458 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5459 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5460 {
5461 /* Check that I2C transfer finished */
5462 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5463 /* Mean XferCount == 0*/
5464 /* So clear Flag NACKF only */
5465 if (hi2c->XferCount == 0U)
5466 {
5467 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5468 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5469 Warning[Pa134]: left and right operands are identical */
5470 {
5471 /* Call I2C Listen complete process */
5472 I2C_ITListenCplt(hi2c, tmpITFlags);
5473 }
5474 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5475 {
5476 /* Clear NACK Flag */
5477 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5478
5479 /* Flush TX register */
5480 I2C_Flush_TXDR(hi2c);
5481
5482 /* Last Byte is Transmitted */
5483 /* Call I2C Slave Sequential complete process */
5484 I2C_ITSlaveSeqCplt(hi2c);
5485 }
5486 else
5487 {
5488 /* Clear NACK Flag */
5489 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5490 }
5491 }
5492 else
5493 {
5494 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5495 /* Clear NACK Flag */
5496 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5497
5498 /* Set ErrorCode corresponding to a Non-Acknowledge */
5499 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5500
5501 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5502 {
5503 /* Call the corresponding callback to inform upper layer of End of Transfer */
5504 I2C_ITError(hi2c, hi2c->ErrorCode);
5505 }
5506 }
5507 }
5508 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5509 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5510 {
5511 if (hi2c->XferCount > 0U)
5512 {
5513 /* Read data from RXDR */
5514 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5515
5516 /* Increment Buffer pointer */
5517 hi2c->pBuffPtr++;
5518
5519 hi2c->XferSize--;
5520 hi2c->XferCount--;
5521 }
5522
5523 if ((hi2c->XferCount == 0U) && \
5524 (tmpoptions != I2C_NO_OPTION_FRAME))
5525 {
5526 /* Call I2C Slave Sequential complete process */
5527 I2C_ITSlaveSeqCplt(hi2c);
5528 }
5529 }
5530 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5531 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5532 {
5533 I2C_ITAddrCplt(hi2c, tmpITFlags);
5534 }
5535 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5536 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5537 {
5538 /* Write data to TXDR only if XferCount not reach "0" */
5539 /* A TXIS flag can be set, during STOP treatment */
5540 /* Check if all Data have already been sent */
5541 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5542 if (hi2c->XferCount > 0U)
5543 {
5544 /* Write data to TXDR */
5545 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5546
5547 /* Increment Buffer pointer */
5548 hi2c->pBuffPtr++;
5549
5550 hi2c->XferCount--;
5551 hi2c->XferSize--;
5552 }
5553 else
5554 {
5555 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5556 {
5557 /* Last Byte is Transmitted */
5558 /* Call I2C Slave Sequential complete process */
5559 I2C_ITSlaveSeqCplt(hi2c);
5560 }
5561 }
5562 }
5563 else
5564 {
5565 /* Nothing to do */
5566 }
5567
5568 /* Process Unlocked */
5569 __HAL_UNLOCK(hi2c);
5570
5571 return HAL_OK;
5572 }
5573
5574 #if defined(HAL_DMA_MODULE_ENABLED)
5575 /**
5576 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5577 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5578 * the configuration information for the specified I2C.
5579 * @param ITFlags Interrupt flags to handle.
5580 * @param ITSources Interrupt sources enabled.
5581 * @retval HAL status
5582 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5583 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5584 uint32_t ITSources)
5585 {
5586 uint16_t devaddress;
5587 uint32_t xfermode;
5588
5589 /* Process Locked */
5590 __HAL_LOCK(hi2c);
5591
5592 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5593 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5594 {
5595 /* Clear NACK Flag */
5596 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5597
5598 /* Set corresponding Error Code */
5599 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5600
5601 /* No need to generate STOP, it is automatically done */
5602 /* But enable STOP interrupt, to treat it */
5603 /* Error callback will be send during stop flag treatment */
5604 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5605
5606 /* Flush TX register */
5607 I2C_Flush_TXDR(hi2c);
5608 }
5609 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5610 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5611 {
5612 /* Disable TC interrupt */
5613 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5614
5615 if (hi2c->XferCount != 0U)
5616 {
5617 /* Recover Slave address */
5618 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5619
5620 /* Prepare the new XferSize to transfer */
5621 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5622 {
5623 hi2c->XferSize = MAX_NBYTE_SIZE;
5624 xfermode = I2C_RELOAD_MODE;
5625 }
5626 else
5627 {
5628 hi2c->XferSize = hi2c->XferCount;
5629 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5630 {
5631 xfermode = hi2c->XferOptions;
5632 }
5633 else
5634 {
5635 xfermode = I2C_AUTOEND_MODE;
5636 }
5637 }
5638
5639 /* Set the new XferSize in Nbytes register */
5640 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5641
5642 /* Update XferCount value */
5643 hi2c->XferCount -= hi2c->XferSize;
5644
5645 /* Enable DMA Request */
5646 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5647 {
5648 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5649 }
5650 else
5651 {
5652 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5653 }
5654 }
5655 else
5656 {
5657 /* Call TxCpltCallback() if no stop mode is set */
5658 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5659 {
5660 /* Call I2C Master Sequential complete process */
5661 I2C_ITMasterSeqCplt(hi2c);
5662 }
5663 else
5664 {
5665 /* Wrong size Status regarding TCR flag event */
5666 /* Call the corresponding callback to inform upper layer of End of Transfer */
5667 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5668 }
5669 }
5670 }
5671 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5672 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5673 {
5674 if (hi2c->XferCount == 0U)
5675 {
5676 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5677 {
5678 /* Generate a stop condition in case of no transfer option */
5679 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5680 {
5681 /* Generate Stop */
5682 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5683 }
5684 else
5685 {
5686 /* Call I2C Master Sequential complete process */
5687 I2C_ITMasterSeqCplt(hi2c);
5688 }
5689 }
5690 }
5691 else
5692 {
5693 /* Wrong size Status regarding TC flag event */
5694 /* Call the corresponding callback to inform upper layer of End of Transfer */
5695 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5696 }
5697 }
5698 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5699 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5700 {
5701 /* Call I2C Master complete process */
5702 I2C_ITMasterCplt(hi2c, ITFlags);
5703 }
5704 else
5705 {
5706 /* Nothing to do */
5707 }
5708
5709 /* Process Unlocked */
5710 __HAL_UNLOCK(hi2c);
5711
5712 return HAL_OK;
5713 }
5714
5715 /**
5716 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5717 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5718 * the configuration information for the specified I2C.
5719 * @param ITFlags Interrupt flags to handle.
5720 * @param ITSources Interrupt sources enabled.
5721 * @retval HAL status
5722 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5723 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5724 uint32_t ITSources)
5725 {
5726 uint32_t direction = I2C_GENERATE_START_WRITE;
5727
5728 /* Process Locked */
5729 __HAL_LOCK(hi2c);
5730
5731 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5732 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5733 {
5734 /* Clear NACK Flag */
5735 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5736
5737 /* Set corresponding Error Code */
5738 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5739
5740 /* No need to generate STOP, it is automatically done */
5741 /* But enable STOP interrupt, to treat it */
5742 /* Error callback will be send during stop flag treatment */
5743 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5744
5745 /* Flush TX register */
5746 I2C_Flush_TXDR(hi2c);
5747 }
5748 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5749 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5750 {
5751 /* Write LSB part of Memory Address */
5752 hi2c->Instance->TXDR = hi2c->Memaddress;
5753
5754 /* Reset Memaddress content */
5755 hi2c->Memaddress = 0xFFFFFFFFU;
5756 }
5757 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5758 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5759 {
5760 /* Disable Interrupt related to address step */
5761 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5762
5763 /* Enable only Error interrupt */
5764 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5765
5766 if (hi2c->XferCount != 0U)
5767 {
5768 /* Prepare the new XferSize to transfer */
5769 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5770 {
5771 hi2c->XferSize = MAX_NBYTE_SIZE;
5772 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5773 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5774 }
5775 else
5776 {
5777 hi2c->XferSize = hi2c->XferCount;
5778 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5779 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5780 }
5781
5782 /* Update XferCount value */
5783 hi2c->XferCount -= hi2c->XferSize;
5784
5785 /* Enable DMA Request */
5786 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5787 {
5788 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5789 }
5790 else
5791 {
5792 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5793 }
5794 }
5795 else
5796 {
5797 /* Wrong size Status regarding TCR flag event */
5798 /* Call the corresponding callback to inform upper layer of End of Transfer */
5799 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5800 }
5801 }
5802 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5803 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5804 {
5805 /* Disable Interrupt related to address step */
5806 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5807
5808 /* Enable only Error and NACK interrupt for data transfer */
5809 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5810
5811 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5812 {
5813 direction = I2C_GENERATE_START_READ;
5814 }
5815
5816 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5817 {
5818 hi2c->XferSize = MAX_NBYTE_SIZE;
5819
5820 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5821 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5822 I2C_RELOAD_MODE, direction);
5823 }
5824 else
5825 {
5826 hi2c->XferSize = hi2c->XferCount;
5827
5828 /* Set NBYTES to write and generate RESTART */
5829 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5830 I2C_AUTOEND_MODE, direction);
5831 }
5832
5833 /* Update XferCount value */
5834 hi2c->XferCount -= hi2c->XferSize;
5835
5836 /* Enable DMA Request */
5837 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5838 {
5839 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5840 }
5841 else
5842 {
5843 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5844 }
5845 }
5846 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5847 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5848 {
5849 /* Call I2C Master complete process */
5850 I2C_ITMasterCplt(hi2c, ITFlags);
5851 }
5852 else
5853 {
5854 /* Nothing to do */
5855 }
5856
5857 /* Process Unlocked */
5858 __HAL_UNLOCK(hi2c);
5859
5860 return HAL_OK;
5861 }
5862
5863 /**
5864 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5865 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5866 * the configuration information for the specified I2C.
5867 * @param ITFlags Interrupt flags to handle.
5868 * @param ITSources Interrupt sources enabled.
5869 * @retval HAL status
5870 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5871 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5872 uint32_t ITSources)
5873 {
5874 uint32_t tmpoptions = hi2c->XferOptions;
5875 uint32_t treatdmanack = 0U;
5876 HAL_I2C_StateTypeDef tmpstate;
5877
5878 /* Process locked */
5879 __HAL_LOCK(hi2c);
5880
5881 /* Check if STOPF is set */
5882 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5883 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5884 {
5885 /* Call I2C Slave complete process */
5886 I2C_ITSlaveCplt(hi2c, ITFlags);
5887 }
5888
5889 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5890 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5891 {
5892 /* Check that I2C transfer finished */
5893 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5894 /* Mean XferCount == 0 */
5895 /* So clear Flag NACKF only */
5896 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5897 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5898 {
5899 /* Split check of hdmarx, for MISRA compliance */
5900 if (hi2c->hdmarx != NULL)
5901 {
5902 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5903 {
5904 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5905 {
5906 treatdmanack = 1U;
5907 }
5908 }
5909 }
5910
5911 /* Split check of hdmatx, for MISRA compliance */
5912 if (hi2c->hdmatx != NULL)
5913 {
5914 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5915 {
5916 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5917 {
5918 treatdmanack = 1U;
5919 }
5920 }
5921 }
5922
5923 if (treatdmanack == 1U)
5924 {
5925 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5926 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5927 Warning[Pa134]: left and right operands are identical */
5928 {
5929 /* Call I2C Listen complete process */
5930 I2C_ITListenCplt(hi2c, ITFlags);
5931 }
5932 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5933 {
5934 /* Clear NACK Flag */
5935 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5936
5937 /* Flush TX register */
5938 I2C_Flush_TXDR(hi2c);
5939
5940 /* Last Byte is Transmitted */
5941 /* Call I2C Slave Sequential complete process */
5942 I2C_ITSlaveSeqCplt(hi2c);
5943 }
5944 else
5945 {
5946 /* Clear NACK Flag */
5947 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5948 }
5949 }
5950 else
5951 {
5952 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5953 /* Clear NACK Flag */
5954 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5955
5956 /* Set ErrorCode corresponding to a Non-Acknowledge */
5957 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5958
5959 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5960 tmpstate = hi2c->State;
5961
5962 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5963 {
5964 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5965 {
5966 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5967 }
5968 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5969 {
5970 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5971 }
5972 else
5973 {
5974 /* Do nothing */
5975 }
5976
5977 /* Call the corresponding callback to inform upper layer of End of Transfer */
5978 I2C_ITError(hi2c, hi2c->ErrorCode);
5979 }
5980 }
5981 }
5982 else
5983 {
5984 /* Only Clear NACK Flag, no DMA treatment is pending */
5985 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5986 }
5987 }
5988 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5989 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5990 {
5991 I2C_ITAddrCplt(hi2c, ITFlags);
5992 }
5993 else
5994 {
5995 /* Nothing to do */
5996 }
5997
5998 /* Process Unlocked */
5999 __HAL_UNLOCK(hi2c);
6000
6001 return HAL_OK;
6002 }
6003 #endif /* HAL_DMA_MODULE_ENABLED */
6004
6005 /**
6006 * @brief Master sends target device address followed by internal memory address for write request.
6007 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6008 * the configuration information for the specified I2C.
6009 * @param DevAddress Target device address: The device 7 bits address value
6010 * in datasheet must be shifted to the left before calling the interface
6011 * @param MemAddress Internal memory address
6012 * @param MemAddSize Size of internal memory address
6013 * @param Timeout Timeout duration
6014 * @param Tickstart Tick start value
6015 * @retval HAL status
6016 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6017 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6018 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6019 uint32_t Tickstart)
6020 {
6021 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
6022
6023 /* Wait until TXIS flag is set */
6024 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6025 {
6026 return HAL_ERROR;
6027 }
6028
6029 /* If Memory address size is 8Bit */
6030 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6031 {
6032 /* Send Memory Address */
6033 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6034 }
6035 /* If Memory address size is 16Bit */
6036 else
6037 {
6038 /* Send MSB of Memory Address */
6039 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6040
6041 /* Wait until TXIS flag is set */
6042 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6043 {
6044 return HAL_ERROR;
6045 }
6046
6047 /* Send LSB of Memory Address */
6048 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6049 }
6050
6051 /* Wait until TCR flag is set */
6052 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
6053 {
6054 return HAL_ERROR;
6055 }
6056
6057 return HAL_OK;
6058 }
6059
6060 /**
6061 * @brief Master sends target device address followed by internal memory address for read request.
6062 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6063 * the configuration information for the specified I2C.
6064 * @param DevAddress Target device address: The device 7 bits address value
6065 * in datasheet must be shifted to the left before calling the interface
6066 * @param MemAddress Internal memory address
6067 * @param MemAddSize Size of internal memory address
6068 * @param Timeout Timeout duration
6069 * @param Tickstart Tick start value
6070 * @retval HAL status
6071 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6072 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6073 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6074 uint32_t Tickstart)
6075 {
6076 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
6077
6078 /* Wait until TXIS flag is set */
6079 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6080 {
6081 return HAL_ERROR;
6082 }
6083
6084 /* If Memory address size is 8Bit */
6085 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6086 {
6087 /* Send Memory Address */
6088 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6089 }
6090 /* If Memory address size is 16Bit */
6091 else
6092 {
6093 /* Send MSB of Memory Address */
6094 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6095
6096 /* Wait until TXIS flag is set */
6097 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6098 {
6099 return HAL_ERROR;
6100 }
6101
6102 /* Send LSB of Memory Address */
6103 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6104 }
6105
6106 /* Wait until TC flag is set */
6107 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
6108 {
6109 return HAL_ERROR;
6110 }
6111
6112 return HAL_OK;
6113 }
6114
6115 /**
6116 * @brief I2C Address complete process callback.
6117 * @param hi2c I2C handle.
6118 * @param ITFlags Interrupt flags to handle.
6119 * @retval None
6120 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6121 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6122 {
6123 uint8_t transferdirection;
6124 uint16_t slaveaddrcode;
6125 uint16_t ownadd1code;
6126 uint16_t ownadd2code;
6127
6128 /* Prevent unused argument(s) compilation warning */
6129 UNUSED(ITFlags);
6130
6131 /* In case of Listen state, need to inform upper layer of address match code event */
6132 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6133 {
6134 transferdirection = I2C_GET_DIR(hi2c);
6135 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
6136 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
6137 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
6138
6139 /* If 10bits addressing mode is selected */
6140 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
6141 {
6142 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
6143 {
6144 slaveaddrcode = ownadd1code;
6145 hi2c->AddrEventCount++;
6146 if (hi2c->AddrEventCount == 2U)
6147 {
6148 /* Reset Address Event counter */
6149 hi2c->AddrEventCount = 0U;
6150
6151 /* Clear ADDR flag */
6152 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6153
6154 /* Process Unlocked */
6155 __HAL_UNLOCK(hi2c);
6156
6157 /* Call Slave Addr callback */
6158 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6159 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6160 #else
6161 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6162 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6163 }
6164 }
6165 else
6166 {
6167 slaveaddrcode = ownadd2code;
6168
6169 /* Disable ADDR Interrupts */
6170 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6171
6172 /* Process Unlocked */
6173 __HAL_UNLOCK(hi2c);
6174
6175 /* Call Slave Addr callback */
6176 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6177 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6178 #else
6179 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6180 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6181 }
6182 }
6183 /* else 7 bits addressing mode is selected */
6184 else
6185 {
6186 /* Disable ADDR Interrupts */
6187 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6188
6189 /* Process Unlocked */
6190 __HAL_UNLOCK(hi2c);
6191
6192 /* Call Slave Addr callback */
6193 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6194 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6195 #else
6196 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6197 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6198 }
6199 }
6200 /* Else clear address flag only */
6201 else
6202 {
6203 /* Clear ADDR flag */
6204 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6205
6206 /* Process Unlocked */
6207 __HAL_UNLOCK(hi2c);
6208 }
6209 }
6210
6211 /**
6212 * @brief I2C Master sequential complete process.
6213 * @param hi2c I2C handle.
6214 * @retval None
6215 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)6216 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
6217 {
6218 /* Reset I2C handle mode */
6219 hi2c->Mode = HAL_I2C_MODE_NONE;
6220
6221 /* No Generate Stop, to permit restart mode */
6222 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
6223 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6224 {
6225 hi2c->State = HAL_I2C_STATE_READY;
6226 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6227 hi2c->XferISR = NULL;
6228
6229 /* Disable Interrupts */
6230 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6231
6232 /* Process Unlocked */
6233 __HAL_UNLOCK(hi2c);
6234
6235 /* Call the corresponding callback to inform upper layer of End of Transfer */
6236 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6237 hi2c->MasterTxCpltCallback(hi2c);
6238 #else
6239 HAL_I2C_MasterTxCpltCallback(hi2c);
6240 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6241 }
6242 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6243 else
6244 {
6245 hi2c->State = HAL_I2C_STATE_READY;
6246 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6247 hi2c->XferISR = NULL;
6248
6249 /* Disable Interrupts */
6250 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6251
6252 /* Process Unlocked */
6253 __HAL_UNLOCK(hi2c);
6254
6255 /* Call the corresponding callback to inform upper layer of End of Transfer */
6256 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6257 hi2c->MasterRxCpltCallback(hi2c);
6258 #else
6259 HAL_I2C_MasterRxCpltCallback(hi2c);
6260 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6261 }
6262 }
6263
6264 /**
6265 * @brief I2C Slave sequential complete process.
6266 * @param hi2c I2C handle.
6267 * @retval None
6268 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)6269 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
6270 {
6271 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6272
6273 /* Reset I2C handle mode */
6274 hi2c->Mode = HAL_I2C_MODE_NONE;
6275
6276 #if defined(HAL_DMA_MODULE_ENABLED)
6277 /* If a DMA is ongoing, Update handle size context */
6278 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6279 {
6280 /* Disable DMA Request */
6281 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6282 }
6283 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6284 {
6285 /* Disable DMA Request */
6286 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6287 }
6288 else
6289 {
6290 /* Do nothing */
6291 }
6292 #endif /* HAL_DMA_MODULE_ENABLED */
6293
6294 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
6295 {
6296 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
6297 hi2c->State = HAL_I2C_STATE_LISTEN;
6298 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6299
6300 /* Disable Interrupts */
6301 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6302
6303 /* Process Unlocked */
6304 __HAL_UNLOCK(hi2c);
6305
6306 /* Call the corresponding callback to inform upper layer of End of Transfer */
6307 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6308 hi2c->SlaveTxCpltCallback(hi2c);
6309 #else
6310 HAL_I2C_SlaveTxCpltCallback(hi2c);
6311 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6312 }
6313
6314 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
6315 {
6316 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
6317 hi2c->State = HAL_I2C_STATE_LISTEN;
6318 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6319
6320 /* Disable Interrupts */
6321 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6322
6323 /* Process Unlocked */
6324 __HAL_UNLOCK(hi2c);
6325
6326 /* Call the corresponding callback to inform upper layer of End of Transfer */
6327 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6328 hi2c->SlaveRxCpltCallback(hi2c);
6329 #else
6330 HAL_I2C_SlaveRxCpltCallback(hi2c);
6331 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6332 }
6333 else
6334 {
6335 /* Nothing to do */
6336 }
6337 }
6338
6339 /**
6340 * @brief I2C Master complete process.
6341 * @param hi2c I2C handle.
6342 * @param ITFlags Interrupt flags to handle.
6343 * @retval None
6344 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6345 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6346 {
6347 uint32_t tmperror;
6348 uint32_t tmpITFlags = ITFlags;
6349 __IO uint32_t tmpreg;
6350
6351 /* Clear STOP Flag */
6352 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6353
6354 /* Disable Interrupts and Store Previous state */
6355 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6356 {
6357 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6358 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6359 }
6360 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6361 {
6362 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6363 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6364 }
6365 else
6366 {
6367 /* Do nothing */
6368 }
6369
6370 /* Clear Configuration Register 2 */
6371 I2C_RESET_CR2(hi2c);
6372
6373 /* Reset handle parameters */
6374 hi2c->XferISR = NULL;
6375 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6376
6377 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6378 {
6379 /* Clear NACK Flag */
6380 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6381
6382 /* Set acknowledge error code */
6383 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6384 }
6385
6386 /* Fetch Last receive data if any */
6387 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6388 {
6389 /* Read data from RXDR */
6390 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6391 UNUSED(tmpreg);
6392 }
6393
6394 /* Flush TX register */
6395 I2C_Flush_TXDR(hi2c);
6396
6397 /* Store current volatile hi2c->ErrorCode, misra rule */
6398 tmperror = hi2c->ErrorCode;
6399
6400 /* Call the corresponding callback to inform upper layer of End of Transfer */
6401 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6402 {
6403 /* Call the corresponding callback to inform upper layer of End of Transfer */
6404 I2C_ITError(hi2c, hi2c->ErrorCode);
6405 }
6406 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6407 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6408 {
6409 hi2c->State = HAL_I2C_STATE_READY;
6410 hi2c->PreviousState = I2C_STATE_NONE;
6411
6412 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6413 {
6414 hi2c->Mode = HAL_I2C_MODE_NONE;
6415
6416 /* Process Unlocked */
6417 __HAL_UNLOCK(hi2c);
6418
6419 /* Call the corresponding callback to inform upper layer of End of Transfer */
6420 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6421 hi2c->MemTxCpltCallback(hi2c);
6422 #else
6423 HAL_I2C_MemTxCpltCallback(hi2c);
6424 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6425 }
6426 else
6427 {
6428 hi2c->Mode = HAL_I2C_MODE_NONE;
6429
6430 /* Process Unlocked */
6431 __HAL_UNLOCK(hi2c);
6432
6433 /* Call the corresponding callback to inform upper layer of End of Transfer */
6434 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6435 hi2c->MasterTxCpltCallback(hi2c);
6436 #else
6437 HAL_I2C_MasterTxCpltCallback(hi2c);
6438 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6439 }
6440 }
6441 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6442 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6443 {
6444 hi2c->State = HAL_I2C_STATE_READY;
6445 hi2c->PreviousState = I2C_STATE_NONE;
6446
6447 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6448 {
6449 hi2c->Mode = HAL_I2C_MODE_NONE;
6450
6451 /* Process Unlocked */
6452 __HAL_UNLOCK(hi2c);
6453
6454 /* Call the corresponding callback to inform upper layer of End of Transfer */
6455 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6456 hi2c->MemRxCpltCallback(hi2c);
6457 #else
6458 HAL_I2C_MemRxCpltCallback(hi2c);
6459 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6460 }
6461 else
6462 {
6463 hi2c->Mode = HAL_I2C_MODE_NONE;
6464
6465 /* Process Unlocked */
6466 __HAL_UNLOCK(hi2c);
6467
6468 /* Call the corresponding callback to inform upper layer of End of Transfer */
6469 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6470 hi2c->MasterRxCpltCallback(hi2c);
6471 #else
6472 HAL_I2C_MasterRxCpltCallback(hi2c);
6473 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6474 }
6475 }
6476 else
6477 {
6478 /* Nothing to do */
6479 }
6480 }
6481
6482 /**
6483 * @brief I2C Slave complete process.
6484 * @param hi2c I2C handle.
6485 * @param ITFlags Interrupt flags to handle.
6486 * @retval None
6487 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6488 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6489 {
6490 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6491 uint32_t tmpITFlags = ITFlags;
6492 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6493
6494 /* Clear STOP Flag */
6495 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6496
6497 /* Disable Interrupts and Store Previous state */
6498 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6499 {
6500 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6501 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6502 }
6503 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6504 {
6505 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6506 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6507 }
6508 else if (tmpstate == HAL_I2C_STATE_LISTEN)
6509 {
6510 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
6511 hi2c->PreviousState = I2C_STATE_NONE;
6512 }
6513 else
6514 {
6515 /* Do nothing */
6516 }
6517
6518 /* Disable Address Acknowledge */
6519 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6520
6521 /* Clear Configuration Register 2 */
6522 I2C_RESET_CR2(hi2c);
6523
6524 /* Flush TX register */
6525 I2C_Flush_TXDR(hi2c);
6526
6527 #if defined(HAL_DMA_MODULE_ENABLED)
6528 /* If a DMA is ongoing, Update handle size context */
6529 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6530 {
6531 /* Disable DMA Request */
6532 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6533
6534 if (hi2c->hdmatx != NULL)
6535 {
6536 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6537 }
6538 }
6539 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6540 {
6541 /* Disable DMA Request */
6542 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6543
6544 if (hi2c->hdmarx != NULL)
6545 {
6546 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6547 }
6548 }
6549 else
6550 {
6551 /* Do nothing */
6552 }
6553 #endif /* HAL_DMA_MODULE_ENABLED */
6554
6555 /* Store Last receive data if any */
6556 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6557 {
6558 /* Remove RXNE flag on temporary variable as read done */
6559 tmpITFlags &= ~I2C_FLAG_RXNE;
6560
6561 /* Read data from RXDR */
6562 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6563
6564 /* Increment Buffer pointer */
6565 hi2c->pBuffPtr++;
6566
6567 if ((hi2c->XferSize > 0U))
6568 {
6569 hi2c->XferSize--;
6570 hi2c->XferCount--;
6571 }
6572 }
6573
6574 /* All data are not transferred, so set error code accordingly */
6575 if (hi2c->XferCount != 0U)
6576 {
6577 /* Set ErrorCode corresponding to a Non-Acknowledge */
6578 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6579 }
6580
6581 hi2c->Mode = HAL_I2C_MODE_NONE;
6582 hi2c->XferISR = NULL;
6583
6584 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6585 {
6586 /* Call the corresponding callback to inform upper layer of End of Transfer */
6587 I2C_ITError(hi2c, hi2c->ErrorCode);
6588
6589 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6590 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6591 {
6592 /* Call I2C Listen complete process */
6593 I2C_ITListenCplt(hi2c, tmpITFlags);
6594 }
6595 }
6596 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6597 {
6598 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6599 I2C_ITSlaveSeqCplt(hi2c);
6600
6601 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6602 hi2c->State = HAL_I2C_STATE_READY;
6603 hi2c->PreviousState = I2C_STATE_NONE;
6604
6605 /* Process Unlocked */
6606 __HAL_UNLOCK(hi2c);
6607
6608 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6609 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6610 hi2c->ListenCpltCallback(hi2c);
6611 #else
6612 HAL_I2C_ListenCpltCallback(hi2c);
6613 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6614 }
6615 /* Call the corresponding callback to inform upper layer of End of Transfer */
6616 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6617 {
6618 hi2c->State = HAL_I2C_STATE_READY;
6619 hi2c->PreviousState = I2C_STATE_NONE;
6620
6621 /* Process Unlocked */
6622 __HAL_UNLOCK(hi2c);
6623
6624 /* Call the corresponding callback to inform upper layer of End of Transfer */
6625 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6626 hi2c->SlaveRxCpltCallback(hi2c);
6627 #else
6628 HAL_I2C_SlaveRxCpltCallback(hi2c);
6629 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6630 }
6631 else
6632 {
6633 hi2c->State = HAL_I2C_STATE_READY;
6634 hi2c->PreviousState = I2C_STATE_NONE;
6635
6636 /* Process Unlocked */
6637 __HAL_UNLOCK(hi2c);
6638
6639 /* Call the corresponding callback to inform upper layer of End of Transfer */
6640 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6641 hi2c->SlaveTxCpltCallback(hi2c);
6642 #else
6643 HAL_I2C_SlaveTxCpltCallback(hi2c);
6644 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6645 }
6646 }
6647
6648 /**
6649 * @brief I2C Listen complete process.
6650 * @param hi2c I2C handle.
6651 * @param ITFlags Interrupt flags to handle.
6652 * @retval None
6653 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6654 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6655 {
6656 /* Reset handle parameters */
6657 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6658 hi2c->PreviousState = I2C_STATE_NONE;
6659 hi2c->State = HAL_I2C_STATE_READY;
6660 hi2c->Mode = HAL_I2C_MODE_NONE;
6661 hi2c->XferISR = NULL;
6662
6663 /* Store Last receive data if any */
6664 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6665 {
6666 /* Read data from RXDR */
6667 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6668
6669 /* Increment Buffer pointer */
6670 hi2c->pBuffPtr++;
6671
6672 if ((hi2c->XferSize > 0U))
6673 {
6674 hi2c->XferSize--;
6675 hi2c->XferCount--;
6676
6677 /* Set ErrorCode corresponding to a Non-Acknowledge */
6678 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6679 }
6680 }
6681
6682 /* Disable all Interrupts*/
6683 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6684
6685 /* Clear NACK Flag */
6686 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6687
6688 /* Process Unlocked */
6689 __HAL_UNLOCK(hi2c);
6690
6691 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6692 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6693 hi2c->ListenCpltCallback(hi2c);
6694 #else
6695 HAL_I2C_ListenCpltCallback(hi2c);
6696 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6697 }
6698
6699 /**
6700 * @brief I2C interrupts error process.
6701 * @param hi2c I2C handle.
6702 * @param ErrorCode Error code to handle.
6703 * @retval None
6704 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6705 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6706 {
6707 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6708
6709 #if defined(HAL_DMA_MODULE_ENABLED)
6710 uint32_t tmppreviousstate;
6711 #endif /* HAL_DMA_MODULE_ENABLED */
6712
6713 /* Reset handle parameters */
6714 hi2c->Mode = HAL_I2C_MODE_NONE;
6715 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6716 hi2c->XferCount = 0U;
6717
6718 /* Set new error code */
6719 hi2c->ErrorCode |= ErrorCode;
6720
6721 /* Disable Interrupts */
6722 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6723 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6724 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6725 {
6726 /* Disable all interrupts, except interrupts related to LISTEN state */
6727 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6728
6729 /* keep HAL_I2C_STATE_LISTEN if set */
6730 hi2c->State = HAL_I2C_STATE_LISTEN;
6731 hi2c->XferISR = I2C_Slave_ISR_IT;
6732 }
6733 else
6734 {
6735 /* Disable all interrupts */
6736 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6737
6738 /* Flush TX register */
6739 I2C_Flush_TXDR(hi2c);
6740
6741 /* If state is an abort treatment on going, don't change state */
6742 /* This change will be do later */
6743 if (hi2c->State != HAL_I2C_STATE_ABORT)
6744 {
6745 /* Set HAL_I2C_STATE_READY */
6746 hi2c->State = HAL_I2C_STATE_READY;
6747
6748 /* Check if a STOPF is detected */
6749 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6750 {
6751 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6752 {
6753 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6754 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6755 }
6756
6757 /* Clear STOP Flag */
6758 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6759 }
6760
6761 }
6762 hi2c->XferISR = NULL;
6763 }
6764
6765 #if defined(HAL_DMA_MODULE_ENABLED)
6766 /* Abort DMA TX transfer if any */
6767 tmppreviousstate = hi2c->PreviousState;
6768
6769 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6770 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6771 {
6772 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6773 {
6774 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6775 }
6776
6777 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6778 {
6779 /* Set the I2C DMA Abort callback :
6780 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6781 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6782
6783 /* Process Unlocked */
6784 __HAL_UNLOCK(hi2c);
6785
6786 /* Abort DMA TX */
6787 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6788 {
6789 /* Call Directly XferAbortCallback function in case of error */
6790 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6791 }
6792 }
6793 else
6794 {
6795 I2C_TreatErrorCallback(hi2c);
6796 }
6797 }
6798 /* Abort DMA RX transfer if any */
6799 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6800 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6801 {
6802 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6803 {
6804 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6805 }
6806
6807 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6808 {
6809 /* Set the I2C DMA Abort callback :
6810 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6811 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6812
6813 /* Process Unlocked */
6814 __HAL_UNLOCK(hi2c);
6815
6816 /* Abort DMA RX */
6817 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6818 {
6819 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6820 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6821 }
6822 }
6823 else
6824 {
6825 I2C_TreatErrorCallback(hi2c);
6826 }
6827 }
6828 else
6829 #endif /* HAL_DMA_MODULE_ENABLED */
6830 {
6831 I2C_TreatErrorCallback(hi2c);
6832 }
6833 }
6834
6835 /**
6836 * @brief I2C Error callback treatment.
6837 * @param hi2c I2C handle.
6838 * @retval None
6839 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6840 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6841 {
6842 if (hi2c->State == HAL_I2C_STATE_ABORT)
6843 {
6844 hi2c->State = HAL_I2C_STATE_READY;
6845 hi2c->PreviousState = I2C_STATE_NONE;
6846
6847 /* Process Unlocked */
6848 __HAL_UNLOCK(hi2c);
6849
6850 /* Call the corresponding callback to inform upper layer of End of Transfer */
6851 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6852 hi2c->AbortCpltCallback(hi2c);
6853 #else
6854 HAL_I2C_AbortCpltCallback(hi2c);
6855 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6856 }
6857 else
6858 {
6859 hi2c->PreviousState = I2C_STATE_NONE;
6860
6861 /* Process Unlocked */
6862 __HAL_UNLOCK(hi2c);
6863
6864 /* Call the corresponding callback to inform upper layer of End of Transfer */
6865 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6866 hi2c->ErrorCallback(hi2c);
6867 #else
6868 HAL_I2C_ErrorCallback(hi2c);
6869 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6870 }
6871 }
6872
6873 /**
6874 * @brief I2C Tx data register flush process.
6875 * @param hi2c I2C handle.
6876 * @retval None
6877 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6878 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6879 {
6880 /* If a pending TXIS flag is set */
6881 /* Write a dummy data in TXDR to clear it */
6882 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6883 {
6884 hi2c->Instance->TXDR = 0x00U;
6885 }
6886
6887 /* Flush TX register if not empty */
6888 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6889 {
6890 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6891 }
6892 }
6893
6894 #if defined(HAL_DMA_MODULE_ENABLED)
6895 /**
6896 * @brief DMA I2C master transmit process complete callback.
6897 * @param hdma DMA handle
6898 * @retval None
6899 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6900 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6901 {
6902 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
6903 /* Derogation MISRAC2012-Rule-11.5 */
6904 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6905
6906 /* Disable DMA Request */
6907 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6908
6909 /* If last transfer, enable STOP interrupt */
6910 if (hi2c->XferCount == 0U)
6911 {
6912 /* Enable STOP interrupt */
6913 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6914 }
6915 /* else prepare a new DMA transfer and enable TCReload interrupt */
6916 else
6917 {
6918 /* Update Buffer pointer */
6919 hi2c->pBuffPtr += hi2c->XferSize;
6920
6921 /* Set the XferSize to transfer */
6922 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6923 {
6924 hi2c->XferSize = MAX_NBYTE_SIZE;
6925 }
6926 else
6927 {
6928 hi2c->XferSize = hi2c->XferCount;
6929 }
6930
6931 /* Enable the DMA channel */
6932 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
6933 {
6934 if (hi2c->hdmatx->LinkedListQueue != NULL)
6935 {
6936 /* Set DMA data size */
6937 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
6938
6939 /* Set DMA source address */
6940 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
6941
6942 /* Set DMA destination address */
6943 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR;
6944
6945 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
6946 }
6947 else
6948 {
6949 /* Call the corresponding callback to inform upper layer of End of Transfer */
6950 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6951 }
6952 }
6953 else
6954 {
6955 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6956 hi2c->XferSize);
6957 }
6958
6959 if (dmaxferstatus != HAL_OK)
6960 {
6961 /* Call the corresponding callback to inform upper layer of End of Transfer */
6962 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6963 }
6964 else
6965 {
6966 /* Enable TC interrupts */
6967 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6968 }
6969 }
6970 }
6971
6972
6973 /**
6974 * @brief DMA I2C slave transmit process complete callback.
6975 * @param hdma DMA handle
6976 * @retval None
6977 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6978 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6979 {
6980 /* Derogation MISRAC2012-Rule-11.5 */
6981 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6982 uint32_t tmpoptions = hi2c->XferOptions;
6983
6984 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6985 {
6986 /* Disable DMA Request */
6987 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6988
6989 /* Last Byte is Transmitted */
6990 /* Call I2C Slave Sequential complete process */
6991 I2C_ITSlaveSeqCplt(hi2c);
6992 }
6993 else
6994 {
6995 /* No specific action, Master fully manage the generation of STOP condition */
6996 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6997 /* So STOP condition should be manage through Interrupt treatment */
6998 }
6999 }
7000
7001
7002 /**
7003 * @brief DMA I2C master receive process complete callback.
7004 * @param hdma DMA handle
7005 * @retval None
7006 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)7007 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
7008 {
7009 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
7010 /* Derogation MISRAC2012-Rule-11.5 */
7011 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7012
7013 /* Disable DMA Request */
7014 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7015
7016 /* If last transfer, enable STOP interrupt */
7017 if (hi2c->XferCount == 0U)
7018 {
7019 /* Enable STOP interrupt */
7020 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
7021 }
7022 /* else prepare a new DMA transfer and enable TCReload interrupt */
7023 else
7024 {
7025 /* Update Buffer pointer */
7026 hi2c->pBuffPtr += hi2c->XferSize;
7027
7028 /* Set the XferSize to transfer */
7029 if (hi2c->XferCount > MAX_NBYTE_SIZE)
7030 {
7031 hi2c->XferSize = MAX_NBYTE_SIZE;
7032 }
7033 else
7034 {
7035 hi2c->XferSize = hi2c->XferCount;
7036 }
7037
7038 /* Enable the DMA channel */
7039 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
7040 {
7041 if (hi2c->hdmarx->LinkedListQueue != NULL)
7042 {
7043 /* Set DMA data size */
7044 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
7045
7046 /* Set DMA source address */
7047 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR;
7048
7049 /* Set DMA destination address */
7050 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
7051
7052 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
7053 }
7054 else
7055 {
7056 /* Call the corresponding callback to inform upper layer of End of Transfer */
7057 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7058 }
7059 }
7060 else
7061 {
7062 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
7063 hi2c->XferSize);
7064 }
7065
7066 if (dmaxferstatus != HAL_OK)
7067 {
7068 /* Call the corresponding callback to inform upper layer of End of Transfer */
7069 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7070 }
7071 else
7072 {
7073 /* Enable TC interrupts */
7074 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
7075 }
7076 }
7077 }
7078
7079
7080 /**
7081 * @brief DMA I2C slave receive process complete callback.
7082 * @param hdma DMA handle
7083 * @retval None
7084 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)7085 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
7086 {
7087 /* Derogation MISRAC2012-Rule-11.5 */
7088 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7089 uint32_t tmpoptions = hi2c->XferOptions;
7090
7091 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
7092 (tmpoptions != I2C_NO_OPTION_FRAME))
7093 {
7094 /* Disable DMA Request */
7095 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7096
7097 /* Call I2C Slave Sequential complete process */
7098 I2C_ITSlaveSeqCplt(hi2c);
7099 }
7100 else
7101 {
7102 /* No specific action, Master fully manage the generation of STOP condition */
7103 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7104 /* So STOP condition should be manage through Interrupt treatment */
7105 }
7106 }
7107
7108
7109 /**
7110 * @brief DMA I2C communication error callback.
7111 * @param hdma DMA handle
7112 * @retval None
7113 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7114 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7115 {
7116 /* Derogation MISRAC2012-Rule-11.5 */
7117 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7118
7119 /* Disable Acknowledge */
7120 hi2c->Instance->CR2 |= I2C_CR2_NACK;
7121
7122 /* Call the corresponding callback to inform upper layer of End of Transfer */
7123 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7124 }
7125
7126
7127 /**
7128 * @brief DMA I2C communication abort callback
7129 * (To be called at end of DMA Abort procedure).
7130 * @param hdma DMA handle.
7131 * @retval None
7132 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7133 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7134 {
7135 /* Derogation MISRAC2012-Rule-11.5 */
7136 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7137
7138 /* Reset AbortCpltCallback */
7139 if (hi2c->hdmatx != NULL)
7140 {
7141 hi2c->hdmatx->XferAbortCallback = NULL;
7142 }
7143 if (hi2c->hdmarx != NULL)
7144 {
7145 hi2c->hdmarx->XferAbortCallback = NULL;
7146 }
7147
7148 I2C_TreatErrorCallback(hi2c);
7149 }
7150
7151 #endif /* HAL_DMA_MODULE_ENABLED */
7152
7153 /**
7154 * @brief This function handles I2C Communication Timeout. It waits
7155 * until a flag is no longer in the specified status.
7156 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7157 * the configuration information for the specified I2C.
7158 * @param Flag Specifies the I2C flag to check.
7159 * @param Status The actual Flag status (SET or RESET).
7160 * @param Timeout Timeout duration
7161 * @param Tickstart Tick start value
7162 * @retval HAL status
7163 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7164 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
7165 uint32_t Timeout, uint32_t Tickstart)
7166 {
7167 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7168 {
7169 /* Check for the Timeout */
7170 if (Timeout != HAL_MAX_DELAY)
7171 {
7172 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7173 {
7174 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7175 hi2c->State = HAL_I2C_STATE_READY;
7176 hi2c->Mode = HAL_I2C_MODE_NONE;
7177
7178 /* Process Unlocked */
7179 __HAL_UNLOCK(hi2c);
7180 return HAL_ERROR;
7181 }
7182 }
7183 }
7184 return HAL_OK;
7185 }
7186
7187 /**
7188 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
7189 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7190 * the configuration information for the specified I2C.
7191 * @param Timeout Timeout duration
7192 * @param Tickstart Tick start value
7193 * @retval HAL status
7194 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7195 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7196 uint32_t Tickstart)
7197 {
7198 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
7199 {
7200 /* Check if an error is detected */
7201 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7202 {
7203 return HAL_ERROR;
7204 }
7205
7206 /* Check for the Timeout */
7207 if (Timeout != HAL_MAX_DELAY)
7208 {
7209 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7210 {
7211 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7212 hi2c->State = HAL_I2C_STATE_READY;
7213 hi2c->Mode = HAL_I2C_MODE_NONE;
7214
7215 /* Process Unlocked */
7216 __HAL_UNLOCK(hi2c);
7217
7218 return HAL_ERROR;
7219 }
7220 }
7221 }
7222 return HAL_OK;
7223 }
7224
7225 /**
7226 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7227 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7228 * the configuration information for the specified I2C.
7229 * @param Timeout Timeout duration
7230 * @param Tickstart Tick start value
7231 * @retval HAL status
7232 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7233 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7234 uint32_t Tickstart)
7235 {
7236 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7237 {
7238 /* Check if an error is detected */
7239 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7240 {
7241 return HAL_ERROR;
7242 }
7243
7244 /* Check for the Timeout */
7245 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7246 {
7247 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7248 hi2c->State = HAL_I2C_STATE_READY;
7249 hi2c->Mode = HAL_I2C_MODE_NONE;
7250
7251 /* Process Unlocked */
7252 __HAL_UNLOCK(hi2c);
7253
7254 return HAL_ERROR;
7255 }
7256 }
7257 return HAL_OK;
7258 }
7259
7260 /**
7261 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7262 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7263 * the configuration information for the specified I2C.
7264 * @param Timeout Timeout duration
7265 * @param Tickstart Tick start value
7266 * @retval HAL status
7267 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7268 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7269 uint32_t Tickstart)
7270 {
7271 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7272 {
7273 /* Check if an error is detected */
7274 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7275 {
7276 return HAL_ERROR;
7277 }
7278
7279 /* Check if a STOPF is detected */
7280 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7281 {
7282 /* Check if an RXNE is pending */
7283 /* Store Last receive data if any */
7284 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7285 {
7286 /* Return HAL_OK */
7287 /* The Reading of data from RXDR will be done in caller function */
7288 return HAL_OK;
7289 }
7290 else
7291 {
7292 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7293 {
7294 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7295 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7296 }
7297 else
7298 {
7299 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7300 }
7301
7302 /* Clear STOP Flag */
7303 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7304
7305 /* Clear Configuration Register 2 */
7306 I2C_RESET_CR2(hi2c);
7307
7308 hi2c->State = HAL_I2C_STATE_READY;
7309 hi2c->Mode = HAL_I2C_MODE_NONE;
7310
7311 /* Process Unlocked */
7312 __HAL_UNLOCK(hi2c);
7313
7314 return HAL_ERROR;
7315 }
7316 }
7317
7318 /* Check for the Timeout */
7319 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7320 {
7321 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7322 hi2c->State = HAL_I2C_STATE_READY;
7323
7324 /* Process Unlocked */
7325 __HAL_UNLOCK(hi2c);
7326
7327 return HAL_ERROR;
7328 }
7329 }
7330 return HAL_OK;
7331 }
7332
7333 /**
7334 * @brief This function handles errors detection during an I2C Communication.
7335 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7336 * the configuration information for the specified I2C.
7337 * @param Timeout Timeout duration
7338 * @param Tickstart Tick start value
7339 * @retval HAL status
7340 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7341 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7342 {
7343 HAL_StatusTypeDef status = HAL_OK;
7344 uint32_t itflag = hi2c->Instance->ISR;
7345 uint32_t error_code = 0;
7346 uint32_t tickstart = Tickstart;
7347 uint32_t tmp1;
7348 HAL_I2C_ModeTypeDef tmp2;
7349
7350 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7351 {
7352 /* Clear NACKF Flag */
7353 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7354
7355 /* Wait until STOP Flag is set or timeout occurred */
7356 /* AutoEnd should be initiate after AF */
7357 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7358 {
7359 /* Check for the Timeout */
7360 if (Timeout != HAL_MAX_DELAY)
7361 {
7362 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7363 {
7364 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7365 tmp2 = hi2c->Mode;
7366
7367 /* In case of I2C still busy, try to regenerate a STOP manually */
7368 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7369 (tmp1 != I2C_CR2_STOP) && \
7370 (tmp2 != HAL_I2C_MODE_SLAVE))
7371 {
7372 /* Generate Stop */
7373 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7374
7375 /* Update Tick with new reference */
7376 tickstart = HAL_GetTick();
7377 }
7378
7379 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7380 {
7381 /* Check for the Timeout */
7382 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7383 {
7384 error_code |= HAL_I2C_ERROR_TIMEOUT;
7385
7386 status = HAL_ERROR;
7387
7388 break;
7389 }
7390 }
7391 }
7392 }
7393 }
7394
7395 /* In case STOP Flag is detected, clear it */
7396 if (status == HAL_OK)
7397 {
7398 /* Clear STOP Flag */
7399 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7400 }
7401
7402 error_code |= HAL_I2C_ERROR_AF;
7403
7404 status = HAL_ERROR;
7405 }
7406
7407 /* Refresh Content of Status register */
7408 itflag = hi2c->Instance->ISR;
7409
7410 /* Then verify if an additional errors occurs */
7411 /* Check if a Bus error occurred */
7412 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7413 {
7414 error_code |= HAL_I2C_ERROR_BERR;
7415
7416 /* Clear BERR flag */
7417 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7418
7419 status = HAL_ERROR;
7420 }
7421
7422 /* Check if an Over-Run/Under-Run error occurred */
7423 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7424 {
7425 error_code |= HAL_I2C_ERROR_OVR;
7426
7427 /* Clear OVR flag */
7428 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7429
7430 status = HAL_ERROR;
7431 }
7432
7433 /* Check if an Arbitration Loss error occurred */
7434 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7435 {
7436 error_code |= HAL_I2C_ERROR_ARLO;
7437
7438 /* Clear ARLO flag */
7439 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7440
7441 status = HAL_ERROR;
7442 }
7443
7444 if (status != HAL_OK)
7445 {
7446 /* Flush TX register */
7447 I2C_Flush_TXDR(hi2c);
7448
7449 /* Clear Configuration Register 2 */
7450 I2C_RESET_CR2(hi2c);
7451
7452 hi2c->ErrorCode |= error_code;
7453 hi2c->State = HAL_I2C_STATE_READY;
7454 hi2c->Mode = HAL_I2C_MODE_NONE;
7455
7456 /* Process Unlocked */
7457 __HAL_UNLOCK(hi2c);
7458 }
7459
7460 return status;
7461 }
7462
7463 /**
7464 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7465 * @param hi2c I2C handle.
7466 * @param DevAddress Specifies the slave address to be programmed.
7467 * @param Size Specifies the number of bytes to be programmed.
7468 * This parameter must be a value between 0 and 255.
7469 * @param Mode New state of the I2C START condition generation.
7470 * This parameter can be one of the following values:
7471 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7472 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7473 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7474 * @param Request New state of the I2C START condition generation.
7475 * This parameter can be one of the following values:
7476 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7477 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7478 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7479 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7480 * @retval None
7481 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7482 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7483 uint32_t Request)
7484 {
7485 /* Check the parameters */
7486 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7487 assert_param(IS_TRANSFER_MODE(Mode));
7488 assert_param(IS_TRANSFER_REQUEST(Request));
7489
7490 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7491 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7492 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7493 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7494
7495 /* update CR2 register */
7496 MODIFY_REG(hi2c->Instance->CR2, \
7497 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7498 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7499 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7500 }
7501
7502 /**
7503 * @brief Manage the enabling of Interrupts.
7504 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7505 * the configuration information for the specified I2C.
7506 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7507 * @retval None
7508 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7509 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7510 {
7511 uint32_t tmpisr = 0U;
7512
7513 #if defined(HAL_DMA_MODULE_ENABLED)
7514 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7515 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7516 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7517 #endif /* HAL_DMA_MODULE_ENABLED */
7518 {
7519 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7520 {
7521 /* Enable ERR, STOP, NACK, and ADDR interrupts */
7522 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7523 }
7524
7525 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7526 {
7527 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7528 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7529 }
7530
7531 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7532 {
7533 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7534 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7535 }
7536
7537 if (InterruptRequest == I2C_XFER_ERROR_IT)
7538 {
7539 /* Enable ERR and NACK interrupts */
7540 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7541 }
7542
7543 if (InterruptRequest == I2C_XFER_CPLT_IT)
7544 {
7545 /* Enable STOP interrupts */
7546 tmpisr |= I2C_IT_STOPI;
7547 }
7548 }
7549
7550 #if defined(HAL_DMA_MODULE_ENABLED)
7551 else
7552 {
7553 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7554 {
7555 /* Enable ERR, STOP, NACK and ADDR interrupts */
7556 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7557 }
7558
7559 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7560 {
7561 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7562 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7563 }
7564
7565 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7566 {
7567 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7568 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7569 }
7570
7571 if (InterruptRequest == I2C_XFER_ERROR_IT)
7572 {
7573 /* Enable ERR and NACK interrupts */
7574 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7575 }
7576
7577 if (InterruptRequest == I2C_XFER_CPLT_IT)
7578 {
7579 /* Enable STOP interrupts */
7580 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7581 }
7582
7583 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7584 {
7585 /* Enable TC interrupts */
7586 tmpisr |= I2C_IT_TCI;
7587 }
7588 }
7589 #endif /* HAL_DMA_MODULE_ENABLED */
7590
7591 /* Enable interrupts only at the end */
7592 /* to avoid the risk of I2C interrupt handle execution before */
7593 /* all interrupts requested done */
7594 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7595 }
7596
7597
7598 /**
7599 * @brief Manage the disabling of Interrupts.
7600 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7601 * the configuration information for the specified I2C.
7602 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7603 * @retval None
7604 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7605 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7606 {
7607 uint32_t tmpisr = 0U;
7608
7609 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7610 {
7611 /* Disable TC and TXI interrupts */
7612 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7613
7614 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7615 {
7616 /* Disable NACK and STOP interrupts */
7617 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7618 }
7619 }
7620
7621 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7622 {
7623 /* Disable TC and RXI interrupts */
7624 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7625
7626 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7627 {
7628 /* Disable NACK and STOP interrupts */
7629 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7630 }
7631 }
7632
7633 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7634 {
7635 /* Disable ADDR, NACK and STOP interrupts */
7636 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7637 }
7638
7639 if (InterruptRequest == I2C_XFER_ERROR_IT)
7640 {
7641 /* Enable ERR and NACK interrupts */
7642 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7643 }
7644
7645 if (InterruptRequest == I2C_XFER_CPLT_IT)
7646 {
7647 /* Enable STOP interrupts */
7648 tmpisr |= I2C_IT_STOPI;
7649 }
7650
7651 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7652 {
7653 /* Enable TC interrupts */
7654 tmpisr |= I2C_IT_TCI;
7655 }
7656
7657 /* Disable interrupts only at the end */
7658 /* to avoid a breaking situation like at "t" time */
7659 /* all disable interrupts request are not done */
7660 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7661 }
7662
7663 /**
7664 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7665 * @param hi2c I2C handle.
7666 * @retval None
7667 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7668 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7669 {
7670 /* if user set XferOptions to I2C_OTHER_FRAME */
7671 /* it request implicitly to generate a restart condition */
7672 /* set XferOptions to I2C_FIRST_FRAME */
7673 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7674 {
7675 hi2c->XferOptions = I2C_FIRST_FRAME;
7676 }
7677 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7678 /* it request implicitly to generate a restart condition */
7679 /* then generate a stop condition at the end of transfer */
7680 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7681 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7682 {
7683 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7684 }
7685 else
7686 {
7687 /* Nothing to do */
7688 }
7689 }
7690
7691 /**
7692 * @}
7693 */
7694
7695 #endif /* HAL_I2C_MODULE_ENABLED */
7696 /**
7697 * @}
7698 */
7699
7700 /**
7701 * @}
7702 */
7703
