1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H5xx_HAL_GTZC_H 22 #define STM32H5xx_HAL_GTZC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_def.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup GTZC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup GTZC_Exported_Types GTZC Exported Types 42 * @{ 43 */ 44 45 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ 46 #define GTZC_MCPBB_NB_VCTR_REG_MAX (32U) 47 #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) 48 typedef struct 49 { 50 uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for 51 a super-block. Each bit corresponds to a block 52 inside the super-block. 0 means non-secure, 53 1 means secure */ 54 uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for 55 a super-block. Each bit corresponds to a block 56 inside the super-block. 0 means non-privilege, 57 1 means privilege */ 58 uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of 59 a super-block (32 blocks). 0 means unlocked, 60 1 means locked */ 61 } MPCBB_Attribute_ConfigTypeDef; 62 63 typedef struct 64 { 65 uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access 66 field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ 67 uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). 68 It can be a value of @ref GTZC_MPCBB_InvertSecureState */ 69 MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ 70 } MPCBB_ConfigTypeDef; 71 72 typedef struct 73 { 74 uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref 75 GTZC_MPCWM_AreaId */ 76 uint32_t Offset; /*!< Offset of the watermark area, starting from the selected 77 memory base address. It must aligned on 128KB for FMC 78 and OCTOSPI memories, and on 32-byte for BKPSRAM */ 79 uint32_t Length; /*!< Length of the watermark area, starting from the selected 80 Offset. It must aligned on 128KB for FMC and OCTOSPI 81 memories, and on 32-byte for BKPSRAM */ 82 uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value 83 of @ref GTZC_MPCWM_Attribute */ 84 uint32_t Lock; /*!< Lock of the watermark area. It can be a value 85 of @ref GTZC_MPCWM_Lock */ 86 uint32_t AreaStatus; /*!< Status of the watermark area. It can be set to 87 ENABLE or DISABLE */ 88 } MPCWM_ConfigTypeDef; 89 90 /** 91 * @} 92 */ 93 94 /* Private constants ---------------------------------------------------------*/ 95 96 /** @defgroup GTZC_Private_Constants GTZC Private Constants 97 * @{ 98 */ 99 100 /** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition 101 * @{ 102 */ 103 104 /* composition definition for Peripheral identifier parameter (PeriphId) used in 105 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 106 * functions and also in all HAL_GTZC_TZIC relative functions. 107 * Bitmap Definition 108 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 109 * Each bit is dedicated to a single register. 110 * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets 111 * all peripherals within all registers. 112 * bits[4:0] Field "bit position". Define the bit position within the 113 * register dedicated to the peripheral, value from 0 to 31. 114 */ 115 #define GTZC_PERIPH_REG_SHIFT (28U) 116 #define GTZC_PERIPH_REG (0xF0000000U) 117 #define GTZC1_PERIPH_REG1 (0x00000000U) 118 #define GTZC1_PERIPH_REG2 (0x10000000U) 119 #define GTZC1_PERIPH_REG3 (0x20000000U) 120 #if defined (GTZC_TZIC1) 121 #define GTZC1_PERIPH_REG4 (0x30000000U) 122 #endif /* defined (GTZC_TZIC1) */ 123 #define GTZC_PERIPH_BIT_POSITION (0x0000001FU) 124 125 /** 126 * @} 127 */ 128 129 /** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks 130 * @{ 131 */ 132 #define GTZC_ATTR_SEC_MASK 0x100U 133 #define GTZC_ATTR_PRIV_MASK 0x200U 134 135 /** 136 * @} 137 */ 138 139 /** 140 * @} 141 */ 142 143 /* Exported constants --------------------------------------------------------*/ 144 145 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 146 * @{ 147 */ 148 149 /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values 150 * @{ 151 */ 152 153 #define GTZC_MPCBB_SRWILADIS_ENABLE (0U) 154 #define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) 155 156 /** 157 * @} 158 */ 159 160 /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values 161 * @{ 162 */ 163 164 #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) 165 #define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) 166 167 /** 168 * @} 169 */ 170 171 /** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values 172 * @{ 173 */ 174 175 #define GTZC_TZSC_MPCWM_ID1 (0U) 176 #define GTZC_TZSC_MPCWM_ID2 (1U) 177 178 /** 179 * @} 180 */ 181 182 /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values 183 * @{ 184 */ 185 #define GTZC_PERIPH_TIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) 186 #define GTZC_PERIPH_TIM3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) 187 #if defined (TIM4) 188 #define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) 189 #endif /* defined (TIM4) */ 190 #if defined (TIM5) 191 #define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos) 192 #endif /* defined (TIM5) */ 193 #define GTZC_PERIPH_TIM6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos) 194 #define GTZC_PERIPH_TIM7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos) 195 #if defined (TIM12) 196 #define GTZC_PERIPH_TIM12 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM12_Pos) 197 #endif /* defined (TIM12) */ 198 #if defined (TIM13) 199 #define GTZC_PERIPH_TIM13 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM13_Pos) 200 #endif /* defined (TIM13) */ 201 #if defined (TIM14) 202 #define GTZC_PERIPH_TIM14 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM14_Pos) 203 #endif /* defined (TIM14) */ 204 #define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) 205 #define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) 206 #define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) 207 #define GTZC_PERIPH_SPI3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) 208 #define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) 209 #define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) 210 #if defined (UART4) 211 #define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) 212 #endif /* defined (UART4) */ 213 #if defined (UART5) 214 #define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) 215 #endif /* defined (UART5) */ 216 #define GTZC_PERIPH_I2C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) 217 #define GTZC_PERIPH_I2C2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) 218 #define GTZC_PERIPH_I3C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I3C1_Pos) 219 #define GTZC_PERIPH_CRS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos) 220 #if defined (USART6) 221 #define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos) 222 #endif /* defined (USART6) */ 223 #if defined (USART10) 224 #define GTZC_PERIPH_USART10 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART10_Pos) 225 #endif /* defined (USART10) */ 226 #if defined (USART11) 227 #define GTZC_PERIPH_USART11 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART11_Pos) 228 #endif /* defined (USART11) */ 229 #if defined (CEC) 230 #define GTZC_PERIPH_HDMICEC (GTZC1_PERIPH_REG1 | GTZC_CFGR1_HDMICEC_Pos) 231 #endif /* defined (CEC) */ 232 #define GTZC_PERIPH_DAC12 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_DAC12_Pos) 233 #if defined (UART7) 234 #define GTZC_PERIPH_UART7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART7_Pos) 235 #endif /* defined (UART7) */ 236 #if defined (UART8) 237 #define GTZC_PERIPH_UART8 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART8_Pos) 238 #endif /* defined (UART8) */ 239 #if defined (UART9) 240 #define GTZC_PERIPH_UART9 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART9_Pos) 241 #endif /* defined (UART9) */ 242 #if defined (UART12) 243 #define GTZC_PERIPH_UART12 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART12_Pos) 244 #endif /* defined (UART12) */ 245 #define GTZC_PERIPH_DTS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_DTS_Pos) 246 #define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) 247 248 #define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_FDCAN1_Pos) 249 #if defined (FDCAN2) 250 #define GTZC_PERIPH_FDCAN2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_FDCAN2_Pos) 251 #endif /* defined (FDCAN2) */ 252 #if defined (UCPD1) 253 #define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_UCPD1_Pos) 254 #endif /* defined (UCPD1) */ 255 #if defined (OPAMP1) 256 #define GTZC_PERIPH_OPAMP (GTZC1_PERIPH_REG2 | GTZC_CFGR2_OPAMP_Pos) 257 #endif /* defined (OPAMP1) */ 258 #if defined (COMP1) 259 #define GTZC_PERIPH_COMP (GTZC1_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos) 260 #endif /* defined (COMP1) */ 261 #define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) 262 #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) 263 #if defined (TIM8) 264 #define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) 265 #endif /* defined (TIM8) */ 266 #define GTZC_PERIPH_USART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) 267 #if defined (TIM15) 268 #define GTZC_PERIPH_TIM15 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos) 269 #endif /* defined (TIM15) */ 270 #if defined (TIM16) 271 #define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) 272 #endif /* defined (TIM16) */ 273 #if defined (TIM17) 274 #define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) 275 #endif /* defined (TIM17) */ 276 #if defined (SPI4) 277 #define GTZC_PERIPH_SPI4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI4_Pos) 278 #endif /* defined (SPI4) */ 279 #if defined (SPI6) 280 #define GTZC_PERIPH_SPI6 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI6_Pos) 281 #endif /* defined (SPI6) */ 282 #if defined (SAI1) 283 #define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) 284 #endif /* defined (SAI1) */ 285 #if defined (SAI2) 286 #define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) 287 #endif /* defined (SAI2) */ 288 #define GTZC_PERIPH_USB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USB_Pos) 289 #if defined (SPI5) 290 #define GTZC_PERIPH_SPI5 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI5_Pos) 291 #endif /* defined (SPI5) */ 292 #define GTZC_PERIPH_LPUART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos) 293 #if defined (I2C3) 294 #define GTZC_PERIPH_I2C3 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos) 295 #endif /* defined (I2C3) */ 296 #if defined (I2C4) 297 #define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_I2C4_Pos) 298 #endif /* defined (I2C4) */ 299 #define GTZC_PERIPH_LPTIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos) 300 #if defined (LPTIM3) 301 #define GTZC_PERIPH_LPTIM3 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM3_Pos) 302 #endif /* defined (LPTIM3) */ 303 #if defined (LPTIM4) 304 #define GTZC_PERIPH_LPTIM4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM4_Pos) 305 #endif /* defined (LPTIM4) */ 306 #if defined (LPTIM5) 307 #define GTZC_PERIPH_LPTIM5 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM5_Pos) 308 #endif /* defined (LPTIM5) */ 309 310 #if defined (LPTIM6) 311 #define GTZC_PERIPH_LPTIM6 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_LPTIM6_Pos) 312 #endif /* defined (LPTIM6) */ 313 #define GTZC_PERIPH_VREFBUF (GTZC1_PERIPH_REG3 | GTZC_CFGR3_VREFBUF_Pos) 314 #if defined (I3C2) 315 #define GTZC_PERIPH_I3C2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_I3C2_Pos) 316 #endif /* defined (I3C2) */ 317 #define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) 318 #if defined (CORDIC) 319 #define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos) 320 #endif /* defined (CORDIC) */ 321 #if defined (FMAC) 322 #define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos) 323 #endif /* defined (FMAC) */ 324 #if defined (ETH) 325 #define GTZC_PERIPH_ETHERNET (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ETHERNET_Pos) 326 #endif /* defined (ETH) */ 327 #define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) 328 #if defined (DCACHE1) 329 #define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos) 330 #endif /* defined (DCACHE1) */ 331 #define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) 332 #if defined (DCMI) 333 #define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_PSSI_Pos) 334 #endif /* defined (DCMI) */ 335 #if defined (AES) 336 #define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) 337 #endif /* defined (AES) */ 338 #if defined (HASH) 339 #define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) 340 #endif /* defined (HASH) */ 341 #define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) 342 #if defined (PKA) 343 #define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) 344 #endif /* defined (PKA) */ 345 #if defined (SAES) 346 #define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) 347 #endif /* defined (SAES) */ 348 #if defined (SDMMC1) 349 #define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos) 350 #endif /* defined (SDMMC1) */ 351 #if defined (SDMMC2) 352 #define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos) 353 #endif /* defined (SDMMC2) */ 354 #if defined (FMC_Bank1_R) 355 #define GTZC_PERIPH_FMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMC_REG_Pos) 356 #endif /* defined (FMC_Bank1_R) */ 357 #if defined (OCTOSPI1) 358 #define GTZC_PERIPH_OCTOSPI1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_Pos) 359 #endif /* defined (OCTOSPI1) */ 360 #define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) 361 362 #if defined (GTZC_TZIC1) 363 #define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) 364 #define GTZC_PERIPH_GPDMA2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA2_Pos) 365 #define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) 366 #define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) 367 #define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos) 368 #define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) 369 #define GTZC_PERIPH_SBS (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SBS_Pos) 370 #define GTZC_PERIPH_RTC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos) 371 #define GTZC_PERIPH_TAMP (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TAMP_Pos) 372 #define GTZC_PERIPH_PWR (GTZC1_PERIPH_REG4 | GTZC_CFGR4_PWR_Pos) 373 #define GTZC_PERIPH_RCC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_RCC_Pos) 374 #define GTZC_PERIPH_EXTI (GTZC1_PERIPH_REG4 | GTZC_CFGR4_EXTI_Pos) 375 #define GTZC_PERIPH_TZSC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC_Pos) 376 #define GTZC_PERIPH_TZIC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC_Pos) 377 #define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos) 378 #define GTZC_PERIPH_FMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FMC_MEM_Pos) 379 #define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos) 380 #define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) 381 #define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) 382 #define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) 383 #define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) 384 #define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos) 385 #define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos) 386 #endif /* defined (GTZC_TZIC1) */ 387 388 #define GTZC_PERIPH_ALL (0x00000020U) 389 390 /* Note that two maximum values are also defined here: 391 * - max number of securable AHB/APB peripherals or masters 392 * (used in TZSC sub-block) 393 * - max number of securable and TrustZone-aware AHB/APB peripherals or masters 394 * (used in TZIC sub-block) 395 */ 396 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_RAMCFG + 1U)) 397 #if defined (GTZC_TZIC1) 398 #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB3_REG + 1U)) 399 #endif /* defined (GTZC_TZIC1) */ 400 401 /** 402 * @} 403 */ 404 405 /** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values 406 * @note secure and non-secure attributes are only available from secure state when the system 407 * implement the security (TZEN=1) 408 * @{ 409 */ 410 411 /* user-oriented definitions for attribute parameter (PeriphAttributes) used in 412 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 413 * functions 414 */ 415 #if defined (GTZC_TZIC1) 416 #define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 417 #define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 418 #endif /* (GTZC_TZIC1) */ 419 #define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 420 #define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 421 422 /** 423 * @} 424 */ 425 426 #if defined (GTZC_TZSC_CR_LCK_Msk) 427 /** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values 428 * @{ 429 */ 430 431 /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ 432 #define GTZC_TZSC_LOCK_OFF (0U) 433 #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk 434 435 /** 436 * @} 437 */ 438 #endif /* (GTZC_TZSC_CR_LCK_Msk) */ 439 440 /** @defgroup GTZC_MPCWM_Group GTZC MPCWM values 441 * @{ 442 */ 443 444 /* user-oriented definitions for TZSC_MPCWM */ 445 #define GTZC_TZSC_MPCWM_GRANULARITY_1 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */ 446 #define GTZC_TZSC_MPCWM_GRANULARITY_2 0x00000020U /* BKPSRAM granularity: 32 bytes */ 447 448 /** 449 * @} 450 */ 451 452 /** @defgroup GTZC_MPCWM_Lock GTZC MPCWM Lock values 453 * @{ 454 */ 455 456 /* user-oriented definitions for TZSC_MPCWM */ 457 #define GTZC_TZSC_MPCWM_LOCK_OFF (0U) 458 #define GTZC_TZSC_MPCWM_LOCK_ON GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk 459 460 /** 461 * @} 462 */ 463 464 /** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values 465 * @{ 466 */ 467 468 /* user-oriented definitions for TZSC_MPCWM */ 469 #define GTZC_TZSC_MPCWM_REGION_NSEC (0U) 470 #define GTZC_TZSC_MPCWM_REGION_SEC (1U) 471 #define GTZC_TZSC_MPCWM_REGION_NPRIV (0U) 472 #define GTZC_TZSC_MPCWM_REGION_PRIV (2U) 473 474 /** 475 * @} 476 */ 477 478 /** @defgroup GTZC_MPCBB_Group GTZC MPCBB values 479 * @{ 480 */ 481 482 /* user-oriented definitions for MPCBB */ 483 #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ 484 #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ 485 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) 486 #define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) 487 488 #define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) 489 #define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) 490 #define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) 491 #define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) 492 493 /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ 494 #define GTZC_MCPBB_LOCK_OFF (0U) 495 #define GTZC_MCPBB_LOCK_ON (1U) 496 497 /** 498 * @} 499 */ 500 501 /** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values 502 * @{ 503 */ 504 505 /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ 506 #define GTZC_TZIC_NO_ILA_EVENT (0U) 507 #define GTZC_TZIC_ILA_EVENT_PENDING (1U) 508 509 /** 510 * @} 511 */ 512 513 /** 514 * @} 515 */ 516 517 /* Private macros ------------------------------------------------------------*/ 518 519 /** @defgroup GTZC_Private_Macros GTZC Private Macros 520 * @{ 521 */ 522 523 /* retrieve information to access register for a specific PeriphId */ 524 #define GTZC_GET_REG_INDEX(periph_id)\ 525 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) 526 527 #define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) 528 529 #if defined (GTZC_TZIC1) 530 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 531 ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ 532 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) 533 #else 534 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 535 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) 536 #endif /* defined (GTZC_TZIC1) */ 537 538 #define GTZC_MEM_SIZE(mem)\ 539 ( mem ## _SIZE ) 540 541 #if defined (GTZC_TZIC1) 542 #define GTZC_BASE_ADDRESS_S(mem)\ 543 ( mem ## _BASE_S ) 544 #endif /* defined (GTZC_TZIC1) */ 545 546 #define GTZC_BASE_ADDRESS_NS(mem)\ 547 ( mem ## _BASE_NS ) 548 549 /** 550 * @} 551 */ 552 553 /* Exported macros -----------------------------------------------------------*/ 554 555 /** @defgroup GTZC_Exported_Macros GTZC Exported Macros 556 * @{ 557 */ 558 559 /* user-oriented macro to get array index of a specific PeriphId 560 * in case of GTZC_PERIPH_ALL usage in the two following functions: 561 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 562 */ 563 #define HAL_GTZC_GET_ARRAY_INDEX(periph_id)\ 564 ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) 565 566 /** 567 * @} 568 */ 569 570 /* Exported functions --------------------------------------------------------*/ 571 572 /** @addtogroup GTZC_Exported_Functions 573 * @{ 574 */ 575 576 /** @addtogroup GTZC_Exported_Functions_Group1 577 * @brief TZSC Initialization and Configuration functions 578 * @{ 579 */ 580 581 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, 582 uint32_t PeriphAttributes); 583 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, 584 uint32_t *PeriphAttributes); 585 586 /** 587 * @} 588 */ 589 590 /** @addtogroup GTZC_Exported_Functions_Group2 591 * @brief MPCWM Initialization and Configuration functions 592 * @{ 593 */ 594 595 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, 596 const MPCWM_ConfigTypeDef *pMPCWM_Desc); 597 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, 598 MPCWM_ConfigTypeDef *pMPCWM_Desc); 599 /** 600 * @} 601 */ 602 603 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 604 605 /** @addtogroup GTZC_Exported_Functions_Group3 606 * @brief TZSC and TZSC-MPCWM Lock functions 607 * @{ 608 */ 609 610 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); 611 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); 612 613 /** 614 * @} 615 */ 616 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 617 /** @addtogroup GTZC_Exported_Functions_Group4 618 * @brief MPCBB Initialization and Configuration functions 619 * @{ 620 */ 621 622 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, 623 const MPCBB_ConfigTypeDef *pMPCBB_desc); 624 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, 625 MPCBB_ConfigTypeDef *pMPCBB_desc); 626 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, 627 uint32_t NbBlocks, 628 const uint32_t *pMemAttributes); 629 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, 630 uint32_t NbBlocks, 631 uint32_t *pMemAttributes); 632 633 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 634 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, 635 uint32_t NbSuperBlocks, 636 const uint32_t *pLockAttributes); 637 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, 638 uint32_t NbSuperBlocks, 639 uint32_t *pLockAttributes); 640 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); 641 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, 642 uint32_t *pLockState); 643 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 644 645 /** 646 * @} 647 */ 648 649 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 650 651 /** @addtogroup GTZC_Exported_Functions_Group5 652 * @brief TZIC functions 653 * @{ 654 */ 655 656 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 657 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 658 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); 659 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 660 661 /** 662 * @} 663 */ 664 665 /** @addtogroup GTZC_Exported_Functions_Group6 666 * @brief IRQ related Functions 667 * @{ 668 */ 669 670 void HAL_GTZC_IRQHandler(void); 671 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 672 673 /** 674 * @} 675 */ 676 677 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 678 679 /** 680 * @} 681 */ 682 683 /** 684 * @} 685 */ 686 687 /** 688 * @} 689 */ 690 691 #ifdef __cplusplus 692 } 693 #endif 694 695 #endif /* STM32H5xx_HAL_GTZC_H */ 696 697
