1 /** 2 ********************************************************************************************************************** 3 * @file stm32h5xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 21 #ifndef STM32H5xx_HAL_DMA_H 22 #define STM32H5xx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ----------------------------------------------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_def.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 40 /* Exported types ----------------------------------------------------------------------------------------------------*/ 41 42 /** @defgroup DMA_Exported_Types DMA Exported Types 43 * @brief DMA Exported Types 44 * @{ 45 */ 46 47 /** 48 * @brief DMA Transfer Configuration Structure definition. 49 */ 50 typedef struct 51 { 52 uint32_t Request; /*!< Specifies the DMA channel request. 53 This parameter can be a value of @ref DMA_Request_Selection */ 54 55 uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. 56 Block Hardware request feature can be used only with dedicated peripherals. 57 This parameter can be a value of @ref DMA_Block_Request */ 58 59 uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. 60 This parameter can be a value of @ref DMA_Transfer_Direction */ 61 62 uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. 63 This parameter can be a value of @ref DMA_Source_Increment_Mode */ 64 65 uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. 66 This parameter can be a value of @ref DMA_Destination_Increment_Mode */ 67 68 uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. 69 This parameter can be a value of @ref DMA_Source_Data_Width */ 70 71 uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. 72 This parameter can be a value of @ref DMA_Destination_Data_Width */ 73 74 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 75 This parameter can be a value of @ref DMA_Priority_Level */ 76 77 uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA 78 channel. 79 This parameter can be a value between 1 and 64 */ 80 81 uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the 82 DMA channel. 83 This parameter can be a value between 1 and 64 */ 84 85 uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. 86 This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ 87 88 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 89 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 90 91 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. 92 This parameter can be a value of @ref DMA_Transfer_Mode */ 93 94 } DMA_InitTypeDef; 95 96 /** 97 * @brief DMA Linked-List Configuration Structure Definition. 98 */ 99 typedef struct 100 { 101 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 102 This parameter can be a value of @ref DMA_Priority_Level */ 103 104 uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. 105 This parameter can be a value of @ref DMAEx_Link_Step_Mode */ 106 107 uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. 108 This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ 109 110 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 111 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 112 113 uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. 114 This parameter can be a value of @ref DMAEx_LinkedList_Mode */ 115 116 } DMA_InitLinkedListTypeDef; 117 118 /** 119 * @brief HAL DMA State Enumeration Definition. 120 */ 121 typedef enum 122 { 123 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 124 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 125 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 126 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 127 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 128 HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ 129 130 } HAL_DMA_StateTypeDef; 131 132 /** 133 * @brief HAL DMA Level Complete Enumeration Definition. 134 */ 135 typedef enum 136 { 137 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ 138 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ 139 140 } HAL_DMA_LevelCompleteTypeDef; 141 142 /** 143 * @brief HAL DMA Callbacks IDs Enumeration Definition. 144 */ 145 typedef enum 146 { 147 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ 148 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ 149 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ 150 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ 151 HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ 152 HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ 153 154 } HAL_DMA_CallbackIDTypeDef; 155 156 /** 157 * @brief DMA handle Structure definition 158 */ 159 typedef struct __DMA_HandleTypeDef 160 { 161 DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ 162 163 DMA_InitTypeDef Init; /*!< DMA channel init parameters */ 164 165 DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ 166 167 HAL_LockTypeDef Lock; /*!< DMA locking object */ 168 169 uint32_t Mode; /*!< DMA transfer mode */ 170 171 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 172 173 __IO uint32_t ErrorCode; /*!< DMA error code */ 174 175 void *Parent; /*!< Parent object state */ 176 177 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 178 179 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ 180 181 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 182 183 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ 184 185 void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ 186 187 struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ 188 189 } DMA_HandleTypeDef; 190 /** 191 * @} 192 */ 193 194 195 /* Exported constants ------------------------------------------------------------------------------------------------*/ 196 /** @defgroup DMA_Exported_Constants DMA Exported Constants 197 * @brief DMA Exported constants 198 * @{ 199 */ 200 201 /** @defgroup DMA_Error_Codes DMA Error Codes 202 * @brief DMA Error Codes 203 * @{ 204 */ 205 #define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ 206 #define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ 207 #define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ 208 #define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ 209 #define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ 210 #define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ 211 #define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ 212 #define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ 213 #define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ 214 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition 220 * @brief DMA Interrupt Enable Definition 221 * @{ 222 */ 223 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ 224 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ 225 #define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ 226 #define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ 227 #define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ 228 #define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ 229 #define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup DMA_Flag_Definition DMA Flag Definition 235 * @brief DMA Flag Definition 236 * @{ 237 */ 238 #define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ 239 #define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ 240 #define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ 241 #define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ 242 #define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ 243 #define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ 244 #define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ 245 #define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup DMA_Request_Selection DMA Request Selection 251 * @brief DMA Request Selection 252 * @{ 253 */ 254 /* GPDMA1 requests */ 255 #define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ 256 #if defined (ADC2) 257 #define GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */ 258 #endif /* ADC2 */ 259 #define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH */ 260 #define GPDMA1_REQUEST_DAC2_CH2 3U /*!< GPDMA1 HW request is DAC2_CH */ 261 #define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ 262 #define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ 263 #define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ 264 #define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ 265 #define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ 266 #define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ 267 #define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ 268 #define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ 269 #define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ 270 #define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ 271 #define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ 272 #define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ 273 #if defined (I2C3) 274 #define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ 275 #define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ 276 #endif /* I2C3 */ 277 #define GPDMA1_REQUEST_USART1_RX 21U /*!< GPDMA1 HW request is USART1_RX */ 278 #define GPDMA1_REQUEST_USART1_TX 22U /*!< GPDMA1 HW request is USART1_TX */ 279 #define GPDMA1_REQUEST_USART2_RX 23U /*!< GPDMA1 HW request is USART2_RX */ 280 #define GPDMA1_REQUEST_USART2_TX 24U /*!< GPDMA1 HW request is USART2_TX */ 281 #define GPDMA1_REQUEST_USART3_RX 25U /*!< GPDMA1 HW request is USART3_RX */ 282 #define GPDMA1_REQUEST_USART3_TX 26U /*!< GPDMA1 HW request is USART3_TX */ 283 #if defined (UART4) 284 #define GPDMA1_REQUEST_UART4_RX 27U /*!< GPDMA1 HW request is UART4_RX */ 285 #define GPDMA1_REQUEST_UART4_TX 28U /*!< GPDMA1 HW request is UART4_TX */ 286 #endif /* UART4 */ 287 #if defined (UART4) 288 #define GPDMA1_REQUEST_UART5_RX 29U /*!< GPDMA1 HW request is UART5_RX */ 289 #define GPDMA1_REQUEST_UART5_TX 30U /*!< GPDMA1 HW request is UART5_TX */ 290 #endif /* UART5 */ 291 #if defined (UART4) 292 #define GPDMA1_REQUEST_USART6_RX 31U /*!< GPDMA1 HW request is USART6_RX */ 293 #define GPDMA1_REQUEST_USART6_TX 32U /*!< GPDMA1 HW request is USART6_TX */ 294 #endif /* USART6 */ 295 #if defined (UART7) 296 #define GPDMA1_REQUEST_UART7_RX 33U /*!< GPDMA1 HW request is UART7_RX */ 297 #define GPDMA1_REQUEST_UART7_TX 34U /*!< GPDMA1 HW request is UART7_TX */ 298 #endif /* UART7 */ 299 #if defined (UART8) 300 #define GPDMA1_REQUEST_UART8_RX 35U /*!< GPDMA1 HW request is UART8_RX */ 301 #define GPDMA1_REQUEST_UART8_TX 36U /*!< GPDMA1 HW request is UART8_TX */ 302 #endif /* UART8 */ 303 #if defined (UART9) 304 #define GPDMA1_REQUEST_UART9_RX 37U /*!< GPDMA1 HW request is UART9_RX */ 305 #define GPDMA1_REQUEST_UART9_TX 38U /*!< GPDMA1 HW request is UART9_TX */ 306 #endif /* UART9 */ 307 #if defined (USART10) 308 #define GPDMA1_REQUEST_USART10_RX 39U /*!< GPDMA1 HW request is USART10_RX */ 309 #define GPDMA1_REQUEST_USART10_TX 40U /*!< GPDMA1 HW request is USART10_TX */ 310 #endif /* USART10 */ 311 #if defined (USART11) 312 #define GPDMA1_REQUEST_USART11_RX 41U /*!< GPDMA1 HW request is USART11_RX */ 313 #define GPDMA1_REQUEST_USART11_TX 42U /*!< GPDMA1 HW request is USART11_TX */ 314 #endif /* USART11 */ 315 #if defined (UART12) 316 #define GPDMA1_REQUEST_UART12_RX 43U /*!< GPDMA1 HW request is UART12_RX */ 317 #define GPDMA1_REQUEST_UART12_TX 44U /*!< GPDMA1 HW request is UART12_TX */ 318 #endif /* UART12 */ 319 #define GPDMA1_REQUEST_LPUART1_RX 45U /*!< GPDMA1 HW request is LPUART1_RX */ 320 #define GPDMA1_REQUEST_LPUART1_TX 46U /*!< GPDMA1 HW request is LPUART1_TX */ 321 #if defined (SPI4) 322 #define GPDMA1_REQUEST_SPI4_RX 47U /*!< GPDMA1 HW request is SPI4_RX */ 323 #define GPDMA1_REQUEST_SPI4_TX 48U /*!< GPDMA1 HW request is SPI4_TX */ 324 #endif /* SPI4 */ 325 #if defined (SPI5) 326 #define GPDMA1_REQUEST_SPI5_RX 49U /*!< GPDMA1 HW request is SPI5_RX */ 327 #define GPDMA1_REQUEST_SPI5_TX 50U /*!< GPDMA1 HW request is SPI5_TX */ 328 #endif /* SPI5 */ 329 #if defined (SPI6) 330 #define GPDMA1_REQUEST_SPI6_RX 51U /*!< GPDMA1 HW request is SPI6_RX */ 331 #define GPDMA1_REQUEST_SPI6_TX 52U /*!< GPDMA1 HW request is SPI6_TX */ 332 #endif /* SPI6 */ 333 #if defined (SAI1) 334 #define GPDMA1_REQUEST_SAI1_A 53U /*!< GPDMA1 HW request is SAI1_A */ 335 #define GPDMA1_REQUEST_SAI1_B 54U /*!< GPDMA1 HW request is SAI1_B */ 336 #endif /* SAI1 */ 337 #if defined (SAI2) 338 #define GPDMA1_REQUEST_SAI2_A 55U /*!< GPDMA1 HW request is SAI2_A */ 339 #define GPDMA1_REQUEST_SAI2_B 56U /*!< GPDMA1 HW request is SAI2_B */ 340 #endif /* SAI2 */ 341 #if defined (OCTOSPI1) 342 #define GPDMA1_REQUEST_OCTOSPI1 57U /*!< GPDMA1 HW request is OCTOSPI1 */ 343 #endif /* OCTOSPI1 */ 344 #define GPDMA1_REQUEST_TIM1_CH1 58U /*!< GPDMA1 HW request is TIM1_CH1 */ 345 #define GPDMA1_REQUEST_TIM1_CH2 59U /*!< GPDMA1 HW request is TIM1_CH2 */ 346 #define GPDMA1_REQUEST_TIM1_CH3 60U /*!< GPDMA1 HW request is TIM1_CH3 */ 347 #define GPDMA1_REQUEST_TIM1_CH4 61U /*!< GPDMA1 HW request is TIM1_CH4 */ 348 #define GPDMA1_REQUEST_TIM1_UP 62U /*!< GPDMA1 HW request is TIM1_UP */ 349 #define GPDMA1_REQUEST_TIM1_TRIG 63U /*!< GPDMA1 HW request is TIM1_TRIG */ 350 #define GPDMA1_REQUEST_TIM1_COM 64U /*!< GPDMA1 HW request is TIM1_COM */ 351 #if defined (TIM8) 352 #define GPDMA1_REQUEST_TIM8_CH1 65U /*!< GPDMA1 HW request is TIM8_CH1 */ 353 #define GPDMA1_REQUEST_TIM8_CH2 66U /*!< GPDMA1 HW request is TIM8_CH2 */ 354 #define GPDMA1_REQUEST_TIM8_CH3 67U /*!< GPDMA1 HW request is TIM8_CH3 */ 355 #define GPDMA1_REQUEST_TIM8_CH4 68U /*!< GPDMA1 HW request is TIM8_CH4 */ 356 #define GPDMA1_REQUEST_TIM8_UP 69U /*!< GPDMA1 HW request is TIM8_UP */ 357 #define GPDMA1_REQUEST_TIM8_TRIG 70U /*!< GPDMA1 HW request is TIM8_TRIG */ 358 #define GPDMA1_REQUEST_TIM8_COM 71U /*!< GPDMA1 HW request is TIM8_COM */ 359 #endif /* TIM8 */ 360 #define GPDMA1_REQUEST_TIM2_CH1 72U /*!< GPDMA1 HW request is TIM2_CH1 */ 361 #define GPDMA1_REQUEST_TIM2_CH2 73U /*!< GPDMA1 HW request is TIM2_CH2 */ 362 #define GPDMA1_REQUEST_TIM2_CH3 74U /*!< GPDMA1 HW request is TIM2_CH3 */ 363 #define GPDMA1_REQUEST_TIM2_CH4 75U /*!< GPDMA1 HW request is TIM2_CH4 */ 364 #define GPDMA1_REQUEST_TIM2_UP 76U /*!< GPDMA1 HW request is TIM2_UP */ 365 #define GPDMA1_REQUEST_TIM3_CH1 77U /*!< GPDMA1 HW request is TIM3_CH1 */ 366 #define GPDMA1_REQUEST_TIM3_CH2 78U /*!< GPDMA1 HW request is TIM3_CH2 */ 367 #define GPDMA1_REQUEST_TIM3_CH3 79U /*!< GPDMA1 HW request is TIM3_CH3 */ 368 #define GPDMA1_REQUEST_TIM3_CH4 80U /*!< GPDMA1 HW request is TIM3_CH4 */ 369 #define GPDMA1_REQUEST_TIM3_UP 81U /*!< GPDMA1 HW request is TIM3_UP */ 370 #define GPDMA1_REQUEST_TIM3_TRIG 82U /*!< GPDMA1 HW request is TIM3_TRIG */ 371 #if defined (TIM4) 372 #define GPDMA1_REQUEST_TIM4_CH1 83U /*!< GPDMA1 HW request is TIM4_CH1 */ 373 #define GPDMA1_REQUEST_TIM4_CH2 84U /*!< GPDMA1 HW request is TIM4_CH2 */ 374 #define GPDMA1_REQUEST_TIM4_CH3 85U /*!< GPDMA1 HW request is TIM4_CH3 */ 375 #define GPDMA1_REQUEST_TIM4_CH4 86U /*!< GPDMA1 HW request is TIM4_CH4 */ 376 #define GPDMA1_REQUEST_TIM4_UP 87U /*!< GPDMA1 HW request is TIM4_UP */ 377 #endif /* TIM4 */ 378 #if defined (TIM5) 379 #define GPDMA1_REQUEST_TIM5_CH1 88U /*!< GPDMA1 HW request is TIM5_CH1 */ 380 #define GPDMA1_REQUEST_TIM5_CH2 89U /*!< GPDMA1 HW request is TIM5_CH2 */ 381 #define GPDMA1_REQUEST_TIM5_CH3 90U /*!< GPDMA1 HW request is TIM5_CH3 */ 382 #define GPDMA1_REQUEST_TIM5_CH4 91U /*!< GPDMA1 HW request is TIM5_CH4 */ 383 #define GPDMA1_REQUEST_TIM5_UP 92U /*!< GPDMA1 HW request is TIM5_UP */ 384 #define GPDMA1_REQUEST_TIM5_TRIG 93U /*!< GPDMA1 HW request is TIM5_TRIG */ 385 #endif /* TIM5 */ 386 #if defined (TIM15) 387 #define GPDMA1_REQUEST_TIM15_CH1 94U /*!< GPDMA1 HW request is TIM15_CH1 */ 388 #define GPDMA1_REQUEST_TIM15_UP 95U /*!< GPDMA1 HW request is TIM15_UP */ 389 #define GPDMA1_REQUEST_TIM15_TRIG 96U /*!< GPDMA1 HW request is TIM15_TRIG */ 390 #define GPDMA1_REQUEST_TIM15_COM 97U /*!< GPDMA1 HW request is TIM15_COM */ 391 #endif /* TIM15 */ 392 #if defined (TIM16) 393 #define GPDMA1_REQUEST_TIM16_CH1 98U /*!< GPDMA1 HW request is TIM16_CH1 */ 394 #define GPDMA1_REQUEST_TIM16_UP 99U /*!< GPDMA1 HW request is TIM16_UP */ 395 #endif /* TIM16 */ 396 #if defined (TIM17) 397 #define GPDMA1_REQUEST_TIM17_CH1 100U /*!< GPDMA1 HW request is TIM17_CH1 */ 398 #define GPDMA1_REQUEST_TIM17_UP 101U /*!< GPDMA1 HW request is TIM17_UP */ 399 #endif /* TIM17 */ 400 #define GPDMA1_REQUEST_LPTIM1_IC1 102U /*!< GPDMA1 HW request is LPTIM1_IC1 */ 401 #define GPDMA1_REQUEST_LPTIM1_IC2 103U /*!< GPDMA1 HW request is LPTIM1_IC2 */ 402 #define GPDMA1_REQUEST_LPTIM1_UE 104U /*!< GPDMA1 HW request is LPTIM1_UE */ 403 #define GPDMA1_REQUEST_LPTIM2_IC1 105U /*!< GPDMA1 HW request is LPTIM2_IC1 */ 404 #define GPDMA1_REQUEST_LPTIM2_IC2 106U /*!< GPDMA1 HW request is LPTIM2_IC2 */ 405 #define GPDMA1_REQUEST_LPTIM2_UE 107U /*!< GPDMA1 HW request is LPTIM2_UE */ 406 #if defined (DCMI) 407 #define GPDMA1_REQUEST_DCMI 108U /*!< GPDMA1 HW request is DCMI */ 408 #endif /* DCMI */ 409 #if defined (AES) 410 #define GPDMA1_REQUEST_AES_OUT 109U /*!< GPDMA1 HW request is AES_OUT */ 411 #define GPDMA1_REQUEST_AES_IN 110U /*!< GPDMA1 HW request is AES_IN */ 412 #endif /* AES */ 413 #define GPDMA1_REQUEST_HASH_IN 111U /*!< GPDMA1 HW request is HASH_IN */ 414 #if defined (UCPD1) 415 #define GPDMA1_REQUEST_UCPD1_RX 112U /*!< GPDMA1 HW request is UCPD1_RX */ 416 #define GPDMA1_REQUEST_UCPD1_TX 113U /*!< GPDMA1 HW request is UCPD1_TX */ 417 #endif /* UCPD1 */ 418 #if defined (CORDIC) 419 #define GPDMA1_REQUEST_CORDIC_READ 114U /*!< GPDMA1 HW request is CORDIC_READ */ 420 #define GPDMA1_REQUEST_CORDIC_WRITE 115U /*!< GPDMA1 HW request is CORDIC_WRITE */ 421 #endif /* CORDIC */ 422 #if defined (FMAC) 423 #define GPDMA1_REQUEST_FMAC_READ 116U /*!< GPDMA1 HW request is FMAC_READ */ 424 #define GPDMA1_REQUEST_FMAC_WRITE 117U /*!< GPDMA1 HW request is FMAC_WRITE */ 425 #endif /* FMAC */ 426 #if defined (SAES) 427 #define GPDMA1_REQUEST_SAES_OUT 118U /*!< GPDMA1 HW request is SAES_OUT */ 428 #define GPDMA1_REQUEST_SAES_IN 119U /*!< GPDMA1 HW request is SAES_IN */ 429 #endif /* SAES */ 430 #define GPDMA1_REQUEST_I3C1_RX 120U /*!< GPDMA1 HW request is I3C1_RX */ 431 #define GPDMA1_REQUEST_I3C1_TX 121U /*!< GPDMA1 HW request is I3C1_TX */ 432 #define GPDMA1_REQUEST_I3C1_TC 122U /*!< GPDMA1 HW request is I3C1_TC */ 433 #define GPDMA1_REQUEST_I3C1_RS 123U /*!< GPDMA1 HW request is I3C1_RS */ 434 #if defined (I2C4) 435 #define GPDMA1_REQUEST_I2C4_RX 124U /*!< GPDMA1 HW request is I2C4_RX */ 436 #define GPDMA1_REQUEST_I2C4_TX 125U /*!< GPDMA1 HW request is I2C4_TX */ 437 #endif /* I2C4 */ 438 #if defined (LPTIM3) 439 #define GPDMA1_REQUEST_LPTIM3_IC1 127U /*!< GPDMA1 HW request is LPTIM3_IC1 */ 440 #define GPDMA1_REQUEST_LPTIM3_IC2 128U /*!< GPDMA1 HW request is LPTIM3_IC2 */ 441 #define GPDMA1_REQUEST_LPTIM3_UE 129U /*!< GPDMA1 HW request is LPTIM3_UE */ 442 #endif /* LPTIM3 */ 443 #if defined (LPTIM5) 444 #define GPDMA1_REQUEST_LPTIM5_IC1 130U /*!< GPDMA1 HW request is LPTIM5_IC1 */ 445 #define GPDMA1_REQUEST_LPTIM5_IC2 131U /*!< GPDMA1 HW request is LPTIM5_IC2 */ 446 #define GPDMA1_REQUEST_LPTIM5_UE 132U /*!< GPDMA1 HW request is LPTIM5_UE */ 447 #endif /* LPTIM5 */ 448 #if defined (LPTIM6) 449 #define GPDMA1_REQUEST_LPTIM6_IC1 133U /*!< GPDMA1 HW request is LPTIM6_IC1 */ 450 #define GPDMA1_REQUEST_LPTIM6_IC2 134U /*!< GPDMA1 HW request is LPTIM6_IC2 */ 451 #define GPDMA1_REQUEST_LPTIM6_UE 135U /*!< GPDMA1 HW request is LPTIM6_UE */ 452 #endif /* LPTIM6 */ 453 #if defined (I3C2) 454 #define GPDMA1_REQUEST_I3C2_RX 136U /*!< GPDMA1 HW request is I3C2_RX */ 455 #define GPDMA1_REQUEST_I3C2_TX 137U /*!< GPDMA1 HW request is I3C2_TX */ 456 #define GPDMA1_REQUEST_I3C2_TC 138U /*!< GPDMA1 HW request is I3C2_TC */ 457 #define GPDMA1_REQUEST_I3C2_RS 139U /*!< GPDMA1 HW request is I3C2_RS */ 458 #endif /* I3C2 */ 459 460 /* GPDMA2 requests */ 461 #define GPDMA2_REQUEST_ADC1 0U /*!< GPDMA2 HW request is ADC1 */ 462 #if defined (ADC2) 463 #define GPDMA2_REQUEST_ADC2 1U /*!< GPDMA2 HW request is ADC2 */ 464 #endif /* ADC2 */ 465 #define GPDMA2_REQUEST_DAC1_CH1 2U /*!< GPDMA2 HW request is DAC1_CH */ 466 #define GPDMA2_REQUEST_DAC2_CH2 3U /*!< GPDMA2 HW request is DAC2_CH */ 467 #define GPDMA2_REQUEST_TIM6_UP 4U /*!< GPDMA2 HW request is TIM6_UP */ 468 #define GPDMA2_REQUEST_TIM7_UP 5U /*!< GPDMA2 HW request is TIM7_UP */ 469 #define GPDMA2_REQUEST_SPI1_RX 6U /*!< GPDMA2 HW request is SPI1_RX */ 470 #define GPDMA2_REQUEST_SPI1_TX 7U /*!< GPDMA2 HW request is SPI1_TX */ 471 #define GPDMA2_REQUEST_SPI2_RX 8U /*!< GPDMA2 HW request is SPI2_RX */ 472 #define GPDMA2_REQUEST_SPI2_TX 9U /*!< GPDMA2 HW request is SPI2_TX */ 473 #define GPDMA2_REQUEST_SPI3_RX 10U /*!< GPDMA2 HW request is SPI3_RX */ 474 #define GPDMA2_REQUEST_SPI3_TX 11U /*!< GPDMA2 HW request is SPI3_TX */ 475 #define GPDMA2_REQUEST_I2C1_RX 12U /*!< GPDMA2 HW request is I2C1_RX */ 476 #define GPDMA2_REQUEST_I2C1_TX 13U /*!< GPDMA2 HW request is I2C1_TX */ 477 #define GPDMA2_REQUEST_I2C2_RX 15U /*!< GPDMA2 HW request is I2C2_RX */ 478 #define GPDMA2_REQUEST_I2C2_TX 16U /*!< GPDMA2 HW request is I2C2_TX */ 479 #if defined (I2C3) 480 #define GPDMA2_REQUEST_I2C3_RX 18U /*!< GPDMA2 HW request is I2C3_RX */ 481 #define GPDMA2_REQUEST_I2C3_TX 19U /*!< GPDMA2 HW request is I2C3_TX */ 482 #endif /* I2C3 */ 483 #define GPDMA2_REQUEST_USART1_RX 21U /*!< GPDMA2 HW request is USART1_RX */ 484 #define GPDMA2_REQUEST_USART1_TX 22U /*!< GPDMA2 HW request is USART1_TX */ 485 #define GPDMA2_REQUEST_USART2_RX 23U /*!< GPDMA2 HW request is USART2_RX */ 486 #define GPDMA2_REQUEST_USART2_TX 24U /*!< GPDMA2 HW request is USART2_TX */ 487 #define GPDMA2_REQUEST_USART3_RX 25U /*!< GPDMA2 HW request is USART3_RX */ 488 #define GPDMA2_REQUEST_USART3_TX 26U /*!< GPDMA2 HW request is USART3_TX */ 489 #if defined (UART4) 490 #define GPDMA2_REQUEST_UART4_RX 27U /*!< GPDMA2 HW request is UART4_RX */ 491 #define GPDMA2_REQUEST_UART4_TX 28U /*!< GPDMA2 HW request is UART4_TX */ 492 #endif /* UART4 */ 493 #if defined (UART4) 494 #define GPDMA2_REQUEST_UART5_RX 29U /*!< GPDMA2 HW request is UART5_RX */ 495 #define GPDMA2_REQUEST_UART5_TX 30U /*!< GPDMA2 HW request is UART5_TX */ 496 #endif /* UART5 */ 497 #if defined (UART4) 498 #define GPDMA2_REQUEST_USART6_RX 31U /*!< GPDMA2 HW request is USART6_RX */ 499 #define GPDMA2_REQUEST_USART6_TX 32U /*!< GPDMA2 HW request is USART6_TX */ 500 #endif /* USART6 */ 501 #if defined (UART7) 502 #define GPDMA2_REQUEST_UART7_RX 33U /*!< GPDMA2 HW request is UART7_RX */ 503 #define GPDMA2_REQUEST_UART7_TX 34U /*!< GPDMA2 HW request is UART7_TX */ 504 #endif /* UART7 */ 505 #if defined (UART8) 506 #define GPDMA2_REQUEST_UART8_RX 35U /*!< GPDMA2 HW request is UART8_RX */ 507 #define GPDMA2_REQUEST_UART8_TX 36U /*!< GPDMA2 HW request is UART8_TX */ 508 #endif /* UART8 */ 509 #if defined (UART9) 510 #define GPDMA2_REQUEST_UART9_RX 37U /*!< GPDMA2 HW request is UART9_RX */ 511 #define GPDMA2_REQUEST_UART9_TX 38U /*!< GPDMA2 HW request is UART9_TX */ 512 #endif /* UART9 */ 513 #if defined (USART10) 514 #define GPDMA2_REQUEST_USART10_RX 39U /*!< GPDMA2 HW request is USART10_RX */ 515 #define GPDMA2_REQUEST_USART10_TX 40U /*!< GPDMA2 HW request is USART10_TX */ 516 #endif /* USART10 */ 517 #if defined (USART11) 518 #define GPDMA2_REQUEST_USART11_RX 41U /*!< GPDMA2 HW request is USART11_RX */ 519 #define GPDMA2_REQUEST_USART11_TX 42U /*!< GPDMA2 HW request is USART11_TX */ 520 #endif /* USART11 */ 521 #if defined (UART12) 522 #define GPDMA2_REQUEST_UART12_RX 43U /*!< GPDMA2 HW request is UART12_RX */ 523 #define GPDMA2_REQUEST_UART12_TX 44U /*!< GPDMA2 HW request is UART12_TX */ 524 #endif /* UART12 */ 525 #define GPDMA2_REQUEST_LPUART1_RX 45U /*!< GPDMA2 HW request is LPUART1_RX */ 526 #define GPDMA2_REQUEST_LPUART1_TX 46U /*!< GPDMA2 HW request is LPUART1_TX */ 527 #if defined (SPI4) 528 #define GPDMA2_REQUEST_SPI4_RX 47U /*!< GPDMA2 HW request is SPI4_RX */ 529 #define GPDMA2_REQUEST_SPI4_TX 48U /*!< GPDMA2 HW request is SPI4_TX */ 530 #endif /* SPI4 */ 531 #if defined (SPI5) 532 #define GPDMA2_REQUEST_SPI5_RX 49U /*!< GPDMA2 HW request is SPI5_RX */ 533 #define GPDMA2_REQUEST_SPI5_TX 50U /*!< GPDMA2 HW request is SPI5_TX */ 534 #endif /* SPI5 */ 535 #if defined (SPI6) 536 #define GPDMA2_REQUEST_SPI6_RX 51U /*!< GPDMA2 HW request is SPI6_RX */ 537 #define GPDMA2_REQUEST_SPI6_TX 52U /*!< GPDMA2 HW request is SPI6_TX */ 538 #endif /* SPI6 */ 539 #if defined (SAI1) 540 #define GPDMA2_REQUEST_SAI1_A 53U /*!< GPDMA2 HW request is SAI1_A */ 541 #define GPDMA2_REQUEST_SAI1_B 54U /*!< GPDMA2 HW request is SAI1_B */ 542 #endif /* SAI1 */ 543 #if defined (SAI2) 544 #define GPDMA2_REQUEST_SAI2_A 55U /*!< GPDMA2 HW request is SAI2_A */ 545 #define GPDMA2_REQUEST_SAI2_B 56U /*!< GPDMA2 HW request is SAI2_B */ 546 #endif /* SAI2 */ 547 #if defined (OCTOSPI1) 548 #define GPDMA2_REQUEST_OCTOSPI1 57U /*!< GPDMA2 HW request is OCTOSPI1 */ 549 #endif /* OCTOSPI1 */ 550 #define GPDMA2_REQUEST_TIM1_CH1 58U /*!< GPDMA2 HW request is TIM1_CH1 */ 551 #define GPDMA2_REQUEST_TIM1_CH2 59U /*!< GPDMA2 HW request is TIM1_CH2 */ 552 #define GPDMA2_REQUEST_TIM1_CH3 60U /*!< GPDMA2 HW request is TIM1_CH3 */ 553 #define GPDMA2_REQUEST_TIM1_CH4 61U /*!< GPDMA2 HW request is TIM1_CH4 */ 554 #define GPDMA2_REQUEST_TIM1_UP 62U /*!< GPDMA2 HW request is TIM1_UP */ 555 #define GPDMA2_REQUEST_TIM1_TRIG 63U /*!< GPDMA2 HW request is TIM1_TRIG */ 556 #define GPDMA2_REQUEST_TIM1_COM 64U /*!< GPDMA2 HW request is TIM1_COM */ 557 #if defined (TIM8) 558 #define GPDMA2_REQUEST_TIM8_CH1 65U /*!< GPDMA2 HW request is TIM8_CH1 */ 559 #define GPDMA2_REQUEST_TIM8_CH2 66U /*!< GPDMA2 HW request is TIM8_CH2 */ 560 #define GPDMA2_REQUEST_TIM8_CH3 67U /*!< GPDMA2 HW request is TIM8_CH3 */ 561 #define GPDMA2_REQUEST_TIM8_CH4 68U /*!< GPDMA2 HW request is TIM8_CH4 */ 562 #define GPDMA2_REQUEST_TIM8_UP 69U /*!< GPDMA2 HW request is TIM8_UP */ 563 #define GPDMA2_REQUEST_TIM8_TRIG 70U /*!< GPDMA2 HW request is TIM8_TRIG */ 564 #define GPDMA2_REQUEST_TIM8_COM 71U /*!< GPDMA2 HW request is TIM8_COM */ 565 #endif /* TIM8 */ 566 #define GPDMA2_REQUEST_TIM2_CH1 72U /*!< GPDMA2 HW request is TIM2_CH1 */ 567 #define GPDMA2_REQUEST_TIM2_CH2 73U /*!< GPDMA2 HW request is TIM2_CH2 */ 568 #define GPDMA2_REQUEST_TIM2_CH3 74U /*!< GPDMA2 HW request is TIM2_CH3 */ 569 #define GPDMA2_REQUEST_TIM2_CH4 75U /*!< GPDMA2 HW request is TIM2_CH4 */ 570 #define GPDMA2_REQUEST_TIM2_UP 76U /*!< GPDMA2 HW request is TIM2_UP */ 571 #define GPDMA2_REQUEST_TIM3_CH1 77U /*!< GPDMA2 HW request is TIM3_CH1 */ 572 #define GPDMA2_REQUEST_TIM3_CH2 78U /*!< GPDMA2 HW request is TIM3_CH2 */ 573 #define GPDMA2_REQUEST_TIM3_CH3 79U /*!< GPDMA2 HW request is TIM3_CH3 */ 574 #define GPDMA2_REQUEST_TIM3_CH4 80U /*!< GPDMA2 HW request is TIM3_CH4 */ 575 #define GPDMA2_REQUEST_TIM3_UP 81U /*!< GPDMA2 HW request is TIM3_UP */ 576 #define GPDMA2_REQUEST_TIM3_TRIG 82U /*!< GPDMA2 HW request is TIM3_TRIG */ 577 #if defined (TIM4) 578 #define GPDMA2_REQUEST_TIM4_CH1 83U /*!< GPDMA2 HW request is TIM4_CH1 */ 579 #define GPDMA2_REQUEST_TIM4_CH2 84U /*!< GPDMA2 HW request is TIM4_CH2 */ 580 #define GPDMA2_REQUEST_TIM4_CH3 85U /*!< GPDMA2 HW request is TIM4_CH3 */ 581 #define GPDMA2_REQUEST_TIM4_CH4 86U /*!< GPDMA2 HW request is TIM4_CH4 */ 582 #define GPDMA2_REQUEST_TIM4_UP 87U /*!< GPDMA2 HW request is TIM4_UP */ 583 #endif /* TIM4 */ 584 #if defined (TIM5) 585 #define GPDMA2_REQUEST_TIM5_CH1 88U /*!< GPDMA2 HW request is TIM5_CH1 */ 586 #define GPDMA2_REQUEST_TIM5_CH2 89U /*!< GPDMA2 HW request is TIM5_CH2 */ 587 #define GPDMA2_REQUEST_TIM5_CH3 90U /*!< GPDMA2 HW request is TIM5_CH3 */ 588 #define GPDMA2_REQUEST_TIM5_CH4 91U /*!< GPDMA2 HW request is TIM5_CH4 */ 589 #define GPDMA2_REQUEST_TIM5_UP 92U /*!< GPDMA2 HW request is TIM5_UP */ 590 #define GPDMA2_REQUEST_TIM5_TRIG 93U /*!< GPDMA2 HW request is TIM5_TRIG */ 591 #endif /* TIM5 */ 592 #if defined (TIM15) 593 #define GPDMA2_REQUEST_TIM15_CH1 94U /*!< GPDMA2 HW request is TIM15_CH1 */ 594 #define GPDMA2_REQUEST_TIM15_UP 95U /*!< GPDMA2 HW request is TIM15_UP */ 595 #define GPDMA2_REQUEST_TIM15_TRIG 96U /*!< GPDMA2 HW request is TIM15_TRIG */ 596 #define GPDMA2_REQUEST_TIM15_COM 97U /*!< GPDMA2 HW request is TIM15_COM */ 597 #endif /* TIM15 */ 598 #if defined (TIM16) 599 #define GPDMA2_REQUEST_TIM16_CH1 98U /*!< GPDMA2 HW request is TIM16_CH1 */ 600 #define GPDMA2_REQUEST_TIM16_UP 99U /*!< GPDMA2 HW request is TIM16_UP */ 601 #endif /* TIM16 */ 602 #if defined (TIM17) 603 #define GPDMA2_REQUEST_TIM17_CH1 100U /*!< GPDMA2 HW request is TIM17_CH1 */ 604 #define GPDMA2_REQUEST_TIM17_UP 101U /*!< GPDMA2 HW request is TIM17_UP */ 605 #endif /* TIM17 */ 606 #define GPDMA2_REQUEST_LPTIM1_IC1 102U /*!< GPDMA2 HW request is LPTIM1_IC1 */ 607 #define GPDMA2_REQUEST_LPTIM1_IC2 103U /*!< GPDMA2 HW request is LPTIM1_IC2 */ 608 #define GPDMA2_REQUEST_LPTIM1_UE 104U /*!< GPDMA2 HW request is LPTIM1_UE */ 609 #define GPDMA2_REQUEST_LPTIM2_IC1 105U /*!< GPDMA2 HW request is LPTIM2_IC1 */ 610 #define GPDMA2_REQUEST_LPTIM2_IC2 106U /*!< GPDMA2 HW request is LPTIM2_IC2 */ 611 #define GPDMA2_REQUEST_LPTIM2_UE 107U /*!< GPDMA2 HW request is LPTIM2_UE */ 612 #if defined (DCMI) 613 #define GPDMA2_REQUEST_DCMI 108U /*!< GPDMA2 HW request is DCMI */ 614 #endif /* DCMI */ 615 #if defined (AES) 616 #define GPDMA2_REQUEST_AES_OUT 109U /*!< GPDMA2 HW request is AES_OUT */ 617 #define GPDMA2_REQUEST_AES_IN 110U /*!< GPDMA2 HW request is AES_IN */ 618 #endif /* AES */ 619 #define GPDMA2_REQUEST_HASH_IN 111U /*!< GPDMA2 HW request is HASH_IN */ 620 #if defined (UCPD1) 621 #define GPDMA2_REQUEST_UCPD1_RX 112U /*!< GPDMA2 HW request is UCPD1_RX */ 622 #define GPDMA2_REQUEST_UCPD1_TX 113U /*!< GPDMA2 HW request is UCPD1_TX */ 623 #endif /* UCPD1 */ 624 #if defined (CORDIC) 625 #define GPDMA2_REQUEST_CORDIC_READ 114U /*!< GPDMA2 HW request is CORDIC_READ */ 626 #define GPDMA2_REQUEST_CORDIC_WRITE 115U /*!< GPDMA2 HW request is CORDIC_WRITE */ 627 #endif /* CORDIC */ 628 #if defined (FMAC) 629 #define GPDMA2_REQUEST_FMAC_READ 116U /*!< GPDMA2 HW request is FMAC_READ */ 630 #define GPDMA2_REQUEST_FMAC_WRITE 117U /*!< GPDMA2 HW request is FMAC_WRITE */ 631 #endif /* FMAC */ 632 #if defined (SAES) 633 #define GPDMA2_REQUEST_SAES_OUT 118U /*!< GPDMA2 HW request is SAES_OUT */ 634 #define GPDMA2_REQUEST_SAES_IN 119U /*!< GPDMA2 HW request is SAES_IN */ 635 #endif /* SAES */ 636 #define GPDMA2_REQUEST_I3C1_RX 120U /*!< GPDMA2 HW request is I3C1_RX */ 637 #define GPDMA2_REQUEST_I3C1_TX 121U /*!< GPDMA2 HW request is I3C1_TX */ 638 #define GPDMA2_REQUEST_I3C1_TC 122U /*!< GPDMA2 HW request is I3C1_TC */ 639 #define GPDMA2_REQUEST_I3C1_RS 123U /*!< GPDMA2 HW request is I3C1_RS */ 640 #if defined (I2C4) 641 #define GPDMA2_REQUEST_I2C4_RX 124U /*!< GPDMA2 HW request is I2C4_RX */ 642 #define GPDMA2_REQUEST_I2C4_TX 125U /*!< GPDMA2 HW request is I2C4_TX */ 643 #endif /* I2C4 */ 644 #if defined (LPTIM3) 645 #define GPDMA2_REQUEST_LPTIM3_IC1 127U /*!< GPDMA2 HW request is LPTIM3_IC1 */ 646 #define GPDMA2_REQUEST_LPTIM3_IC2 128U /*!< GPDMA2 HW request is LPTIM3_IC2 */ 647 #define GPDMA2_REQUEST_LPTIM3_UE 129U /*!< GPDMA2 HW request is LPTIM3_UE */ 648 #endif /* LPTIM3 */ 649 #if defined (LPTIM5) 650 #define GPDMA2_REQUEST_LPTIM5_IC1 130U /*!< GPDMA2 HW request is LPTIM5_IC1 */ 651 #define GPDMA2_REQUEST_LPTIM5_IC2 131U /*!< GPDMA2 HW request is LPTIM5_IC2 */ 652 #define GPDMA2_REQUEST_LPTIM5_UE 132U /*!< GPDMA2 HW request is LPTIM5_UE */ 653 #endif /* LPTIM5 */ 654 #if defined (LPTIM6) 655 #define GPDMA2_REQUEST_LPTIM6_IC1 133U /*!< GPDMA2 HW request is LPTIM6_IC1 */ 656 #define GPDMA2_REQUEST_LPTIM6_IC2 134U /*!< GPDMA2 HW request is LPTIM6_IC2 */ 657 #define GPDMA2_REQUEST_LPTIM6_UE 135U /*!< GPDMA2 HW request is LPTIM6_UE */ 658 #endif /* LPTIM6 */ 659 #if defined (I3C2) 660 #define GPDMA2_REQUEST_I3C2_RX 136U /*!< GPDMA2 HW request is I3C2_RX */ 661 #define GPDMA2_REQUEST_I3C2_TX 137U /*!< GPDMA2 HW request is I3C2_TX */ 662 #define GPDMA2_REQUEST_I3C2_TC 138U /*!< GPDMA2 HW request is I3C2_TC */ 663 #define GPDMA2_REQUEST_I3C2_RS 139U /*!< GPDMA2 HW request is I3C2_RS */ 664 #endif /* I3C2 */ 665 666 /* Software request */ 667 #define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ 668 /** 669 * @} 670 */ 671 672 /** @defgroup DMA_Block_Request DMA Block Request 673 * @brief DMA Block Request 674 * @{ 675 */ 676 #define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ 677 #define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ 678 /** 679 * @} 680 */ 681 682 /** @defgroup DMA_Transfer_Direction DMA Transfer Direction 683 * @brief DMA transfer direction 684 * @{ 685 */ 686 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 687 #define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ 688 #define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ 689 /** 690 * @} 691 */ 692 693 /** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode 694 * @brief DMA Source Increment Mode 695 * @{ 696 */ 697 #define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ 698 #define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ 699 /** 700 * @} 701 */ 702 703 /** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode 704 * @brief DMA Destination Increment Mode 705 * @{ 706 */ 707 #define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ 708 #define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ 709 /** 710 * @} 711 */ 712 713 /** @defgroup DMA_Source_Data_Width DMA Source Data Width 714 * @brief DMA Source Data Width 715 * @{ 716 */ 717 #define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ 718 #define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ 719 #define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ 720 /** 721 * @} 722 */ 723 724 /** @defgroup DMA_Destination_Data_Width DMA destination Data Width 725 * @brief DMA destination Data Width 726 * @{ 727 */ 728 #define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ 729 #define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ 730 #define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ 731 /** 732 * @} 733 */ 734 735 /** @defgroup DMA_Priority_Level DMA Priority Level 736 * @brief DMA Priority Level 737 * @{ 738 */ 739 #define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ 740 #define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ 741 #define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ 742 #define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ 743 /** 744 * @} 745 */ 746 747 /** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port 748 * @brief DMA Transfer Allocated Port 749 * @{ 750 */ 751 #define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ 752 #define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ 753 #define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ 754 #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ 755 /** 756 * @} 757 */ 758 759 /** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode 760 * @brief DMA Transfer Event Mode 761 * @{ 762 */ 763 #define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the 764 HT event is generated at the half of each block */ 765 #define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block 766 and the HT event is generated at the half of the repeated 767 block */ 768 #define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list 769 item and the HT event is generated at the half of each 770 linked-list item */ 771 #define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last 772 linked-list item and the HT event is generated at the half 773 of the last linked-list item */ 774 /** 775 * @} 776 */ 777 778 /** @defgroup DMA_Transfer_Mode DMA Transfer Mode 779 * @brief DMA Transfer Mode 780 * @{ 781 */ 782 #define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ 783 /** 784 * @} 785 */ 786 787 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 788 * @brief DMA Channel Security and Privilege Attributes 789 * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 790 * @{ 791 */ 792 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ 793 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 794 795 #define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ 796 #define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ 797 #define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ 798 #define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ 799 #define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ 800 #define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ 801 802 #define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ 803 #define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ 804 /** 805 * @} 806 */ 807 808 /** 809 * @} 810 */ 811 812 813 /* Exported macro ----------------------------------------------------------------------------------------------------*/ 814 /** @defgroup DMA_Exported_Macros DMA Exported Macros 815 * @brief DMA Exported Macros 816 * @{ 817 */ 818 819 /** @brief Reset DMA handle state. 820 * @param __HANDLE__ : DMA handle. 821 * @retval None. 822 */ 823 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ 824 ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 825 826 /** 827 * @brief Enable the specified DMA Channel. 828 * @param __HANDLE__ : DMA handle. 829 * @retval None 830 */ 831 #define __HAL_DMA_ENABLE(__HANDLE__) \ 832 ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 833 834 /** 835 * @brief Disable the specified DMA Channel. 836 * @param __HANDLE__ : DMA handle. 837 * @retval None 838 */ 839 #define __HAL_DMA_DISABLE(__HANDLE__) \ 840 ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) 841 842 /** 843 * @brief Get the DMA channel pending flags. 844 * @param __HANDLE__ : DMA handle. 845 * @param __FLAG__ : Get the specified flag. 846 * This parameter can be any combination of the following values: 847 * @arg DMA_FLAG_TC : Transfer Complete flag. 848 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 849 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 850 * @arg DMA_FLAG_ULE : Update linked-list Error flag. 851 * @arg DMA_FLAG_USE : User Setting Error flag. 852 * @arg DMA_FLAG_TO : Trigger Overrun flag. 853 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 854 * @arg DMA_FLAG_IDLEF : Idle flag. 855 * @retval The state of FLAG (SET or RESET). 856 */ 857 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ 858 ((__HANDLE__)->Instance->CSR & (__FLAG__)) 859 860 /** 861 * @brief Clear the DMA Channel pending flags. 862 * @param __HANDLE__ : DMA handle. 863 * @param __FLAG__ : Specifies the flag to clear. 864 * This parameter can be any combination of the following values: 865 * @arg DMA_FLAG_TC : Transfer Complete flag. 866 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 867 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 868 * @arg DMA_FLAG_ULE : Update Linked-List Error flag. 869 * @arg DMA_FLAG_USE : User Setting Error flag. 870 * @arg DMA_FLAG_TO : Trigger Overrun flag. 871 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 872 * @retval None 873 */ 874 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 875 ((__HANDLE__)->Instance->CFCR = (__FLAG__)) 876 877 /** 878 * @brief Enable the specified DMA Channel interrupts. 879 * @param __HANDLE__ : DMA handle. 880 * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. 881 * This parameter can be any combination of the following values: 882 * @arg DMA_IT_TC : Transfer Complete interrupt. 883 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 884 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 885 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 886 * @arg DMA_IT_USE : User Setting Error interrupt. 887 * @arg DMA_IT_TO : Trigger Overrun interrupt. 888 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 889 * @retval None 890 */ 891 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 892 ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 893 894 /** 895 * @brief Disable the specified DMA Channel interrupts. 896 * @param __HANDLE__ : DMA handle. 897 * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. 898 * This parameter can be any combination of the following values: 899 * @arg DMA_IT_TC : Transfer Complete interrupt. 900 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 901 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 902 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 903 * @arg DMA_IT_USE : User Setting Error interrupt. 904 * @arg DMA_IT_TO : Trigger Overrun interrupt. 905 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 906 * @retval None 907 */ 908 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 909 ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 910 911 /** 912 * @brief Checks whether the specified DMA Channel interrupt is enabled or not. 913 * @param __HANDLE__ : DMA handle. 914 * @param __INTERRUPT__ : specifies the DMA interrupt source to check. 915 * @arg DMA_IT_TC : Transfer Complete interrupt. 916 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 917 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 918 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 919 * @arg DMA_IT_USE : User Setting Error interrupt. 920 * @arg DMA_IT_TO : Trigger Overrun interrupt. 921 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 922 * @retval The state of DMA_IT (SET or RESET). 923 */ 924 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 925 (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 926 927 /** 928 * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. 929 * @param __HANDLE__ : DMA handle. 930 * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). 931 */ 932 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ 933 MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) 934 935 /** 936 * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. 937 * @param __HANDLE__ : DMA handle. 938 * @retval The number of remaining data units in the current DMA Stream transfer. 939 */ 940 #define __HAL_DMA_GET_COUNTER(__HANDLE__) \ 941 (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) 942 /** 943 * @} 944 */ 945 946 947 /* Include DMA HAL Extension module */ 948 #include "stm32h5xx_hal_dma_ex.h" 949 950 951 /* Exported functions ------------------------------------------------------------------------------------------------*/ 952 /** @defgroup DMA_Exported_Functions DMA Exported Functions 953 * @brief DMA Exported Functions 954 * @{ 955 */ 956 957 /** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions 958 * @brief Initialization and De-Initialization Functions 959 * @{ 960 */ 961 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); 962 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); 963 /** 964 * @} 965 */ 966 967 /** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions 968 * @brief I/O Operation Functions 969 * @{ 970 */ 971 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, 972 uint32_t SrcAddress, 973 uint32_t DstAddress, 974 uint32_t SrcDataSize); 975 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, 976 uint32_t SrcAddress, 977 uint32_t DstAddress, 978 uint32_t SrcDataSize); 979 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); 980 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); 981 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, 982 HAL_DMA_LevelCompleteTypeDef CompleteLevel, 983 uint32_t Timeout); 984 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); 985 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, 986 HAL_DMA_CallbackIDTypeDef CallbackID, 987 void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); 988 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, 989 HAL_DMA_CallbackIDTypeDef CallbackID); 990 /** 991 * @} 992 */ 993 994 /** @defgroup DMA_Exported_Functions_Group3 State and Error Functions 995 * @brief State and Error Functions 996 * @{ 997 */ 998 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); 999 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); 1000 /** 1001 * @} 1002 */ 1003 1004 /** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions 1005 * @brief DMA Attributes Functions 1006 * @{ 1007 */ 1008 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, 1009 uint32_t ChannelAttributes); 1010 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, 1011 uint32_t *const pChannelAttributes); 1012 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1013 HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); 1014 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1015 HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, 1016 uint32_t *const pLockState); 1017 1018 /** 1019 * @} 1020 */ 1021 1022 /** 1023 * @} 1024 */ 1025 1026 1027 /* Private constants -------------------------------------------------------------------------------------------------*/ 1028 /** @defgroup DMA_Private_Constants DMA Private Constants 1029 * @brief DMA Private Constants 1030 * @{ 1031 */ 1032 #define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ 1033 #define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ 1034 #define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ 1035 #define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ 1036 #define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ 1037 #define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ 1038 #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ 1039 #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ 1040 #define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ 1041 #define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ 1042 #define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ 1043 #define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ 1044 /** 1045 * @} 1046 */ 1047 1048 1049 /* Private macros ----------------------------------------------------------------------------------------------------*/ 1050 /** @defgroup DMA_Private_Macros DMA Private Macros 1051 * @brief DMA Private Macros 1052 * @{ 1053 */ 1054 #define GET_DMA_INSTANCE(__HANDLE__) \ 1055 ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) 1056 1057 #define GET_DMA_CHANNEL(__HANDLE__) \ 1058 ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) 1059 1060 #define IS_DMA_MODE(MODE) \ 1061 ((MODE) == DMA_NORMAL) 1062 1063 #define IS_DMA_DIRECTION(DIRECTION) \ 1064 (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ 1065 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 1066 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 1067 1068 #define IS_DMA_LEVEL_COMPLETE(LEVEL) \ 1069 (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ 1070 ((LEVEL) == HAL_DMA_HALF_TRANSFER)) 1071 1072 #define IS_DMA_SOURCE_INC(INC) \ 1073 (((INC) == DMA_SINC_FIXED) || \ 1074 ((INC) == DMA_SINC_INCREMENTED)) 1075 1076 #define IS_DMA_DESTINATION_INC(INC) \ 1077 (((INC) == DMA_DINC_FIXED) || \ 1078 ((INC) == DMA_DINC_INCREMENTED)) 1079 1080 #define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ 1081 (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ 1082 ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ 1083 ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)) 1084 1085 #define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ 1086 (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ 1087 ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ 1088 ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)) 1089 1090 #define IS_DMA_BURST_LENGTH(LENGTH) \ 1091 (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ 1092 ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) 1093 1094 #define IS_DMA_PRIORITY(PRIORITY) \ 1095 (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ 1096 ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ 1097 ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ 1098 ((PRIORITY) == DMA_HIGH_PRIORITY)) 1099 1100 #define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ 1101 (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) 1102 1103 #if defined (I3C2) 1104 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_I3C2_RS)) 1105 #else 1106 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM6_UE)) 1107 #endif /* I3C2 */ 1108 1109 #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ 1110 (((MODE) == DMA_BREQ_SINGLE_BURST) || \ 1111 ((MODE) == DMA_BREQ_BLOCK)) 1112 1113 #define IS_DMA_TCEM_EVENT_MODE(MODE) \ 1114 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 1115 ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ 1116 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 1117 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 1118 1119 #define IS_DMA_BLOCK_SIZE(SIZE) \ 1120 (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) 1121 1122 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1123 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 1124 (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ 1125 (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ 1126 (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) 1127 #else 1128 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 1129 (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ 1130 ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) 1131 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1132 1133 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1134 #define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \ 1135 (((INSTANCE)->SMISR & (GLOBAL_FLAG))) 1136 #else 1137 #define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \ 1138 (((INSTANCE)->MISR & (GLOBAL_FLAG))) 1139 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1140 /** 1141 * @} 1142 */ 1143 1144 1145 /* Private functions -------------------------------------------------------------------------------------------------*/ 1146 /** @defgroup DMA_Private_Functions DMA Private Functions 1147 * @brief DMA Private Functions 1148 * @{ 1149 */ 1150 1151 /** 1152 * @} 1153 */ 1154 1155 /** 1156 * @} 1157 */ 1158 1159 /** 1160 * @} 1161 */ 1162 1163 /** 1164 * @} 1165 */ 1166 1167 #ifdef __cplusplus 1168 } 1169 #endif 1170 1171 #endif /* STM32H5xx_HAL_DMA_H */ 1172