1 /** 2 ********************************************************************************************************************** 3 * @file stm32h5xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32H5xx_HAL_DMA_H 21 #define STM32H5xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 39 /* Exported types ----------------------------------------------------------------------------------------------------*/ 40 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @brief DMA Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief DMA Transfer Configuration Structure definition. 48 */ 49 typedef struct 50 { 51 uint32_t Request; /*!< Specifies the DMA channel request. 52 This parameter can be a value of @ref DMA_Request_Selection */ 53 54 uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. 55 Block Hardware request feature can be used only with dedicated peripherals. 56 This parameter can be a value of @ref DMA_Block_Request */ 57 58 uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. 59 This parameter can be a value of @ref DMA_Transfer_Direction */ 60 61 uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. 62 This parameter can be a value of @ref DMA_Source_Increment_Mode */ 63 64 uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. 65 This parameter can be a value of @ref DMA_Destination_Increment_Mode */ 66 67 uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. 68 This parameter can be a value of @ref DMA_Source_Data_Width */ 69 70 uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. 71 This parameter can be a value of @ref DMA_Destination_Data_Width */ 72 73 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 74 This parameter can be a value of @ref DMA_Priority_Level */ 75 76 uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA 77 channel. 78 This parameter can be a value between 1 and 64 */ 79 80 uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the 81 DMA channel. 82 This parameter can be a value between 1 and 64 */ 83 84 uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. 85 This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ 86 87 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 88 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 89 90 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. 91 This parameter can be a value of @ref DMA_Transfer_Mode */ 92 93 } DMA_InitTypeDef; 94 95 /** 96 * @brief DMA Linked-List Configuration Structure Definition. 97 */ 98 typedef struct 99 { 100 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 101 This parameter can be a value of @ref DMA_Priority_Level */ 102 103 uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. 104 This parameter can be a value of @ref DMAEx_Link_Step_Mode */ 105 106 uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. 107 This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ 108 109 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 110 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 111 112 uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. 113 This parameter can be a value of @ref DMAEx_LinkedList_Mode */ 114 115 } DMA_InitLinkedListTypeDef; 116 117 /** 118 * @brief HAL DMA State Enumeration Definition. 119 */ 120 typedef enum 121 { 122 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 123 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 124 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 125 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 126 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 127 HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ 128 129 } HAL_DMA_StateTypeDef; 130 131 /** 132 * @brief HAL DMA Level Complete Enumeration Definition. 133 */ 134 typedef enum 135 { 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ 137 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ 138 139 } HAL_DMA_LevelCompleteTypeDef; 140 141 /** 142 * @brief HAL DMA Callbacks IDs Enumeration Definition. 143 */ 144 typedef enum 145 { 146 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ 147 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ 148 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ 149 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ 150 HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ 151 HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ 152 153 } HAL_DMA_CallbackIDTypeDef; 154 155 /** 156 * @brief DMA handle Structure definition 157 */ 158 typedef struct __DMA_HandleTypeDef 159 { 160 DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ 161 162 DMA_InitTypeDef Init; /*!< DMA channel init parameters */ 163 164 DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ 165 166 HAL_LockTypeDef Lock; /*!< DMA locking object */ 167 168 uint32_t Mode; /*!< DMA transfer mode */ 169 170 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 171 172 __IO uint32_t ErrorCode; /*!< DMA error code */ 173 174 void *Parent; /*!< Parent object state */ 175 176 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 177 178 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ 179 180 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 181 182 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ 183 184 void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ 185 186 struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ 187 188 } DMA_HandleTypeDef; 189 /** 190 * @} 191 */ 192 193 194 /* Exported constants ------------------------------------------------------------------------------------------------*/ 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants 196 * @brief DMA Exported constants 197 * @{ 198 */ 199 200 /** @defgroup DMA_Error_Codes DMA Error Codes 201 * @brief DMA Error Codes 202 * @{ 203 */ 204 #define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ 205 #define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ 206 #define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ 207 #define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ 208 #define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ 209 #define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ 210 #define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ 211 #define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ 212 #define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ 213 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition 219 * @brief DMA Interrupt Enable Definition 220 * @{ 221 */ 222 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ 223 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ 224 #define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ 225 #define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ 226 #define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ 227 #define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ 228 #define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup DMA_Flag_Definition DMA Flag Definition 234 * @brief DMA Flag Definition 235 * @{ 236 */ 237 #define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ 238 #define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ 239 #define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ 240 #define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ 241 #define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ 242 #define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ 243 #define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ 244 #define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup DMA_Request_Selection DMA Request Selection 250 * @brief DMA Request Selection 251 * @{ 252 */ 253 /* GPDMA1 requests */ 254 #define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ 255 #if defined (ADC2) 256 #define GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */ 257 #endif /* ADC2 */ 258 #define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */ 259 #define GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */ 260 #define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ 261 #define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ 262 #define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ 263 #define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ 264 #define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ 265 #define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ 266 #define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ 267 #define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ 268 #define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ 269 #define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ 270 #define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ 271 #define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ 272 #if defined (I2C3) 273 #define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ 274 #define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ 275 #endif /* I2C3 */ 276 #define GPDMA1_REQUEST_USART1_RX 21U /*!< GPDMA1 HW request is USART1_RX */ 277 #define GPDMA1_REQUEST_USART1_TX 22U /*!< GPDMA1 HW request is USART1_TX */ 278 #define GPDMA1_REQUEST_USART2_RX 23U /*!< GPDMA1 HW request is USART2_RX */ 279 #define GPDMA1_REQUEST_USART2_TX 24U /*!< GPDMA1 HW request is USART2_TX */ 280 #define GPDMA1_REQUEST_USART3_RX 25U /*!< GPDMA1 HW request is USART3_RX */ 281 #define GPDMA1_REQUEST_USART3_TX 26U /*!< GPDMA1 HW request is USART3_TX */ 282 #if defined (UART4) 283 #define GPDMA1_REQUEST_UART4_RX 27U /*!< GPDMA1 HW request is UART4_RX */ 284 #define GPDMA1_REQUEST_UART4_TX 28U /*!< GPDMA1 HW request is UART4_TX */ 285 #endif /* UART4 */ 286 #if defined (UART4) 287 #define GPDMA1_REQUEST_UART5_RX 29U /*!< GPDMA1 HW request is UART5_RX */ 288 #define GPDMA1_REQUEST_UART5_TX 30U /*!< GPDMA1 HW request is UART5_TX */ 289 #endif /* UART5 */ 290 #if defined (UART4) 291 #define GPDMA1_REQUEST_USART6_RX 31U /*!< GPDMA1 HW request is USART6_RX */ 292 #define GPDMA1_REQUEST_USART6_TX 32U /*!< GPDMA1 HW request is USART6_TX */ 293 #endif /* USART6 */ 294 #if defined (UART7) 295 #define GPDMA1_REQUEST_UART7_RX 33U /*!< GPDMA1 HW request is UART7_RX */ 296 #define GPDMA1_REQUEST_UART7_TX 34U /*!< GPDMA1 HW request is UART7_TX */ 297 #endif /* UART7 */ 298 #if defined (UART8) 299 #define GPDMA1_REQUEST_UART8_RX 35U /*!< GPDMA1 HW request is UART8_RX */ 300 #define GPDMA1_REQUEST_UART8_TX 36U /*!< GPDMA1 HW request is UART8_TX */ 301 #endif /* UART8 */ 302 #if defined (UART9) 303 #define GPDMA1_REQUEST_UART9_RX 37U /*!< GPDMA1 HW request is UART9_RX */ 304 #define GPDMA1_REQUEST_UART9_TX 38U /*!< GPDMA1 HW request is UART9_TX */ 305 #endif /* UART9 */ 306 #if defined (USART10) 307 #define GPDMA1_REQUEST_USART10_RX 39U /*!< GPDMA1 HW request is USART10_RX */ 308 #define GPDMA1_REQUEST_USART10_TX 40U /*!< GPDMA1 HW request is USART10_TX */ 309 #endif /* USART10 */ 310 #if defined (USART11) 311 #define GPDMA1_REQUEST_USART11_RX 41U /*!< GPDMA1 HW request is USART11_RX */ 312 #define GPDMA1_REQUEST_USART11_TX 42U /*!< GPDMA1 HW request is USART11_TX */ 313 #endif /* USART11 */ 314 #if defined (UART12) 315 #define GPDMA1_REQUEST_UART12_RX 43U /*!< GPDMA1 HW request is UART12_RX */ 316 #define GPDMA1_REQUEST_UART12_TX 44U /*!< GPDMA1 HW request is UART12_TX */ 317 #endif /* UART12 */ 318 #define GPDMA1_REQUEST_LPUART1_RX 45U /*!< GPDMA1 HW request is LPUART1_RX */ 319 #define GPDMA1_REQUEST_LPUART1_TX 46U /*!< GPDMA1 HW request is LPUART1_TX */ 320 #if defined (SPI4) 321 #define GPDMA1_REQUEST_SPI4_RX 47U /*!< GPDMA1 HW request is SPI4_RX */ 322 #define GPDMA1_REQUEST_SPI4_TX 48U /*!< GPDMA1 HW request is SPI4_TX */ 323 #endif /* SPI4 */ 324 #if defined (SPI5) 325 #define GPDMA1_REQUEST_SPI5_RX 49U /*!< GPDMA1 HW request is SPI5_RX */ 326 #define GPDMA1_REQUEST_SPI5_TX 50U /*!< GPDMA1 HW request is SPI5_TX */ 327 #endif /* SPI5 */ 328 #if defined (SPI6) 329 #define GPDMA1_REQUEST_SPI6_RX 51U /*!< GPDMA1 HW request is SPI6_RX */ 330 #define GPDMA1_REQUEST_SPI6_TX 52U /*!< GPDMA1 HW request is SPI6_TX */ 331 #endif /* SPI6 */ 332 #if defined (SAI1) 333 #define GPDMA1_REQUEST_SAI1_A 53U /*!< GPDMA1 HW request is SAI1_A */ 334 #define GPDMA1_REQUEST_SAI1_B 54U /*!< GPDMA1 HW request is SAI1_B */ 335 #endif /* SAI1 */ 336 #if defined (SAI2) 337 #define GPDMA1_REQUEST_SAI2_A 55U /*!< GPDMA1 HW request is SAI2_A */ 338 #define GPDMA1_REQUEST_SAI2_B 56U /*!< GPDMA1 HW request is SAI2_B */ 339 #endif /* SAI2 */ 340 #if defined (OCTOSPI1) 341 #define GPDMA1_REQUEST_OCTOSPI1 57U /*!< GPDMA1 HW request is OCTOSPI1 */ 342 #endif /* OCTOSPI1 */ 343 #define GPDMA1_REQUEST_TIM1_CH1 58U /*!< GPDMA1 HW request is TIM1_CH1 */ 344 #define GPDMA1_REQUEST_TIM1_CH2 59U /*!< GPDMA1 HW request is TIM1_CH2 */ 345 #define GPDMA1_REQUEST_TIM1_CH3 60U /*!< GPDMA1 HW request is TIM1_CH3 */ 346 #define GPDMA1_REQUEST_TIM1_CH4 61U /*!< GPDMA1 HW request is TIM1_CH4 */ 347 #define GPDMA1_REQUEST_TIM1_UP 62U /*!< GPDMA1 HW request is TIM1_UP */ 348 #define GPDMA1_REQUEST_TIM1_TRIG 63U /*!< GPDMA1 HW request is TIM1_TRIG */ 349 #define GPDMA1_REQUEST_TIM1_COM 64U /*!< GPDMA1 HW request is TIM1_COM */ 350 #if defined (TIM8) 351 #define GPDMA1_REQUEST_TIM8_CH1 65U /*!< GPDMA1 HW request is TIM8_CH1 */ 352 #define GPDMA1_REQUEST_TIM8_CH2 66U /*!< GPDMA1 HW request is TIM8_CH2 */ 353 #define GPDMA1_REQUEST_TIM8_CH3 67U /*!< GPDMA1 HW request is TIM8_CH3 */ 354 #define GPDMA1_REQUEST_TIM8_CH4 68U /*!< GPDMA1 HW request is TIM8_CH4 */ 355 #define GPDMA1_REQUEST_TIM8_UP 69U /*!< GPDMA1 HW request is TIM8_UP */ 356 #define GPDMA1_REQUEST_TIM8_TRIG 70U /*!< GPDMA1 HW request is TIM8_TRIG */ 357 #define GPDMA1_REQUEST_TIM8_COM 71U /*!< GPDMA1 HW request is TIM8_COM */ 358 #endif /* TIM8 */ 359 #define GPDMA1_REQUEST_TIM2_CH1 72U /*!< GPDMA1 HW request is TIM2_CH1 */ 360 #define GPDMA1_REQUEST_TIM2_CH2 73U /*!< GPDMA1 HW request is TIM2_CH2 */ 361 #define GPDMA1_REQUEST_TIM2_CH3 74U /*!< GPDMA1 HW request is TIM2_CH3 */ 362 #define GPDMA1_REQUEST_TIM2_CH4 75U /*!< GPDMA1 HW request is TIM2_CH4 */ 363 #define GPDMA1_REQUEST_TIM2_UP 76U /*!< GPDMA1 HW request is TIM2_UP */ 364 #define GPDMA1_REQUEST_TIM3_CH1 77U /*!< GPDMA1 HW request is TIM3_CH1 */ 365 #define GPDMA1_REQUEST_TIM3_CH2 78U /*!< GPDMA1 HW request is TIM3_CH2 */ 366 #define GPDMA1_REQUEST_TIM3_CH3 79U /*!< GPDMA1 HW request is TIM3_CH3 */ 367 #define GPDMA1_REQUEST_TIM3_CH4 80U /*!< GPDMA1 HW request is TIM3_CH4 */ 368 #define GPDMA1_REQUEST_TIM3_UP 81U /*!< GPDMA1 HW request is TIM3_UP */ 369 #define GPDMA1_REQUEST_TIM3_TRIG 82U /*!< GPDMA1 HW request is TIM3_TRIG */ 370 #if defined (TIM4) 371 #define GPDMA1_REQUEST_TIM4_CH1 83U /*!< GPDMA1 HW request is TIM4_CH1 */ 372 #define GPDMA1_REQUEST_TIM4_CH2 84U /*!< GPDMA1 HW request is TIM4_CH2 */ 373 #define GPDMA1_REQUEST_TIM4_CH3 85U /*!< GPDMA1 HW request is TIM4_CH3 */ 374 #define GPDMA1_REQUEST_TIM4_CH4 86U /*!< GPDMA1 HW request is TIM4_CH4 */ 375 #define GPDMA1_REQUEST_TIM4_UP 87U /*!< GPDMA1 HW request is TIM4_UP */ 376 #endif /* TIM4 */ 377 #if defined (TIM5) 378 #define GPDMA1_REQUEST_TIM5_CH1 88U /*!< GPDMA1 HW request is TIM5_CH1 */ 379 #define GPDMA1_REQUEST_TIM5_CH2 89U /*!< GPDMA1 HW request is TIM5_CH2 */ 380 #define GPDMA1_REQUEST_TIM5_CH3 90U /*!< GPDMA1 HW request is TIM5_CH3 */ 381 #define GPDMA1_REQUEST_TIM5_CH4 91U /*!< GPDMA1 HW request is TIM5_CH4 */ 382 #define GPDMA1_REQUEST_TIM5_UP 92U /*!< GPDMA1 HW request is TIM5_UP */ 383 #define GPDMA1_REQUEST_TIM5_TRIG 93U /*!< GPDMA1 HW request is TIM5_TRIG */ 384 #endif /* TIM5 */ 385 #if defined (TIM15) 386 #define GPDMA1_REQUEST_TIM15_CH1 94U /*!< GPDMA1 HW request is TIM15_CH1 */ 387 #define GPDMA1_REQUEST_TIM15_UP 95U /*!< GPDMA1 HW request is TIM15_UP */ 388 #define GPDMA1_REQUEST_TIM15_TRIG 96U /*!< GPDMA1 HW request is TIM15_TRIG */ 389 #define GPDMA1_REQUEST_TIM15_COM 97U /*!< GPDMA1 HW request is TIM15_COM */ 390 #endif /* TIM15 */ 391 #if defined (TIM16) 392 #define GPDMA1_REQUEST_TIM16_CH1 98U /*!< GPDMA1 HW request is TIM16_CH1 */ 393 #define GPDMA1_REQUEST_TIM16_UP 99U /*!< GPDMA1 HW request is TIM16_UP */ 394 #endif /* TIM16 */ 395 #if defined (TIM17) 396 #define GPDMA1_REQUEST_TIM17_CH1 100U /*!< GPDMA1 HW request is TIM17_CH1 */ 397 #define GPDMA1_REQUEST_TIM17_UP 101U /*!< GPDMA1 HW request is TIM17_UP */ 398 #endif /* TIM17 */ 399 #define GPDMA1_REQUEST_LPTIM1_IC1 102U /*!< GPDMA1 HW request is LPTIM1_IC1 */ 400 #define GPDMA1_REQUEST_LPTIM1_IC2 103U /*!< GPDMA1 HW request is LPTIM1_IC2 */ 401 #define GPDMA1_REQUEST_LPTIM1_UE 104U /*!< GPDMA1 HW request is LPTIM1_UE */ 402 #define GPDMA1_REQUEST_LPTIM2_IC1 105U /*!< GPDMA1 HW request is LPTIM2_IC1 */ 403 #define GPDMA1_REQUEST_LPTIM2_IC2 106U /*!< GPDMA1 HW request is LPTIM2_IC2 */ 404 #define GPDMA1_REQUEST_LPTIM2_UE 107U /*!< GPDMA1 HW request is LPTIM2_UE */ 405 #if defined (DCMI) 406 #define GPDMA1_REQUEST_DCMI 108U /*!< GPDMA1 HW request is DCMI */ 407 #endif /* DCMI */ 408 #if defined (AES) 409 #define GPDMA1_REQUEST_AES_OUT 109U /*!< GPDMA1 HW request is AES_OUT */ 410 #define GPDMA1_REQUEST_AES_IN 110U /*!< GPDMA1 HW request is AES_IN */ 411 #endif /* AES */ 412 #define GPDMA1_REQUEST_HASH_IN 111U /*!< GPDMA1 HW request is HASH_IN */ 413 #if defined (UCPD1) 414 #define GPDMA1_REQUEST_UCPD1_RX 112U /*!< GPDMA1 HW request is UCPD1_RX */ 415 #define GPDMA1_REQUEST_UCPD1_TX 113U /*!< GPDMA1 HW request is UCPD1_TX */ 416 #endif /* UCPD1 */ 417 #if defined (CORDIC) 418 #define GPDMA1_REQUEST_CORDIC_READ 114U /*!< GPDMA1 HW request is CORDIC_READ */ 419 #define GPDMA1_REQUEST_CORDIC_WRITE 115U /*!< GPDMA1 HW request is CORDIC_WRITE */ 420 #endif /* CORDIC */ 421 #if defined (FMAC) 422 #define GPDMA1_REQUEST_FMAC_READ 116U /*!< GPDMA1 HW request is FMAC_READ */ 423 #define GPDMA1_REQUEST_FMAC_WRITE 117U /*!< GPDMA1 HW request is FMAC_WRITE */ 424 #endif /* FMAC */ 425 #if defined (SAES) 426 #define GPDMA1_REQUEST_SAES_OUT 118U /*!< GPDMA1 HW request is SAES_OUT */ 427 #define GPDMA1_REQUEST_SAES_IN 119U /*!< GPDMA1 HW request is SAES_IN */ 428 #endif /* SAES */ 429 #define GPDMA1_REQUEST_I3C1_RX 120U /*!< GPDMA1 HW request is I3C1_RX */ 430 #define GPDMA1_REQUEST_I3C1_TX 121U /*!< GPDMA1 HW request is I3C1_TX */ 431 #define GPDMA1_REQUEST_I3C1_TC 122U /*!< GPDMA1 HW request is I3C1_TC */ 432 #define GPDMA1_REQUEST_I3C1_RS 123U /*!< GPDMA1 HW request is I3C1_RS */ 433 #if defined (I2C4) 434 #define GPDMA1_REQUEST_I2C4_RX 124U /*!< GPDMA1 HW request is I2C4_RX */ 435 #define GPDMA1_REQUEST_I2C4_TX 125U /*!< GPDMA1 HW request is I2C4_TX */ 436 #endif /* I2C4 */ 437 #if defined (LPTIM3) 438 #define GPDMA1_REQUEST_LPTIM3_IC1 127U /*!< GPDMA1 HW request is LPTIM3_IC1 */ 439 #define GPDMA1_REQUEST_LPTIM3_IC2 128U /*!< GPDMA1 HW request is LPTIM3_IC2 */ 440 #define GPDMA1_REQUEST_LPTIM3_UE 129U /*!< GPDMA1 HW request is LPTIM3_UE */ 441 #endif /* LPTIM3 */ 442 #if defined (LPTIM5) 443 #define GPDMA1_REQUEST_LPTIM5_IC1 130U /*!< GPDMA1 HW request is LPTIM5_IC1 */ 444 #define GPDMA1_REQUEST_LPTIM5_IC2 131U /*!< GPDMA1 HW request is LPTIM5_IC2 */ 445 #define GPDMA1_REQUEST_LPTIM5_UE 132U /*!< GPDMA1 HW request is LPTIM5_UE */ 446 #endif /* LPTIM5 */ 447 #if defined (LPTIM6) 448 #define GPDMA1_REQUEST_LPTIM6_IC1 133U /*!< GPDMA1 HW request is LPTIM6_IC1 */ 449 #define GPDMA1_REQUEST_LPTIM6_IC2 134U /*!< GPDMA1 HW request is LPTIM6_IC2 */ 450 #define GPDMA1_REQUEST_LPTIM6_UE 135U /*!< GPDMA1 HW request is LPTIM6_UE */ 451 #endif /* LPTIM6 */ 452 #if defined (I3C2) 453 #define GPDMA1_REQUEST_I3C2_RX 136U /*!< GPDMA1 HW request is I3C2_RX */ 454 #define GPDMA1_REQUEST_I3C2_TX 137U /*!< GPDMA1 HW request is I3C2_TX */ 455 #define GPDMA1_REQUEST_I3C2_TC 138U /*!< GPDMA1 HW request is I3C2_TC */ 456 #define GPDMA1_REQUEST_I3C2_RS 139U /*!< GPDMA1 HW request is I3C2_RS */ 457 #endif /* I3C2 */ 458 459 /* GPDMA2 requests */ 460 #define GPDMA2_REQUEST_ADC1 0U /*!< GPDMA2 HW request is ADC1 */ 461 #if defined (ADC2) 462 #define GPDMA2_REQUEST_ADC2 1U /*!< GPDMA2 HW request is ADC2 */ 463 #endif /* ADC2 */ 464 #define GPDMA2_REQUEST_DAC1_CH1 2U /*!< GPDMA2 HW request is DAC1_CH1 */ 465 #define GPDMA2_REQUEST_DAC1_CH2 3U /*!< GPDMA2 HW request is DAC1_CH2 */ 466 #define GPDMA2_REQUEST_TIM6_UP 4U /*!< GPDMA2 HW request is TIM6_UP */ 467 #define GPDMA2_REQUEST_TIM7_UP 5U /*!< GPDMA2 HW request is TIM7_UP */ 468 #define GPDMA2_REQUEST_SPI1_RX 6U /*!< GPDMA2 HW request is SPI1_RX */ 469 #define GPDMA2_REQUEST_SPI1_TX 7U /*!< GPDMA2 HW request is SPI1_TX */ 470 #define GPDMA2_REQUEST_SPI2_RX 8U /*!< GPDMA2 HW request is SPI2_RX */ 471 #define GPDMA2_REQUEST_SPI2_TX 9U /*!< GPDMA2 HW request is SPI2_TX */ 472 #define GPDMA2_REQUEST_SPI3_RX 10U /*!< GPDMA2 HW request is SPI3_RX */ 473 #define GPDMA2_REQUEST_SPI3_TX 11U /*!< GPDMA2 HW request is SPI3_TX */ 474 #define GPDMA2_REQUEST_I2C1_RX 12U /*!< GPDMA2 HW request is I2C1_RX */ 475 #define GPDMA2_REQUEST_I2C1_TX 13U /*!< GPDMA2 HW request is I2C1_TX */ 476 #define GPDMA2_REQUEST_I2C2_RX 15U /*!< GPDMA2 HW request is I2C2_RX */ 477 #define GPDMA2_REQUEST_I2C2_TX 16U /*!< GPDMA2 HW request is I2C2_TX */ 478 #if defined (I2C3) 479 #define GPDMA2_REQUEST_I2C3_RX 18U /*!< GPDMA2 HW request is I2C3_RX */ 480 #define GPDMA2_REQUEST_I2C3_TX 19U /*!< GPDMA2 HW request is I2C3_TX */ 481 #endif /* I2C3 */ 482 #define GPDMA2_REQUEST_USART1_RX 21U /*!< GPDMA2 HW request is USART1_RX */ 483 #define GPDMA2_REQUEST_USART1_TX 22U /*!< GPDMA2 HW request is USART1_TX */ 484 #define GPDMA2_REQUEST_USART2_RX 23U /*!< GPDMA2 HW request is USART2_RX */ 485 #define GPDMA2_REQUEST_USART2_TX 24U /*!< GPDMA2 HW request is USART2_TX */ 486 #define GPDMA2_REQUEST_USART3_RX 25U /*!< GPDMA2 HW request is USART3_RX */ 487 #define GPDMA2_REQUEST_USART3_TX 26U /*!< GPDMA2 HW request is USART3_TX */ 488 #if defined (UART4) 489 #define GPDMA2_REQUEST_UART4_RX 27U /*!< GPDMA2 HW request is UART4_RX */ 490 #define GPDMA2_REQUEST_UART4_TX 28U /*!< GPDMA2 HW request is UART4_TX */ 491 #endif /* UART4 */ 492 #if defined (UART4) 493 #define GPDMA2_REQUEST_UART5_RX 29U /*!< GPDMA2 HW request is UART5_RX */ 494 #define GPDMA2_REQUEST_UART5_TX 30U /*!< GPDMA2 HW request is UART5_TX */ 495 #endif /* UART5 */ 496 #if defined (UART4) 497 #define GPDMA2_REQUEST_USART6_RX 31U /*!< GPDMA2 HW request is USART6_RX */ 498 #define GPDMA2_REQUEST_USART6_TX 32U /*!< GPDMA2 HW request is USART6_TX */ 499 #endif /* USART6 */ 500 #if defined (UART7) 501 #define GPDMA2_REQUEST_UART7_RX 33U /*!< GPDMA2 HW request is UART7_RX */ 502 #define GPDMA2_REQUEST_UART7_TX 34U /*!< GPDMA2 HW request is UART7_TX */ 503 #endif /* UART7 */ 504 #if defined (UART8) 505 #define GPDMA2_REQUEST_UART8_RX 35U /*!< GPDMA2 HW request is UART8_RX */ 506 #define GPDMA2_REQUEST_UART8_TX 36U /*!< GPDMA2 HW request is UART8_TX */ 507 #endif /* UART8 */ 508 #if defined (UART9) 509 #define GPDMA2_REQUEST_UART9_RX 37U /*!< GPDMA2 HW request is UART9_RX */ 510 #define GPDMA2_REQUEST_UART9_TX 38U /*!< GPDMA2 HW request is UART9_TX */ 511 #endif /* UART9 */ 512 #if defined (USART10) 513 #define GPDMA2_REQUEST_USART10_RX 39U /*!< GPDMA2 HW request is USART10_RX */ 514 #define GPDMA2_REQUEST_USART10_TX 40U /*!< GPDMA2 HW request is USART10_TX */ 515 #endif /* USART10 */ 516 #if defined (USART11) 517 #define GPDMA2_REQUEST_USART11_RX 41U /*!< GPDMA2 HW request is USART11_RX */ 518 #define GPDMA2_REQUEST_USART11_TX 42U /*!< GPDMA2 HW request is USART11_TX */ 519 #endif /* USART11 */ 520 #if defined (UART12) 521 #define GPDMA2_REQUEST_UART12_RX 43U /*!< GPDMA2 HW request is UART12_RX */ 522 #define GPDMA2_REQUEST_UART12_TX 44U /*!< GPDMA2 HW request is UART12_TX */ 523 #endif /* UART12 */ 524 #define GPDMA2_REQUEST_LPUART1_RX 45U /*!< GPDMA2 HW request is LPUART1_RX */ 525 #define GPDMA2_REQUEST_LPUART1_TX 46U /*!< GPDMA2 HW request is LPUART1_TX */ 526 #if defined (SPI4) 527 #define GPDMA2_REQUEST_SPI4_RX 47U /*!< GPDMA2 HW request is SPI4_RX */ 528 #define GPDMA2_REQUEST_SPI4_TX 48U /*!< GPDMA2 HW request is SPI4_TX */ 529 #endif /* SPI4 */ 530 #if defined (SPI5) 531 #define GPDMA2_REQUEST_SPI5_RX 49U /*!< GPDMA2 HW request is SPI5_RX */ 532 #define GPDMA2_REQUEST_SPI5_TX 50U /*!< GPDMA2 HW request is SPI5_TX */ 533 #endif /* SPI5 */ 534 #if defined (SPI6) 535 #define GPDMA2_REQUEST_SPI6_RX 51U /*!< GPDMA2 HW request is SPI6_RX */ 536 #define GPDMA2_REQUEST_SPI6_TX 52U /*!< GPDMA2 HW request is SPI6_TX */ 537 #endif /* SPI6 */ 538 #if defined (SAI1) 539 #define GPDMA2_REQUEST_SAI1_A 53U /*!< GPDMA2 HW request is SAI1_A */ 540 #define GPDMA2_REQUEST_SAI1_B 54U /*!< GPDMA2 HW request is SAI1_B */ 541 #endif /* SAI1 */ 542 #if defined (SAI2) 543 #define GPDMA2_REQUEST_SAI2_A 55U /*!< GPDMA2 HW request is SAI2_A */ 544 #define GPDMA2_REQUEST_SAI2_B 56U /*!< GPDMA2 HW request is SAI2_B */ 545 #endif /* SAI2 */ 546 #if defined (OCTOSPI1) 547 #define GPDMA2_REQUEST_OCTOSPI1 57U /*!< GPDMA2 HW request is OCTOSPI1 */ 548 #endif /* OCTOSPI1 */ 549 #define GPDMA2_REQUEST_TIM1_CH1 58U /*!< GPDMA2 HW request is TIM1_CH1 */ 550 #define GPDMA2_REQUEST_TIM1_CH2 59U /*!< GPDMA2 HW request is TIM1_CH2 */ 551 #define GPDMA2_REQUEST_TIM1_CH3 60U /*!< GPDMA2 HW request is TIM1_CH3 */ 552 #define GPDMA2_REQUEST_TIM1_CH4 61U /*!< GPDMA2 HW request is TIM1_CH4 */ 553 #define GPDMA2_REQUEST_TIM1_UP 62U /*!< GPDMA2 HW request is TIM1_UP */ 554 #define GPDMA2_REQUEST_TIM1_TRIG 63U /*!< GPDMA2 HW request is TIM1_TRIG */ 555 #define GPDMA2_REQUEST_TIM1_COM 64U /*!< GPDMA2 HW request is TIM1_COM */ 556 #if defined (TIM8) 557 #define GPDMA2_REQUEST_TIM8_CH1 65U /*!< GPDMA2 HW request is TIM8_CH1 */ 558 #define GPDMA2_REQUEST_TIM8_CH2 66U /*!< GPDMA2 HW request is TIM8_CH2 */ 559 #define GPDMA2_REQUEST_TIM8_CH3 67U /*!< GPDMA2 HW request is TIM8_CH3 */ 560 #define GPDMA2_REQUEST_TIM8_CH4 68U /*!< GPDMA2 HW request is TIM8_CH4 */ 561 #define GPDMA2_REQUEST_TIM8_UP 69U /*!< GPDMA2 HW request is TIM8_UP */ 562 #define GPDMA2_REQUEST_TIM8_TRIG 70U /*!< GPDMA2 HW request is TIM8_TRIG */ 563 #define GPDMA2_REQUEST_TIM8_COM 71U /*!< GPDMA2 HW request is TIM8_COM */ 564 #endif /* TIM8 */ 565 #define GPDMA2_REQUEST_TIM2_CH1 72U /*!< GPDMA2 HW request is TIM2_CH1 */ 566 #define GPDMA2_REQUEST_TIM2_CH2 73U /*!< GPDMA2 HW request is TIM2_CH2 */ 567 #define GPDMA2_REQUEST_TIM2_CH3 74U /*!< GPDMA2 HW request is TIM2_CH3 */ 568 #define GPDMA2_REQUEST_TIM2_CH4 75U /*!< GPDMA2 HW request is TIM2_CH4 */ 569 #define GPDMA2_REQUEST_TIM2_UP 76U /*!< GPDMA2 HW request is TIM2_UP */ 570 #define GPDMA2_REQUEST_TIM3_CH1 77U /*!< GPDMA2 HW request is TIM3_CH1 */ 571 #define GPDMA2_REQUEST_TIM3_CH2 78U /*!< GPDMA2 HW request is TIM3_CH2 */ 572 #define GPDMA2_REQUEST_TIM3_CH3 79U /*!< GPDMA2 HW request is TIM3_CH3 */ 573 #define GPDMA2_REQUEST_TIM3_CH4 80U /*!< GPDMA2 HW request is TIM3_CH4 */ 574 #define GPDMA2_REQUEST_TIM3_UP 81U /*!< GPDMA2 HW request is TIM3_UP */ 575 #define GPDMA2_REQUEST_TIM3_TRIG 82U /*!< GPDMA2 HW request is TIM3_TRIG */ 576 #if defined (TIM4) 577 #define GPDMA2_REQUEST_TIM4_CH1 83U /*!< GPDMA2 HW request is TIM4_CH1 */ 578 #define GPDMA2_REQUEST_TIM4_CH2 84U /*!< GPDMA2 HW request is TIM4_CH2 */ 579 #define GPDMA2_REQUEST_TIM4_CH3 85U /*!< GPDMA2 HW request is TIM4_CH3 */ 580 #define GPDMA2_REQUEST_TIM4_CH4 86U /*!< GPDMA2 HW request is TIM4_CH4 */ 581 #define GPDMA2_REQUEST_TIM4_UP 87U /*!< GPDMA2 HW request is TIM4_UP */ 582 #endif /* TIM4 */ 583 #if defined (TIM5) 584 #define GPDMA2_REQUEST_TIM5_CH1 88U /*!< GPDMA2 HW request is TIM5_CH1 */ 585 #define GPDMA2_REQUEST_TIM5_CH2 89U /*!< GPDMA2 HW request is TIM5_CH2 */ 586 #define GPDMA2_REQUEST_TIM5_CH3 90U /*!< GPDMA2 HW request is TIM5_CH3 */ 587 #define GPDMA2_REQUEST_TIM5_CH4 91U /*!< GPDMA2 HW request is TIM5_CH4 */ 588 #define GPDMA2_REQUEST_TIM5_UP 92U /*!< GPDMA2 HW request is TIM5_UP */ 589 #define GPDMA2_REQUEST_TIM5_TRIG 93U /*!< GPDMA2 HW request is TIM5_TRIG */ 590 #endif /* TIM5 */ 591 #if defined (TIM15) 592 #define GPDMA2_REQUEST_TIM15_CH1 94U /*!< GPDMA2 HW request is TIM15_CH1 */ 593 #define GPDMA2_REQUEST_TIM15_UP 95U /*!< GPDMA2 HW request is TIM15_UP */ 594 #define GPDMA2_REQUEST_TIM15_TRIG 96U /*!< GPDMA2 HW request is TIM15_TRIG */ 595 #define GPDMA2_REQUEST_TIM15_COM 97U /*!< GPDMA2 HW request is TIM15_COM */ 596 #endif /* TIM15 */ 597 #if defined (TIM16) 598 #define GPDMA2_REQUEST_TIM16_CH1 98U /*!< GPDMA2 HW request is TIM16_CH1 */ 599 #define GPDMA2_REQUEST_TIM16_UP 99U /*!< GPDMA2 HW request is TIM16_UP */ 600 #endif /* TIM16 */ 601 #if defined (TIM17) 602 #define GPDMA2_REQUEST_TIM17_CH1 100U /*!< GPDMA2 HW request is TIM17_CH1 */ 603 #define GPDMA2_REQUEST_TIM17_UP 101U /*!< GPDMA2 HW request is TIM17_UP */ 604 #endif /* TIM17 */ 605 #define GPDMA2_REQUEST_LPTIM1_IC1 102U /*!< GPDMA2 HW request is LPTIM1_IC1 */ 606 #define GPDMA2_REQUEST_LPTIM1_IC2 103U /*!< GPDMA2 HW request is LPTIM1_IC2 */ 607 #define GPDMA2_REQUEST_LPTIM1_UE 104U /*!< GPDMA2 HW request is LPTIM1_UE */ 608 #define GPDMA2_REQUEST_LPTIM2_IC1 105U /*!< GPDMA2 HW request is LPTIM2_IC1 */ 609 #define GPDMA2_REQUEST_LPTIM2_IC2 106U /*!< GPDMA2 HW request is LPTIM2_IC2 */ 610 #define GPDMA2_REQUEST_LPTIM2_UE 107U /*!< GPDMA2 HW request is LPTIM2_UE */ 611 #if defined (DCMI) 612 #define GPDMA2_REQUEST_DCMI 108U /*!< GPDMA2 HW request is DCMI */ 613 #endif /* DCMI */ 614 #if defined (AES) 615 #define GPDMA2_REQUEST_AES_OUT 109U /*!< GPDMA2 HW request is AES_OUT */ 616 #define GPDMA2_REQUEST_AES_IN 110U /*!< GPDMA2 HW request is AES_IN */ 617 #endif /* AES */ 618 #define GPDMA2_REQUEST_HASH_IN 111U /*!< GPDMA2 HW request is HASH_IN */ 619 #if defined (UCPD1) 620 #define GPDMA2_REQUEST_UCPD1_RX 112U /*!< GPDMA2 HW request is UCPD1_RX */ 621 #define GPDMA2_REQUEST_UCPD1_TX 113U /*!< GPDMA2 HW request is UCPD1_TX */ 622 #endif /* UCPD1 */ 623 #if defined (CORDIC) 624 #define GPDMA2_REQUEST_CORDIC_READ 114U /*!< GPDMA2 HW request is CORDIC_READ */ 625 #define GPDMA2_REQUEST_CORDIC_WRITE 115U /*!< GPDMA2 HW request is CORDIC_WRITE */ 626 #endif /* CORDIC */ 627 #if defined (FMAC) 628 #define GPDMA2_REQUEST_FMAC_READ 116U /*!< GPDMA2 HW request is FMAC_READ */ 629 #define GPDMA2_REQUEST_FMAC_WRITE 117U /*!< GPDMA2 HW request is FMAC_WRITE */ 630 #endif /* FMAC */ 631 #if defined (SAES) 632 #define GPDMA2_REQUEST_SAES_OUT 118U /*!< GPDMA2 HW request is SAES_OUT */ 633 #define GPDMA2_REQUEST_SAES_IN 119U /*!< GPDMA2 HW request is SAES_IN */ 634 #endif /* SAES */ 635 #define GPDMA2_REQUEST_I3C1_RX 120U /*!< GPDMA2 HW request is I3C1_RX */ 636 #define GPDMA2_REQUEST_I3C1_TX 121U /*!< GPDMA2 HW request is I3C1_TX */ 637 #define GPDMA2_REQUEST_I3C1_TC 122U /*!< GPDMA2 HW request is I3C1_TC */ 638 #define GPDMA2_REQUEST_I3C1_RS 123U /*!< GPDMA2 HW request is I3C1_RS */ 639 #if defined (I2C4) 640 #define GPDMA2_REQUEST_I2C4_RX 124U /*!< GPDMA2 HW request is I2C4_RX */ 641 #define GPDMA2_REQUEST_I2C4_TX 125U /*!< GPDMA2 HW request is I2C4_TX */ 642 #endif /* I2C4 */ 643 #if defined (LPTIM3) 644 #define GPDMA2_REQUEST_LPTIM3_IC1 127U /*!< GPDMA2 HW request is LPTIM3_IC1 */ 645 #define GPDMA2_REQUEST_LPTIM3_IC2 128U /*!< GPDMA2 HW request is LPTIM3_IC2 */ 646 #define GPDMA2_REQUEST_LPTIM3_UE 129U /*!< GPDMA2 HW request is LPTIM3_UE */ 647 #endif /* LPTIM3 */ 648 #if defined (LPTIM5) 649 #define GPDMA2_REQUEST_LPTIM5_IC1 130U /*!< GPDMA2 HW request is LPTIM5_IC1 */ 650 #define GPDMA2_REQUEST_LPTIM5_IC2 131U /*!< GPDMA2 HW request is LPTIM5_IC2 */ 651 #define GPDMA2_REQUEST_LPTIM5_UE 132U /*!< GPDMA2 HW request is LPTIM5_UE */ 652 #endif /* LPTIM5 */ 653 #if defined (LPTIM6) 654 #define GPDMA2_REQUEST_LPTIM6_IC1 133U /*!< GPDMA2 HW request is LPTIM6_IC1 */ 655 #define GPDMA2_REQUEST_LPTIM6_IC2 134U /*!< GPDMA2 HW request is LPTIM6_IC2 */ 656 #define GPDMA2_REQUEST_LPTIM6_UE 135U /*!< GPDMA2 HW request is LPTIM6_UE */ 657 #endif /* LPTIM6 */ 658 #if defined (I3C2) 659 #define GPDMA2_REQUEST_I3C2_RX 136U /*!< GPDMA2 HW request is I3C2_RX */ 660 #define GPDMA2_REQUEST_I3C2_TX 137U /*!< GPDMA2 HW request is I3C2_TX */ 661 #define GPDMA2_REQUEST_I3C2_TC 138U /*!< GPDMA2 HW request is I3C2_TC */ 662 #define GPDMA2_REQUEST_I3C2_RS 139U /*!< GPDMA2 HW request is I3C2_RS */ 663 #endif /* I3C2 */ 664 665 /* Software request */ 666 #define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ 667 /** 668 * @} 669 */ 670 671 /** @defgroup DMA_Block_Request DMA Block Request 672 * @brief DMA Block Request 673 * @{ 674 */ 675 #define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ 676 #define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ 677 /** 678 * @} 679 */ 680 681 /** @defgroup DMA_Transfer_Direction DMA Transfer Direction 682 * @brief DMA transfer direction 683 * @{ 684 */ 685 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 686 #define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ 687 #define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ 688 /** 689 * @} 690 */ 691 692 /** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode 693 * @brief DMA Source Increment Mode 694 * @{ 695 */ 696 #define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ 697 #define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ 698 /** 699 * @} 700 */ 701 702 /** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode 703 * @brief DMA Destination Increment Mode 704 * @{ 705 */ 706 #define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ 707 #define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ 708 /** 709 * @} 710 */ 711 712 /** @defgroup DMA_Source_Data_Width DMA Source Data Width 713 * @brief DMA Source Data Width 714 * @{ 715 */ 716 #define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ 717 #define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ 718 #define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ 719 /** 720 * @} 721 */ 722 723 /** @defgroup DMA_Destination_Data_Width DMA destination Data Width 724 * @brief DMA destination Data Width 725 * @{ 726 */ 727 #define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ 728 #define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ 729 #define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ 730 731 /** 732 * @} 733 */ 734 735 /** @defgroup DMA_Priority_Level DMA Priority Level 736 * @brief DMA Priority Level 737 * @{ 738 */ 739 #define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ 740 #define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ 741 #define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ 742 #define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ 743 /** 744 * @} 745 */ 746 747 /** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port 748 * @brief DMA Transfer Allocated Port 749 * @{ 750 */ 751 #define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ 752 #define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ 753 #define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ 754 #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ 755 /** 756 * @} 757 */ 758 759 /** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode 760 * @brief DMA Transfer Event Mode 761 * @{ 762 */ 763 #define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the 764 HT event is generated at the half of each block */ 765 #define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block 766 and the HT event is generated at the half of the repeated 767 block */ 768 #define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list 769 item and the HT event is generated at the half of each 770 linked-list item */ 771 #define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last 772 linked-list item and the HT event is generated at the half 773 of the last linked-list item */ 774 /** 775 * @} 776 */ 777 778 /** @defgroup DMA_Transfer_Mode DMA Transfer Mode 779 * @brief DMA Transfer Mode 780 * @{ 781 */ 782 #define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ 783 #define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ 784 /** 785 * @} 786 */ 787 788 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 789 * @brief DMA Channel Security and Privilege Attributes 790 * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 791 * @{ 792 */ 793 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ 794 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 795 796 #define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ 797 #define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ 798 #define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ 799 #define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ 800 #define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ 801 #define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ 802 803 #define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ 804 #define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ 805 /** 806 * @} 807 */ 808 809 810 /** 811 * @} 812 */ 813 814 815 /* Exported macro ----------------------------------------------------------------------------------------------------*/ 816 /** @defgroup DMA_Exported_Macros DMA Exported Macros 817 * @brief DMA Exported Macros 818 * @{ 819 */ 820 821 /** @brief Reset DMA handle state. 822 * @param __HANDLE__ : DMA handle. 823 * @retval None. 824 */ 825 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ 826 ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 827 828 /** 829 * @brief Enable the specified DMA Channel. 830 * @param __HANDLE__ : DMA handle. 831 * @retval None 832 */ 833 #define __HAL_DMA_ENABLE(__HANDLE__) \ 834 ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 835 836 /** 837 * @brief Disable the specified DMA Channel. 838 * @param __HANDLE__ : DMA handle. 839 * @retval None 840 */ 841 #define __HAL_DMA_DISABLE(__HANDLE__) \ 842 ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) 843 844 /** 845 * @brief Get the DMA channel pending flags. 846 * @param __HANDLE__ : DMA handle. 847 * @param __FLAG__ : Get the specified flag. 848 * This parameter can be any combination of the following values: 849 * @arg DMA_FLAG_TC : Transfer Complete flag. 850 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 851 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 852 * @arg DMA_FLAG_ULE : Update linked-list Error flag. 853 * @arg DMA_FLAG_USE : User Setting Error flag. 854 * @arg DMA_FLAG_TO : Trigger Overrun flag. 855 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 856 * @arg DMA_FLAG_IDLEF : Idle flag. 857 * @retval The state of FLAG (SET or RESET). 858 */ 859 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ 860 ((__HANDLE__)->Instance->CSR & (__FLAG__)) 861 862 /** 863 * @brief Clear the DMA Channel pending flags. 864 * @param __HANDLE__ : DMA handle. 865 * @param __FLAG__ : Specifies the flag to clear. 866 * This parameter can be any combination of the following values: 867 * @arg DMA_FLAG_TC : Transfer Complete flag. 868 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 869 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 870 * @arg DMA_FLAG_ULE : Update Linked-List Error flag. 871 * @arg DMA_FLAG_USE : User Setting Error flag. 872 * @arg DMA_FLAG_TO : Trigger Overrun flag. 873 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 874 * @retval None 875 */ 876 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 877 ((__HANDLE__)->Instance->CFCR = (__FLAG__)) 878 879 /** 880 * @brief Enable the specified DMA Channel interrupts. 881 * @param __HANDLE__ : DMA handle. 882 * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. 883 * This parameter can be any combination of the following values: 884 * @arg DMA_IT_TC : Transfer Complete interrupt. 885 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 886 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 887 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 888 * @arg DMA_IT_USE : User Setting Error interrupt. 889 * @arg DMA_IT_TO : Trigger Overrun interrupt. 890 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 891 * @retval None 892 */ 893 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 894 ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 895 896 /** 897 * @brief Disable the specified DMA Channel interrupts. 898 * @param __HANDLE__ : DMA handle. 899 * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. 900 * This parameter can be any combination of the following values: 901 * @arg DMA_IT_TC : Transfer Complete interrupt. 902 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 903 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 904 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 905 * @arg DMA_IT_USE : User Setting Error interrupt. 906 * @arg DMA_IT_TO : Trigger Overrun interrupt. 907 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 908 * @retval None 909 */ 910 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 911 ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 912 913 /** 914 * @brief Checks whether the specified DMA Channel interrupt is enabled or not. 915 * @param __HANDLE__ : DMA handle. 916 * @param __INTERRUPT__ : specifies the DMA interrupt source to check. 917 * @arg DMA_IT_TC : Transfer Complete interrupt. 918 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 919 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 920 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 921 * @arg DMA_IT_USE : User Setting Error interrupt. 922 * @arg DMA_IT_TO : Trigger Overrun interrupt. 923 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 924 * @retval The state of DMA_IT (SET or RESET). 925 */ 926 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 927 (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 928 929 /** 930 * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. 931 * @param __HANDLE__ : DMA handle. 932 * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). 933 */ 934 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ 935 MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) 936 937 /** 938 * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. 939 * @param __HANDLE__ : DMA handle. 940 * @retval The number of remaining data units in the current DMA Stream transfer. 941 */ 942 #define __HAL_DMA_GET_COUNTER(__HANDLE__) \ 943 (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) 944 /** 945 * @} 946 */ 947 948 949 /* Include DMA HAL Extension module */ 950 #include "stm32h5xx_hal_dma_ex.h" 951 952 953 /* Exported functions ------------------------------------------------------------------------------------------------*/ 954 /** @defgroup DMA_Exported_Functions DMA Exported Functions 955 * @brief DMA Exported Functions 956 * @{ 957 */ 958 959 /** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions 960 * @brief Initialization and De-Initialization Functions 961 * @{ 962 */ 963 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); 964 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); 965 /** 966 * @} 967 */ 968 969 /** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions 970 * @brief I/O Operation Functions 971 * @{ 972 */ 973 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, 974 uint32_t SrcAddress, 975 uint32_t DstAddress, 976 uint32_t SrcDataSize); 977 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, 978 uint32_t SrcAddress, 979 uint32_t DstAddress, 980 uint32_t SrcDataSize); 981 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); 982 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); 983 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, 984 HAL_DMA_LevelCompleteTypeDef CompleteLevel, 985 uint32_t Timeout); 986 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); 987 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, 988 HAL_DMA_CallbackIDTypeDef CallbackID, 989 void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); 990 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, 991 HAL_DMA_CallbackIDTypeDef CallbackID); 992 /** 993 * @} 994 */ 995 996 /** @defgroup DMA_Exported_Functions_Group3 State and Error Functions 997 * @brief State and Error Functions 998 * @{ 999 */ 1000 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); 1001 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); 1002 /** 1003 * @} 1004 */ 1005 1006 /** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions 1007 * @brief DMA Attributes Functions 1008 * @{ 1009 */ 1010 1011 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, 1012 uint32_t ChannelAttributes); 1013 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, 1014 uint32_t *const pChannelAttributes); 1015 1016 #if defined (DMA_RCFGLOCKR_LOCK0) 1017 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1018 HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); 1019 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1020 HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, 1021 uint32_t *const pLockState); 1022 1023 #endif /* DMA_RCFGLOCKR_LOCK0 */ 1024 1025 /** 1026 * @} 1027 */ 1028 1029 /** 1030 * @} 1031 */ 1032 1033 1034 /* Private constants -------------------------------------------------------------------------------------------------*/ 1035 /** @defgroup DMA_Private_Constants DMA Private Constants 1036 * @brief DMA Private Constants 1037 * @{ 1038 */ 1039 #define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ 1040 #define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ 1041 #define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ 1042 #define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ 1043 #define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ 1044 #define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ 1045 #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ 1046 #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ 1047 #define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ 1048 #define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ 1049 #define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ 1050 #define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ 1051 /** 1052 * @} 1053 */ 1054 1055 1056 /* Private macros ----------------------------------------------------------------------------------------------------*/ 1057 /** @defgroup DMA_Private_Macros DMA Private Macros 1058 * @brief DMA Private Macros 1059 * @{ 1060 */ 1061 #define GET_DMA_INSTANCE(__HANDLE__) \ 1062 ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) 1063 1064 #define GET_DMA_CHANNEL(__HANDLE__) \ 1065 ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) 1066 1067 #define IS_DMA_MODE(MODE) \ 1068 (((MODE) == DMA_NORMAL) || \ 1069 ((MODE) == DMA_PFCTRL)) 1070 1071 #define IS_DMA_DIRECTION(DIRECTION) \ 1072 (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ 1073 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 1074 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 1075 1076 #define IS_DMA_LEVEL_COMPLETE(LEVEL) \ 1077 (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ 1078 ((LEVEL) == HAL_DMA_HALF_TRANSFER)) 1079 1080 #define IS_DMA_SOURCE_INC(INC) \ 1081 (((INC) == DMA_SINC_FIXED) || \ 1082 ((INC) == DMA_SINC_INCREMENTED)) 1083 1084 #define IS_DMA_DESTINATION_INC(INC) \ 1085 (((INC) == DMA_DINC_FIXED) || \ 1086 ((INC) == DMA_DINC_INCREMENTED)) 1087 1088 #define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ 1089 (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ 1090 ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ 1091 ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)) 1092 1093 #define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ 1094 (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ 1095 ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ 1096 ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)) 1097 1098 #define IS_DMA_BURST_LENGTH(LENGTH) \ 1099 (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ 1100 ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) 1101 1102 #define IS_DMA_PRIORITY(PRIORITY) \ 1103 (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ 1104 ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ 1105 ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ 1106 ((PRIORITY) == DMA_HIGH_PRIORITY)) 1107 1108 #define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ 1109 (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) 1110 1111 #if defined (I3C2) 1112 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_I3C2_RS)) 1113 #else 1114 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM6_UE)) 1115 #endif /* I3C2 */ 1116 1117 #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ 1118 (((MODE) == DMA_BREQ_SINGLE_BURST) || \ 1119 ((MODE) == DMA_BREQ_BLOCK)) 1120 1121 #define IS_DMA_TCEM_EVENT_MODE(MODE) \ 1122 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 1123 ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ 1124 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 1125 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 1126 1127 #define IS_DMA_BLOCK_SIZE(SIZE) \ 1128 (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) 1129 1130 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1131 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 1132 (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ 1133 (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ 1134 (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) 1135 #else 1136 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 1137 (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ 1138 ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) 1139 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1140 1141 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1142 #define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ 1143 (((INSTANCE)->SMISR & (GLOBAL_FLAG))) 1144 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1145 #define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ 1146 (((INSTANCE)->MISR & (GLOBAL_FLAG))) 1147 1148 /** 1149 * @} 1150 */ 1151 1152 1153 /* Private functions -------------------------------------------------------------------------------------------------*/ 1154 /** @defgroup DMA_Private_Functions DMA Private Functions 1155 * @brief DMA Private Functions 1156 * @{ 1157 */ 1158 1159 /** 1160 * @} 1161 */ 1162 1163 /** 1164 * @} 1165 */ 1166 1167 /** 1168 * @} 1169 */ 1170 1171 /** 1172 * @} 1173 */ 1174 1175 #ifdef __cplusplus 1176 } 1177 #endif 1178 1179 #endif /* STM32H5xx_HAL_DMA_H */ 1180
