1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32H5xx_HAL_CORTEX_H 22 #define __STM32H5xx_HAL_CORTEX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_def.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup CORTEX CORTEX 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 45 * @{ 46 */ 47 typedef struct 48 { 49 uint8_t Enable; /*!< Specifies the status of the region. 50 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 51 uint8_t Number; /*!< Specifies the index of the region to protect. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 53 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 54 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 55 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 56 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 57 uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter 58 can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 59 uint8_t DisableExec; /*!< Specifies the instruction access status. 60 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 61 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 62 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 63 } MPU_Region_InitTypeDef; 64 /** 65 * @} 66 */ 67 68 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes 69 * Initialization Structure Definition 70 * @{ 71 */ 72 typedef struct 73 { 74 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 75 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 76 77 uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter 78 can be a combination of @ref CORTEX_MPU_Attributes */ 79 80 } MPU_Attributes_InitTypeDef; 81 /** 82 * @} 83 */ 84 85 86 /** 87 * @} 88 */ 89 90 /* Exported constants --------------------------------------------------------*/ 91 92 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 93 * @{ 94 */ 95 96 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 97 * @{ 98 */ 99 #define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority, 100 4 bits for subpriority */ 101 #define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority, 102 3 bits for subpriority */ 103 #define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority, 104 2 bits for subpriority */ 105 #define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority, 106 1 bit for subpriority */ 107 #define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority, 108 0 bit for subpriority */ 109 /** 110 * @} 111 */ 112 113 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 114 * @{ 115 */ 116 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */ 117 #define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */ 118 #define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */ 119 #define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */ 120 /** 121 * @} 122 */ 123 124 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 125 * @{ 126 */ 127 #define MPU_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers, 128 privileged software access to the default memory map is disabled */ 129 #define MPU_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers, 130 privileged software access to the default memory map is disabled */ 131 #define MPU_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers, 132 privileged software access to the default memory map is enabled */ 133 #define MPU_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers, 134 privileged software access to the default memory map is enabled */ 135 /** 136 * @} 137 */ 138 139 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 140 * @{ 141 */ 142 #define MPU_REGION_ENABLE 1U /*!< MPU region enabled */ 143 #define MPU_REGION_DISABLE 0U /*!< MPU region disabled */ 144 /** 145 * @} 146 */ 147 148 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 149 * @{ 150 */ 151 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< MPU region execution permitted (if read permitted) */ 152 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< MPU region execution not permitted */ 153 /** 154 * @} 155 */ 156 157 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 158 * @{ 159 */ 160 #define MPU_ACCESS_NOT_SHAREABLE 0U /*!< MPU region not shareable */ 161 #define MPU_ACCESS_OUTER_SHAREABLE 1U /*!< MPU region outer shareable */ 162 #define MPU_ACCESS_INNER_SHAREABLE 3U /*!< MPU region inner shareable */ 163 /** 164 * @} 165 */ 166 167 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 168 * @{ 169 */ 170 #define MPU_REGION_PRIV_RW 0U /*!< MPU region Read/write by privileged code only */ 171 #define MPU_REGION_ALL_RW 1U /*!< MPU region Read/write by any privilege level */ 172 #define MPU_REGION_PRIV_RO 2U /*!< MPU region Read-only by privileged code only */ 173 #define MPU_REGION_ALL_RO 3U /*!< MPU region Read-only by any privilege level */ 174 /** 175 * @} 176 */ 177 178 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 179 * @{ 180 */ 181 #define MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */ 182 #define MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */ 183 #define MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */ 184 #define MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */ 185 #define MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */ 186 #define MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */ 187 #define MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */ 188 #define MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */ 189 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 190 #define MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */ 191 #define MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */ 192 #define MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */ 193 #define MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */ 194 #endif /* __ARM_FEATURE_CMSE */ 195 /** 196 * @} 197 */ 198 199 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 200 * @{ 201 */ 202 #define MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */ 203 #define MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */ 204 #define MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */ 205 #define MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */ 206 #define MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */ 207 #define MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */ 208 #define MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */ 209 #define MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */ 210 /** 211 * @} 212 */ 213 214 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 215 * @{ 216 */ 217 #define MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */ 218 #define MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */ 219 #define MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */ 220 #define MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */ 221 222 #define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ 223 #define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ 224 #define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ 225 226 #define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ 227 #define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ 228 229 #define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ 230 #define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ 231 #define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ 232 #define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */ 233 234 /** 235 * @} 236 */ 237 238 /** 239 * @} 240 */ 241 242 /* Exported macros -----------------------------------------------------------*/ 243 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 244 * @{ 245 */ 246 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 247 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 248 249 /** 250 * @} 251 */ 252 253 /* Exported functions --------------------------------------------------------*/ 254 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 255 * @{ 256 */ 257 258 /** @defgroup CORTEX_Exported_Functions_Group1 NVIC functions 259 * @brief NVIC functions 260 * @{ 261 */ 262 /* NVIC functions *****************************/ 263 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 264 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 265 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 266 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 267 void HAL_NVIC_SystemReset(void); 268 uint32_t HAL_NVIC_GetPriorityGrouping(void); 269 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 270 uint32_t *const pSubPriority); 271 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 272 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 273 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 274 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 275 /** 276 * @} 277 */ 278 279 /** @defgroup CORTEX_Exported_Functions_Group2 SYSTICK functions 280 * @brief SYSTICK functions 281 * @{ 282 */ 283 /* SYSTICK functions ***********************************************/ 284 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 285 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 286 void HAL_SYSTICK_IRQHandler(void); 287 void HAL_SYSTICK_Callback(void); 288 /** 289 * @} 290 */ 291 292 /** @defgroup CORTEX_Exported_Functions_Group3 MPU functions 293 * @brief MPU functions 294 * @{ 295 */ 296 /* MPU functions ***********************************************/ 297 void HAL_MPU_Enable(uint32_t MPU_Control); 298 void HAL_MPU_Disable(void); 299 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 300 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 301 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 302 /* MPU_NS Control functions ***********************************************/ 303 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 304 void HAL_MPU_Disable_NS(void); 305 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 306 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 307 #endif /* __ARM_FEATURE_CMSE */ 308 /** 309 * @} 310 */ 311 312 /** 313 * @} 314 */ 315 316 /* Private types -------------------------------------------------------------*/ 317 /* Private variables ---------------------------------------------------------*/ 318 /* Private constants ---------------------------------------------------------*/ 319 /* Private macros ------------------------------------------------------------*/ 320 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 321 * @{ 322 */ 323 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 324 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 325 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 326 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 327 ((GROUP) == NVIC_PRIORITYGROUP_4)) 328 329 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 330 331 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 332 333 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 334 335 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ 336 ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ 337 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ 338 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 339 340 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 341 #define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS)) 342 #endif /* __ARM_FEATURE_CMSE */ 343 344 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 345 ((STATE) == MPU_REGION_DISABLE)) 346 347 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 348 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 349 350 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ 351 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ 352 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 353 354 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ 355 ((TYPE) == MPU_REGION_ALL_RW) || \ 356 ((TYPE) == MPU_REGION_PRIV_RO) || \ 357 ((TYPE) == MPU_REGION_ALL_RO)) 358 359 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 360 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 361 ((NUMBER) == MPU_REGION_NUMBER1) || \ 362 ((NUMBER) == MPU_REGION_NUMBER2) || \ 363 ((NUMBER) == MPU_REGION_NUMBER3) || \ 364 ((NUMBER) == MPU_REGION_NUMBER4) || \ 365 ((NUMBER) == MPU_REGION_NUMBER5) || \ 366 ((NUMBER) == MPU_REGION_NUMBER6) || \ 367 ((NUMBER) == MPU_REGION_NUMBER7) || \ 368 ((NUMBER) == MPU_REGION_NUMBER8) || \ 369 ((NUMBER) == MPU_REGION_NUMBER9) || \ 370 ((NUMBER) == MPU_REGION_NUMBER10)|| \ 371 ((NUMBER) == MPU_REGION_NUMBER11)) 372 #else 373 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 374 ((NUMBER) == MPU_REGION_NUMBER1) || \ 375 ((NUMBER) == MPU_REGION_NUMBER2) || \ 376 ((NUMBER) == MPU_REGION_NUMBER3) || \ 377 ((NUMBER) == MPU_REGION_NUMBER4) || \ 378 ((NUMBER) == MPU_REGION_NUMBER5) || \ 379 ((NUMBER) == MPU_REGION_NUMBER6) || \ 380 ((NUMBER) == MPU_REGION_NUMBER7)) 381 #endif /* __ARM_FEATURE_CMSE */ 382 383 #define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ 384 ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ 385 ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ 386 ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ 387 ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ 388 ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ 389 ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ 390 ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) 391 392 /** 393 * @} 394 */ 395 396 /* Private functions ---------------------------------------------------------*/ 397 398 /** 399 * @} 400 */ 401 402 /** 403 * @} 404 */ 405 406 #ifdef __cplusplus 407 } 408 #endif 409 410 #endif /* __STM32H5xx_HAL_CORTEX_H */ 411 412 413
