1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL UTILS driver contains a set of generic APIs that can be
23 used by user:
24 (+) Device electronic signature
25 (+) Timing functions
26 (+) PLL configuration functions
27
28 @endverbatim
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32G4xx_LL_UTILS_H
33 #define STM32G4xx_LL_UTILS_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32g4xx.h"
41
42 /** @addtogroup STM32G4xx_LL_Driver
43 * @{
44 */
45
46 /** @defgroup UTILS_LL UTILS
47 * @{
48 */
49
50 /* Private types -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52
53 /* Private constants ---------------------------------------------------------*/
54 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
55 * @{
56 */
57
58 /* Max delay can be used in LL_mDelay */
59 #define LL_MAX_DELAY 0xFFFFFFFFU
60
61 /**
62 * @brief Unique device ID register base address
63 */
64 #define UID_BASE_ADDRESS UID_BASE
65
66 /**
67 * @brief Flash size data register base address
68 */
69 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
70
71 /**
72 * @brief Package data register base address
73 */
74 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
75
76 /**
77 * @}
78 */
79
80 /* Private macros ------------------------------------------------------------*/
81 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
82 * @{
83 */
84 /**
85 * @}
86 */
87 /* Exported types ------------------------------------------------------------*/
88 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
89 * @{
90 */
91 /**
92 * @brief UTILS PLL structure definition
93 */
94 typedef struct
95 {
96 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
97 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
98
99 This feature can be modified afterwards using unitary function
100 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
101
102 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
103 This parameter must be a number between Min_Data = 8 and Max_Data = 86
104
105 This feature can be modified afterwards using unitary function
106 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
107
108 uint32_t PLLR; /*!< Division for the main system clock.
109 This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
110
111 This feature can be modified afterwards using unitary function
112 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
113 } LL_UTILS_PLLInitTypeDef;
114
115 /**
116 * @brief UTILS System, AHB and APB buses clock configuration structure definition
117 */
118 typedef struct
119 {
120 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
121 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
122
123 This feature can be modified afterwards using unitary function
124 @ref LL_RCC_SetAHBPrescaler(). */
125
126 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
127 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
128
129 This feature can be modified afterwards using unitary function
130 @ref LL_RCC_SetAPB1Prescaler(). */
131
132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
133 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
134
135 This feature can be modified afterwards using unitary function
136 @ref LL_RCC_SetAPB2Prescaler(). */
137
138 } LL_UTILS_ClkInitTypeDef;
139
140 /**
141 * @}
142 */
143
144 /* Exported constants --------------------------------------------------------*/
145 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
146 * @{
147 */
148
149 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
150 * @{
151 */
152 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
153 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
154 /**
155 * @}
156 */
157
158 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
159 * @{
160 */
161 #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
162 #define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */
163 #if defined (STM32G411xB) || defined (STM32G411xC) || defined (STM32G431xx) || defined (STM32G414xx) || defined (STM32G441xx) || \
164 defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || defined (STM32G484xx)
165 #define LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 0x00000002U /*!< LQFP100 \ LQFP80 package type */
166 #define LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 /*!< For backward compatibility */
167 #else
168 #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
169 #endif /* STM32G411xB || STM32G411xC || STM32G431xx || STM32G414xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
170 #define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */
171 #define LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 0x00000007U /*!< LQFP128 \ UFBGA121 package type */
172 #define LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 /*!< For backward compatibility */
173 #define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */
174 #define LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U /*!< LQFP32 package type */
175 #define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */
176 #define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */
177 #define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */
178 #define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */
179 #define LL_UTILS_PACKAGETYPE_TFBGA100 0x0000000EU /*!< TFBGA100 package type */
180 #define LL_UTILS_PACKAGETYPE_UFBGA100 LL_UTILS_PACKAGETYPE_TFBGA100 /*!< For backward compatibility */
181 #define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U /*!< LQFP48 EBIKE package type */
182 #if defined (STM32G491xx) || defined (STM32G4A1xx)
183 #define LL_UTILS_PACKAGETYPE_LQFP80 0x00000011U /*!< LQFP80 package type */
184 #endif /* STM32G491xx || STM32G4A1xx */
185
186 /**
187 * @}
188 */
189
190 /**
191 * @}
192 */
193
194 /* Exported macro ------------------------------------------------------------*/
195
196 /* Exported functions --------------------------------------------------------*/
197 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
198 * @{
199 */
200
201 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
202 * @{
203 */
204
205 /**
206 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
207 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
208 */
LL_GetUID_Word0(void)209 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
210 {
211 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
212 }
213
214 /**
215 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
216 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
217 */
LL_GetUID_Word1(void)218 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
219 {
220 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
221 }
222
223 /**
224 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
225 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
226 */
LL_GetUID_Word2(void)227 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
228 {
229 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
230 }
231
232 /**
233 * @brief Get Flash memory size
234 * @note This bitfield indicates the size of the device Flash memory expressed in
235 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
236 * @retval FLASH_SIZE[15:0]: Flash memory size
237 */
LL_GetFlashSize(void)238 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
239 {
240 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
241 }
242
243 /**
244 * @brief Get Package type
245 * @retval Returned value can be one of the following values:
246 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
247 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
248 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP81
249 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP128
250 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
251 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP32
252 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
253 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
254 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49
255 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64
256 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
257 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
258 *
259 */
LL_GetPackageType(void)260 __STATIC_INLINE uint32_t LL_GetPackageType(void)
261 {
262 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
263 }
264
265 /**
266 * @}
267 */
268
269 /** @defgroup UTILS_LL_EF_DELAY DELAY
270 * @{
271 */
272
273 /**
274 * @brief This function configures the Cortex-M SysTick source of the time base.
275 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
276 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
277 * configuration by calling this function, for a delay use rather osDelay RTOS service.
278 * @param Ticks Frequency of Ticks (Hz)
279 * @retval None
280 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)281 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
282 {
283 /* Configure the SysTick to have interrupt in 1ms time base */
284 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
285 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
286 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
287 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
288 }
289
290 void LL_Init1msTick(uint32_t HCLKFrequency);
291 void LL_mDelay(uint32_t Delay);
292
293 /**
294 * @}
295 */
296
297 /** @defgroup UTILS_EF_SYSTEM SYSTEM
298 * @{
299 */
300
301 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
302 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
303 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
304 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
305 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
306 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
307
308 /**
309 * @}
310 */
311
312 /**
313 * @}
314 */
315
316 /**
317 * @}
318 */
319
320 /**
321 * @}
322 */
323
324 #ifdef __cplusplus
325 }
326 #endif
327
328 #endif /* STM32G4xx_LL_UTILS_H */
329
330
