1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef STM32G4xx_LL_RCC_H
20 #define STM32G4xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32g4xx.h"
28
29 /** @addtogroup STM32G4xx_LL_Driver
30 * @{
31 */
32
33 /** @defgroup RCC_LL RCC
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
40 * @{
41 */
42
43 /**
44 * @}
45 */
46
47 /* Private constants ---------------------------------------------------------*/
48 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
49 * @{
50 */
51 /* Defines used to perform offsets*/
52 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
53 #define RCC_OFFSET_CCIPR 0U
54 #define RCC_OFFSET_CCIPR2 0x14U
55
56 /**
57 * @}
58 */
59
60 /* Private macros ------------------------------------------------------------*/
61 #if defined(USE_FULL_LL_DRIVER)
62 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
63 * @{
64 */
65 /**
66 * @}
67 */
68 #endif /*USE_FULL_LL_DRIVER*/
69
70 /* Exported types ------------------------------------------------------------*/
71 #if defined(USE_FULL_LL_DRIVER)
72 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
73 * @{
74 */
75
76 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
77 * @{
78 */
79
80 /**
81 * @brief RCC Clocks Frequency Structure
82 */
83 typedef struct
84 {
85 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
86 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
87 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
88 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
89 } LL_RCC_ClocksTypeDef;
90
91 /**
92 * @}
93 */
94
95 /**
96 * @}
97 */
98 #endif /* USE_FULL_LL_DRIVER */
99
100 /* Exported constants --------------------------------------------------------*/
101 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
102 * @{
103 */
104
105 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
106 * @brief Defines used to adapt values of different oscillators
107 * @note These values could be modified in the user environment according to
108 * HW set-up.
109 * @{
110 */
111 #if !defined (HSE_VALUE)
112 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
113 #endif /* HSE_VALUE */
114
115 #if !defined (HSI_VALUE)
116 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
117 #endif /* HSI_VALUE */
118
119 #if !defined (LSE_VALUE)
120 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
121 #endif /* LSE_VALUE */
122
123 #if !defined (LSI_VALUE)
124 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
125 #endif /* LSI_VALUE */
126
127 #if !defined (HSI48_VALUE)
128 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
129 #endif /* HSI48_VALUE */
130
131 #if !defined (EXTERNAL_CLOCK_VALUE)
132 #define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN, I2S and SAI1 external clock source in Hz */
133 #endif /* EXTERNAL_CLOCK_VALUE */
134
135 /**
136 * @}
137 */
138
139 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
140 * @brief Flags defines which can be used with LL_RCC_WriteReg function
141 * @{
142 */
143 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
144 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
145 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
146 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
147 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
148 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
149 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
150 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
151 /**
152 * @}
153 */
154
155 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
156 * @brief Flags defines which can be used with LL_RCC_ReadReg function
157 * @{
158 */
159 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
160 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
161 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
162 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
163 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
164 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
165 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
166 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
167 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
168 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
169 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
170 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
171 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
172 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
173 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
174 /**
175 * @}
176 */
177
178 /** @defgroup RCC_LL_EC_IT IT Defines
179 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
180 * @{
181 */
182 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
183 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
184 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
185 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
186 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
187 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
188 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
189 /**
190 * @}
191 */
192
193 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
194 * @{
195 */
196 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
197 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
198 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
199 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
200 /**
201 * @}
202 */
203
204 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
205 * @{
206 */
207 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
208 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
209 /**
210 * @}
211 */
212
213 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
214 * @{
215 */
216 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
217 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
218 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
219 /**
220 * @}
221 */
222
223 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
224 * @{
225 */
226 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
227 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
228 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
229 /**
230 * @}
231 */
232
233 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
234 * @{
235 */
236 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
237 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
238 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
239 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
240 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
241 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
242 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
243 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
244 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
245 /**
246 * @}
247 */
248
249 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
250 * @{
251 */
252 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
253 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
254 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
255 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
256 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
257 /**
258 * @}
259 */
260
261 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
262 * @{
263 */
264 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
265 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
266 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
267 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
268 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
269 /**
270 * @}
271 */
272
273 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
274 * @{
275 */
276 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
277 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
278 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
279 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
280 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
281 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
282 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
283 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
284 /**
285 * @}
286 */
287
288 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
289 * @{
290 */
291 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
292 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
293 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
294 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
295 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
296 /**
297 * @}
298 */
299
300 #if defined(USE_FULL_LL_DRIVER)
301 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
302 * @{
303 */
304 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
305 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
306 /**
307 * @}
308 */
309 #endif /* USE_FULL_LL_DRIVER */
310
311 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
312 * @{
313 */
314 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
315 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
316 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
317 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
318 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
319 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
320 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
321 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
322 #if defined(RCC_CCIPR_USART3SEL)
323 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
324 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
325 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
326 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
327 #endif /* RCC_CCIPR_USART3SEL */
328 /**
329 * @}
330 */
331
332 /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
333 * @{
334 */
335 #if defined(RCC_CCIPR_UART4SEL)
336 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
337 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
338 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
339 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
340 #endif /* RCC_CCIPR_UART4SEL */
341 #if defined(RCC_CCIPR_UART5SEL)
342 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
343 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
344 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
345 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
346 #endif /* RCC_CCIPR_UART5SEL */
347 /**
348 * @}
349 */
350
351 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
352 * @{
353 */
354 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
355 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
356 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
357 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
358 /**
359 * @}
360 */
361
362 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
363 * @{
364 */
365 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
366 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
367 #define LL_RCC_I2C1_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
368 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
369 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
370 #define LL_RCC_I2C2_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
371 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
372 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
373 #define LL_RCC_I2C3_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
374 #if defined(RCC_CCIPR2_I2C4SEL)
375 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
376 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
377 #define LL_RCC_I2C4_CLKSOURCE_HSI (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
378 #endif /* RCC_CCIPR2_I2C4SEL */
379 /**
380 * @}
381 */
382
383 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
384 * @{
385 */
386 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock source */
387 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock used as LPTIM1 clock source */
388 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock used as LPTIM1 clock source */
389 #define LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE clock used as LPTIM1 clock source */
390 /**
391 * @}
392 */
393
394 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
395 * @{
396 */
397 #define LL_RCC_SAI1_CLKSOURCE_SYSCLK 0x00000000U /*!< System clock used as SAI1 clock source */
398 #define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL clock used as SAI1 clock source */
399 #define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL_1 /*!< EXT clock used as SAI1 clock source */
400 #define LL_RCC_SAI1_CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1) /*!< HSI clock used as SAI1 clock source */
401 /**
402 * @}
403 */
404
405 /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
406 * @{
407 */
408 #define LL_RCC_I2S_CLKSOURCE_SYSCLK 0x00000000U /*!< System clock used as I2S clock source */
409 #define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 /*!< PLL clock used as I2S clock source */
410 #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2S23SEL_1 /*!< EXT clock used as I2S clock source */
411 #define LL_RCC_I2S_CLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1) /*!< HSI clock used as I2S clock source */
412 /**
413 * @}
414 */
415
416 #if defined(FDCAN1)
417 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
418 * @{
419 */
420 #define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN clock source */
421 #define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 /*!< PLL clock used as FDCAN clock source */
422 #define LL_RCC_FDCAN_CLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 /*!< PCLK1 clock used as FDCAN clock source */
423 /**
424 * @}
425 */
426 #endif /* FDCAN1 */
427
428 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
429 * @{
430 */
431 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
432 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
433 /**
434 * @}
435 */
436
437 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
438 * @{
439 */
440 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
441 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
442 /**
443 * @}
444 */
445
446 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
447 * @{
448 */
449 #define LL_RCC_ADC12_CLKSOURCE_NONE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U)) /*!< No clock used as ADC12 clock source */
450 #define LL_RCC_ADC12_CLKSOURCE_PLL (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< PLL clock used as ADC12 clock source */
451 #define LL_RCC_ADC12_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< SYSCLK clock used as ADC12 clock source */
452 #if defined(RCC_CCIPR_ADC345SEL)
453 #define LL_RCC_ADC345_CLKSOURCE_NONE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U)) /*!< No clock used as ADC345 clock source */
454 #define LL_RCC_ADC345_CLKSOURCE_PLL (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_0 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */
455 #define LL_RCC_ADC345_CLKSOURCE_SYSCLK (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_1 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */
456 #endif /* RCC_CCIPR_ADC345SEL */
457 /**
458 * @}
459 */
460
461 /** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
462 * @{
463 */
464 #define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as QuadSPI clock source */
465 #define LL_RCC_QUADSPI_CLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 /*!< HSI used as QuadSPI clock source */
466 #define LL_RCC_QUADSPI_CLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 /*!< PLL used as QuadSPI clock source */
467 /**
468 * @}
469 */
470
471
472 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
473 * @{
474 */
475 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
476 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
477 #if defined(RCC_CCIPR_USART3SEL)
478 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
479 #endif /* RCC_CCIPR_USART3SEL */
480 /**
481 * @}
482 */
483
484 /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
485 * @{
486 */
487 #if defined(RCC_CCIPR_UART4SEL)
488 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
489 #endif /* RCC_CCIPR_UART4SEL */
490 #if defined(RCC_CCIPR_UART5SEL)
491 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
492 #endif /* RCC_CCIPR_UART5SEL */
493 /**
494 * @}
495 */
496
497 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
498 * @{
499 */
500 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
501 /**
502 * @}
503 */
504
505 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
506 * @{
507 */
508 #define LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
509 #define LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
510 #if defined(RCC_CCIPR_I2C3SEL)
511 #define LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
512 #endif /* RCC_CCIPR_I2C3SEL */
513 #if defined(RCC_CCIPR2_I2C4SEL)
514 #define LL_RCC_I2C4_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
515 #endif /* RCC_CCIPR2_I2C4SEL */
516 /**
517 * @}
518 */
519
520 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
521 * @{
522 */
523 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
524 /**
525 * @}
526 */
527
528 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
529 * @{
530 */
531 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
532 /**
533 * @}
534 */
535
536 /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
537 * @{
538 */
539 #define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2S23SEL /*!< I2S Clock source selection */
540 /**
541 * @}
542 */
543
544 #if defined(FDCAN1)
545 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
546 * @{
547 */
548 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR_FDCANSEL /*!< FDCAN Clock source selection */
549 #endif /* FDCAN1 */
550
551 /**
552 * @}
553 */
554
555 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
556 * @{
557 */
558 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
559 /**
560 * @}
561 */
562
563 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
564 * @{
565 */
566 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
567 /**
568 * @}
569 */
570
571 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
572 * @{
573 */
574 #define LL_RCC_ADC12_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos)) /*!< ADC12 Clock source selection */
575 #if defined(RCC_CCIPR_ADC345SEL_Pos)
576 #define LL_RCC_ADC345_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL >> RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */
577 #endif /* RCC_CCIPR_ADC345SEL_Pos */
578 /**
579 * @}
580 */
581
582 /** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
583 * @{
584 */
585 #define LL_RCC_QUADSPI_CLKSOURCE RCC_CCIPR2_QSPISEL /*!< QuadSPI Clock source selection */
586 /**
587 * @}
588 */
589
590 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
591 * @{
592 */
593 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
594 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
595 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
596 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
597 /**
598 * @}
599 */
600
601
602 /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
603 * @{
604 */
605 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
606 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
607 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
608 /**
609 * @}
610 */
611
612 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
613 * @{
614 */
615 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
616 #define LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0 /*!< PLL division factor by 2 */
617 #define LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1 /*!< PLL division factor by 3 */
618 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 4 */
619 #define LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2 /*!< PLL division factor by 5 */
620 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 6 */
621 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 7 */
622 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 8 */
623 #define LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3 /*!< PLL division factor by 9 */
624 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 10 */
625 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 11 */
626 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 12 */
627 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 13 */
628 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 14 */
629 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 15 */
630 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 16 */
631 /**
632 * @}
633 */
634
635 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
636 * @{
637 */
638 #define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
639 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
640 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
641 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
642 /**
643 * @}
644 */
645
646 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
647 * @{
648 */
649 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
650 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
651 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
652 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
653 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
654 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
655 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
656 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
657 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
658 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
659 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
660 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
661 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
662 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
663 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
664 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
665 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
666 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
667 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
668 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
669 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
670 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
671 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
672 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
673 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
674 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
675 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
676 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
677 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
678 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
679 /**
680 * @}
681 */
682
683 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
684 * @{
685 */
686 #define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
687 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
688 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
689 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
690 /**
691 * @}
692 */
693
694 /**
695 * @}
696 */
697
698 /* Exported macro ------------------------------------------------------------*/
699 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
700 * @{
701 */
702
703 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
704 * @{
705 */
706
707 /**
708 * @brief Write a value in RCC register
709 * @param __REG__ Register to be written
710 * @param __VALUE__ Value to be written in the register
711 * @retval None
712 */
713 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
714
715 /**
716 * @brief Read a value in RCC register
717 * @param __REG__ Register to be read
718 * @retval Register value
719 */
720 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
721 /**
722 * @}
723 */
724
725 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
726 * @{
727 */
728
729 /**
730 * @brief Helper macro to calculate the PLLCLK frequency on system domain
731 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
732 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
733 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
734 * @param __PLLM__ This parameter can be one of the following values:
735 * @arg @ref LL_RCC_PLLM_DIV_1
736 * @arg @ref LL_RCC_PLLM_DIV_2
737 * @arg @ref LL_RCC_PLLM_DIV_3
738 * @arg @ref LL_RCC_PLLM_DIV_4
739 * @arg @ref LL_RCC_PLLM_DIV_5
740 * @arg @ref LL_RCC_PLLM_DIV_6
741 * @arg @ref LL_RCC_PLLM_DIV_7
742 * @arg @ref LL_RCC_PLLM_DIV_8
743 * @arg @ref LL_RCC_PLLM_DIV_9
744 * @arg @ref LL_RCC_PLLM_DIV_10
745 * @arg @ref LL_RCC_PLLM_DIV_11
746 * @arg @ref LL_RCC_PLLM_DIV_12
747 * @arg @ref LL_RCC_PLLM_DIV_13
748 * @arg @ref LL_RCC_PLLM_DIV_14
749 * @arg @ref LL_RCC_PLLM_DIV_15
750 * @arg @ref LL_RCC_PLLM_DIV_16
751 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
752 * @param __PLLR__ This parameter can be one of the following values:
753 * @arg @ref LL_RCC_PLLR_DIV_2
754 * @arg @ref LL_RCC_PLLR_DIV_4
755 * @arg @ref LL_RCC_PLLR_DIV_6
756 * @arg @ref LL_RCC_PLLR_DIV_8
757 * @retval PLL clock frequency (in Hz)
758 */
759 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
760 ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
761
762 /**
763 * @brief Helper macro to calculate the PLLCLK frequency used on ADC domain
764 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
765 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
766 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
767 * @param __PLLM__ This parameter can be one of the following values:
768 * @arg @ref LL_RCC_PLLM_DIV_1
769 * @arg @ref LL_RCC_PLLM_DIV_2
770 * @arg @ref LL_RCC_PLLM_DIV_3
771 * @arg @ref LL_RCC_PLLM_DIV_4
772 * @arg @ref LL_RCC_PLLM_DIV_5
773 * @arg @ref LL_RCC_PLLM_DIV_6
774 * @arg @ref LL_RCC_PLLM_DIV_7
775 * @arg @ref LL_RCC_PLLM_DIV_8
776 * @arg @ref LL_RCC_PLLM_DIV_9
777 * @arg @ref LL_RCC_PLLM_DIV_10
778 * @arg @ref LL_RCC_PLLM_DIV_11
779 * @arg @ref LL_RCC_PLLM_DIV_12
780 * @arg @ref LL_RCC_PLLM_DIV_13
781 * @arg @ref LL_RCC_PLLM_DIV_14
782 * @arg @ref LL_RCC_PLLM_DIV_15
783 * @arg @ref LL_RCC_PLLM_DIV_16
784
785 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
786 * @param __PLLP__ This parameter can be one of the following values:
787 * @arg @ref LL_RCC_PLLP_DIV_2
788 * @arg @ref LL_RCC_PLLP_DIV_3
789 * @arg @ref LL_RCC_PLLP_DIV_4
790 * @arg @ref LL_RCC_PLLP_DIV_5
791 * @arg @ref LL_RCC_PLLP_DIV_6
792 * @arg @ref LL_RCC_PLLP_DIV_7
793 * @arg @ref LL_RCC_PLLP_DIV_8
794 * @arg @ref LL_RCC_PLLP_DIV_9
795 * @arg @ref LL_RCC_PLLP_DIV_10
796 * @arg @ref LL_RCC_PLLP_DIV_11
797 * @arg @ref LL_RCC_PLLP_DIV_12
798 * @arg @ref LL_RCC_PLLP_DIV_13
799 * @arg @ref LL_RCC_PLLP_DIV_14
800 * @arg @ref LL_RCC_PLLP_DIV_15
801 * @arg @ref LL_RCC_PLLP_DIV_16
802 * @arg @ref LL_RCC_PLLP_DIV_17
803 * @arg @ref LL_RCC_PLLP_DIV_18
804 * @arg @ref LL_RCC_PLLP_DIV_19
805 * @arg @ref LL_RCC_PLLP_DIV_20
806 * @arg @ref LL_RCC_PLLP_DIV_21
807 * @arg @ref LL_RCC_PLLP_DIV_22
808 * @arg @ref LL_RCC_PLLP_DIV_23
809 * @arg @ref LL_RCC_PLLP_DIV_24
810 * @arg @ref LL_RCC_PLLP_DIV_25
811 * @arg @ref LL_RCC_PLLP_DIV_26
812 * @arg @ref LL_RCC_PLLP_DIV_27
813 * @arg @ref LL_RCC_PLLP_DIV_28
814 * @arg @ref LL_RCC_PLLP_DIV_29
815 * @arg @ref LL_RCC_PLLP_DIV_30
816 * @arg @ref LL_RCC_PLLP_DIV_31
817 * @retval PLL clock frequency (in Hz)
818 */
819 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
820 ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
821
822 /**
823 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
824 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
825 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
826 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
827 * @param __PLLM__ This parameter can be one of the following values:
828 * @arg @ref LL_RCC_PLLM_DIV_1
829 * @arg @ref LL_RCC_PLLM_DIV_2
830 * @arg @ref LL_RCC_PLLM_DIV_3
831 * @arg @ref LL_RCC_PLLM_DIV_4
832 * @arg @ref LL_RCC_PLLM_DIV_5
833 * @arg @ref LL_RCC_PLLM_DIV_6
834 * @arg @ref LL_RCC_PLLM_DIV_7
835 * @arg @ref LL_RCC_PLLM_DIV_8
836 * @arg @ref LL_RCC_PLLM_DIV_9
837 * @arg @ref LL_RCC_PLLM_DIV_10
838 * @arg @ref LL_RCC_PLLM_DIV_11
839 * @arg @ref LL_RCC_PLLM_DIV_12
840 * @arg @ref LL_RCC_PLLM_DIV_13
841 * @arg @ref LL_RCC_PLLM_DIV_14
842 * @arg @ref LL_RCC_PLLM_DIV_15
843 * @arg @ref LL_RCC_PLLM_DIV_16
844 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
845 * @param __PLLQ__ This parameter can be one of the following values:
846 * @arg @ref LL_RCC_PLLQ_DIV_2
847 * @arg @ref LL_RCC_PLLQ_DIV_4
848 * @arg @ref LL_RCC_PLLQ_DIV_6
849 * @arg @ref LL_RCC_PLLQ_DIV_8
850 * @retval PLL clock frequency (in Hz)
851 */
852 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
853 ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
854
855 /**
856 * @brief Helper macro to calculate the HCLK frequency
857 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
858 * @param __AHBPRESCALER__ This parameter can be one of the following values:
859 * @arg @ref LL_RCC_SYSCLK_DIV_1
860 * @arg @ref LL_RCC_SYSCLK_DIV_2
861 * @arg @ref LL_RCC_SYSCLK_DIV_4
862 * @arg @ref LL_RCC_SYSCLK_DIV_8
863 * @arg @ref LL_RCC_SYSCLK_DIV_16
864 * @arg @ref LL_RCC_SYSCLK_DIV_64
865 * @arg @ref LL_RCC_SYSCLK_DIV_128
866 * @arg @ref LL_RCC_SYSCLK_DIV_256
867 * @arg @ref LL_RCC_SYSCLK_DIV_512
868 * @retval HCLK clock frequency (in Hz)
869 */
870 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
871
872 /**
873 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
874 * @param __HCLKFREQ__ HCLK frequency
875 * @param __APB1PRESCALER__ This parameter can be one of the following values:
876 * @arg @ref LL_RCC_APB1_DIV_1
877 * @arg @ref LL_RCC_APB1_DIV_2
878 * @arg @ref LL_RCC_APB1_DIV_4
879 * @arg @ref LL_RCC_APB1_DIV_8
880 * @arg @ref LL_RCC_APB1_DIV_16
881 * @retval PCLK1 clock frequency (in Hz)
882 */
883 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))
884
885 /**
886 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
887 * @param __HCLKFREQ__ HCLK frequency
888 * @param __APB2PRESCALER__ This parameter can be one of the following values:
889 * @arg @ref LL_RCC_APB2_DIV_1
890 * @arg @ref LL_RCC_APB2_DIV_2
891 * @arg @ref LL_RCC_APB2_DIV_4
892 * @arg @ref LL_RCC_APB2_DIV_8
893 * @arg @ref LL_RCC_APB2_DIV_16
894 * @retval PCLK2 clock frequency (in Hz)
895 */
896 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))
897
898 /**
899 * @}
900 */
901
902 /**
903 * @}
904 */
905
906 /* Exported functions --------------------------------------------------------*/
907 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
908 * @{
909 */
910
911 /** @defgroup RCC_LL_EF_HSE HSE
912 * @{
913 */
914
915 /**
916 * @brief Enable the Clock Security System.
917 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
918 * @retval None
919 */
LL_RCC_HSE_EnableCSS(void)920 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
921 {
922 SET_BIT(RCC->CR, RCC_CR_CSSON);
923 }
924
925 /**
926 * @brief Enable HSE external oscillator (HSE Bypass)
927 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
928 * @retval None
929 */
LL_RCC_HSE_EnableBypass(void)930 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
931 {
932 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
933 }
934
935 /**
936 * @brief Disable HSE external oscillator (HSE Bypass)
937 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
938 * @retval None
939 */
LL_RCC_HSE_DisableBypass(void)940 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
941 {
942 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
943 }
944
945 /**
946 * @brief Enable HSE crystal oscillator (HSE ON)
947 * @rmtoll CR HSEON LL_RCC_HSE_Enable
948 * @retval None
949 */
LL_RCC_HSE_Enable(void)950 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
951 {
952 SET_BIT(RCC->CR, RCC_CR_HSEON);
953 }
954
955 /**
956 * @brief Disable HSE crystal oscillator (HSE ON)
957 * @rmtoll CR HSEON LL_RCC_HSE_Disable
958 * @retval None
959 */
LL_RCC_HSE_Disable(void)960 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
961 {
962 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
963 }
964
965 /**
966 * @brief Check if HSE oscillator Ready
967 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
968 * @retval State of bit (1 or 0).
969 */
LL_RCC_HSE_IsReady(void)970 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
971 {
972 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
973 }
974
975 /**
976 * @}
977 */
978
979 /** @defgroup RCC_LL_EF_HSI HSI
980 * @{
981 */
982
983 /**
984 * @brief Enable HSI even in stop mode
985 * @note HSI oscillator is forced ON even in Stop mode
986 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
987 * @retval None
988 */
LL_RCC_HSI_EnableInStopMode(void)989 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
990 {
991 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
992 }
993
994 /**
995 * @brief Disable HSI in stop mode
996 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
997 * @retval None
998 */
LL_RCC_HSI_DisableInStopMode(void)999 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1000 {
1001 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1002 }
1003
1004 /**
1005 * @brief Enable HSI oscillator
1006 * @rmtoll CR HSION LL_RCC_HSI_Enable
1007 * @retval None
1008 */
LL_RCC_HSI_Enable(void)1009 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1010 {
1011 SET_BIT(RCC->CR, RCC_CR_HSION);
1012 }
1013
1014 /**
1015 * @brief Disable HSI oscillator
1016 * @rmtoll CR HSION LL_RCC_HSI_Disable
1017 * @retval None
1018 */
LL_RCC_HSI_Disable(void)1019 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1020 {
1021 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1022 }
1023
1024 /**
1025 * @brief Check if HSI clock is ready
1026 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1027 * @retval State of bit (1 or 0).
1028 */
LL_RCC_HSI_IsReady(void)1029 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1030 {
1031 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1032 }
1033
1034 /**
1035 * @brief Get HSI Calibration value
1036 * @note When HSITRIM is written, HSICAL is updated with the sum of
1037 * HSITRIM and the factory trim value
1038 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1039 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1040 */
LL_RCC_HSI_GetCalibration(void)1041 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1042 {
1043 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1044 }
1045
1046 /**
1047 * @brief Set HSI Calibration trimming
1048 * @note user-programmable trimming value that is added to the HSICAL
1049 * @note Default value is 16, which, when added to the HSICAL value,
1050 * should trim the HSI to 16 MHz +/- 1 %
1051 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1052 * @param Value Between Min_Data = 0 and Max_Data = 127
1053 * @retval None
1054 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1055 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1056 {
1057 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1058 }
1059
1060 /**
1061 * @brief Get HSI Calibration trimming
1062 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1063 * @retval Between Min_Data = 0 and Max_Data = 127
1064 */
LL_RCC_HSI_GetCalibTrimming(void)1065 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1066 {
1067 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1068 }
1069
1070 /**
1071 * @}
1072 */
1073
1074 /** @defgroup RCC_LL_EF_HSI48 HSI48
1075 * @{
1076 */
1077
1078 /**
1079 * @brief Enable HSI48
1080 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
1081 * @retval None
1082 */
LL_RCC_HSI48_Enable(void)1083 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1084 {
1085 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1086 }
1087
1088 /**
1089 * @brief Disable HSI48
1090 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
1091 * @retval None
1092 */
LL_RCC_HSI48_Disable(void)1093 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1094 {
1095 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1096 }
1097
1098 /**
1099 * @brief Check if HSI48 oscillator Ready
1100 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
1101 * @retval State of bit (1 or 0).
1102 */
LL_RCC_HSI48_IsReady(void)1103 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1104 {
1105 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
1106 }
1107
1108 /**
1109 * @brief Get HSI48 Calibration value
1110 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1111 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1112 */
LL_RCC_HSI48_GetCalibration(void)1113 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1114 {
1115 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1116 }
1117
1118 /**
1119 * @}
1120 */
1121
1122 /** @defgroup RCC_LL_EF_LSE LSE
1123 * @{
1124 */
1125
1126 /**
1127 * @brief Enable Low Speed External (LSE) crystal.
1128 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1129 * @retval None
1130 */
LL_RCC_LSE_Enable(void)1131 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1132 {
1133 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1134 }
1135
1136 /**
1137 * @brief Disable Low Speed External (LSE) crystal.
1138 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1139 * @retval None
1140 */
LL_RCC_LSE_Disable(void)1141 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1142 {
1143 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1144 }
1145
1146 /**
1147 * @brief Enable external clock source (LSE bypass).
1148 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1149 * @retval None
1150 */
LL_RCC_LSE_EnableBypass(void)1151 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1152 {
1153 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1154 }
1155
1156 /**
1157 * @brief Disable external clock source (LSE bypass).
1158 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1159 * @retval None
1160 */
LL_RCC_LSE_DisableBypass(void)1161 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1162 {
1163 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1164 }
1165
1166 /**
1167 * @brief Set LSE oscillator drive capability
1168 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1169 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1170 * @param LSEDrive This parameter can be one of the following values:
1171 * @arg @ref LL_RCC_LSEDRIVE_LOW
1172 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1173 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1174 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1175 * @retval None
1176 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1177 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1178 {
1179 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1180 }
1181
1182 /**
1183 * @brief Get LSE oscillator drive capability
1184 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1185 * @retval Returned value can be one of the following values:
1186 * @arg @ref LL_RCC_LSEDRIVE_LOW
1187 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1188 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1189 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1190 */
LL_RCC_LSE_GetDriveCapability(void)1191 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1192 {
1193 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1194 }
1195
1196 /**
1197 * @brief Enable Clock security system on LSE.
1198 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1199 * @retval None
1200 */
LL_RCC_LSE_EnableCSS(void)1201 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1202 {
1203 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1204 }
1205
1206 /**
1207 * @brief Disable Clock security system on LSE.
1208 * @note Clock security system can be disabled only after a LSE
1209 * failure detection. In that case it MUST be disabled by software.
1210 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1211 * @retval None
1212 */
LL_RCC_LSE_DisableCSS(void)1213 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1214 {
1215 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1216 }
1217
1218 /**
1219 * @brief Check if LSE oscillator Ready
1220 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1221 * @retval State of bit (1 or 0).
1222 */
LL_RCC_LSE_IsReady(void)1223 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1224 {
1225 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1226 }
1227
1228 /**
1229 * @brief Check if CSS on LSE failure Detection
1230 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1231 * @retval State of bit (1 or 0).
1232 */
LL_RCC_LSE_IsCSSDetected(void)1233 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1234 {
1235 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1236 }
1237
1238 /**
1239 * @}
1240 */
1241
1242 /** @defgroup RCC_LL_EF_LSI LSI
1243 * @{
1244 */
1245
1246 /**
1247 * @brief Enable LSI Oscillator
1248 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1249 * @retval None
1250 */
LL_RCC_LSI_Enable(void)1251 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1252 {
1253 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1254 }
1255
1256 /**
1257 * @brief Disable LSI Oscillator
1258 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1259 * @retval None
1260 */
LL_RCC_LSI_Disable(void)1261 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1262 {
1263 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1264 }
1265
1266 /**
1267 * @brief Check if LSI is Ready
1268 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1269 * @retval State of bit (1 or 0).
1270 */
LL_RCC_LSI_IsReady(void)1271 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1272 {
1273 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
1274 }
1275
1276 /**
1277 * @}
1278 */
1279
1280 /** @defgroup RCC_LL_EF_LSCO LSCO
1281 * @{
1282 */
1283
1284 /**
1285 * @brief Enable Low speed clock
1286 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1287 * @retval None
1288 */
LL_RCC_LSCO_Enable(void)1289 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1290 {
1291 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1292 }
1293
1294 /**
1295 * @brief Disable Low speed clock
1296 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1297 * @retval None
1298 */
LL_RCC_LSCO_Disable(void)1299 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1300 {
1301 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1302 }
1303
1304 /**
1305 * @brief Configure Low speed clock selection
1306 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
1307 * @param Source This parameter can be one of the following values:
1308 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1309 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1310 * @retval None
1311 */
LL_RCC_LSCO_SetSource(uint32_t Source)1312 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1313 {
1314 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
1315 }
1316
1317 /**
1318 * @brief Get Low speed clock selection
1319 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
1320 * @retval Returned value can be one of the following values:
1321 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1322 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1323 */
LL_RCC_LSCO_GetSource(void)1324 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1325 {
1326 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
1327 }
1328
1329 /**
1330 * @}
1331 */
1332
1333 /** @defgroup RCC_LL_EF_System System
1334 * @{
1335 */
1336
1337 /**
1338 * @brief Configure the system clock source
1339 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1340 * @param Source This parameter can be one of the following values:
1341 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1342 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1343 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1344 * @retval None
1345 */
LL_RCC_SetSysClkSource(uint32_t Source)1346 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1347 {
1348 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1349 }
1350
1351 /**
1352 * @brief Get the system clock source
1353 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1354 * @retval Returned value can be one of the following values:
1355 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1356 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1357 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1358 */
LL_RCC_GetSysClkSource(void)1359 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1360 {
1361 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1362 }
1363
1364 /**
1365 * @brief Set AHB prescaler
1366 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1367 * @param Prescaler This parameter can be one of the following values:
1368 * @arg @ref LL_RCC_SYSCLK_DIV_1
1369 * @arg @ref LL_RCC_SYSCLK_DIV_2
1370 * @arg @ref LL_RCC_SYSCLK_DIV_4
1371 * @arg @ref LL_RCC_SYSCLK_DIV_8
1372 * @arg @ref LL_RCC_SYSCLK_DIV_16
1373 * @arg @ref LL_RCC_SYSCLK_DIV_64
1374 * @arg @ref LL_RCC_SYSCLK_DIV_128
1375 * @arg @ref LL_RCC_SYSCLK_DIV_256
1376 * @arg @ref LL_RCC_SYSCLK_DIV_512
1377 * @retval None
1378 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1379 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1380 {
1381 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1382 }
1383
1384 /**
1385 * @brief Set APB1 prescaler
1386 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1387 * @param Prescaler This parameter can be one of the following values:
1388 * @arg @ref LL_RCC_APB1_DIV_1
1389 * @arg @ref LL_RCC_APB1_DIV_2
1390 * @arg @ref LL_RCC_APB1_DIV_4
1391 * @arg @ref LL_RCC_APB1_DIV_8
1392 * @arg @ref LL_RCC_APB1_DIV_16
1393 * @retval None
1394 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1395 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1396 {
1397 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1398 }
1399
1400 /**
1401 * @brief Set APB2 prescaler
1402 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1403 * @param Prescaler This parameter can be one of the following values:
1404 * @arg @ref LL_RCC_APB2_DIV_1
1405 * @arg @ref LL_RCC_APB2_DIV_2
1406 * @arg @ref LL_RCC_APB2_DIV_4
1407 * @arg @ref LL_RCC_APB2_DIV_8
1408 * @arg @ref LL_RCC_APB2_DIV_16
1409 * @retval None
1410 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1411 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1412 {
1413 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1414 }
1415
1416 /**
1417 * @brief Get AHB prescaler
1418 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1419 * @retval Returned value can be one of the following values:
1420 * @arg @ref LL_RCC_SYSCLK_DIV_1
1421 * @arg @ref LL_RCC_SYSCLK_DIV_2
1422 * @arg @ref LL_RCC_SYSCLK_DIV_4
1423 * @arg @ref LL_RCC_SYSCLK_DIV_8
1424 * @arg @ref LL_RCC_SYSCLK_DIV_16
1425 * @arg @ref LL_RCC_SYSCLK_DIV_64
1426 * @arg @ref LL_RCC_SYSCLK_DIV_128
1427 * @arg @ref LL_RCC_SYSCLK_DIV_256
1428 * @arg @ref LL_RCC_SYSCLK_DIV_512
1429 */
LL_RCC_GetAHBPrescaler(void)1430 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1431 {
1432 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1433 }
1434
1435 /**
1436 * @brief Get APB1 prescaler
1437 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1438 * @retval Returned value can be one of the following values:
1439 * @arg @ref LL_RCC_APB1_DIV_1
1440 * @arg @ref LL_RCC_APB1_DIV_2
1441 * @arg @ref LL_RCC_APB1_DIV_4
1442 * @arg @ref LL_RCC_APB1_DIV_8
1443 * @arg @ref LL_RCC_APB1_DIV_16
1444 */
LL_RCC_GetAPB1Prescaler(void)1445 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1446 {
1447 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1448 }
1449
1450 /**
1451 * @brief Get APB2 prescaler
1452 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1453 * @retval Returned value can be one of the following values:
1454 * @arg @ref LL_RCC_APB2_DIV_1
1455 * @arg @ref LL_RCC_APB2_DIV_2
1456 * @arg @ref LL_RCC_APB2_DIV_4
1457 * @arg @ref LL_RCC_APB2_DIV_8
1458 * @arg @ref LL_RCC_APB2_DIV_16
1459 */
LL_RCC_GetAPB2Prescaler(void)1460 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1461 {
1462 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1463 }
1464
1465 /**
1466 * @}
1467 */
1468
1469 /** @defgroup RCC_LL_EF_MCO MCO
1470 * @{
1471 */
1472
1473 /**
1474 * @brief Configure MCOx
1475 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
1476 * CFGR MCOPRE LL_RCC_ConfigMCO
1477 * @param MCOxSource This parameter can be one of the following values:
1478 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1479 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1480 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1481 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1482 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
1483 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1484 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1485 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1486 *
1487 * (*) value not defined in all devices.
1488 * @param MCOxPrescaler This parameter can be one of the following values:
1489 * @arg @ref LL_RCC_MCO1_DIV_1
1490 * @arg @ref LL_RCC_MCO1_DIV_2
1491 * @arg @ref LL_RCC_MCO1_DIV_4
1492 * @arg @ref LL_RCC_MCO1_DIV_8
1493 * @arg @ref LL_RCC_MCO1_DIV_16
1494 * @retval None
1495 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1496 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1497 {
1498 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1499 }
1500
1501 /**
1502 * @}
1503 */
1504
1505 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1506 * @{
1507 */
1508
1509 /**
1510 * @brief Configure USARTx clock source
1511 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1512 * @param USARTxSource This parameter can be one of the following values:
1513 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1514 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1515 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1516 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1517 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1518 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1519 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1520 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1521 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
1522 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
1523 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
1524 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
1525 * @retval None
1526 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1527 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1528 {
1529 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
1530 }
1531
1532 #if defined(UART4)
1533 /**
1534 * @brief Configure UARTx clock source
1535 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
1536 * @param UARTxSource This parameter can be one of the following values:
1537 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
1538 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
1539 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
1540 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
1541 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
1542 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
1543 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
1544 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
1545 *
1546 * (*) value not defined in all devices.
1547 * @retval None
1548 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)1549 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
1550 {
1551 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
1552 }
1553 #endif /* UART4 */
1554
1555 /**
1556 * @brief Configure LPUART1x clock source
1557 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
1558 * @param LPUARTxSource This parameter can be one of the following values:
1559 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1560 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1561 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1562 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1563 * @retval None
1564 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1565 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1566 {
1567 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
1568 }
1569
1570 /**
1571 * @brief Configure I2Cx clock source
1572 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
1573 * @param I2CxSource This parameter can be one of the following values:
1574 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1575 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1576 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1577 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
1578 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
1579 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
1580 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
1581 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1582 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1583 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
1584 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
1585 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
1586 *
1587 * (*) value not defined in all devices.
1588 * @retval None
1589 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1590 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1591 {
1592 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
1593 MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
1594 }
1595
1596 /**
1597 * @brief Configure LPTIMx clock source
1598 * @rmtoll CCIPR LPTIM1SEL LL_RCC_SetLPTIMClockSource
1599 * @param LPTIMxSource This parameter can be one of the following values:
1600 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1601 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1602 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1603 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1604 * @retval None
1605 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)1606 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
1607 {
1608 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
1609 }
1610
1611 #if defined(SAI1)
1612 /**
1613 * @brief Configure SAIx clock source
1614 * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
1615 * @param SAIxSource This parameter can be one of the following values:
1616 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
1617 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
1618 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
1619 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
1620 *
1621 * (*) value not defined in all devices.
1622 * @retval None
1623 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)1624 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
1625 {
1626 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
1627 }
1628 #endif /* SAI1 */
1629
1630 #if defined(SPI_I2S_SUPPORT)
1631 /**
1632 * @brief Configure I2S clock source
1633 * @rmtoll CCIPR I2S23SEL LL_RCC_SetI2SClockSource
1634 * @param I2SxSource This parameter can be one of the following values:
1635 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1636 * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
1637 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1638 * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
1639 * @retval None
1640 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)1641 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1642 {
1643 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
1644 }
1645 #endif /* SPI_I2S_SUPPORT */
1646
1647 #if defined(FDCAN1)
1648 /**
1649 * @brief Configure FDCAN clock source
1650 * @rmtoll CCIPR FDCANSEL LL_RCC_SetFDCANClockSource
1651 * @param FDCANxSource This parameter can be one of the following values:
1652 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
1653 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
1654 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
1655 * @retval None
1656 */
LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)1657 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
1658 {
1659 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, FDCANxSource);
1660 }
1661 #endif /* FDCAN1 */
1662
1663 /**
1664 * @brief Configure RNG clock source
1665 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
1666 * @param RNGxSource This parameter can be one of the following values:
1667 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1668 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1669 * @retval None
1670 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)1671 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
1672 {
1673 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
1674 }
1675
1676 /**
1677 * @brief Configure USB clock source
1678 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
1679 * @param USBxSource This parameter can be one of the following values:
1680 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1681 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1682 * @retval None
1683 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)1684 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1685 {
1686 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
1687 }
1688
1689 /**
1690 * @brief Configure ADC clock source
1691 * @rmtoll CCIPR ADC12SEL LL_RCC_SetADCClockSource\n
1692 * CCIPR ADC345SEL LL_RCC_SetADCClockSource
1693 * @param ADCxSource This parameter can be one of the following values:
1694 * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
1695 * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
1696 * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
1697 * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
1698 * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
1699 * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
1700 *
1701 * (*) value not defined in all devices.
1702 * @retval None
1703 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1704 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1705 {
1706 MODIFY_REG(RCC->CCIPR, 3U << ((ADCxSource & 0x001F0000U) >> 16U), ((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U)));
1707 }
1708
1709 #if defined(QUADSPI)
1710 /**
1711 * @brief Configure QUADSPI clock source
1712 * @rmtoll CCIPR2 QSPISEL LL_RCC_SetQUADSPIClockSource
1713 * @param Source This parameter can be one of the following values:
1714 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
1715 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
1716 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
1717 * @retval None
1718 */
LL_RCC_SetQUADSPIClockSource(uint32_t Source)1719 __STATIC_INLINE void LL_RCC_SetQUADSPIClockSource(uint32_t Source)
1720 {
1721 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source);
1722 }
1723 #endif /* QUADSPI */
1724
1725 /**
1726 * @brief Get USARTx clock source
1727 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
1728 * @param USARTx This parameter can be one of the following values:
1729 * @arg @ref LL_RCC_USART1_CLKSOURCE
1730 * @arg @ref LL_RCC_USART2_CLKSOURCE
1731 * @arg @ref LL_RCC_USART3_CLKSOURCE
1732 * @retval Returned value can be one of the following values:
1733 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1734 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1735 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1736 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1737 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1738 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1739 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1740 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1741 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
1742 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
1743 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
1744 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
1745 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1746 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1747 {
1748 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
1749 }
1750
1751 #if defined(UART4)
1752 /**
1753 * @brief Get UARTx clock source
1754 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
1755 * @param UARTx This parameter can be one of the following values:
1756 * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
1757 * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
1758 * @retval Returned value can be one of the following values:
1759 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
1760 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
1761 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
1762 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
1763 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
1764 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
1765 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
1766 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
1767 *
1768 * (*) value not defined in all devices.
1769 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)1770 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
1771 {
1772 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
1773 }
1774 #endif /* UART4 */
1775
1776 /**
1777 * @brief Get LPUARTx clock source
1778 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
1779 * @param LPUARTx This parameter can be one of the following values:
1780 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
1781 * @retval Returned value can be one of the following values:
1782 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1783 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1784 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1785 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1786 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)1787 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
1788 {
1789 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
1790 }
1791
1792 /**
1793 * @brief Get I2Cx clock source
1794 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
1795 * @param I2Cx This parameter can be one of the following values:
1796 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1797 * @arg @ref LL_RCC_I2C2_CLKSOURCE
1798 * @arg @ref LL_RCC_I2C3_CLKSOURCE
1799 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
1800 *
1801 * (*) value not defined in all devices.
1802 * @retval Returned value can be one of the following values:
1803 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1804 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1805 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1806 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
1807 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
1808 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
1809 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
1810 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1811 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1812 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
1813 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
1814 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
1815 *
1816 * (*) value not defined in all devices.
1817 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)1818 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1819 {
1820 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
1821 return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
1822 }
1823
1824 /**
1825 * @brief Get LPTIMx clock source
1826 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
1827 * @param LPTIMx This parameter can be one of the following values:
1828 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
1829 * @retval Returned value can be one of the following values:
1830 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1831 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1832 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1833 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1834 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)1835 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
1836 {
1837 return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
1838 }
1839
1840 /**
1841 * @brief Get SAIx clock source
1842 * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
1843 * @param SAIx This parameter can be one of the following values:
1844 * @arg @ref LL_RCC_SAI1_CLKSOURCE
1845 *
1846 * (*) value not defined in all devices.
1847 * @retval Returned value can be one of the following values:
1848 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
1849 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
1850 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
1851 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
1852 *
1853 * (*) value not defined in all devices.
1854 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)1855 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
1856 {
1857 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
1858 }
1859
1860 /**
1861 * @brief Get I2Sx clock source
1862 * @rmtoll CCIPR I2S23SEL LL_RCC_GetI2SClockSource
1863 * @param I2Sx This parameter can be one of the following values:
1864 * @arg @ref LL_RCC_I2S_CLKSOURCE
1865 * @retval Returned value can be one of the following values:
1866 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1867 * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
1868 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1869 * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
1870 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)1871 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1872 {
1873 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
1874 }
1875
1876 #if defined(FDCAN1)
1877 /**
1878 * @brief Get FDCANx clock source
1879 * @rmtoll CCIPR FDCANSEL LL_RCC_GetFDCANClockSource
1880 * @param FDCANx This parameter can be one of the following values:
1881 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1882 * @retval Returned value can be one of the following values:
1883 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
1884 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
1885 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
1886 * @retval None
1887 */
LL_RCC_GetFDCANClockSource(uint32_t FDCANx)1888 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
1889 {
1890 return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx));
1891 }
1892 #endif /* FDCAN1 */
1893
1894 /**
1895 * @brief Get RNGx clock source
1896 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
1897 * @param RNGx This parameter can be one of the following values:
1898 * @arg @ref LL_RCC_RNG_CLKSOURCE
1899 * @retval Returned value can be one of the following values:
1900 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1901 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1902 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)1903 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
1904 {
1905 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
1906 }
1907
1908 /**
1909 * @brief Get USBx clock source
1910 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
1911 * @param USBx This parameter can be one of the following values:
1912 * @arg @ref LL_RCC_USB_CLKSOURCE
1913 * @retval Returned value can be one of the following values:
1914 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1915 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1916 */
LL_RCC_GetUSBClockSource(uint32_t USBx)1917 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1918 {
1919 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
1920 }
1921
1922 /**
1923 * @brief Get ADCx clock source
1924 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
1925 * @param ADCx This parameter can be one of the following values:
1926 * @arg @ref LL_RCC_ADC12_CLKSOURCE
1927 * @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
1928 * @retval Returned value can be one of the following values:
1929 * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
1930 * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
1931 * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
1932 * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
1933 * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
1934 * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
1935 *
1936 * (*) value not defined in all devices.
1937 */
LL_RCC_GetADCClockSource(uint32_t ADCx)1938 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1939 {
1940 return (uint32_t)((READ_BIT(RCC->CCIPR, 3UL << ((ADCx & 0x001F0000U) >> 16U)) >> ((ADCx & 0x001F0000U) >> 16U)) | (ADCx & 0xFFFF0000U));
1941 }
1942
1943 #if defined(QUADSPI)
1944 /**
1945 * @brief Get QUADSPI clock source
1946 * @rmtoll CCIPR2 QSPISEL LL_RCC_GetQUADSPIClockSource
1947 * @param QUADSPIx This parameter can be one of the following values:
1948 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE
1949 * @retval Returned value can be one of the following values:
1950 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
1951 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
1952 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
1953 */
LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)1954 __STATIC_INLINE uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)
1955 {
1956 return (uint32_t)(READ_BIT(RCC->CCIPR2, QUADSPIx));
1957 }
1958 #endif /* QUADSPI */
1959 /**
1960 * @}
1961 */
1962
1963 /** @defgroup RCC_LL_EF_RTC RTC
1964 * @{
1965 */
1966
1967 /**
1968 * @brief Set RTC Clock Source
1969 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
1970 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1971 * set). The BDRST bit can be used to reset them.
1972 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
1973 * @param Source This parameter can be one of the following values:
1974 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1975 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1976 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1977 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1978 * @retval None
1979 */
LL_RCC_SetRTCClockSource(uint32_t Source)1980 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1981 {
1982 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
1983 }
1984
1985 /**
1986 * @brief Get RTC Clock Source
1987 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
1988 * @retval Returned value can be one of the following values:
1989 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1990 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1991 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1992 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1993 */
LL_RCC_GetRTCClockSource(void)1994 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1995 {
1996 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
1997 }
1998
1999 /**
2000 * @brief Enable RTC
2001 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2002 * @retval None
2003 */
LL_RCC_EnableRTC(void)2004 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2005 {
2006 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2007 }
2008
2009 /**
2010 * @brief Disable RTC
2011 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2012 * @retval None
2013 */
LL_RCC_DisableRTC(void)2014 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2015 {
2016 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2017 }
2018
2019 /**
2020 * @brief Check if RTC has been enabled or not
2021 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2022 * @retval State of bit (1 or 0).
2023 */
LL_RCC_IsEnabledRTC(void)2024 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2025 {
2026 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2027 }
2028
2029 /**
2030 * @brief Force the Backup domain reset
2031 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2032 * @retval None
2033 */
LL_RCC_ForceBackupDomainReset(void)2034 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2035 {
2036 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2037 }
2038
2039 /**
2040 * @brief Release the Backup domain reset
2041 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2042 * @retval None
2043 */
LL_RCC_ReleaseBackupDomainReset(void)2044 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2045 {
2046 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2047 }
2048
2049 /**
2050 * @}
2051 */
2052
2053
2054 /** @defgroup RCC_LL_EF_PLL PLL
2055 * @{
2056 */
2057
2058 /**
2059 * @brief Enable PLL
2060 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2061 * @retval None
2062 */
LL_RCC_PLL_Enable(void)2063 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2064 {
2065 SET_BIT(RCC->CR, RCC_CR_PLLON);
2066 }
2067
2068 /**
2069 * @brief Disable PLL
2070 * @note Cannot be disabled if the PLL clock is used as the system clock
2071 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2072 * @retval None
2073 */
LL_RCC_PLL_Disable(void)2074 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2075 {
2076 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2077 }
2078
2079 /**
2080 * @brief Check if PLL Ready
2081 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2082 * @retval State of bit (1 or 0).
2083 */
LL_RCC_PLL_IsReady(void)2084 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2085 {
2086 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2087 }
2088
2089 /**
2090 * @brief Configure PLL used for SYSCLK Domain
2091 * @note PLL Source and PLLM Divider can be written only when PLL
2092 * is disabled.
2093 * @note PLLN/PLLR can be written only when PLL is disabled.
2094 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2095 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2096 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2097 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2098 * @param Source This parameter can be one of the following values:
2099 * @arg @ref LL_RCC_PLLSOURCE_NONE
2100 * @arg @ref LL_RCC_PLLSOURCE_HSI
2101 * @arg @ref LL_RCC_PLLSOURCE_HSE
2102 * @param PLLM This parameter can be one of the following values:
2103 * @arg @ref LL_RCC_PLLM_DIV_1
2104 * @arg @ref LL_RCC_PLLM_DIV_2
2105 * @arg @ref LL_RCC_PLLM_DIV_3
2106 * @arg @ref LL_RCC_PLLM_DIV_4
2107 * @arg @ref LL_RCC_PLLM_DIV_5
2108 * @arg @ref LL_RCC_PLLM_DIV_6
2109 * @arg @ref LL_RCC_PLLM_DIV_7
2110 * @arg @ref LL_RCC_PLLM_DIV_8
2111 * @arg @ref LL_RCC_PLLM_DIV_9
2112 * @arg @ref LL_RCC_PLLM_DIV_10
2113 * @arg @ref LL_RCC_PLLM_DIV_11
2114 * @arg @ref LL_RCC_PLLM_DIV_12
2115 * @arg @ref LL_RCC_PLLM_DIV_13
2116 * @arg @ref LL_RCC_PLLM_DIV_14
2117 * @arg @ref LL_RCC_PLLM_DIV_15
2118 * @arg @ref LL_RCC_PLLM_DIV_16
2119 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2120 * @param PLLR This parameter can be one of the following values:
2121 * @arg @ref LL_RCC_PLLR_DIV_2
2122 * @arg @ref LL_RCC_PLLR_DIV_4
2123 * @arg @ref LL_RCC_PLLR_DIV_6
2124 * @arg @ref LL_RCC_PLLR_DIV_8
2125 * @retval None
2126 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2127 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2128 {
2129 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2130 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
2131 }
2132
2133 /**
2134 * @brief Configure PLL used for ADC domain clock
2135 * @note PLL Source and PLLM Divider can be written only when PLL
2136 * is disabled.
2137 * @note PLLN/PLLP can be written only when PLL is disabled.
2138 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
2139 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
2140 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
2141 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_ADC
2142 * @param Source This parameter can be one of the following values:
2143 * @arg @ref LL_RCC_PLLSOURCE_NONE
2144 * @arg @ref LL_RCC_PLLSOURCE_HSI
2145 * @arg @ref LL_RCC_PLLSOURCE_HSE
2146 * @param PLLM This parameter can be one of the following values:
2147 * @arg @ref LL_RCC_PLLM_DIV_1
2148 * @arg @ref LL_RCC_PLLM_DIV_2
2149 * @arg @ref LL_RCC_PLLM_DIV_3
2150 * @arg @ref LL_RCC_PLLM_DIV_4
2151 * @arg @ref LL_RCC_PLLM_DIV_5
2152 * @arg @ref LL_RCC_PLLM_DIV_6
2153 * @arg @ref LL_RCC_PLLM_DIV_7
2154 * @arg @ref LL_RCC_PLLM_DIV_8
2155 * @arg @ref LL_RCC_PLLM_DIV_9
2156 * @arg @ref LL_RCC_PLLM_DIV_10
2157 * @arg @ref LL_RCC_PLLM_DIV_11
2158 * @arg @ref LL_RCC_PLLM_DIV_12
2159 * @arg @ref LL_RCC_PLLM_DIV_13
2160 * @arg @ref LL_RCC_PLLM_DIV_14
2161 * @arg @ref LL_RCC_PLLM_DIV_15
2162 * @arg @ref LL_RCC_PLLM_DIV_16
2163 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2164 * @param PLLP This parameter can be one of the following values:
2165 * @arg @ref LL_RCC_PLLP_DIV_2
2166 * @arg @ref LL_RCC_PLLP_DIV_3
2167 * @arg @ref LL_RCC_PLLP_DIV_4
2168 * @arg @ref LL_RCC_PLLP_DIV_5
2169 * @arg @ref LL_RCC_PLLP_DIV_6
2170 * @arg @ref LL_RCC_PLLP_DIV_7
2171 * @arg @ref LL_RCC_PLLP_DIV_8
2172 * @arg @ref LL_RCC_PLLP_DIV_9
2173 * @arg @ref LL_RCC_PLLP_DIV_10
2174 * @arg @ref LL_RCC_PLLP_DIV_11
2175 * @arg @ref LL_RCC_PLLP_DIV_12
2176 * @arg @ref LL_RCC_PLLP_DIV_13
2177 * @arg @ref LL_RCC_PLLP_DIV_14
2178 * @arg @ref LL_RCC_PLLP_DIV_15
2179 * @arg @ref LL_RCC_PLLP_DIV_16
2180 * @arg @ref LL_RCC_PLLP_DIV_17
2181 * @arg @ref LL_RCC_PLLP_DIV_18
2182 * @arg @ref LL_RCC_PLLP_DIV_19
2183 * @arg @ref LL_RCC_PLLP_DIV_20
2184 * @arg @ref LL_RCC_PLLP_DIV_21
2185 * @arg @ref LL_RCC_PLLP_DIV_22
2186 * @arg @ref LL_RCC_PLLP_DIV_23
2187 * @arg @ref LL_RCC_PLLP_DIV_24
2188 * @arg @ref LL_RCC_PLLP_DIV_25
2189 * @arg @ref LL_RCC_PLLP_DIV_26
2190 * @arg @ref LL_RCC_PLLP_DIV_27
2191 * @arg @ref LL_RCC_PLLP_DIV_28
2192 * @arg @ref LL_RCC_PLLP_DIV_29
2193 * @arg @ref LL_RCC_PLLP_DIV_30
2194 * @arg @ref LL_RCC_PLLP_DIV_31
2195 * @retval None
2196 */
LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2197 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2198 {
2199 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
2200 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2201 }
2202
2203 /**
2204 * @brief Configure PLL used for 48Mhz domain clock
2205 * @note PLL Source and PLLM Divider can be written only when PLL,
2206 * is disabled.
2207 * @note PLLN/PLLQ can be written only when PLL is disabled.
2208 * @note This can be selected for USB, RNG
2209 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
2210 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
2211 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
2212 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
2213 * @param Source This parameter can be one of the following values:
2214 * @arg @ref LL_RCC_PLLSOURCE_NONE
2215 * @arg @ref LL_RCC_PLLSOURCE_HSI
2216 * @arg @ref LL_RCC_PLLSOURCE_HSE
2217 * @param PLLM This parameter can be one of the following values:
2218 * @arg @ref LL_RCC_PLLM_DIV_1
2219 * @arg @ref LL_RCC_PLLM_DIV_2
2220 * @arg @ref LL_RCC_PLLM_DIV_3
2221 * @arg @ref LL_RCC_PLLM_DIV_4
2222 * @arg @ref LL_RCC_PLLM_DIV_5
2223 * @arg @ref LL_RCC_PLLM_DIV_6
2224 * @arg @ref LL_RCC_PLLM_DIV_7
2225 * @arg @ref LL_RCC_PLLM_DIV_8
2226 * @arg @ref LL_RCC_PLLM_DIV_9
2227 * @arg @ref LL_RCC_PLLM_DIV_10
2228 * @arg @ref LL_RCC_PLLM_DIV_11
2229 * @arg @ref LL_RCC_PLLM_DIV_12
2230 * @arg @ref LL_RCC_PLLM_DIV_13
2231 * @arg @ref LL_RCC_PLLM_DIV_14
2232 * @arg @ref LL_RCC_PLLM_DIV_15
2233 * @arg @ref LL_RCC_PLLM_DIV_16
2234 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2235 * @param PLLQ This parameter can be one of the following values:
2236 * @arg @ref LL_RCC_PLLQ_DIV_2
2237 * @arg @ref LL_RCC_PLLQ_DIV_4
2238 * @arg @ref LL_RCC_PLLQ_DIV_6
2239 * @arg @ref LL_RCC_PLLQ_DIV_8
2240 * @retval None
2241 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2242 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2243 {
2244 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2245 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2246 }
2247
2248 /**
2249 * @brief Configure PLL clock source
2250 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
2251 * @param PLLSource This parameter can be one of the following values:
2252 * @arg @ref LL_RCC_PLLSOURCE_NONE
2253 * @arg @ref LL_RCC_PLLSOURCE_HSI
2254 * @arg @ref LL_RCC_PLLSOURCE_HSE
2255 * @retval None
2256 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)2257 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
2258 {
2259 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
2260 }
2261
2262 /**
2263 * @brief Get the oscillator used as PLL clock source.
2264 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
2265 * @retval Returned value can be one of the following values:
2266 * @arg @ref LL_RCC_PLLSOURCE_NONE
2267 * @arg @ref LL_RCC_PLLSOURCE_HSI
2268 * @arg @ref LL_RCC_PLLSOURCE_HSE
2269 */
LL_RCC_PLL_GetMainSource(void)2270 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
2271 {
2272 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
2273 }
2274
2275 /**
2276 * @brief Get Main PLL multiplication factor for VCO
2277 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
2278 * @retval Between Min_Data = 8 and Max_Data = 127
2279 */
LL_RCC_PLL_GetN(void)2280 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
2281 {
2282 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
2283 }
2284
2285 /**
2286 * @brief Get Main PLL division factor for PLLP
2287 * @note Used for PLLADCCLK (ADC clock)
2288 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP\n
2289 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
2290 * @retval Returned value can be one of the following values:
2291 * @arg @ref LL_RCC_PLLP_DIV_2
2292 * @arg @ref LL_RCC_PLLP_DIV_3
2293 * @arg @ref LL_RCC_PLLP_DIV_4
2294 * @arg @ref LL_RCC_PLLP_DIV_5
2295 * @arg @ref LL_RCC_PLLP_DIV_6
2296 * @arg @ref LL_RCC_PLLP_DIV_7
2297 * @arg @ref LL_RCC_PLLP_DIV_8
2298 * @arg @ref LL_RCC_PLLP_DIV_9
2299 * @arg @ref LL_RCC_PLLP_DIV_10
2300 * @arg @ref LL_RCC_PLLP_DIV_11
2301 * @arg @ref LL_RCC_PLLP_DIV_12
2302 * @arg @ref LL_RCC_PLLP_DIV_13
2303 * @arg @ref LL_RCC_PLLP_DIV_14
2304 * @arg @ref LL_RCC_PLLP_DIV_15
2305 * @arg @ref LL_RCC_PLLP_DIV_16
2306 * @arg @ref LL_RCC_PLLP_DIV_17
2307 * @arg @ref LL_RCC_PLLP_DIV_18
2308 * @arg @ref LL_RCC_PLLP_DIV_19
2309 * @arg @ref LL_RCC_PLLP_DIV_20
2310 * @arg @ref LL_RCC_PLLP_DIV_21
2311 * @arg @ref LL_RCC_PLLP_DIV_22
2312 * @arg @ref LL_RCC_PLLP_DIV_23
2313 * @arg @ref LL_RCC_PLLP_DIV_24
2314 * @arg @ref LL_RCC_PLLP_DIV_25
2315 * @arg @ref LL_RCC_PLLP_DIV_26
2316 * @arg @ref LL_RCC_PLLP_DIV_27
2317 * @arg @ref LL_RCC_PLLP_DIV_28
2318 * @arg @ref LL_RCC_PLLP_DIV_29
2319 * @arg @ref LL_RCC_PLLP_DIV_30
2320 * @arg @ref LL_RCC_PLLP_DIV_31
2321 */
LL_RCC_PLL_GetP(void)2322 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
2323 {
2324 return (uint32_t) ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) != 0U) ? READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) : ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) == RCC_PLLCFGR_PLLP) ? LL_RCC_PLLP_DIV_17 : LL_RCC_PLLP_DIV_7) );
2325 }
2326
2327 /**
2328 * @brief Get Main PLL division factor for PLLQ
2329 * @note Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
2330 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
2331 * @retval Returned value can be one of the following values:
2332 * @arg @ref LL_RCC_PLLQ_DIV_2
2333 * @arg @ref LL_RCC_PLLQ_DIV_4
2334 * @arg @ref LL_RCC_PLLQ_DIV_6
2335 * @arg @ref LL_RCC_PLLQ_DIV_8
2336 */
LL_RCC_PLL_GetQ(void)2337 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
2338 {
2339 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
2340 }
2341
2342 /**
2343 * @brief Get Main PLL division factor for PLLR
2344 * @note Used for PLLCLK (system clock)
2345 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
2346 * @retval Returned value can be one of the following values:
2347 * @arg @ref LL_RCC_PLLR_DIV_2
2348 * @arg @ref LL_RCC_PLLR_DIV_4
2349 * @arg @ref LL_RCC_PLLR_DIV_6
2350 * @arg @ref LL_RCC_PLLR_DIV_8
2351 */
LL_RCC_PLL_GetR(void)2352 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
2353 {
2354 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
2355 }
2356
2357 /**
2358 * @brief Get Division factor for the main PLL and other PLL
2359 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
2360 * @retval Returned value can be one of the following values:
2361 * @arg @ref LL_RCC_PLLM_DIV_1
2362 * @arg @ref LL_RCC_PLLM_DIV_2
2363 * @arg @ref LL_RCC_PLLM_DIV_3
2364 * @arg @ref LL_RCC_PLLM_DIV_4
2365 * @arg @ref LL_RCC_PLLM_DIV_5
2366 * @arg @ref LL_RCC_PLLM_DIV_6
2367 * @arg @ref LL_RCC_PLLM_DIV_7
2368 * @arg @ref LL_RCC_PLLM_DIV_8
2369 * @arg @ref LL_RCC_PLLM_DIV_9
2370 * @arg @ref LL_RCC_PLLM_DIV_10
2371 * @arg @ref LL_RCC_PLLM_DIV_11
2372 * @arg @ref LL_RCC_PLLM_DIV_12
2373 * @arg @ref LL_RCC_PLLM_DIV_13
2374 * @arg @ref LL_RCC_PLLM_DIV_14
2375 * @arg @ref LL_RCC_PLLM_DIV_15
2376 * @arg @ref LL_RCC_PLLM_DIV_16
2377 */
LL_RCC_PLL_GetDivider(void)2378 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
2379 {
2380 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
2381 }
2382
2383 /**
2384 * @brief Enable PLL output mapped on ADC domain clock
2385 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
2386 * @retval None
2387 */
LL_RCC_PLL_EnableDomain_ADC(void)2388 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
2389 {
2390 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2391 }
2392
2393 /**
2394 * @brief Disable PLL output mapped on ADC domain clock
2395 * @note Cannot be disabled if the PLL clock is used as the system
2396 * clock
2397 * @note In order to save power, when the PLLCLK of the PLL is
2398 * not used, should be 0
2399 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
2400 * @retval None
2401 */
LL_RCC_PLL_DisableDomain_ADC(void)2402 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
2403 {
2404 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2405 }
2406
2407 /**
2408 * @brief Check if PLL output mapped on ADC domain clock is enabled
2409 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
2410 * @retval State of bit (1 or 0).
2411 */
LL_RCC_PLL_IsEnabledDomain_ADC(void)2412 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
2413 {
2414 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
2415 }
2416
2417 /**
2418 * @brief Enable PLL output mapped on 48MHz domain clock
2419 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
2420 * @retval None
2421 */
LL_RCC_PLL_EnableDomain_48M(void)2422 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
2423 {
2424 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2425 }
2426
2427 /**
2428 * @brief Disable PLL output mapped on 48MHz domain clock
2429 * @note Cannot be disabled if the PLL clock is used as the system
2430 * clock
2431 * @note In order to save power, when the PLLCLK of the PLL is
2432 * not used, should be 0
2433 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
2434 * @retval None
2435 */
LL_RCC_PLL_DisableDomain_48M(void)2436 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
2437 {
2438 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2439 }
2440
2441 /**
2442 * @brief Check if PLL output mapped on 48MHz domain clock is enabled
2443 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
2444 * @retval State of bit (1 or 0).
2445 */
LL_RCC_PLL_IsEnabledDomain_48M(void)2446 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
2447 {
2448 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
2449 }
2450
2451 /**
2452 * @brief Enable PLL output mapped on SYSCLK domain
2453 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
2454 * @retval None
2455 */
LL_RCC_PLL_EnableDomain_SYS(void)2456 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
2457 {
2458 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2459 }
2460
2461 /**
2462 * @brief Disable PLL output mapped on SYSCLK domain
2463 * @note Cannot be disabled if the PLL clock is used as the system
2464 * clock
2465 * @note In order to save power, when the PLLCLK of the PLL is
2466 * not used, Main PLL should be 0
2467 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
2468 * @retval None
2469 */
LL_RCC_PLL_DisableDomain_SYS(void)2470 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
2471 {
2472 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2473 }
2474
2475 /**
2476 * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
2477 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
2478 * @retval State of bit (1 or 0).
2479 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)2480 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
2481 {
2482 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
2483 }
2484
2485 /**
2486 * @}
2487 */
2488
2489 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2490 * @{
2491 */
2492
2493 /**
2494 * @brief Clear LSI ready interrupt flag
2495 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
2496 * @retval None
2497 */
LL_RCC_ClearFlag_LSIRDY(void)2498 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
2499 {
2500 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
2501 }
2502
2503 /**
2504 * @brief Clear LSE ready interrupt flag
2505 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
2506 * @retval None
2507 */
LL_RCC_ClearFlag_LSERDY(void)2508 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2509 {
2510 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
2511 }
2512
2513 /**
2514 * @brief Clear HSI ready interrupt flag
2515 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2516 * @retval None
2517 */
LL_RCC_ClearFlag_HSIRDY(void)2518 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2519 {
2520 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
2521 }
2522
2523 /**
2524 * @brief Clear HSE ready interrupt flag
2525 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
2526 * @retval None
2527 */
LL_RCC_ClearFlag_HSERDY(void)2528 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2529 {
2530 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
2531 }
2532
2533 /**
2534 * @brief Clear PLL ready interrupt flag
2535 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2536 * @retval None
2537 */
LL_RCC_ClearFlag_PLLRDY(void)2538 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2539 {
2540 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
2541 }
2542
2543 /**
2544 * @brief Clear HSI48 ready interrupt flag
2545 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
2546 * @retval None
2547 */
LL_RCC_ClearFlag_HSI48RDY(void)2548 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
2549 {
2550 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
2551 }
2552
2553 /**
2554 * @brief Clear Clock security system interrupt flag
2555 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
2556 * @retval None
2557 */
LL_RCC_ClearFlag_HSECSS(void)2558 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2559 {
2560 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
2561 }
2562
2563 /**
2564 * @brief Clear LSE Clock security system interrupt flag
2565 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
2566 * @retval None
2567 */
LL_RCC_ClearFlag_LSECSS(void)2568 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
2569 {
2570 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
2571 }
2572
2573 /**
2574 * @brief Check if LSI ready interrupt occurred or not
2575 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2576 * @retval State of bit (1 or 0).
2577 */
LL_RCC_IsActiveFlag_LSIRDY(void)2578 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2579 {
2580 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
2581 }
2582
2583 /**
2584 * @brief Check if LSE ready interrupt occurred or not
2585 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2586 * @retval State of bit (1 or 0).
2587 */
LL_RCC_IsActiveFlag_LSERDY(void)2588 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2589 {
2590 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
2591 }
2592
2593 /**
2594 * @brief Check if HSI ready interrupt occurred or not
2595 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2596 * @retval State of bit (1 or 0).
2597 */
LL_RCC_IsActiveFlag_HSIRDY(void)2598 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2599 {
2600 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
2601 }
2602
2603 /**
2604 * @brief Check if HSE ready interrupt occurred or not
2605 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2606 * @retval State of bit (1 or 0).
2607 */
LL_RCC_IsActiveFlag_HSERDY(void)2608 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2609 {
2610 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
2611 }
2612
2613 /**
2614 * @brief Check if PLL ready interrupt occurred or not
2615 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2616 * @retval State of bit (1 or 0).
2617 */
LL_RCC_IsActiveFlag_PLLRDY(void)2618 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2619 {
2620 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
2621 }
2622
2623 /**
2624 * @brief Check if HSI48 ready interrupt occurred or not
2625 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
2626 * @retval State of bit (1 or 0).
2627 */
LL_RCC_IsActiveFlag_HSI48RDY(void)2628 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
2629 {
2630 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
2631 }
2632
2633 /**
2634 * @brief Check if Clock security system interrupt occurred or not
2635 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
2636 * @retval State of bit (1 or 0).
2637 */
LL_RCC_IsActiveFlag_HSECSS(void)2638 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2639 {
2640 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
2641 }
2642
2643 /**
2644 * @brief Check if LSE Clock security system interrupt occurred or not
2645 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
2646 * @retval State of bit (1 or 0).
2647 */
LL_RCC_IsActiveFlag_LSECSS(void)2648 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
2649 {
2650 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
2651 }
2652
2653 /**
2654 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2655 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2656 * @retval State of bit (1 or 0).
2657 */
LL_RCC_IsActiveFlag_IWDGRST(void)2658 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2659 {
2660 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
2661 }
2662
2663 /**
2664 * @brief Check if RCC flag Low Power reset is set or not.
2665 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2666 * @retval State of bit (1 or 0).
2667 */
LL_RCC_IsActiveFlag_LPWRRST(void)2668 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2669 {
2670 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
2671 }
2672
2673 /**
2674 * @brief Check if RCC flag Option byte reset is set or not.
2675 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2676 * @retval State of bit (1 or 0).
2677 */
LL_RCC_IsActiveFlag_OBLRST(void)2678 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2679 {
2680 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
2681 }
2682
2683 /**
2684 * @brief Check if RCC flag Pin reset is set or not.
2685 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2686 * @retval State of bit (1 or 0).
2687 */
LL_RCC_IsActiveFlag_PINRST(void)2688 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2689 {
2690 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
2691 }
2692
2693 /**
2694 * @brief Check if RCC flag Software reset is set or not.
2695 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2696 * @retval State of bit (1 or 0).
2697 */
LL_RCC_IsActiveFlag_SFTRST(void)2698 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2699 {
2700 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
2701 }
2702
2703 /**
2704 * @brief Check if RCC flag Window Watchdog reset is set or not.
2705 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2706 * @retval State of bit (1 or 0).
2707 */
LL_RCC_IsActiveFlag_WWDGRST(void)2708 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2709 {
2710 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
2711 }
2712
2713 /**
2714 * @brief Check if RCC flag BOR reset is set or not.
2715 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
2716 * @retval State of bit (1 or 0).
2717 */
LL_RCC_IsActiveFlag_BORRST(void)2718 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
2719 {
2720 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
2721 }
2722
2723 /**
2724 * @brief Set RMVF bit to clear the reset flags.
2725 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2726 * @retval None
2727 */
LL_RCC_ClearResetFlags(void)2728 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2729 {
2730 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2731 }
2732
2733 /**
2734 * @}
2735 */
2736
2737 /** @defgroup RCC_LL_EF_IT_Management IT Management
2738 * @{
2739 */
2740
2741 /**
2742 * @brief Enable LSI ready interrupt
2743 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
2744 * @retval None
2745 */
LL_RCC_EnableIT_LSIRDY(void)2746 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2747 {
2748 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2749 }
2750
2751 /**
2752 * @brief Enable LSE ready interrupt
2753 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
2754 * @retval None
2755 */
LL_RCC_EnableIT_LSERDY(void)2756 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2757 {
2758 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2759 }
2760
2761 /**
2762 * @brief Enable HSI ready interrupt
2763 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
2764 * @retval None
2765 */
LL_RCC_EnableIT_HSIRDY(void)2766 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2767 {
2768 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2769 }
2770
2771 /**
2772 * @brief Enable HSE ready interrupt
2773 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
2774 * @retval None
2775 */
LL_RCC_EnableIT_HSERDY(void)2776 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2777 {
2778 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2779 }
2780
2781 /**
2782 * @brief Enable PLL ready interrupt
2783 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
2784 * @retval None
2785 */
LL_RCC_EnableIT_PLLRDY(void)2786 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2787 {
2788 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
2789 }
2790
2791 /**
2792 * @brief Enable HSI48 ready interrupt
2793 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
2794 * @retval None
2795 */
LL_RCC_EnableIT_HSI48RDY(void)2796 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
2797 {
2798 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
2799 }
2800
2801 /**
2802 * @brief Enable LSE clock security system interrupt
2803 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
2804 * @retval None
2805 */
LL_RCC_EnableIT_LSECSS(void)2806 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
2807 {
2808 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
2809 }
2810
2811 /**
2812 * @brief Disable LSI ready interrupt
2813 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
2814 * @retval None
2815 */
LL_RCC_DisableIT_LSIRDY(void)2816 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2817 {
2818 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2819 }
2820
2821 /**
2822 * @brief Disable LSE ready interrupt
2823 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
2824 * @retval None
2825 */
LL_RCC_DisableIT_LSERDY(void)2826 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2827 {
2828 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2829 }
2830
2831 /**
2832 * @brief Disable HSI ready interrupt
2833 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
2834 * @retval None
2835 */
LL_RCC_DisableIT_HSIRDY(void)2836 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2837 {
2838 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2839 }
2840
2841 /**
2842 * @brief Disable HSE ready interrupt
2843 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
2844 * @retval None
2845 */
LL_RCC_DisableIT_HSERDY(void)2846 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2847 {
2848 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2849 }
2850
2851 /**
2852 * @brief Disable PLL ready interrupt
2853 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
2854 * @retval None
2855 */
LL_RCC_DisableIT_PLLRDY(void)2856 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2857 {
2858 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
2859 }
2860
2861 /**
2862 * @brief Disable HSI48 ready interrupt
2863 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
2864 * @retval None
2865 */
LL_RCC_DisableIT_HSI48RDY(void)2866 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
2867 {
2868 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
2869 }
2870
2871 /**
2872 * @brief Disable LSE clock security system interrupt
2873 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
2874 * @retval None
2875 */
LL_RCC_DisableIT_LSECSS(void)2876 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
2877 {
2878 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
2879 }
2880
2881 /**
2882 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2883 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2884 * @retval State of bit (1 or 0).
2885 */
LL_RCC_IsEnabledIT_LSIRDY(void)2886 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2887 {
2888 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
2889 }
2890
2891 /**
2892 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2893 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2894 * @retval State of bit (1 or 0).
2895 */
LL_RCC_IsEnabledIT_LSERDY(void)2896 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2897 {
2898 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
2899 }
2900
2901 /**
2902 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2903 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2904 * @retval State of bit (1 or 0).
2905 */
LL_RCC_IsEnabledIT_HSIRDY(void)2906 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2907 {
2908 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
2909 }
2910
2911 /**
2912 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2913 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2914 * @retval State of bit (1 or 0).
2915 */
LL_RCC_IsEnabledIT_HSERDY(void)2916 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2917 {
2918 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
2919 }
2920
2921 /**
2922 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2923 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2924 * @retval State of bit (1 or 0).
2925 */
LL_RCC_IsEnabledIT_PLLRDY(void)2926 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2927 {
2928 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
2929 }
2930
2931 /**
2932 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
2933 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
2934 * @retval State of bit (1 or 0).
2935 */
LL_RCC_IsEnabledIT_HSI48RDY(void)2936 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
2937 {
2938 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
2939 }
2940
2941 /**
2942 * @brief Checks if LSECSS interrupt source is enabled or disabled.
2943 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
2944 * @retval State of bit (1 or 0).
2945 */
LL_RCC_IsEnabledIT_LSECSS(void)2946 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
2947 {
2948 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
2949 }
2950
2951 /**
2952 * @}
2953 */
2954
2955 #if defined(USE_FULL_LL_DRIVER)
2956 /** @defgroup RCC_LL_EF_Init De-initialization function
2957 * @{
2958 */
2959 ErrorStatus LL_RCC_DeInit(void);
2960 /**
2961 * @}
2962 */
2963
2964 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2965 * @{
2966 */
2967 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2968 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2969 #if defined(UART4)
2970 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
2971 #endif /* UART4 */
2972 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2973 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
2974 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
2975 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
2976 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2977 #if defined(FDCAN1)
2978 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
2979 #endif /* FDCAN1 */
2980 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
2981 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2982 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2983 #if defined(QUADSPI)
2984 uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);
2985 #endif /* QUADSPI */
2986 /**
2987 * @}
2988 */
2989 #endif /* USE_FULL_LL_DRIVER */
2990
2991 /**
2992 * @}
2993 */
2994
2995 /**
2996 * @}
2997 */
2998
2999 /**
3000 * @}
3001 */
3002
3003 #ifdef __cplusplus
3004 }
3005 #endif
3006
3007 #endif /* STM32G4xx_LL_RCC_H */
3008
3009
