1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_LPTIM_H
21 #define STM32G4xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
48 * @{
49 */
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
58 * @{
59 */
60
61 /**
62 * @brief LPTIM Init structure definition
63 */
64 typedef struct
65 {
66 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
67 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
68
69 This feature can be modified afterwards using unitary
70 function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary
76 function @ref LL_LPTIM_SetPrescaler().*/
77
78 uint32_t Waveform; /*!< Specifies the waveform shape.
79 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
80
81 This feature can be modified afterwards using unitary
82 function @ref LL_LPTIM_ConfigOutput().*/
83
84 uint32_t Polarity; /*!< Specifies waveform polarity.
85 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
86
87 This feature can be modified afterwards using unitary
88 function @ref LL_LPTIM_ConfigOutput().*/
89 } LL_LPTIM_InitTypeDef;
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
98 * @{
99 */
100
101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
103 * @{
104 */
105 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
106 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
107 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
108 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
109 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
110 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
111 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
112 /**
113 * @}
114 */
115
116 /** @defgroup LPTIM_LL_EC_IT IT Defines
117 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
118 * @{
119 */
120 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
121 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
122 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
123 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
124 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
125 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
126 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
127 /**
128 * @}
129 */
130
131 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
132 * @{
133 */
134 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
135 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
136 /**
137 * @}
138 */
139
140 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
141 * @{
142 */
143 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
144 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
145 /**
146 * @}
147 */
148
149 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
150 * @{
151 */
152 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
153 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
154 /**
155 * @}
156 */
157
158 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
159 * @{
160 */
161 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
162 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
168 * @{
169 */
170 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
171 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
172 /**
173 * @}
174 */
175
176 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
177 * @{
178 */
179 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
180 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
181 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
182 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
183 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
184 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
185 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
186 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
187 /**
188 * @}
189 */
190
191 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
192 * @{
193 */
194 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
195 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
196 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
197 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
198 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
199 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
200 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
201 #define LL_LPTIM_TRIG_SOURCE_COMP2 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP2 output*/
202 #define LL_LPTIM_TRIG_SOURCE_COMP3 LPTIM_CFGR_TRIGSEL_3 /*!<External input trigger is connected to COMP3 output*/
203 #define LL_LPTIM_TRIG_SOURCE_COMP4 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP4 output*/
204 #if defined(COMP5)
205 #define LL_LPTIM_TRIG_SOURCE_COMP5 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP5 output*/
206 #endif /* COMP5 */
207 #if defined(COMP6)
208 #define LL_LPTIM_TRIG_SOURCE_COMP6 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP6 output*/
209 #endif /* COMP6 */
210 #if defined(COMP7)
211 #define LL_LPTIM_TRIG_SOURCE_COMP7 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_2) /*!<External input trigger is connected to COMP7 output*/
212 #endif /* COMP7 */
213 /**
214 * @}
215 */
216
217 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
218 * @{
219 */
220 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
221 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
222 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
223 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
224 /**
225 * @}
226 */
227
228 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
229 * @{
230 */
231 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
232 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
233 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
234 /**
235 * @}
236 */
237
238 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
239 * @{
240 */
241 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
242 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
243 /**
244 * @}
245 */
246
247 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
248 * @{
249 */
250 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
251 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
252 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
253 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
254 /**
255 * @}
256 */
257
258 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
259 * @{
260 */
261 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
262 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
263 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
264 /**
265 * @}
266 */
267
268 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
269 * @{
270 */
271 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
272 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
273 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
274 /**
275 * @}
276 */
277
278 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
279 * @{
280 */
281 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
282 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_IN1_0
283 #define LL_LPTIM_INPUT1_SRC_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
284 #if defined(COMP5)
285 #define LL_LPTIM_INPUT1_SRC_COMP5 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0)
286 #endif /* COMP5 */
287 #if defined(COMP7)
288 #define LL_LPTIM_INPUT1_SRC_COMP7 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
289 #endif /* COMP7 */
290 /**
291 * @}
292 */
293
294 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
295 * @{
296 */
297 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
298 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_IN2_0
299 #define LL_LPTIM_INPUT2_SRC_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
300 #if defined(COMP6)
301 #define LL_LPTIM_INPUT2_SRC_COMP6 (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0)
302 #endif /* COMP6 */
303 /**
304 * @}
305 */
306
307 /**
308 * @}
309 */
310
311 /* Exported macro ------------------------------------------------------------*/
312 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
313 * @{
314 */
315
316 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
317 * @{
318 */
319
320 /**
321 * @brief Write a value in LPTIM register
322 * @param __INSTANCE__ LPTIM Instance
323 * @param __REG__ Register to be written
324 * @param __VALUE__ Value to be written in the register
325 * @retval None
326 */
327 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
328
329 /**
330 * @brief Read a value in LPTIM register
331 * @param __INSTANCE__ LPTIM Instance
332 * @param __REG__ Register to be read
333 * @retval Register value
334 */
335 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
336 /**
337 * @}
338 */
339
340 /**
341 * @}
342 */
343
344 /* Exported functions --------------------------------------------------------*/
345 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
346 * @{
347 */
348
349 /** Legacy definitions for compatibility purpose
350 @cond 0
351 */
352 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
353 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
354 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
355 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
356 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
357 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
358 /**
359 @endcond
360 */
361
362 #if defined(USE_FULL_LL_DRIVER)
363 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
364 * @{
365 */
366
367 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
368 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
369 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
370 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
371 /**
372 * @}
373 */
374 #endif /* USE_FULL_LL_DRIVER */
375
376 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
377 * @{
378 */
379
380 /**
381 * @brief Enable the LPTIM instance
382 * @note After setting the ENABLE bit, a delay of two counter clock is needed
383 * before the LPTIM instance is actually enabled.
384 * @rmtoll CR ENABLE LL_LPTIM_Enable
385 * @param LPTIMx Low-Power Timer instance
386 * @retval None
387 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)388 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
389 {
390 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
391 }
392
393 /**
394 * @brief Indicates whether the LPTIM instance is enabled.
395 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
396 * @param LPTIMx Low-Power Timer instance
397 * @retval State of bit (1 or 0).
398 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)399 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
400 {
401 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
402 }
403
404 /**
405 * @brief Starts the LPTIM counter in the desired mode.
406 * @note LPTIM instance must be enabled before starting the counter.
407 * @note It is possible to change on the fly from One Shot mode to
408 * Continuous mode.
409 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
410 * CR SNGSTRT LL_LPTIM_StartCounter
411 * @param LPTIMx Low-Power Timer instance
412 * @param OperatingMode This parameter can be one of the following values:
413 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
414 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
415 * @retval None
416 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)417 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
418 {
419 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
420 }
421
422 /**
423 * @brief Enable reset after read.
424 * @note After calling this function any read access to LPTIM_CNT
425 * register will asynchronously reset the LPTIM_CNT register content.
426 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
427 * @param LPTIMx Low-Power Timer instance
428 * @retval None
429 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)430 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
431 {
432 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
433 }
434
435 /**
436 * @brief Disable reset after read.
437 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
438 * @param LPTIMx Low-Power Timer instance
439 * @retval None
440 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)441 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
442 {
443 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
444 }
445
446 /**
447 * @brief Indicate whether the reset after read feature is enabled.
448 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
449 * @param LPTIMx Low-Power Timer instance
450 * @retval State of bit (1 or 0).
451 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)452 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
453 {
454 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
455 }
456
457 /**
458 * @brief Reset of the LPTIM_CNT counter register (synchronous).
459 * @note Due to the synchronous nature of this reset, it only takes
460 * place after a synchronization delay of 3 LPTIM core clock cycles
461 * (LPTIM core clock may be different from APB clock).
462 * @note COUNTRST is automatically cleared by hardware
463 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
464 * @param LPTIMx Low-Power Timer instance
465 * @retval None
466 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)467 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
468 {
469 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
470 }
471
472 /**
473 * @brief Set the LPTIM registers update mode (enable/disable register preload)
474 * @note This function must be called when the LPTIM instance is disabled.
475 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
476 * @param LPTIMx Low-Power Timer instance
477 * @param UpdateMode This parameter can be one of the following values:
478 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
479 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
480 * @retval None
481 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)482 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
483 {
484 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
485 }
486
487 /**
488 * @brief Get the LPTIM registers update mode
489 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
490 * @param LPTIMx Low-Power Timer instance
491 * @retval Returned value can be one of the following values:
492 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
493 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
494 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)495 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
496 {
497 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
498 }
499
500 /**
501 * @brief Set the auto reload value
502 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
503 * @note After a write to the LPTIMx_ARR register a new write operation to the
504 * same register can only be performed when the previous write operation
505 * is completed. Any successive write before the ARROK flag is set, will
506 * lead to unpredictable results.
507 * @note autoreload value be strictly greater than the compare value.
508 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
509 * @param LPTIMx Low-Power Timer instance
510 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
511 * @retval None
512 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)513 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
514 {
515 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
516 }
517
518 /**
519 * @brief Get actual auto reload value
520 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
521 * @param LPTIMx Low-Power Timer instance
522 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
523 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)524 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
525 {
526 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
527 }
528
529 /**
530 * @brief Set the compare value
531 * @note After a write to the LPTIMx_CMP register a new write operation to the
532 * same register can only be performed when the previous write operation
533 * is completed. Any successive write before the CMPOK flag is set, will
534 * lead to unpredictable results.
535 * @rmtoll CMP CMP LL_LPTIM_SetCompare
536 * @param LPTIMx Low-Power Timer instance
537 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
538 * @retval None
539 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)540 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
541 {
542 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
543 }
544
545 /**
546 * @brief Get actual compare value
547 * @rmtoll CMP CMP LL_LPTIM_GetCompare
548 * @param LPTIMx Low-Power Timer instance
549 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
550 */
LL_LPTIM_GetCompare(const LPTIM_TypeDef * LPTIMx)551 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
552 {
553 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
554 }
555
556 /**
557 * @brief Get actual counter value
558 * @note When the LPTIM instance is running with an asynchronous clock, reading
559 * the LPTIMx_CNT register may return unreliable values. So in this case
560 * it is necessary to perform two consecutive read accesses and verify
561 * that the two returned values are identical.
562 * @rmtoll CNT CNT LL_LPTIM_GetCounter
563 * @param LPTIMx Low-Power Timer instance
564 * @retval Counter value
565 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)566 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
567 {
568 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
569 }
570
571 /**
572 * @brief Set the counter mode (selection of the LPTIM counter clock source).
573 * @note The counter mode can be set only when the LPTIM instance is disabled.
574 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
575 * @param LPTIMx Low-Power Timer instance
576 * @param CounterMode This parameter can be one of the following values:
577 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
578 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
579 * @retval None
580 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)581 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
582 {
583 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
584 }
585
586 /**
587 * @brief Get the counter mode
588 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
589 * @param LPTIMx Low-Power Timer instance
590 * @retval Returned value can be one of the following values:
591 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
592 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
593 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)594 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
595 {
596 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
597 }
598
599 /**
600 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
601 * @note This function must be called when the LPTIM instance is disabled.
602 * @note Regarding the LPTIM output polarity the change takes effect
603 * immediately, so the output default value will change immediately after
604 * the polarity is re-configured, even before the timer is enabled.
605 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
606 * CFGR WAVPOL LL_LPTIM_ConfigOutput
607 * @param LPTIMx Low-Power Timer instance
608 * @param Waveform This parameter can be one of the following values:
609 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
610 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
611 * @param Polarity This parameter can be one of the following values:
612 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
613 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
614 * @retval None
615 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)616 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
617 {
618 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
619 }
620
621 /**
622 * @brief Set waveform shape
623 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
624 * @param LPTIMx Low-Power Timer instance
625 * @param Waveform This parameter can be one of the following values:
626 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
627 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
628 * @retval None
629 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)630 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
631 {
632 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
633 }
634
635 /**
636 * @brief Get actual waveform shape
637 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
638 * @param LPTIMx Low-Power Timer instance
639 * @retval Returned value can be one of the following values:
640 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
641 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
642 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)643 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
644 {
645 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
646 }
647
648 /**
649 * @brief Set output polarity
650 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
651 * @param LPTIMx Low-Power Timer instance
652 * @param Polarity This parameter can be one of the following values:
653 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
654 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
655 * @retval None
656 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)657 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
658 {
659 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
660 }
661
662 /**
663 * @brief Get actual output polarity
664 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
665 * @param LPTIMx Low-Power Timer instance
666 * @retval Returned value can be one of the following values:
667 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
668 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
669 */
LL_LPTIM_GetPolarity(const LPTIM_TypeDef * LPTIMx)670 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
671 {
672 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
673 }
674
675 /**
676 * @brief Set actual prescaler division ratio.
677 * @note This function must be called when the LPTIM instance is disabled.
678 * @note When the LPTIM is configured to be clocked by an internal clock source
679 * and the LPTIM counter is configured to be updated by active edges
680 * detected on the LPTIM external Input1, the internal clock provided to
681 * the LPTIM must be not be prescaled.
682 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
683 * @param LPTIMx Low-Power Timer instance
684 * @param Prescaler This parameter can be one of the following values:
685 * @arg @ref LL_LPTIM_PRESCALER_DIV1
686 * @arg @ref LL_LPTIM_PRESCALER_DIV2
687 * @arg @ref LL_LPTIM_PRESCALER_DIV4
688 * @arg @ref LL_LPTIM_PRESCALER_DIV8
689 * @arg @ref LL_LPTIM_PRESCALER_DIV16
690 * @arg @ref LL_LPTIM_PRESCALER_DIV32
691 * @arg @ref LL_LPTIM_PRESCALER_DIV64
692 * @arg @ref LL_LPTIM_PRESCALER_DIV128
693 * @retval None
694 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)695 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
696 {
697 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
698 }
699
700 /**
701 * @brief Get actual prescaler division ratio.
702 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
703 * @param LPTIMx Low-Power Timer instance
704 * @retval Returned value can be one of the following values:
705 * @arg @ref LL_LPTIM_PRESCALER_DIV1
706 * @arg @ref LL_LPTIM_PRESCALER_DIV2
707 * @arg @ref LL_LPTIM_PRESCALER_DIV4
708 * @arg @ref LL_LPTIM_PRESCALER_DIV8
709 * @arg @ref LL_LPTIM_PRESCALER_DIV16
710 * @arg @ref LL_LPTIM_PRESCALER_DIV32
711 * @arg @ref LL_LPTIM_PRESCALER_DIV64
712 * @arg @ref LL_LPTIM_PRESCALER_DIV128
713 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)714 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
715 {
716 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
717 }
718
719 /**
720 * @brief Set LPTIM input 1 source (default GPIO).
721 * @rmtoll OR IN1 LL_LPTIM_SetInput1Src
722 * @param LPTIMx Low-Power Timer instance
723 * @param Src This parameter can be one of the following values:
724 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
725 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
726 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP3
727 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP5 (*)
728 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP7 (*)
729 * (*) Value not defined for all devices
730 * @retval None
731 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)732 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
733 {
734 MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN1, Src);
735 }
736
737 /**
738 * @brief Set LPTIM input 2 source (default GPIO).
739 * @rmtoll OR IN2 LL_LPTIM_SetInput2Src
740 * @param LPTIMx Low-Power Timer instance
741 * @param Src This parameter can be one of the following values:
742 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
743 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
744 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP4
745 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP6 (*)
746 * (*) Value not defined for all devices
747 * @retval None
748 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)749 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
750 {
751 MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN2, Src);
752 }
753
754 /**
755 * @}
756 */
757
758 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
759 * @{
760 */
761
762 /**
763 * @brief Enable the timeout function
764 * @note This function must be called when the LPTIM instance is disabled.
765 * @note The first trigger event will start the timer, any successive trigger
766 * event will reset the counter and the timer will restart.
767 * @note The timeout value corresponds to the compare value; if no trigger
768 * occurs within the expected time frame, the MCU is waked-up by the
769 * compare match event.
770 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
771 * @param LPTIMx Low-Power Timer instance
772 * @retval None
773 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)774 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
775 {
776 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
777 }
778
779 /**
780 * @brief Disable the timeout function
781 * @note This function must be called when the LPTIM instance is disabled.
782 * @note A trigger event arriving when the timer is already started will be
783 * ignored.
784 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
785 * @param LPTIMx Low-Power Timer instance
786 * @retval None
787 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)788 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
789 {
790 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
791 }
792
793 /**
794 * @brief Indicate whether the timeout function is enabled.
795 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
796 * @param LPTIMx Low-Power Timer instance
797 * @retval State of bit (1 or 0).
798 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)799 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
800 {
801 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
802 }
803
804 /**
805 * @brief Start the LPTIM counter
806 * @note This function must be called when the LPTIM instance is disabled.
807 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
808 * @param LPTIMx Low-Power Timer instance
809 * @retval None
810 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)811 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
812 {
813 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
814 }
815
816 /**
817 * @brief Configure the external trigger used as a trigger event for the LPTIM.
818 * @note This function must be called when the LPTIM instance is disabled.
819 * @note An internal clock source must be present when a digital filter is
820 * required for the trigger.
821 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
822 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
823 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
824 * @param LPTIMx Low-Power Timer instance
825 * @param Source This parameter can be one of the following values:
826 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
827 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
828 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
829 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
830 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
831 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
832 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
833 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
834 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
835 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
836 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
837 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
838 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
839 *
840 * (*) Value not defined in all devices. \n
841 *
842 * @param Filter This parameter can be one of the following values:
843 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
844 * @arg @ref LL_LPTIM_TRIG_FILTER_2
845 * @arg @ref LL_LPTIM_TRIG_FILTER_4
846 * @arg @ref LL_LPTIM_TRIG_FILTER_8
847 * @param Polarity This parameter can be one of the following values:
848 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
849 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
850 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
851 * @retval None
852 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)853 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
854 {
855 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
856 }
857
858 /**
859 * @brief Get actual external trigger source.
860 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
861 * @param LPTIMx Low-Power Timer instance
862 * @retval Returned value can be one of the following values:
863 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
864 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
865 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
866 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
867 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
868 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
869 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
870 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
871 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
872 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
873 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
874 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
875 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
876 *
877 * (*) Value not defined in all devices. \n
878 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)879 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
880 {
881 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
882 }
883
884 /**
885 * @brief Get actual external trigger filter.
886 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
887 * @param LPTIMx Low-Power Timer instance
888 * @retval Returned value can be one of the following values:
889 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
890 * @arg @ref LL_LPTIM_TRIG_FILTER_2
891 * @arg @ref LL_LPTIM_TRIG_FILTER_4
892 * @arg @ref LL_LPTIM_TRIG_FILTER_8
893 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)894 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
895 {
896 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
897 }
898
899 /**
900 * @brief Get actual external trigger polarity.
901 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
902 * @param LPTIMx Low-Power Timer instance
903 * @retval Returned value can be one of the following values:
904 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
905 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
906 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
907 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)908 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
909 {
910 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
911 }
912
913 /**
914 * @}
915 */
916
917 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
918 * @{
919 */
920
921 /**
922 * @brief Set the source of the clock used by the LPTIM instance.
923 * @note This function must be called when the LPTIM instance is disabled.
924 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
925 * @param LPTIMx Low-Power Timer instance
926 * @param ClockSource This parameter can be one of the following values:
927 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
928 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
929 * @retval None
930 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)931 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
932 {
933 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
934 }
935
936 /**
937 * @brief Get actual LPTIM instance clock source.
938 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
939 * @param LPTIMx Low-Power Timer instance
940 * @retval Returned value can be one of the following values:
941 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
942 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
943 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)944 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
945 {
946 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
947 }
948
949 /**
950 * @brief Configure the active edge or edges used by the counter when
951 the LPTIM is clocked by an external clock source.
952 * @note This function must be called when the LPTIM instance is disabled.
953 * @note When both external clock signal edges are considered active ones,
954 * the LPTIM must also be clocked by an internal clock source with a
955 * frequency equal to at least four times the external clock frequency.
956 * @note An internal clock source must be present when a digital filter is
957 * required for external clock.
958 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
959 * CFGR CKPOL LL_LPTIM_ConfigClock
960 * @param LPTIMx Low-Power Timer instance
961 * @param ClockFilter This parameter can be one of the following values:
962 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
963 * @arg @ref LL_LPTIM_CLK_FILTER_2
964 * @arg @ref LL_LPTIM_CLK_FILTER_4
965 * @arg @ref LL_LPTIM_CLK_FILTER_8
966 * @param ClockPolarity This parameter can be one of the following values:
967 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
968 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
969 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
970 * @retval None
971 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)972 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
973 {
974 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
975 }
976
977 /**
978 * @brief Get actual clock polarity
979 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
980 * @param LPTIMx Low-Power Timer instance
981 * @retval Returned value can be one of the following values:
982 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
983 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
984 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
985 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)986 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
987 {
988 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
989 }
990
991 /**
992 * @brief Get actual clock digital filter
993 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
994 * @param LPTIMx Low-Power Timer instance
995 * @retval Returned value can be one of the following values:
996 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
997 * @arg @ref LL_LPTIM_CLK_FILTER_2
998 * @arg @ref LL_LPTIM_CLK_FILTER_4
999 * @arg @ref LL_LPTIM_CLK_FILTER_8
1000 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1001 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1002 {
1003 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1004 }
1005
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1011 * @{
1012 */
1013
1014 /**
1015 * @brief Configure the encoder mode.
1016 * @note This function must be called when the LPTIM instance is disabled.
1017 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1018 * @param LPTIMx Low-Power Timer instance
1019 * @param EncoderMode This parameter can be one of the following values:
1020 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1021 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1022 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1023 * @retval None
1024 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1025 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1026 {
1027 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1028 }
1029
1030 /**
1031 * @brief Get actual encoder mode.
1032 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1033 * @param LPTIMx Low-Power Timer instance
1034 * @retval Returned value can be one of the following values:
1035 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1036 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1037 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1038 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1039 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1040 {
1041 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1042 }
1043
1044 /**
1045 * @brief Enable the encoder mode
1046 * @note This function must be called when the LPTIM instance is disabled.
1047 * @note In this mode the LPTIM instance must be clocked by an internal clock
1048 * source. Also, the prescaler division ratio must be equal to 1.
1049 * @note LPTIM instance must be configured in continuous mode prior enabling
1050 * the encoder mode.
1051 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1052 * @param LPTIMx Low-Power Timer instance
1053 * @retval None
1054 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1055 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1056 {
1057 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1058 }
1059
1060 /**
1061 * @brief Disable the encoder mode
1062 * @note This function must be called when the LPTIM instance is disabled.
1063 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1064 * @param LPTIMx Low-Power Timer instance
1065 * @retval None
1066 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1067 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1068 {
1069 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1070 }
1071
1072 /**
1073 * @brief Indicates whether the LPTIM operates in encoder mode.
1074 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1075 * @param LPTIMx Low-Power Timer instance
1076 * @retval State of bit (1 or 0).
1077 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1078 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1079 {
1080 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1081 }
1082
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1088 * @{
1089 */
1090
1091
1092 /**
1093 * @brief Clear the compare match flag (CMPMCF)
1094 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM
1095 * @param LPTIMx Low-Power Timer instance
1096 * @retval None
1097 */
LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef * LPTIMx)1098 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1099 {
1100 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1101 }
1102
1103 /**
1104 * @brief Inform application whether a compare match interrupt has occurred.
1105 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1106 * @param LPTIMx Low-Power Timer instance
1107 * @retval State of bit (1 or 0).
1108 */
LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef * LPTIMx)1109 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
1110 {
1111 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
1112 }
1113
1114 /**
1115 * @brief Clear the autoreload match flag (ARRMCF)
1116 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1117 * @param LPTIMx Low-Power Timer instance
1118 * @retval None
1119 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1120 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1121 {
1122 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1123 }
1124
1125 /**
1126 * @brief Inform application whether a autoreload match interrupt has occurred.
1127 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1128 * @param LPTIMx Low-Power Timer instance
1129 * @retval State of bit (1 or 0).
1130 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1131 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1132 {
1133 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1134 }
1135
1136 /**
1137 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1138 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1139 * @param LPTIMx Low-Power Timer instance
1140 * @retval None
1141 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1142 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1143 {
1144 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1145 }
1146
1147 /**
1148 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1149 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1150 * @param LPTIMx Low-Power Timer instance
1151 * @retval State of bit (1 or 0).
1152 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1153 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1154 {
1155 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1156 }
1157
1158 /**
1159 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1160 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1161 * @param LPTIMx Low-Power Timer instance
1162 * @retval None
1163 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1164 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1165 {
1166 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1167 }
1168
1169 /**
1170 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
1171 completed. If so, a new one can be initiated.
1172 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1173 * @param LPTIMx Low-Power Timer instance
1174 * @retval State of bit (1 or 0).
1175 */
LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef * LPTIMx)1176 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
1177 {
1178 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1179 }
1180
1181 /**
1182 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1183 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1184 * @param LPTIMx Low-Power Timer instance
1185 * @retval None
1186 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1187 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1188 {
1189 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1190 }
1191
1192 /**
1193 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1194 completed. If so, a new one can be initiated.
1195 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1196 * @param LPTIMx Low-Power Timer instance
1197 * @retval State of bit (1 or 0).
1198 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1199 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1200 {
1201 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1202 }
1203
1204 /**
1205 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1206 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1207 * @param LPTIMx Low-Power Timer instance
1208 * @retval None
1209 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1210 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1211 {
1212 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1213 }
1214
1215 /**
1216 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1217 operates in encoder mode).
1218 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1219 * @param LPTIMx Low-Power Timer instance
1220 * @retval State of bit (1 or 0).
1221 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1222 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1223 {
1224 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1225 }
1226
1227 /**
1228 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1229 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1230 * @param LPTIMx Low-Power Timer instance
1231 * @retval None
1232 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1233 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1234 {
1235 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1236 }
1237
1238 /**
1239 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1240 operates in encoder mode).
1241 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1242 * @param LPTIMx Low-Power Timer instance
1243 * @retval State of bit (1 or 0).
1244 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1245 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1246 {
1247 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1248 }
1249
1250 /**
1251 * @}
1252 */
1253
1254 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1255 * @{
1256 */
1257
1258 /**
1259 * @brief Enable compare match interrupt (CMPMIE).
1260 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1261 * @param LPTIMx Low-Power Timer instance
1262 * @retval None
1263 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1264 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1265 {
1266 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1267 }
1268
1269 /**
1270 * @brief Disable compare match interrupt (CMPMIE).
1271 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1272 * @param LPTIMx Low-Power Timer instance
1273 * @retval None
1274 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1275 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1276 {
1277 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1278 }
1279
1280 /**
1281 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1282 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1283 * @param LPTIMx Low-Power Timer instance
1284 * @retval State of bit (1 or 0).
1285 */
LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef * LPTIMx)1286 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
1287 {
1288 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1289 }
1290
1291 /**
1292 * @brief Enable autoreload match interrupt (ARRMIE).
1293 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1294 * @param LPTIMx Low-Power Timer instance
1295 * @retval None
1296 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1297 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1298 {
1299 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1300 }
1301
1302 /**
1303 * @brief Disable autoreload match interrupt (ARRMIE).
1304 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1305 * @param LPTIMx Low-Power Timer instance
1306 * @retval None
1307 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1308 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1309 {
1310 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1311 }
1312
1313 /**
1314 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1315 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1316 * @param LPTIMx Low-Power Timer instance
1317 * @retval State of bit (1 or 0).
1318 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)1319 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
1320 {
1321 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1322 }
1323
1324 /**
1325 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1326 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1327 * @param LPTIMx Low-Power Timer instance
1328 * @retval None
1329 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1330 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1331 {
1332 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1333 }
1334
1335 /**
1336 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1337 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1338 * @param LPTIMx Low-Power Timer instance
1339 * @retval None
1340 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1341 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1342 {
1343 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1344 }
1345
1346 /**
1347 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1348 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1349 * @param LPTIMx Low-Power Timer instance
1350 * @retval State of bit (1 or 0).
1351 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1352 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1353 {
1354 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1355 }
1356
1357 /**
1358 * @brief Enable compare register write completed interrupt (CMPOKIE).
1359 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1360 * @param LPTIMx Low-Power Timer instance
1361 * @retval None
1362 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1363 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1364 {
1365 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1366 }
1367
1368 /**
1369 * @brief Disable compare register write completed interrupt (CMPOKIE).
1370 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1371 * @param LPTIMx Low-Power Timer instance
1372 * @retval None
1373 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1374 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1375 {
1376 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1377 }
1378
1379 /**
1380 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1381 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1382 * @param LPTIMx Low-Power Timer instance
1383 * @retval State of bit (1 or 0).
1384 */
LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef * LPTIMx)1385 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
1386 {
1387 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1388 }
1389
1390 /**
1391 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1392 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1393 * @param LPTIMx Low-Power Timer instance
1394 * @retval None
1395 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1396 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1397 {
1398 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1399 }
1400
1401 /**
1402 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1403 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1404 * @param LPTIMx Low-Power Timer instance
1405 * @retval None
1406 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1407 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1408 {
1409 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1410 }
1411
1412 /**
1413 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1414 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1415 * @param LPTIMx Low-Power Timer instance
1416 * @retval State of bit(1 or 0).
1417 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)1418 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
1419 {
1420 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1421 }
1422
1423 /**
1424 * @brief Enable direction change to up interrupt (UPIE).
1425 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1426 * @param LPTIMx Low-Power Timer instance
1427 * @retval None
1428 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1429 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1430 {
1431 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1432 }
1433
1434 /**
1435 * @brief Disable direction change to up interrupt (UPIE).
1436 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1437 * @param LPTIMx Low-Power Timer instance
1438 * @retval None
1439 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1440 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1441 {
1442 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1443 }
1444
1445 /**
1446 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1447 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1448 * @param LPTIMx Low-Power Timer instance
1449 * @retval State of bit(1 or 0).
1450 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)1451 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
1452 {
1453 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1454 }
1455
1456 /**
1457 * @brief Enable direction change to down interrupt (DOWNIE).
1458 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1459 * @param LPTIMx Low-Power Timer instance
1460 * @retval None
1461 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1462 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1463 {
1464 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1465 }
1466
1467 /**
1468 * @brief Disable direction change to down interrupt (DOWNIE).
1469 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1470 * @param LPTIMx Low-Power Timer instance
1471 * @retval None
1472 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1473 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1474 {
1475 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1476 }
1477
1478 /**
1479 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1480 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1481 * @param LPTIMx Low-Power Timer instance
1482 * @retval State of bit(1 or 0).
1483 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)1484 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
1485 {
1486 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1487 }
1488
1489 /**
1490 * @}
1491 */
1492
1493 /**
1494 * @}
1495 */
1496
1497 /**
1498 * @}
1499 */
1500
1501
1502
1503 /**
1504 * @}
1505 */
1506
1507 #ifdef __cplusplus
1508 }
1509 #endif
1510
1511 #endif /* STM32G4xx_LL_LPTIM_H */
1512
