1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_LL_FMC_H 21 #define STM32G4xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /** @addtogroup STM32G4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FMC_BANK1) 42 43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FMC_NORSRAM_BANK4)) 47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 59 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 60 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 61 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 62 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 63 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 64 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 65 ((__MODE__) == FMC_ACCESS_MODE_D)) 66 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 67 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 68 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 69 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 70 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 71 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 72 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 73 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 74 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 75 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 76 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 77 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 78 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 79 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 80 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 81 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 82 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 83 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 84 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 85 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 86 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 87 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 88 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 89 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 90 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 91 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 92 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 93 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 94 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 95 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 96 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 97 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 98 99 #endif /* FMC_BANK1 */ 100 #if defined(FMC_BANK3) 101 102 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 103 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 104 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 105 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 106 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 107 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 108 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 109 110 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 111 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 112 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 113 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 114 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 115 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 116 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 117 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 118 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 119 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 120 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 121 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 122 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 123 124 #endif /* FMC_BANK3 */ 125 126 /** 127 * @} 128 */ 129 130 /* Exported typedef ----------------------------------------------------------*/ 131 132 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 133 * @{ 134 */ 135 136 #if defined(FMC_BANK1) 137 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 138 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 139 #endif /* FMC_BANK1 */ 140 #if defined(FMC_BANK3) 141 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 142 #endif /* FMC_BANK3 */ 143 144 #if defined(FMC_BANK1) 145 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 146 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 147 #endif /* FMC_BANK1 */ 148 #if defined(FMC_BANK3) 149 #define FMC_NAND_DEVICE FMC_Bank3_R 150 #endif /* FMC_BANK3 */ 151 152 #if defined(FMC_BANK1) 153 /** 154 * @brief FMC NORSRAM Configuration Structure definition 155 */ 156 typedef struct 157 { 158 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 159 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 160 161 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 162 multiplexed on the data bus or not. 163 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ 164 165 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 166 the corresponding memory device. 167 This parameter can be a value of @ref FMC_Memory_Type */ 168 169 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 170 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 171 172 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 173 valid only with synchronous burst Flash memories. 174 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 175 176 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 177 the Flash memory in burst mode. 178 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 179 180 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 181 clock cycle before the wait state or during the wait state, 182 valid only when accessing memories in burst mode. 183 This parameter can be a value of @ref FMC_Wait_Timing */ 184 185 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device 186 by the FMC. 187 This parameter can be a value of @ref FMC_Write_Operation */ 188 189 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 190 signal, valid for Flash memory access in burst mode. 191 This parameter can be a value of @ref FMC_Wait_Signal */ 192 193 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 194 This parameter can be a value of @ref FMC_Extended_Mode */ 195 196 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 197 valid only with asynchronous Flash memories. 198 This parameter can be a value of @ref FMC_AsynchronousWait */ 199 200 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 201 This parameter can be a value of @ref FMC_Write_Burst */ 202 203 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 204 This parameter is only enabled through the FMC_BCR1 register, 205 and don't care through FMC_BCR2..4 registers. 206 This parameter can be a value of @ref FMC_Continous_Clock */ 207 208 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 209 This parameter is only enabled through the FMC_BCR1 register, 210 and don't care through FMC_BCR2..4 registers. 211 This parameter can be a value of @ref FMC_Write_FIFO */ 212 213 uint32_t PageSize; /*!< Specifies the memory page size. 214 This parameter can be a value of @ref FMC_Page_Size */ 215 216 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 217 This parameter can be a value of @ref FMC_Byte_Lane */ 218 219 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this 220 NSBank for PSRAM refresh. 221 This parameter can be set to ENABLE or DISABLE */ 222 223 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for 224 synchronous accesses and in HCLK cycles for asynchronous accesses, 225 valid only if MaxChipSelectPulse is ENABLE. 226 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 227 @note: This parameter is common to all NSBank. */ 228 } FMC_NORSRAM_InitTypeDef; 229 230 /** 231 * @brief FMC NORSRAM Timing parameters structure definition 232 */ 233 typedef struct 234 { 235 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 236 the duration of the address setup time. 237 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 238 @note This parameter is not used with synchronous NOR Flash memories. */ 239 240 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 241 the duration of the address hold time. 242 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 243 @note This parameter is not used with synchronous NOR Flash memories. */ 244 245 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 246 the duration of the data setup time. 247 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 248 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 249 NOR Flash memories. */ 250 251 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 252 the duration of the data hold time. 253 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 254 @note This parameter is used for used in asynchronous accesses. */ 255 256 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 257 the duration of the bus turnaround. 258 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 259 @note This parameter is only used for multiplexed NOR Flash memories. */ 260 261 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 262 HCLK cycles. This parameter can be a value between Min_Data = 2 and 263 Max_Data = 16. 264 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 265 accesses. */ 266 267 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 268 to the memory before getting the first data. 269 The parameter value depends on the memory type as shown below: 270 - It must be set to 0 in case of a CRAM 271 - It is don't care in asynchronous NOR, SRAM or ROM accesses 272 - It may assume a value between Min_Data = 2 and Max_Data = 17 273 in NOR Flash memories with synchronous burst mode enable */ 274 275 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 276 This parameter can be a value of @ref FMC_Access_Mode */ 277 } FMC_NORSRAM_TimingTypeDef; 278 #endif /* FMC_BANK1 */ 279 280 #if defined(FMC_BANK3) 281 /** 282 * @brief FMC NAND Configuration Structure definition 283 */ 284 typedef struct 285 { 286 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 287 This parameter can be a value of @ref FMC_NAND_Bank */ 288 289 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 290 This parameter can be any value of @ref FMC_Wait_feature */ 291 292 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 293 This parameter can be any value of @ref FMC_NAND_Data_Width */ 294 295 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 296 This parameter can be any value of @ref FMC_ECC */ 297 298 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 299 This parameter can be any value of @ref FMC_ECC_Page_Size */ 300 301 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 302 delay between CLE low and RE low. 303 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 304 305 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 306 delay between ALE low and RE low. 307 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 308 } FMC_NAND_InitTypeDef; 309 #endif /* FMC_BANK3 */ 310 311 #if defined(FMC_BANK3) 312 /** 313 * @brief FMC NAND Timing parameters structure definition 314 */ 315 typedef struct 316 { 317 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 318 the command assertion for NAND-Flash read or write access 319 to common/Attribute or I/O memory space (depending on 320 the memory space timing to be configured). 321 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 322 323 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 324 command for NAND-Flash read or write access to 325 common/Attribute or I/O memory space (depending on the 326 memory space timing to be configured). 327 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 328 329 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 330 (and data for write access) after the command de-assertion 331 for NAND-Flash read or write access to common/Attribute 332 or I/O memory space (depending on the memory space timing 333 to be configured). 334 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 335 336 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 337 data bus is kept in HiZ after the start of a NAND-Flash 338 write access to common/Attribute or I/O memory space (depending 339 on the memory space timing to be configured). 340 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 341 } FMC_NAND_PCC_TimingTypeDef; 342 #endif /* FMC_BANK3 */ 343 344 345 /** 346 * @} 347 */ 348 349 /* Exported constants --------------------------------------------------------*/ 350 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 351 * @{ 352 */ 353 #if defined(FMC_BANK1) 354 355 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 356 * @{ 357 */ 358 359 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 360 * @{ 361 */ 362 #define FMC_NORSRAM_BANK1 (0x00000000U) 363 #define FMC_NORSRAM_BANK2 (0x00000002U) 364 #define FMC_NORSRAM_BANK3 (0x00000004U) 365 #define FMC_NORSRAM_BANK4 (0x00000006U) 366 /** 367 * @} 368 */ 369 370 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 371 * @{ 372 */ 373 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 374 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 375 /** 376 * @} 377 */ 378 379 /** @defgroup FMC_Memory_Type FMC Memory Type 380 * @{ 381 */ 382 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 383 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 384 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 385 /** 386 * @} 387 */ 388 389 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 390 * @{ 391 */ 392 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 393 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 394 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 395 /** 396 * @} 397 */ 398 399 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 400 * @{ 401 */ 402 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 403 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 404 /** 405 * @} 406 */ 407 408 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 409 * @{ 410 */ 411 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 412 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 413 /** 414 * @} 415 */ 416 417 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 418 * @{ 419 */ 420 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 421 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 422 /** 423 * @} 424 */ 425 426 /** @defgroup FMC_Wait_Timing FMC Wait Timing 427 * @{ 428 */ 429 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 430 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 431 /** 432 * @} 433 */ 434 435 /** @defgroup FMC_Write_Operation FMC Write Operation 436 * @{ 437 */ 438 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 439 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 440 /** 441 * @} 442 */ 443 444 /** @defgroup FMC_Wait_Signal FMC Wait Signal 445 * @{ 446 */ 447 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 448 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 449 /** 450 * @} 451 */ 452 453 /** @defgroup FMC_Extended_Mode FMC Extended Mode 454 * @{ 455 */ 456 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 457 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 458 /** 459 * @} 460 */ 461 462 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 463 * @{ 464 */ 465 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 466 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 467 /** 468 * @} 469 */ 470 471 /** @defgroup FMC_Page_Size FMC Page Size 472 * @{ 473 */ 474 #define FMC_PAGE_SIZE_NONE (0x00000000U) 475 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 476 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 477 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 478 | FMC_BCRx_CPSIZE_1) 479 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 480 /** 481 * @} 482 */ 483 484 /** @defgroup FMC_Write_Burst FMC Write Burst 485 * @{ 486 */ 487 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 488 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 489 /** 490 * @} 491 */ 492 493 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 494 * @{ 495 */ 496 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 497 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 498 /** 499 * @} 500 */ 501 502 #if defined(FMC_BCR1_WFDIS) 503 /** @defgroup FMC_Write_FIFO FMC Write FIFO 504 * @{ 505 */ 506 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 507 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 508 #endif /* FMC_BCR1_WFDIS */ 509 /** 510 * @} 511 */ 512 513 /** @defgroup FMC_Access_Mode FMC Access Mode 514 * @{ 515 */ 516 #define FMC_ACCESS_MODE_A (0x00000000U) 517 #define FMC_ACCESS_MODE_B (0x10000000U) 518 #define FMC_ACCESS_MODE_C (0x20000000U) 519 #define FMC_ACCESS_MODE_D (0x30000000U) 520 /** 521 * @} 522 */ 523 524 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 525 * @{ 526 */ 527 #define FMC_NBL_SETUPTIME_0 (0x00000000U) 528 #define FMC_NBL_SETUPTIME_1 (0x00400000U) 529 #define FMC_NBL_SETUPTIME_2 (0x00800000U) 530 #define FMC_NBL_SETUPTIME_3 (0x00C00000U) 531 /** 532 * @} 533 */ 534 535 /** 536 * @} 537 */ 538 #endif /* FMC_BANK1 */ 539 540 #if defined(FMC_BANK3) 541 542 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 543 * @{ 544 */ 545 /** @defgroup FMC_NAND_Bank FMC NAND Bank 546 * @{ 547 */ 548 #define FMC_NAND_BANK3 (0x00000100U) 549 /** 550 * @} 551 */ 552 553 /** @defgroup FMC_Wait_feature FMC Wait feature 554 * @{ 555 */ 556 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 557 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 558 /** 559 * @} 560 */ 561 562 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 563 * @{ 564 */ 565 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 566 /** 567 * @} 568 */ 569 570 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 571 * @{ 572 */ 573 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 574 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 575 /** 576 * @} 577 */ 578 579 /** @defgroup FMC_ECC FMC ECC 580 * @{ 581 */ 582 #define FMC_NAND_ECC_DISABLE (0x00000000U) 583 #define FMC_NAND_ECC_ENABLE (0x00000040U) 584 /** 585 * @} 586 */ 587 588 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 589 * @{ 590 */ 591 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 592 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 593 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 594 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 595 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 596 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 597 /** 598 * @} 599 */ 600 601 /** 602 * @} 603 */ 604 #endif /* FMC_BANK3 */ 605 606 607 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 608 * @{ 609 */ 610 #if defined(FMC_BANK3) 611 #define FMC_IT_RISING_EDGE (0x00000008U) 612 #define FMC_IT_LEVEL (0x00000010U) 613 #define FMC_IT_FALLING_EDGE (0x00000020U) 614 #endif /* FMC_BANK3 */ 615 /** 616 * @} 617 */ 618 619 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 620 * @{ 621 */ 622 #if defined(FMC_BANK3) 623 #define FMC_FLAG_RISING_EDGE (0x00000001U) 624 #define FMC_FLAG_LEVEL (0x00000002U) 625 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 626 #define FMC_FLAG_FEMPT (0x00000040U) 627 #endif /* FMC_BANK3 */ 628 /** 629 * @} 630 */ 631 632 /** 633 * @} 634 */ 635 636 /** 637 * @} 638 */ 639 640 /* Private macro -------------------------------------------------------------*/ 641 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 642 * @{ 643 */ 644 #if defined(FMC_BANK1) 645 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 646 * @brief macros to handle NOR device enable/disable and read/write operations 647 * @{ 648 */ 649 650 /** 651 * @brief Enable the NORSRAM device access. 652 * @param __INSTANCE__ FMC_NORSRAM Instance 653 * @param __BANK__ FMC_NORSRAM Bank 654 * @retval None 655 */ 656 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 657 |= FMC_BCRx_MBKEN) 658 659 /** 660 * @brief Disable the NORSRAM device access. 661 * @param __INSTANCE__ FMC_NORSRAM Instance 662 * @param __BANK__ FMC_NORSRAM Bank 663 * @retval None 664 */ 665 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 666 &= ~FMC_BCRx_MBKEN) 667 668 /** 669 * @} 670 */ 671 #endif /* FMC_BANK1 */ 672 673 #if defined(FMC_BANK3) 674 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 675 * @brief macros to handle NAND device enable/disable 676 * @{ 677 */ 678 679 /** 680 * @brief Enable the NAND device access. 681 * @param __INSTANCE__ FMC_NAND Instance 682 * @retval None 683 */ 684 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 685 686 /** 687 * @brief Disable the NAND device access. 688 * @param __INSTANCE__ FMC_NAND Instance 689 * @param __BANK__ FMC_NAND Bank 690 * @retval None 691 */ 692 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 693 694 /** 695 * @} 696 */ 697 #endif /* FMC_BANK3 */ 698 699 #if defined(FMC_BANK3) 700 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 701 * @brief macros to handle NAND interrupts 702 * @{ 703 */ 704 705 /** 706 * @brief Enable the NAND device interrupt. 707 * @param __INSTANCE__ FMC_NAND instance 708 * @param __INTERRUPT__ FMC_NAND interrupt 709 * This parameter can be any combination of the following values: 710 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 711 * @arg FMC_IT_LEVEL: Interrupt level. 712 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 713 * @retval None 714 */ 715 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 716 717 /** 718 * @brief Disable the NAND device interrupt. 719 * @param __INSTANCE__ FMC_NAND Instance 720 * @param __INTERRUPT__ FMC_NAND interrupt 721 * This parameter can be any combination of the following values: 722 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 723 * @arg FMC_IT_LEVEL: Interrupt level. 724 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 725 * @retval None 726 */ 727 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 728 729 /** 730 * @brief Get flag status of the NAND device. 731 * @param __INSTANCE__ FMC_NAND Instance 732 * @param __BANK__ FMC_NAND Bank 733 * @param __FLAG__ FMC_NAND flag 734 * This parameter can be any combination of the following values: 735 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 736 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 737 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 738 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 739 * @retval The state of FLAG (SET or RESET). 740 */ 741 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 742 743 /** 744 * @brief Clear flag status of the NAND device. 745 * @param __INSTANCE__ FMC_NAND Instance 746 * @param __FLAG__ FMC_NAND flag 747 * This parameter can be any combination of the following values: 748 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 749 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 750 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 751 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 752 * @retval None 753 */ 754 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 755 756 /** 757 * @} 758 */ 759 #endif /* FMC_BANK3 */ 760 761 762 /** 763 * @} 764 */ 765 766 /** 767 * @} 768 */ 769 770 /* Private functions ---------------------------------------------------------*/ 771 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 772 * @{ 773 */ 774 775 #if defined(FMC_BANK1) 776 /** @defgroup FMC_LL_NORSRAM NOR SRAM 777 * @{ 778 */ 779 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 780 * @{ 781 */ 782 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 783 const FMC_NORSRAM_InitTypeDef *Init); 784 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 785 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 786 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 787 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 788 uint32_t ExtendedMode); 789 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 790 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 791 /** 792 * @} 793 */ 794 795 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 796 * @{ 797 */ 798 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 799 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 800 /** 801 * @} 802 */ 803 /** 804 * @} 805 */ 806 #endif /* FMC_BANK1 */ 807 808 #if defined(FMC_BANK3) 809 /** @defgroup FMC_LL_NAND NAND 810 * @{ 811 */ 812 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 813 * @{ 814 */ 815 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); 816 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 817 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 818 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 819 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 820 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 821 /** 822 * @} 823 */ 824 825 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 826 * @{ 827 */ 828 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 829 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 830 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 831 uint32_t Timeout); 832 /** 833 * @} 834 */ 835 /** 836 * @} 837 */ 838 #endif /* FMC_BANK3 */ 839 840 841 /** 842 * @} 843 */ 844 845 /** 846 * @} 847 */ 848 849 /** 850 * @} 851 */ 852 853 #ifdef __cplusplus 854 } 855 #endif 856 857 #endif /* STM32G4xx_LL_FMC_H */ 858
