1 /**
2   ******************************************************************************
3   * @file    stm32g0xx_ll_usb.h
4   * @author  MCD Application Team
5   * @brief   Header file of USB Low Layer HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2018 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G0xx_LL_USB_H
21 #define STM32G0xx_LL_USB_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g0xx_hal_def.h"
29 
30 #if defined (USB_DRD_FS)
31 /** @addtogroup STM32G0xx_HAL_Driver
32   * @{
33   */
34 
35 /** @addtogroup USB_LL
36   * @{
37   */
38 
39 /* Exported types ------------------------------------------------------------*/
40 #ifndef HAL_USB_TIMEOUT
41 #define HAL_USB_TIMEOUT                                       0xF000000U
42 #endif /* define HAL_USB_TIMEOUT */
43 
44 /**
45   * @brief  USB Mode definition
46   */
47 
48 typedef enum
49 {
50   USB_DEVICE_MODE = 0,
51   USB_HOST_MODE   = 1
52 } USB_ModeTypeDef;
53 
54 /**
55   * @brief  URB States definition
56   */
57 typedef enum
58 {
59   URB_IDLE = 0,
60   URB_DONE,
61   URB_NOTREADY,
62   URB_NYET,
63   URB_ERROR,
64   URB_STALL
65 } USB_URBStateTypeDef;
66 
67 /**
68   * @brief  Host channel States  definition
69   */
70 typedef enum
71 {
72   HC_IDLE = 0,
73   HC_XFRC,
74   HC_HALTED,
75   HC_ACK,
76   HC_NAK,
77   HC_NYET,
78   HC_STALL,
79   HC_XACTERR,
80   HC_BBLERR,
81   HC_DATATGLERR
82 } USB_HCStateTypeDef;
83 
84 
85 /**
86   * @brief  USB Instance Initialization Structure definition
87   */
88 typedef struct
89 {
90   uint8_t dev_endpoints;            /*!< Device Endpoints number.
91                                          This parameter depends on the used USB core.
92                                          This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
93 
94   uint8_t Host_channels;            /*!< Host Channels number.
95                                          This parameter Depends on the used USB core.
96                                          This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
97 
98   uint8_t dma_enable;              /*!< USB DMA state.
99                                          If DMA is not supported this parameter shall be set by default to zero */
100 
101   uint8_t speed;                   /*!< USB Core speed.
102                                         This parameter can be any value of @ref PCD_Speed/HCD_Speed
103                                                                                 (HCD_SPEED_xxx, HCD_SPEED_xxx) */
104 
105   uint8_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
106 
107   uint8_t phy_itface;              /*!< Select the used PHY interface.
108                                         This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module  */
109 
110   uint8_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
111 
112   uint8_t low_power_enable;        /*!< Enable or disable the low Power Mode.                                  */
113 
114   uint8_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
115 
116   uint8_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
117 
118   uint8_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
119 
120   uint8_t bulk_doublebuffer_enable;  /*!< Enable or disable the double buffer mode on bulk EP                  */
121 
122   uint8_t iso_singlebuffer_enable;   /*!< Enable or disable the Single buffer mode on Isochronous  EP          */
123 } USB_CfgTypeDef;
124 
125 typedef struct
126 {
127   uint8_t   num;                  /*!< Endpoint number
128                                        This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
129 
130   uint8_t   is_in;                /*!< Endpoint direction
131                                        This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
132 
133   uint8_t   is_stall;             /*!< Endpoint stall condition
134                                        This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
135 
136   uint8_t   type;                 /*!< Endpoint type
137                                        This parameter can be any value of @ref USB_LL_EP_Type                   */
138 
139   uint8_t   data_pid_start;       /*!< Initial data PID
140                                        This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
141 
142 
143   uint16_t  pmaadress;            /*!< PMA Address
144                                        This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
145 
146   uint16_t  pmaaddr0;             /*!< PMA Address0
147                                        This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
148 
149   uint16_t  pmaaddr1;             /*!< PMA Address1
150                                        This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */
151 
152   uint8_t   doublebuffer;         /*!< Double buffer enable
153                                        This parameter can be 0 or 1                                             */
154 
155 
156   uint32_t  maxpacket;            /*!< Endpoint Max packet size
157                                        This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
158 
159   uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
160 
161   uint32_t  xfer_len;             /*!< Current transfer length                                                  */
162 
163   uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
164 
165   uint32_t  xfer_len_db;          /*!< double buffer transfer length used with bulk double buffer in            */
166 
167   uint8_t   xfer_fill_db;         /*!< double buffer Need to Fill new buffer  used with bulk_in                 */
168 } USB_EPTypeDef;
169 
170 typedef struct
171 {
172   uint8_t   dev_addr;           /*!< USB device address.
173                                      This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
174 
175   uint8_t   phy_ch_num;         /*!< Host channel number.
176                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
177 
178   uint8_t   ep_num;             /*!< Endpoint number.
179                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
180 
181   uint8_t   ch_dir;             /*!< channel direction
182                                      This parameter store the physical channel direction IN/OUT/BIDIR           */
183 
184   uint8_t   speed;              /*!< USB Host Channel speed.
185                                      This parameter can be any value of @ref HCD_Device_Speed:
186                                                                              (HCD_DEVICE_SPEED_xxx)             */
187 
188   uint8_t   hub_port_nbr;       /*!< USB HUB port number                                                        */
189   uint8_t   hub_addr;           /*!< USB HUB address                                                            */
190 
191   uint8_t   ep_type;            /*!< Endpoint Type.
192                                      This parameter can be any value of @ref USB_LL_EP_Type                     */
193 
194   uint16_t  max_packet;         /*!< Endpoint Max packet size.
195                                      This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
196 
197   uint8_t   data_pid;           /*!< Initial data PID.
198                                      This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
199 
200   uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */
201 
202   uint32_t  xfer_len;           /*!< Current transfer length.                                                   */
203 
204   uint32_t  xfer_len_db;        /*!< Current transfer length used in double buffer mode.                        */
205 
206 
207   uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */
208 
209   uint8_t   toggle_in;          /*!< IN transfer current toggle flag.
210                                      This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
211 
212   uint8_t   toggle_out;         /*!< OUT transfer current toggle flag
213                                      This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
214 
215   uint32_t  ErrCnt;             /*!< Host channel error count.                                                  */
216 
217   uint16_t  pmaadress;          /*!< PMA Address
218                                      This parameter can be any value between Min_addr = 0 and Max_addr = 1K     */
219 
220   uint16_t  pmaaddr0;           /*!< PMA Address0
221                                      This parameter can be any value between Min_addr = 0 and Max_addr = 1K     */
222 
223   uint16_t  pmaaddr1;           /*!< PMA Address1
224                                      This parameter can be any value between Min_addr = 0 and Max_addr = 1K     */
225 
226   uint8_t   doublebuffer;       /*!< Double buffer enable
227                                      This parameter can be 0 or 1                                               */
228 
229   USB_URBStateTypeDef urb_state;  /*!< URB state.
230                                        This parameter can be any value of @ref USB_URBStateTypeDef              */
231 
232   USB_HCStateTypeDef state;       /*!< Host Channel state.
233                                        This parameter can be any value of @ref USB_HCStateTypeDef               */
234 } USB_HCTypeDef;
235 
236 typedef USB_ModeTypeDef     USB_DRD_ModeTypeDef;
237 typedef USB_CfgTypeDef      USB_DRD_CfgTypeDef;
238 typedef USB_EPTypeDef       USB_DRD_EPTypeDef;
239 typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef;
240 typedef USB_HCStateTypeDef  USB_DRD_HCStateTypeDef;
241 typedef USB_HCTypeDef       USB_DRD_HCTypeDef;
242 
243 /* Exported constants --------------------------------------------------------*/
244 
245 /** @defgroup PCD_Exported_Constants PCD Exported Constants
246   * @{
247   */
248 /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
249   * @{
250   */
251 #define EP_MPS_64                              0U
252 #define EP_MPS_32                              1U
253 #define EP_MPS_16                              2U
254 #define EP_MPS_8                               3U
255 /**
256   * @}
257   */
258 
259 /** @defgroup USB_LL_EP_Type USB Low Layer EP Type
260   * @{
261   */
262 #define EP_TYPE_CTRL                           0U
263 #define EP_TYPE_ISOC                           1U
264 #define EP_TYPE_BULK                           2U
265 #define EP_TYPE_INTR                           3U
266 #define EP_TYPE_MSK                            3U
267 /**
268   * @}
269   */
270 
271 /** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
272   * @{
273   */
274 #define EP_SPEED_LOW                           0U
275 #define EP_SPEED_FULL                          1U
276 #define EP_SPEED_HIGH                          2U
277 /**
278   * @}
279   */
280 
281 /** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type
282   * @{
283   */
284 #define HC_PID_DATA0                           0U
285 #define HC_PID_DATA2                           1U
286 #define HC_PID_DATA1                           2U
287 #define HC_PID_SETUP                           3U
288 /**
289   * @}
290   */
291 
292 /** @defgroup USB_LL Device Speed
293   * @{
294   */
295 #define USBD_FS_SPEED                          2U
296 #define USBH_FSLS_SPEED                        1U
297 /**
298   * @}
299   */
300 
301 #define EP_ADDR_MSK                            0x7U
302 
303 #ifndef USE_USB_DOUBLE_BUFFER
304 #define USE_USB_DOUBLE_BUFFER                  1U
305 #endif /* USE_USB_DOUBLE_BUFFER */
306 
307 #define USB_EMBEDDED_PHY                       2U
308 
309 /*!< USB Speed */
310 #define USB_DRD_SPEED_FS                       1U
311 #define USB_DRD_SPEED_LS                       2U
312 #define USB_DRD_SPEED_LSFS                     3U
313 
314 /*!< Channel Direction  */
315 #define CH_IN_DIR                              1U
316 #define CH_OUT_DIR                             0U
317 
318 /*!< Number of used channels in the Application */
319 #ifndef USB_DRD_USED_CHANNELS
320 #define USB_DRD_USED_CHANNELS                  8U
321 #endif /* USB_DRD_USED_CHANNELS */
322 
323 /**
324   * used for USB_HC_DoubleBuffer API
325   */
326 #define USB_DRD_BULK_DBUFF_ENBALE                   1U
327 #define USB_DRD_BULK_DBUFF_DISABLE                  2U
328 #define USB_DRD_ISOC_DBUFF_ENBALE                   3U
329 #define USB_DRD_ISOC_DBUFF_DISABLE                  4U
330 
331 /* First available address in PMA */
332 #define PMA_START_ADDR          (0x10U + (8U *(USB_DRD_USED_CHANNELS - 2U)))
333 #define PMA_END_ADDR             USB_DRD_PMA_SIZE
334 
335 /* Exported macro ------------------------------------------------------------*/
336 /**
337   * @}
338   */
339 /********************  Bit definition for USB_COUNTn_RX register  *************/
340 #define USB_CNTRX_NBLK_MSK                    (0x1FU << 26)
341 #define USB_CNTRX_BLSIZE                      (0x1U << 31)
342 
343 
344 /*Set Channel/Endpoint to the USB Register */
345 #define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue)  (*(__IO uint32_t *)\
346                                                       (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue))
347 
348 /*Get Channel/Endpoint from the USB Register */
349 #define USB_DRD_GET_CHEP(USBx, bEpChNum)             (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum)))
350 
351 
352 /**
353   * @brief free buffer used from the application realizing it to the line
354   *         toggles bit SW_BUF in the double buffered endpoint register
355   * @param USBx USB device.
356   * @param   bEpChNum, bDir
357   * @retval None
358   */
359 #define USB_DRD_FREE_USER_BUFFER(USBx, bEpChNum, bDir) \
360   do { \
361     if ((bDir) == 0U) \
362     { \
363       /* OUT double buffered endpoint */ \
364       USB_DRD_TX_DTOG((USBx), (bEpChNum)); \
365     } \
366     else if ((bDir) == 1U) \
367     { \
368       /* IN double buffered endpoint */ \
369       USB_DRD_RX_DTOG((USBx), (bEpChNum)); \
370     } \
371   } while(0)
372 
373 
374 /**
375   * @brief Set the Setup bit in the corresponding channel, when a Setup
376      transaction is needed.
377   * @param USBx USB device.
378   * @param   bEpChNum
379   * @retval None
380   */
381 #define USB_DRD_CHEP_TX_SETUP(USBx, bEpChNum) \
382   do { \
383     uint32_t _wRegVal; \
384     \
385     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \
386     \
387     /* Set Setup bit */ \
388     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \
389   } while(0)
390 
391 
392 /**
393   * @brief  Clears bit ERR_RX in the Channel register
394   * @param  USBx USB peripheral instance register address.
395   * @param  bChNum Endpoint Number.
396   * @retval None
397   */
398 #define USB_DRD_CLEAR_CHEP_RX_ERR(USBx, bChNum) \
399   do { \
400     uint32_t _wRegVal; \
401     \
402     _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \
403     _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | \
404                (USB_CHEP_VTTX | USB_CHEP_ERRTX); \
405     \
406     USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \
407   } while(0) /* USB_DRD_CLEAR_CHEP_RX_ERR */
408 
409 
410 /**
411   * @brief  Clears bit ERR_TX in the Channel register
412   * @param  USBx USB peripheral instance register address.
413   * @param  bChNum Endpoint Number.
414   * @retval None
415   */
416 #define USB_DRD_CLEAR_CHEP_TX_ERR(USBx, bChNum) \
417   do { \
418     uint32_t _wRegVal; \
419     \
420     _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \
421     _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | \
422                (USB_CHEP_VTRX|USB_CHEP_ERRRX); \
423     \
424     USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \
425   } while(0) /* USB_DRD_CLEAR_CHEP_TX_ERR */
426 
427 
428 /**
429   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
430   * @param  USBx USB peripheral instance register address.
431   * @param  bEpChNum Endpoint Number.
432   * @param  wState new state
433   * @retval None
434   */
435 #define USB_DRD_SET_CHEP_TX_STATUS(USBx, bEpChNum, wState) \
436   do { \
437     uint32_t _wRegVal; \
438     \
439     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_TX_DTOGMASK; \
440     /* toggle first bit ? */ \
441     if ((USB_CHEP_TX_DTOG1 & (wState)) != 0U) \
442     { \
443       _wRegVal ^= USB_CHEP_TX_DTOG1; \
444     } \
445     /* toggle second bit ?  */ \
446     if ((USB_CHEP_TX_DTOG2 & (wState)) != 0U) \
447     { \
448       _wRegVal ^= USB_CHEP_TX_DTOG2; \
449     } \
450     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX| USB_CHEP_VTTX)); \
451   } while(0) /* USB_DRD_SET_CHEP_TX_STATUS */
452 
453 
454 /**
455   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
456   * @param  USBx USB peripheral instance register address.
457   * @param  bEpChNum Endpoint Number.
458   * @param  wState new state
459   * @retval None
460   */
461 #define USB_DRD_SET_CHEP_RX_STATUS(USBx, bEpChNum, wState) \
462   do { \
463     uint32_t _wRegVal; \
464     \
465     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_RX_DTOGMASK; \
466     /* toggle first bit ? */ \
467     if ((USB_CHEP_RX_DTOG1 & (wState)) != 0U) \
468     { \
469       _wRegVal ^= USB_CHEP_RX_DTOG1; \
470     } \
471     /* toggle second bit ? */ \
472     if ((USB_CHEP_RX_DTOG2 & (wState)) != 0U) \
473     { \
474       _wRegVal ^= USB_CHEP_RX_DTOG2; \
475     } \
476     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \
477   } while(0) /* USB_DRD_SET_CHEP_RX_STATUS */
478 
479 
480 /**
481   * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
482   *         /STAT_RX[1:0])
483   * @param  USBx USB peripheral instance register address.
484   * @param  bEpChNum Endpoint Number.
485   * @retval status
486   */
487 #define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) \
488   ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX)
489 
490 #define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) \
491   ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX)
492 
493 
494 /**
495   * @brief  set  EP_KIND bit.
496   * @param  USBx USB peripheral instance register address.
497   * @param  bEpChNum Endpoint Number.
498   * @retval None
499   */
500 #define USB_DRD_SET_CHEP_KIND(USBx, bEpChNum) \
501   do { \
502     uint32_t _wRegVal; \
503     \
504     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \
505     \
506     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); \
507   } while(0) /* USB_DRD_SET_CHEP_KIND */
508 
509 
510 /**
511   * @brief  clear EP_KIND bit.
512   * @param  USBx USB peripheral instance register address.
513   * @param  bEpChNum Endpoint Number.
514   * @retval None
515   */
516 #define USB_DRD_CLEAR_CHEP_KIND(USBx, bEpChNum) \
517   do { \
518     uint32_t _wRegVal; \
519     \
520     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_EP_KIND_MASK; \
521     \
522     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \
523   } while(0) /* USB_DRD_CLEAR_CHEP_KIND */
524 
525 
526 /**
527   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
528   * @param  USBx USB peripheral instance register address.
529   * @param  bEpChNum Endpoint Number.
530   * @retval None
531   */
532 #define USB_DRD_CLEAR_RX_CHEP_CTR(USBx, bEpChNum) \
533   do { \
534     uint32_t _wRegVal; \
535     \
536     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); \
537     \
538     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTTX)); \
539   } while(0) /* USB_CLEAR_RX_CHEP_CTR */
540 
541 #define USB_DRD_CLEAR_TX_CHEP_CTR(USBx, bEpChNum) \
542   do { \
543     uint32_t _wRegVal; \
544     \
545     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); \
546     \
547     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX)); \
548   } while(0) /* USB_CLEAR_TX_CHEP_CTR */
549 
550 
551 /**
552   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
553   * @param  USBx USB peripheral instance register address.
554   * @param  bEpChNum Endpoint Number.
555   * @retval None
556   */
557 #define USB_DRD_RX_DTOG(USBx, bEpChNum) \
558   do { \
559     uint32_t _wEPVal; \
560     \
561     _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \
562     \
563     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX)); \
564   } while(0) /* USB_DRD_RX_DTOG */
565 
566 #define USB_DRD_TX_DTOG(USBx, bEpChNum) \
567   do { \
568     uint32_t _wEPVal; \
569     \
570     _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \
571     \
572     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX)); \
573   } while(0) /* USB_TX_DTOG */
574 
575 
576 /**
577   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
578   * @param  USBx USB peripheral instance register address.
579   * @param  bEpChNum Endpoint Number.
580   * @retval None
581   */
582 #define USB_DRD_CLEAR_RX_DTOG(USBx, bEpChNum) \
583   do { \
584     uint32_t _wRegVal; \
585     \
586     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \
587     \
588     if ((_wRegVal & USB_CHEP_DTOG_RX) != 0U) \
589     { \
590       USB_DRD_RX_DTOG((USBx), (bEpChNum)); \
591     } \
592   } while(0) /* USB_DRD_CLEAR_RX_DTOG */
593 
594 #define USB_DRD_CLEAR_TX_DTOG(USBx, bEpChNum) \
595   do { \
596     uint32_t _wRegVal; \
597     \
598     _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \
599     \
600     if ((_wRegVal & USB_CHEP_DTOG_TX) != 0U) \
601     { \
602       USB_DRD_TX_DTOG((USBx), (bEpChNum)); \
603     } \
604   } while(0) /* USB_DRD_CLEAR_TX_DTOG */
605 
606 
607 /**
608   * @brief  Sets address in an endpoint register.
609   * @param  USBx USB peripheral instance register address.
610   * @param  bEpChNum Endpoint Number.
611   * @param  bAddr Address.
612   * @retval None
613   */
614 #define USB_DRD_SET_CHEP_ADDRESS(USBx, bEpChNum, bAddr) \
615   do { \
616     uint32_t _wRegVal; \
617     \
618     /*Read the USB->CHEPx into _wRegVal, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the EpAddress*/ \
619     _wRegVal = (USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK) | (bAddr); \
620     \
621     /*Set _wRegVal in USB->CHEPx and set Transmit/Receive Valid Transfer  (x=bEpChNum)*/ \
622     USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \
623   } while(0) /* USB_DRD_SET_CHEP_ADDRESS */
624 
625 
626 /* PMA API Buffer Descriptor Management ------------------------------------------------------------*/
627 /* Buffer Descriptor Table   TXBD0/RXBD0 --- > TXBD7/RXBD7  8 possible descriptor
628 * The buffer descriptor is located inside the packet buffer memory (USB_PMA_BUFF)
629 *          TXBD    [Reserve         |Countx| Address_Tx]
630 *          RXBD    [BLSIEZ|NUM_Block |CounRx| Address_Rx] */
631 
632 /* Set TX Buffer Descriptor Address Field */
633 #define USB_DRD_SET_CHEP_TX_ADDRESS(USBx, bEpChNum, wAddr) \
634   do { \
635     /* Reset old Address */ \
636     (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_ADDMSK; \
637     \
638     /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \
639     (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \
640   } while(0) /* USB_DRD_SET_CHEP_TX_ADDRESS */
641 
642 /* Set RX Buffer Descriptor Address Field */
643 #define USB_DRD_SET_CHEP_RX_ADDRESS(USBx, bEpChNum, wAddr) \
644   do { \
645     /* Reset old Address */ \
646     (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_RXBD_ADDMSK; \
647     \
648     /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \
649     (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \
650   } while(0) /* USB_SET_CHEP_RX_ADDRESS */
651 
652 
653 /**
654   * @brief  Sets counter of rx buffer with no. of blocks.
655   * @param  pdwReg Register pointer
656   * @param  wCount Counter.
657   * @param  wNBlocks no. of Blocks.
658   * @retval None
659   */
660 #define USB_DRD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
661   do { \
662     /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \
663     (wNBlocks) =((uint32_t)(wCount) >> 5U); \
664     if (((uint32_t)(wCount) % 32U) == 0U)  \
665     { \
666       (wNBlocks)--; \
667     } \
668     \
669     (pdwReg)|= (uint32_t)((((wNBlocks) << 26U)) | USB_CNTRX_BLSIZE); \
670   } while(0) /* USB_DRD_CALC_BLK32 */
671 
672 #define USB_DRD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
673   do { \
674     /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \
675     (wNBlocks) = (uint32_t)((uint32_t)(wCount) >> 1U); \
676     if (((wCount) & 0x1U) != 0U) \
677     { \
678       (wNBlocks)++; \
679     } \
680     (pdwReg) |= (uint32_t)((wNBlocks) << 26U); \
681   } while(0) /* USB_DRD_CALC_BLK2 */
682 
683 #define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \
684   do { \
685     uint32_t wNBlocks; \
686     \
687     (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \
688     \
689     if ((wCount) > 62U) \
690     { \
691       USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
692     } \
693     else \
694     { \
695       if ((wCount) == 0U) \
696       { \
697         (pdwReg) |= USB_CNTRX_BLSIZE; \
698       } \
699       else \
700       { \
701         USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
702       } \
703     } \
704   } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */
705 
706 
707 /**
708   * @brief  sets counter for the tx/rx buffer.
709   * @param  USBx USB peripheral instance register address.
710   * @param  bEpChNum Endpoint Number.
711   * @param  wCount Counter value.
712   * @retval None
713   */
714 #define USB_DRD_SET_CHEP_TX_CNT(USBx,bEpChNum, wCount) \
715   do { \
716     /* Reset old TX_Count value */ \
717     (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_COUNTMSK; \
718     \
719     /* Set the wCount in the dedicated EP_TXBuffer */ \
720     (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \
721   } while(0)
722 
723 #define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) \
724   USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount))
725 
726 #define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) \
727   USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount))
728 
729 /**
730   * @brief  gets counter of the tx buffer.
731   * @param  USBx USB peripheral instance register address.
732   * @param  bEpChNum Endpoint Number.
733   * @retval Counter value
734   */
735 #define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum)           (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >> 16U)
736 #define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum)           (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >> 16U)
737 
738 #define USB_DRD_GET_EP_TX_CNT                             USB_GET_CHEP_TX_CNT
739 #define USB_DRD_GET_CH_TX_CNT                             USB_GET_CHEP_TX_CNT
740 
741 #define USB_DRD_GET_EP_RX_CNT                             USB_DRD_GET_CHEP_RX_CNT
742 #define USB_DRD_GET_CH_RX_CNT                             USB_DRD_GET_CHEP_RX_CNT
743 /**
744   * @brief  Sets buffer 0/1 address in a double buffer endpoint.
745   * @param  USBx USB peripheral instance register address.
746   * @param  bEpChNum Endpoint Number.
747   * @param  wBuf0Addr buffer 0 address.
748   * @retval Counter value
749   */
750 #define USB_DRD_SET_CHEP_DBUF0_ADDR(USBx, bEpChNum, wBuf0Addr) \
751   USB_DRD_SET_CHEP_TX_ADDRESS((USBx), (bEpChNum), (wBuf0Addr))
752 
753 #define USB_DRD_SET_CHEP_DBUF1_ADDR(USBx, bEpChNum, wBuf1Addr) \
754   USB_DRD_SET_CHEP_RX_ADDRESS((USBx), (bEpChNum), (wBuf1Addr))
755 
756 
757 /**
758   * @brief  Sets addresses in a double buffer endpoint.
759   * @param  USBx USB peripheral instance register address.
760   * @param  bEpChNum Endpoint Number.
761   * @param  wBuf0Addr: buffer 0 address.
762   * @param  wBuf1Addr = buffer 1 address.
763   * @retval None
764   */
765 #define USB_DRD_SET_CHEP_DBUF_ADDR(USBx, bEpChNum, wBuf0Addr, wBuf1Addr) \
766   do { \
767     USB_DRD_SET_CHEP_DBUF0_ADDR((USBx), (bEpChNum), (wBuf0Addr)); \
768     USB_DRD_SET_CHEP_DBUF1_ADDR((USBx), (bEpChNum), (wBuf1Addr)); \
769   } while(0) /* USB_DRD_SET_CHEP_DBUF_ADDR */
770 
771 
772 /**
773   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
774   * @param  USBx USB peripheral instance register address.
775   * @param  bEpChNum Endpoint Number.
776   * @param  bDir endpoint dir  EP_DBUF_OUT = OUT
777   *         EP_DBUF_IN  = IN
778   * @param  wCount: Counter value
779   * @retval None
780   */
781 #define USB_DRD_SET_CHEP_DBUF0_CNT(USBx, bEpChNum, bDir, wCount) \
782   do { \
783     if ((bDir) == 0U) \
784     { \
785       /* OUT endpoint */ \
786       USB_DRD_SET_CHEP_RX_DBUF0_CNT((USBx), (bEpChNum), (wCount)); \
787     } \
788     else \
789     { \
790       if ((bDir) == 1U) \
791       { \
792         /* IN endpoint */ \
793         USB_DRD_SET_CHEP_TX_CNT((USBx), (bEpChNum), (wCount)); \
794       } \
795     } \
796   } while(0) /* USB_DRD_SET_CHEP_DBUF0_CNT */
797 
798 #define USB_DRD_SET_CHEP_DBUF1_CNT(USBx, bEpChNum, bDir, wCount) \
799   do { \
800     if ((bDir) == 0U) \
801     { \
802       /* OUT endpoint */ \
803       USB_DRD_SET_CHEP_RX_CNT((USBx), (bEpChNum), (wCount)); \
804     } \
805     else \
806     { \
807       if ((bDir) == 1U) \
808       { \
809         /* IN endpoint */ \
810         (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_TXBD_COUNTMSK; \
811         (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \
812       } \
813     } \
814   } while(0) /* USB_DRD_SET_CHEP_DBUF1_CNT */
815 
816 #define USB_DRD_SET_CHEP_DBUF_CNT(USBx, bEpChNum, bDir, wCount) \
817   do { \
818     USB_DRD_SET_CHEP_DBUF0_CNT((USBx), (bEpChNum), (bDir), (wCount)); \
819     USB_DRD_SET_CHEP_DBUF1_CNT((USBx), (bEpChNum), (bDir), (wCount)); \
820   } while(0) /* USB_DRD_SET_EPCH_DBUF_CNT  */
821 
822 /**
823   * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
824   * @param  USBx USB peripheral instance register address.
825   * @param  bEpChNum Endpoint Number.
826   * @retval None
827   */
828 #define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum)     (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum)))
829 #define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum)     (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum)))
830 
831 /**
832   * @}
833   */
834 
835 /* Exported macro ------------------------------------------------------------*/
836 /**
837   * @}
838   */
839 
840 /* Exported functions --------------------------------------------------------*/
841 /** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
842   * @{
843   */
844 
845 
846 HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg);
847 HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg);
848 HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx);
849 HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx);
850 HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode);
851 
852 HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx);
853 HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num);
854 
855 #if defined (HAL_PCD_MODULE_ENABLED)
856 HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep);
857 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep);
858 HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep);
859 HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep);
860 HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep);
861 HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep);
862 #endif /* defined (HAL_PCD_MODULE_ENABLED) */
863 
864 HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address);
865 HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx);
866 HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx);
867 HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx);
868 uint32_t          USB_ReadInterrupts(USB_DRD_TypeDef const *USBx);
869 
870 HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx);
871 HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg);
872 HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch);
873 HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch);
874 HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc);
875 
876 uint32_t          USB_GetHostSpeed(USB_DRD_TypeDef const *USBx);
877 uint32_t          USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx);
878 HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx);
879 HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state);
880 HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum,
881                               uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps);
882 
883 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx);
884 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx);
885 
886 void              USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf,
887                                uint16_t wPMABufAddr, uint16_t wNBytes);
888 
889 void              USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf,
890                               uint16_t wPMABufAddr, uint16_t wNBytes);
891 
892 /**
893   * @}
894   */
895 
896 /**
897   * @}
898   */
899 
900 /**
901   * @}
902   */
903 
904 /**
905   * @}
906   */
907 #endif /* defined (USB_DRD_FS) */
908 
909 #ifdef __cplusplus
910 }
911 #endif /* __cplusplus */
912 
913 
914 #endif /* STM32G0xx_LL_USB_H */
915