1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32G0xx_LL_TIM_H
21 #define __STM32G0xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g0xx.h"
29
30 /** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #if defined(COMP3)
120 #define TIM_POSITION_BRK_SOURCE \
121 ((Source == LL_TIM_BKIN_SOURCE_BKIN) ? 0U :\
122 (Source == LL_TIM_BKIN_SOURCE_BKCOMP1) ? 1U :\
123 (Source == LL_TIM_BKIN_SOURCE_BKCOMP2) ? 2U :3U)
124 #else
125 #define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL)
126 #endif /* COMP3 */
127
128 /* Generic bit definitions for TIMx_AF1 register */
129 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
130 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
131
132
133 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
134 #define DT_DELAY_1 ((uint8_t)0x7F)
135 #define DT_DELAY_2 ((uint8_t)0x3F)
136 #define DT_DELAY_3 ((uint8_t)0x1F)
137 #define DT_DELAY_4 ((uint8_t)0x1F)
138
139 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
140 #define DT_RANGE_1 ((uint8_t)0x00)
141 #define DT_RANGE_2 ((uint8_t)0x80)
142 #define DT_RANGE_3 ((uint8_t)0xC0)
143 #define DT_RANGE_4 ((uint8_t)0xE0)
144
145 /** Legacy definitions for compatibility purpose
146 @cond 0
147 */
148 /**
149 @endcond
150 */
151
152 #define OCREF_CLEAR_SELECT_Pos (16U)
153 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x00010000 */
154 /**
155 * @}
156 */
157
158 /* Private macros ------------------------------------------------------------*/
159 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
160 * @{
161 */
162 /** @brief Convert channel id into channel index.
163 * @param __CHANNEL__ This parameter can be one of the following values:
164 * @arg @ref LL_TIM_CHANNEL_CH1
165 * @arg @ref LL_TIM_CHANNEL_CH1N
166 * @arg @ref LL_TIM_CHANNEL_CH2
167 * @arg @ref LL_TIM_CHANNEL_CH2N
168 * @arg @ref LL_TIM_CHANNEL_CH3
169 * @arg @ref LL_TIM_CHANNEL_CH3N
170 * @arg @ref LL_TIM_CHANNEL_CH4
171 * @arg @ref LL_TIM_CHANNEL_CH5
172 * @arg @ref LL_TIM_CHANNEL_CH6
173 * @retval none
174 */
175 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
176 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
184
185 /** @brief Calculate the deadtime sampling period(in ps).
186 * @param __TIMCLK__ timer input clock frequency (in Hz).
187 * @param __CKD__ This parameter can be one of the following values:
188 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
191 * @retval none
192 */
193 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
194 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
195 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
196 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
197 /**
198 * @}
199 */
200
201
202 /* Exported types ------------------------------------------------------------*/
203 #if defined(USE_FULL_LL_DRIVER)
204 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
205 * @{
206 */
207
208 /**
209 * @brief TIM Time Base configuration structure definition.
210 */
211 typedef struct
212 {
213 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
214 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
215
216 This feature can be modified afterwards using unitary function
217 @ref LL_TIM_SetPrescaler().*/
218
219 uint32_t CounterMode; /*!< Specifies the counter mode.
220 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
221
222 This feature can be modified afterwards using unitary function
223 @ref LL_TIM_SetCounterMode().*/
224
225 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
226 Auto-Reload Register at the next update event.
227 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
228 Some timer instances may support 32 bits counters. In that case this parameter must
229 be a number between 0x0000 and 0xFFFFFFFF.
230
231 This feature can be modified afterwards using unitary function
232 @ref LL_TIM_SetAutoReload().*/
233
234 uint32_t ClockDivision; /*!< Specifies the clock division.
235 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
236
237 This feature can be modified afterwards using unitary function
238 @ref LL_TIM_SetClockDivision().*/
239
240 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
241 reaches zero, an update event is generated and counting restarts
242 from the RCR value (N).
243 This means in PWM mode that (N+1) corresponds to:
244 - the number of PWM periods in edge-aligned mode
245 - the number of half PWM period in center-aligned mode
246 GP timers: this parameter must be a number between Min_Data = 0x00 and
247 Max_Data = 0xFF.
248 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
249 Max_Data = 0xFFFF.
250
251 This feature can be modified afterwards using unitary function
252 @ref LL_TIM_SetRepetitionCounter().*/
253 } LL_TIM_InitTypeDef;
254
255 /**
256 * @brief TIM Output Compare configuration structure definition.
257 */
258 typedef struct
259 {
260 uint32_t OCMode; /*!< Specifies the output mode.
261 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
262
263 This feature can be modified afterwards using unitary function
264 @ref LL_TIM_OC_SetMode().*/
265
266 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
267 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
268
269 This feature can be modified afterwards using unitary functions
270 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
271
272 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
273 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
274
275 This feature can be modified afterwards using unitary functions
276 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
277
278 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
279 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
280
281 This feature can be modified afterwards using unitary function
282 LL_TIM_OC_SetCompareCHx (x=1..6).*/
283
284 uint32_t OCPolarity; /*!< Specifies the output polarity.
285 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
286
287 This feature can be modified afterwards using unitary function
288 @ref LL_TIM_OC_SetPolarity().*/
289
290 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
291 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
292
293 This feature can be modified afterwards using unitary function
294 @ref LL_TIM_OC_SetPolarity().*/
295
296
297 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
298 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
299
300 This feature can be modified afterwards using unitary function
301 @ref LL_TIM_OC_SetIdleState().*/
302
303 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
304 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
305
306 This feature can be modified afterwards using unitary function
307 @ref LL_TIM_OC_SetIdleState().*/
308 } LL_TIM_OC_InitTypeDef;
309
310 /**
311 * @brief TIM Input Capture configuration structure definition.
312 */
313
314 typedef struct
315 {
316
317 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
318 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
319
320 This feature can be modified afterwards using unitary function
321 @ref LL_TIM_IC_SetPolarity().*/
322
323 uint32_t ICActiveInput; /*!< Specifies the input.
324 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
325
326 This feature can be modified afterwards using unitary function
327 @ref LL_TIM_IC_SetActiveInput().*/
328
329 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
330 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
331
332 This feature can be modified afterwards using unitary function
333 @ref LL_TIM_IC_SetPrescaler().*/
334
335 uint32_t ICFilter; /*!< Specifies the input capture filter.
336 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
337
338 This feature can be modified afterwards using unitary function
339 @ref LL_TIM_IC_SetFilter().*/
340 } LL_TIM_IC_InitTypeDef;
341
342
343 /**
344 * @brief TIM Encoder interface configuration structure definition.
345 */
346 typedef struct
347 {
348 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
349 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
350
351 This feature can be modified afterwards using unitary function
352 @ref LL_TIM_SetEncoderMode().*/
353
354 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
355 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
356
357 This feature can be modified afterwards using unitary function
358 @ref LL_TIM_IC_SetPolarity().*/
359
360 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
361 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
362
363 This feature can be modified afterwards using unitary function
364 @ref LL_TIM_IC_SetActiveInput().*/
365
366 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
367 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
368
369 This feature can be modified afterwards using unitary function
370 @ref LL_TIM_IC_SetPrescaler().*/
371
372 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
373 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
374
375 This feature can be modified afterwards using unitary function
376 @ref LL_TIM_IC_SetFilter().*/
377
378 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
379 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
380
381 This feature can be modified afterwards using unitary function
382 @ref LL_TIM_IC_SetPolarity().*/
383
384 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
385 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
386
387 This feature can be modified afterwards using unitary function
388 @ref LL_TIM_IC_SetActiveInput().*/
389
390 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
391 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
392
393 This feature can be modified afterwards using unitary function
394 @ref LL_TIM_IC_SetPrescaler().*/
395
396 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
397 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
398
399 This feature can be modified afterwards using unitary function
400 @ref LL_TIM_IC_SetFilter().*/
401
402 } LL_TIM_ENCODER_InitTypeDef;
403
404 /**
405 * @brief TIM Hall sensor interface configuration structure definition.
406 */
407 typedef struct
408 {
409
410 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
411 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
412
413 This feature can be modified afterwards using unitary function
414 @ref LL_TIM_IC_SetPolarity().*/
415
416 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
417 Prescaler must be set to get a maximum counter period longer than the
418 time interval between 2 consecutive changes on the Hall inputs.
419 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
420
421 This feature can be modified afterwards using unitary function
422 @ref LL_TIM_IC_SetPrescaler().*/
423
424 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
425 This parameter can be a value of
426 @ref TIM_LL_EC_IC_FILTER.
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_IC_SetFilter().*/
430
431 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
432 A positive pulse (TRGO event) is generated with a programmable delay every time
433 a change occurs on the Hall inputs.
434 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
435
436 This feature can be modified afterwards using unitary function
437 @ref LL_TIM_OC_SetCompareCH2().*/
438 } LL_TIM_HALLSENSOR_InitTypeDef;
439
440 /**
441 * @brief BDTR (Break and Dead Time) structure definition
442 */
443 typedef struct
444 {
445 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
446 This parameter can be a value of @ref TIM_LL_EC_OSSR
447
448 This feature can be modified afterwards using unitary function
449 @ref LL_TIM_SetOffStates()
450
451 @note This bit-field cannot be modified as long as LOCK level 2 has been
452 programmed. */
453
454 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
455 This parameter can be a value of @ref TIM_LL_EC_OSSI
456
457 This feature can be modified afterwards using unitary function
458 @ref LL_TIM_SetOffStates()
459
460 @note This bit-field cannot be modified as long as LOCK level 2 has been
461 programmed. */
462
463 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
464 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
465
466 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
467 register has been written, their content is frozen until the next reset.*/
468
469 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
470 switching-on of the outputs.
471 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
472
473 This feature can be modified afterwards using unitary function
474 @ref LL_TIM_OC_SetDeadTime()
475
476 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
477 programmed. */
478
479 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
480 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
481
482 This feature can be modified afterwards using unitary functions
483 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
484
485 @note This bit-field can not be modified as long as LOCK level 1 has been
486 programmed. */
487
488 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
489 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
490
491 This feature can be modified afterwards using unitary function
492 @ref LL_TIM_ConfigBRK()
493
494 @note This bit-field can not be modified as long as LOCK level 1 has been
495 programmed. */
496
497 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
498 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
499
500 This feature can be modified afterwards using unitary function
501 @ref LL_TIM_ConfigBRK()
502
503 @note This bit-field can not be modified as long as LOCK level 1 has been
504 programmed. */
505
506 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
507 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
508
509 This feature can be modified afterwards using unitary functions
510 @ref LL_TIM_ConfigBRK()
511
512 @note Bidirectional break input is only supported by advanced timers instances.
513
514 @note This bit-field can not be modified as long as LOCK level 1 has been
515 programmed. */
516
517 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
518 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
519
520 This feature can be modified afterwards using unitary functions
521 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
522
523 @note This bit-field can not be modified as long as LOCK level 1 has been
524 programmed. */
525
526 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
527 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
528
529 This feature can be modified afterwards using unitary function
530 @ref LL_TIM_ConfigBRK2()
531
532 @note This bit-field can not be modified as long as LOCK level 1 has been
533 programmed. */
534
535 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
536 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
537
538 This feature can be modified afterwards using unitary function
539 @ref LL_TIM_ConfigBRK2()
540
541 @note This bit-field can not be modified as long as LOCK level 1 has been
542 programmed. */
543
544 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
545 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
546
547 This feature can be modified afterwards using unitary functions
548 @ref LL_TIM_ConfigBRK2()
549
550 @note Bidirectional break input is only supported by advanced timers instances.
551
552 @note This bit-field can not be modified as long as LOCK level 1 has been
553 programmed. */
554
555 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
556 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
557
558 This feature can be modified afterwards using unitary functions
559 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
560
561 @note This bit-field can not be modified as long as LOCK level 1 has been
562 programmed. */
563 } LL_TIM_BDTR_InitTypeDef;
564
565 /**
566 * @}
567 */
568 #endif /* USE_FULL_LL_DRIVER */
569
570 /* Exported constants --------------------------------------------------------*/
571 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
572 * @{
573 */
574
575 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
576 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
577 * @{
578 */
579 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
580 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
581 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
582 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
583 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
584 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
585 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
586 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
587 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
588 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
589 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
590 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
591 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
592 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
593 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
594 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
595 /**
596 * @}
597 */
598
599 #if defined(USE_FULL_LL_DRIVER)
600 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
601 * @{
602 */
603 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
604 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
605 /**
606 * @}
607 */
608
609 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
610 * @{
611 */
612 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
613 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
614 /**
615 * @}
616 */
617
618 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
619 * @{
620 */
621 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
622 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
623 /**
624 * @}
625 */
626 #endif /* USE_FULL_LL_DRIVER */
627
628 /** @defgroup TIM_LL_EC_IT IT Defines
629 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
630 * @{
631 */
632 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
633 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
634 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
635 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
636 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
637 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
638 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
639 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
640 /**
641 * @}
642 */
643
644 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
645 * @{
646 */
647 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
648 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
654 * @{
655 */
656 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
657 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
663 * @{
664 */
665 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
666 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
667 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
668 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
669 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
670 /**
671 * @}
672 */
673
674 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
675 * @{
676 */
677 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
678 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
679 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
680 /**
681 * @}
682 */
683
684 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
685 * @{
686 */
687 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
688 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
694 * @{
695 */
696 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
697 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
703 * @{
704 */
705 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
706 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
712 * @{
713 */
714 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
715 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
716 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
717 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
718 /**
719 * @}
720 */
721
722 /** @defgroup TIM_LL_EC_CHANNEL Channel
723 * @{
724 */
725 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
726 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
727 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
728 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
729 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
730 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
731 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
732 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
733 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
734 /**
735 * @}
736 */
737
738 #if defined(USE_FULL_LL_DRIVER)
739 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
740 * @{
741 */
742 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
743 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
744 /**
745 * @}
746 */
747 #endif /* USE_FULL_LL_DRIVER */
748
749 /** Legacy definitions for compatibility purpose
750 @cond 0
751 */
752 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
753 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
754 /**
755 @endcond
756 */
757
758 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
759 * @{
760 */
761 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
762 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
763 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
764 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
765 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
766 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
767 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
768 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
769 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
770 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
771 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
772 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
773 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
774 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
775 /**
776 * @}
777 */
778
779 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
780 * @{
781 */
782 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
783 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
784 /**
785 * @}
786 */
787
788 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
789 * @{
790 */
791 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
792 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
793 /**
794 * @}
795 */
796
797 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
798 * @{
799 */
800 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
801 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
802 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
803 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
804 /**
805 * @}
806 */
807
808 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
809 * @{
810 */
811 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
812 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
813 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
814 /**
815 * @}
816 */
817
818 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
819 * @{
820 */
821 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
822 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
823 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
824 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
825 /**
826 * @}
827 */
828
829 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
830 * @{
831 */
832 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
833 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
834 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
835 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
836 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
837 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
838 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
839 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
840 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
841 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
842 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
843 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
844 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
845 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
846 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
847 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
848 /**
849 * @}
850 */
851
852 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
853 * @{
854 */
855 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
856 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
857 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
858 /**
859 * @}
860 */
861
862 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
863 * @{
864 */
865 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
866 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
867 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
868 /**
869 * @}
870 */
871
872 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
873 * @{
874 */
875 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
876 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
877 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
878 /**
879 * @}
880 */
881
882 /** @defgroup TIM_LL_EC_TRGO Trigger Output
883 * @{
884 */
885 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
886 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
887 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
888 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
889 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
890 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
891 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
892 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
893 /**
894 * @}
895 */
896
897 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
898 * @{
899 */
900 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
901 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
902 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
903 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
909 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
910 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
911 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
912 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
913 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
914 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
915 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
916 /**
917 * @}
918 */
919
920 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
921 * @{
922 */
923 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
924 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
925 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
926 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
927 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
928 /**
929 * @}
930 */
931
932 /** @defgroup TIM_LL_EC_TS Trigger Selection
933 * @{
934 */
935 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
936 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
937 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
938 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
939 #if defined(USB_BASE)
940 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
941 #endif /* USB_BASE */
942 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
943 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
944 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
945 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
946 /**
947 * @}
948 */
949
950 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
951 * @{
952 */
953 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
954 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
955 /**
956 * @}
957 */
958
959 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
960 * @{
961 */
962 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
963 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
964 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
965 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
966 /**
967 * @}
968 */
969
970 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
971 * @{
972 */
973 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
974 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
975 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
976 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
977 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
978 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
979 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
980 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
981 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
982 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
983 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
984 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
985 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
986 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
987 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
988 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
989 /**
990 * @}
991 */
992
993 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
994 * @{
995 */
996 #define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
997 #if defined(COMP1) && defined(COMP2)
998 #define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
999 #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1000 #endif /* COMP1 && COMP2 */
1001 #if defined(COMP3)
1002 #define LL_TIM_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP3_OUT */
1003 #endif /* COMP3 */
1004 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
1005 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
1006 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
1007 #define LL_TIM_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1008 #define LL_TIM_ETRSOURCE_MCO TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to MCO */
1009 #define LL_TIM_ETRSOURCE_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MCO2 */
1010 /**
1011 * @}
1012 */
1013
1014 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1015 * @{
1016 */
1017 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1018 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1024 * @{
1025 */
1026 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1027 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1028 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1029 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1030 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1031 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1032 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1033 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1034 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1035 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1036 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1037 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1038 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1039 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1040 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1041 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1042 /**
1043 * @}
1044 */
1045
1046 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1047 * @{
1048 */
1049 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1050 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1051 /**
1052 * @}
1053 */
1054
1055 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1056 * @{
1057 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1059 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1060 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1061 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1062 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1063 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1064 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1065 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1066 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1067 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1068 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1069 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1070 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1071 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1072 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1073 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1074 /**
1075 * @}
1076 */
1077
1078 /** @defgroup TIM_LL_EC_OSSI OSSI
1079 * @{
1080 */
1081 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1082 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup TIM_LL_EC_OSSR OSSR
1088 * @{
1089 */
1090 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1091 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1092 /**
1093 * @}
1094 */
1095
1096 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1097 * @{
1098 */
1099 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1100 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1101 /**
1102 * @}
1103 */
1104
1105 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1106 * @{
1107 */
1108 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1109 #if defined(COMP1) && defined(COMP2)
1110 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1111 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1112 #endif /* COMP1 && COMP2 */
1113 #if defined(COMP3)
1114 #define LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E /*!< internal signal: COMP3 output */
1115 #endif /* COMP3 */
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1121 * @{
1122 */
1123 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1124 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1125 /**
1126 * @}
1127 */
1128
1129 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1130 * @{
1131 */
1132 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1133 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1134 /**
1135 * @}
1136 */
1137
1138 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1139 * @{
1140 */
1141 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1142 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1143 /**
1144 * @}
1145 */
1146
1147 /** Legacy definitions for compatibility purpose
1148 @cond 0
1149 */
1150 #define LL_TIM_ReArmBRK(_PARAM_)
1151 #define LL_TIM_ReArmBRK2(_PARAM_)
1152 /**
1153 @endcond
1154 */
1155
1156 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1157 * @{
1158 */
1159 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1160 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1161 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1162 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1163 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1164 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1165 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1166 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1167 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1168 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1169 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1170 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1171 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1172 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1173 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1174 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1175 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1176 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1177 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1178 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1179 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1180 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1181 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1182 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1183 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1184 /**
1185 * @}
1186 */
1187
1188 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1189 * @{
1190 */
1191 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1192 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1193 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1194 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1195 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1196 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1197 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1198 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1199 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1200 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1201 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1202 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1203 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1204 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1205 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1206 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1207 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1208 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1209 /**
1210 * @}
1211 */
1212
1213 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1214 * @{
1215 */
1216 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
1217 #if defined(COMP1)
1218 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
1219 #endif /* COMP1 */
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup TIM_LL_EC_TIM1_TI2_RMP TIM1 Timer Input Ch2 Remap
1225 * @{
1226 */
1227 #define LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U /*!< TIM1 input 2 is connected to GPIO */
1228 #if defined(COMP2)
1229 #define LL_TIM_TIM1_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM1 input 2 is connected to COMP2_OUT */
1230 #endif /* COMP2 */
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup TIM_LL_EC_TIM1_TI3_RMP TIM1 Timer Input Ch3 Remap
1236 * @{
1237 */
1238 #define LL_TIM_TIM1_TI3_RMP_GPIO 0x00000000U /*!< TIM1 input 3 is connected to GPIO */
1239 #if defined(COMP3)
1240 #define LL_TIM_TIM1_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM1 input 3 is connected to COMP3_OUT */
1241 #endif /* COMP3 */
1242 /**
1243 * @}
1244 */
1245
1246 #if defined(TIM2)
1247 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
1248 * @{
1249 */
1250 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
1251 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
1257 * @{
1258 */
1259 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
1260 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP2_OUT */
1261 /**
1262 * @}
1263 */
1264
1265 /** @defgroup TIM_LL_EC_TIM2_TI3_RMP TIM2 Timer Input Ch3 Remap
1266 * @{
1267 */
1268 #define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
1269 #if defined(COMP3)
1270 #define LL_TIM_TIM2_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP3_OUT */
1271 #endif /* COMP3 */
1272 /**
1273 * @}
1274 */
1275 #endif /* TIM2 */
1276
1277 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1278 * @{
1279 */
1280 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
1281 #if defined(COMP1)
1282 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
1283 #endif /* COMP1 */
1284 /**
1285 * @}
1286 */
1287
1288 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
1289 * @{
1290 */
1291 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
1292 #if defined(COMP2)
1293 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP2_OUT */
1294 #endif /* COMP2 */
1295 /**
1296 * @}
1297 */
1298
1299 /** @defgroup TIM_LL_EC_TIM3_TI3_RMP TIM3 Timer Input Ch3 Remap
1300 * @{
1301 */
1302 #define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
1303 #if defined(COMP3)
1304 #define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
1305 #endif /* COMP3 */
1306 /**
1307 * @}
1308 */
1309
1310 #if defined(TIM4)
1311 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 Timer Input Ch1 Remap
1312 * @{
1313 */
1314 #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
1315 #if defined(COMP1)
1316 #define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
1317 #endif /* COMP1 */
1318 /**
1319 * @}
1320 */
1321
1322 /** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 Timer Input Ch2 Remap
1323 * @{
1324 */
1325 #define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
1326 #if defined(COMP2)
1327 #define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP2_OUT */
1328 #endif /* COMP2 */
1329 /**
1330 * @}
1331 */
1332
1333 /** @defgroup TIM_LL_EC_TIM4_TI3_RMP TIM4 Timer Input Ch3 Remap
1334 * @{
1335 */
1336 #define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
1337 #if defined(COMP3)
1338 #define LL_TIM_TIM4_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP3_OUT */
1339 #endif /* COMP3 */
1340 /**
1341 * @}
1342 */
1343 #endif /* TIM4 */
1344
1345 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input Ch1 Remap
1346 * @{
1347 */
1348 #define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U /*!< TIM14 input 1 is connected to GPIO */
1349 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK TIM_TISEL_TI1SEL_0 /*!< TIM14 input 1 is connected to RTC clock */
1350 #define LL_TIM_TIM14_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM14 input 1 is connected to HSE/32 clock */
1351 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM14 input 1 is connected to MCO */
1352 #define LL_TIM_TIM14_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM14 input 1 is connected to MCO2 */
1353 /**
1354 * @}
1355 */
1356
1357 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1358 * @{
1359 */
1360 #if defined(TIM15)
1361 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
1362 #if defined(TIM2)
1363 #define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 input 1 */
1364 #endif /* TIM2 */
1365 #if defined(TIM3)
1366 #define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 input 1 */
1367 #endif /* TIM3 */
1368 #endif /* TIM15 */
1369 /**
1370 * @}
1371 */
1372
1373 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1374 * @{
1375 */
1376 #if defined(TIM15)
1377 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
1378 #if defined(TIM2)
1379 #define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to TIM2 input 2 */
1380 #endif /* TIM2 */
1381 #if defined(TIM3)
1382 #define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 2 is connected to TIM3 input 2 */
1383 #endif /* TIM3 */
1384 #endif /* TIM15 */
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1390 * @{
1391 */
1392 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1393 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to LSI */
1394 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to LSE */
1395 #define LL_TIM_TIM16_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to RTC_WAKEUP */
1396 #define LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to MCO2 */
1397 /**
1398 * @}
1399 */
1400
1401 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1402 * @{
1403 */
1404 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1405 #define LL_TIM_TIM17_TI1_RMP_HSI48 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to HSI48/256 */
1406 #define LL_TIM_TIM17_TI1_RMP_HSE_32 TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to HSE/32 clock */
1407 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to MCO */
1408 #define LL_TIM_TIM17_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to MCO2 */
1409 /**
1410 * @}
1411 */
1412
1413 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1414 * @{
1415 */
1416 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
1417 #if defined(COMP1) && defined(COMP2)
1418 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1419 #if defined(COMP3)
1420 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_OR1_OCREF_CLR_0 /*!< OCREF clear input is connected to COMP2_OUT */
1421 #define LL_TIM_OCREF_CLR_INT_COMP3 TIM1_OR1_OCREF_CLR_1 /*!< OCREF clear input is connected to COMP3_OUT */
1422 #else
1423 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_OR1_OCREF_CLR /*!< OCREF clear input is connected to COMP2_OUT */
1424 #endif /* COMP3 */
1425 #endif /* COMP1 & COMP2 */
1426 /**
1427 * @}
1428 */
1429
1430 /** Legacy definitions for compatibility purpose
1431 @cond 0
1432 */
1433 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1434 /**
1435 @endcond
1436 */
1437
1438 /**
1439 * @}
1440 */
1441
1442 /* Exported macro ------------------------------------------------------------*/
1443 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1444 * @{
1445 */
1446
1447 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1448 * @{
1449 */
1450 /**
1451 * @brief Write a value in TIM register.
1452 * @param __INSTANCE__ TIM Instance
1453 * @param __REG__ Register to be written
1454 * @param __VALUE__ Value to be written in the register
1455 * @retval None
1456 */
1457 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1458
1459 /**
1460 * @brief Read a value in TIM register.
1461 * @param __INSTANCE__ TIM Instance
1462 * @param __REG__ Register to be read
1463 * @retval Register value
1464 */
1465 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1466 /**
1467 * @}
1468 */
1469
1470 /**
1471 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1472 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1473 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1474 * to TIMx_CNT register bit 31)
1475 * @param __CNT__ Counter value
1476 * @retval UIF status bit
1477 */
1478 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1479 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1480
1481 /**
1482 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1483 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1484 * @param __TIMCLK__ timer input clock frequency (in Hz)
1485 * @param __CKD__ This parameter can be one of the following values:
1486 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1487 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1488 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1489 * @param __DT__ deadtime duration (in ns)
1490 * @retval DTG[0:7]
1491 */
1492 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1493 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1494 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1495 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1496 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1497 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1498 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1499 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1500 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1501 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1502 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1503 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1504 0U)
1505
1506 /**
1507 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1508 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1509 * @param __TIMCLK__ timer input clock frequency (in Hz)
1510 * @param __CNTCLK__ counter clock frequency (in Hz)
1511 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1512 */
1513 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1514 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1515
1516 /**
1517 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1518 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1519 * @param __TIMCLK__ timer input clock frequency (in Hz)
1520 * @param __PSC__ prescaler
1521 * @param __FREQ__ output signal frequency (in Hz)
1522 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1523 */
1524 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1525 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1526
1527 /**
1528 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1529 * active/inactive delay.
1530 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1531 * @param __TIMCLK__ timer input clock frequency (in Hz)
1532 * @param __PSC__ prescaler
1533 * @param __DELAY__ timer output compare active/inactive delay (in us)
1534 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1535 */
1536 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1537 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1538 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1539
1540 /**
1541 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1542 * (when the timer operates in one pulse mode).
1543 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1544 * @param __TIMCLK__ timer input clock frequency (in Hz)
1545 * @param __PSC__ prescaler
1546 * @param __DELAY__ timer output compare active/inactive delay (in us)
1547 * @param __PULSE__ pulse duration (in us)
1548 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1549 */
1550 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1551 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1552 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1553
1554 /**
1555 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1556 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1557 * @param __ICPSC__ This parameter can be one of the following values:
1558 * @arg @ref LL_TIM_ICPSC_DIV1
1559 * @arg @ref LL_TIM_ICPSC_DIV2
1560 * @arg @ref LL_TIM_ICPSC_DIV4
1561 * @arg @ref LL_TIM_ICPSC_DIV8
1562 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1563 */
1564 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1565 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1566
1567
1568 /**
1569 * @}
1570 */
1571
1572 /* Exported functions --------------------------------------------------------*/
1573 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1574 * @{
1575 */
1576
1577 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1578 * @{
1579 */
1580 /**
1581 * @brief Enable timer counter.
1582 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1583 * @param TIMx Timer instance
1584 * @retval None
1585 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1586 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1587 {
1588 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1589 }
1590
1591 /**
1592 * @brief Disable timer counter.
1593 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1594 * @param TIMx Timer instance
1595 * @retval None
1596 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1597 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1598 {
1599 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1600 }
1601
1602 /**
1603 * @brief Indicates whether the timer counter is enabled.
1604 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1605 * @param TIMx Timer instance
1606 * @retval State of bit (1 or 0).
1607 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1608 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1609 {
1610 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1611 }
1612
1613 /**
1614 * @brief Enable update event generation.
1615 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1616 * @param TIMx Timer instance
1617 * @retval None
1618 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1619 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1620 {
1621 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1622 }
1623
1624 /**
1625 * @brief Disable update event generation.
1626 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1627 * @param TIMx Timer instance
1628 * @retval None
1629 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1630 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1631 {
1632 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1633 }
1634
1635 /**
1636 * @brief Indicates whether update event generation is enabled.
1637 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1638 * @param TIMx Timer instance
1639 * @retval Inverted state of bit (0 or 1).
1640 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1641 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1642 {
1643 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1644 }
1645
1646 /**
1647 * @brief Set update event source
1648 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1649 * generate an update interrupt or DMA request if enabled:
1650 * - Counter overflow/underflow
1651 * - Setting the UG bit
1652 * - Update generation through the slave mode controller
1653 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1654 * overflow/underflow generates an update interrupt or DMA request if enabled.
1655 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1656 * @param TIMx Timer instance
1657 * @param UpdateSource This parameter can be one of the following values:
1658 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1659 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1660 * @retval None
1661 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1662 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1663 {
1664 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1665 }
1666
1667 /**
1668 * @brief Get actual event update source
1669 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1670 * @param TIMx Timer instance
1671 * @retval Returned value can be one of the following values:
1672 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1673 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1674 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1675 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1676 {
1677 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1678 }
1679
1680 /**
1681 * @brief Set one pulse mode (one shot v.s. repetitive).
1682 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1683 * @param TIMx Timer instance
1684 * @param OnePulseMode This parameter can be one of the following values:
1685 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1686 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1687 * @retval None
1688 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1689 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1690 {
1691 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1692 }
1693
1694 /**
1695 * @brief Get actual one pulse mode.
1696 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1697 * @param TIMx Timer instance
1698 * @retval Returned value can be one of the following values:
1699 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1700 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1701 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1702 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1703 {
1704 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1705 }
1706
1707 /**
1708 * @brief Set the timer counter counting mode.
1709 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1710 * check whether or not the counter mode selection feature is supported
1711 * by a timer instance.
1712 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1713 * requires a timer reset to avoid unexpected direction
1714 * due to DIR bit readonly in center aligned mode.
1715 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1716 * CR1 CMS LL_TIM_SetCounterMode
1717 * @param TIMx Timer instance
1718 * @param CounterMode This parameter can be one of the following values:
1719 * @arg @ref LL_TIM_COUNTERMODE_UP
1720 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1721 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1722 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1723 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1724 * @retval None
1725 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1726 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1727 {
1728 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1729 }
1730
1731 /**
1732 * @brief Get actual counter mode.
1733 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1734 * check whether or not the counter mode selection feature is supported
1735 * by a timer instance.
1736 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1737 * CR1 CMS LL_TIM_GetCounterMode
1738 * @param TIMx Timer instance
1739 * @retval Returned value can be one of the following values:
1740 * @arg @ref LL_TIM_COUNTERMODE_UP
1741 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1742 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1743 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1744 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1745 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1746 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1747 {
1748 uint32_t counter_mode;
1749
1750 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1751
1752 if (counter_mode == 0U)
1753 {
1754 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1755 }
1756
1757 return counter_mode;
1758 }
1759
1760 /**
1761 * @brief Enable auto-reload (ARR) preload.
1762 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1763 * @param TIMx Timer instance
1764 * @retval None
1765 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1766 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1767 {
1768 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1769 }
1770
1771 /**
1772 * @brief Disable auto-reload (ARR) preload.
1773 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1774 * @param TIMx Timer instance
1775 * @retval None
1776 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1777 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1778 {
1779 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1780 }
1781
1782 /**
1783 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1784 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1785 * @param TIMx Timer instance
1786 * @retval State of bit (1 or 0).
1787 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1788 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1789 {
1790 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1791 }
1792
1793 /**
1794 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1795 * (when supported) and the digital filters.
1796 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1797 * whether or not the clock division feature is supported by the timer
1798 * instance.
1799 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1800 * @param TIMx Timer instance
1801 * @param ClockDivision This parameter can be one of the following values:
1802 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1803 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1804 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1805 * @retval None
1806 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1807 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1808 {
1809 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1810 }
1811
1812 /**
1813 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1814 * generators (when supported) and the digital filters.
1815 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1816 * whether or not the clock division feature is supported by the timer
1817 * instance.
1818 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1819 * @param TIMx Timer instance
1820 * @retval Returned value can be one of the following values:
1821 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1822 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1823 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1824 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1825 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1826 {
1827 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1828 }
1829
1830 /**
1831 * @brief Set the counter value.
1832 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1833 * whether or not a timer instance supports a 32 bits counter.
1834 * @rmtoll CNT CNT LL_TIM_SetCounter
1835 * @param TIMx Timer instance
1836 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1837 * @retval None
1838 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1839 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1840 {
1841 WRITE_REG(TIMx->CNT, Counter);
1842 }
1843
1844 /**
1845 * @brief Get the counter value.
1846 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1847 * whether or not a timer instance supports a 32 bits counter.
1848 * @rmtoll CNT CNT LL_TIM_GetCounter
1849 * @param TIMx Timer instance
1850 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1851 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1852 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1853 {
1854 return (uint32_t)(READ_REG(TIMx->CNT));
1855 }
1856
1857 /**
1858 * @brief Get the current direction of the counter
1859 * @rmtoll CR1 DIR LL_TIM_GetDirection
1860 * @param TIMx Timer instance
1861 * @retval Returned value can be one of the following values:
1862 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1863 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1864 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1865 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1866 {
1867 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1868 }
1869
1870 /**
1871 * @brief Set the prescaler value.
1872 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1873 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1874 * prescaler ratio is taken into account at the next update event.
1875 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1876 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1877 * @param TIMx Timer instance
1878 * @param Prescaler between Min_Data=0 and Max_Data=65535
1879 * @retval None
1880 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1881 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1882 {
1883 WRITE_REG(TIMx->PSC, Prescaler);
1884 }
1885
1886 /**
1887 * @brief Get the prescaler value.
1888 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1889 * @param TIMx Timer instance
1890 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1891 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1892 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1893 {
1894 return (uint32_t)(READ_REG(TIMx->PSC));
1895 }
1896
1897 /**
1898 * @brief Set the auto-reload value.
1899 * @note The counter is blocked while the auto-reload value is null.
1900 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1901 * whether or not a timer instance supports a 32 bits counter.
1902 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1903 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1904 * @param TIMx Timer instance
1905 * @param AutoReload between Min_Data=0 and Max_Data=65535
1906 * @retval None
1907 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1908 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1909 {
1910 WRITE_REG(TIMx->ARR, AutoReload);
1911 }
1912
1913 /**
1914 * @brief Get the auto-reload value.
1915 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1916 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1917 * whether or not a timer instance supports a 32 bits counter.
1918 * @param TIMx Timer instance
1919 * @retval Auto-reload value
1920 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1921 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1922 {
1923 return (uint32_t)(READ_REG(TIMx->ARR));
1924 }
1925
1926 /**
1927 * @brief Set the repetition counter value.
1928 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1929 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1930 * whether or not a timer instance supports a repetition counter.
1931 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1932 * @param TIMx Timer instance
1933 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1934 * @retval None
1935 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1936 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1937 {
1938 WRITE_REG(TIMx->RCR, RepetitionCounter);
1939 }
1940
1941 /**
1942 * @brief Get the repetition counter value.
1943 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1944 * whether or not a timer instance supports a repetition counter.
1945 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1946 * @param TIMx Timer instance
1947 * @retval Repetition counter value
1948 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1949 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1950 {
1951 return (uint32_t)(READ_REG(TIMx->RCR));
1952 }
1953
1954 /**
1955 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1956 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1957 * in an atomic way.
1958 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1959 * @param TIMx Timer instance
1960 * @retval None
1961 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1962 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1963 {
1964 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1965 }
1966
1967 /**
1968 * @brief Disable update interrupt flag (UIF) remapping.
1969 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1970 * @param TIMx Timer instance
1971 * @retval None
1972 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1973 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1974 {
1975 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1976 }
1977
1978 /**
1979 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1980 * @param Counter Counter value
1981 * @retval State of bit (1 or 0).
1982 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1983 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1984 {
1985 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1986 }
1987
1988 /**
1989 * @}
1990 */
1991
1992 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1993 * @{
1994 */
1995 /**
1996 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1997 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1998 * they are updated only when a commutation event (COM) occurs.
1999 * @note Only on channels that have a complementary output.
2000 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2001 * whether or not a timer instance is able to generate a commutation event.
2002 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2003 * @param TIMx Timer instance
2004 * @retval None
2005 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2006 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2007 {
2008 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2009 }
2010
2011 /**
2012 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2013 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2014 * whether or not a timer instance is able to generate a commutation event.
2015 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2016 * @param TIMx Timer instance
2017 * @retval None
2018 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2019 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2020 {
2021 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2022 }
2023
2024 /**
2025 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
2026 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
2027 * @param TIMx Timer instance
2028 * @retval State of bit (1 or 0).
2029 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)2030 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
2031 {
2032 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
2033 }
2034
2035 /**
2036 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2037 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2038 * whether or not a timer instance is able to generate a commutation event.
2039 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2040 * @param TIMx Timer instance
2041 * @param CCUpdateSource This parameter can be one of the following values:
2042 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2043 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2044 * @retval None
2045 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2046 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2047 {
2048 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2049 }
2050
2051 /**
2052 * @brief Set the trigger of the capture/compare DMA request.
2053 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2054 * @param TIMx Timer instance
2055 * @param DMAReqTrigger This parameter can be one of the following values:
2056 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2057 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2058 * @retval None
2059 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2060 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2061 {
2062 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2063 }
2064
2065 /**
2066 * @brief Get actual trigger of the capture/compare DMA request.
2067 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2068 * @param TIMx Timer instance
2069 * @retval Returned value can be one of the following values:
2070 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2071 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2072 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2073 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2074 {
2075 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2076 }
2077
2078 /**
2079 * @brief Set the lock level to freeze the
2080 * configuration of several capture/compare parameters.
2081 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2082 * the lock mechanism is supported by a timer instance.
2083 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2084 * @param TIMx Timer instance
2085 * @param LockLevel This parameter can be one of the following values:
2086 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2087 * @arg @ref LL_TIM_LOCKLEVEL_1
2088 * @arg @ref LL_TIM_LOCKLEVEL_2
2089 * @arg @ref LL_TIM_LOCKLEVEL_3
2090 * @retval None
2091 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2092 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2093 {
2094 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2095 }
2096
2097 /**
2098 * @brief Enable capture/compare channels.
2099 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2100 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2101 * CCER CC2E LL_TIM_CC_EnableChannel\n
2102 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2103 * CCER CC3E LL_TIM_CC_EnableChannel\n
2104 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2105 * CCER CC4E LL_TIM_CC_EnableChannel\n
2106 * CCER CC5E LL_TIM_CC_EnableChannel\n
2107 * CCER CC6E LL_TIM_CC_EnableChannel
2108 * @param TIMx Timer instance
2109 * @param Channels This parameter can be a combination of the following values:
2110 * @arg @ref LL_TIM_CHANNEL_CH1
2111 * @arg @ref LL_TIM_CHANNEL_CH1N
2112 * @arg @ref LL_TIM_CHANNEL_CH2
2113 * @arg @ref LL_TIM_CHANNEL_CH2N
2114 * @arg @ref LL_TIM_CHANNEL_CH3
2115 * @arg @ref LL_TIM_CHANNEL_CH3N
2116 * @arg @ref LL_TIM_CHANNEL_CH4
2117 * @arg @ref LL_TIM_CHANNEL_CH5
2118 * @arg @ref LL_TIM_CHANNEL_CH6
2119 * @retval None
2120 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2121 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2122 {
2123 SET_BIT(TIMx->CCER, Channels);
2124 }
2125
2126 /**
2127 * @brief Disable capture/compare channels.
2128 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2129 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2130 * CCER CC2E LL_TIM_CC_DisableChannel\n
2131 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2132 * CCER CC3E LL_TIM_CC_DisableChannel\n
2133 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2134 * CCER CC4E LL_TIM_CC_DisableChannel\n
2135 * CCER CC5E LL_TIM_CC_DisableChannel\n
2136 * CCER CC6E LL_TIM_CC_DisableChannel
2137 * @param TIMx Timer instance
2138 * @param Channels This parameter can be a combination of the following values:
2139 * @arg @ref LL_TIM_CHANNEL_CH1
2140 * @arg @ref LL_TIM_CHANNEL_CH1N
2141 * @arg @ref LL_TIM_CHANNEL_CH2
2142 * @arg @ref LL_TIM_CHANNEL_CH2N
2143 * @arg @ref LL_TIM_CHANNEL_CH3
2144 * @arg @ref LL_TIM_CHANNEL_CH3N
2145 * @arg @ref LL_TIM_CHANNEL_CH4
2146 * @arg @ref LL_TIM_CHANNEL_CH5
2147 * @arg @ref LL_TIM_CHANNEL_CH6
2148 * @retval None
2149 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2150 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2151 {
2152 CLEAR_BIT(TIMx->CCER, Channels);
2153 }
2154
2155 /**
2156 * @brief Indicate whether channel(s) is(are) enabled.
2157 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2158 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2159 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2160 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2161 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2162 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2163 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2164 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2165 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2166 * @param TIMx Timer instance
2167 * @param Channels This parameter can be a combination of the following values:
2168 * @arg @ref LL_TIM_CHANNEL_CH1
2169 * @arg @ref LL_TIM_CHANNEL_CH1N
2170 * @arg @ref LL_TIM_CHANNEL_CH2
2171 * @arg @ref LL_TIM_CHANNEL_CH2N
2172 * @arg @ref LL_TIM_CHANNEL_CH3
2173 * @arg @ref LL_TIM_CHANNEL_CH3N
2174 * @arg @ref LL_TIM_CHANNEL_CH4
2175 * @arg @ref LL_TIM_CHANNEL_CH5
2176 * @arg @ref LL_TIM_CHANNEL_CH6
2177 * @retval State of bit (1 or 0).
2178 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2179 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2180 {
2181 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2182 }
2183
2184 /**
2185 * @}
2186 */
2187
2188 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2189 * @{
2190 */
2191 /**
2192 * @brief Configure an output channel.
2193 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2194 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2195 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2196 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2197 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2198 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2199 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2200 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2201 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2202 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2203 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2204 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2205 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2206 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2207 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2208 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2209 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2210 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2211 * @param TIMx Timer instance
2212 * @param Channel This parameter can be one of the following values:
2213 * @arg @ref LL_TIM_CHANNEL_CH1
2214 * @arg @ref LL_TIM_CHANNEL_CH2
2215 * @arg @ref LL_TIM_CHANNEL_CH3
2216 * @arg @ref LL_TIM_CHANNEL_CH4
2217 * @arg @ref LL_TIM_CHANNEL_CH5
2218 * @arg @ref LL_TIM_CHANNEL_CH6
2219 * @param Configuration This parameter must be a combination of all the following values:
2220 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2221 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2222 * @retval None
2223 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2224 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2225 {
2226 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2227 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2228 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2229 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2230 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2231 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2232 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2233 }
2234
2235 /**
2236 * @brief Define the behavior of the output reference signal OCxREF from which
2237 * OCx and OCxN (when relevant) are derived.
2238 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2239 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2240 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2241 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2242 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2243 * CCMR3 OC6M LL_TIM_OC_SetMode
2244 * @param TIMx Timer instance
2245 * @param Channel This parameter can be one of the following values:
2246 * @arg @ref LL_TIM_CHANNEL_CH1
2247 * @arg @ref LL_TIM_CHANNEL_CH2
2248 * @arg @ref LL_TIM_CHANNEL_CH3
2249 * @arg @ref LL_TIM_CHANNEL_CH4
2250 * @arg @ref LL_TIM_CHANNEL_CH5
2251 * @arg @ref LL_TIM_CHANNEL_CH6
2252 * @param Mode This parameter can be one of the following values:
2253 * @arg @ref LL_TIM_OCMODE_FROZEN
2254 * @arg @ref LL_TIM_OCMODE_ACTIVE
2255 * @arg @ref LL_TIM_OCMODE_INACTIVE
2256 * @arg @ref LL_TIM_OCMODE_TOGGLE
2257 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2258 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2259 * @arg @ref LL_TIM_OCMODE_PWM1
2260 * @arg @ref LL_TIM_OCMODE_PWM2
2261 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2262 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2263 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2264 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2265 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2266 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2267 * @retval None
2268 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2269 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2270 {
2271 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2272 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2273 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2274 }
2275
2276 /**
2277 * @brief Get the output compare mode of an output channel.
2278 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2279 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2280 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2281 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2282 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2283 * CCMR3 OC6M LL_TIM_OC_GetMode
2284 * @param TIMx Timer instance
2285 * @param Channel This parameter can be one of the following values:
2286 * @arg @ref LL_TIM_CHANNEL_CH1
2287 * @arg @ref LL_TIM_CHANNEL_CH2
2288 * @arg @ref LL_TIM_CHANNEL_CH3
2289 * @arg @ref LL_TIM_CHANNEL_CH4
2290 * @arg @ref LL_TIM_CHANNEL_CH5
2291 * @arg @ref LL_TIM_CHANNEL_CH6
2292 * @retval Returned value can be one of the following values:
2293 * @arg @ref LL_TIM_OCMODE_FROZEN
2294 * @arg @ref LL_TIM_OCMODE_ACTIVE
2295 * @arg @ref LL_TIM_OCMODE_INACTIVE
2296 * @arg @ref LL_TIM_OCMODE_TOGGLE
2297 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2298 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2299 * @arg @ref LL_TIM_OCMODE_PWM1
2300 * @arg @ref LL_TIM_OCMODE_PWM2
2301 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2302 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2303 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2304 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2305 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2306 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2307 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2308 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2309 {
2310 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2311 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2312 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2313 }
2314
2315 /**
2316 * @brief Set the polarity of an output channel.
2317 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2318 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2319 * CCER CC2P LL_TIM_OC_SetPolarity\n
2320 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2321 * CCER CC3P LL_TIM_OC_SetPolarity\n
2322 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2323 * CCER CC4P LL_TIM_OC_SetPolarity\n
2324 * CCER CC5P LL_TIM_OC_SetPolarity\n
2325 * CCER CC6P LL_TIM_OC_SetPolarity
2326 * @param TIMx Timer instance
2327 * @param Channel This parameter can be one of the following values:
2328 * @arg @ref LL_TIM_CHANNEL_CH1
2329 * @arg @ref LL_TIM_CHANNEL_CH1N
2330 * @arg @ref LL_TIM_CHANNEL_CH2
2331 * @arg @ref LL_TIM_CHANNEL_CH2N
2332 * @arg @ref LL_TIM_CHANNEL_CH3
2333 * @arg @ref LL_TIM_CHANNEL_CH3N
2334 * @arg @ref LL_TIM_CHANNEL_CH4
2335 * @arg @ref LL_TIM_CHANNEL_CH5
2336 * @arg @ref LL_TIM_CHANNEL_CH6
2337 * @param Polarity This parameter can be one of the following values:
2338 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2339 * @arg @ref LL_TIM_OCPOLARITY_LOW
2340 * @retval None
2341 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2342 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2343 {
2344 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2345 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2346 }
2347
2348 /**
2349 * @brief Get the polarity of an output channel.
2350 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2351 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2352 * CCER CC2P LL_TIM_OC_GetPolarity\n
2353 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2354 * CCER CC3P LL_TIM_OC_GetPolarity\n
2355 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2356 * CCER CC4P LL_TIM_OC_GetPolarity\n
2357 * CCER CC5P LL_TIM_OC_GetPolarity\n
2358 * CCER CC6P LL_TIM_OC_GetPolarity
2359 * @param TIMx Timer instance
2360 * @param Channel This parameter can be one of the following values:
2361 * @arg @ref LL_TIM_CHANNEL_CH1
2362 * @arg @ref LL_TIM_CHANNEL_CH1N
2363 * @arg @ref LL_TIM_CHANNEL_CH2
2364 * @arg @ref LL_TIM_CHANNEL_CH2N
2365 * @arg @ref LL_TIM_CHANNEL_CH3
2366 * @arg @ref LL_TIM_CHANNEL_CH3N
2367 * @arg @ref LL_TIM_CHANNEL_CH4
2368 * @arg @ref LL_TIM_CHANNEL_CH5
2369 * @arg @ref LL_TIM_CHANNEL_CH6
2370 * @retval Returned value can be one of the following values:
2371 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2372 * @arg @ref LL_TIM_OCPOLARITY_LOW
2373 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2374 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2375 {
2376 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2377 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2378 }
2379
2380 /**
2381 * @brief Set the IDLE state of an output channel
2382 * @note This function is significant only for the timer instances
2383 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2384 * can be used to check whether or not a timer instance provides
2385 * a break input.
2386 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2387 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2388 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2389 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2390 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2391 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2392 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2393 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2394 * CR2 OIS6 LL_TIM_OC_SetIdleState
2395 * @param TIMx Timer instance
2396 * @param Channel This parameter can be one of the following values:
2397 * @arg @ref LL_TIM_CHANNEL_CH1
2398 * @arg @ref LL_TIM_CHANNEL_CH1N
2399 * @arg @ref LL_TIM_CHANNEL_CH2
2400 * @arg @ref LL_TIM_CHANNEL_CH2N
2401 * @arg @ref LL_TIM_CHANNEL_CH3
2402 * @arg @ref LL_TIM_CHANNEL_CH3N
2403 * @arg @ref LL_TIM_CHANNEL_CH4
2404 * @arg @ref LL_TIM_CHANNEL_CH5
2405 * @arg @ref LL_TIM_CHANNEL_CH6
2406 * @param IdleState This parameter can be one of the following values:
2407 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2408 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2409 * @retval None
2410 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2411 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2412 {
2413 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2414 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2415 }
2416
2417 /**
2418 * @brief Get the IDLE state of an output channel
2419 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2420 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2421 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2422 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2423 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2424 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2425 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2426 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2427 * CR2 OIS6 LL_TIM_OC_GetIdleState
2428 * @param TIMx Timer instance
2429 * @param Channel This parameter can be one of the following values:
2430 * @arg @ref LL_TIM_CHANNEL_CH1
2431 * @arg @ref LL_TIM_CHANNEL_CH1N
2432 * @arg @ref LL_TIM_CHANNEL_CH2
2433 * @arg @ref LL_TIM_CHANNEL_CH2N
2434 * @arg @ref LL_TIM_CHANNEL_CH3
2435 * @arg @ref LL_TIM_CHANNEL_CH3N
2436 * @arg @ref LL_TIM_CHANNEL_CH4
2437 * @arg @ref LL_TIM_CHANNEL_CH5
2438 * @arg @ref LL_TIM_CHANNEL_CH6
2439 * @retval Returned value can be one of the following values:
2440 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2441 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2442 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2443 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2444 {
2445 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2446 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2447 }
2448
2449 /**
2450 * @brief Enable fast mode for the output channel.
2451 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2452 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2453 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2454 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2455 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2456 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2457 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2458 * @param TIMx Timer instance
2459 * @param Channel This parameter can be one of the following values:
2460 * @arg @ref LL_TIM_CHANNEL_CH1
2461 * @arg @ref LL_TIM_CHANNEL_CH2
2462 * @arg @ref LL_TIM_CHANNEL_CH3
2463 * @arg @ref LL_TIM_CHANNEL_CH4
2464 * @arg @ref LL_TIM_CHANNEL_CH5
2465 * @arg @ref LL_TIM_CHANNEL_CH6
2466 * @retval None
2467 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2468 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2469 {
2470 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2471 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2472 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2473
2474 }
2475
2476 /**
2477 * @brief Disable fast mode for the output channel.
2478 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2479 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2480 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2481 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2482 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2483 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2484 * @param TIMx Timer instance
2485 * @param Channel This parameter can be one of the following values:
2486 * @arg @ref LL_TIM_CHANNEL_CH1
2487 * @arg @ref LL_TIM_CHANNEL_CH2
2488 * @arg @ref LL_TIM_CHANNEL_CH3
2489 * @arg @ref LL_TIM_CHANNEL_CH4
2490 * @arg @ref LL_TIM_CHANNEL_CH5
2491 * @arg @ref LL_TIM_CHANNEL_CH6
2492 * @retval None
2493 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2494 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2495 {
2496 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2497 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2498 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2499
2500 }
2501
2502 /**
2503 * @brief Indicates whether fast mode is enabled for the output channel.
2504 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2505 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2506 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2507 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2508 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2509 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2510 * @param TIMx Timer instance
2511 * @param Channel This parameter can be one of the following values:
2512 * @arg @ref LL_TIM_CHANNEL_CH1
2513 * @arg @ref LL_TIM_CHANNEL_CH2
2514 * @arg @ref LL_TIM_CHANNEL_CH3
2515 * @arg @ref LL_TIM_CHANNEL_CH4
2516 * @arg @ref LL_TIM_CHANNEL_CH5
2517 * @arg @ref LL_TIM_CHANNEL_CH6
2518 * @retval State of bit (1 or 0).
2519 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2520 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2521 {
2522 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2523 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2524 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2525 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2526 }
2527
2528 /**
2529 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2530 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2531 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2532 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2533 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2534 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2535 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2536 * @param TIMx Timer instance
2537 * @param Channel This parameter can be one of the following values:
2538 * @arg @ref LL_TIM_CHANNEL_CH1
2539 * @arg @ref LL_TIM_CHANNEL_CH2
2540 * @arg @ref LL_TIM_CHANNEL_CH3
2541 * @arg @ref LL_TIM_CHANNEL_CH4
2542 * @arg @ref LL_TIM_CHANNEL_CH5
2543 * @arg @ref LL_TIM_CHANNEL_CH6
2544 * @retval None
2545 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2546 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2547 {
2548 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2549 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2550 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2551 }
2552
2553 /**
2554 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2555 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2556 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2557 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2558 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2559 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2560 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2561 * @param TIMx Timer instance
2562 * @param Channel This parameter can be one of the following values:
2563 * @arg @ref LL_TIM_CHANNEL_CH1
2564 * @arg @ref LL_TIM_CHANNEL_CH2
2565 * @arg @ref LL_TIM_CHANNEL_CH3
2566 * @arg @ref LL_TIM_CHANNEL_CH4
2567 * @arg @ref LL_TIM_CHANNEL_CH5
2568 * @arg @ref LL_TIM_CHANNEL_CH6
2569 * @retval None
2570 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2571 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2572 {
2573 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2574 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2575 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2576 }
2577
2578 /**
2579 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2580 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2581 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2582 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2583 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2584 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2585 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2586 * @param TIMx Timer instance
2587 * @param Channel This parameter can be one of the following values:
2588 * @arg @ref LL_TIM_CHANNEL_CH1
2589 * @arg @ref LL_TIM_CHANNEL_CH2
2590 * @arg @ref LL_TIM_CHANNEL_CH3
2591 * @arg @ref LL_TIM_CHANNEL_CH4
2592 * @arg @ref LL_TIM_CHANNEL_CH5
2593 * @arg @ref LL_TIM_CHANNEL_CH6
2594 * @retval State of bit (1 or 0).
2595 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2596 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2597 {
2598 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2599 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2600 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2601 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2602 }
2603
2604 /**
2605 * @brief Enable clearing the output channel on an external event.
2606 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2607 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2608 * or not a timer instance can clear the OCxREF signal on an external event.
2609 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2610 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2611 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2612 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2613 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2614 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2615 * @param TIMx Timer instance
2616 * @param Channel This parameter can be one of the following values:
2617 * @arg @ref LL_TIM_CHANNEL_CH1
2618 * @arg @ref LL_TIM_CHANNEL_CH2
2619 * @arg @ref LL_TIM_CHANNEL_CH3
2620 * @arg @ref LL_TIM_CHANNEL_CH4
2621 * @arg @ref LL_TIM_CHANNEL_CH5
2622 * @arg @ref LL_TIM_CHANNEL_CH6
2623 * @retval None
2624 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2625 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2626 {
2627 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2628 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2629 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2630 }
2631
2632 /**
2633 * @brief Disable clearing the output channel on an external event.
2634 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2635 * or not a timer instance can clear the OCxREF signal on an external event.
2636 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2637 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2638 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2639 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2640 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2641 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2642 * @param TIMx Timer instance
2643 * @param Channel This parameter can be one of the following values:
2644 * @arg @ref LL_TIM_CHANNEL_CH1
2645 * @arg @ref LL_TIM_CHANNEL_CH2
2646 * @arg @ref LL_TIM_CHANNEL_CH3
2647 * @arg @ref LL_TIM_CHANNEL_CH4
2648 * @arg @ref LL_TIM_CHANNEL_CH5
2649 * @arg @ref LL_TIM_CHANNEL_CH6
2650 * @retval None
2651 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2652 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2653 {
2654 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2655 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2656 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2657 }
2658
2659 /**
2660 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2661 * @note This function enables clearing the output channel on an external event.
2662 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2663 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2664 * or not a timer instance can clear the OCxREF signal on an external event.
2665 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2666 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2667 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2668 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2669 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2670 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2671 * @param TIMx Timer instance
2672 * @param Channel This parameter can be one of the following values:
2673 * @arg @ref LL_TIM_CHANNEL_CH1
2674 * @arg @ref LL_TIM_CHANNEL_CH2
2675 * @arg @ref LL_TIM_CHANNEL_CH3
2676 * @arg @ref LL_TIM_CHANNEL_CH4
2677 * @arg @ref LL_TIM_CHANNEL_CH5
2678 * @arg @ref LL_TIM_CHANNEL_CH6
2679 * @retval State of bit (1 or 0).
2680 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2681 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2682 {
2683 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2684 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2685 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2686 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2687 }
2688
2689 /**
2690 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2691 * the Ocx and OCxN signals).
2692 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2693 * dead-time insertion feature is supported by a timer instance.
2694 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2695 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2696 * @param TIMx Timer instance
2697 * @param DeadTime between Min_Data=0 and Max_Data=255
2698 * @retval None
2699 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2700 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2701 {
2702 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2703 }
2704
2705 /**
2706 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2707 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2708 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2709 * whether or not a timer instance supports a 32 bits counter.
2710 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2711 * output channel 1 is supported by a timer instance.
2712 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2713 * @param TIMx Timer instance
2714 * @param CompareValue between Min_Data=0 and Max_Data=65535
2715 * @retval None
2716 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2717 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2718 {
2719 WRITE_REG(TIMx->CCR1, CompareValue);
2720 }
2721
2722 /**
2723 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2724 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2725 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2726 * whether or not a timer instance supports a 32 bits counter.
2727 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2728 * output channel 2 is supported by a timer instance.
2729 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2730 * @param TIMx Timer instance
2731 * @param CompareValue between Min_Data=0 and Max_Data=65535
2732 * @retval None
2733 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2734 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2735 {
2736 WRITE_REG(TIMx->CCR2, CompareValue);
2737 }
2738
2739 /**
2740 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2741 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2742 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2743 * whether or not a timer instance supports a 32 bits counter.
2744 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2745 * output channel is supported by a timer instance.
2746 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2747 * @param TIMx Timer instance
2748 * @param CompareValue between Min_Data=0 and Max_Data=65535
2749 * @retval None
2750 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2751 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2752 {
2753 WRITE_REG(TIMx->CCR3, CompareValue);
2754 }
2755
2756 /**
2757 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2758 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2759 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2760 * whether or not a timer instance supports a 32 bits counter.
2761 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2762 * output channel 4 is supported by a timer instance.
2763 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2764 * @param TIMx Timer instance
2765 * @param CompareValue between Min_Data=0 and Max_Data=65535
2766 * @retval None
2767 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2768 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2769 {
2770 WRITE_REG(TIMx->CCR4, CompareValue);
2771 }
2772
2773 /**
2774 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2775 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2776 * output channel 5 is supported by a timer instance.
2777 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2778 * @param TIMx Timer instance
2779 * @param CompareValue between Min_Data=0 and Max_Data=65535
2780 * @retval None
2781 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2782 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2783 {
2784 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2785 }
2786
2787 /**
2788 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2789 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2790 * output channel 6 is supported by a timer instance.
2791 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2792 * @param TIMx Timer instance
2793 * @param CompareValue between Min_Data=0 and Max_Data=65535
2794 * @retval None
2795 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2796 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2797 {
2798 WRITE_REG(TIMx->CCR6, CompareValue);
2799 }
2800
2801 /**
2802 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2803 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2804 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2805 * whether or not a timer instance supports a 32 bits counter.
2806 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2807 * output channel 1 is supported by a timer instance.
2808 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2809 * @param TIMx Timer instance
2810 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2811 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2812 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2813 {
2814 return (uint32_t)(READ_REG(TIMx->CCR1));
2815 }
2816
2817 /**
2818 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2819 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2820 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2821 * whether or not a timer instance supports a 32 bits counter.
2822 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2823 * output channel 2 is supported by a timer instance.
2824 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2825 * @param TIMx Timer instance
2826 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2827 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2828 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2829 {
2830 return (uint32_t)(READ_REG(TIMx->CCR2));
2831 }
2832
2833 /**
2834 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2835 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2836 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2837 * whether or not a timer instance supports a 32 bits counter.
2838 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2839 * output channel 3 is supported by a timer instance.
2840 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2841 * @param TIMx Timer instance
2842 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2843 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2844 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2845 {
2846 return (uint32_t)(READ_REG(TIMx->CCR3));
2847 }
2848
2849 /**
2850 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2851 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2852 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2853 * whether or not a timer instance supports a 32 bits counter.
2854 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2855 * output channel 4 is supported by a timer instance.
2856 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2857 * @param TIMx Timer instance
2858 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2859 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2860 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2861 {
2862 return (uint32_t)(READ_REG(TIMx->CCR4));
2863 }
2864
2865 /**
2866 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2867 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2868 * output channel 5 is supported by a timer instance.
2869 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2870 * @param TIMx Timer instance
2871 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2872 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2873 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2874 {
2875 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2876 }
2877
2878 /**
2879 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2880 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2881 * output channel 6 is supported by a timer instance.
2882 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2883 * @param TIMx Timer instance
2884 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2885 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2886 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2887 {
2888 return (uint32_t)(READ_REG(TIMx->CCR6));
2889 }
2890
2891 /**
2892 * @brief Select on which reference signal the OC5REF is combined to.
2893 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2894 * whether or not a timer instance supports the combined 3-phase PWM mode.
2895 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2896 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2897 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2898 * @param TIMx Timer instance
2899 * @param GroupCH5 This parameter can be a combination of the following values:
2900 * @arg @ref LL_TIM_GROUPCH5_NONE
2901 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2902 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2903 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2904 * @retval None
2905 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2906 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2907 {
2908 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2909 }
2910
2911 /**
2912 * @}
2913 */
2914
2915 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2916 * @{
2917 */
2918 /**
2919 * @brief Configure input channel.
2920 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2921 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2922 * CCMR1 IC1F LL_TIM_IC_Config\n
2923 * CCMR1 CC2S LL_TIM_IC_Config\n
2924 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2925 * CCMR1 IC2F LL_TIM_IC_Config\n
2926 * CCMR2 CC3S LL_TIM_IC_Config\n
2927 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2928 * CCMR2 IC3F LL_TIM_IC_Config\n
2929 * CCMR2 CC4S LL_TIM_IC_Config\n
2930 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2931 * CCMR2 IC4F LL_TIM_IC_Config\n
2932 * CCER CC1P LL_TIM_IC_Config\n
2933 * CCER CC1NP LL_TIM_IC_Config\n
2934 * CCER CC2P LL_TIM_IC_Config\n
2935 * CCER CC2NP LL_TIM_IC_Config\n
2936 * CCER CC3P LL_TIM_IC_Config\n
2937 * CCER CC3NP LL_TIM_IC_Config\n
2938 * CCER CC4P LL_TIM_IC_Config\n
2939 * CCER CC4NP LL_TIM_IC_Config
2940 * @param TIMx Timer instance
2941 * @param Channel This parameter can be one of the following values:
2942 * @arg @ref LL_TIM_CHANNEL_CH1
2943 * @arg @ref LL_TIM_CHANNEL_CH2
2944 * @arg @ref LL_TIM_CHANNEL_CH3
2945 * @arg @ref LL_TIM_CHANNEL_CH4
2946 * @param Configuration This parameter must be a combination of all the following values:
2947 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2948 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2949 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2950 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2951 * @retval None
2952 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2953 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2954 {
2955 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2956 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2957 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2958 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2959 << SHIFT_TAB_ICxx[iChannel]);
2960 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2961 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2962 }
2963
2964 /**
2965 * @brief Set the active input.
2966 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2967 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2968 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2969 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2970 * @param TIMx Timer instance
2971 * @param Channel This parameter can be one of the following values:
2972 * @arg @ref LL_TIM_CHANNEL_CH1
2973 * @arg @ref LL_TIM_CHANNEL_CH2
2974 * @arg @ref LL_TIM_CHANNEL_CH3
2975 * @arg @ref LL_TIM_CHANNEL_CH4
2976 * @param ICActiveInput This parameter can be one of the following values:
2977 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2978 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2979 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2980 * @retval None
2981 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2982 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2983 {
2984 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2985 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2986 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2987 }
2988
2989 /**
2990 * @brief Get the current active input.
2991 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2992 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2993 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2994 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2995 * @param TIMx Timer instance
2996 * @param Channel This parameter can be one of the following values:
2997 * @arg @ref LL_TIM_CHANNEL_CH1
2998 * @arg @ref LL_TIM_CHANNEL_CH2
2999 * @arg @ref LL_TIM_CHANNEL_CH3
3000 * @arg @ref LL_TIM_CHANNEL_CH4
3001 * @retval Returned value can be one of the following values:
3002 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3003 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3004 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3005 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3006 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3007 {
3008 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3009 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3010 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3011 }
3012
3013 /**
3014 * @brief Set the prescaler of input channel.
3015 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3016 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3017 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3018 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3019 * @param TIMx Timer instance
3020 * @param Channel This parameter can be one of the following values:
3021 * @arg @ref LL_TIM_CHANNEL_CH1
3022 * @arg @ref LL_TIM_CHANNEL_CH2
3023 * @arg @ref LL_TIM_CHANNEL_CH3
3024 * @arg @ref LL_TIM_CHANNEL_CH4
3025 * @param ICPrescaler This parameter can be one of the following values:
3026 * @arg @ref LL_TIM_ICPSC_DIV1
3027 * @arg @ref LL_TIM_ICPSC_DIV2
3028 * @arg @ref LL_TIM_ICPSC_DIV4
3029 * @arg @ref LL_TIM_ICPSC_DIV8
3030 * @retval None
3031 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3032 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3033 {
3034 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3035 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3036 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3037 }
3038
3039 /**
3040 * @brief Get the current prescaler value acting on an input channel.
3041 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3042 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3043 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3044 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3045 * @param TIMx Timer instance
3046 * @param Channel This parameter can be one of the following values:
3047 * @arg @ref LL_TIM_CHANNEL_CH1
3048 * @arg @ref LL_TIM_CHANNEL_CH2
3049 * @arg @ref LL_TIM_CHANNEL_CH3
3050 * @arg @ref LL_TIM_CHANNEL_CH4
3051 * @retval Returned value can be one of the following values:
3052 * @arg @ref LL_TIM_ICPSC_DIV1
3053 * @arg @ref LL_TIM_ICPSC_DIV2
3054 * @arg @ref LL_TIM_ICPSC_DIV4
3055 * @arg @ref LL_TIM_ICPSC_DIV8
3056 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3057 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3058 {
3059 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3060 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3061 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3062 }
3063
3064 /**
3065 * @brief Set the input filter duration.
3066 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3067 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3068 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3069 * CCMR2 IC4F LL_TIM_IC_SetFilter
3070 * @param TIMx Timer instance
3071 * @param Channel This parameter can be one of the following values:
3072 * @arg @ref LL_TIM_CHANNEL_CH1
3073 * @arg @ref LL_TIM_CHANNEL_CH2
3074 * @arg @ref LL_TIM_CHANNEL_CH3
3075 * @arg @ref LL_TIM_CHANNEL_CH4
3076 * @param ICFilter This parameter can be one of the following values:
3077 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3078 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3079 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3080 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3081 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3082 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3083 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3084 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3085 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3086 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3087 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3088 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3089 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3090 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3091 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3092 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3093 * @retval None
3094 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3095 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3096 {
3097 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3098 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3099 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3100 }
3101
3102 /**
3103 * @brief Get the input filter duration.
3104 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3105 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3106 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3107 * CCMR2 IC4F LL_TIM_IC_GetFilter
3108 * @param TIMx Timer instance
3109 * @param Channel This parameter can be one of the following values:
3110 * @arg @ref LL_TIM_CHANNEL_CH1
3111 * @arg @ref LL_TIM_CHANNEL_CH2
3112 * @arg @ref LL_TIM_CHANNEL_CH3
3113 * @arg @ref LL_TIM_CHANNEL_CH4
3114 * @retval Returned value can be one of the following values:
3115 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3116 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3117 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3118 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3119 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3120 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3121 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3122 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3123 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3124 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3125 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3126 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3127 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3128 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3129 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3130 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3131 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3132 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3133 {
3134 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3135 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3136 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3137 }
3138
3139 /**
3140 * @brief Set the input channel polarity.
3141 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3142 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3143 * CCER CC2P LL_TIM_IC_SetPolarity\n
3144 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3145 * CCER CC3P LL_TIM_IC_SetPolarity\n
3146 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3147 * CCER CC4P LL_TIM_IC_SetPolarity\n
3148 * CCER CC4NP LL_TIM_IC_SetPolarity
3149 * @param TIMx Timer instance
3150 * @param Channel This parameter can be one of the following values:
3151 * @arg @ref LL_TIM_CHANNEL_CH1
3152 * @arg @ref LL_TIM_CHANNEL_CH2
3153 * @arg @ref LL_TIM_CHANNEL_CH3
3154 * @arg @ref LL_TIM_CHANNEL_CH4
3155 * @param ICPolarity This parameter can be one of the following values:
3156 * @arg @ref LL_TIM_IC_POLARITY_RISING
3157 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3158 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3159 * @retval None
3160 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3161 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3162 {
3163 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3164 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3165 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3166 }
3167
3168 /**
3169 * @brief Get the current input channel polarity.
3170 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3171 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3172 * CCER CC2P LL_TIM_IC_GetPolarity\n
3173 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3174 * CCER CC3P LL_TIM_IC_GetPolarity\n
3175 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3176 * CCER CC4P LL_TIM_IC_GetPolarity\n
3177 * CCER CC4NP LL_TIM_IC_GetPolarity
3178 * @param TIMx Timer instance
3179 * @param Channel This parameter can be one of the following values:
3180 * @arg @ref LL_TIM_CHANNEL_CH1
3181 * @arg @ref LL_TIM_CHANNEL_CH2
3182 * @arg @ref LL_TIM_CHANNEL_CH3
3183 * @arg @ref LL_TIM_CHANNEL_CH4
3184 * @retval Returned value can be one of the following values:
3185 * @arg @ref LL_TIM_IC_POLARITY_RISING
3186 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3187 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3188 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3189 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3190 {
3191 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3192 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3193 SHIFT_TAB_CCxP[iChannel]);
3194 }
3195
3196 /**
3197 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3198 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3199 * a timer instance provides an XOR input.
3200 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3201 * @param TIMx Timer instance
3202 * @retval None
3203 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3204 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3205 {
3206 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3207 }
3208
3209 /**
3210 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3211 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3212 * a timer instance provides an XOR input.
3213 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3214 * @param TIMx Timer instance
3215 * @retval None
3216 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3217 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3218 {
3219 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3220 }
3221
3222 /**
3223 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3224 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3225 * a timer instance provides an XOR input.
3226 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3227 * @param TIMx Timer instance
3228 * @retval State of bit (1 or 0).
3229 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3230 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3231 {
3232 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3233 }
3234
3235 /**
3236 * @brief Get captured value for input channel 1.
3237 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3238 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3239 * whether or not a timer instance supports a 32 bits counter.
3240 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3241 * input channel 1 is supported by a timer instance.
3242 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3243 * @param TIMx Timer instance
3244 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3245 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3246 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3247 {
3248 return (uint32_t)(READ_REG(TIMx->CCR1));
3249 }
3250
3251 /**
3252 * @brief Get captured value for input channel 2.
3253 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3254 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3255 * whether or not a timer instance supports a 32 bits counter.
3256 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3257 * input channel 2 is supported by a timer instance.
3258 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3259 * @param TIMx Timer instance
3260 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3261 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3262 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3263 {
3264 return (uint32_t)(READ_REG(TIMx->CCR2));
3265 }
3266
3267 /**
3268 * @brief Get captured value for input channel 3.
3269 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3270 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3271 * whether or not a timer instance supports a 32 bits counter.
3272 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3273 * input channel 3 is supported by a timer instance.
3274 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3275 * @param TIMx Timer instance
3276 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3277 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3278 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3279 {
3280 return (uint32_t)(READ_REG(TIMx->CCR3));
3281 }
3282
3283 /**
3284 * @brief Get captured value for input channel 4.
3285 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3286 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3287 * whether or not a timer instance supports a 32 bits counter.
3288 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3289 * input channel 4 is supported by a timer instance.
3290 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3291 * @param TIMx Timer instance
3292 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3293 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3294 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3295 {
3296 return (uint32_t)(READ_REG(TIMx->CCR4));
3297 }
3298
3299 /**
3300 * @}
3301 */
3302
3303 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3304 * @{
3305 */
3306 /**
3307 * @brief Enable external clock mode 2.
3308 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3309 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3310 * whether or not a timer instance supports external clock mode2.
3311 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3312 * @param TIMx Timer instance
3313 * @retval None
3314 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3315 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3316 {
3317 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3318 }
3319
3320 /**
3321 * @brief Disable external clock mode 2.
3322 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3323 * whether or not a timer instance supports external clock mode2.
3324 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3325 * @param TIMx Timer instance
3326 * @retval None
3327 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3328 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3329 {
3330 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3331 }
3332
3333 /**
3334 * @brief Indicate whether external clock mode 2 is enabled.
3335 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3336 * whether or not a timer instance supports external clock mode2.
3337 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3338 * @param TIMx Timer instance
3339 * @retval State of bit (1 or 0).
3340 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3341 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3342 {
3343 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3344 }
3345
3346 /**
3347 * @brief Set the clock source of the counter clock.
3348 * @note when selected clock source is external clock mode 1, the timer input
3349 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3350 * function. This timer input must be configured by calling
3351 * the @ref LL_TIM_IC_Config() function.
3352 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3353 * whether or not a timer instance supports external clock mode1.
3354 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3355 * whether or not a timer instance supports external clock mode2.
3356 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3357 * SMCR ECE LL_TIM_SetClockSource
3358 * @param TIMx Timer instance
3359 * @param ClockSource This parameter can be one of the following values:
3360 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3361 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3362 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3363 * @retval None
3364 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3365 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3366 {
3367 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3368 }
3369
3370 /**
3371 * @brief Set the encoder interface mode.
3372 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3373 * whether or not a timer instance supports the encoder mode.
3374 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3375 * @param TIMx Timer instance
3376 * @param EncoderMode This parameter can be one of the following values:
3377 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3378 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3379 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3380 * @retval None
3381 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3382 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3383 {
3384 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3385 }
3386
3387 /**
3388 * @}
3389 */
3390
3391 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3392 * @{
3393 */
3394 /**
3395 * @brief Set the trigger output (TRGO) used for timer synchronization .
3396 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3397 * whether or not a timer instance can operate as a master timer.
3398 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3399 * @param TIMx Timer instance
3400 * @param TimerSynchronization This parameter can be one of the following values:
3401 * @arg @ref LL_TIM_TRGO_RESET
3402 * @arg @ref LL_TIM_TRGO_ENABLE
3403 * @arg @ref LL_TIM_TRGO_UPDATE
3404 * @arg @ref LL_TIM_TRGO_CC1IF
3405 * @arg @ref LL_TIM_TRGO_OC1REF
3406 * @arg @ref LL_TIM_TRGO_OC2REF
3407 * @arg @ref LL_TIM_TRGO_OC3REF
3408 * @arg @ref LL_TIM_TRGO_OC4REF
3409 * @retval None
3410 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3411 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3412 {
3413 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3414 }
3415
3416 /**
3417 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3418 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3419 * whether or not a timer instance can be used for ADC synchronization.
3420 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3421 * @param TIMx Timer Instance
3422 * @param ADCSynchronization This parameter can be one of the following values:
3423 * @arg @ref LL_TIM_TRGO2_RESET
3424 * @arg @ref LL_TIM_TRGO2_ENABLE
3425 * @arg @ref LL_TIM_TRGO2_UPDATE
3426 * @arg @ref LL_TIM_TRGO2_CC1F
3427 * @arg @ref LL_TIM_TRGO2_OC1
3428 * @arg @ref LL_TIM_TRGO2_OC2
3429 * @arg @ref LL_TIM_TRGO2_OC3
3430 * @arg @ref LL_TIM_TRGO2_OC4
3431 * @arg @ref LL_TIM_TRGO2_OC5
3432 * @arg @ref LL_TIM_TRGO2_OC6
3433 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3434 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3435 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3436 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3437 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3438 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3439 * @retval None
3440 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3441 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3442 {
3443 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3444 }
3445
3446 /**
3447 * @brief Set the synchronization mode of a slave timer.
3448 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3449 * a timer instance can operate as a slave timer.
3450 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3451 * @param TIMx Timer instance
3452 * @param SlaveMode This parameter can be one of the following values:
3453 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3454 * @arg @ref LL_TIM_SLAVEMODE_RESET
3455 * @arg @ref LL_TIM_SLAVEMODE_GATED
3456 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3457 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3458 * @retval None
3459 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3460 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3461 {
3462 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3463 }
3464
3465 /**
3466 * @brief Set the selects the trigger input to be used to synchronize the counter.
3467 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3468 * a timer instance can operate as a slave timer.
3469 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3470 * @param TIMx Timer instance
3471 * @param TriggerInput This parameter can be one of the following values:
3472 * @arg @ref LL_TIM_TS_ITR0
3473 * @arg @ref LL_TIM_TS_ITR1
3474 * @arg @ref LL_TIM_TS_ITR2
3475 * @arg @ref LL_TIM_TS_ITR3
3476 * @arg @ref LL_TIM_TS_ITR7 (*)
3477 * @arg @ref LL_TIM_TS_TI1F_ED
3478 * @arg @ref LL_TIM_TS_TI1FP1
3479 * @arg @ref LL_TIM_TS_TI2FP2
3480 * @arg @ref LL_TIM_TS_ETRF
3481 *
3482 * (*) Value not defined in all devices.
3483 * @retval None
3484 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3485 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3486 {
3487 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3488 }
3489
3490 /**
3491 * @brief Enable the Master/Slave mode.
3492 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3493 * a timer instance can operate as a slave timer.
3494 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3495 * @param TIMx Timer instance
3496 * @retval None
3497 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3498 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3499 {
3500 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3501 }
3502
3503 /**
3504 * @brief Disable the Master/Slave mode.
3505 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3506 * a timer instance can operate as a slave timer.
3507 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3508 * @param TIMx Timer instance
3509 * @retval None
3510 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3511 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3512 {
3513 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3514 }
3515
3516 /**
3517 * @brief Indicates whether the Master/Slave mode is enabled.
3518 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3519 * a timer instance can operate as a slave timer.
3520 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3521 * @param TIMx Timer instance
3522 * @retval State of bit (1 or 0).
3523 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3524 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3525 {
3526 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3527 }
3528
3529 /**
3530 * @brief Configure the external trigger (ETR) input.
3531 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3532 * a timer instance provides an external trigger input.
3533 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3534 * SMCR ETPS LL_TIM_ConfigETR\n
3535 * SMCR ETF LL_TIM_ConfigETR
3536 * @param TIMx Timer instance
3537 * @param ETRPolarity This parameter can be one of the following values:
3538 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3539 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3540 * @param ETRPrescaler This parameter can be one of the following values:
3541 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3542 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3543 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3544 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3545 * @param ETRFilter This parameter can be one of the following values:
3546 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3547 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3548 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3549 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3550 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3551 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3552 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3553 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3554 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3555 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3556 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3557 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3558 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3559 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3560 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3561 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3562 * @retval None
3563 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3564 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3565 uint32_t ETRFilter)
3566 {
3567 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3568 }
3569
3570 /**
3571 * @brief Select the external trigger (ETR) input source.
3572 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3573 * not a timer instance supports ETR source selection.
3574 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3575 * @param TIMx Timer instance
3576 * @param ETRSource This parameter can be one of the following values:
3577 * TIM1
3578 *
3579 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3580 * @arg @ref LL_TIM_ETRSOURCE_COMP1 (**)
3581 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (**)
3582 * @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
3583 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3584 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
3585 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
3586 *
3587 * TIM2 (*)
3588 *
3589 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3590 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3591 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3592 * @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
3593 * @arg @ref LL_TIM_ETRSOURCE_LSE
3594 * @arg @ref LL_TIM_ETRSOURCE_MCO (**)
3595 * @arg @ref LL_TIM_ETRSOURCE_MCO2 (**)
3596 *
3597 * TIM3
3598 *
3599 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3600 * @arg @ref LL_TIM_ETRSOURCE_COMP1 (**)
3601 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (**)
3602 * @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
3603 *
3604 * TIM4 (*)
3605 *
3606 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3607 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3608 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3609 * @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
3610 *
3611 * (*) Timer instance not available on all devices \n
3612 * (**) Value not defined in all devices. \n
3613 *
3614 * @retval None
3615 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3616 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3617 {
3618 #if defined(COMP3)
3619 uint32_t etrsel_shift = ((ETRSource == LL_TIM_ETRSOURCE_COMP3) ? 1u : 0u);
3620 if ((TIMx == TIM1) || (TIMx == TIM2))
3621 {
3622 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3623 }
3624 else
3625 {
3626 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource >> etrsel_shift);
3627 }
3628 #else
3629 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3630 #endif /* COMP3 */
3631 }
3632
3633 /**
3634 * @}
3635 */
3636
3637 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3638 * @{
3639 */
3640 /**
3641 * @brief Enable the break function.
3642 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3643 * a timer instance provides a break input.
3644 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3645 * @param TIMx Timer instance
3646 * @retval None
3647 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3648 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3649 {
3650 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3651 }
3652
3653 /**
3654 * @brief Disable the break function.
3655 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3656 * @param TIMx Timer instance
3657 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3658 * a timer instance provides a break input.
3659 * @retval None
3660 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3661 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3662 {
3663 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3664 }
3665
3666 /**
3667 * @brief Configure the break input.
3668 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3669 * a timer instance provides a break input.
3670 * @note Bidirectional mode is only supported by advanced timer instances.
3671 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3672 * a timer instance is an advanced-control timer.
3673 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3674 * in input mode and in open drain output mode. Any active Break event will
3675 * assert a low logic level on the Break input to indicate an internal break
3676 * event to external devices.
3677 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3678 * LL_TIM_BREAK_AFMODE_INPUT.
3679 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3680 * BDTR BKF LL_TIM_ConfigBRK\n
3681 * BDTR BKBID LL_TIM_ConfigBRK
3682 * @param TIMx Timer instance
3683 * @param BreakPolarity This parameter can be one of the following values:
3684 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3685 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3686 * @param BreakFilter This parameter can be one of the following values:
3687 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3688 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3689 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3690 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3691 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3692 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3693 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3694 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3695 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3696 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3697 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3698 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3699 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3700 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3701 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3702 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3703 * @param BreakAFMode This parameter can be one of the following values:
3704 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3705 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3706 * @retval None
3707 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3708 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3709 uint32_t BreakAFMode)
3710 {
3711 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3712 }
3713
3714 /**
3715 * @brief Disarm the break input (when it operates in bidirectional mode).
3716 * @note The break input can be disarmed only when it is configured in
3717 * bidirectional mode and when when MOE is reset.
3718 * @note Purpose is to be able to have the input voltage back to high-state,
3719 * whatever the time constant on the output .
3720 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3721 * @param TIMx Timer instance
3722 * @retval None
3723 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3724 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3725 {
3726 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3727 }
3728
3729 /**
3730 * @brief Enable the break 2 function.
3731 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3732 * a timer instance provides a second break input.
3733 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3734 * @param TIMx Timer instance
3735 * @retval None
3736 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3737 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3738 {
3739 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3740 }
3741
3742 /**
3743 * @brief Disable the break 2 function.
3744 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3745 * a timer instance provides a second break input.
3746 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3747 * @param TIMx Timer instance
3748 * @retval None
3749 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3750 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3751 {
3752 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3753 }
3754
3755 /**
3756 * @brief Configure the break 2 input.
3757 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3758 * a timer instance provides a second break input.
3759 * @note Bidirectional mode is only supported by advanced timer instances.
3760 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3761 * a timer instance is an advanced-control timer.
3762 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3763 * in input mode and in open drain output mode. Any active Break event will
3764 * assert a low logic level on the Break 2 input to indicate an internal break
3765 * event to external devices.
3766 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3767 * LL_TIM_BREAK2_AFMODE_INPUT.
3768 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3769 * BDTR BK2F LL_TIM_ConfigBRK2\n
3770 * BDTR BK2BID LL_TIM_ConfigBRK2
3771 * @param TIMx Timer instance
3772 * @param Break2Polarity This parameter can be one of the following values:
3773 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3774 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3775 * @param Break2Filter This parameter can be one of the following values:
3776 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3777 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3778 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3779 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3780 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3781 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3782 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3783 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3784 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3785 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3786 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3787 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3788 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3789 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3790 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3791 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3792 * @param Break2AFMode This parameter can be one of the following values:
3793 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3794 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3795 * @retval None
3796 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3797 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3798 uint32_t Break2AFMode)
3799 {
3800 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3801 }
3802
3803 /**
3804 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3805 * @note The break 2 input can be disarmed only when it is configured in
3806 * bidirectional mode and when when MOE is reset.
3807 * @note Purpose is to be able to have the input voltage back to high-state,
3808 * whatever the time constant on the output.
3809 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3810 * @param TIMx Timer instance
3811 * @retval None
3812 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3813 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3814 {
3815 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3816 }
3817
3818 /**
3819 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3820 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3821 * a timer instance provides a break input.
3822 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3823 * BDTR OSSR LL_TIM_SetOffStates
3824 * @param TIMx Timer instance
3825 * @param OffStateIdle This parameter can be one of the following values:
3826 * @arg @ref LL_TIM_OSSI_DISABLE
3827 * @arg @ref LL_TIM_OSSI_ENABLE
3828 * @param OffStateRun This parameter can be one of the following values:
3829 * @arg @ref LL_TIM_OSSR_DISABLE
3830 * @arg @ref LL_TIM_OSSR_ENABLE
3831 * @retval None
3832 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3833 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3834 {
3835 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3836 }
3837
3838 /**
3839 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3840 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3841 * a timer instance provides a break input.
3842 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3843 * @param TIMx Timer instance
3844 * @retval None
3845 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3846 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3847 {
3848 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3849 }
3850
3851 /**
3852 * @brief Disable automatic output (MOE can be set only by software).
3853 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3854 * a timer instance provides a break input.
3855 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3856 * @param TIMx Timer instance
3857 * @retval None
3858 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3859 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3860 {
3861 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3862 }
3863
3864 /**
3865 * @brief Indicate whether automatic output is enabled.
3866 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3867 * a timer instance provides a break input.
3868 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3869 * @param TIMx Timer instance
3870 * @retval State of bit (1 or 0).
3871 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3872 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3873 {
3874 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3875 }
3876
3877 /**
3878 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3879 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3880 * software and is reset in case of break or break2 event
3881 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3882 * a timer instance provides a break input.
3883 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3884 * @param TIMx Timer instance
3885 * @retval None
3886 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3887 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3888 {
3889 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3890 }
3891
3892 /**
3893 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3894 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3895 * software and is reset in case of break or break2 event.
3896 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3897 * a timer instance provides a break input.
3898 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3899 * @param TIMx Timer instance
3900 * @retval None
3901 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3902 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3903 {
3904 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3905 }
3906
3907 /**
3908 * @brief Indicates whether outputs are enabled.
3909 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3910 * a timer instance provides a break input.
3911 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3912 * @param TIMx Timer instance
3913 * @retval State of bit (1 or 0).
3914 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3915 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3916 {
3917 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3918 }
3919
3920 /**
3921 * @brief Enable the signals connected to the designated timer break input.
3922 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3923 * or not a timer instance allows for break input selection.
3924 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3925 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3926 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3927 * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
3928 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3929 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3930 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3931 * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource
3932 * @param TIMx Timer instance
3933 * @param BreakInput This parameter can be one of the following values:
3934 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3935 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3936 * @param Source This parameter can be one of the following values:
3937 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3938 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3939 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3940 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
3941 *
3942 * (*) Value not defined in all devices. \n
3943 *
3944 * @retval None
3945 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3946 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3947 {
3948 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3949 SET_BIT(*pReg, Source);
3950 }
3951
3952 /**
3953 * @brief Disable the signals connected to the designated timer break input.
3954 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3955 * or not a timer instance allows for break input selection.
3956 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3957 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3958 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3959 * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
3960 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3961 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3962 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3963 * AF2 BK2CMP3E LL_TIM_DisableBreakInputSource
3964 * @param TIMx Timer instance
3965 * @param BreakInput This parameter can be one of the following values:
3966 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3967 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3968 * @param Source This parameter can be one of the following values:
3969 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3970 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3971 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3972 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
3973 *
3974 * (*) Value not defined in all devices. \n
3975 *
3976 * @retval None
3977 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3978 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3979 {
3980 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3981 CLEAR_BIT(*pReg, Source);
3982 }
3983
3984 /**
3985 * @brief Set the polarity of the break signal for the timer break input.
3986 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3987 * or not a timer instance allows for break input selection.
3988 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3989 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3990 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3991 * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
3992 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3993 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3994 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
3995 * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity
3996 * @param TIMx Timer instance
3997 * @param BreakInput This parameter can be one of the following values:
3998 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3999 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4000 * @param Source This parameter can be one of the following values:
4001 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4002 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4003 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4004 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
4005 * @param Polarity This parameter can be one of the following values:
4006 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4007 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4008 *
4009 * (*) Value not defined in all devices. \n
4010 *
4011 * @retval None
4012 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4013 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4014 uint32_t Polarity)
4015 {
4016 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4017 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4018 }
4019 /**
4020 * @}
4021 */
4022
4023 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4024 * @{
4025 */
4026 /**
4027 * @brief Configures the timer DMA burst feature.
4028 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4029 * not a timer instance supports the DMA burst mode.
4030 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4031 * DCR DBA LL_TIM_ConfigDMABurst
4032 * @param TIMx Timer instance
4033 * @param DMABurstBaseAddress This parameter can be one of the following values:
4034 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4035 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4036 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4037 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4038 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4039 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4040 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4041 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4042 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4043 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4044 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4045 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4046 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4047 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4048 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4049 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4050 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4051 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4052 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
4053 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4054 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4055 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4056 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4057 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4058 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4059 * @param DMABurstLength This parameter can be one of the following values:
4060 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4061 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4062 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4063 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4064 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4065 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4066 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4067 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4068 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4069 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4070 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4071 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4072 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4073 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4074 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4075 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4076 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4077 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4078 * @retval None
4079 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)4080 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
4081 {
4082 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
4083 }
4084
4085 /**
4086 * @}
4087 */
4088
4089 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4090 * @{
4091 */
4092 /**
4093 * @brief Remap TIM inputs (input channel, internal/external triggers).
4094 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4095 * a some timer inputs can be remapped.
4096 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
4097 * TIM1_TISEL TI2SEL LL_TIM_SetRemap\n
4098 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
4099 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
4100 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
4101 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
4102 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
4103 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
4104 * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
4105 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
4106 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
4107 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
4108 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
4109 * TIM17_TISEL TI1SEL LL_TIM_SetRemap
4110 * @param TIMx Timer instance
4111 * @param Remap Remap param depends on the TIMx. Description available only
4112 * in CHM version of the User Manual (not in .pdf).
4113 * Otherwise see Reference Manual description of TISEL registers.
4114 *
4115 * Below description summarizes "Timer Instance" and "Remap" param combinations:
4116 *
4117 * TIM1: any combination of TI1_RMP and TI2_RMP where
4118 *
4119 * . . TI1_RMP can be one of the following values
4120 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
4121 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (**)
4122 *
4123 * . . TI2_RMP can be one of the following values
4124 * @arg @ref LL_TIM_TIM1_TI2_RMP_GPIO
4125 * @arg @ref LL_TIM_TIM1_TI2_RMP_COMP2 (**)
4126 *
4127 * . . TI3_RMP can be one of the following values
4128 * @arg @ref LL_TIM_TIM1_TI3_RMP_GPIO
4129 * @arg @ref LL_TIM_TIM1_TI3_RMP_COMP3 (**)
4130 *
4131 * TIM2: any combination of TI1_RMP and TI2_RMP where
4132 *
4133 * . . TI1_RMP can be one of the following values
4134 * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
4135 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1 (**)
4136 *
4137 * . . TI2_RMP can be one of the following values
4138 * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
4139 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2 (**)
4140 *
4141 * . . TI3_RMP can be one of the following values
4142 * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
4143 * @arg @ref LL_TIM_TIM2_TI3_RMP_COMP3 (**)
4144 *
4145 * TIM3: any combination of TI1_RMP and TI2_RMP where
4146 *
4147 * . . TI1_RMP can be one of the following values
4148 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
4149 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 (**)
4150 *
4151 * . . TI2_RMP can be one of the following values
4152 * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
4153 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2 (**)
4154 *
4155 * . . TI3_RMP can be one of the following values
4156 * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
4157 * @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3 (**)
4158 *
4159 * TIM4: any combination of TI1_RMP, TI2_RMP and TI3_RMP where (*)
4160 *
4161 * . . TI1_RMP can be one of the following values
4162 * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
4163 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1 (**)
4164 *
4165 * . . TI2_RMP can be one of the following values
4166 * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
4167 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2 (**)
4168 *
4169 * . . TI3_RMP can be one of the following values
4170 * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
4171 * @arg @ref LL_TIM_TIM4_TI3_RMP_COMP3 (**)
4172 *
4173 * TIM14: one of the following values
4174 *
4175 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
4176 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
4177 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE_32
4178 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
4179 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO2 (**)
4180 *
4181 * TIM15: any combination of TI1_RMP and TI2_RMP where
4182 *
4183 * . . TI1_RMP can be one of the following values
4184 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
4185 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_IC1
4186 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_IC1
4187 *
4188 * . . TI2_RMP can be one of the following values
4189 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
4190 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_IC2
4191 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_IC2
4192 *
4193 * TIM16: one of the following values
4194 *
4195 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
4196 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
4197 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
4198 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
4199 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO2(**)
4200 *
4201 * TIM17: one of the following values
4202 *
4203 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
4204 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
4205 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
4206 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSI48 (**)
4207 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO2(**)
4208 *
4209 * (*) Timer instance not available on all devices \n
4210 * (**) Value not defined in all devices. \n
4211 *
4212 * @retval None
4213 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4214 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4215 {
4216 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4217 }
4218
4219 /**
4220 * @}
4221 */
4222
4223 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4224 * @{
4225 */
4226 /**
4227 * @brief Set the OCREF clear input source
4228 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4229 * @note This function can only be used in Output compare and PWM modes.
4230 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4231 * @rmtoll OR1 OCREF_CLR LL_TIM_SetOCRefClearInputSource
4232 * @param TIMx Timer instance
4233 * @param OCRefClearInputSource This parameter can be one of the following values:
4234 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4235 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 (*)
4236 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*)
4237 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP3 (*)
4238 *
4239 * (*) Value not defined in all devices. \n
4240 *
4241 * @retval None
4242 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4243 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4244 {
4245 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
4246 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
4247 MODIFY_REG(TIMx->OR1, TIM1_OR1_OCREF_CLR, OCRefClearInputSource);
4248 }
4249 /**
4250 * @}
4251 */
4252
4253 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4254 * @{
4255 */
4256 /**
4257 * @brief Clear the update interrupt flag (UIF).
4258 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4259 * @param TIMx Timer instance
4260 * @retval None
4261 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4262 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4263 {
4264 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4265 }
4266
4267 /**
4268 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4269 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4270 * @param TIMx Timer instance
4271 * @retval State of bit (1 or 0).
4272 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4273 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4274 {
4275 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4276 }
4277
4278 /**
4279 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4280 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4281 * @param TIMx Timer instance
4282 * @retval None
4283 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4284 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4285 {
4286 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4287 }
4288
4289 /**
4290 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4291 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4292 * @param TIMx Timer instance
4293 * @retval State of bit (1 or 0).
4294 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4295 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4296 {
4297 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4298 }
4299
4300 /**
4301 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4302 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4303 * @param TIMx Timer instance
4304 * @retval None
4305 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4306 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4307 {
4308 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4309 }
4310
4311 /**
4312 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4313 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4314 * @param TIMx Timer instance
4315 * @retval State of bit (1 or 0).
4316 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4317 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4318 {
4319 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4320 }
4321
4322 /**
4323 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4324 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4325 * @param TIMx Timer instance
4326 * @retval None
4327 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4328 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4329 {
4330 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4331 }
4332
4333 /**
4334 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4335 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4336 * @param TIMx Timer instance
4337 * @retval State of bit (1 or 0).
4338 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4339 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4340 {
4341 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4342 }
4343
4344 /**
4345 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4346 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4347 * @param TIMx Timer instance
4348 * @retval None
4349 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4350 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4351 {
4352 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4353 }
4354
4355 /**
4356 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4357 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4358 * @param TIMx Timer instance
4359 * @retval State of bit (1 or 0).
4360 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4361 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4362 {
4363 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4364 }
4365
4366 /**
4367 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4368 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4369 * @param TIMx Timer instance
4370 * @retval None
4371 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4372 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4373 {
4374 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4375 }
4376
4377 /**
4378 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4379 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4380 * @param TIMx Timer instance
4381 * @retval State of bit (1 or 0).
4382 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4383 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4384 {
4385 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4386 }
4387
4388 /**
4389 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4390 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4391 * @param TIMx Timer instance
4392 * @retval None
4393 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4394 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4395 {
4396 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4397 }
4398
4399 /**
4400 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4401 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4402 * @param TIMx Timer instance
4403 * @retval State of bit (1 or 0).
4404 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4405 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4406 {
4407 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4408 }
4409
4410 /**
4411 * @brief Clear the commutation interrupt flag (COMIF).
4412 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4413 * @param TIMx Timer instance
4414 * @retval None
4415 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4416 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4417 {
4418 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4419 }
4420
4421 /**
4422 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4423 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4424 * @param TIMx Timer instance
4425 * @retval State of bit (1 or 0).
4426 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4427 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4428 {
4429 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4430 }
4431
4432 /**
4433 * @brief Clear the trigger interrupt flag (TIF).
4434 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4435 * @param TIMx Timer instance
4436 * @retval None
4437 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4438 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4439 {
4440 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4441 }
4442
4443 /**
4444 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4445 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4446 * @param TIMx Timer instance
4447 * @retval State of bit (1 or 0).
4448 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4449 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4450 {
4451 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4452 }
4453
4454 /**
4455 * @brief Clear the break interrupt flag (BIF).
4456 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4457 * @param TIMx Timer instance
4458 * @retval None
4459 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4460 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4461 {
4462 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4463 }
4464
4465 /**
4466 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4467 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4468 * @param TIMx Timer instance
4469 * @retval State of bit (1 or 0).
4470 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4471 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4472 {
4473 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4474 }
4475
4476 /**
4477 * @brief Clear the break 2 interrupt flag (B2IF).
4478 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4479 * @param TIMx Timer instance
4480 * @retval None
4481 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4482 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4483 {
4484 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4485 }
4486
4487 /**
4488 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4489 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4490 * @param TIMx Timer instance
4491 * @retval State of bit (1 or 0).
4492 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4493 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4494 {
4495 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4496 }
4497
4498 /**
4499 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4500 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4501 * @param TIMx Timer instance
4502 * @retval None
4503 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4504 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4505 {
4506 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4507 }
4508
4509 /**
4510 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4511 * (Capture/Compare 1 interrupt is pending).
4512 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4513 * @param TIMx Timer instance
4514 * @retval State of bit (1 or 0).
4515 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4516 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4517 {
4518 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4519 }
4520
4521 /**
4522 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4523 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4524 * @param TIMx Timer instance
4525 * @retval None
4526 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4527 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4528 {
4529 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4530 }
4531
4532 /**
4533 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4534 * (Capture/Compare 2 over-capture interrupt is pending).
4535 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4536 * @param TIMx Timer instance
4537 * @retval State of bit (1 or 0).
4538 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4539 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4540 {
4541 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4542 }
4543
4544 /**
4545 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4546 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4547 * @param TIMx Timer instance
4548 * @retval None
4549 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4550 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4551 {
4552 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4553 }
4554
4555 /**
4556 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4557 * (Capture/Compare 3 over-capture interrupt is pending).
4558 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4559 * @param TIMx Timer instance
4560 * @retval State of bit (1 or 0).
4561 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4562 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4563 {
4564 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4565 }
4566
4567 /**
4568 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4569 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4570 * @param TIMx Timer instance
4571 * @retval None
4572 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4573 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4574 {
4575 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4576 }
4577
4578 /**
4579 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4580 * (Capture/Compare 4 over-capture interrupt is pending).
4581 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4582 * @param TIMx Timer instance
4583 * @retval State of bit (1 or 0).
4584 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4585 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4586 {
4587 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4588 }
4589
4590 /**
4591 * @brief Clear the system break interrupt flag (SBIF).
4592 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4593 * @param TIMx Timer instance
4594 * @retval None
4595 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4596 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4597 {
4598 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4599 }
4600
4601 /**
4602 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4603 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4604 * @param TIMx Timer instance
4605 * @retval State of bit (1 or 0).
4606 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4607 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4608 {
4609 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4610 }
4611
4612 /**
4613 * @}
4614 */
4615
4616 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4617 * @{
4618 */
4619 /**
4620 * @brief Enable update interrupt (UIE).
4621 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4622 * @param TIMx Timer instance
4623 * @retval None
4624 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4625 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4626 {
4627 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4628 }
4629
4630 /**
4631 * @brief Disable update interrupt (UIE).
4632 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4633 * @param TIMx Timer instance
4634 * @retval None
4635 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4636 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4637 {
4638 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4639 }
4640
4641 /**
4642 * @brief Indicates whether the update interrupt (UIE) is enabled.
4643 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4644 * @param TIMx Timer instance
4645 * @retval State of bit (1 or 0).
4646 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4647 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4648 {
4649 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4650 }
4651
4652 /**
4653 * @brief Enable capture/compare 1 interrupt (CC1IE).
4654 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4655 * @param TIMx Timer instance
4656 * @retval None
4657 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4658 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4659 {
4660 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4661 }
4662
4663 /**
4664 * @brief Disable capture/compare 1 interrupt (CC1IE).
4665 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4666 * @param TIMx Timer instance
4667 * @retval None
4668 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4669 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4670 {
4671 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4672 }
4673
4674 /**
4675 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4676 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4677 * @param TIMx Timer instance
4678 * @retval State of bit (1 or 0).
4679 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4680 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4681 {
4682 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4683 }
4684
4685 /**
4686 * @brief Enable capture/compare 2 interrupt (CC2IE).
4687 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4688 * @param TIMx Timer instance
4689 * @retval None
4690 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4691 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4692 {
4693 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4694 }
4695
4696 /**
4697 * @brief Disable capture/compare 2 interrupt (CC2IE).
4698 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4699 * @param TIMx Timer instance
4700 * @retval None
4701 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4702 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4703 {
4704 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4705 }
4706
4707 /**
4708 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4709 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4710 * @param TIMx Timer instance
4711 * @retval State of bit (1 or 0).
4712 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4713 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4714 {
4715 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4716 }
4717
4718 /**
4719 * @brief Enable capture/compare 3 interrupt (CC3IE).
4720 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4721 * @param TIMx Timer instance
4722 * @retval None
4723 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4724 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4725 {
4726 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4727 }
4728
4729 /**
4730 * @brief Disable capture/compare 3 interrupt (CC3IE).
4731 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4732 * @param TIMx Timer instance
4733 * @retval None
4734 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4735 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4736 {
4737 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4738 }
4739
4740 /**
4741 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4742 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4743 * @param TIMx Timer instance
4744 * @retval State of bit (1 or 0).
4745 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4746 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4747 {
4748 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4749 }
4750
4751 /**
4752 * @brief Enable capture/compare 4 interrupt (CC4IE).
4753 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4754 * @param TIMx Timer instance
4755 * @retval None
4756 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4757 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4758 {
4759 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4760 }
4761
4762 /**
4763 * @brief Disable capture/compare 4 interrupt (CC4IE).
4764 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4765 * @param TIMx Timer instance
4766 * @retval None
4767 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4768 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4769 {
4770 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4771 }
4772
4773 /**
4774 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4775 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4776 * @param TIMx Timer instance
4777 * @retval State of bit (1 or 0).
4778 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4779 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4780 {
4781 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4782 }
4783
4784 /**
4785 * @brief Enable commutation interrupt (COMIE).
4786 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4787 * @param TIMx Timer instance
4788 * @retval None
4789 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4790 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4791 {
4792 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4793 }
4794
4795 /**
4796 * @brief Disable commutation interrupt (COMIE).
4797 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4798 * @param TIMx Timer instance
4799 * @retval None
4800 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4801 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4802 {
4803 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4804 }
4805
4806 /**
4807 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4808 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4809 * @param TIMx Timer instance
4810 * @retval State of bit (1 or 0).
4811 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4812 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4813 {
4814 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4815 }
4816
4817 /**
4818 * @brief Enable trigger interrupt (TIE).
4819 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4820 * @param TIMx Timer instance
4821 * @retval None
4822 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4823 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4824 {
4825 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4826 }
4827
4828 /**
4829 * @brief Disable trigger interrupt (TIE).
4830 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4831 * @param TIMx Timer instance
4832 * @retval None
4833 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4834 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4835 {
4836 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4837 }
4838
4839 /**
4840 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4841 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4842 * @param TIMx Timer instance
4843 * @retval State of bit (1 or 0).
4844 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4845 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4846 {
4847 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4848 }
4849
4850 /**
4851 * @brief Enable break interrupt (BIE).
4852 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4853 * @param TIMx Timer instance
4854 * @retval None
4855 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4856 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4857 {
4858 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4859 }
4860
4861 /**
4862 * @brief Disable break interrupt (BIE).
4863 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4864 * @param TIMx Timer instance
4865 * @retval None
4866 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4867 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4868 {
4869 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4870 }
4871
4872 /**
4873 * @brief Indicates whether the break interrupt (BIE) is enabled.
4874 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4875 * @param TIMx Timer instance
4876 * @retval State of bit (1 or 0).
4877 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4878 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4879 {
4880 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4881 }
4882
4883 /**
4884 * @}
4885 */
4886
4887 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4888 * @{
4889 */
4890 /**
4891 * @brief Enable update DMA request (UDE).
4892 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4893 * @param TIMx Timer instance
4894 * @retval None
4895 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4896 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4897 {
4898 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4899 }
4900
4901 /**
4902 * @brief Disable update DMA request (UDE).
4903 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4904 * @param TIMx Timer instance
4905 * @retval None
4906 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4907 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4908 {
4909 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4910 }
4911
4912 /**
4913 * @brief Indicates whether the update DMA request (UDE) is enabled.
4914 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4915 * @param TIMx Timer instance
4916 * @retval State of bit (1 or 0).
4917 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4918 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4919 {
4920 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4921 }
4922
4923 /**
4924 * @brief Enable capture/compare 1 DMA request (CC1DE).
4925 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4926 * @param TIMx Timer instance
4927 * @retval None
4928 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4929 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4930 {
4931 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4932 }
4933
4934 /**
4935 * @brief Disable capture/compare 1 DMA request (CC1DE).
4936 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4937 * @param TIMx Timer instance
4938 * @retval None
4939 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4940 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4941 {
4942 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4943 }
4944
4945 /**
4946 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4947 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4948 * @param TIMx Timer instance
4949 * @retval State of bit (1 or 0).
4950 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4951 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4952 {
4953 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4954 }
4955
4956 /**
4957 * @brief Enable capture/compare 2 DMA request (CC2DE).
4958 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4959 * @param TIMx Timer instance
4960 * @retval None
4961 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4962 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4963 {
4964 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4965 }
4966
4967 /**
4968 * @brief Disable capture/compare 2 DMA request (CC2DE).
4969 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4970 * @param TIMx Timer instance
4971 * @retval None
4972 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4973 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4974 {
4975 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4976 }
4977
4978 /**
4979 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4980 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4981 * @param TIMx Timer instance
4982 * @retval State of bit (1 or 0).
4983 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4984 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4985 {
4986 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4987 }
4988
4989 /**
4990 * @brief Enable capture/compare 3 DMA request (CC3DE).
4991 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4992 * @param TIMx Timer instance
4993 * @retval None
4994 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4995 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4996 {
4997 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4998 }
4999
5000 /**
5001 * @brief Disable capture/compare 3 DMA request (CC3DE).
5002 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
5003 * @param TIMx Timer instance
5004 * @retval None
5005 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)5006 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
5007 {
5008 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5009 }
5010
5011 /**
5012 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
5013 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
5014 * @param TIMx Timer instance
5015 * @retval State of bit (1 or 0).
5016 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)5017 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
5018 {
5019 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
5020 }
5021
5022 /**
5023 * @brief Enable capture/compare 4 DMA request (CC4DE).
5024 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
5025 * @param TIMx Timer instance
5026 * @retval None
5027 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)5028 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
5029 {
5030 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5031 }
5032
5033 /**
5034 * @brief Disable capture/compare 4 DMA request (CC4DE).
5035 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
5036 * @param TIMx Timer instance
5037 * @retval None
5038 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)5039 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
5040 {
5041 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5042 }
5043
5044 /**
5045 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
5046 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
5047 * @param TIMx Timer instance
5048 * @retval State of bit (1 or 0).
5049 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)5050 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
5051 {
5052 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
5053 }
5054
5055 /**
5056 * @brief Enable commutation DMA request (COMDE).
5057 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
5058 * @param TIMx Timer instance
5059 * @retval None
5060 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)5061 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
5062 {
5063 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
5064 }
5065
5066 /**
5067 * @brief Disable commutation DMA request (COMDE).
5068 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
5069 * @param TIMx Timer instance
5070 * @retval None
5071 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)5072 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
5073 {
5074 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
5075 }
5076
5077 /**
5078 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
5079 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
5080 * @param TIMx Timer instance
5081 * @retval State of bit (1 or 0).
5082 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)5083 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
5084 {
5085 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
5086 }
5087
5088 /**
5089 * @brief Enable trigger interrupt (TDE).
5090 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
5091 * @param TIMx Timer instance
5092 * @retval None
5093 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)5094 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
5095 {
5096 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
5097 }
5098
5099 /**
5100 * @brief Disable trigger interrupt (TDE).
5101 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
5102 * @param TIMx Timer instance
5103 * @retval None
5104 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)5105 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
5106 {
5107 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
5108 }
5109
5110 /**
5111 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
5112 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
5113 * @param TIMx Timer instance
5114 * @retval State of bit (1 or 0).
5115 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)5116 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
5117 {
5118 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
5119 }
5120
5121 /**
5122 * @}
5123 */
5124
5125 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
5126 * @{
5127 */
5128 /**
5129 * @brief Generate an update event.
5130 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
5131 * @param TIMx Timer instance
5132 * @retval None
5133 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)5134 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
5135 {
5136 SET_BIT(TIMx->EGR, TIM_EGR_UG);
5137 }
5138
5139 /**
5140 * @brief Generate Capture/Compare 1 event.
5141 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
5142 * @param TIMx Timer instance
5143 * @retval None
5144 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)5145 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
5146 {
5147 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
5148 }
5149
5150 /**
5151 * @brief Generate Capture/Compare 2 event.
5152 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
5153 * @param TIMx Timer instance
5154 * @retval None
5155 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)5156 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
5157 {
5158 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
5159 }
5160
5161 /**
5162 * @brief Generate Capture/Compare 3 event.
5163 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
5164 * @param TIMx Timer instance
5165 * @retval None
5166 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)5167 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
5168 {
5169 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
5170 }
5171
5172 /**
5173 * @brief Generate Capture/Compare 4 event.
5174 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
5175 * @param TIMx Timer instance
5176 * @retval None
5177 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)5178 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
5179 {
5180 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
5181 }
5182
5183 /**
5184 * @brief Generate commutation event.
5185 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
5186 * @param TIMx Timer instance
5187 * @retval None
5188 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)5189 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
5190 {
5191 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
5192 }
5193
5194 /**
5195 * @brief Generate trigger event.
5196 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
5197 * @param TIMx Timer instance
5198 * @retval None
5199 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)5200 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
5201 {
5202 SET_BIT(TIMx->EGR, TIM_EGR_TG);
5203 }
5204
5205 /**
5206 * @brief Generate break event.
5207 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
5208 * @param TIMx Timer instance
5209 * @retval None
5210 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)5211 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
5212 {
5213 SET_BIT(TIMx->EGR, TIM_EGR_BG);
5214 }
5215
5216 /**
5217 * @brief Generate break 2 event.
5218 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
5219 * @param TIMx Timer instance
5220 * @retval None
5221 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)5222 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
5223 {
5224 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
5225 }
5226
5227 /**
5228 * @}
5229 */
5230
5231 #if defined(USE_FULL_LL_DRIVER)
5232 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5233 * @{
5234 */
5235
5236 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
5237 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5238 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
5239 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5240 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5241 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5242 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5243 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5244 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5245 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5246 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5247 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5248 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5249 /**
5250 * @}
5251 */
5252 #endif /* USE_FULL_LL_DRIVER */
5253
5254 /**
5255 * @}
5256 */
5257
5258 /**
5259 * @}
5260 */
5261
5262 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
5263
5264 /**
5265 * @}
5266 */
5267
5268 #ifdef __cplusplus
5269 }
5270 #endif
5271
5272 #endif /* __STM32G0xx_LL_TIM_H */
5273
