1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G0xx_LL_ADC_H
21 #define STM32G0xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g0xx.h"
29
30 /** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer rank bits position into the selected register */
51
52 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
53
54 /* Definition of ADC group regular sequencer bits information to be inserted */
55 /* into ADC group regular sequencer ranks literals definition. */
56 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
57 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
58 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
59 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
60 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
61 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
62 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
63 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
64
65
66
67 /* Internal mask for ADC group regular trigger: */
68 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
69 /* - regular trigger source */
70 /* - regular trigger edge */
71 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
72 compatibility with some ADC on other STM32 series
73 having this setting set by HW default value) */
74
75 /* Mask containing trigger source masks for each of possible */
76 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
77 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
78 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
79 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
80 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
81 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
82
83 /* Mask containing trigger edge masks for each of possible */
84 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
85 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
86 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
87 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
88 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
89 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
90
91 /* Definition of ADC group regular trigger bits information. */
92 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
93 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
94
95
96
97 /* Internal mask for ADC channel: */
98 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
99 /* - channel identifier defined by number */
100 /* - channel identifier defined by bitfield */
101 /* - channel differentiation between external channels (connected to */
102 /* GPIO pins) and internal channels (connected to internal paths) */
103 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
104 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
105 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
106 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
107 if set to mode "fully configurable", can contain channels with a restricted channel number.
108 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
109 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
110 position in register */
111 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
112 ADC_CHANNEL_ID_INTERNAL_CH_MASK)
113 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
114 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
115 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
116
117 /* Channel differentiation between external and internal channels */
118 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
119 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
120
121 /* Definition of channels ID number information to be inserted into */
122 /* channels literals definition. */
123 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
124 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
125 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
126 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
127 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
128 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
129 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
130 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
131 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
132 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
133 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
134 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
135 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
136 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
137 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
138 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
139 ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
140 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
141 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
142 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
143
144 /* Definition of channels ID bitfield information to be inserted into */
145 /* channels literals definition. */
146 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
147 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
148 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
149 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
150 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
151 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
152 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
153 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
154 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
155 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
156 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
157 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
158 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
159 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
160 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
161 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
162 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
163 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
164 #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
165
166 /* Internal mask for ADC channel sampling time: */
167 /* To select into literals LL_ADC_SAMPLINGTIME_x */
168 /* the relevant bits for: */
169 /* (concatenation of multiple bits used in register SMPR) */
170 /* - ADC channels sampling time: setting channel wise, to map each channel */
171 /* on one of the common sampling time available. */
172 /* - ADC channels common sampling time: set a sampling time into one of the */
173 /* common sampling time available. */
174 #define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
175 #define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
176 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
177
178 /* Internal mask for ADC analog watchdog: */
179 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
180 /* (concatenation of multiple bits used in different analog watchdogs, */
181 /* (feature of several watchdogs not available on all STM32 series)). */
182 /* - analog watchdog 1: monitored channel defined by number, */
183 /* selection of ADC group (ADC group regular). */
184 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
185 /* selection on groups. */
186
187 /* Internal register offset for ADC analog watchdog channel configuration */
188 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
189 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
190 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
191
192 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
193 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
194 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
195 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
196
197 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
198 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
199
200 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
201 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
202 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
203
204 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
205 in ADC_AWD_CRX_REGOFFSET_MASK */
206
207 /* Internal register offset for ADC analog watchdog threshold configuration */
208 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
209 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
210 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
211 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
212 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
213 in ADC_AWD_TRX_REGOFFSET_MASK */
214 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
215 threshold high: mask of bit */
216 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
217 threshold high: position of bit */
218 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
219 position to perform a shift of 4 ranks */
220 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
221
222
223
224 /* ADC registers bits positions */
225 #define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */
226 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
227 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
228 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
229 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
230 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
231 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
232 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
233 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
234 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
235 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
236 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
237 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
238 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
239 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
240 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
241 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
242 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
243 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
244 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
245 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
246 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
247 #define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
248 #define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
249 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
250
251
252 /* ADC registers bits groups */
253 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
254 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
255 HW property "rs": Software can read as well as set this bit.
256 Writing '0' has no effect on the bit value. */
257
258
259 /* ADC internal channels related definitions */
260 /* Internal voltage reference VrefInt */
261 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of
262 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
263 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
264 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value
265 with which VrefInt has been calibrated in production
266 (tolerance: +-10 mV) (unit: mV). */
267 /* Temperature sensor */
268 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G0,
269 temperature sensor ADC raw data acquired at temperature 30 DegC
270 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
271 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G0,
272 temperature sensor ADC raw data acquired at temperature 130 DegC
273 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
274 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor
275 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
276 (tolerance: +-5 DegC) (unit: DegC). */
277 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor
278 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
279 (tolerance: +-5 DegC) (unit: DegC). */
280 #define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) value
281 with which temperature sensor has been calibrated in production
282 (tolerance: +-10 mV) (unit: mV). */
283
284 /**
285 * @}
286 */
287
288
289 /* Private macros ------------------------------------------------------------*/
290 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
291 * @{
292 */
293
294 /**
295 * @brief Driver macro reserved for internal use: set a pointer to
296 * a register from a register basis from which an offset
297 * is applied.
298 * @param __REG__ Register basis from which the offset is applied.
299 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
300 * @retval Pointer to register address
301 */
302 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
303 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
304
305 /**
306 * @}
307 */
308
309
310 /* Exported types ------------------------------------------------------------*/
311 #if defined(USE_FULL_LL_DRIVER)
312 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
313 * @{
314 */
315
316 /**
317 * @brief Structure definition of some features of ADC common parameters
318 * and multimode
319 * (all ADC instances belonging to the same ADC common instance).
320 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
321 * is conditioned to ADC instances state (all ADC instances
322 * sharing the same ADC common instance):
323 * All ADC instances sharing the same ADC common instance must be
324 * disabled.
325 */
326 typedef struct
327 {
328 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
329 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
330 This feature can be modified afterwards using unitary function
331 @ref LL_ADC_SetCommonClock(). */
332
333 } LL_ADC_CommonInitTypeDef;
334
335 /**
336 * @brief Structure definition of some features of ADC instance.
337 * @note These parameters have an impact on ADC scope: ADC instance.
338 * Refer to corresponding unitary functions into
339 * @ref ADC_LL_EF_Configuration_ADC_Instance .
340 * @note The setting of these parameters by function @ref LL_ADC_Init()
341 * is conditioned to ADC state:
342 * ADC instance must be disabled.
343 * This condition is applied to all ADC features, for efficiency
344 * and compatibility over all STM32 series. However, the different
345 * features can be set under different ADC state conditions
346 * (setting possible with ADC enabled without conversion on going,
347 * ADC enabled with conversion on going, ...)
348 * Each feature can be updated afterwards with a unitary function
349 * and potentially with ADC in a different state than disabled,
350 * refer to description of each function for setting
351 * conditioned to ADC state.
352 */
353 typedef struct
354 {
355 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
356 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
357 @note On this STM32 series, this parameter has some clock ratio constraints:
358 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled
359 only if PCLK has a 50% duty clock cycle (APB prescaler configured
360 inside the RCC must be bypassed and the system clock must by 50% duty
361 cycle).
362 This feature can be modified afterwards using unitary function
363 @ref LL_ADC_SetClock().
364 For more details, refer to description of this function. */
365
366 uint32_t Resolution; /*!< Set ADC resolution.
367 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
368 This feature can be modified afterwards using unitary function
369 @ref LL_ADC_SetResolution(). */
370
371 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
372 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
373 This feature can be modified afterwards using unitary function
374 @ref LL_ADC_SetDataAlignment(). */
375
376 uint32_t LowPowerMode; /*!< Set ADC low power mode.
377 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
378 This feature can be modified afterwards using unitary function
379 @ref LL_ADC_SetLowPowerMode(). */
380
381 } LL_ADC_InitTypeDef;
382
383 /**
384 * @brief Structure definition of some features of ADC group regular.
385 * @note These parameters have an impact on ADC scope: ADC group regular.
386 * Refer to corresponding unitary functions into
387 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
388 * (functions with prefix "REG").
389 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
390 * is conditioned to ADC state:
391 * ADC instance must be disabled.
392 * This condition is applied to all ADC features, for efficiency
393 * and compatibility over all STM32 series. However, the different
394 * features can be set under different ADC state conditions
395 * (setting possible with ADC enabled without conversion on going,
396 * ADC enabled with conversion on going, ...)
397 * Each feature can be updated afterwards with a unitary function
398 * and potentially with ADC in a different state than disabled,
399 * refer to description of each function for setting
400 * conditioned to ADC state.
401 */
402 typedef struct
403 {
404 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
405 from external peripheral (timer event, external interrupt line).
406 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
407 @note On this STM32 series, setting trigger source to external trigger also
408 set trigger polarity to rising edge(default setting for compatibility
409 with some ADC on other STM32 series having this setting set by HW
410 default value).
411 In case of need to modify trigger edge, use function
412 @ref LL_ADC_REG_SetTriggerEdge().
413 This feature can be modified afterwards using unitary function
414 @ref LL_ADC_REG_SetTriggerSource(). */
415
416 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
417 @note This parameter has an effect only if group regular sequencer is set
418 to mode "fully configurable". Refer to function
419 @ref LL_ADC_REG_SetSequencerConfigurable().
420 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
421 This feature can be modified afterwards using unitary function
422 @ref LL_ADC_REG_SetSequencerLength(). */
423
424 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
425 and scan conversions interrupted every selected number of ranks.
426 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
427 @note This parameter has an effect only if group regular sequencer is
428 enabled (depending on the sequencer mode: scan length of 2 ranks or
429 more, or several ADC channels enabled in group regular sequencer.
430 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
431 This feature can be modified afterwards using unitary function
432 @ref LL_ADC_REG_SetSequencerDiscont(). */
433
434 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
435 conversions are performed in single mode (one conversion per trigger) or in
436 continuous mode (after the first trigger, following conversions launched
437 successively automatically).
438 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
439 Note: It is not possible to enable both ADC group regular continuous mode
440 and discontinuous mode.
441 This feature can be modified afterwards using unitary function
442 @ref LL_ADC_REG_SetContinuousMode(). */
443
444 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
445 by DMA, and DMA requests mode.
446 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
447 This feature can be modified afterwards using unitary function
448 @ref LL_ADC_REG_SetDMATransfer(). */
449
450 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
451 data preserved or overwritten.
452 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
453 This feature can be modified afterwards using unitary function
454 @ref LL_ADC_REG_SetOverrun(). */
455
456 } LL_ADC_REG_InitTypeDef;
457
458 /**
459 * @}
460 */
461 #endif /* USE_FULL_LL_DRIVER */
462
463 /* Exported constants --------------------------------------------------------*/
464 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
465 * @{
466 */
467
468 /** @defgroup ADC_LL_EC_FLAG ADC flags
469 * @brief Flags defines which can be used with LL_ADC_ReadReg function
470 * @{
471 */
472 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
473 #define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
474 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
475 conversion */
476 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
477 conversions */
478 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
479 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
480 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
481 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
482 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
483 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
484 /**
485 * @}
486 */
487
488 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
489 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
490 * @{
491 */
492 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
493 #define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
494 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
495 conversion */
496 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
497 conversions */
498 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
499 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
500 phase */
501 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
502 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
503 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
504 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
505 /**
506 * @}
507 */
508
509 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
510 * @{
511 */
512 /* List of ADC registers intended to be used (most commonly) with */
513 /* DMA transfer. */
514 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
515 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
516 (corresponding to register DR) to be used with ADC configured in independent
517 mode. Without DMA transfer, register accessed by LL function
518 @ref LL_ADC_REG_ReadConversionData32() and other
519 functions @ref LL_ADC_REG_ReadConversionDatax() */
520 /**
521 * @}
522 */
523
524 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
525 * @{
526 */
527 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
528 prescaler */
529 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
530 prescaler division by 2. Setting common to ADC instances of ADC common
531 group, applied ADC instance wise to each instance clock set to clock source
532 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
533 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
534 prescaler division by 4. Setting common to ADC instances of ADC common
535 group, applied ADC instance wise to each instance clock set to clock source
536 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
537 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
538 prescaler division by 6. Setting common to ADC instances of ADC common
539 group, applied ADC instance wise to each instance clock set to clock source
540 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
541 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
542 prescaler division by 8. Setting common to ADC instances of ADC common
543 group, applied ADC instance wise to each instance clock set to clock source
544 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
545 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
546 prescaler division by 10. Setting common to ADC instances of ADC common
547 group, applied ADC instance wise to each instance clock set to clock source
548 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
549 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
550 prescaler division by 12. Setting common to ADC instances of ADC common
551 group, applied ADC instance wise to each instance clock set to clock source
552 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
553 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
554 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
555 prescaler division by 16. Setting common to ADC instances of ADC common
556 group, applied ADC instance wise to each instance clock set to clock source
557 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
558 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
559 prescaler division by 32. Setting common to ADC instances of ADC common
560 group, applied ADC instance wise to each instance clock set to clock source
561 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
562 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
563 prescaler division by 64. Setting common to ADC instances of ADC common
564 group, applied ADC instance wise to each instance clock set to clock source
565 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
566 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
567 prescaler division by 128. Setting common to ADC instances of ADC common
568 group, applied ADC instance wise to each instance clock set to clock source
569 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
570 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
571 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
572 prescaler division by 256. Setting common to ADC instances of ADC common
573 group, applied ADC instance wise to each instance clock set to clock source
574 asynchronous (refer to function @ref LL_ADC_SetClock() ). */
575 /**
576 * @}
577 */
578
579 /** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode
580 * @{
581 */
582 #define LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL) /*!< ADC clock mode to high frequency.
583 On STM32G0, ADC clock frequency above 3.5MHz. */
584 #define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN) /*!< ADC clock mode to low frequency.
585 On STM32G0,ADC clock frequency below 3.5MHz. */
586 /**
587 * @}
588 */
589
590 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
591 * @{
592 */
593 /* Note: Other measurement paths to internal channels may be available */
594 /* (connections to other peripherals). */
595 /* If they are not listed below, they do not require any specific */
596 /* path enable. In this case, Access to measurement path is done */
597 /* only by selecting the corresponding ADC internal channel. */
598 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
599 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
600 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
601 temperature sensor */
602 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
603 /**
604 * @}
605 */
606
607 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
608 * @{
609 */
610 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock
611 divided by 4 */
612 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
613 divided by 2 */
614 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 \
615 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
616 not divided */
617 #define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock
618 prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
619 /**
620 * @}
621 */
622
623 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
624 * @{
625 */
626 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
627 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
628 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
629 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
630 /**
631 * @}
632 */
633
634 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
635 * @{
636 */
637 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
638 (alignment on data register LSB bit 0)*/
639 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
640 (alignment on data register MSB bit 15)*/
641 /**
642 * @}
643 */
644
645 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
646 * @{
647 */
648 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
649 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power
650 mode, ADC conversions are performed only when necessary
651 (when previous ADC conversion data is read).
652 See description with function @ref LL_ADC_SetLowPowerMode(). */
653 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC
654 automatically powers-off after a ADC conversion and automatically wakes up
655 when a new ADC conversion is triggered (with startup time between trigger
656 and start of sampling). See description with function
657 @ref LL_ADC_SetLowPowerMode(). */
658 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait
659 and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
660 /**
661 * @}
662 */
663
664 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
665 * @{
666 */
667 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency.
668 Note: ADC trigger frequency mode must be set to low frequency when a duration
669 is exceeded before ADC conversion start trigger event (between ADC enable
670 and ADC conversion start trigger event or between two ADC conversion start
671 trigger event).
672 Duration value: Refer to device datasheet, parameter "tIdle". */
673 #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency.
674 Note: ADC trigger frequency mode must be set to low frequency when a duration
675 is exceeded before ADC conversion start trigger event (between ADC enable
676 and ADC conversion start trigger event or between two ADC conversion start
677 trigger event).
678 Duration value: Refer to device datasheet, parameter "tIdle". */
679 /**
680 * @}
681 */
682
683 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
684 * @{
685 */
686 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group
687 of channels: sampling time nb 1 */
688 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \
689 | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group
690 of channels: sampling time nb 2 */
691 /**
692 * @}
693 */
694
695 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
696 * @{
697 */
698 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
699 /**
700 * @}
701 */
702
703 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
704 * @{
705 */
706 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \
707 | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */
708 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \
709 | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */
710 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \
711 | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */
712 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \
713 | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */
714 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \
715 | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */
716 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \
717 | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */
718 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \
719 | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */
720 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \
721 | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */
722 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \
723 | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */
724 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \
725 | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */
726 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \
727 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
728 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \
729 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
730 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \
731 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
732 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \
733 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
734 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \
735 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
736 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \
737 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
738 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \
739 | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
740 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \
741 | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
742 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \
743 | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
744 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
745 connected to VrefInt: Internal voltage reference. */
746 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
747 connected to Temperature sensor. */
748 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
749 connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/3
750 to have channel voltage always below Vdda. */
751 /**
752 * @}
753 */
754
755 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
756 * @{
757 */
758 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
759 conversion trigger internal: SW start. */
760 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
761 conversion trigger from external peripheral: TIM1 TRGO.
762 Trigger edge set to rising edge (default setting). */
763 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
764 conversion trigger from external peripheral: TIM1 channel 4 event
765 (capture compare: input capture or output capture).
766 Trigger edge set to rising edge (default setting). */
767 #if defined(TIM2)
768 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1\
769 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
770 conversion trigger from external peripheral: TIM2 TRGO.
771 Trigger edge set to rising edge (default setting). */
772 #endif /* TIM2 */
773 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | \
774 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
775 conversion trigger from external peripheral: TIM3 TRGO.
776 Trigger edge set to rising edge (default setting). */
777 #if defined(TIM4)
778 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | \
779 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
780 conversion trigger from external peripheral: TIM4 TRGO.
781 Trigger edge set to rising edge (default setting). */
782 #endif /* TIM4 */
783 #if defined(TIM6)
784 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | \
785 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
786 conversion trigger from external peripheral: TIM6 TRGO.
787 Trigger edge set to rising edge (default setting). */
788 #endif /* TIM6 */
789 #if defined(TIM15)
790 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
791 conversion trigger from external peripheral: TIM15 TRGO.
792 Trigger edge set to rising edge (default setting). */
793 #endif /* TIM15 */
794 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | \
795 ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
796 conversion trigger from external peripheral: external interrupt line 11.
797 Trigger edge set to rising edge (default setting). */
798 /**
799 * @}
800 */
801
802 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
803 * @{
804 */
805 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
806 trigger polarity set to rising edge */
807 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion
808 trigger polarity set to falling edge */
809 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
810 trigger polarity set to both rising and falling edges */
811 /**
812 * @}
813 */
814
815 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
816 * @{
817 */
818 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
819 one conversion per trigger */
820 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode:
821 after the first trigger, following conversions launched successively
822 automatically */
823 /**
824 * @}
825 */
826
827 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
828 * @{
829 */
830 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
831 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA,
832 in limited mode (one shot mode): DMA transfer requests are stopped when
833 number of DMA data transfers (number of ADC conversions) is reached.
834 This ADC mode is intended to be used with DMA mode non-circular. */
835 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are
836 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
837 whatever number of DMA data transferred (number of ADC conversions).
838 This ADC mode is intended to be used with DMA mode circular. */
839 /**
840 * @}
841 */
842
843 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
844 * @{
845 */
846 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
847 data preserved */
848 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
849 data overwritten */
850 /**
851 * @}
852 */
853
854 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
855 * @{
856 */
857 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable:
858 sequencer length and each rank affectation to a channel are fixed
859 by channel HW number. Refer to description of function
860 @ref LL_ADC_REG_SetSequencerChannels(). */
861 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable:
862 sequencer length and each rank affectation to a channel are configurable.
863 Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
864 /**
865 * @}
866 */
867
868 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
869 * @{
870 */
871 #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable
872 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
873 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable
874 with 2 ranks in the sequence */
875 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable
876 with 3 ranks in the sequence */
877 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable
878 with 4 ranks in the sequence */
879 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable
880 with 5 ranks in the sequence */
881 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable
882 with 6 ranks in the sequence */
883 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable
884 with 7 ranks in the sequence */
885 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable
886 with 8 ranks in the sequence */
887 /**
888 * @}
889 */
890
891 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
892 * @{
893 */
894 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if
895 sequencer set to mode not fully configurable, refer to function
896 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
897 direction forward: from lowest channel number to highest channel number
898 (scan of all ranks, ADC conversion of ranks with channels enabled in
899 sequencer). On some other STM32 series, this setting is not available
900 and the default scan direction is forward. */
901 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if
902 sequencer set to mode not fully configurable, refer to function
903 @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
904 direction backward: from highest channel number to lowest channel number
905 (scan of all ranks, ADC conversion of ranks with channels enabled in
906 sequencer) */
907 /**
908 * @}
909 */
910
911 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
912 * @{
913 */
914 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
915 discontinuous mode disable */
916 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer
917 discontinuous mode enable with sequence interruption every rank */
918 /**
919 * @}
920 */
921
922 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
923 * @{
924 */
925 #define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */
926 #define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */
927 #define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */
928 #define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */
929 #define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */
930 #define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */
931 #define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */
932 #define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */
933 /**
934 * @}
935 */
936
937 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
938 * @{
939 */
940 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
941 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
942 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
943 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \
944 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
945 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
946 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \
947 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
948 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \
949 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
950 #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 \
951 | ADC_SMPR_SMP1_1 \
952 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
953 /**
954 * @}
955 */
956
957 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
958 * @{
959 */
960 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
961 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
962 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
963 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
964 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
965 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
966 /**
967 * @}
968 */
969
970 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
971 * @{
972 */
973 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
974 disabled */
975 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
976 | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring
977 of all channels, converted by group regular only */
978 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
979 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
980 of ADC channel ADCx_IN0, converted by group regular only */
981 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
982 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
983 of ADC channel ADCx_IN1, converted by group regular only */
984 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
985 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
986 of ADC channel ADCx_IN2, converted by group regular only */
987 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
988 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
989 of ADC channel ADCx_IN3, converted by group regular only */
990 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
991 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
992 of ADC channel ADCx_IN4, converted by group regular only */
993 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
994 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
995 of ADC channel ADCx_IN5, converted by group regular only */
996 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
997 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
998 of ADC channel ADCx_IN6, converted by group regular only */
999 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1000 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1001 of ADC channel ADCx_IN7, converted by group regular only */
1002 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1003 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1004 of ADC channel ADCx_IN8, converted by group regular only */
1005 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1006 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1007 of ADC channel ADCx_IN9, converted by group regular only */
1008 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1009 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1010 of ADC channel ADCx_IN10, converted by group regular only */
1011 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1012 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1013 of ADC channel ADCx_IN11, converted by group regular only */
1014 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1015 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1016 of ADC channel ADCx_IN12, converted by group regular only */
1017 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1018 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1019 of ADC channel ADCx_IN13, converted by group regular only */
1020 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1021 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1022 of ADC channel ADCx_IN14, converted by group regular only */
1023 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1024 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1025 of ADC channel ADCx_IN15, converted by group regular only */
1026 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1027 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1028 of ADC channel ADCx_IN16, converted by group regular only */
1029 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1030 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1031 of ADC channel ADCx_IN17, converted by group regular only */
1032 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1033 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1034 of ADC channel ADCx_IN18, converted by group regular only */
1035 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1036 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1037 of ADC internal channel connected to VrefInt: Internal
1038 voltage reference, converted by group regular only */
1039 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1040 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1041 of ADC internal channel connected to internal temperature sensor,
1042 converted by group regular only */
1043 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1044 | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
1045 of ADC internal channel connected to Vbat/3: Vbat
1046 voltage through a divider ladder of factor 1/3 to have channel voltage always
1047 below Vdda, converted by group regular only */
1048 /**
1049 * @}
1050 */
1051
1052 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1053 * @{
1054 */
1055 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */
1056 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
1057 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \
1058 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low
1059 concatenated into the same data */
1060 /**
1061 * @}
1062 */
1063
1064 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1065 * @{
1066 */
1067 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1068 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of
1069 ADC group regular. Literal suffix "continued" is kept for compatibility
1070 with other STM32 devices featuring ADC group injected, in this case other
1071 oversampling scope parameters are available. */
1072 /**
1073 * @}
1074 */
1075
1076 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1077 * @{
1078 */
1079 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1080 (all conversions of oversampling ratio are done from 1 trigger) */
1081 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous
1082 mode (each conversion of oversampling ratio needs a trigger) */
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1088 * @{
1089 */
1090 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1091 (sum of conversions data computed to result as oversampling conversion data
1092 (before potential shift) */
1093 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1094 (sum of conversions data computed to result as oversampling conversion data
1095 (before potential shift) */
1096 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1097 (sum of conversions data computed to result as oversampling conversion data
1098 (before potential shift) */
1099 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1100 (sum of conversions data computed to result as oversampling conversion data
1101 (before potential shift) */
1102 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1103 (sum of conversions data computed to result as oversampling conversion data
1104 (before potential shift) */
1105 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1106 (sum of conversions data computed to result as oversampling conversion data
1107 (before potential shift) */
1108 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1109 (sum of conversions data computed to result as oversampling conversion data
1110 (before potential shift) */
1111 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1112 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1113 (sum of conversions data computed to result as oversampling conversion data
1114 (before potential shift) */
1115 /**
1116 * @}
1117 */
1118
1119 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1120 * @{
1121 */
1122 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1123 (sum of the ADC conversions data is not divided to result as oversampling
1124 conversion data) */
1125 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1126 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1127 to result as oversampling conversion data) */
1128 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1129 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1130 to result as oversampling conversion data) */
1131 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1132 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1133 to result as oversampling conversion data) */
1134 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1135 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1136 to result as oversampling conversion data) */
1137 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1138 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1139 to result as oversampling conversion data) */
1140 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1141 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1142 to result as oversampling conversion data) */
1143 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1144 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1145 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1146 to result as oversampling conversion data) */
1147 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1148 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1149 to result as oversampling conversion data) */
1150 /**
1151 * @}
1152 */
1153
1154 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
1155 * @{
1156 */
1157 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
1158 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
1159 calibration parameters. This value is coded on 16 bits
1160 (to fit on signed word or double word) and corresponds
1161 to an inconsistent temperature value. */
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1167 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1168 * not timeout values.
1169 * For details on delays values, refer to descriptions in source code
1170 * above each literal definition.
1171 * @{
1172 */
1173
1174 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1175 /* not timeout values. */
1176 /* Timeout values for ADC operations are dependent to device clock */
1177 /* configuration (system clock versus ADC clock), */
1178 /* and therefore must be defined in user application. */
1179 /* Indications for estimation of ADC timeout delays, for this */
1180 /* STM32 series: */
1181 /* - ADC calibration time: maximum delay is 82/fADC. */
1182 /* (refer to device datasheet, parameter "tCAL") */
1183 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1184 /* (refer to device datasheet, parameter "tSTAB") */
1185 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1186 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1187 /* cycles */
1188 /* - ADC conversion time: duration depending on ADC clock and ADC */
1189 /* configuration. */
1190 /* (refer to device reference manual, section "Timing") */
1191
1192 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1193 /* Delay set to maximum value (refer to device datasheet, */
1194 /* parameter "tADCVREG_STUP"). */
1195 /* Unit: us */
1196 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
1197 regulator start-up time) */
1198
1199 /* Delay for internal voltage reference stabilization time. */
1200 /* Delay set to maximum value (refer to device datasheet, */
1201 /* parameter "tstart_vrefint"). */
1202 /* Unit: us */
1203 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
1204 time */
1205
1206 /* Delay for temperature sensor stabilization time. */
1207 /* Literal set to maximum value (refer to device datasheet, */
1208 /* parameter "tSTART"). */
1209 /* Unit: us */
1210 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time
1211 (starting from temperature sensor enable, refer to
1212 @ref LL_ADC_SetCommonPathInternalCh()) */
1213 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
1214 time (starting from ADC enable, refer to
1215 @ref LL_ADC_Enable()) */
1216
1217 /* Delay required between ADC end of calibration and ADC enable. */
1218 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1219 /* are required between ADC end of calibration and ADC enable. */
1220 /* Wait time can be computed in user application by waiting for the */
1221 /* equivalent number of CPU cycles, by taking into account */
1222 /* ratio of CPU clock versus ADC clock prescalers. */
1223 /* Unit: ADC clock cycles. */
1224 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration
1225 and ADC enable */
1226
1227 /**
1228 * @}
1229 */
1230
1231 /**
1232 * @}
1233 */
1234
1235
1236 /* Exported macro ------------------------------------------------------------*/
1237 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1238 * @{
1239 */
1240
1241 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1242 * @{
1243 */
1244
1245 /**
1246 * @brief Write a value in ADC register
1247 * @param __INSTANCE__ ADC Instance
1248 * @param __REG__ Register to be written
1249 * @param __VALUE__ Value to be written in the register
1250 * @retval None
1251 */
1252 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1253
1254 /**
1255 * @brief Read a value in ADC register
1256 * @param __INSTANCE__ ADC Instance
1257 * @param __REG__ Register to be read
1258 * @retval Register value
1259 */
1260 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1261 /**
1262 * @}
1263 */
1264
1265 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1266 * @{
1267 */
1268
1269 /**
1270 * @brief Helper macro to get ADC channel number in decimal format
1271 * from literals LL_ADC_CHANNEL_x.
1272 * @note Example:
1273 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1274 * will return decimal number "4".
1275 * @note The input can be a value from functions where a channel
1276 * number is returned, either defined with number
1277 * or with bitfield (only one bit must be set).
1278 * @param __CHANNEL__ This parameter can be one of the following values:
1279 * @arg @ref LL_ADC_CHANNEL_0
1280 * @arg @ref LL_ADC_CHANNEL_1
1281 * @arg @ref LL_ADC_CHANNEL_2
1282 * @arg @ref LL_ADC_CHANNEL_3
1283 * @arg @ref LL_ADC_CHANNEL_4
1284 * @arg @ref LL_ADC_CHANNEL_5
1285 * @arg @ref LL_ADC_CHANNEL_6
1286 * @arg @ref LL_ADC_CHANNEL_7
1287 * @arg @ref LL_ADC_CHANNEL_8
1288 * @arg @ref LL_ADC_CHANNEL_9
1289 * @arg @ref LL_ADC_CHANNEL_10
1290 * @arg @ref LL_ADC_CHANNEL_11
1291 * @arg @ref LL_ADC_CHANNEL_12
1292 * @arg @ref LL_ADC_CHANNEL_13
1293 * @arg @ref LL_ADC_CHANNEL_14
1294 * @arg @ref LL_ADC_CHANNEL_15 (1)
1295 * @arg @ref LL_ADC_CHANNEL_16 (1)
1296 * @arg @ref LL_ADC_CHANNEL_17 (1)
1297 * @arg @ref LL_ADC_CHANNEL_18
1298 * @arg @ref LL_ADC_CHANNEL_VREFINT
1299 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1300 * @arg @ref LL_ADC_CHANNEL_VBAT
1301 *
1302 * (1) On STM32G0, parameter can be set in ADC group sequencer
1303 * only if sequencer is set in mode "not fully configurable",
1304 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1305 * @retval Value between Min_Data=0 and Max_Data=18
1306 */
1307 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1308 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1309 ( \
1310 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1311 ) \
1312 : \
1313 ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) : \
1314 ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) : \
1315 ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) : \
1316 ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) : \
1317 ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) : \
1318 ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) : \
1319 ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) : \
1320 ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) : \
1321 ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) : \
1322 ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) : \
1323 ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) : \
1324 ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) : \
1325 ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) : \
1326 ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) : \
1327 ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) : \
1328 ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) : \
1329 ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) : \
1330 ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) : \
1331 ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) : \
1332 (0UL)))))))))))))))))))))
1333
1334 /**
1335 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1336 * from number in decimal format.
1337 * @note Example:
1338 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1339 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1340 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1341 * @retval Returned value can be one of the following values:
1342 * @arg @ref LL_ADC_CHANNEL_0
1343 * @arg @ref LL_ADC_CHANNEL_1
1344 * @arg @ref LL_ADC_CHANNEL_2
1345 * @arg @ref LL_ADC_CHANNEL_3
1346 * @arg @ref LL_ADC_CHANNEL_4
1347 * @arg @ref LL_ADC_CHANNEL_5
1348 * @arg @ref LL_ADC_CHANNEL_6
1349 * @arg @ref LL_ADC_CHANNEL_7
1350 * @arg @ref LL_ADC_CHANNEL_8
1351 * @arg @ref LL_ADC_CHANNEL_9
1352 * @arg @ref LL_ADC_CHANNEL_10
1353 * @arg @ref LL_ADC_CHANNEL_11
1354 * @arg @ref LL_ADC_CHANNEL_12
1355 * @arg @ref LL_ADC_CHANNEL_13
1356 * @arg @ref LL_ADC_CHANNEL_14
1357 * @arg @ref LL_ADC_CHANNEL_15 (1)
1358 * @arg @ref LL_ADC_CHANNEL_16 (1)
1359 * @arg @ref LL_ADC_CHANNEL_17 (1)
1360 * @arg @ref LL_ADC_CHANNEL_18
1361 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
1362 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
1363 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
1364 *
1365 * (1) On STM32G0, parameter can be set in ADC group sequencer
1366 * only if sequencer is set in mode "not fully configurable",
1367 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1368 * (2) For ADC channel read back from ADC register,
1369 * comparison with internal channel parameter to be done
1370 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1371 */
1372 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1373 (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1374 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
1375
1376 /**
1377 * @brief Helper macro to determine whether the selected channel
1378 * corresponds to literal definitions of driver.
1379 * @note The different literal definitions of ADC channels are:
1380 * - ADC internal channel:
1381 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1382 * - ADC external channel (channel connected to a GPIO pin):
1383 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1384 * @note The channel parameter must be a value defined from literal
1385 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1386 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1387 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1388 * must not be a value from functions where a channel number is
1389 * returned from ADC registers,
1390 * because internal and external channels share the same channel
1391 * number in ADC registers. The differentiation is made only with
1392 * parameters definitions of driver.
1393 * @param __CHANNEL__ This parameter can be one of the following values:
1394 * @arg @ref LL_ADC_CHANNEL_0
1395 * @arg @ref LL_ADC_CHANNEL_1
1396 * @arg @ref LL_ADC_CHANNEL_2
1397 * @arg @ref LL_ADC_CHANNEL_3
1398 * @arg @ref LL_ADC_CHANNEL_4
1399 * @arg @ref LL_ADC_CHANNEL_5
1400 * @arg @ref LL_ADC_CHANNEL_6
1401 * @arg @ref LL_ADC_CHANNEL_7
1402 * @arg @ref LL_ADC_CHANNEL_8
1403 * @arg @ref LL_ADC_CHANNEL_9
1404 * @arg @ref LL_ADC_CHANNEL_10
1405 * @arg @ref LL_ADC_CHANNEL_11
1406 * @arg @ref LL_ADC_CHANNEL_12
1407 * @arg @ref LL_ADC_CHANNEL_13
1408 * @arg @ref LL_ADC_CHANNEL_14
1409 * @arg @ref LL_ADC_CHANNEL_15 (1)
1410 * @arg @ref LL_ADC_CHANNEL_16 (1)
1411 * @arg @ref LL_ADC_CHANNEL_17 (1)
1412 * @arg @ref LL_ADC_CHANNEL_18
1413 * @arg @ref LL_ADC_CHANNEL_VREFINT
1414 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1415 * @arg @ref LL_ADC_CHANNEL_VBAT
1416 *
1417 * (1) On STM32G0, parameter can be set in ADC group sequencer
1418 * only if sequencer is set in mode "not fully configurable",
1419 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1420 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
1421 connected to a GPIO pin).
1422 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1423 */
1424 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1425 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1426
1427 /**
1428 * @brief Helper macro to convert a channel defined from parameter
1429 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1430 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1431 * to its equivalent parameter definition of a ADC external channel
1432 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1433 * @note The channel parameter can be, additionally to a value
1434 * defined from parameter definition of a ADC internal channel
1435 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1436 * a value defined from parameter definition of
1437 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1438 * or a value from functions where a channel number is returned
1439 * from ADC registers.
1440 * @param __CHANNEL__ This parameter can be one of the following values:
1441 * @arg @ref LL_ADC_CHANNEL_0
1442 * @arg @ref LL_ADC_CHANNEL_1
1443 * @arg @ref LL_ADC_CHANNEL_2
1444 * @arg @ref LL_ADC_CHANNEL_3
1445 * @arg @ref LL_ADC_CHANNEL_4
1446 * @arg @ref LL_ADC_CHANNEL_5
1447 * @arg @ref LL_ADC_CHANNEL_6
1448 * @arg @ref LL_ADC_CHANNEL_7
1449 * @arg @ref LL_ADC_CHANNEL_8
1450 * @arg @ref LL_ADC_CHANNEL_9
1451 * @arg @ref LL_ADC_CHANNEL_10
1452 * @arg @ref LL_ADC_CHANNEL_11
1453 * @arg @ref LL_ADC_CHANNEL_12
1454 * @arg @ref LL_ADC_CHANNEL_13
1455 * @arg @ref LL_ADC_CHANNEL_14
1456 * @arg @ref LL_ADC_CHANNEL_15 (1)
1457 * @arg @ref LL_ADC_CHANNEL_16 (1)
1458 * @arg @ref LL_ADC_CHANNEL_17 (1)
1459 * @arg @ref LL_ADC_CHANNEL_18
1460 * @arg @ref LL_ADC_CHANNEL_VREFINT
1461 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1462 * @arg @ref LL_ADC_CHANNEL_VBAT
1463 *
1464 * (1) On STM32G0, parameter can be set in ADC group sequencer
1465 * only if sequencer is set in mode "not fully configurable",
1466 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1467 * @retval Returned value can be one of the following values:
1468 * @arg @ref LL_ADC_CHANNEL_0
1469 * @arg @ref LL_ADC_CHANNEL_1
1470 * @arg @ref LL_ADC_CHANNEL_2
1471 * @arg @ref LL_ADC_CHANNEL_3
1472 * @arg @ref LL_ADC_CHANNEL_4
1473 * @arg @ref LL_ADC_CHANNEL_5
1474 * @arg @ref LL_ADC_CHANNEL_6
1475 * @arg @ref LL_ADC_CHANNEL_7
1476 * @arg @ref LL_ADC_CHANNEL_8
1477 * @arg @ref LL_ADC_CHANNEL_9
1478 * @arg @ref LL_ADC_CHANNEL_10
1479 * @arg @ref LL_ADC_CHANNEL_11
1480 * @arg @ref LL_ADC_CHANNEL_12
1481 * @arg @ref LL_ADC_CHANNEL_13
1482 * @arg @ref LL_ADC_CHANNEL_14
1483 * @arg @ref LL_ADC_CHANNEL_15
1484 * @arg @ref LL_ADC_CHANNEL_16
1485 * @arg @ref LL_ADC_CHANNEL_17
1486 * @arg @ref LL_ADC_CHANNEL_18
1487 */
1488 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1489 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1490
1491 /**
1492 * @brief Helper macro to determine whether the internal channel
1493 * selected is available on the ADC instance selected.
1494 * @note The channel parameter must be a value defined from parameter
1495 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1496 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1497 * must not be a value defined from parameter definition of
1498 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1499 * or a value from functions where a channel number is
1500 * returned from ADC registers,
1501 * because internal and external channels share the same channel
1502 * number in ADC registers. The differentiation is made only with
1503 * parameters definitions of driver.
1504 * @param __ADC_INSTANCE__ ADC instance
1505 * @param __CHANNEL__ This parameter can be one of the following values:
1506 * @arg @ref LL_ADC_CHANNEL_VREFINT
1507 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1508 * @arg @ref LL_ADC_CHANNEL_VBAT
1509 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1510 * Value "1" if the internal channel selected is available on the ADC instance selected.
1511 */
1512 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1513 (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1514 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1515 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT))
1516
1517 /**
1518 * @brief Helper macro to define ADC analog watchdog parameter:
1519 * define a single channel to monitor with analog watchdog
1520 * from sequencer channel and groups definition.
1521 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1522 * Example:
1523 * LL_ADC_SetAnalogWDMonitChannels(
1524 * ADC1, LL_ADC_AWD1,
1525 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1526 * @param __CHANNEL__ This parameter can be one of the following values:
1527 * @arg @ref LL_ADC_CHANNEL_0
1528 * @arg @ref LL_ADC_CHANNEL_1
1529 * @arg @ref LL_ADC_CHANNEL_2
1530 * @arg @ref LL_ADC_CHANNEL_3
1531 * @arg @ref LL_ADC_CHANNEL_4
1532 * @arg @ref LL_ADC_CHANNEL_5
1533 * @arg @ref LL_ADC_CHANNEL_6
1534 * @arg @ref LL_ADC_CHANNEL_7
1535 * @arg @ref LL_ADC_CHANNEL_8
1536 * @arg @ref LL_ADC_CHANNEL_9
1537 * @arg @ref LL_ADC_CHANNEL_10
1538 * @arg @ref LL_ADC_CHANNEL_11
1539 * @arg @ref LL_ADC_CHANNEL_12
1540 * @arg @ref LL_ADC_CHANNEL_13
1541 * @arg @ref LL_ADC_CHANNEL_14
1542 * @arg @ref LL_ADC_CHANNEL_15 (1)
1543 * @arg @ref LL_ADC_CHANNEL_16 (1)
1544 * @arg @ref LL_ADC_CHANNEL_17 (1)
1545 * @arg @ref LL_ADC_CHANNEL_18
1546 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
1547 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
1548 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
1549 *
1550 * (1) On STM32G0, parameter can be set in ADC group sequencer
1551 * only if sequencer is set in mode "not fully configurable",
1552 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1553 * (2) For ADC channel read back from ADC register,
1554 * comparison with internal channel parameter to be done
1555 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1556 * @param __GROUP__ This parameter can be one of the following values:
1557 * @arg @ref LL_ADC_GROUP_REGULAR
1558 * @retval Returned value can be one of the following values:
1559 * @arg @ref LL_ADC_AWD_DISABLE
1560 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1561 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1562 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1563 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1564 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1565 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1566 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1567 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1568 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1569 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1570 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1571 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1572 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1573 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1574 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1575 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1576 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1577 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1578 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1579 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1580 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1581 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1582 * @arg @ref LL_ADC_AWD_CH_VBAT_REG
1583 */
1584 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1585 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
1586
1587 /**
1588 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1589 * or low in function of ADC resolution, when ADC resolution is
1590 * different of 12 bits.
1591 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1592 * or @ref LL_ADC_SetAnalogWDThresholds().
1593 * Example, with a ADC resolution of 8 bits, to set the value of
1594 * analog watchdog threshold high (on 8 bits):
1595 * LL_ADC_SetAnalogWDThresholds
1596 * (< ADCx param >,
1597 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1598 * );
1599 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1600 * @arg @ref LL_ADC_RESOLUTION_12B
1601 * @arg @ref LL_ADC_RESOLUTION_10B
1602 * @arg @ref LL_ADC_RESOLUTION_8B
1603 * @arg @ref LL_ADC_RESOLUTION_6B
1604 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1605 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1606 */
1607 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1608 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1609
1610 /**
1611 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1612 * or low in function of ADC resolution, when ADC resolution is
1613 * different of 12 bits.
1614 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1615 * Example, with a ADC resolution of 8 bits, to get the value of
1616 * analog watchdog threshold high (on 8 bits):
1617 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1618 * (LL_ADC_RESOLUTION_8B,
1619 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1620 * );
1621 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1622 * @arg @ref LL_ADC_RESOLUTION_12B
1623 * @arg @ref LL_ADC_RESOLUTION_10B
1624 * @arg @ref LL_ADC_RESOLUTION_8B
1625 * @arg @ref LL_ADC_RESOLUTION_6B
1626 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1627 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1628 */
1629 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1630 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1631
1632 /**
1633 * @brief Helper macro to get the ADC analog watchdog threshold high
1634 * or low from raw value containing both thresholds concatenated.
1635 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1636 * Example, to get analog watchdog threshold high from the register raw value:
1637 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1638 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1639 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1640 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1641 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1642 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1643 */
1644 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1645 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
1646 & LL_ADC_AWD_THRESHOLD_LOW)
1647
1648 /**
1649 * @brief Helper macro to select the ADC common instance
1650 * to which is belonging the selected ADC instance.
1651 * @note ADC common register instance can be used for:
1652 * - Set parameters common to several ADC instances
1653 * - Multimode (for devices with several ADC instances)
1654 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1655 * @param __ADCx__ ADC instance
1656 * @retval ADC common register instance
1657 */
1658 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1659 (ADC1_COMMON)
1660
1661 /**
1662 * @brief Helper macro to check if all ADC instances sharing the same
1663 * ADC common instance are disabled.
1664 * @note This check is required by functions with setting conditioned to
1665 * ADC state:
1666 * All ADC instances of the ADC common group must be disabled.
1667 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1668 * @note On devices with only 1 ADC common instance, parameter of this macro
1669 * is useless and can be ignored (parameter kept for compatibility
1670 * with devices featuring several ADC common instances).
1671 * @param __ADCXY_COMMON__ ADC common instance
1672 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1673 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1674 * are disabled.
1675 * Value "1" if at least one ADC instance sharing the same ADC common instance
1676 * is enabled.
1677 */
1678 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1679 LL_ADC_IsEnabled(ADC1)
1680
1681 /**
1682 * @brief Helper macro to define the ADC conversion data full-scale digital
1683 * value corresponding to the selected ADC resolution.
1684 * @note ADC conversion data full-scale corresponds to voltage range
1685 * determined by analog voltage references Vref+ and Vref-
1686 * (refer to reference manual).
1687 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1688 * @arg @ref LL_ADC_RESOLUTION_12B
1689 * @arg @ref LL_ADC_RESOLUTION_10B
1690 * @arg @ref LL_ADC_RESOLUTION_8B
1691 * @arg @ref LL_ADC_RESOLUTION_6B
1692 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
1693 */
1694 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1695 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
1696
1697 /**
1698 * @brief Helper macro to convert the ADC conversion data from
1699 * a resolution to another resolution.
1700 * @param __DATA__ ADC conversion data to be converted
1701 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
1702 * This parameter can be one of the following values:
1703 * @arg @ref LL_ADC_RESOLUTION_12B
1704 * @arg @ref LL_ADC_RESOLUTION_10B
1705 * @arg @ref LL_ADC_RESOLUTION_8B
1706 * @arg @ref LL_ADC_RESOLUTION_6B
1707 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1708 * This parameter can be one of the following values:
1709 * @arg @ref LL_ADC_RESOLUTION_12B
1710 * @arg @ref LL_ADC_RESOLUTION_10B
1711 * @arg @ref LL_ADC_RESOLUTION_8B
1712 * @arg @ref LL_ADC_RESOLUTION_6B
1713 * @retval ADC conversion data to the requested resolution
1714 */
1715 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1716 __ADC_RESOLUTION_CURRENT__,\
1717 __ADC_RESOLUTION_TARGET__) \
1718 (((__DATA__) \
1719 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) \
1720 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)) \
1721 )
1722
1723 /**
1724 * @brief Helper macro to calculate the voltage (unit: mVolt)
1725 * corresponding to a ADC conversion data (unit: digital value).
1726 * @note Analog reference voltage (Vref+) must be either known from
1727 * user board environment or can be calculated using ADC measurement
1728 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1729 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1730 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1731 * (unit: digital value).
1732 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1733 * @arg @ref LL_ADC_RESOLUTION_12B
1734 * @arg @ref LL_ADC_RESOLUTION_10B
1735 * @arg @ref LL_ADC_RESOLUTION_8B
1736 * @arg @ref LL_ADC_RESOLUTION_6B
1737 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1738 */
1739 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1740 __ADC_DATA__,\
1741 __ADC_RESOLUTION__) \
1742 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1743 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1744 )
1745
1746 /**
1747 * @brief Helper macro to calculate analog reference voltage (Vref+)
1748 * (unit: mVolt) from ADC conversion data of internal voltage
1749 * reference VrefInt.
1750 * @note Computation is using VrefInt calibration value
1751 * stored in system memory for each device during production.
1752 * @note This voltage depends on user board environment: voltage level
1753 * connected to pin Vref+.
1754 * On devices with small package, the pin Vref+ is not present
1755 * and internally bonded to pin Vdda.
1756 * @note On this STM32 series, calibration data of internal voltage reference
1757 * VrefInt corresponds to a resolution of 12 bits,
1758 * this is the recommended ADC resolution to convert voltage of
1759 * internal voltage reference VrefInt.
1760 * Otherwise, this macro performs the processing to scale
1761 * ADC conversion data to 12 bits.
1762 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1763 * of internal voltage reference VrefInt (unit: digital value).
1764 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1765 * @arg @ref LL_ADC_RESOLUTION_12B
1766 * @arg @ref LL_ADC_RESOLUTION_10B
1767 * @arg @ref LL_ADC_RESOLUTION_8B
1768 * @arg @ref LL_ADC_RESOLUTION_6B
1769 * @retval Analog reference voltage (unit: mV)
1770 */
1771 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1772 __ADC_RESOLUTION__) \
1773 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1774 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1775 (__ADC_RESOLUTION__), \
1776 LL_ADC_RESOLUTION_12B) \
1777 )
1778
1779 /**
1780 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1781 * from ADC conversion data of internal temperature sensor.
1782 * @note Computation is using temperature sensor calibration values
1783 * stored in system memory for each device during production.
1784 * @note Calculation formula:
1785 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1786 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1787 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1788 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1789 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1790 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1791 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1792 * TEMP_DEGC_CAL1 (calibrated in factory)
1793 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1794 * TEMP_DEGC_CAL2 (calibrated in factory)
1795 * Caution: Calculation relevancy under reserve that calibration
1796 * parameters are correct (address and data).
1797 * To calculate temperature using temperature sensor
1798 * datasheet typical values (generic values less, therefore
1799 * less accurate than calibrated values),
1800 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1801 * @note As calculation input, the analog reference voltage (Vref+) must be
1802 * defined as it impacts the ADC LSB equivalent voltage.
1803 * @note Analog reference voltage (Vref+) must be either known from
1804 * user board environment or can be calculated using ADC measurement
1805 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1806 * @note On this STM32 series, calibration data of temperature sensor
1807 * corresponds to a resolution of 12 bits,
1808 * this is the recommended ADC resolution to convert voltage of
1809 * temperature sensor.
1810 * Otherwise, this macro performs the processing to scale
1811 * ADC conversion data to 12 bits.
1812 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1813 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1814 * temperature sensor (unit: digital value).
1815 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1816 * sensor voltage has been measured.
1817 * This parameter can be one of the following values:
1818 * @arg @ref LL_ADC_RESOLUTION_12B
1819 * @arg @ref LL_ADC_RESOLUTION_10B
1820 * @arg @ref LL_ADC_RESOLUTION_8B
1821 * @arg @ref LL_ADC_RESOLUTION_6B
1822 * @retval Temperature (unit: degree Celsius)
1823 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
1824 */
1825 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1826 __TEMPSENSOR_ADC_DATA__,\
1827 __ADC_RESOLUTION__)\
1828 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
1829 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1830 (__ADC_RESOLUTION__), \
1831 LL_ADC_RESOLUTION_12B) \
1832 * (__VREFANALOG_VOLTAGE__)) \
1833 / TEMPSENSOR_CAL_VREFANALOG) \
1834 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1835 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1836 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1837 ) + TEMPSENSOR_CAL1_TEMP \
1838 ) \
1839 : \
1840 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
1841 )
1842
1843 /**
1844 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1845 * from ADC conversion data of internal temperature sensor.
1846 * @note Computation is using temperature sensor typical values
1847 * (refer to device datasheet).
1848 * @note Calculation formula:
1849 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1850 * / Avg_Slope + CALx_TEMP
1851 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1852 * (unit: digital value)
1853 * Avg_Slope = temperature sensor slope
1854 * (unit: uV/Degree Celsius)
1855 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1856 * temperature CALx_TEMP (unit: mV)
1857 * Caution: Calculation relevancy under reserve the temperature sensor
1858 * of the current device has characteristics in line with
1859 * datasheet typical values.
1860 * If temperature sensor calibration values are available on
1861 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1862 * temperature calculation will be more accurate using
1863 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1864 * @note As calculation input, the analog reference voltage (Vref+) must be
1865 * defined as it impacts the ADC LSB equivalent voltage.
1866 * @note Analog reference voltage (Vref+) must be either known from
1867 * user board environment or can be calculated using ADC measurement
1868 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1869 * @note ADC measurement data must correspond to a resolution of 12 bits
1870 * (full scale digital value 4095). If not the case, the data must be
1871 * preliminarily rescaled to an equivalent resolution of 12 bits.
1872 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
1873 (unit: uV/DegCelsius).
1874 * On STM32G0, refer to device datasheet parameter "Avg_Slope".
1875 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
1876 (at temperature and Vref+ defined in parameters below) (unit: mV).
1877 * On STM32G0, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
1878 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
1879 (see parameter above) is corresponding (unit: degree Celsius)
1880 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
1881 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1882 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1883 * This parameter can be one of the following values:
1884 * @arg @ref LL_ADC_RESOLUTION_12B
1885 * @arg @ref LL_ADC_RESOLUTION_10B
1886 * @arg @ref LL_ADC_RESOLUTION_8B
1887 * @arg @ref LL_ADC_RESOLUTION_6B
1888 * @retval Temperature (unit: degree Celsius)
1889 */
1890 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1891 __TEMPSENSOR_TYP_CALX_V__,\
1892 __TEMPSENSOR_CALX_TEMP__,\
1893 __VREFANALOG_VOLTAGE__,\
1894 __TEMPSENSOR_ADC_DATA__,\
1895 __ADC_RESOLUTION__) \
1896 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1897 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1898 * 1000UL) \
1899 - \
1900 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1901 * 1000UL) \
1902 ) \
1903 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
1904 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
1905 )
1906
1907 /**
1908 * @}
1909 */
1910
1911 /**
1912 * @}
1913 */
1914
1915
1916 /* Exported functions --------------------------------------------------------*/
1917 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1918 * @{
1919 */
1920
1921 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1922 * @{
1923 */
1924 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1925 /* configuration of ADC instance, groups and multimode (if available): */
1926 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1927
1928 /**
1929 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1930 * ADC register address from ADC instance and a list of ADC registers
1931 * intended to be used (most commonly) with DMA transfer.
1932 * @note These ADC registers are data registers:
1933 * when ADC conversion data is available in ADC data registers,
1934 * ADC generates a DMA transfer request.
1935 * @note This macro is intended to be used with LL DMA driver, refer to
1936 * function "LL_DMA_ConfigAddresses()".
1937 * Example:
1938 * LL_DMA_ConfigAddresses(DMA1,
1939 * LL_DMA_CHANNEL_1,
1940 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1941 * (uint32_t)&< array or variable >,
1942 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1943 * @note For devices with several ADC: in multimode, some devices
1944 * use a different data register outside of ADC instance scope
1945 * (common data register). This macro manages this register difference,
1946 * only ADC instance has to be set as parameter.
1947 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1948 * @param ADCx ADC instance
1949 * @param Register This parameter can be one of the following values:
1950 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1951 * @retval ADC register address
1952 */
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)1953 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
1954 {
1955 /* Prevent unused argument(s) compilation warning */
1956 (void)(Register);
1957
1958 /* Retrieve address of register DR */
1959 return (uint32_t) &(ADCx->DR);
1960 }
1961
1962 /**
1963 * @}
1964 */
1965
1966 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
1967 * ADC instances
1968 * @{
1969 */
1970
1971 /**
1972 * @brief Set parameter common to several ADC: Clock source and prescaler.
1973 * @note On this STM32 series, setting of this feature is conditioned to
1974 * ADC state:
1975 * All ADC instances of the ADC common group must be disabled.
1976 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1977 * ADC instance or by using helper macro helper macro
1978 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1979 * @rmtoll CCR PRESC LL_ADC_SetCommonClock
1980 * @param ADCxy_COMMON ADC common instance
1981 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1982 * @param CommonClock This parameter can be one of the following values:
1983 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1984 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1985 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1986 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1987 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1988 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1989 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1990 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1991 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1992 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1993 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1994 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1995 *
1996 * (1) ADC common clock asynchronous prescaler is applied to
1997 * each ADC instance if the corresponding ADC instance clock
1998 * is set to clock source asynchronous.
1999 * (refer to function @ref LL_ADC_SetClock() ).
2000 * @retval None
2001 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2002 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2003 {
2004 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
2005 }
2006
2007 /**
2008 * @brief Get parameter common to several ADC: Clock source and prescaler.
2009 * @rmtoll CCR PRESC LL_ADC_GetCommonClock
2010 * @param ADCxy_COMMON ADC common instance
2011 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2012 * @retval Returned value can be one of the following values:
2013 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
2014 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
2015 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
2016 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
2017 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
2018 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
2019 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
2020 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
2021 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
2022 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
2023 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
2024 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
2025 *
2026 * (1) ADC common clock asynchronous prescaler is applied to
2027 * each ADC instance if the corresponding ADC instance clock
2028 * is set to clock source asynchronous.
2029 * (refer to function @ref LL_ADC_SetClock() ).
2030 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)2031 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
2032 {
2033 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
2034 }
2035
2036 /**
2037 * @brief Legacy feature, useless on STM32G0 (ADC common clock low frequency
2038 mode is automatically managed by ADC peripheral on STM32G0).
2039 Function kept for legacy purpose.
2040 * @note On this STM32 series, setting of this feature is conditioned to
2041 * ADC state:
2042 * ADC must be disabled or enabled without conversion on going
2043 * on group regular.
2044 * @rmtoll CCR LFMEN LL_ADC_SetCommonFrequencyMode
2045 * @param ADCxy_COMMON ADC common instance
2046 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2047 * @param CommonFrequencyMode This parameter can be one of the following values:
2048 * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
2049 * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
2050 * @retval None
2051 */
LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonFrequencyMode)2052 __STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonFrequencyMode)
2053 {
2054 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, CommonFrequencyMode);
2055 }
2056
2057 /**
2058 * @brief Legacy feature, useless on STM32G0 (ADC common clock low frequency
2059 mode is automatically managed by ADC peripheral on STM32G0).
2060 Function kept for legacy purpose.
2061 * @rmtoll CCR LFMEN LL_ADC_GetCommonFrequencyMode
2062 * @param ADCxy_COMMON ADC common instance
2063 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2064 * @retval Returned value can be one of the following values:
2065 * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
2066 * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
2067 */
LL_ADC_GetCommonFrequencyMode(const ADC_Common_TypeDef * ADCxy_COMMON)2068 __STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(const ADC_Common_TypeDef *ADCxy_COMMON)
2069 {
2070 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN));
2071 }
2072
2073 /**
2074 * @brief Set parameter common to several ADC: measurement path to
2075 * internal channels (VrefInt, temperature sensor, ...).
2076 * Configure all paths (overwrite current configuration).
2077 * @note One or several values can be selected.
2078 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2079 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2080 * The values not selected are removed from configuration.
2081 * @note Stabilization time of measurement path to internal channel:
2082 * After enabling internal paths, before starting ADC conversion,
2083 * a delay is required for internal voltage reference and
2084 * temperature sensor stabilization time.
2085 * Refer to device datasheet.
2086 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2087 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
2088 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
2089 * @note ADC internal channel sampling time constraint:
2090 * For ADC conversion of internal channels,
2091 * a sampling time minimum value is required.
2092 * Refer to device datasheet.
2093 * @note On this STM32 series, setting of this feature is conditioned to
2094 * ADC state:
2095 * All ADC instances of the ADC common group must be disabled.
2096 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2097 * ADC instance or by using helper macro helper macro
2098 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2099 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2100 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2101 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2102 * @param ADCxy_COMMON ADC common instance
2103 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2104 * @param PathInternal This parameter can be a combination of the following values:
2105 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2106 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2107 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2108 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2109 * @retval None
2110 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2111 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2112 {
2113 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2114 }
2115
2116 /**
2117 * @brief Set parameter common to several ADC: measurement path to
2118 * internal channels (VrefInt, temperature sensor, ...).
2119 * Add paths to the current configuration.
2120 * @note One or several values can be selected.
2121 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2122 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2123 * @note Stabilization time of measurement path to internal channel:
2124 * After enabling internal paths, before starting ADC conversion,
2125 * a delay is required for internal voltage reference and
2126 * temperature sensor stabilization time.
2127 * Refer to device datasheet.
2128 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2129 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
2130 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
2131 * @note ADC internal channel sampling time constraint:
2132 * For ADC conversion of internal channels,
2133 * a sampling time minimum value is required.
2134 * Refer to device datasheet.
2135 * @note On this STM32 series, setting of this feature is conditioned to
2136 * ADC state:
2137 * All ADC instances of the ADC common group must be disabled.
2138 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2139 * ADC instance or by using helper macro helper macro
2140 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2141 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2142 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
2143 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
2144 * @param ADCxy_COMMON ADC common instance
2145 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2146 * @param PathInternal This parameter can be a combination of the following values:
2147 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2148 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2149 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2150 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2151 * @retval None
2152 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2153 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2154 {
2155 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2156 }
2157
2158 /**
2159 * @brief Set parameter common to several ADC: measurement path to
2160 * internal channels (VrefInt, temperature sensor, ...).
2161 * Remove paths to the current configuration.
2162 * @note One or several values can be selected.
2163 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2164 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2165 * @note On this STM32 series, setting of this feature is conditioned to
2166 * ADC state:
2167 * All ADC instances of the ADC common group must be disabled.
2168 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2169 * ADC instance or by using helper macro helper macro
2170 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2171 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2172 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
2173 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
2174 * @param ADCxy_COMMON ADC common instance
2175 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2176 * @param PathInternal This parameter can be a combination of the following values:
2177 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2178 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2179 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2180 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2181 * @retval None
2182 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2183 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2184 {
2185 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2186 }
2187
2188 /**
2189 * @brief Get parameter common to several ADC: measurement path to internal
2190 * channels (VrefInt, temperature sensor, ...).
2191 * @note One or several values can be selected.
2192 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2193 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2194 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2195 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2196 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2197 * @param ADCxy_COMMON ADC common instance
2198 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2199 * @retval Returned value can be a combination of the following values:
2200 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2201 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2202 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2203 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2204 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)2205 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
2206 {
2207 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2208 }
2209
2210 /**
2211 * @}
2212 */
2213
2214 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2215 * @{
2216 */
2217
2218 /**
2219 * @brief Set ADC instance clock source and prescaler.
2220 * @note On this STM32 series, setting of this feature is conditioned to
2221 * ADC state:
2222 * ADC must be disabled.
2223 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
2224 * @param ADCx ADC instance
2225 * @param ClockSource This parameter can be one of the following values:
2226 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2227 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2228 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
2229 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
2230 *
2231 * (1) Asynchronous clock prescaler can be configured using
2232 * function @ref LL_ADC_SetCommonClock().\n
2233 * (2) Caution: This parameter has some clock ratio constraints:
2234 * This configuration must be enabled only if PCLK has a 50%
2235 * duty clock cycle (APB prescaler configured inside the RCC
2236 * must be bypassed and the system clock must by 50% duty
2237 * cycle).
2238 * Refer to reference manual.
2239 * @retval None
2240 */
LL_ADC_SetClock(ADC_TypeDef * ADCx,uint32_t ClockSource)2241 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
2242 {
2243 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
2244 }
2245
2246 /**
2247 * @brief Get ADC instance clock source and prescaler.
2248 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
2249 * @param ADCx ADC instance
2250 * @retval Returned value can be one of the following values:
2251 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2252 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2253 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
2254 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
2255 *
2256 * (1) Asynchronous clock prescaler can be retrieved using
2257 * function @ref LL_ADC_GetCommonClock().\n
2258 * (2) Caution: This parameter has some clock ratio constraints:
2259 * This configuration must be enabled only if PCLK has a 50%
2260 * duty clock cycle (APB prescaler configured inside the RCC
2261 * must be bypassed and the system clock must by 50% duty
2262 * cycle).
2263 * Refer to reference manual.
2264 */
LL_ADC_GetClock(const ADC_TypeDef * ADCx)2265 __STATIC_INLINE uint32_t LL_ADC_GetClock(const ADC_TypeDef *ADCx)
2266 {
2267 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
2268 }
2269
2270 /**
2271 * @brief Set ADC calibration factor in the mode single-ended
2272 * or differential (for devices with differential mode available).
2273 * @note This function is intended to set calibration parameters
2274 * without having to perform a new calibration using
2275 * @ref LL_ADC_StartCalibration().
2276 * @note On this STM32 series, setting of this feature is conditioned to
2277 * ADC state:
2278 * ADC must be enabled, without calibration on going, without conversion
2279 * on going on group regular.
2280 * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor
2281 * @param ADCx ADC instance
2282 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2283 * @retval None
2284 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)2285 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
2286 {
2287 MODIFY_REG(ADCx->CALFACT,
2288 ADC_CALFACT_CALFACT,
2289 CalibrationFactor);
2290 }
2291
2292 /**
2293 * @brief Get ADC calibration factor in the mode single-ended
2294 * or differential (for devices with differential mode available).
2295 * @note Calibration factors are set by hardware after performing
2296 * a calibration run using function @ref LL_ADC_StartCalibration().
2297 * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor
2298 * @param ADCx ADC instance
2299 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2300 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx)2301 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx)
2302 {
2303 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
2304 }
2305
2306 /**
2307 * @brief Set ADC resolution.
2308 * Refer to reference manual for alignments formats
2309 * dependencies to ADC resolutions.
2310 * @note On this STM32 series, setting of this feature is conditioned to
2311 * ADC state:
2312 * ADC must be disabled.
2313 * @rmtoll CFGR1 RES LL_ADC_SetResolution
2314 * @param ADCx ADC instance
2315 * @param Resolution This parameter can be one of the following values:
2316 * @arg @ref LL_ADC_RESOLUTION_12B
2317 * @arg @ref LL_ADC_RESOLUTION_10B
2318 * @arg @ref LL_ADC_RESOLUTION_8B
2319 * @arg @ref LL_ADC_RESOLUTION_6B
2320 * @retval None
2321 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2322 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2323 {
2324 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
2325 }
2326
2327 /**
2328 * @brief Get ADC resolution.
2329 * Refer to reference manual for alignments formats
2330 * dependencies to ADC resolutions.
2331 * @rmtoll CFGR1 RES LL_ADC_GetResolution
2332 * @param ADCx ADC instance
2333 * @retval Returned value can be one of the following values:
2334 * @arg @ref LL_ADC_RESOLUTION_12B
2335 * @arg @ref LL_ADC_RESOLUTION_10B
2336 * @arg @ref LL_ADC_RESOLUTION_8B
2337 * @arg @ref LL_ADC_RESOLUTION_6B
2338 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)2339 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
2340 {
2341 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
2342 }
2343
2344 /**
2345 * @brief Set ADC conversion data alignment.
2346 * @note Refer to reference manual for alignments formats
2347 * dependencies to ADC resolutions.
2348 * @note On this STM32 series, setting of this feature is conditioned to
2349 * ADC state:
2350 * ADC must be disabled.
2351 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
2352 * @param ADCx ADC instance
2353 * @param DataAlignment This parameter can be one of the following values:
2354 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2355 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2356 * @retval None
2357 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2358 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2359 {
2360 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
2361 }
2362
2363 /**
2364 * @brief Get ADC conversion data alignment.
2365 * @note Refer to reference manual for alignments formats
2366 * dependencies to ADC resolutions.
2367 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
2368 * @param ADCx ADC instance
2369 * @retval Returned value can be one of the following values:
2370 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2371 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2372 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)2373 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
2374 {
2375 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2376 }
2377
2378 /**
2379 * @brief Set ADC low power mode.
2380 * @note Description of ADC low power modes:
2381 * - ADC low power mode "auto wait": Dynamic low power mode,
2382 * ADC conversions occurrences are limited to the minimum necessary
2383 * in order to reduce power consumption.
2384 * New ADC conversion starts only when the previous
2385 * unitary conversion data (for ADC group regular)
2386 * has been retrieved by user software.
2387 * In the meantime, ADC remains idle: does not performs any
2388 * other conversion.
2389 * This mode allows to automatically adapt the ADC conversions
2390 * triggers to the speed of the software that reads the data.
2391 * Moreover, this avoids risk of overrun for low frequency
2392 * applications.
2393 * How to use this low power mode:
2394 * - It is not recommended to use with interruption or DMA
2395 * since these modes have to clear immediately the EOC flag
2396 * (by CPU to free the IRQ pending event or by DMA).
2397 * Auto wait will work but fort a very short time, discarding
2398 * its intended benefit (except specific case of high load of CPU
2399 * or DMA transfers which can justify usage of auto wait).
2400 * - Do use with polling: 1. Start conversion,
2401 * 2. Later on, when conversion data is needed: poll for end of
2402 * conversion to ensure that conversion is completed and
2403 * retrieve ADC conversion data. This will trig another
2404 * ADC conversion start.
2405 * - ADC low power mode "auto power-off" (feature available on
2406 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2407 * the ADC automatically powers-off after a conversion and
2408 * automatically wakes up when a new conversion is triggered
2409 * (with startup time between trigger and start of sampling).
2410 * This feature can be combined with low power mode "auto wait".
2411 * @note With ADC low power mode "auto wait", the ADC conversion data read
2412 * is corresponding to previous ADC conversion start, independently
2413 * of delay during which ADC was idle.
2414 * Therefore, the ADC conversion data may be outdated: does not
2415 * correspond to the current voltage level on the selected
2416 * ADC channel.
2417 * @note On this STM32 series, setting of this feature is conditioned to
2418 * ADC state:
2419 * ADC must be disabled.
2420 * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
2421 * CFGR1 AUTOFF LL_ADC_SetLowPowerMode
2422 * @param ADCx ADC instance
2423 * @param LowPowerMode This parameter can be one of the following values:
2424 * @arg @ref LL_ADC_LP_MODE_NONE
2425 * @arg @ref LL_ADC_LP_AUTOWAIT
2426 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2427 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2428 * @retval None
2429 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2430 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2431 {
2432 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
2433 }
2434
2435 /**
2436 * @brief Get ADC low power mode:
2437 * @note Description of ADC low power modes:
2438 * - ADC low power mode "auto wait": Dynamic low power mode,
2439 * ADC conversions occurrences are limited to the minimum necessary
2440 * in order to reduce power consumption.
2441 * New ADC conversion starts only when the previous
2442 * unitary conversion data (for ADC group regular)
2443 * has been retrieved by user software.
2444 * In the meantime, ADC remains idle: does not performs any
2445 * other conversion.
2446 * This mode allows to automatically adapt the ADC conversions
2447 * triggers to the speed of the software that reads the data.
2448 * Moreover, this avoids risk of overrun for low frequency
2449 * applications.
2450 * How to use this low power mode:
2451 * - It is not recommended to use with interruption or DMA
2452 * since these modes have to clear immediately the EOC flag
2453 * (by CPU to free the IRQ pending event or by DMA).
2454 * Auto wait will work but fort a very short time, discarding
2455 * its intended benefit (except specific case of high load of CPU
2456 * or DMA transfers which can justify usage of auto wait).
2457 * - Do use with polling: 1. Start conversion,
2458 * 2. Later on, when conversion data is needed: poll for end of
2459 * conversion to ensure that conversion is completed and
2460 * retrieve ADC conversion data. This will trig another
2461 * ADC conversion start.
2462 * - ADC low power mode "auto power-off" (feature available on
2463 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2464 * the ADC automatically powers-off after a conversion and
2465 * automatically wakes up when a new conversion is triggered
2466 * (with startup time between trigger and start of sampling).
2467 * This feature can be combined with low power mode "auto wait".
2468 * @note With ADC low power mode "auto wait", the ADC conversion data read
2469 * is corresponding to previous ADC conversion start, independently
2470 * of delay during which ADC was idle.
2471 * Therefore, the ADC conversion data may be outdated: does not
2472 * correspond to the current voltage level on the selected
2473 * ADC channel.
2474 * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
2475 * CFGR1 AUTOFF LL_ADC_GetLowPowerMode
2476 * @param ADCx ADC instance
2477 * @retval Returned value can be one of the following values:
2478 * @arg @ref LL_ADC_LP_MODE_NONE
2479 * @arg @ref LL_ADC_LP_AUTOWAIT
2480 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2481 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2482 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)2483 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
2484 {
2485 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
2486 }
2487
2488 /**
2489 * @brief Set ADC trigger frequency mode.
2490 * @note ADC trigger frequency mode must be set to low frequency when
2491 * a duration is exceeded before ADC conversion start trigger event
2492 * (between ADC enable and ADC conversion start trigger event
2493 * or between two ADC conversion start trigger event).
2494 * Duration value: Refer to device datasheet, parameter "tIdle".
2495 * @note When ADC trigger frequency mode is set to low frequency,
2496 * some rearm cycles are inserted before performing ADC conversion
2497 * start, inducing a delay of 2 ADC clock cycles.
2498 * @note Usage of ADC trigger frequency mode with ADC low power mode:
2499 * - Low power mode auto wait: Only the first ADC conversion
2500 * start trigger inserts the rearm delay.
2501 * - Low power mode auto power-off: ADC trigger frequency mode
2502 * is discarded.
2503 * @note On this STM32 series, setting of this feature is conditioned to
2504 * ADC state:
2505 * ADC must be disabled.
2506 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
2507 * @param ADCx ADC instance
2508 * @param TriggerFrequencyMode This parameter can be one of the following values:
2509 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2510 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2511 * @retval None
2512 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)2513 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
2514 {
2515 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
2516 }
2517
2518 /**
2519 * @brief Get ADC trigger frequency mode.
2520 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
2521 * @param ADCx ADC instance
2522 * @retval Returned value can be one of the following values:
2523 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2524 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2525 */
LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef * ADCx)2526 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx)
2527 {
2528 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
2529 }
2530
2531 /**
2532 * @brief Set sampling time common to a group of channels.
2533 * @note Unit: ADC clock cycles.
2534 * @note On this STM32 series, sampling time scope is on ADC instance:
2535 * Sampling time common to all channels.
2536 * (on some other STM32 series, sampling time is channel wise)
2537 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2538 * converted:
2539 * sampling time constraints must be respected (sampling time can be
2540 * adjusted in function of ADC clock frequency and sampling time
2541 * setting).
2542 * Refer to device datasheet for timings values (parameters TS_vrefint,
2543 * TS_temp, ...).
2544 * @note Conversion time is the addition of sampling time and processing time.
2545 * On this STM32 series, ADC processing time is:
2546 * - 12.5 ADC clock cycles at ADC resolution 12 bits
2547 * - 10.5 ADC clock cycles at ADC resolution 10 bits
2548 * - 8.5 ADC clock cycles at ADC resolution 8 bits
2549 * - 6.5 ADC clock cycles at ADC resolution 6 bits
2550 * @note In case of ADC conversion of internal channel (VrefInt,
2551 * temperature sensor, ...), a sampling time minimum value
2552 * is required.
2553 * Refer to device datasheet.
2554 * @note On this STM32 series, setting of this feature is conditioned to
2555 * ADC state:
2556 * ADC must be disabled or enabled without conversion on going
2557 * on group regular.
2558 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
2559 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
2560 * @param ADCx ADC instance
2561 * @param SamplingTimeY This parameter can be one of the following values:
2562 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2563 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2564 * @param SamplingTime This parameter can be one of the following values:
2565 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2566 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2567 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2568 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2569 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2570 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2571 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2572 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2573 * @retval None
2574 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)2575 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
2576 uint32_t SamplingTime)
2577 {
2578 MODIFY_REG(ADCx->SMPR,
2579 ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
2580 SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2581 }
2582
2583 /**
2584 * @brief Get sampling time common to a group of channels.
2585 * @note Unit: ADC clock cycles.
2586 * @note On this STM32 series, sampling time scope is on ADC instance:
2587 * Sampling time common to all channels.
2588 * (on some other STM32 series, sampling time is channel wise)
2589 * @note Conversion time is the addition of sampling time and processing time.
2590 * Refer to reference manual for ADC processing time of
2591 * this STM32 series.
2592 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
2593 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
2594 * @param ADCx ADC instance
2595 * @param SamplingTimeY This parameter can be one of the following values:
2596 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2597 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2598 * @retval Returned value can be one of the following values:
2599 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2600 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2601 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2602 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2603 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2604 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2605 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2606 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2607 */
LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef * ADCx,uint32_t SamplingTimeY)2608 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
2609 {
2610 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
2611 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2612 }
2613
2614 /**
2615 * @}
2616 */
2617
2618 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2619 * @{
2620 */
2621
2622 /**
2623 * @brief Set ADC group regular conversion trigger source:
2624 * internal (SW start) or from external peripheral (timer event,
2625 * external interrupt line).
2626 * @note On this STM32 series, setting trigger source to external trigger
2627 * also set trigger polarity to rising edge
2628 * (default setting for compatibility with some ADC on other
2629 * STM32 series having this setting set by HW default value).
2630 * In case of need to modify trigger edge, use
2631 * function @ref LL_ADC_REG_SetTriggerEdge().
2632 * @note On this STM32 series, ADC trigger frequency mode must be set
2633 * in function of frequency of ADC group regular conversion trigger.
2634 * Refer to description of function
2635 * @ref LL_ADC_SetTriggerFrequencyMode().
2636 * @note Availability of parameters of trigger sources from timer
2637 * depends on timers availability on the selected device.
2638 * @note On this STM32 series, setting of this feature is conditioned to
2639 * ADC state:
2640 * ADC must be disabled.
2641 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
2642 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
2643 * @param ADCx ADC instance
2644 * @param TriggerSource This parameter can be one of the following values:
2645 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2646 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2647 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2648 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
2649 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2650 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (1)
2651 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
2652 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2653 *
2654 * (1) On STM32G0, parameter not available on all devices
2655 * @retval None
2656 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2657 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2658 {
2659 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
2660 }
2661
2662 /**
2663 * @brief Get ADC group regular conversion trigger source:
2664 * internal (SW start) or from external peripheral (timer event,
2665 * external interrupt line).
2666 * @note To determine whether group regular trigger source is
2667 * internal (SW start) or external, without detail
2668 * of which peripheral is selected as external trigger,
2669 * (equivalent to
2670 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2671 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2672 * @note Availability of parameters of trigger sources from timer
2673 * depends on timers availability on the selected device.
2674 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
2675 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
2676 * @param ADCx ADC instance
2677 * @retval Returned value can be one of the following values:
2678 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2679 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2680 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2681 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
2682 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2683 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (1)
2684 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
2685 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2686 *
2687 * (1) On STM32G0, parameter not available on all devices
2688 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)2689 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
2690 {
2691 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
2692
2693 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2694 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
2695 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2696
2697 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
2698 /* to match with triggers literals definition. */
2699 return ((trigger_source
2700 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
2701 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
2702 );
2703 }
2704
2705 /**
2706 * @brief Get ADC group regular conversion trigger source internal (SW start)
2707 * or external.
2708 * @note In case of group regular trigger source set to external trigger,
2709 * to determine which peripheral is selected as external trigger,
2710 * use function @ref LL_ADC_REG_GetTriggerSource().
2711 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2712 * @param ADCx ADC instance
2713 * @retval Value "0" if trigger source external trigger
2714 * Value "1" if trigger source SW start.
2715 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)2716 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
2717 {
2718 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
2719 }
2720
2721 /**
2722 * @brief Set ADC group regular conversion trigger polarity.
2723 * @note Applicable only for trigger source set to external trigger.
2724 * @note On this STM32 series, setting of this feature is conditioned to
2725 * ADC state:
2726 * ADC must be disabled.
2727 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
2728 * @param ADCx ADC instance
2729 * @param ExternalTriggerEdge This parameter can be one of the following values:
2730 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2731 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2732 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2733 * @retval None
2734 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)2735 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
2736 {
2737 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
2738 }
2739
2740 /**
2741 * @brief Get ADC group regular conversion trigger polarity.
2742 * @note Applicable only for trigger source set to external trigger.
2743 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
2744 * @param ADCx ADC instance
2745 * @retval Returned value can be one of the following values:
2746 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2747 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2748 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2749 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)2750 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
2751 {
2752 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
2753 }
2754
2755 /**
2756 * @brief Set ADC group regular sequencer configuration flexibility.
2757 * @note On this STM32 series, ADC group regular sequencer both modes
2758 * "fully configurable" or "not fully configurable" are
2759 * available:
2760 * - sequencer configured to fully configurable:
2761 * sequencer length and each rank
2762 * affectation to a channel are configurable.
2763 * Refer to description of function
2764 * @ref LL_ADC_REG_SetSequencerLength().
2765 * - sequencer configured to not fully configurable:
2766 * sequencer length and each rank affectation to a channel
2767 * are fixed by channel HW number.
2768 * Refer to description of function
2769 * @ref LL_ADC_REG_SetSequencerChannels().
2770 * @note On this STM32 series, after modifying sequencer (functions
2771 * @ref LL_ADC_REG_SetSequencerLength()
2772 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2773 * it is mandatory to wait for the assertion of CCRDY flag
2774 * Otherwise, some actions may be ignored.
2775 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2776 * for more details.
2777 * @note On this STM32 series, setting of this feature is conditioned to
2778 * ADC state:
2779 * ADC must be disabled.
2780 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2781 * @param ADCx ADC instance
2782 * @param Configurability This parameter can be one of the following values:
2783 * @arg @ref LL_ADC_REG_SEQ_FIXED
2784 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2785 * @retval None
2786 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)2787 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
2788 {
2789 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
2790 }
2791
2792 /**
2793 * @brief Get ADC group regular sequencer configuration flexibility.
2794 * @note On this STM32 series, ADC group regular sequencer both modes
2795 * "fully configurable" or "not fully configurable" are
2796 * available:
2797 * - sequencer configured to fully configurable:
2798 * sequencer length and each rank
2799 * affectation to a channel are configurable.
2800 * Refer to description of function
2801 * @ref LL_ADC_REG_SetSequencerLength().
2802 * - sequencer configured to not fully configurable:
2803 * sequencer length and each rank affectation to a channel
2804 * are fixed by channel HW number.
2805 * Refer to description of function
2806 * @ref LL_ADC_REG_SetSequencerChannels().
2807 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2808 * @param ADCx ADC instance
2809 * @retval Returned value can be one of the following values:
2810 * @arg @ref LL_ADC_REG_SEQ_FIXED
2811 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2812 */
LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef * ADCx)2813 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx)
2814 {
2815 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
2816 }
2817
2818 /**
2819 * @brief Set ADC group regular sequencer length and scan direction.
2820 * @note Description of ADC group regular sequencer features:
2821 * - For devices with sequencer fully configurable
2822 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2823 * sequencer length and each rank affectation to a channel
2824 * are configurable.
2825 * This function performs configuration of:
2826 * - Sequence length: Number of ranks in the scan sequence.
2827 * - Sequence direction: Unless specified in parameters, sequencer
2828 * scan direction is forward (from rank 1 to rank n).
2829 * Sequencer ranks are selected using
2830 * function "LL_ADC_REG_SetSequencerRanks()".
2831 * - For devices with sequencer not fully configurable
2832 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2833 * sequencer length and each rank affectation to a channel
2834 * are defined by channel number.
2835 * This function performs configuration of:
2836 * - Sequence length: Number of ranks in the scan sequence is
2837 * defined by number of channels set in the sequence,
2838 * rank of each channel is fixed by channel HW number.
2839 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2840 * - Sequence direction: Unless specified in parameters, sequencer
2841 * scan direction is forward (from lowest channel number to
2842 * highest channel number).
2843 * Sequencer ranks are selected using
2844 * function "LL_ADC_REG_SetSequencerChannels()".
2845 * To set scan direction differently, refer to function
2846 * @ref LL_ADC_REG_SetSequencerScanDirection().
2847 * @note On this STM32 series, ADC group regular sequencer both modes
2848 * "fully configurable" or "not fully configurable"
2849 * are available, they can be chosen using
2850 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2851 * @note On this STM32 series, after modifying sequencer (functions
2852 * @ref LL_ADC_REG_SetSequencerLength()
2853 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2854 * it is mandatory to wait for the assertion of CCRDY flag
2855 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2856 * Otherwise, some actions may be ignored.
2857 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2858 * for more details.
2859 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2860 * ADC conversion on only 1 channel.
2861 * @note On this STM32 series, setting of this feature is conditioned to
2862 * ADC state:
2863 * ADC must be disabled or enabled without conversion on going
2864 * on group regular.
2865 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
2866 * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
2867 * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
2868 * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
2869 * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
2870 * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
2871 * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
2872 * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
2873 * @param ADCx ADC instance
2874 * @param SequencerNbRanks This parameter can be one of the following values:
2875 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2876 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2877 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2878 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2879 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2880 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2881 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2882 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2883 * @retval None
2884 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2885 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2886 {
2887 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
2888 }
2889
2890 /**
2891 * @brief Get ADC group regular sequencer length and scan direction.
2892 * @note Description of ADC group regular sequencer features:
2893 * - For devices with sequencer fully configurable
2894 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2895 * sequencer length and each rank affectation to a channel
2896 * are configurable.
2897 * This function retrieves:
2898 * - Sequence length: Number of ranks in the scan sequence.
2899 * - Sequence direction: Unless specified in parameters, sequencer
2900 * scan direction is forward (from rank 1 to rank n).
2901 * Sequencer ranks are selected using
2902 * function "LL_ADC_REG_SetSequencerRanks()".
2903 * - For devices with sequencer not fully configurable
2904 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2905 * sequencer length and each rank affectation to a channel
2906 * are defined by channel number.
2907 * This function retrieves:
2908 * - Sequence length: Number of ranks in the scan sequence is
2909 * defined by number of channels set in the sequence,
2910 * rank of each channel is fixed by channel HW number.
2911 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2912 * - Sequence direction: Unless specified in parameters, sequencer
2913 * scan direction is forward (from lowest channel number to
2914 * highest channel number).
2915 * Sequencer ranks are selected using
2916 * function "LL_ADC_REG_SetSequencerChannels()".
2917 * To set scan direction differently, refer to function
2918 * @ref LL_ADC_REG_SetSequencerScanDirection().
2919 * @note On this STM32 series, ADC group regular sequencer both modes
2920 * "fully configurable" or "not fully configurable"
2921 * are available, they can be chosen using
2922 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2923 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2924 * ADC conversion on only 1 channel.
2925 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
2926 * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
2927 * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
2928 * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
2929 * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
2930 * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
2931 * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
2932 * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
2933 * @param ADCx ADC instance
2934 * @retval Returned value can be one of the following values:
2935 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2936 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2937 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2938 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2939 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2940 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2941 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2942 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2943 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)2944 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
2945 {
2946 __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
2947 uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
2948 uint32_t rank_index;
2949 uint32_t rank_shifted;
2950
2951 /* Parse register for end of sequence identifier */
2952 /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
2953 (ADC_CHSELR_SQ2), value "4" to length of end of sequence
2954 identifier (0xF) */
2955 for (rank_index = 0U; rank_index <= (28U - 4U); rank_index += 4U)
2956 {
2957 rank_shifted = (uint32_t)(0xF0UL << rank_index);
2958 if ((channels_ranks & rank_shifted) == rank_shifted)
2959 {
2960 sequencer_length = rank_shifted;
2961 break;
2962 }
2963 }
2964
2965 return sequencer_length;
2966 }
2967
2968 /**
2969 * @brief Set ADC group regular sequencer scan direction.
2970 * @note On this STM32 series, parameter relevant only is sequencer is set
2971 * to mode not fully configurable,
2972 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2973 * @note On some other STM32 series, this setting is not available and
2974 * the default scan direction is forward.
2975 * @note On this STM32 series, after modifying sequencer (functions
2976 * @ref LL_ADC_REG_SetSequencerLength()
2977 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2978 * it is mandatory to wait for the assertion of CCRDY flag
2979 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2980 * Otherwise, some actions may be ignored.
2981 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2982 * for more details.
2983 * @note On this STM32 series, setting of this feature is conditioned to
2984 * ADC state:
2985 * ADC must be disabled.
2986 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
2987 * @param ADCx ADC instance
2988 * @param ScanDirection This parameter can be one of the following values:
2989 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2990 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2991 * @retval None
2992 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)2993 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
2994 {
2995 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
2996 }
2997
2998 /**
2999 * @brief Get ADC group regular sequencer scan direction.
3000 * @note On this STM32 series, parameter relevant only is sequencer is set
3001 * to mode not fully configurable,
3002 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3003 * @note On some other STM32 series, this setting is not available and
3004 * the default scan direction is forward.
3005 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
3006 * @param ADCx ADC instance
3007 * @retval Returned value can be one of the following values:
3008 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
3009 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
3010 */
LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef * ADCx)3011 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx)
3012 {
3013 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
3014 }
3015
3016 /**
3017 * @brief Set ADC group regular sequencer discontinuous mode:
3018 * sequence subdivided and scan conversions interrupted every selected
3019 * number of ranks.
3020 * @note It is not possible to enable both ADC group regular
3021 * continuous mode and sequencer discontinuous mode.
3022 * @note On this STM32 series, setting of this feature is conditioned to
3023 * ADC state:
3024 * ADC must be disabled.
3025 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
3026 * @param ADCx ADC instance
3027 * @param SeqDiscont This parameter can be one of the following values:
3028 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3029 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3030 * @retval None
3031 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3032 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3033 {
3034 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
3035 }
3036
3037 /**
3038 * @brief Get ADC group regular sequencer discontinuous mode:
3039 * sequence subdivided and scan conversions interrupted every selected
3040 * number of ranks.
3041 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
3042 * @param ADCx ADC instance
3043 * @retval Returned value can be one of the following values:
3044 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3045 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3046 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)3047 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
3048 {
3049 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
3050 }
3051
3052 /**
3053 * @brief Set ADC group regular sequence: channel on the selected
3054 * scan sequence rank.
3055 * @note This function performs configuration of:
3056 * - Channels ordering into each rank of scan sequence:
3057 * whatever channel can be placed into whatever rank.
3058 * @note On this STM32 series, ADC group regular sequencer is
3059 * fully configurable: sequencer length and each rank
3060 * affectation to a channel are configurable.
3061 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3062 * @note Depending on devices and packages, some channels may not be available.
3063 * Refer to device datasheet for channels availability.
3064 * @note On this STM32 series, to measure internal channels (VrefInt,
3065 * TempSensor, ...), measurement paths to internal channels must be
3066 * enabled separately.
3067 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3068 * @note On this STM32 series, after modifying sequencer (functions
3069 * @ref LL_ADC_REG_SetSequencerLength()
3070 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3071 * it is mandatory to wait for the assertion of CCRDY flag
3072 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3073 * Otherwise, some actions may be ignored.
3074 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3075 * for more details.
3076 * @note On this STM32 series, setting of this feature is conditioned to
3077 * ADC state:
3078 * ADC must be disabled or enabled without conversion on going
3079 * on group regular.
3080 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n
3081 * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n
3082 * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n
3083 * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n
3084 * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n
3085 * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n
3086 * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n
3087 * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks
3088 * @param ADCx ADC instance
3089 * @param Rank This parameter can be one of the following values:
3090 * @arg @ref LL_ADC_REG_RANK_1
3091 * @arg @ref LL_ADC_REG_RANK_2
3092 * @arg @ref LL_ADC_REG_RANK_3
3093 * @arg @ref LL_ADC_REG_RANK_4
3094 * @arg @ref LL_ADC_REG_RANK_5
3095 * @arg @ref LL_ADC_REG_RANK_6
3096 * @arg @ref LL_ADC_REG_RANK_7
3097 * @arg @ref LL_ADC_REG_RANK_8
3098 * @param Channel This parameter can be one of the following values:
3099 * @arg @ref LL_ADC_CHANNEL_0
3100 * @arg @ref LL_ADC_CHANNEL_1
3101 * @arg @ref LL_ADC_CHANNEL_2
3102 * @arg @ref LL_ADC_CHANNEL_3
3103 * @arg @ref LL_ADC_CHANNEL_4
3104 * @arg @ref LL_ADC_CHANNEL_5
3105 * @arg @ref LL_ADC_CHANNEL_6
3106 * @arg @ref LL_ADC_CHANNEL_7
3107 * @arg @ref LL_ADC_CHANNEL_8
3108 * @arg @ref LL_ADC_CHANNEL_9
3109 * @arg @ref LL_ADC_CHANNEL_10
3110 * @arg @ref LL_ADC_CHANNEL_11
3111 * @arg @ref LL_ADC_CHANNEL_12
3112 * @arg @ref LL_ADC_CHANNEL_13
3113 * @arg @ref LL_ADC_CHANNEL_14
3114 * @arg @ref LL_ADC_CHANNEL_15 (1)
3115 * @arg @ref LL_ADC_CHANNEL_16 (1)
3116 * @arg @ref LL_ADC_CHANNEL_17 (1)
3117 * @arg @ref LL_ADC_CHANNEL_18
3118 * @arg @ref LL_ADC_CHANNEL_VREFINT
3119 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3120 * @arg @ref LL_ADC_CHANNEL_VBAT
3121 *
3122 * (1) On STM32G0, parameter can be set in ADC group sequencer
3123 * only if sequencer is set in mode "not fully configurable",
3124 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3125 * @retval None
3126 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3127 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3128 {
3129 /* Set bits with content of parameter "Channel" with bits position */
3130 /* in register depending on parameter "Rank". */
3131 /* Parameters "Rank" and "Channel" are used with masks because containing */
3132 /* other bits reserved for other purpose. */
3133 MODIFY_REG(ADCx->CHSELR,
3134 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3135 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3136 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3137 }
3138
3139 /**
3140 * @brief Get ADC group regular sequence: channel on the selected
3141 * scan sequence rank.
3142 * @note On this STM32 series, ADC group regular sequencer is
3143 * fully configurable: sequencer length and each rank
3144 * affectation to a channel are configurable.
3145 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3146 * @note Depending on devices and packages, some channels may not be available.
3147 * Refer to device datasheet for channels availability.
3148 * @note Usage of the returned channel number:
3149 * - To reinject this channel into another function LL_ADC_xxx:
3150 * the returned channel number is only partly formatted on definition
3151 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3152 * with parts of literals LL_ADC_CHANNEL_x or using
3153 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3154 * Then the selected literal LL_ADC_CHANNEL_x can be used
3155 * as parameter for another function.
3156 * - To get the channel number in decimal format:
3157 * process the returned value with the helper macro
3158 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3159 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n
3160 * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n
3161 * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n
3162 * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n
3163 * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n
3164 * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n
3165 * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n
3166 * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks
3167 * @param ADCx ADC instance
3168 * @param Rank This parameter can be one of the following values:
3169 * @arg @ref LL_ADC_REG_RANK_1
3170 * @arg @ref LL_ADC_REG_RANK_2
3171 * @arg @ref LL_ADC_REG_RANK_3
3172 * @arg @ref LL_ADC_REG_RANK_4
3173 * @arg @ref LL_ADC_REG_RANK_5
3174 * @arg @ref LL_ADC_REG_RANK_6
3175 * @arg @ref LL_ADC_REG_RANK_7
3176 * @arg @ref LL_ADC_REG_RANK_8
3177 * @retval Returned value can be one of the following values:
3178 * @arg @ref LL_ADC_CHANNEL_0
3179 * @arg @ref LL_ADC_CHANNEL_1
3180 * @arg @ref LL_ADC_CHANNEL_2
3181 * @arg @ref LL_ADC_CHANNEL_3
3182 * @arg @ref LL_ADC_CHANNEL_4
3183 * @arg @ref LL_ADC_CHANNEL_5
3184 * @arg @ref LL_ADC_CHANNEL_6
3185 * @arg @ref LL_ADC_CHANNEL_7
3186 * @arg @ref LL_ADC_CHANNEL_8
3187 * @arg @ref LL_ADC_CHANNEL_9
3188 * @arg @ref LL_ADC_CHANNEL_10
3189 * @arg @ref LL_ADC_CHANNEL_11
3190 * @arg @ref LL_ADC_CHANNEL_12
3191 * @arg @ref LL_ADC_CHANNEL_13
3192 * @arg @ref LL_ADC_CHANNEL_14
3193 * @arg @ref LL_ADC_CHANNEL_15 (1)
3194 * @arg @ref LL_ADC_CHANNEL_16 (1)
3195 * @arg @ref LL_ADC_CHANNEL_17 (1)
3196 * @arg @ref LL_ADC_CHANNEL_18
3197 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
3198 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
3199 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
3200 *
3201 * (1) On STM32G0, parameter can be set in ADC group sequencer
3202 * only if sequencer is set in mode "not fully configurable",
3203 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
3204 * (2) For ADC channel read back from ADC register,
3205 * comparison with internal channel parameter to be done
3206 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3207 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)3208 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
3209 {
3210 return (uint32_t)((READ_BIT(ADCx->CHSELR,
3211 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3212 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
3213 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3214 );
3215 }
3216
3217 /**
3218 * @brief Set ADC group regular sequence: channel on rank corresponding to
3219 * channel number.
3220 * @note This function performs:
3221 * - Channels ordering into each rank of scan sequence:
3222 * rank of each channel is fixed by channel HW number
3223 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3224 * - Set channels selected by overwriting the current sequencer
3225 * configuration.
3226 * @note On this STM32 series, ADC group regular sequencer both modes
3227 * "fully configurable" or "not fully configurable"
3228 * are available, they can be chosen using
3229 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3230 * This function can be used with setting "not fully configurable".
3231 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3232 * and @ref LL_ADC_REG_SetSequencerLength().
3233 * @note On this STM32 series, after modifying sequencer (functions
3234 * @ref LL_ADC_REG_SetSequencerLength()
3235 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3236 * it is mandatory to wait for the assertion of CCRDY flag
3237 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3238 * Otherwise, some actions may be ignored.
3239 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3240 * for more details.
3241 * @note Depending on devices and packages, some channels may not be available.
3242 * Refer to device datasheet for channels availability.
3243 * @note On this STM32 series, to measure internal channels (VrefInt,
3244 * TempSensor, ...), measurement paths to internal channels must be
3245 * enabled separately.
3246 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3247 * @note On this STM32 series, setting of this feature is conditioned to
3248 * ADC state:
3249 * ADC must be disabled or enabled without conversion on going
3250 * on group regular.
3251 * @note One or several values can be selected.
3252 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3253 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
3254 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
3255 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
3256 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
3257 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
3258 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
3259 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
3260 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
3261 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
3262 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
3263 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
3264 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
3265 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
3266 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
3267 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
3268 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
3269 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
3270 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
3271 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
3272 * @param ADCx ADC instance
3273 * @param Channel This parameter can be a combination of the following values:
3274 * @arg @ref LL_ADC_CHANNEL_0
3275 * @arg @ref LL_ADC_CHANNEL_1
3276 * @arg @ref LL_ADC_CHANNEL_2
3277 * @arg @ref LL_ADC_CHANNEL_3
3278 * @arg @ref LL_ADC_CHANNEL_4
3279 * @arg @ref LL_ADC_CHANNEL_5
3280 * @arg @ref LL_ADC_CHANNEL_6
3281 * @arg @ref LL_ADC_CHANNEL_7
3282 * @arg @ref LL_ADC_CHANNEL_8
3283 * @arg @ref LL_ADC_CHANNEL_9
3284 * @arg @ref LL_ADC_CHANNEL_10
3285 * @arg @ref LL_ADC_CHANNEL_11
3286 * @arg @ref LL_ADC_CHANNEL_12
3287 * @arg @ref LL_ADC_CHANNEL_13
3288 * @arg @ref LL_ADC_CHANNEL_14
3289 * @arg @ref LL_ADC_CHANNEL_15 (1)
3290 * @arg @ref LL_ADC_CHANNEL_16 (1)
3291 * @arg @ref LL_ADC_CHANNEL_17 (1)
3292 * @arg @ref LL_ADC_CHANNEL_18
3293 * @arg @ref LL_ADC_CHANNEL_VREFINT
3294 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3295 * @arg @ref LL_ADC_CHANNEL_VBAT
3296 *
3297 * (1) On STM32G0, parameter can be set in ADC group sequencer
3298 * only if sequencer is set in mode "not fully configurable",
3299 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3300 * @retval None
3301 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)3302 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
3303 {
3304 /* Parameter "Channel" is used with masks because containing */
3305 /* other bits reserved for other purpose. */
3306 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3307 }
3308
3309 /**
3310 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
3311 * channel number.
3312 * @note This function performs:
3313 * - Channels ordering into each rank of scan sequence:
3314 * rank of each channel is fixed by channel HW number
3315 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3316 * - Set channels selected by adding them to the current sequencer
3317 * configuration.
3318 * @note On this STM32 series, ADC group regular sequencer both modes
3319 * "fully configurable" or "not fully configurable"
3320 * are available, they can be chosen using
3321 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3322 * This function can be used with setting "not fully configurable".
3323 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3324 * and @ref LL_ADC_REG_SetSequencerLength().
3325 * @note On this STM32 series, after modifying sequencer (functions
3326 * @ref LL_ADC_REG_SetSequencerLength()
3327 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3328 * it is mandatory to wait for the assertion of CCRDY flag
3329 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3330 * Otherwise, some actions may be ignored.
3331 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3332 * for more details.
3333 * @note Depending on devices and packages, some channels may not be available.
3334 * Refer to device datasheet for channels availability.
3335 * @note On this STM32 series, to measure internal channels (VrefInt,
3336 * TempSensor, ...), measurement paths to internal channels must be
3337 * enabled separately.
3338 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3339 * @note On this STM32 series, setting of this feature is conditioned to
3340 * ADC state:
3341 * ADC must be disabled or enabled without conversion on going
3342 * on group regular.
3343 * @note One or several values can be selected.
3344 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3345 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
3346 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
3347 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
3348 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
3349 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
3350 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
3351 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
3352 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
3353 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
3354 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
3355 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
3356 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
3357 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
3358 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
3359 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
3360 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
3361 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
3362 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
3363 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
3364 * @param ADCx ADC instance
3365 * @param Channel This parameter can be a combination of the following values:
3366 * @arg @ref LL_ADC_CHANNEL_0
3367 * @arg @ref LL_ADC_CHANNEL_1
3368 * @arg @ref LL_ADC_CHANNEL_2
3369 * @arg @ref LL_ADC_CHANNEL_3
3370 * @arg @ref LL_ADC_CHANNEL_4
3371 * @arg @ref LL_ADC_CHANNEL_5
3372 * @arg @ref LL_ADC_CHANNEL_6
3373 * @arg @ref LL_ADC_CHANNEL_7
3374 * @arg @ref LL_ADC_CHANNEL_8
3375 * @arg @ref LL_ADC_CHANNEL_9
3376 * @arg @ref LL_ADC_CHANNEL_10
3377 * @arg @ref LL_ADC_CHANNEL_11
3378 * @arg @ref LL_ADC_CHANNEL_12
3379 * @arg @ref LL_ADC_CHANNEL_13
3380 * @arg @ref LL_ADC_CHANNEL_14
3381 * @arg @ref LL_ADC_CHANNEL_15 (1)
3382 * @arg @ref LL_ADC_CHANNEL_16 (1)
3383 * @arg @ref LL_ADC_CHANNEL_17 (1)
3384 * @arg @ref LL_ADC_CHANNEL_18
3385 * @arg @ref LL_ADC_CHANNEL_VREFINT
3386 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3387 * @arg @ref LL_ADC_CHANNEL_VBAT
3388 *
3389 * (1) On STM32G0, parameter can be set in ADC group sequencer
3390 * only if sequencer is set in mode "not fully configurable",
3391 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3392 * @retval None
3393 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)3394 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
3395 {
3396 /* Parameter "Channel" is used with masks because containing */
3397 /* other bits reserved for other purpose. */
3398 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3399 }
3400
3401 /**
3402 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
3403 * channel number.
3404 * @note This function performs:
3405 * - Channels ordering into each rank of scan sequence:
3406 * rank of each channel is fixed by channel HW number
3407 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3408 * - Set channels selected by removing them to the current sequencer
3409 * configuration.
3410 * @note On this STM32 series, ADC group regular sequencer both modes
3411 * "fully configurable" or "not fully configurable"
3412 * are available, they can be chosen using
3413 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3414 * This function can be used with setting "not fully configurable".
3415 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3416 * and @ref LL_ADC_REG_SetSequencerLength().
3417 * @note On this STM32 series, after modifying sequencer (functions
3418 * @ref LL_ADC_REG_SetSequencerLength()
3419 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3420 * it is mandatory to wait for the assertion of CCRDY flag
3421 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3422 * Otherwise, some actions may be ignored.
3423 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3424 * for more details.
3425 * @note Depending on devices and packages, some channels may not be available.
3426 * Refer to device datasheet for channels availability.
3427 * @note On this STM32 series, to measure internal channels (VrefInt,
3428 * TempSensor, ...), measurement paths to internal channels must be
3429 * enabled separately.
3430 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3431 * @note On this STM32 series, setting of this feature is conditioned to
3432 * ADC state:
3433 * ADC must be disabled or enabled without conversion on going
3434 * on group regular.
3435 * @note One or several values can be selected.
3436 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3437 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
3438 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
3439 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
3440 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
3441 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
3442 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
3443 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
3444 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
3445 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
3446 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
3447 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
3448 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
3449 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
3450 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
3451 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
3452 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
3453 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
3454 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
3455 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
3456 * @param ADCx ADC instance
3457 * @param Channel This parameter can be a combination of the following values:
3458 * @arg @ref LL_ADC_CHANNEL_0
3459 * @arg @ref LL_ADC_CHANNEL_1
3460 * @arg @ref LL_ADC_CHANNEL_2
3461 * @arg @ref LL_ADC_CHANNEL_3
3462 * @arg @ref LL_ADC_CHANNEL_4
3463 * @arg @ref LL_ADC_CHANNEL_5
3464 * @arg @ref LL_ADC_CHANNEL_6
3465 * @arg @ref LL_ADC_CHANNEL_7
3466 * @arg @ref LL_ADC_CHANNEL_8
3467 * @arg @ref LL_ADC_CHANNEL_9
3468 * @arg @ref LL_ADC_CHANNEL_10
3469 * @arg @ref LL_ADC_CHANNEL_11
3470 * @arg @ref LL_ADC_CHANNEL_12
3471 * @arg @ref LL_ADC_CHANNEL_13
3472 * @arg @ref LL_ADC_CHANNEL_14
3473 * @arg @ref LL_ADC_CHANNEL_15 (1)
3474 * @arg @ref LL_ADC_CHANNEL_16 (1)
3475 * @arg @ref LL_ADC_CHANNEL_17 (1)
3476 * @arg @ref LL_ADC_CHANNEL_18
3477 * @arg @ref LL_ADC_CHANNEL_VREFINT
3478 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3479 * @arg @ref LL_ADC_CHANNEL_VBAT
3480 *
3481 * (1) On STM32G0, parameter can be set in ADC group sequencer
3482 * only if sequencer is set in mode "not fully configurable",
3483 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3484 * @retval None
3485 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)3486 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
3487 {
3488 /* Parameter "Channel" is used with masks because containing */
3489 /* other bits reserved for other purpose. */
3490 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3491 }
3492
3493 /**
3494 * @brief Get ADC group regular sequence: channel on rank corresponding to
3495 * channel number.
3496 * @note This function performs:
3497 * - Channels order reading into each rank of scan sequence:
3498 * rank of each channel is fixed by channel HW number
3499 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3500 * @note On this STM32 series, ADC group regular sequencer both modes
3501 * "fully configurable" or "not fully configurable"
3502 * are available, they can be chosen using
3503 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3504 * This function can be used with setting "not fully configurable".
3505 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3506 * and @ref LL_ADC_REG_SetSequencerLength().
3507 * @note Depending on devices and packages, some channels may not be available.
3508 * Refer to device datasheet for channels availability.
3509 * @note On this STM32 series, to measure internal channels (VrefInt,
3510 * TempSensor, ...), measurement paths to internal channels must be
3511 * enabled separately.
3512 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3513 * @note On this STM32 series, setting of this feature is conditioned to
3514 * ADC state:
3515 * ADC must be disabled or enabled without conversion on going
3516 * on group regular.
3517 * @note One or several values can be retrieved.
3518 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3519 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
3520 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
3521 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
3522 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
3523 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
3524 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
3525 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
3526 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
3527 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
3528 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
3529 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
3530 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
3531 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
3532 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
3533 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
3534 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
3535 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
3536 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
3537 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
3538 * @param ADCx ADC instance
3539 * @retval Returned value can be a combination of the following values:
3540 * @arg @ref LL_ADC_CHANNEL_0
3541 * @arg @ref LL_ADC_CHANNEL_1
3542 * @arg @ref LL_ADC_CHANNEL_2
3543 * @arg @ref LL_ADC_CHANNEL_3
3544 * @arg @ref LL_ADC_CHANNEL_4
3545 * @arg @ref LL_ADC_CHANNEL_5
3546 * @arg @ref LL_ADC_CHANNEL_6
3547 * @arg @ref LL_ADC_CHANNEL_7
3548 * @arg @ref LL_ADC_CHANNEL_8
3549 * @arg @ref LL_ADC_CHANNEL_9
3550 * @arg @ref LL_ADC_CHANNEL_10
3551 * @arg @ref LL_ADC_CHANNEL_11
3552 * @arg @ref LL_ADC_CHANNEL_12
3553 * @arg @ref LL_ADC_CHANNEL_13
3554 * @arg @ref LL_ADC_CHANNEL_14
3555 * @arg @ref LL_ADC_CHANNEL_15 (1)
3556 * @arg @ref LL_ADC_CHANNEL_16 (1)
3557 * @arg @ref LL_ADC_CHANNEL_17 (1)
3558 * @arg @ref LL_ADC_CHANNEL_18
3559 * @arg @ref LL_ADC_CHANNEL_VREFINT
3560 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3561 * @arg @ref LL_ADC_CHANNEL_VBAT
3562 *
3563 * (1) On STM32G0, parameter can be set in ADC group sequencer
3564 * only if sequencer is set in mode "not fully configurable",
3565 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3566 */
LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef * ADCx)3567 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx)
3568 {
3569 uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
3570
3571 return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
3572 | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
3573 | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
3574 | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
3575 | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
3576 | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
3577 | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
3578 | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
3579 | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
3580 | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
3581 | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
3582 | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
3583 | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
3584 | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
3585 | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
3586 | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
3587 | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
3588 | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
3589 #if defined(ADC_CCR_VBATEN)
3590 | (((channels_bitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
3591 #endif /* ADC_CCR_VBATEN */
3592 );
3593 }
3594
3595 /**
3596 * @brief Set ADC continuous conversion mode on ADC group regular.
3597 * @note Description of ADC continuous conversion mode:
3598 * - single mode: one conversion per trigger
3599 * - continuous mode: after the first trigger, following
3600 * conversions launched successively automatically.
3601 * @note It is not possible to enable both ADC group regular
3602 * continuous mode and sequencer discontinuous mode.
3603 * @note On this STM32 series, setting of this feature is conditioned to
3604 * ADC state:
3605 * ADC must be disabled.
3606 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
3607 * @param ADCx ADC instance
3608 * @param Continuous This parameter can be one of the following values:
3609 * @arg @ref LL_ADC_REG_CONV_SINGLE
3610 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3611 * @retval None
3612 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3613 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3614 {
3615 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
3616 }
3617
3618 /**
3619 * @brief Get ADC continuous conversion mode on ADC group regular.
3620 * @note Description of ADC continuous conversion mode:
3621 * - single mode: one conversion per trigger
3622 * - continuous mode: after the first trigger, following
3623 * conversions launched successively automatically.
3624 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
3625 * @param ADCx ADC instance
3626 * @retval Returned value can be one of the following values:
3627 * @arg @ref LL_ADC_REG_CONV_SINGLE
3628 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3629 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)3630 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
3631 {
3632 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
3633 }
3634
3635 /**
3636 * @brief Set ADC group regular conversion data transfer: no transfer or
3637 * transfer by DMA, and DMA requests mode.
3638 * @note If transfer by DMA selected, specifies the DMA requests
3639 * mode:
3640 * - Limited mode (One shot mode): DMA transfer requests are stopped
3641 * when number of DMA data transfers (number of
3642 * ADC conversions) is reached.
3643 * This ADC mode is intended to be used with DMA mode non-circular.
3644 * - Unlimited mode: DMA transfer requests are unlimited,
3645 * whatever number of DMA data transfers (number of
3646 * ADC conversions).
3647 * This ADC mode is intended to be used with DMA mode circular.
3648 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3649 * mode non-circular:
3650 * when DMA transfers size will be reached, DMA will stop transfers of
3651 * ADC conversions data ADC will raise an overrun error
3652 * (overrun flag and interruption if enabled).
3653 * @note To configure DMA source address (peripheral address),
3654 * use function @ref LL_ADC_DMA_GetRegAddr().
3655 * @note On this STM32 series, setting of this feature is conditioned to
3656 * ADC state:
3657 * ADC must be disabled.
3658 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
3659 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
3660 * @param ADCx ADC instance
3661 * @param DMATransfer This parameter can be one of the following values:
3662 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3663 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3664 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3665 * @retval None
3666 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3667 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3668 {
3669 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
3670 }
3671
3672 /**
3673 * @brief Get ADC group regular conversion data transfer: no transfer or
3674 * transfer by DMA, and DMA requests mode.
3675 * @note If transfer by DMA selected, specifies the DMA requests
3676 * mode:
3677 * - Limited mode (One shot mode): DMA transfer requests are stopped
3678 * when number of DMA data transfers (number of
3679 * ADC conversions) is reached.
3680 * This ADC mode is intended to be used with DMA mode non-circular.
3681 * - Unlimited mode: DMA transfer requests are unlimited,
3682 * whatever number of DMA data transfers (number of
3683 * ADC conversions).
3684 * This ADC mode is intended to be used with DMA mode circular.
3685 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3686 * mode non-circular:
3687 * when DMA transfers size will be reached, DMA will stop transfers of
3688 * ADC conversions data ADC will raise an overrun error
3689 * (overrun flag and interruption if enabled).
3690 * @note To configure DMA source address (peripheral address),
3691 * use function @ref LL_ADC_DMA_GetRegAddr().
3692 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
3693 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
3694 * @param ADCx ADC instance
3695 * @retval Returned value can be one of the following values:
3696 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3697 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3698 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3699 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)3700 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
3701 {
3702 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
3703 }
3704
3705 /**
3706 * @brief Set ADC group regular behavior in case of overrun:
3707 * data preserved or overwritten.
3708 * @note Compatibility with devices without feature overrun:
3709 * other devices without this feature have a behavior
3710 * equivalent to data overwritten.
3711 * The default setting of overrun is data preserved.
3712 * Therefore, for compatibility with all devices, parameter
3713 * overrun should be set to data overwritten.
3714 * @note On this STM32 series, setting of this feature is conditioned to
3715 * ADC state:
3716 * ADC must be disabled.
3717 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
3718 * @param ADCx ADC instance
3719 * @param Overrun This parameter can be one of the following values:
3720 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3721 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3722 * @retval None
3723 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3724 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3725 {
3726 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
3727 }
3728
3729 /**
3730 * @brief Get ADC group regular behavior in case of overrun:
3731 * data preserved or overwritten.
3732 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
3733 * @param ADCx ADC instance
3734 * @retval Returned value can be one of the following values:
3735 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3736 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3737 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)3738 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
3739 {
3740 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
3741 }
3742
3743 /**
3744 * @}
3745 */
3746
3747 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3748 * @{
3749 */
3750
3751 /**
3752 * @brief Set sampling time of the selected ADC channel
3753 * Unit: ADC clock cycles.
3754 * @note On this device, sampling time is on channel scope: independently
3755 * of channel mapped on ADC group regular or injected.
3756 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3757 * converted:
3758 * sampling time constraints must be respected (sampling time can be
3759 * adjusted in function of ADC clock frequency and sampling time
3760 * setting).
3761 * Refer to device datasheet for timings values (parameters TS_vrefint,
3762 * TS_temp, ...).
3763 * @note Conversion time is the addition of sampling time and processing time.
3764 * Refer to reference manual for ADC processing time of
3765 * this STM32 series.
3766 * @note In case of ADC conversion of internal channel (VrefInt,
3767 * temperature sensor, ...), a sampling time minimum value
3768 * is required.
3769 * Refer to device datasheet.
3770 * @note On this STM32 series, setting of this feature is conditioned to
3771 * ADC state:
3772 * ADC must be disabled or enabled without conversion on going
3773 * on group regular.
3774 * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n
3775 * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n
3776 * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n
3777 * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n
3778 * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n
3779 * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n
3780 * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n
3781 * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n
3782 * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n
3783 * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n
3784 * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n
3785 * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n
3786 * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n
3787 * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n
3788 * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n
3789 * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n
3790 * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n
3791 * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n
3792 * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime
3793 * @param ADCx ADC instance
3794 * @param Channel This parameter can be a combination of the following values:
3795 * @arg @ref LL_ADC_CHANNEL_0
3796 * @arg @ref LL_ADC_CHANNEL_1
3797 * @arg @ref LL_ADC_CHANNEL_2
3798 * @arg @ref LL_ADC_CHANNEL_3
3799 * @arg @ref LL_ADC_CHANNEL_4
3800 * @arg @ref LL_ADC_CHANNEL_5
3801 * @arg @ref LL_ADC_CHANNEL_6
3802 * @arg @ref LL_ADC_CHANNEL_7
3803 * @arg @ref LL_ADC_CHANNEL_8
3804 * @arg @ref LL_ADC_CHANNEL_9
3805 * @arg @ref LL_ADC_CHANNEL_10
3806 * @arg @ref LL_ADC_CHANNEL_11
3807 * @arg @ref LL_ADC_CHANNEL_12
3808 * @arg @ref LL_ADC_CHANNEL_13
3809 * @arg @ref LL_ADC_CHANNEL_14
3810 * @arg @ref LL_ADC_CHANNEL_15 (1)
3811 * @arg @ref LL_ADC_CHANNEL_16 (1)
3812 * @arg @ref LL_ADC_CHANNEL_17 (1)
3813 * @arg @ref LL_ADC_CHANNEL_18
3814 * @arg @ref LL_ADC_CHANNEL_VREFINT
3815 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3816 * @arg @ref LL_ADC_CHANNEL_VBAT
3817 *
3818 * (1) On STM32G0, parameter can be set in ADC group sequencer
3819 * only if sequencer is set in mode "not fully configurable",
3820 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3821 * @param SamplingTimeY This parameter can be one of the following values:
3822 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3823 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3824 * @retval None
3825 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTimeY)3826 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
3827 {
3828 /* Parameter "Channel" is used with masks because containing */
3829 /* other bits reserved for other purpose. */
3830 MODIFY_REG(ADCx->SMPR,
3831 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
3832 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
3833 );
3834 }
3835
3836 /**
3837 * @brief Get sampling time of the selected ADC channel
3838 * Unit: ADC clock cycles.
3839 * @note On this device, sampling time is on channel scope: independently
3840 * of channel mapped on ADC group regular or injected.
3841 * @note Conversion time is the addition of sampling time and processing time.
3842 * Refer to reference manual for ADC processing time of
3843 * this STM32 series.
3844 * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n
3845 * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n
3846 * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n
3847 * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n
3848 * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n
3849 * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n
3850 * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n
3851 * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n
3852 * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n
3853 * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n
3854 * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n
3855 * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n
3856 * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n
3857 * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n
3858 * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n
3859 * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n
3860 * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n
3861 * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n
3862 * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime
3863 * @param ADCx ADC instance
3864 * @param Channel This parameter can be one of the following values:
3865 * @arg @ref LL_ADC_CHANNEL_0
3866 * @arg @ref LL_ADC_CHANNEL_1
3867 * @arg @ref LL_ADC_CHANNEL_2
3868 * @arg @ref LL_ADC_CHANNEL_3
3869 * @arg @ref LL_ADC_CHANNEL_4
3870 * @arg @ref LL_ADC_CHANNEL_5
3871 * @arg @ref LL_ADC_CHANNEL_6
3872 * @arg @ref LL_ADC_CHANNEL_7
3873 * @arg @ref LL_ADC_CHANNEL_8
3874 * @arg @ref LL_ADC_CHANNEL_9
3875 * @arg @ref LL_ADC_CHANNEL_10
3876 * @arg @ref LL_ADC_CHANNEL_11
3877 * @arg @ref LL_ADC_CHANNEL_12
3878 * @arg @ref LL_ADC_CHANNEL_13
3879 * @arg @ref LL_ADC_CHANNEL_14
3880 * @arg @ref LL_ADC_CHANNEL_15 (1)
3881 * @arg @ref LL_ADC_CHANNEL_16 (1)
3882 * @arg @ref LL_ADC_CHANNEL_17 (1)
3883 * @arg @ref LL_ADC_CHANNEL_18
3884 * @arg @ref LL_ADC_CHANNEL_VREFINT
3885 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3886 * @arg @ref LL_ADC_CHANNEL_VBAT
3887 *
3888 * (1) On STM32G0, parameter can be set in ADC group sequencer
3889 * only if sequencer is set in mode "not fully configurable",
3890 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3891 * @retval Returned value can be one of the following values:
3892 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3893 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3894 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)3895 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
3896 {
3897 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
3898
3899 /* Retrieve sampling time bit corresponding to the selected channel */
3900 /* and shift it to position 0. */
3901 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
3902 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3903 + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
3904 & 0x1FUL));
3905
3906 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
3907 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
3908 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
3909 }
3910
3911 /**
3912 * @}
3913 */
3914
3915 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3916 * @{
3917 */
3918
3919 /**
3920 * @brief Set ADC analog watchdog monitored channels:
3921 * a single channel, multiple channels or all channels,
3922 * on ADC group regular.
3923 * @note Once monitored channels are selected, analog watchdog
3924 * is enabled.
3925 * @note In case of need to define a single channel to monitor
3926 * with analog watchdog from sequencer channel definition,
3927 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3928 * @note On this STM32 series, there are 2 kinds of analog watchdog
3929 * instance:
3930 * - AWD standard (instance AWD1):
3931 * - channels monitored: can monitor 1 channel or all channels.
3932 * - groups monitored: ADC group regular.
3933 * - resolution: resolution is not limited (corresponds to
3934 * ADC resolution configured).
3935 * - AWD flexible (instances AWD2, AWD3):
3936 * - channels monitored: flexible on channels monitored, selection is
3937 * channel wise, from from 1 to all channels.
3938 * Specificity of this analog watchdog: Multiple channels can
3939 * be selected. For example:
3940 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3941 * - groups monitored: not selection possible (monitoring on both
3942 * groups regular and injected).
3943 * Channels selected are monitored on groups regular and injected:
3944 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3945 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3946 * - resolution: resolution is not limited (corresponds to
3947 * ADC resolution configured).
3948 * @note On this STM32 series, setting of this feature is conditioned to
3949 * ADC state:
3950 * ADC must be disabled.
3951 * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3952 * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3953 * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
3954 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
3955 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
3956 * @param ADCx ADC instance
3957 * @param AWDy This parameter can be one of the following values:
3958 * @arg @ref LL_ADC_AWD1
3959 * @arg @ref LL_ADC_AWD2
3960 * @arg @ref LL_ADC_AWD3
3961 * @param AWDChannelGroup This parameter can be one of the following values:
3962 * @arg @ref LL_ADC_AWD_DISABLE
3963 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3964 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3965 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3966 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3967 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3968 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3969 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3970 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3971 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3972 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3973 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3974 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3975 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3976 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3977 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3978 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3979 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3980 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3981 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3982 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3983 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
3984 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
3985 * @arg @ref LL_ADC_AWD_CH_VBAT_REG
3986 * @retval None
3987 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)3988 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
3989 {
3990 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
3991 /* in register and register position depending on parameter "AWDy". */
3992 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
3993 /* containing other bits reserved for other purpose. */
3994 __IO uint32_t *preg;
3995
3996 if (AWDy == LL_ADC_AWD1)
3997 {
3998 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
3999 }
4000 else
4001 {
4002 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
4003 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
4004 }
4005
4006 MODIFY_REG(*preg,
4007 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
4008 AWDChannelGroup & AWDy);
4009 }
4010
4011 /**
4012 * @brief Get ADC analog watchdog monitored channel.
4013 * @note Usage of the returned channel number:
4014 * - To reinject this channel into another function LL_ADC_xxx:
4015 * the returned channel number is only partly formatted on definition
4016 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4017 * with parts of literals LL_ADC_CHANNEL_x or using
4018 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4019 * Then the selected literal LL_ADC_CHANNEL_x can be used
4020 * as parameter for another function.
4021 * - To get the channel number in decimal format:
4022 * process the returned value with the helper macro
4023 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4024 * Applicable only when the analog watchdog is set to monitor
4025 * one channel.
4026 * @note On this STM32 series, there are 2 kinds of analog watchdog
4027 * instance:
4028 * - AWD standard (instance AWD1):
4029 * - channels monitored: can monitor 1 channel or all channels.
4030 * - groups monitored: ADC group regular.
4031 * - resolution: resolution is not limited (corresponds to
4032 * ADC resolution configured).
4033 * - AWD flexible (instances AWD2, AWD3):
4034 * - channels monitored: flexible on channels monitored, selection is
4035 * channel wise, from from 1 to all channels.
4036 * Specificity of this analog watchdog: Multiple channels can
4037 * be selected. For example:
4038 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4039 * - groups monitored: not selection possible (monitoring on both
4040 * groups regular and injected).
4041 * Channels selected are monitored on groups regular and injected:
4042 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4043 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4044 * - resolution: resolution is not limited (corresponds to
4045 * ADC resolution configured).
4046 * @note On this STM32 series, setting of this feature is conditioned to
4047 * ADC state:
4048 * ADC must be disabled or enabled without conversion on going
4049 * on group regular.
4050 * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
4051 * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
4052 * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
4053 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
4054 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
4055 * @param ADCx ADC instance
4056 * @param AWDy This parameter can be one of the following values:
4057 * @arg @ref LL_ADC_AWD1
4058 * @arg @ref LL_ADC_AWD2 (1)
4059 * @arg @ref LL_ADC_AWD3 (1)
4060 *
4061 * (1) On this AWD number, monitored channel can be retrieved
4062 * if only 1 channel is programmed (or none or all channels).
4063 * This function cannot retrieve monitored channel if
4064 * multiple channels are programmed simultaneously
4065 * by bitfield.
4066 * @retval Returned value can be one of the following values:
4067 * @arg @ref LL_ADC_AWD_DISABLE
4068 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
4069 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
4070 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
4071 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
4072 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
4073 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
4074 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
4075 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
4076 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
4077 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
4078 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
4079 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
4080 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
4081 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
4082 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
4083 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
4084 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
4085 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
4086 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
4087 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
4088 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)4089 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
4090 {
4091 __IO const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
4092 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
4093 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
4094 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
4095
4096 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
4097
4098 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
4099 /* (parameter value LL_ADC_AWD_DISABLE). */
4100 /* Else, the selected AWD is enabled and is monitoring a group of channels */
4101 /* or a single channel. */
4102 if (analog_wd_monit_channels != 0UL)
4103 {
4104 if (AWDy == LL_ADC_AWD1)
4105 {
4106 if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
4107 {
4108 /* AWD monitoring a group of channels */
4109 analog_wd_monit_channels = ((analog_wd_monit_channels
4110 | (ADC_AWD_CR23_CHANNEL_MASK)
4111 )
4112 & (~(ADC_CFGR1_AWD1CH))
4113 );
4114 }
4115 else
4116 {
4117 /* AWD monitoring a single channel */
4118 analog_wd_monit_channels = (analog_wd_monit_channels
4119 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos))
4120 );
4121 }
4122 }
4123 else
4124 {
4125 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
4126 {
4127 /* AWD monitoring a group of channels */
4128 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
4129 | (ADC_CFGR1_AWD1EN)
4130 );
4131 }
4132 else
4133 {
4134 /* AWD monitoring a single channel */
4135 /* AWD monitoring a group of channels */
4136 analog_wd_monit_channels = (analog_wd_monit_channels
4137 | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
4138 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos)
4139 );
4140 }
4141 }
4142 }
4143
4144 return analog_wd_monit_channels;
4145 }
4146
4147 /**
4148 * @brief Set ADC analog watchdog thresholds value of both thresholds
4149 * high and low.
4150 * @note If value of only one threshold high or low must be set,
4151 * use function @ref LL_ADC_SetAnalogWDThresholds().
4152 * @note In case of ADC resolution different of 12 bits,
4153 * analog watchdog thresholds data require a specific shift.
4154 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
4155 * @note On this STM32 series, there are 2 kinds of analog watchdog
4156 * instance:
4157 * - AWD standard (instance AWD1):
4158 * - channels monitored: can monitor 1 channel or all channels.
4159 * - groups monitored: ADC group regular.
4160 * - resolution: resolution is not limited (corresponds to
4161 * ADC resolution configured).
4162 * - AWD flexible (instances AWD2, AWD3):
4163 * - channels monitored: flexible on channels monitored, selection is
4164 * channel wise, from from 1 to all channels.
4165 * Specificity of this analog watchdog: Multiple channels can
4166 * be selected. For example:
4167 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4168 * - groups monitored: not selection possible (monitoring on both
4169 * groups regular and injected).
4170 * Channels selected are monitored on groups regular and injected:
4171 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4172 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4173 * - resolution: resolution is not limited (corresponds to
4174 * ADC resolution configured).
4175 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
4176 * impacted: the comparison of analog watchdog thresholds is done on
4177 * oversampling final computation (after ratio and shift application):
4178 * ADC data register bitfield [15:4] (12 most significant bits).
4179 * Examples:
4180 * - Oversampling ratio and shift selected to have ADC conversion data
4181 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
4182 * ADC analog watchdog thresholds must be divided by 16.
4183 * - Oversampling ratio and shift selected to have ADC conversion data
4184 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
4185 * ADC analog watchdog thresholds must be divided by 4.
4186 * - Oversampling ratio and shift selected to have ADC conversion data
4187 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
4188 * ADC analog watchdog thresholds match directly to ADC data register.
4189 * @note On this STM32 series, setting of this feature is conditioned to
4190 * ADC state:
4191 * ADC must be disabled or enabled without conversion on going
4192 * on group regular.
4193 * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n
4194 * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n
4195 * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n
4196 * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n
4197 * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n
4198 * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
4199 * @param ADCx ADC instance
4200 * @param AWDy This parameter can be one of the following values:
4201 * @arg @ref LL_ADC_AWD1
4202 * @arg @ref LL_ADC_AWD2
4203 * @arg @ref LL_ADC_AWD3
4204 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
4205 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
4206 * @retval None
4207 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)4208 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
4209 uint32_t AWDThresholdLowValue)
4210 {
4211 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
4212 /* position in register and register position depending on parameter */
4213 /* "AWDy". */
4214 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
4215 /* containing other bits reserved for other purpose. */
4216 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4217 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4218 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4219 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4220 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
4221 );
4222
4223 MODIFY_REG(*preg,
4224 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
4225 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
4226 }
4227
4228 /**
4229 * @brief Set ADC analog watchdog threshold value of threshold
4230 * high or low.
4231 * @note If values of both thresholds high or low must be set,
4232 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
4233 * @note In case of ADC resolution different of 12 bits,
4234 * analog watchdog thresholds data require a specific shift.
4235 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
4236 * @note On this STM32 series, there are 2 kinds of analog watchdog
4237 * instance:
4238 * - AWD standard (instance AWD1):
4239 * - channels monitored: can monitor 1 channel or all channels.
4240 * - groups monitored: ADC group regular.
4241 * - resolution: resolution is not limited (corresponds to
4242 * ADC resolution configured).
4243 * - AWD flexible (instances AWD2, AWD3):
4244 * - channels monitored: flexible on channels monitored, selection is
4245 * channel wise, from from 1 to all channels.
4246 * Specificity of this analog watchdog: Multiple channels can
4247 * be selected. For example:
4248 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4249 * - groups monitored: not selection possible (monitoring on both
4250 * groups regular and injected).
4251 * Channels selected are monitored on groups regular and injected:
4252 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4253 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4254 * - resolution: resolution is not limited (corresponds to
4255 * ADC resolution configured).
4256 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
4257 * impacted: the comparison of analog watchdog thresholds is done on
4258 * oversampling final computation (after ratio and shift application):
4259 * ADC data register bitfield [15:4] (12 most significant bits).
4260 * Examples:
4261 * - Oversampling ratio and shift selected to have ADC conversion data
4262 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
4263 * ADC analog watchdog thresholds must be divided by 16.
4264 * - Oversampling ratio and shift selected to have ADC conversion data
4265 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
4266 * ADC analog watchdog thresholds must be divided by 4.
4267 * - Oversampling ratio and shift selected to have ADC conversion data
4268 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
4269 * ADC analog watchdog thresholds match directly to ADC data register.
4270 * @note On this STM32 series, setting of this feature is not conditioned to
4271 * ADC state:
4272 * ADC can be disabled, enabled with or without conversion on going
4273 * on ADC group regular.
4274 * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n
4275 * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n
4276 * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n
4277 * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n
4278 * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n
4279 * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
4280 * @param ADCx ADC instance
4281 * @param AWDy This parameter can be one of the following values:
4282 * @arg @ref LL_ADC_AWD1
4283 * @arg @ref LL_ADC_AWD2
4284 * @arg @ref LL_ADC_AWD3
4285 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4286 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4287 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4288 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
4289 * @retval None
4290 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)4291 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
4292 uint32_t AWDThresholdValue)
4293 {
4294 /* Set bits with content of parameter "AWDThresholdValue" with bits */
4295 /* position in register and register position depending on parameters */
4296 /* "AWDThresholdsHighLow" and "AWDy". */
4297 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
4298 /* containing other bits reserved for other purpose. */
4299 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4300 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4301 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4302 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4303 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
4304
4305 MODIFY_REG(*preg,
4306 AWDThresholdsHighLow,
4307 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
4308 }
4309
4310 /**
4311 * @brief Get ADC analog watchdog threshold value of threshold high,
4312 * threshold low or raw data with ADC thresholds high and low
4313 * concatenated.
4314 * @note If raw data with ADC thresholds high and low is retrieved,
4315 * the data of each threshold high or low can be isolated
4316 * using helper macro:
4317 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
4318 * @note In case of ADC resolution different of 12 bits,
4319 * analog watchdog thresholds data require a specific shift.
4320 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
4321 * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n
4322 * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n
4323 * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n
4324 * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n
4325 * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n
4326 * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
4327 * @param ADCx ADC instance
4328 * @param AWDy This parameter can be one of the following values:
4329 * @arg @ref LL_ADC_AWD1
4330 * @arg @ref LL_ADC_AWD2
4331 * @arg @ref LL_ADC_AWD3
4332 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4333 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4334 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4335 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
4336 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4337 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)4338 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
4339 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
4340 {
4341 /* Set bits with content of parameter "AWDThresholdValue" with bits */
4342 /* position in register and register position depending on parameters */
4343 /* "AWDThresholdsHighLow" and "AWDy". */
4344 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
4345 /* containing other bits reserved for other purpose. */
4346 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4347 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4348 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4349 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4350 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
4351
4352 return (uint32_t)(READ_BIT(*preg,
4353 (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
4354 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
4355 & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1)));
4356 }
4357
4358 /**
4359 * @}
4360 */
4361
4362 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
4363 * @{
4364 */
4365
4366 /**
4367 * @brief Set ADC oversampling scope.
4368 * @note On this STM32 series, setting of this feature is conditioned to
4369 * ADC state:
4370 * ADC must be disabled.
4371 * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope
4372 * @param ADCx ADC instance
4373 * @param OvsScope This parameter can be one of the following values:
4374 * @arg @ref LL_ADC_OVS_DISABLE
4375 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4376 * @retval None
4377 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)4378 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
4379 {
4380 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
4381 }
4382
4383 /**
4384 * @brief Get ADC oversampling scope.
4385 * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope
4386 * @param ADCx ADC instance
4387 * @retval Returned value can be one of the following values:
4388 * @arg @ref LL_ADC_OVS_DISABLE
4389 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4390 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)4391 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
4392 {
4393 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
4394 }
4395
4396 /**
4397 * @brief Set ADC oversampling discontinuous mode (triggered mode)
4398 * on the selected ADC group.
4399 * @note Number of oversampled conversions are done either in:
4400 * - continuous mode (all conversions of oversampling ratio
4401 * are done from 1 trigger)
4402 * - discontinuous mode (each conversion of oversampling ratio
4403 * needs a trigger)
4404 * @note On this STM32 series, setting of this feature is conditioned to
4405 * ADC state:
4406 * ADC must be disabled.
4407 * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
4408 * @param ADCx ADC instance
4409 * @param OverSamplingDiscont This parameter can be one of the following values:
4410 * @arg @ref LL_ADC_OVS_REG_CONT
4411 * @arg @ref LL_ADC_OVS_REG_DISCONT
4412 * @retval None
4413 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)4414 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
4415 {
4416 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
4417 }
4418
4419 /**
4420 * @brief Get ADC oversampling discontinuous mode (triggered mode)
4421 * on the selected ADC group.
4422 * @note Number of oversampled conversions are done either in:
4423 * - continuous mode (all conversions of oversampling ratio
4424 * are done from 1 trigger)
4425 * - discontinuous mode (each conversion of oversampling ratio
4426 * needs a trigger)
4427 * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
4428 * @param ADCx ADC instance
4429 * @retval Returned value can be one of the following values:
4430 * @arg @ref LL_ADC_OVS_REG_CONT
4431 * @arg @ref LL_ADC_OVS_REG_DISCONT
4432 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)4433 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
4434 {
4435 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
4436 }
4437
4438 /**
4439 * @brief Set ADC oversampling
4440 * @note This function set the 2 items of oversampling configuration:
4441 * - ratio
4442 * - shift
4443 * @note On this STM32 series, setting of this feature is conditioned to
4444 * ADC state:
4445 * ADC must be disabled.
4446 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
4447 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
4448 * @param ADCx ADC instance
4449 * @param Ratio This parameter can be one of the following values:
4450 * @arg @ref LL_ADC_OVS_RATIO_2
4451 * @arg @ref LL_ADC_OVS_RATIO_4
4452 * @arg @ref LL_ADC_OVS_RATIO_8
4453 * @arg @ref LL_ADC_OVS_RATIO_16
4454 * @arg @ref LL_ADC_OVS_RATIO_32
4455 * @arg @ref LL_ADC_OVS_RATIO_64
4456 * @arg @ref LL_ADC_OVS_RATIO_128
4457 * @arg @ref LL_ADC_OVS_RATIO_256
4458 * @param Shift This parameter can be one of the following values:
4459 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4460 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4461 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4462 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4463 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4464 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4465 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4466 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4467 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4468 * @retval None
4469 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)4470 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
4471 {
4472 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
4473 }
4474
4475 /**
4476 * @brief Get ADC oversampling ratio
4477 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
4478 * @param ADCx ADC instance
4479 * @retval Ratio This parameter can be one of the following values:
4480 * @arg @ref LL_ADC_OVS_RATIO_2
4481 * @arg @ref LL_ADC_OVS_RATIO_4
4482 * @arg @ref LL_ADC_OVS_RATIO_8
4483 * @arg @ref LL_ADC_OVS_RATIO_16
4484 * @arg @ref LL_ADC_OVS_RATIO_32
4485 * @arg @ref LL_ADC_OVS_RATIO_64
4486 * @arg @ref LL_ADC_OVS_RATIO_128
4487 * @arg @ref LL_ADC_OVS_RATIO_256
4488 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)4489 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
4490 {
4491 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
4492 }
4493
4494 /**
4495 * @brief Get ADC oversampling shift
4496 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
4497 * @param ADCx ADC instance
4498 * @retval Shift This parameter can be one of the following values:
4499 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4500 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4501 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4502 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4503 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4504 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4505 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4506 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4507 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4508 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)4509 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
4510 {
4511 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
4512 }
4513
4514 /**
4515 * @}
4516 */
4517
4518 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
4519 * @{
4520 */
4521
4522 /**
4523 * @brief Enable ADC instance internal voltage regulator.
4524 * @note On this STM32 series, there are three possibilities to enable
4525 * the voltage regulator:
4526 * - by enabling it manually
4527 * using function @ref LL_ADC_EnableInternalRegulator().
4528 * - by launching a calibration
4529 * using function @ref LL_ADC_StartCalibration().
4530 * - by enabling the ADC
4531 * using function @ref LL_ADC_Enable().
4532 * @note On this STM32 series, after ADC internal voltage regulator enable,
4533 * a delay for ADC internal voltage regulator stabilization
4534 * is required before performing a ADC calibration or ADC enable.
4535 * Refer to device datasheet, parameter "tADCVREG_STUP".
4536 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
4537 * @note On this STM32 series, setting of this feature is conditioned to
4538 * ADC state:
4539 * ADC must be ADC disabled.
4540 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
4541 * @param ADCx ADC instance
4542 * @retval None
4543 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)4544 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
4545 {
4546 /* Note: Write register with some additional bits forced to state reset */
4547 /* instead of modifying only the selected bit for this function, */
4548 /* to not interfere with bits with HW property "rs". */
4549 MODIFY_REG(ADCx->CR,
4550 ADC_CR_BITS_PROPERTY_RS,
4551 ADC_CR_ADVREGEN);
4552 }
4553
4554 /**
4555 * @brief Disable ADC internal voltage regulator.
4556 * @note On this STM32 series, setting of this feature is conditioned to
4557 * ADC state:
4558 * ADC must be ADC disabled.
4559 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
4560 * @param ADCx ADC instance
4561 * @retval None
4562 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)4563 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
4564 {
4565 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
4566 }
4567
4568 /**
4569 * @brief Get the selected ADC instance internal voltage regulator state.
4570 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
4571 * @param ADCx ADC instance
4572 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
4573 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)4574 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
4575 {
4576 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
4577 }
4578
4579 /**
4580 * @brief Enable the selected ADC instance.
4581 * @note On this STM32 series, after ADC enable, a delay for
4582 * ADC internal analog stabilization is required before performing a
4583 * ADC conversion start.
4584 * Refer to device datasheet, parameter tSTAB.
4585 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4586 * is enabled and when conversion clock is active.
4587 * (not only core clock: this ADC has a dual clock domain)
4588 * @note On this STM32 series, setting of this feature is conditioned to
4589 * ADC state:
4590 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
4591 * @rmtoll CR ADEN LL_ADC_Enable
4592 * @param ADCx ADC instance
4593 * @retval None
4594 */
LL_ADC_Enable(ADC_TypeDef * ADCx)4595 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
4596 {
4597 /* Note: Write register with some additional bits forced to state reset */
4598 /* instead of modifying only the selected bit for this function, */
4599 /* to not interfere with bits with HW property "rs". */
4600 MODIFY_REG(ADCx->CR,
4601 ADC_CR_BITS_PROPERTY_RS,
4602 ADC_CR_ADEN);
4603 }
4604
4605 /**
4606 * @brief Disable the selected ADC instance.
4607 * @note On this STM32 series, setting of this feature is conditioned to
4608 * ADC state:
4609 * ADC must be not disabled. Must be enabled without conversion on going
4610 * on group regular.
4611 * @rmtoll CR ADDIS LL_ADC_Disable
4612 * @param ADCx ADC instance
4613 * @retval None
4614 */
LL_ADC_Disable(ADC_TypeDef * ADCx)4615 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
4616 {
4617 /* Note: Write register with some additional bits forced to state reset */
4618 /* instead of modifying only the selected bit for this function, */
4619 /* to not interfere with bits with HW property "rs". */
4620 MODIFY_REG(ADCx->CR,
4621 ADC_CR_BITS_PROPERTY_RS,
4622 ADC_CR_ADDIS);
4623 }
4624
4625 /**
4626 * @brief Get the selected ADC instance enable state.
4627 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4628 * is enabled and when conversion clock is active.
4629 * (not only core clock: this ADC has a dual clock domain)
4630 * @rmtoll CR ADEN LL_ADC_IsEnabled
4631 * @param ADCx ADC instance
4632 * @retval 0: ADC is disabled, 1: ADC is enabled.
4633 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)4634 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
4635 {
4636 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
4637 }
4638
4639 /**
4640 * @brief Get the selected ADC instance disable state.
4641 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
4642 * @param ADCx ADC instance
4643 * @retval 0: no ADC disable command on going.
4644 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)4645 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
4646 {
4647 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
4648 }
4649
4650 /**
4651 * @brief Start ADC calibration in the mode single-ended
4652 * or differential (for devices with differential mode available).
4653 * @note On this STM32 series, a minimum number of ADC clock cycles
4654 * are required between ADC end of calibration and ADC enable.
4655 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
4656 * @note In case of usage of ADC with DMA transfer:
4657 * On this STM32 series, ADC DMA transfer request should be disabled
4658 * during calibration:
4659 * Calibration factor is available in data register
4660 * and also transferred by DMA.
4661 * To not insert ADC calibration factor among ADC conversion data
4662 * in array variable, DMA transfer must be disabled during
4663 * calibration.
4664 * (DMA transfer setting backup and disable before calibration,
4665 * DMA transfer setting restore after calibration.
4666 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
4667 * @ref LL_ADC_REG_SetDMATransfer() ).
4668 * @note In case of usage of feature auto power-off:
4669 * This mode must be disabled during calibration
4670 * Refer to function @ref LL_ADC_SetLowPowerMode().
4671 * @note On this STM32 series, setting of this feature is conditioned to
4672 * ADC state:
4673 * ADC must be ADC disabled.
4674 * @rmtoll CR ADCAL LL_ADC_StartCalibration
4675 * @param ADCx ADC instance
4676 * @retval None
4677 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)4678 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
4679 {
4680 /* Note: Write register with some additional bits forced to state reset */
4681 /* instead of modifying only the selected bit for this function, */
4682 /* to not interfere with bits with HW property "rs". */
4683 MODIFY_REG(ADCx->CR,
4684 ADC_CR_BITS_PROPERTY_RS,
4685 ADC_CR_ADCAL);
4686 }
4687
4688 /**
4689 * @brief Get ADC calibration state.
4690 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
4691 * @param ADCx ADC instance
4692 * @retval 0: calibration complete, 1: calibration in progress.
4693 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)4694 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
4695 {
4696 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
4697 }
4698
4699 /**
4700 * @}
4701 */
4702
4703 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
4704 * @{
4705 */
4706
4707 /**
4708 * @brief Start ADC group regular conversion.
4709 * @note On this STM32 series, this function is relevant for both
4710 * internal trigger (SW start) and external trigger:
4711 * - If ADC trigger has been set to software start, ADC conversion
4712 * starts immediately.
4713 * - If ADC trigger has been set to external trigger, ADC conversion
4714 * will start at next trigger event (on the selected trigger edge)
4715 * following the ADC start conversion command.
4716 * @note On this STM32 series, setting of this feature is conditioned to
4717 * ADC state:
4718 * ADC must be enabled without conversion on going on group regular,
4719 * without conversion stop command on going on group regular,
4720 * without ADC disable command on going.
4721 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
4722 * @param ADCx ADC instance
4723 * @retval None
4724 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)4725 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
4726 {
4727 /* Note: Write register with some additional bits forced to state reset */
4728 /* instead of modifying only the selected bit for this function, */
4729 /* to not interfere with bits with HW property "rs". */
4730 MODIFY_REG(ADCx->CR,
4731 ADC_CR_BITS_PROPERTY_RS,
4732 ADC_CR_ADSTART);
4733 }
4734
4735 /**
4736 * @brief Stop ADC group regular conversion.
4737 * @note On this STM32 series, setting of this feature is conditioned to
4738 * ADC state:
4739 * ADC must be enabled (potentially with conversion on going on group regular),
4740 * without ADC disable command on going.
4741 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
4742 * @param ADCx ADC instance
4743 * @retval None
4744 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)4745 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
4746 {
4747 /* Note: Write register with some additional bits forced to state reset */
4748 /* instead of modifying only the selected bit for this function, */
4749 /* to not interfere with bits with HW property "rs". */
4750 MODIFY_REG(ADCx->CR,
4751 ADC_CR_BITS_PROPERTY_RS,
4752 ADC_CR_ADSTP);
4753 }
4754
4755 /**
4756 * @brief Get ADC group regular conversion state.
4757 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
4758 * @param ADCx ADC instance
4759 * @retval 0: no conversion is on going on ADC group regular.
4760 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)4761 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
4762 {
4763 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
4764 }
4765
4766 /**
4767 * @brief Get ADC group regular command of conversion stop state
4768 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
4769 * @param ADCx ADC instance
4770 * @retval 0: no command of conversion stop is on going on ADC group regular.
4771 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)4772 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
4773 {
4774 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
4775 }
4776
4777 /**
4778 * @brief Get ADC group regular conversion data, range fit for
4779 * all ADC configurations: all ADC resolutions and
4780 * all oversampling increased data width (for devices
4781 * with feature oversampling).
4782 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
4783 * @param ADCx ADC instance
4784 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4785 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)4786 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
4787 {
4788 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4789 }
4790
4791 /**
4792 * @brief Get ADC group regular conversion data, range fit for
4793 * ADC resolution 12 bits.
4794 * @note For devices with feature oversampling: Oversampling
4795 * can increase data width, function for extended range
4796 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4797 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
4798 * @param ADCx ADC instance
4799 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4800 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)4801 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
4802 {
4803 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x00000FFFUL);
4804 }
4805
4806 /**
4807 * @brief Get ADC group regular conversion data, range fit for
4808 * ADC resolution 10 bits.
4809 * @note For devices with feature oversampling: Oversampling
4810 * can increase data width, function for extended range
4811 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4812 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
4813 * @param ADCx ADC instance
4814 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4815 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)4816 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
4817 {
4818 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000003FFUL);
4819 }
4820
4821 /**
4822 * @brief Get ADC group regular conversion data, range fit for
4823 * ADC resolution 8 bits.
4824 * @note For devices with feature oversampling: Oversampling
4825 * can increase data width, function for extended range
4826 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4827 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
4828 * @param ADCx ADC instance
4829 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4830 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)4831 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
4832 {
4833 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL);
4834 }
4835
4836 /**
4837 * @brief Get ADC group regular conversion data, range fit for
4838 * ADC resolution 6 bits.
4839 * @note For devices with feature oversampling: Oversampling
4840 * can increase data width, function for extended range
4841 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4842 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
4843 * @param ADCx ADC instance
4844 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4845 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)4846 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
4847 {
4848 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x0000003FUL);
4849 }
4850
4851 /**
4852 * @}
4853 */
4854
4855 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4856 * @{
4857 */
4858
4859 /**
4860 * @brief Get flag ADC ready.
4861 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4862 * is enabled and when conversion clock is active.
4863 * (not only core clock: this ADC has a dual clock domain)
4864 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
4865 * @param ADCx ADC instance
4866 * @retval State of bit (1 or 0).
4867 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)4868 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
4869 {
4870 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
4871 }
4872
4873 /**
4874 * @brief Get flag ADC channel configuration ready.
4875 * @note On this STM32 series, after modifying sequencer
4876 * it is mandatory to wait for the assertion of CCRDY flag
4877 * using @ref LL_ADC_IsActiveFlag_CCRDY().
4878 * Otherwise, performing some actions (configuration update,
4879 * ADC conversion start, ... ) will be ignored.
4880 * Functions requiring wait for CCRDY flag are:
4881 * @ref LL_ADC_REG_SetSequencerLength()
4882 * @ref LL_ADC_REG_SetSequencerRanks()
4883 * @ref LL_ADC_REG_SetSequencerChannels()
4884 * @ref LL_ADC_REG_SetSequencerChAdd()
4885 * @ref LL_ADC_REG_SetSequencerChRem()
4886 * @ref LL_ADC_REG_SetSequencerScanDirection()
4887 * @ref LL_ADC_REG_SetSequencerConfigurable()
4888 * @note Duration of ADC channel configuration ready: CCRDY handshake
4889 * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
4890 * has been changed.
4891 * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY
4892 * @param ADCx ADC instance
4893 * @retval State of bit (1 or 0).
4894 */
LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef * ADCx)4895 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx)
4896 {
4897 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
4898 }
4899
4900 /**
4901 * @brief Get flag ADC group regular end of unitary conversion.
4902 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
4903 * @param ADCx ADC instance
4904 * @retval State of bit (1 or 0).
4905 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)4906 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
4907 {
4908 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
4909 }
4910
4911 /**
4912 * @brief Get flag ADC group regular end of sequence conversions.
4913 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
4914 * @param ADCx ADC instance
4915 * @retval State of bit (1 or 0).
4916 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)4917 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
4918 {
4919 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
4920 }
4921
4922 /**
4923 * @brief Get flag ADC group regular overrun.
4924 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
4925 * @param ADCx ADC instance
4926 * @retval State of bit (1 or 0).
4927 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)4928 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
4929 {
4930 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
4931 }
4932
4933 /**
4934 * @brief Get flag ADC group regular end of sampling phase.
4935 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
4936 * @param ADCx ADC instance
4937 * @retval State of bit (1 or 0).
4938 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)4939 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
4940 {
4941 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
4942 }
4943
4944 /**
4945 * @brief Get flag ADC analog watchdog 1 flag
4946 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
4947 * @param ADCx ADC instance
4948 * @retval State of bit (1 or 0).
4949 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)4950 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
4951 {
4952 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
4953 }
4954
4955 /**
4956 * @brief Get flag ADC analog watchdog 2.
4957 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
4958 * @param ADCx ADC instance
4959 * @retval State of bit (1 or 0).
4960 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)4961 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
4962 {
4963 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
4964 }
4965
4966 /**
4967 * @brief Get flag ADC analog watchdog 3.
4968 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
4969 * @param ADCx ADC instance
4970 * @retval State of bit (1 or 0).
4971 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)4972 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
4973 {
4974 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
4975 }
4976
4977 /**
4978 * @brief Get flag ADC end of calibration.
4979 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
4980 * @param ADCx ADC instance
4981 * @retval State of bit (1 or 0).
4982 */
LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef * ADCx)4983 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx)
4984 {
4985 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
4986 }
4987
4988 /**
4989 * @brief Clear flag ADC ready.
4990 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4991 * is enabled and when conversion clock is active.
4992 * (not only core clock: this ADC has a dual clock domain)
4993 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
4994 * @param ADCx ADC instance
4995 * @retval None
4996 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)4997 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
4998 {
4999 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
5000 }
5001
5002 /**
5003 * @brief Clear flag ADC channel configuration ready.
5004 * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY
5005 * @param ADCx ADC instance
5006 * @retval State of bit (1 or 0).
5007 */
LL_ADC_ClearFlag_CCRDY(ADC_TypeDef * ADCx)5008 __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
5009 {
5010 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
5011 }
5012
5013 /**
5014 * @brief Clear flag ADC group regular end of unitary conversion.
5015 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
5016 * @param ADCx ADC instance
5017 * @retval None
5018 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)5019 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
5020 {
5021 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
5022 }
5023
5024 /**
5025 * @brief Clear flag ADC group regular end of sequence conversions.
5026 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
5027 * @param ADCx ADC instance
5028 * @retval None
5029 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)5030 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
5031 {
5032 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
5033 }
5034
5035 /**
5036 * @brief Clear flag ADC group regular overrun.
5037 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
5038 * @param ADCx ADC instance
5039 * @retval None
5040 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)5041 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
5042 {
5043 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
5044 }
5045
5046 /**
5047 * @brief Clear flag ADC group regular end of sampling phase.
5048 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
5049 * @param ADCx ADC instance
5050 * @retval None
5051 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)5052 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
5053 {
5054 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
5055 }
5056
5057 /**
5058 * @brief Clear flag ADC analog watchdog 1.
5059 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
5060 * @param ADCx ADC instance
5061 * @retval None
5062 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)5063 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
5064 {
5065 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
5066 }
5067
5068 /**
5069 * @brief Clear flag ADC analog watchdog 2.
5070 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
5071 * @param ADCx ADC instance
5072 * @retval None
5073 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)5074 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
5075 {
5076 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
5077 }
5078
5079 /**
5080 * @brief Clear flag ADC analog watchdog 3.
5081 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
5082 * @param ADCx ADC instance
5083 * @retval None
5084 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)5085 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
5086 {
5087 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
5088 }
5089
5090 /**
5091 * @brief Clear flag ADC end of calibration.
5092 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
5093 * @param ADCx ADC instance
5094 * @retval None
5095 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)5096 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
5097 {
5098 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
5099 }
5100
5101 /**
5102 * @}
5103 */
5104
5105 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
5106 * @{
5107 */
5108
5109 /**
5110 * @brief Enable ADC ready.
5111 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
5112 * @param ADCx ADC instance
5113 * @retval None
5114 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)5115 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
5116 {
5117 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
5118 }
5119
5120 /**
5121 * @brief Enable interruption ADC channel configuration ready.
5122 * @rmtoll IER CCRDYIE LL_ADC_EnableIT_CCRDY
5123 * @param ADCx ADC instance
5124 * @retval State of bit (1 or 0).
5125 */
LL_ADC_EnableIT_CCRDY(ADC_TypeDef * ADCx)5126 __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
5127 {
5128 SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
5129 }
5130
5131 /**
5132 * @brief Enable interruption ADC group regular end of unitary conversion.
5133 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
5134 * @param ADCx ADC instance
5135 * @retval None
5136 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)5137 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
5138 {
5139 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
5140 }
5141
5142 /**
5143 * @brief Enable interruption ADC group regular end of sequence conversions.
5144 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
5145 * @param ADCx ADC instance
5146 * @retval None
5147 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)5148 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
5149 {
5150 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
5151 }
5152
5153 /**
5154 * @brief Enable ADC group regular interruption overrun.
5155 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
5156 * @param ADCx ADC instance
5157 * @retval None
5158 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)5159 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
5160 {
5161 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
5162 }
5163
5164 /**
5165 * @brief Enable interruption ADC group regular end of sampling.
5166 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
5167 * @param ADCx ADC instance
5168 * @retval None
5169 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)5170 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
5171 {
5172 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
5173 }
5174
5175 /**
5176 * @brief Enable interruption ADC analog watchdog 1.
5177 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
5178 * @param ADCx ADC instance
5179 * @retval None
5180 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)5181 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
5182 {
5183 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
5184 }
5185
5186 /**
5187 * @brief Enable interruption ADC analog watchdog 2.
5188 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
5189 * @param ADCx ADC instance
5190 * @retval None
5191 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)5192 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
5193 {
5194 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
5195 }
5196
5197 /**
5198 * @brief Enable interruption ADC analog watchdog 3.
5199 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
5200 * @param ADCx ADC instance
5201 * @retval None
5202 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)5203 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
5204 {
5205 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
5206 }
5207
5208 /**
5209 * @brief Enable interruption ADC end of calibration.
5210 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
5211 * @param ADCx ADC instance
5212 * @retval None
5213 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)5214 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
5215 {
5216 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
5217 }
5218
5219 /**
5220 * @brief Disable interruption ADC ready.
5221 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
5222 * @param ADCx ADC instance
5223 * @retval None
5224 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)5225 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
5226 {
5227 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
5228 }
5229
5230 /**
5231 * @brief Disable interruption ADC channel configuration ready.
5232 * @rmtoll IER CCRDYIE LL_ADC_DisableIT_CCRDY
5233 * @param ADCx ADC instance
5234 * @retval State of bit (1 or 0).
5235 */
LL_ADC_DisableIT_CCRDY(ADC_TypeDef * ADCx)5236 __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
5237 {
5238 CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
5239 }
5240
5241 /**
5242 * @brief Disable interruption ADC group regular end of unitary conversion.
5243 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
5244 * @param ADCx ADC instance
5245 * @retval None
5246 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)5247 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
5248 {
5249 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
5250 }
5251
5252 /**
5253 * @brief Disable interruption ADC group regular end of sequence conversions.
5254 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
5255 * @param ADCx ADC instance
5256 * @retval None
5257 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)5258 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
5259 {
5260 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
5261 }
5262
5263 /**
5264 * @brief Disable interruption ADC group regular overrun.
5265 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
5266 * @param ADCx ADC instance
5267 * @retval None
5268 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)5269 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
5270 {
5271 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
5272 }
5273
5274 /**
5275 * @brief Disable interruption ADC group regular end of sampling.
5276 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
5277 * @param ADCx ADC instance
5278 * @retval None
5279 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)5280 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
5281 {
5282 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
5283 }
5284
5285 /**
5286 * @brief Disable interruption ADC analog watchdog 1.
5287 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
5288 * @param ADCx ADC instance
5289 * @retval None
5290 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)5291 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
5292 {
5293 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
5294 }
5295
5296 /**
5297 * @brief Disable interruption ADC analog watchdog 2.
5298 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
5299 * @param ADCx ADC instance
5300 * @retval None
5301 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)5302 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
5303 {
5304 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
5305 }
5306
5307 /**
5308 * @brief Disable interruption ADC analog watchdog 3.
5309 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
5310 * @param ADCx ADC instance
5311 * @retval None
5312 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)5313 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
5314 {
5315 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
5316 }
5317
5318 /**
5319 * @brief Disable interruption ADC end of calibration.
5320 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
5321 * @param ADCx ADC instance
5322 * @retval None
5323 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)5324 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
5325 {
5326 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
5327 }
5328
5329 /**
5330 * @brief Get state of interruption ADC ready
5331 * (0: interrupt disabled, 1: interrupt enabled).
5332 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
5333 * @param ADCx ADC instance
5334 * @retval State of bit (1 or 0).
5335 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)5336 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
5337 {
5338 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
5339 }
5340
5341 /**
5342 * @brief Get state of interruption ADC channel configuration ready.
5343 * @rmtoll IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY
5344 * @param ADCx ADC instance
5345 * @retval State of bit (1 or 0).
5346 */
LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef * ADCx)5347 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx)
5348 {
5349 return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
5350 }
5351
5352 /**
5353 * @brief Get state of interruption ADC group regular end of unitary conversion
5354 * (0: interrupt disabled, 1: interrupt enabled).
5355 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
5356 * @param ADCx ADC instance
5357 * @retval State of bit (1 or 0).
5358 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)5359 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
5360 {
5361 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
5362 }
5363
5364 /**
5365 * @brief Get state of interruption ADC group regular end of sequence conversions
5366 * (0: interrupt disabled, 1: interrupt enabled).
5367 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
5368 * @param ADCx ADC instance
5369 * @retval State of bit (1 or 0).
5370 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)5371 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
5372 {
5373 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
5374 }
5375
5376 /**
5377 * @brief Get state of interruption ADC group regular overrun
5378 * (0: interrupt disabled, 1: interrupt enabled).
5379 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
5380 * @param ADCx ADC instance
5381 * @retval State of bit (1 or 0).
5382 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)5383 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
5384 {
5385 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
5386 }
5387
5388 /**
5389 * @brief Get state of interruption ADC group regular end of sampling
5390 * (0: interrupt disabled, 1: interrupt enabled).
5391 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
5392 * @param ADCx ADC instance
5393 * @retval State of bit (1 or 0).
5394 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)5395 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
5396 {
5397 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
5398 }
5399
5400 /**
5401 * @brief Get state of interruption ADC analog watchdog 1
5402 * (0: interrupt disabled, 1: interrupt enabled).
5403 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
5404 * @param ADCx ADC instance
5405 * @retval State of bit (1 or 0).
5406 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)5407 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
5408 {
5409 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
5410 }
5411
5412 /**
5413 * @brief Get state of interruption Get ADC analog watchdog 2
5414 * (0: interrupt disabled, 1: interrupt enabled).
5415 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
5416 * @param ADCx ADC instance
5417 * @retval State of bit (1 or 0).
5418 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)5419 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
5420 {
5421 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
5422 }
5423
5424 /**
5425 * @brief Get state of interruption Get ADC analog watchdog 3
5426 * (0: interrupt disabled, 1: interrupt enabled).
5427 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
5428 * @param ADCx ADC instance
5429 * @retval State of bit (1 or 0).
5430 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)5431 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
5432 {
5433 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
5434 }
5435
5436 /**
5437 * @brief Get state of interruption ADC end of calibration
5438 * (0: interrupt disabled, 1: interrupt enabled).
5439 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
5440 * @param ADCx ADC instance
5441 * @retval State of bit (1 or 0).
5442 */
LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef * ADCx)5443 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
5444 {
5445 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
5446 }
5447
5448 /**
5449 * @}
5450 */
5451
5452 #if defined(USE_FULL_LL_DRIVER)
5453 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
5454 * @{
5455 */
5456
5457 /* Initialization of some features of ADC common parameters and multimode */
5458 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
5459 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5460 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5461
5462 /* De-initialization of ADC instance */
5463 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
5464
5465 /* Initialization of some features of ADC instance */
5466 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
5467 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
5468
5469 /* Initialization of some features of ADC instance and ADC group regular */
5470 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5471 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5472
5473 /**
5474 * @}
5475 */
5476 #endif /* USE_FULL_LL_DRIVER */
5477
5478 /**
5479 * @}
5480 */
5481
5482 /**
5483 * @}
5484 */
5485
5486 #endif /* ADC1 */
5487
5488 /**
5489 * @}
5490 */
5491
5492 #ifdef __cplusplus
5493 }
5494 #endif
5495
5496 #endif /* STM32G0xx_LL_ADC_H */
5497
