1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F7xx_LL_TIM_H
21 #define __STM32F7xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx.h"
29
30 /** @addtogroup STM32F7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 #if defined(TIM_BREAK_INPUT_SUPPORT)
119 /* Defines used for the bit position in the register and perform offsets */
120 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
121
122 /* Generic bit definitions for TIMx_AF1 register */
123 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
124 #endif /* TIM_BREAK_INPUT_SUPPORT */
125
126 /* Remap mask definitions */
127 #define TIMx_OR_RMP_SHIFT 16U
128 #define TIMx_OR_RMP_MASK 0x0000FFFFU
129 #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
130 #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
131 #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
132
133 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
134 #define DT_DELAY_1 ((uint8_t)0x7F)
135 #define DT_DELAY_2 ((uint8_t)0x3F)
136 #define DT_DELAY_3 ((uint8_t)0x1F)
137 #define DT_DELAY_4 ((uint8_t)0x1F)
138
139 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
140 #define DT_RANGE_1 ((uint8_t)0x00)
141 #define DT_RANGE_2 ((uint8_t)0x80)
142 #define DT_RANGE_3 ((uint8_t)0xC0)
143 #define DT_RANGE_4 ((uint8_t)0xE0)
144
145
146 /**
147 * @}
148 */
149
150 /* Private macros ------------------------------------------------------------*/
151 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
152 * @{
153 */
154 /** @brief Convert channel id into channel index.
155 * @param __CHANNEL__ This parameter can be one of the following values:
156 * @arg @ref LL_TIM_CHANNEL_CH1
157 * @arg @ref LL_TIM_CHANNEL_CH1N
158 * @arg @ref LL_TIM_CHANNEL_CH2
159 * @arg @ref LL_TIM_CHANNEL_CH2N
160 * @arg @ref LL_TIM_CHANNEL_CH3
161 * @arg @ref LL_TIM_CHANNEL_CH3N
162 * @arg @ref LL_TIM_CHANNEL_CH4
163 * @arg @ref LL_TIM_CHANNEL_CH5
164 * @arg @ref LL_TIM_CHANNEL_CH6
165 * @retval none
166 */
167 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
168 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
172 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
173 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
174 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
175 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
176
177 /** @brief Calculate the deadtime sampling period(in ps).
178 * @param __TIMCLK__ timer input clock frequency (in Hz).
179 * @param __CKD__ This parameter can be one of the following values:
180 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
181 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
182 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
183 * @retval none
184 */
185 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
186 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
187 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
188 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
189 /**
190 * @}
191 */
192
193
194 /* Exported types ------------------------------------------------------------*/
195 #if defined(USE_FULL_LL_DRIVER)
196 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
197 * @{
198 */
199
200 /**
201 * @brief TIM Time Base configuration structure definition.
202 */
203 typedef struct
204 {
205 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
206 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
207
208 This feature can be modified afterwards using unitary function
209 @ref LL_TIM_SetPrescaler().*/
210
211 uint32_t CounterMode; /*!< Specifies the counter mode.
212 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
213
214 This feature can be modified afterwards using unitary function
215 @ref LL_TIM_SetCounterMode().*/
216
217 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
218 Auto-Reload Register at the next update event.
219 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
220 Some timer instances may support 32 bits counters. In that case this parameter must
221 be a number between 0x0000 and 0xFFFFFFFF.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetAutoReload().*/
225
226 uint32_t ClockDivision; /*!< Specifies the clock division.
227 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
228
229 This feature can be modified afterwards using unitary function
230 @ref LL_TIM_SetClockDivision().*/
231
232 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
233 reaches zero, an update event is generated and counting restarts
234 from the RCR value (N).
235 This means in PWM mode that (N+1) corresponds to:
236 - the number of PWM periods in edge-aligned mode
237 - the number of half PWM period in center-aligned mode
238 GP timers: this parameter must be a number between Min_Data = 0x00 and
239 Max_Data = 0xFF.
240 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
241 Max_Data = 0xFFFF.
242
243 This feature can be modified afterwards using unitary function
244 @ref LL_TIM_SetRepetitionCounter().*/
245 } LL_TIM_InitTypeDef;
246
247 /**
248 * @brief TIM Output Compare configuration structure definition.
249 */
250 typedef struct
251 {
252 uint32_t OCMode; /*!< Specifies the output mode.
253 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
254
255 This feature can be modified afterwards using unitary function
256 @ref LL_TIM_OC_SetMode().*/
257
258 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
259 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
260
261 This feature can be modified afterwards using unitary functions
262 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
263
264 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
265 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
266
267 This feature can be modified afterwards using unitary functions
268 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
269
270 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
271 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
272
273 This feature can be modified afterwards using unitary function
274 LL_TIM_OC_SetCompareCHx (x=1..6).*/
275
276 uint32_t OCPolarity; /*!< Specifies the output polarity.
277 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
278
279 This feature can be modified afterwards using unitary function
280 @ref LL_TIM_OC_SetPolarity().*/
281
282 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
283 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
284
285 This feature can be modified afterwards using unitary function
286 @ref LL_TIM_OC_SetPolarity().*/
287
288
289 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
290 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
291
292 This feature can be modified afterwards using unitary function
293 @ref LL_TIM_OC_SetIdleState().*/
294
295 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
296 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
297
298 This feature can be modified afterwards using unitary function
299 @ref LL_TIM_OC_SetIdleState().*/
300 } LL_TIM_OC_InitTypeDef;
301
302 /**
303 * @brief TIM Input Capture configuration structure definition.
304 */
305
306 typedef struct
307 {
308
309 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
310 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
311
312 This feature can be modified afterwards using unitary function
313 @ref LL_TIM_IC_SetPolarity().*/
314
315 uint32_t ICActiveInput; /*!< Specifies the input.
316 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
317
318 This feature can be modified afterwards using unitary function
319 @ref LL_TIM_IC_SetActiveInput().*/
320
321 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
322 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
323
324 This feature can be modified afterwards using unitary function
325 @ref LL_TIM_IC_SetPrescaler().*/
326
327 uint32_t ICFilter; /*!< Specifies the input capture filter.
328 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
329
330 This feature can be modified afterwards using unitary function
331 @ref LL_TIM_IC_SetFilter().*/
332 } LL_TIM_IC_InitTypeDef;
333
334
335 /**
336 * @brief TIM Encoder interface configuration structure definition.
337 */
338 typedef struct
339 {
340 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
341 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
342
343 This feature can be modified afterwards using unitary function
344 @ref LL_TIM_SetEncoderMode().*/
345
346 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
347 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
348
349 This feature can be modified afterwards using unitary function
350 @ref LL_TIM_IC_SetPolarity().*/
351
352 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
353 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
354
355 This feature can be modified afterwards using unitary function
356 @ref LL_TIM_IC_SetActiveInput().*/
357
358 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
359 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
360
361 This feature can be modified afterwards using unitary function
362 @ref LL_TIM_IC_SetPrescaler().*/
363
364 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
365 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
366
367 This feature can be modified afterwards using unitary function
368 @ref LL_TIM_IC_SetFilter().*/
369
370 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
371 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
372
373 This feature can be modified afterwards using unitary function
374 @ref LL_TIM_IC_SetPolarity().*/
375
376 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
377 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
378
379 This feature can be modified afterwards using unitary function
380 @ref LL_TIM_IC_SetActiveInput().*/
381
382 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
383 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
384
385 This feature can be modified afterwards using unitary function
386 @ref LL_TIM_IC_SetPrescaler().*/
387
388 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
389 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
390
391 This feature can be modified afterwards using unitary function
392 @ref LL_TIM_IC_SetFilter().*/
393
394 } LL_TIM_ENCODER_InitTypeDef;
395
396 /**
397 * @brief TIM Hall sensor interface configuration structure definition.
398 */
399 typedef struct
400 {
401
402 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
403 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
404
405 This feature can be modified afterwards using unitary function
406 @ref LL_TIM_IC_SetPolarity().*/
407
408 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
409 Prescaler must be set to get a maximum counter period longer than the
410 time interval between 2 consecutive changes on the Hall inputs.
411 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
412
413 This feature can be modified afterwards using unitary function
414 @ref LL_TIM_IC_SetPrescaler().*/
415
416 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
417 This parameter can be a value of
418 @ref TIM_LL_EC_IC_FILTER.
419
420 This feature can be modified afterwards using unitary function
421 @ref LL_TIM_IC_SetFilter().*/
422
423 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
424 A positive pulse (TRGO event) is generated with a programmable delay every time
425 a change occurs on the Hall inputs.
426 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_OC_SetCompareCH2().*/
430 } LL_TIM_HALLSENSOR_InitTypeDef;
431
432 /**
433 * @brief BDTR (Break and Dead Time) structure definition
434 */
435 typedef struct
436 {
437 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
438 This parameter can be a value of @ref TIM_LL_EC_OSSR
439
440 This feature can be modified afterwards using unitary function
441 @ref LL_TIM_SetOffStates()
442
443 @note This bit-field cannot be modified as long as LOCK level 2 has been
444 programmed. */
445
446 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
447 This parameter can be a value of @ref TIM_LL_EC_OSSI
448
449 This feature can be modified afterwards using unitary function
450 @ref LL_TIM_SetOffStates()
451
452 @note This bit-field cannot be modified as long as LOCK level 2 has been
453 programmed. */
454
455 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
456 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
457
458 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
459 register has been written, their content is frozen until the next reset.*/
460
461 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
462 switching-on of the outputs.
463 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
464
465 This feature can be modified afterwards using unitary function
466 @ref LL_TIM_OC_SetDeadTime()
467
468 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
469 programmed. */
470
471 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
472 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
473
474 This feature can be modified afterwards using unitary functions
475 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
476
477 @note This bit-field can not be modified as long as LOCK level 1 has been
478 programmed. */
479
480 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
481 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
482
483 This feature can be modified afterwards using unitary function
484 @ref LL_TIM_ConfigBRK()
485
486 @note This bit-field can not be modified as long as LOCK level 1 has been
487 programmed. */
488
489 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
490 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
491
492 This feature can be modified afterwards using unitary function
493 @ref LL_TIM_ConfigBRK()
494
495 @note This bit-field can not be modified as long as LOCK level 1 has been
496 programmed. */
497
498 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
499 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
500
501 This feature can be modified afterwards using unitary functions
502 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
503
504 @note This bit-field can not be modified as long as LOCK level 1 has been
505 programmed. */
506
507 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
508 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
509
510 This feature can be modified afterwards using unitary function
511 @ref LL_TIM_ConfigBRK2()
512
513 @note This bit-field can not be modified as long as LOCK level 1 has been
514 programmed. */
515
516 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
517 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
518
519 This feature can be modified afterwards using unitary function
520 @ref LL_TIM_ConfigBRK2()
521
522 @note This bit-field can not be modified as long as LOCK level 1 has been
523 programmed. */
524
525 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
526 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
527
528 This feature can be modified afterwards using unitary functions
529 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
530
531 @note This bit-field can not be modified as long as LOCK level 1 has been
532 programmed. */
533 } LL_TIM_BDTR_InitTypeDef;
534
535 /**
536 * @}
537 */
538 #endif /* USE_FULL_LL_DRIVER */
539
540 /* Exported constants --------------------------------------------------------*/
541 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
542 * @{
543 */
544
545 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
546 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
547 * @{
548 */
549 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
550 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
551 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
552 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
553 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
554 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
555 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
556 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
557 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
558 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
559 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
560 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
561 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
562 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
563 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
564 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
565 /**
566 * @}
567 */
568
569 #if defined(USE_FULL_LL_DRIVER)
570 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
571 * @{
572 */
573 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
574 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
575 /**
576 * @}
577 */
578
579 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
580 * @{
581 */
582 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
583 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
584 /**
585 * @}
586 */
587
588 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
589 * @{
590 */
591 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
592 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
593 /**
594 * @}
595 */
596 #endif /* USE_FULL_LL_DRIVER */
597
598 /** @defgroup TIM_LL_EC_IT IT Defines
599 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
600 * @{
601 */
602 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
603 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
604 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
605 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
606 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
607 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
608 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
609 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
615 * @{
616 */
617 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
618 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
624 * @{
625 */
626 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
627 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
628 /**
629 * @}
630 */
631
632 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
633 * @{
634 */
635 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
636 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
637 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
638 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
639 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
640 /**
641 * @}
642 */
643
644 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
645 * @{
646 */
647 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
648 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
649 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
650 /**
651 * @}
652 */
653
654 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
655 * @{
656 */
657 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
658 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
659 /**
660 * @}
661 */
662
663 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
664 * @{
665 */
666 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
667 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
668 /**
669 * @}
670 */
671
672 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
673 * @{
674 */
675 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
676 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
677 /**
678 * @}
679 */
680
681 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
682 * @{
683 */
684 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
685 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
686 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
687 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
688 /**
689 * @}
690 */
691
692 /** @defgroup TIM_LL_EC_CHANNEL Channel
693 * @{
694 */
695 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
696 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
697 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
698 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
699 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
700 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
701 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
702 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
703 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
704 /**
705 * @}
706 */
707
708 #if defined(USE_FULL_LL_DRIVER)
709 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
710 * @{
711 */
712 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
713 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
714 /**
715 * @}
716 */
717 #endif /* USE_FULL_LL_DRIVER */
718
719 /** Legacy definitions for compatibility purpose
720 @cond 0
721 */
722 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
723 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
724 /**
725 @endcond
726 */
727
728 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
729 * @{
730 */
731 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
732 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
733 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
734 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
735 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
736 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
737 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
738 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
739 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
740 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
741 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
742 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
743 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
744 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
745 /**
746 * @}
747 */
748
749 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
750 * @{
751 */
752 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
753 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
754 /**
755 * @}
756 */
757
758 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
759 * @{
760 */
761 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
762 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
763 /**
764 * @}
765 */
766
767 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
768 * @{
769 */
770 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
771 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
772 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
773 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
774 /**
775 * @}
776 */
777
778 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
779 * @{
780 */
781 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
782 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
783 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
784 /**
785 * @}
786 */
787
788 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
789 * @{
790 */
791 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
792 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
793 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
794 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
795 /**
796 * @}
797 */
798
799 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
800 * @{
801 */
802 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
803 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
804 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
805 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
806 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
807 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
808 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
809 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
810 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
811 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
812 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
813 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
814 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
815 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
816 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
817 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
823 * @{
824 */
825 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
826 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
827 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
828 /**
829 * @}
830 */
831
832 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
833 * @{
834 */
835 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
836 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
837 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
838 /**
839 * @}
840 */
841
842 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
843 * @{
844 */
845 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
846 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
847 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
848 /**
849 * @}
850 */
851
852 /** @defgroup TIM_LL_EC_TRGO Trigger Output
853 * @{
854 */
855 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
856 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
857 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
858 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
859 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
860 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
861 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
862 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
863 /**
864 * @}
865 */
866
867 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
868 * @{
869 */
870 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
871 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
872 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
873 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
874 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
875 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
876 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
877 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
878 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
879 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
880 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
881 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
882 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
883 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
884 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
885 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
886 /**
887 * @}
888 */
889
890 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
891 * @{
892 */
893 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
894 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
895 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
896 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
897 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
898 /**
899 * @}
900 */
901
902 /** @defgroup TIM_LL_EC_TS Trigger Selection
903 * @{
904 */
905 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
906 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
907 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
908 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
909 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
910 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
911 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
912 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
913 /**
914 * @}
915 */
916
917 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
918 * @{
919 */
920 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
921 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
922 /**
923 * @}
924 */
925
926 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
927 * @{
928 */
929 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
930 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
931 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
932 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
933 /**
934 * @}
935 */
936
937 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
938 * @{
939 */
940 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
941 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
942 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
943 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
944 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
945 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
946 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
947 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
948 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
949 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
950 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
951 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
952 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
953 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
954 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
955 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
956 /**
957 * @}
958 */
959
960
961 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
962 * @{
963 */
964 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
965 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
966 /**
967 * @}
968 */
969
970 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
971 * @{
972 */
973 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
974 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
975 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
976 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
977 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
978 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
979 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
980 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
981 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
982 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
983 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
984 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
985 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
986 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
987 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
988 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
989 /**
990 * @}
991 */
992
993 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
994 * @{
995 */
996 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
997 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
998 /**
999 * @}
1000 */
1001
1002 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1003 * @{
1004 */
1005 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1006 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1007 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1008 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1009 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1010 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1011 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1012 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1013 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1014 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1015 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1016 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1017 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1018 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1019 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1020 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1021 /**
1022 * @}
1023 */
1024
1025 /** @defgroup TIM_LL_EC_OSSI OSSI
1026 * @{
1027 */
1028 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1029 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1030 /**
1031 * @}
1032 */
1033
1034 /** @defgroup TIM_LL_EC_OSSR OSSR
1035 * @{
1036 */
1037 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1038 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1039 /**
1040 * @}
1041 */
1042
1043 #if defined(TIM_BREAK_INPUT_SUPPORT)
1044 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1045 * @{
1046 */
1047 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1048 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1049 /**
1050 * @}
1051 */
1052
1053 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1054 * @{
1055 */
1056 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1057 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BKE /*!< internal signal: DFSDM1 break output */
1058 /**
1059 * @}
1060 */
1061
1062 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1063 * @{
1064 */
1065 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1066 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1067 /**
1068 * @}
1069 */
1070 #endif /* TIM_BREAK_INPUT_SUPPORT */
1071
1072 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1073 * @{
1074 */
1075 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1076 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1077 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1078 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1079 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1080 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1081 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1082 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1083 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1084 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1085 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1086 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1087 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1088 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1089 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1090 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1091 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1092 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1093 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */
1094 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1095 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1096 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1097 #if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
1098 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1099 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1100 #endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
1101 /**
1102 * @}
1103 */
1104
1105 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1106 * @{
1107 */
1108 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1109 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1110 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1111 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1112 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1113 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1114 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1115 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1116 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1117 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1118 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1119 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1120 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1121 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1122 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1123 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1124 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1125 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1126 /**
1127 * @}
1128 */
1129
1130
1131 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
1132 * @{
1133 */
1134 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
1135 #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM2_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
1136 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
1137 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM2_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
1138 /**
1139 * @}
1140 */
1141
1142 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
1143 * @{
1144 */
1145 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
1146 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM5_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
1147 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM5_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
1148 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM5_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
1149 /**
1150 * @}
1151 */
1152
1153 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
1154 * @{
1155 */
1156 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
1157 #define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM11_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
1158 #define LL_TIM_TIM11_TI1_RMP_HSE (TIM11_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE */
1159 #define LL_TIM_TIM11_TI1_RMP_MCO1 (TIM11_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to MCO1 */
1160 /**
1161 * @}
1162 */
1163
1164
1165 /**
1166 * @}
1167 */
1168
1169 /* Exported macro ------------------------------------------------------------*/
1170 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1171 * @{
1172 */
1173
1174 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1175 * @{
1176 */
1177 /**
1178 * @brief Write a value in TIM register.
1179 * @param __INSTANCE__ TIM Instance
1180 * @param __REG__ Register to be written
1181 * @param __VALUE__ Value to be written in the register
1182 * @retval None
1183 */
1184 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1185
1186 /**
1187 * @brief Read a value in TIM register.
1188 * @param __INSTANCE__ TIM Instance
1189 * @param __REG__ Register to be read
1190 * @retval Register value
1191 */
1192 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1193 /**
1194 * @}
1195 */
1196
1197 /**
1198 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1199 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1200 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1201 * to TIMx_CNT register bit 31)
1202 * @param __CNT__ Counter value
1203 * @retval UIF status bit
1204 */
1205 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1206 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1207
1208 /**
1209 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1210 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1211 * @param __TIMCLK__ timer input clock frequency (in Hz)
1212 * @param __CKD__ This parameter can be one of the following values:
1213 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1214 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1215 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1216 * @param __DT__ deadtime duration (in ns)
1217 * @retval DTG[0:7]
1218 */
1219 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1220 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1221 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1222 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1223 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1224 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1225 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1226 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1227 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1228 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1229 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1230 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1231 0U)
1232
1233 /**
1234 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1235 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1236 * @param __TIMCLK__ timer input clock frequency (in Hz)
1237 * @param __CNTCLK__ counter clock frequency (in Hz)
1238 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1239 */
1240 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1241 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1242
1243 /**
1244 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1245 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1246 * @param __TIMCLK__ timer input clock frequency (in Hz)
1247 * @param __PSC__ prescaler
1248 * @param __FREQ__ output signal frequency (in Hz)
1249 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1250 */
1251 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1252 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1253
1254 /**
1255 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1256 * active/inactive delay.
1257 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1258 * @param __TIMCLK__ timer input clock frequency (in Hz)
1259 * @param __PSC__ prescaler
1260 * @param __DELAY__ timer output compare active/inactive delay (in us)
1261 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1262 */
1263 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1264 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1265 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1266
1267 /**
1268 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1269 * (when the timer operates in one pulse mode).
1270 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1271 * @param __TIMCLK__ timer input clock frequency (in Hz)
1272 * @param __PSC__ prescaler
1273 * @param __DELAY__ timer output compare active/inactive delay (in us)
1274 * @param __PULSE__ pulse duration (in us)
1275 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1276 */
1277 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1278 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1279 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1280
1281 /**
1282 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1283 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1284 * @param __ICPSC__ This parameter can be one of the following values:
1285 * @arg @ref LL_TIM_ICPSC_DIV1
1286 * @arg @ref LL_TIM_ICPSC_DIV2
1287 * @arg @ref LL_TIM_ICPSC_DIV4
1288 * @arg @ref LL_TIM_ICPSC_DIV8
1289 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1290 */
1291 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1292 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1293
1294
1295 /**
1296 * @}
1297 */
1298
1299 /* Exported functions --------------------------------------------------------*/
1300 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1301 * @{
1302 */
1303
1304 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1305 * @{
1306 */
1307 /**
1308 * @brief Enable timer counter.
1309 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1310 * @param TIMx Timer instance
1311 * @retval None
1312 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1313 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1314 {
1315 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1316 }
1317
1318 /**
1319 * @brief Disable timer counter.
1320 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1321 * @param TIMx Timer instance
1322 * @retval None
1323 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1324 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1325 {
1326 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1327 }
1328
1329 /**
1330 * @brief Indicates whether the timer counter is enabled.
1331 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1332 * @param TIMx Timer instance
1333 * @retval State of bit (1 or 0).
1334 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1335 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1336 {
1337 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1338 }
1339
1340 /**
1341 * @brief Enable update event generation.
1342 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1343 * @param TIMx Timer instance
1344 * @retval None
1345 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1346 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1347 {
1348 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1349 }
1350
1351 /**
1352 * @brief Disable update event generation.
1353 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1354 * @param TIMx Timer instance
1355 * @retval None
1356 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1357 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1358 {
1359 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1360 }
1361
1362 /**
1363 * @brief Indicates whether update event generation is enabled.
1364 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1365 * @param TIMx Timer instance
1366 * @retval Inverted state of bit (0 or 1).
1367 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1368 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1369 {
1370 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1371 }
1372
1373 /**
1374 * @brief Set update event source
1375 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1376 * generate an update interrupt or DMA request if enabled:
1377 * - Counter overflow/underflow
1378 * - Setting the UG bit
1379 * - Update generation through the slave mode controller
1380 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1381 * overflow/underflow generates an update interrupt or DMA request if enabled.
1382 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1383 * @param TIMx Timer instance
1384 * @param UpdateSource This parameter can be one of the following values:
1385 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1386 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1387 * @retval None
1388 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1389 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1390 {
1391 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1392 }
1393
1394 /**
1395 * @brief Get actual event update source
1396 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1397 * @param TIMx Timer instance
1398 * @retval Returned value can be one of the following values:
1399 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1400 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1401 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1402 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1403 {
1404 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1405 }
1406
1407 /**
1408 * @brief Set one pulse mode (one shot v.s. repetitive).
1409 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1410 * @param TIMx Timer instance
1411 * @param OnePulseMode This parameter can be one of the following values:
1412 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1413 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1414 * @retval None
1415 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1416 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1417 {
1418 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1419 }
1420
1421 /**
1422 * @brief Get actual one pulse mode.
1423 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1424 * @param TIMx Timer instance
1425 * @retval Returned value can be one of the following values:
1426 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1427 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1428 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1429 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1430 {
1431 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1432 }
1433
1434 /**
1435 * @brief Set the timer counter counting mode.
1436 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1437 * check whether or not the counter mode selection feature is supported
1438 * by a timer instance.
1439 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1440 * requires a timer reset to avoid unexpected direction
1441 * due to DIR bit readonly in center aligned mode.
1442 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1443 * CR1 CMS LL_TIM_SetCounterMode
1444 * @param TIMx Timer instance
1445 * @param CounterMode This parameter can be one of the following values:
1446 * @arg @ref LL_TIM_COUNTERMODE_UP
1447 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1448 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1449 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1450 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1451 * @retval None
1452 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1453 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1454 {
1455 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1456 }
1457
1458 /**
1459 * @brief Get actual counter mode.
1460 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1461 * check whether or not the counter mode selection feature is supported
1462 * by a timer instance.
1463 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1464 * CR1 CMS LL_TIM_GetCounterMode
1465 * @param TIMx Timer instance
1466 * @retval Returned value can be one of the following values:
1467 * @arg @ref LL_TIM_COUNTERMODE_UP
1468 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1469 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1470 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1471 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1472 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1473 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1474 {
1475 uint32_t counter_mode;
1476
1477 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1478
1479 if (counter_mode == 0U)
1480 {
1481 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1482 }
1483
1484 return counter_mode;
1485 }
1486
1487 /**
1488 * @brief Enable auto-reload (ARR) preload.
1489 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1490 * @param TIMx Timer instance
1491 * @retval None
1492 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1493 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1494 {
1495 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1496 }
1497
1498 /**
1499 * @brief Disable auto-reload (ARR) preload.
1500 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1501 * @param TIMx Timer instance
1502 * @retval None
1503 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1504 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1505 {
1506 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1507 }
1508
1509 /**
1510 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1511 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1512 * @param TIMx Timer instance
1513 * @retval State of bit (1 or 0).
1514 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1515 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1516 {
1517 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1518 }
1519
1520 /**
1521 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1522 * (when supported) and the digital filters.
1523 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1524 * whether or not the clock division feature is supported by the timer
1525 * instance.
1526 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1527 * @param TIMx Timer instance
1528 * @param ClockDivision This parameter can be one of the following values:
1529 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1530 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1531 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1532 * @retval None
1533 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1534 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1535 {
1536 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1537 }
1538
1539 /**
1540 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1541 * generators (when supported) and the digital filters.
1542 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1543 * whether or not the clock division feature is supported by the timer
1544 * instance.
1545 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1546 * @param TIMx Timer instance
1547 * @retval Returned value can be one of the following values:
1548 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1549 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1550 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1551 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1552 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1553 {
1554 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1555 }
1556
1557 /**
1558 * @brief Set the counter value.
1559 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1560 * whether or not a timer instance supports a 32 bits counter.
1561 * @rmtoll CNT CNT LL_TIM_SetCounter
1562 * @param TIMx Timer instance
1563 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1564 * @retval None
1565 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1566 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1567 {
1568 WRITE_REG(TIMx->CNT, Counter);
1569 }
1570
1571 /**
1572 * @brief Get the counter value.
1573 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1574 * whether or not a timer instance supports a 32 bits counter.
1575 * @rmtoll CNT CNT LL_TIM_GetCounter
1576 * @param TIMx Timer instance
1577 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1578 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1579 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1580 {
1581 return (uint32_t)(READ_REG(TIMx->CNT));
1582 }
1583
1584 /**
1585 * @brief Get the current direction of the counter
1586 * @rmtoll CR1 DIR LL_TIM_GetDirection
1587 * @param TIMx Timer instance
1588 * @retval Returned value can be one of the following values:
1589 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1590 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1591 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1592 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1593 {
1594 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1595 }
1596
1597 /**
1598 * @brief Set the prescaler value.
1599 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1600 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1601 * prescaler ratio is taken into account at the next update event.
1602 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1603 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1604 * @param TIMx Timer instance
1605 * @param Prescaler between Min_Data=0 and Max_Data=65535
1606 * @retval None
1607 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1608 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1609 {
1610 WRITE_REG(TIMx->PSC, Prescaler);
1611 }
1612
1613 /**
1614 * @brief Get the prescaler value.
1615 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1616 * @param TIMx Timer instance
1617 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1618 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1619 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1620 {
1621 return (uint32_t)(READ_REG(TIMx->PSC));
1622 }
1623
1624 /**
1625 * @brief Set the auto-reload value.
1626 * @note The counter is blocked while the auto-reload value is null.
1627 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1628 * whether or not a timer instance supports a 32 bits counter.
1629 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1630 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1631 * @param TIMx Timer instance
1632 * @param AutoReload between Min_Data=0 and Max_Data=65535
1633 * @retval None
1634 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1635 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1636 {
1637 WRITE_REG(TIMx->ARR, AutoReload);
1638 }
1639
1640 /**
1641 * @brief Get the auto-reload value.
1642 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1643 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1644 * whether or not a timer instance supports a 32 bits counter.
1645 * @param TIMx Timer instance
1646 * @retval Auto-reload value
1647 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1648 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1649 {
1650 return (uint32_t)(READ_REG(TIMx->ARR));
1651 }
1652
1653 /**
1654 * @brief Set the repetition counter value.
1655 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1656 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1657 * whether or not a timer instance supports a repetition counter.
1658 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1659 * @param TIMx Timer instance
1660 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1661 * @retval None
1662 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1663 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1664 {
1665 WRITE_REG(TIMx->RCR, RepetitionCounter);
1666 }
1667
1668 /**
1669 * @brief Get the repetition counter value.
1670 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1671 * whether or not a timer instance supports a repetition counter.
1672 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1673 * @param TIMx Timer instance
1674 * @retval Repetition counter value
1675 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1676 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1677 {
1678 return (uint32_t)(READ_REG(TIMx->RCR));
1679 }
1680
1681 /**
1682 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1683 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1684 * in an atomic way.
1685 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1686 * @param TIMx Timer instance
1687 * @retval None
1688 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1689 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1690 {
1691 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1692 }
1693
1694 /**
1695 * @brief Disable update interrupt flag (UIF) remapping.
1696 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1697 * @param TIMx Timer instance
1698 * @retval None
1699 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1700 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1701 {
1702 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1703 }
1704
1705 /**
1706 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1707 * @param Counter Counter value
1708 * @retval State of bit (1 or 0).
1709 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1710 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1711 {
1712 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1713 }
1714
1715 /**
1716 * @}
1717 */
1718
1719 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1720 * @{
1721 */
1722 /**
1723 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1724 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1725 * they are updated only when a commutation event (COM) occurs.
1726 * @note Only on channels that have a complementary output.
1727 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1728 * whether or not a timer instance is able to generate a commutation event.
1729 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1730 * @param TIMx Timer instance
1731 * @retval None
1732 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1733 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1734 {
1735 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1736 }
1737
1738 /**
1739 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1740 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1741 * whether or not a timer instance is able to generate a commutation event.
1742 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1743 * @param TIMx Timer instance
1744 * @retval None
1745 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1746 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1747 {
1748 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1749 }
1750
1751 /**
1752 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1753 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1754 * @param TIMx Timer instance
1755 * @retval State of bit (1 or 0).
1756 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1757 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1758 {
1759 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1760 }
1761
1762 /**
1763 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1764 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1765 * whether or not a timer instance is able to generate a commutation event.
1766 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1767 * @param TIMx Timer instance
1768 * @param CCUpdateSource This parameter can be one of the following values:
1769 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1770 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1771 * @retval None
1772 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1773 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1774 {
1775 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1776 }
1777
1778 /**
1779 * @brief Set the trigger of the capture/compare DMA request.
1780 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1781 * @param TIMx Timer instance
1782 * @param DMAReqTrigger This parameter can be one of the following values:
1783 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1784 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1785 * @retval None
1786 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1787 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1788 {
1789 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1790 }
1791
1792 /**
1793 * @brief Get actual trigger of the capture/compare DMA request.
1794 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1795 * @param TIMx Timer instance
1796 * @retval Returned value can be one of the following values:
1797 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1798 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1799 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1800 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1801 {
1802 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1803 }
1804
1805 /**
1806 * @brief Set the lock level to freeze the
1807 * configuration of several capture/compare parameters.
1808 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1809 * the lock mechanism is supported by a timer instance.
1810 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1811 * @param TIMx Timer instance
1812 * @param LockLevel This parameter can be one of the following values:
1813 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1814 * @arg @ref LL_TIM_LOCKLEVEL_1
1815 * @arg @ref LL_TIM_LOCKLEVEL_2
1816 * @arg @ref LL_TIM_LOCKLEVEL_3
1817 * @retval None
1818 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1819 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1820 {
1821 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1822 }
1823
1824 /**
1825 * @brief Enable capture/compare channels.
1826 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1827 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1828 * CCER CC2E LL_TIM_CC_EnableChannel\n
1829 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1830 * CCER CC3E LL_TIM_CC_EnableChannel\n
1831 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1832 * CCER CC4E LL_TIM_CC_EnableChannel\n
1833 * CCER CC5E LL_TIM_CC_EnableChannel\n
1834 * CCER CC6E LL_TIM_CC_EnableChannel
1835 * @param TIMx Timer instance
1836 * @param Channels This parameter can be a combination of the following values:
1837 * @arg @ref LL_TIM_CHANNEL_CH1
1838 * @arg @ref LL_TIM_CHANNEL_CH1N
1839 * @arg @ref LL_TIM_CHANNEL_CH2
1840 * @arg @ref LL_TIM_CHANNEL_CH2N
1841 * @arg @ref LL_TIM_CHANNEL_CH3
1842 * @arg @ref LL_TIM_CHANNEL_CH3N
1843 * @arg @ref LL_TIM_CHANNEL_CH4
1844 * @arg @ref LL_TIM_CHANNEL_CH5
1845 * @arg @ref LL_TIM_CHANNEL_CH6
1846 * @retval None
1847 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1848 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1849 {
1850 SET_BIT(TIMx->CCER, Channels);
1851 }
1852
1853 /**
1854 * @brief Disable capture/compare channels.
1855 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1856 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1857 * CCER CC2E LL_TIM_CC_DisableChannel\n
1858 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1859 * CCER CC3E LL_TIM_CC_DisableChannel\n
1860 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1861 * CCER CC4E LL_TIM_CC_DisableChannel\n
1862 * CCER CC5E LL_TIM_CC_DisableChannel\n
1863 * CCER CC6E LL_TIM_CC_DisableChannel
1864 * @param TIMx Timer instance
1865 * @param Channels This parameter can be a combination of the following values:
1866 * @arg @ref LL_TIM_CHANNEL_CH1
1867 * @arg @ref LL_TIM_CHANNEL_CH1N
1868 * @arg @ref LL_TIM_CHANNEL_CH2
1869 * @arg @ref LL_TIM_CHANNEL_CH2N
1870 * @arg @ref LL_TIM_CHANNEL_CH3
1871 * @arg @ref LL_TIM_CHANNEL_CH3N
1872 * @arg @ref LL_TIM_CHANNEL_CH4
1873 * @arg @ref LL_TIM_CHANNEL_CH5
1874 * @arg @ref LL_TIM_CHANNEL_CH6
1875 * @retval None
1876 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1877 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1878 {
1879 CLEAR_BIT(TIMx->CCER, Channels);
1880 }
1881
1882 /**
1883 * @brief Indicate whether channel(s) is(are) enabled.
1884 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1885 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1886 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1887 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1888 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1889 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1890 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1891 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1892 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1893 * @param TIMx Timer instance
1894 * @param Channels This parameter can be a combination of the following values:
1895 * @arg @ref LL_TIM_CHANNEL_CH1
1896 * @arg @ref LL_TIM_CHANNEL_CH1N
1897 * @arg @ref LL_TIM_CHANNEL_CH2
1898 * @arg @ref LL_TIM_CHANNEL_CH2N
1899 * @arg @ref LL_TIM_CHANNEL_CH3
1900 * @arg @ref LL_TIM_CHANNEL_CH3N
1901 * @arg @ref LL_TIM_CHANNEL_CH4
1902 * @arg @ref LL_TIM_CHANNEL_CH5
1903 * @arg @ref LL_TIM_CHANNEL_CH6
1904 * @retval State of bit (1 or 0).
1905 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1906 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1907 {
1908 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1909 }
1910
1911 /**
1912 * @}
1913 */
1914
1915 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1916 * @{
1917 */
1918 /**
1919 * @brief Configure an output channel.
1920 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1921 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1922 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1923 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1924 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1925 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1926 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1927 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1928 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1929 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1930 * CCER CC5P LL_TIM_OC_ConfigOutput\n
1931 * CCER CC6P LL_TIM_OC_ConfigOutput\n
1932 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1933 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1934 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1935 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
1936 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
1937 * CR2 OIS6 LL_TIM_OC_ConfigOutput
1938 * @param TIMx Timer instance
1939 * @param Channel This parameter can be one of the following values:
1940 * @arg @ref LL_TIM_CHANNEL_CH1
1941 * @arg @ref LL_TIM_CHANNEL_CH2
1942 * @arg @ref LL_TIM_CHANNEL_CH3
1943 * @arg @ref LL_TIM_CHANNEL_CH4
1944 * @arg @ref LL_TIM_CHANNEL_CH5
1945 * @arg @ref LL_TIM_CHANNEL_CH6
1946 * @param Configuration This parameter must be a combination of all the following values:
1947 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1948 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1949 * @retval None
1950 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1951 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1952 {
1953 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1954 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1955 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1956 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1957 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1958 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1959 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1960 }
1961
1962 /**
1963 * @brief Define the behavior of the output reference signal OCxREF from which
1964 * OCx and OCxN (when relevant) are derived.
1965 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1966 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1967 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1968 * CCMR2 OC4M LL_TIM_OC_SetMode\n
1969 * CCMR3 OC5M LL_TIM_OC_SetMode\n
1970 * CCMR3 OC6M LL_TIM_OC_SetMode
1971 * @param TIMx Timer instance
1972 * @param Channel This parameter can be one of the following values:
1973 * @arg @ref LL_TIM_CHANNEL_CH1
1974 * @arg @ref LL_TIM_CHANNEL_CH2
1975 * @arg @ref LL_TIM_CHANNEL_CH3
1976 * @arg @ref LL_TIM_CHANNEL_CH4
1977 * @arg @ref LL_TIM_CHANNEL_CH5
1978 * @arg @ref LL_TIM_CHANNEL_CH6
1979 * @param Mode This parameter can be one of the following values:
1980 * @arg @ref LL_TIM_OCMODE_FROZEN
1981 * @arg @ref LL_TIM_OCMODE_ACTIVE
1982 * @arg @ref LL_TIM_OCMODE_INACTIVE
1983 * @arg @ref LL_TIM_OCMODE_TOGGLE
1984 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1985 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1986 * @arg @ref LL_TIM_OCMODE_PWM1
1987 * @arg @ref LL_TIM_OCMODE_PWM2
1988 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
1989 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
1990 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
1991 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
1992 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
1993 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
1994 * @retval None
1995 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1996 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1997 {
1998 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1999 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2000 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2001 }
2002
2003 /**
2004 * @brief Get the output compare mode of an output channel.
2005 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2006 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2007 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2008 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2009 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2010 * CCMR3 OC6M LL_TIM_OC_GetMode
2011 * @param TIMx Timer instance
2012 * @param Channel This parameter can be one of the following values:
2013 * @arg @ref LL_TIM_CHANNEL_CH1
2014 * @arg @ref LL_TIM_CHANNEL_CH2
2015 * @arg @ref LL_TIM_CHANNEL_CH3
2016 * @arg @ref LL_TIM_CHANNEL_CH4
2017 * @arg @ref LL_TIM_CHANNEL_CH5
2018 * @arg @ref LL_TIM_CHANNEL_CH6
2019 * @retval Returned value can be one of the following values:
2020 * @arg @ref LL_TIM_OCMODE_FROZEN
2021 * @arg @ref LL_TIM_OCMODE_ACTIVE
2022 * @arg @ref LL_TIM_OCMODE_INACTIVE
2023 * @arg @ref LL_TIM_OCMODE_TOGGLE
2024 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2025 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2026 * @arg @ref LL_TIM_OCMODE_PWM1
2027 * @arg @ref LL_TIM_OCMODE_PWM2
2028 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2029 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2030 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2031 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2032 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2033 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2034 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2035 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2036 {
2037 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2038 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2039 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2040 }
2041
2042 /**
2043 * @brief Set the polarity of an output channel.
2044 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2045 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2046 * CCER CC2P LL_TIM_OC_SetPolarity\n
2047 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2048 * CCER CC3P LL_TIM_OC_SetPolarity\n
2049 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2050 * CCER CC4P LL_TIM_OC_SetPolarity\n
2051 * CCER CC5P LL_TIM_OC_SetPolarity\n
2052 * CCER CC6P LL_TIM_OC_SetPolarity
2053 * @param TIMx Timer instance
2054 * @param Channel This parameter can be one of the following values:
2055 * @arg @ref LL_TIM_CHANNEL_CH1
2056 * @arg @ref LL_TIM_CHANNEL_CH1N
2057 * @arg @ref LL_TIM_CHANNEL_CH2
2058 * @arg @ref LL_TIM_CHANNEL_CH2N
2059 * @arg @ref LL_TIM_CHANNEL_CH3
2060 * @arg @ref LL_TIM_CHANNEL_CH3N
2061 * @arg @ref LL_TIM_CHANNEL_CH4
2062 * @arg @ref LL_TIM_CHANNEL_CH5
2063 * @arg @ref LL_TIM_CHANNEL_CH6
2064 * @param Polarity This parameter can be one of the following values:
2065 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2066 * @arg @ref LL_TIM_OCPOLARITY_LOW
2067 * @retval None
2068 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2069 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2070 {
2071 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2072 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2073 }
2074
2075 /**
2076 * @brief Get the polarity of an output channel.
2077 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2078 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2079 * CCER CC2P LL_TIM_OC_GetPolarity\n
2080 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2081 * CCER CC3P LL_TIM_OC_GetPolarity\n
2082 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2083 * CCER CC4P LL_TIM_OC_GetPolarity\n
2084 * CCER CC5P LL_TIM_OC_GetPolarity\n
2085 * CCER CC6P LL_TIM_OC_GetPolarity
2086 * @param TIMx Timer instance
2087 * @param Channel This parameter can be one of the following values:
2088 * @arg @ref LL_TIM_CHANNEL_CH1
2089 * @arg @ref LL_TIM_CHANNEL_CH1N
2090 * @arg @ref LL_TIM_CHANNEL_CH2
2091 * @arg @ref LL_TIM_CHANNEL_CH2N
2092 * @arg @ref LL_TIM_CHANNEL_CH3
2093 * @arg @ref LL_TIM_CHANNEL_CH3N
2094 * @arg @ref LL_TIM_CHANNEL_CH4
2095 * @arg @ref LL_TIM_CHANNEL_CH5
2096 * @arg @ref LL_TIM_CHANNEL_CH6
2097 * @retval Returned value can be one of the following values:
2098 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2099 * @arg @ref LL_TIM_OCPOLARITY_LOW
2100 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2101 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2102 {
2103 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2104 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2105 }
2106
2107 /**
2108 * @brief Set the IDLE state of an output channel
2109 * @note This function is significant only for the timer instances
2110 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2111 * can be used to check whether or not a timer instance provides
2112 * a break input.
2113 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2114 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2115 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2116 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2117 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2118 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2119 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2120 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2121 * CR2 OIS6 LL_TIM_OC_SetIdleState
2122 * @param TIMx Timer instance
2123 * @param Channel This parameter can be one of the following values:
2124 * @arg @ref LL_TIM_CHANNEL_CH1
2125 * @arg @ref LL_TIM_CHANNEL_CH1N
2126 * @arg @ref LL_TIM_CHANNEL_CH2
2127 * @arg @ref LL_TIM_CHANNEL_CH2N
2128 * @arg @ref LL_TIM_CHANNEL_CH3
2129 * @arg @ref LL_TIM_CHANNEL_CH3N
2130 * @arg @ref LL_TIM_CHANNEL_CH4
2131 * @arg @ref LL_TIM_CHANNEL_CH5
2132 * @arg @ref LL_TIM_CHANNEL_CH6
2133 * @param IdleState This parameter can be one of the following values:
2134 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2135 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2136 * @retval None
2137 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2138 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2139 {
2140 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2141 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2142 }
2143
2144 /**
2145 * @brief Get the IDLE state of an output channel
2146 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2147 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2148 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2149 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2150 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2151 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2152 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2153 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2154 * CR2 OIS6 LL_TIM_OC_GetIdleState
2155 * @param TIMx Timer instance
2156 * @param Channel This parameter can be one of the following values:
2157 * @arg @ref LL_TIM_CHANNEL_CH1
2158 * @arg @ref LL_TIM_CHANNEL_CH1N
2159 * @arg @ref LL_TIM_CHANNEL_CH2
2160 * @arg @ref LL_TIM_CHANNEL_CH2N
2161 * @arg @ref LL_TIM_CHANNEL_CH3
2162 * @arg @ref LL_TIM_CHANNEL_CH3N
2163 * @arg @ref LL_TIM_CHANNEL_CH4
2164 * @arg @ref LL_TIM_CHANNEL_CH5
2165 * @arg @ref LL_TIM_CHANNEL_CH6
2166 * @retval Returned value can be one of the following values:
2167 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2168 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2169 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2170 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2171 {
2172 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2173 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2174 }
2175
2176 /**
2177 * @brief Enable fast mode for the output channel.
2178 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2179 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2180 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2181 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2182 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2183 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2184 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2185 * @param TIMx Timer instance
2186 * @param Channel This parameter can be one of the following values:
2187 * @arg @ref LL_TIM_CHANNEL_CH1
2188 * @arg @ref LL_TIM_CHANNEL_CH2
2189 * @arg @ref LL_TIM_CHANNEL_CH3
2190 * @arg @ref LL_TIM_CHANNEL_CH4
2191 * @arg @ref LL_TIM_CHANNEL_CH5
2192 * @arg @ref LL_TIM_CHANNEL_CH6
2193 * @retval None
2194 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2195 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2196 {
2197 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2198 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2199 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2200
2201 }
2202
2203 /**
2204 * @brief Disable fast mode for the output channel.
2205 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2206 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2207 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2208 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2209 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2210 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2211 * @param TIMx Timer instance
2212 * @param Channel This parameter can be one of the following values:
2213 * @arg @ref LL_TIM_CHANNEL_CH1
2214 * @arg @ref LL_TIM_CHANNEL_CH2
2215 * @arg @ref LL_TIM_CHANNEL_CH3
2216 * @arg @ref LL_TIM_CHANNEL_CH4
2217 * @arg @ref LL_TIM_CHANNEL_CH5
2218 * @arg @ref LL_TIM_CHANNEL_CH6
2219 * @retval None
2220 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2221 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2222 {
2223 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2224 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2225 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2226
2227 }
2228
2229 /**
2230 * @brief Indicates whether fast mode is enabled for the output channel.
2231 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2232 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2233 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2234 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2235 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2236 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2237 * @param TIMx Timer instance
2238 * @param Channel This parameter can be one of the following values:
2239 * @arg @ref LL_TIM_CHANNEL_CH1
2240 * @arg @ref LL_TIM_CHANNEL_CH2
2241 * @arg @ref LL_TIM_CHANNEL_CH3
2242 * @arg @ref LL_TIM_CHANNEL_CH4
2243 * @arg @ref LL_TIM_CHANNEL_CH5
2244 * @arg @ref LL_TIM_CHANNEL_CH6
2245 * @retval State of bit (1 or 0).
2246 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2247 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2248 {
2249 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2250 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2251 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2252 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2253 }
2254
2255 /**
2256 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2257 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2258 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2259 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2260 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2261 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2262 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2263 * @param TIMx Timer instance
2264 * @param Channel This parameter can be one of the following values:
2265 * @arg @ref LL_TIM_CHANNEL_CH1
2266 * @arg @ref LL_TIM_CHANNEL_CH2
2267 * @arg @ref LL_TIM_CHANNEL_CH3
2268 * @arg @ref LL_TIM_CHANNEL_CH4
2269 * @arg @ref LL_TIM_CHANNEL_CH5
2270 * @arg @ref LL_TIM_CHANNEL_CH6
2271 * @retval None
2272 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2273 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2274 {
2275 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2276 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2277 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2278 }
2279
2280 /**
2281 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2282 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2283 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2284 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2285 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2286 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2287 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2288 * @param TIMx Timer instance
2289 * @param Channel This parameter can be one of the following values:
2290 * @arg @ref LL_TIM_CHANNEL_CH1
2291 * @arg @ref LL_TIM_CHANNEL_CH2
2292 * @arg @ref LL_TIM_CHANNEL_CH3
2293 * @arg @ref LL_TIM_CHANNEL_CH4
2294 * @arg @ref LL_TIM_CHANNEL_CH5
2295 * @arg @ref LL_TIM_CHANNEL_CH6
2296 * @retval None
2297 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2298 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2299 {
2300 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2301 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2302 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2303 }
2304
2305 /**
2306 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2307 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2308 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2309 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2310 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2311 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2312 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2313 * @param TIMx Timer instance
2314 * @param Channel This parameter can be one of the following values:
2315 * @arg @ref LL_TIM_CHANNEL_CH1
2316 * @arg @ref LL_TIM_CHANNEL_CH2
2317 * @arg @ref LL_TIM_CHANNEL_CH3
2318 * @arg @ref LL_TIM_CHANNEL_CH4
2319 * @arg @ref LL_TIM_CHANNEL_CH5
2320 * @arg @ref LL_TIM_CHANNEL_CH6
2321 * @retval State of bit (1 or 0).
2322 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2323 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2324 {
2325 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2326 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2327 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2328 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2329 }
2330
2331 /**
2332 * @brief Enable clearing the output channel on an external event.
2333 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2334 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2335 * or not a timer instance can clear the OCxREF signal on an external event.
2336 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2337 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2338 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2339 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2340 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2341 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2342 * @param TIMx Timer instance
2343 * @param Channel This parameter can be one of the following values:
2344 * @arg @ref LL_TIM_CHANNEL_CH1
2345 * @arg @ref LL_TIM_CHANNEL_CH2
2346 * @arg @ref LL_TIM_CHANNEL_CH3
2347 * @arg @ref LL_TIM_CHANNEL_CH4
2348 * @arg @ref LL_TIM_CHANNEL_CH5
2349 * @arg @ref LL_TIM_CHANNEL_CH6
2350 * @retval None
2351 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2352 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2353 {
2354 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2355 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2356 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2357 }
2358
2359 /**
2360 * @brief Disable clearing the output channel on an external event.
2361 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2362 * or not a timer instance can clear the OCxREF signal on an external event.
2363 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2364 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2365 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2366 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2367 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2368 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2369 * @param TIMx Timer instance
2370 * @param Channel This parameter can be one of the following values:
2371 * @arg @ref LL_TIM_CHANNEL_CH1
2372 * @arg @ref LL_TIM_CHANNEL_CH2
2373 * @arg @ref LL_TIM_CHANNEL_CH3
2374 * @arg @ref LL_TIM_CHANNEL_CH4
2375 * @arg @ref LL_TIM_CHANNEL_CH5
2376 * @arg @ref LL_TIM_CHANNEL_CH6
2377 * @retval None
2378 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2379 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2380 {
2381 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2382 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2383 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2384 }
2385
2386 /**
2387 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2388 * @note This function enables clearing the output channel on an external event.
2389 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2390 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2391 * or not a timer instance can clear the OCxREF signal on an external event.
2392 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2393 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2394 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2395 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2396 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2397 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2398 * @param TIMx Timer instance
2399 * @param Channel This parameter can be one of the following values:
2400 * @arg @ref LL_TIM_CHANNEL_CH1
2401 * @arg @ref LL_TIM_CHANNEL_CH2
2402 * @arg @ref LL_TIM_CHANNEL_CH3
2403 * @arg @ref LL_TIM_CHANNEL_CH4
2404 * @arg @ref LL_TIM_CHANNEL_CH5
2405 * @arg @ref LL_TIM_CHANNEL_CH6
2406 * @retval State of bit (1 or 0).
2407 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2408 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2409 {
2410 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2411 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2412 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2413 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2414 }
2415
2416 /**
2417 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2418 * the Ocx and OCxN signals).
2419 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2420 * dead-time insertion feature is supported by a timer instance.
2421 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2422 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2423 * @param TIMx Timer instance
2424 * @param DeadTime between Min_Data=0 and Max_Data=255
2425 * @retval None
2426 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2427 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2428 {
2429 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2430 }
2431
2432 /**
2433 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2434 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2435 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2436 * whether or not a timer instance supports a 32 bits counter.
2437 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2438 * output channel 1 is supported by a timer instance.
2439 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2440 * @param TIMx Timer instance
2441 * @param CompareValue between Min_Data=0 and Max_Data=65535
2442 * @retval None
2443 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2444 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2445 {
2446 WRITE_REG(TIMx->CCR1, CompareValue);
2447 }
2448
2449 /**
2450 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2451 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2452 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2453 * whether or not a timer instance supports a 32 bits counter.
2454 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2455 * output channel 2 is supported by a timer instance.
2456 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2457 * @param TIMx Timer instance
2458 * @param CompareValue between Min_Data=0 and Max_Data=65535
2459 * @retval None
2460 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2461 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2462 {
2463 WRITE_REG(TIMx->CCR2, CompareValue);
2464 }
2465
2466 /**
2467 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2468 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2469 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2470 * whether or not a timer instance supports a 32 bits counter.
2471 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2472 * output channel is supported by a timer instance.
2473 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2474 * @param TIMx Timer instance
2475 * @param CompareValue between Min_Data=0 and Max_Data=65535
2476 * @retval None
2477 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2478 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2479 {
2480 WRITE_REG(TIMx->CCR3, CompareValue);
2481 }
2482
2483 /**
2484 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2485 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2486 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2487 * whether or not a timer instance supports a 32 bits counter.
2488 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2489 * output channel 4 is supported by a timer instance.
2490 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2491 * @param TIMx Timer instance
2492 * @param CompareValue between Min_Data=0 and Max_Data=65535
2493 * @retval None
2494 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2495 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2496 {
2497 WRITE_REG(TIMx->CCR4, CompareValue);
2498 }
2499
2500 /**
2501 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2502 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2503 * output channel 5 is supported by a timer instance.
2504 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2505 * @param TIMx Timer instance
2506 * @param CompareValue between Min_Data=0 and Max_Data=65535
2507 * @retval None
2508 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2509 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2510 {
2511 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2512 }
2513
2514 /**
2515 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2516 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2517 * output channel 6 is supported by a timer instance.
2518 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2519 * @param TIMx Timer instance
2520 * @param CompareValue between Min_Data=0 and Max_Data=65535
2521 * @retval None
2522 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2523 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2524 {
2525 WRITE_REG(TIMx->CCR6, CompareValue);
2526 }
2527
2528 /**
2529 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2530 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2531 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2532 * whether or not a timer instance supports a 32 bits counter.
2533 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2534 * output channel 1 is supported by a timer instance.
2535 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2536 * @param TIMx Timer instance
2537 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2538 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2539 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2540 {
2541 return (uint32_t)(READ_REG(TIMx->CCR1));
2542 }
2543
2544 /**
2545 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2546 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2547 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2548 * whether or not a timer instance supports a 32 bits counter.
2549 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2550 * output channel 2 is supported by a timer instance.
2551 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2552 * @param TIMx Timer instance
2553 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2554 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2555 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2556 {
2557 return (uint32_t)(READ_REG(TIMx->CCR2));
2558 }
2559
2560 /**
2561 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2562 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2563 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2564 * whether or not a timer instance supports a 32 bits counter.
2565 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2566 * output channel 3 is supported by a timer instance.
2567 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2568 * @param TIMx Timer instance
2569 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2570 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2571 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2572 {
2573 return (uint32_t)(READ_REG(TIMx->CCR3));
2574 }
2575
2576 /**
2577 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2578 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2579 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2580 * whether or not a timer instance supports a 32 bits counter.
2581 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2582 * output channel 4 is supported by a timer instance.
2583 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2584 * @param TIMx Timer instance
2585 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2586 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2587 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2588 {
2589 return (uint32_t)(READ_REG(TIMx->CCR4));
2590 }
2591
2592 /**
2593 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2594 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2595 * output channel 5 is supported by a timer instance.
2596 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2597 * @param TIMx Timer instance
2598 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2599 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2600 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2601 {
2602 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2603 }
2604
2605 /**
2606 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2607 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2608 * output channel 6 is supported by a timer instance.
2609 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2610 * @param TIMx Timer instance
2611 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2612 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2613 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2614 {
2615 return (uint32_t)(READ_REG(TIMx->CCR6));
2616 }
2617
2618 /**
2619 * @brief Select on which reference signal the OC5REF is combined to.
2620 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2621 * whether or not a timer instance supports the combined 3-phase PWM mode.
2622 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2623 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2624 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2625 * @param TIMx Timer instance
2626 * @param GroupCH5 This parameter can be a combination of the following values:
2627 * @arg @ref LL_TIM_GROUPCH5_NONE
2628 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2629 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2630 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2631 * @retval None
2632 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2633 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2634 {
2635 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2636 }
2637
2638 /**
2639 * @}
2640 */
2641
2642 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2643 * @{
2644 */
2645 /**
2646 * @brief Configure input channel.
2647 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2648 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2649 * CCMR1 IC1F LL_TIM_IC_Config\n
2650 * CCMR1 CC2S LL_TIM_IC_Config\n
2651 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2652 * CCMR1 IC2F LL_TIM_IC_Config\n
2653 * CCMR2 CC3S LL_TIM_IC_Config\n
2654 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2655 * CCMR2 IC3F LL_TIM_IC_Config\n
2656 * CCMR2 CC4S LL_TIM_IC_Config\n
2657 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2658 * CCMR2 IC4F LL_TIM_IC_Config\n
2659 * CCER CC1P LL_TIM_IC_Config\n
2660 * CCER CC1NP LL_TIM_IC_Config\n
2661 * CCER CC2P LL_TIM_IC_Config\n
2662 * CCER CC2NP LL_TIM_IC_Config\n
2663 * CCER CC3P LL_TIM_IC_Config\n
2664 * CCER CC3NP LL_TIM_IC_Config\n
2665 * CCER CC4P LL_TIM_IC_Config\n
2666 * CCER CC4NP LL_TIM_IC_Config
2667 * @param TIMx Timer instance
2668 * @param Channel This parameter can be one of the following values:
2669 * @arg @ref LL_TIM_CHANNEL_CH1
2670 * @arg @ref LL_TIM_CHANNEL_CH2
2671 * @arg @ref LL_TIM_CHANNEL_CH3
2672 * @arg @ref LL_TIM_CHANNEL_CH4
2673 * @param Configuration This parameter must be a combination of all the following values:
2674 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2675 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2676 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2677 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2678 * @retval None
2679 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2680 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2681 {
2682 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2683 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2684 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2685 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2686 << SHIFT_TAB_ICxx[iChannel]);
2687 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2688 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2689 }
2690
2691 /**
2692 * @brief Set the active input.
2693 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2694 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2695 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2696 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2697 * @param TIMx Timer instance
2698 * @param Channel This parameter can be one of the following values:
2699 * @arg @ref LL_TIM_CHANNEL_CH1
2700 * @arg @ref LL_TIM_CHANNEL_CH2
2701 * @arg @ref LL_TIM_CHANNEL_CH3
2702 * @arg @ref LL_TIM_CHANNEL_CH4
2703 * @param ICActiveInput This parameter can be one of the following values:
2704 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2705 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2706 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2707 * @retval None
2708 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2709 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2710 {
2711 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2712 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2713 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2714 }
2715
2716 /**
2717 * @brief Get the current active input.
2718 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2719 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2720 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2721 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2722 * @param TIMx Timer instance
2723 * @param Channel This parameter can be one of the following values:
2724 * @arg @ref LL_TIM_CHANNEL_CH1
2725 * @arg @ref LL_TIM_CHANNEL_CH2
2726 * @arg @ref LL_TIM_CHANNEL_CH3
2727 * @arg @ref LL_TIM_CHANNEL_CH4
2728 * @retval Returned value can be one of the following values:
2729 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2730 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2731 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2732 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2733 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2734 {
2735 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2736 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2737 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2738 }
2739
2740 /**
2741 * @brief Set the prescaler of input channel.
2742 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2743 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2744 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2745 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2746 * @param TIMx Timer instance
2747 * @param Channel This parameter can be one of the following values:
2748 * @arg @ref LL_TIM_CHANNEL_CH1
2749 * @arg @ref LL_TIM_CHANNEL_CH2
2750 * @arg @ref LL_TIM_CHANNEL_CH3
2751 * @arg @ref LL_TIM_CHANNEL_CH4
2752 * @param ICPrescaler This parameter can be one of the following values:
2753 * @arg @ref LL_TIM_ICPSC_DIV1
2754 * @arg @ref LL_TIM_ICPSC_DIV2
2755 * @arg @ref LL_TIM_ICPSC_DIV4
2756 * @arg @ref LL_TIM_ICPSC_DIV8
2757 * @retval None
2758 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2759 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2760 {
2761 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2762 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2763 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2764 }
2765
2766 /**
2767 * @brief Get the current prescaler value acting on an input channel.
2768 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2769 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2770 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2771 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2772 * @param TIMx Timer instance
2773 * @param Channel This parameter can be one of the following values:
2774 * @arg @ref LL_TIM_CHANNEL_CH1
2775 * @arg @ref LL_TIM_CHANNEL_CH2
2776 * @arg @ref LL_TIM_CHANNEL_CH3
2777 * @arg @ref LL_TIM_CHANNEL_CH4
2778 * @retval Returned value can be one of the following values:
2779 * @arg @ref LL_TIM_ICPSC_DIV1
2780 * @arg @ref LL_TIM_ICPSC_DIV2
2781 * @arg @ref LL_TIM_ICPSC_DIV4
2782 * @arg @ref LL_TIM_ICPSC_DIV8
2783 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2784 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2785 {
2786 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2787 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2788 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2789 }
2790
2791 /**
2792 * @brief Set the input filter duration.
2793 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2794 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2795 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2796 * CCMR2 IC4F LL_TIM_IC_SetFilter
2797 * @param TIMx Timer instance
2798 * @param Channel This parameter can be one of the following values:
2799 * @arg @ref LL_TIM_CHANNEL_CH1
2800 * @arg @ref LL_TIM_CHANNEL_CH2
2801 * @arg @ref LL_TIM_CHANNEL_CH3
2802 * @arg @ref LL_TIM_CHANNEL_CH4
2803 * @param ICFilter This parameter can be one of the following values:
2804 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2805 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2806 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2807 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2808 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2809 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2810 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2811 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2812 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2813 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2814 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2815 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2816 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2817 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2818 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2819 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2820 * @retval None
2821 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2822 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2823 {
2824 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2825 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2826 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2827 }
2828
2829 /**
2830 * @brief Get the input filter duration.
2831 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2832 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2833 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2834 * CCMR2 IC4F LL_TIM_IC_GetFilter
2835 * @param TIMx Timer instance
2836 * @param Channel This parameter can be one of the following values:
2837 * @arg @ref LL_TIM_CHANNEL_CH1
2838 * @arg @ref LL_TIM_CHANNEL_CH2
2839 * @arg @ref LL_TIM_CHANNEL_CH3
2840 * @arg @ref LL_TIM_CHANNEL_CH4
2841 * @retval Returned value can be one of the following values:
2842 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2843 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2844 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2845 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2846 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2847 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2848 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2849 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2850 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2851 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2852 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2853 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2854 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2855 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2856 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2857 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2858 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2859 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2860 {
2861 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2862 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2863 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2864 }
2865
2866 /**
2867 * @brief Set the input channel polarity.
2868 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2869 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2870 * CCER CC2P LL_TIM_IC_SetPolarity\n
2871 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2872 * CCER CC3P LL_TIM_IC_SetPolarity\n
2873 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2874 * CCER CC4P LL_TIM_IC_SetPolarity\n
2875 * CCER CC4NP LL_TIM_IC_SetPolarity
2876 * @param TIMx Timer instance
2877 * @param Channel This parameter can be one of the following values:
2878 * @arg @ref LL_TIM_CHANNEL_CH1
2879 * @arg @ref LL_TIM_CHANNEL_CH2
2880 * @arg @ref LL_TIM_CHANNEL_CH3
2881 * @arg @ref LL_TIM_CHANNEL_CH4
2882 * @param ICPolarity This parameter can be one of the following values:
2883 * @arg @ref LL_TIM_IC_POLARITY_RISING
2884 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2885 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2886 * @retval None
2887 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2888 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2889 {
2890 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2891 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2892 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2893 }
2894
2895 /**
2896 * @brief Get the current input channel polarity.
2897 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2898 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2899 * CCER CC2P LL_TIM_IC_GetPolarity\n
2900 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2901 * CCER CC3P LL_TIM_IC_GetPolarity\n
2902 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2903 * CCER CC4P LL_TIM_IC_GetPolarity\n
2904 * CCER CC4NP LL_TIM_IC_GetPolarity
2905 * @param TIMx Timer instance
2906 * @param Channel This parameter can be one of the following values:
2907 * @arg @ref LL_TIM_CHANNEL_CH1
2908 * @arg @ref LL_TIM_CHANNEL_CH2
2909 * @arg @ref LL_TIM_CHANNEL_CH3
2910 * @arg @ref LL_TIM_CHANNEL_CH4
2911 * @retval Returned value can be one of the following values:
2912 * @arg @ref LL_TIM_IC_POLARITY_RISING
2913 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2914 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2915 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2916 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2917 {
2918 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2919 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2920 SHIFT_TAB_CCxP[iChannel]);
2921 }
2922
2923 /**
2924 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2925 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2926 * a timer instance provides an XOR input.
2927 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2928 * @param TIMx Timer instance
2929 * @retval None
2930 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2931 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2932 {
2933 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2934 }
2935
2936 /**
2937 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2938 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2939 * a timer instance provides an XOR input.
2940 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2941 * @param TIMx Timer instance
2942 * @retval None
2943 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2944 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2945 {
2946 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2947 }
2948
2949 /**
2950 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2951 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2952 * a timer instance provides an XOR input.
2953 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2954 * @param TIMx Timer instance
2955 * @retval State of bit (1 or 0).
2956 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)2957 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
2958 {
2959 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2960 }
2961
2962 /**
2963 * @brief Get captured value for input channel 1.
2964 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2965 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2966 * whether or not a timer instance supports a 32 bits counter.
2967 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2968 * input channel 1 is supported by a timer instance.
2969 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2970 * @param TIMx Timer instance
2971 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2972 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)2973 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
2974 {
2975 return (uint32_t)(READ_REG(TIMx->CCR1));
2976 }
2977
2978 /**
2979 * @brief Get captured value for input channel 2.
2980 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2981 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2982 * whether or not a timer instance supports a 32 bits counter.
2983 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2984 * input channel 2 is supported by a timer instance.
2985 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2986 * @param TIMx Timer instance
2987 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2988 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)2989 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
2990 {
2991 return (uint32_t)(READ_REG(TIMx->CCR2));
2992 }
2993
2994 /**
2995 * @brief Get captured value for input channel 3.
2996 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2997 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2998 * whether or not a timer instance supports a 32 bits counter.
2999 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3000 * input channel 3 is supported by a timer instance.
3001 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3002 * @param TIMx Timer instance
3003 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3004 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3005 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3006 {
3007 return (uint32_t)(READ_REG(TIMx->CCR3));
3008 }
3009
3010 /**
3011 * @brief Get captured value for input channel 4.
3012 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3013 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3014 * whether or not a timer instance supports a 32 bits counter.
3015 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3016 * input channel 4 is supported by a timer instance.
3017 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3018 * @param TIMx Timer instance
3019 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3020 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3021 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3022 {
3023 return (uint32_t)(READ_REG(TIMx->CCR4));
3024 }
3025
3026 /**
3027 * @}
3028 */
3029
3030 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3031 * @{
3032 */
3033 /**
3034 * @brief Enable external clock mode 2.
3035 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3036 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3037 * whether or not a timer instance supports external clock mode2.
3038 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3039 * @param TIMx Timer instance
3040 * @retval None
3041 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3042 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3043 {
3044 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3045 }
3046
3047 /**
3048 * @brief Disable external clock mode 2.
3049 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3050 * whether or not a timer instance supports external clock mode2.
3051 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3052 * @param TIMx Timer instance
3053 * @retval None
3054 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3055 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3056 {
3057 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3058 }
3059
3060 /**
3061 * @brief Indicate whether external clock mode 2 is enabled.
3062 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3063 * whether or not a timer instance supports external clock mode2.
3064 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3065 * @param TIMx Timer instance
3066 * @retval State of bit (1 or 0).
3067 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3068 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3069 {
3070 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3071 }
3072
3073 /**
3074 * @brief Set the clock source of the counter clock.
3075 * @note when selected clock source is external clock mode 1, the timer input
3076 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3077 * function. This timer input must be configured by calling
3078 * the @ref LL_TIM_IC_Config() function.
3079 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3080 * whether or not a timer instance supports external clock mode1.
3081 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3082 * whether or not a timer instance supports external clock mode2.
3083 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3084 * SMCR ECE LL_TIM_SetClockSource
3085 * @param TIMx Timer instance
3086 * @param ClockSource This parameter can be one of the following values:
3087 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3088 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3089 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3090 * @retval None
3091 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3092 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3093 {
3094 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3095 }
3096
3097 /**
3098 * @brief Set the encoder interface mode.
3099 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3100 * whether or not a timer instance supports the encoder mode.
3101 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3102 * @param TIMx Timer instance
3103 * @param EncoderMode This parameter can be one of the following values:
3104 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3105 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3106 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3107 * @retval None
3108 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3109 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3110 {
3111 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3112 }
3113
3114 /**
3115 * @}
3116 */
3117
3118 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3119 * @{
3120 */
3121 /**
3122 * @brief Set the trigger output (TRGO) used for timer synchronization .
3123 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3124 * whether or not a timer instance can operate as a master timer.
3125 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3126 * @param TIMx Timer instance
3127 * @param TimerSynchronization This parameter can be one of the following values:
3128 * @arg @ref LL_TIM_TRGO_RESET
3129 * @arg @ref LL_TIM_TRGO_ENABLE
3130 * @arg @ref LL_TIM_TRGO_UPDATE
3131 * @arg @ref LL_TIM_TRGO_CC1IF
3132 * @arg @ref LL_TIM_TRGO_OC1REF
3133 * @arg @ref LL_TIM_TRGO_OC2REF
3134 * @arg @ref LL_TIM_TRGO_OC3REF
3135 * @arg @ref LL_TIM_TRGO_OC4REF
3136 * @retval None
3137 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3138 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3139 {
3140 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3141 }
3142
3143 /**
3144 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3145 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3146 * whether or not a timer instance can be used for ADC synchronization.
3147 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3148 * @param TIMx Timer Instance
3149 * @param ADCSynchronization This parameter can be one of the following values:
3150 * @arg @ref LL_TIM_TRGO2_RESET
3151 * @arg @ref LL_TIM_TRGO2_ENABLE
3152 * @arg @ref LL_TIM_TRGO2_UPDATE
3153 * @arg @ref LL_TIM_TRGO2_CC1F
3154 * @arg @ref LL_TIM_TRGO2_OC1
3155 * @arg @ref LL_TIM_TRGO2_OC2
3156 * @arg @ref LL_TIM_TRGO2_OC3
3157 * @arg @ref LL_TIM_TRGO2_OC4
3158 * @arg @ref LL_TIM_TRGO2_OC5
3159 * @arg @ref LL_TIM_TRGO2_OC6
3160 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3161 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3162 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3163 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3164 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3165 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3166 * @retval None
3167 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3168 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3169 {
3170 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3171 }
3172
3173 /**
3174 * @brief Set the synchronization mode of a slave timer.
3175 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3176 * a timer instance can operate as a slave timer.
3177 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3178 * @param TIMx Timer instance
3179 * @param SlaveMode This parameter can be one of the following values:
3180 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3181 * @arg @ref LL_TIM_SLAVEMODE_RESET
3182 * @arg @ref LL_TIM_SLAVEMODE_GATED
3183 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3184 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3185 * @retval None
3186 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3187 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3188 {
3189 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3190 }
3191
3192 /**
3193 * @brief Set the selects the trigger input to be used to synchronize the counter.
3194 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3195 * a timer instance can operate as a slave timer.
3196 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3197 * @param TIMx Timer instance
3198 * @param TriggerInput This parameter can be one of the following values:
3199 * @arg @ref LL_TIM_TS_ITR0
3200 * @arg @ref LL_TIM_TS_ITR1
3201 * @arg @ref LL_TIM_TS_ITR2
3202 * @arg @ref LL_TIM_TS_ITR3
3203 * @arg @ref LL_TIM_TS_TI1F_ED
3204 * @arg @ref LL_TIM_TS_TI1FP1
3205 * @arg @ref LL_TIM_TS_TI2FP2
3206 * @arg @ref LL_TIM_TS_ETRF
3207 * @retval None
3208 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3209 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3210 {
3211 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3212 }
3213
3214 /**
3215 * @brief Enable the Master/Slave mode.
3216 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3217 * a timer instance can operate as a slave timer.
3218 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3219 * @param TIMx Timer instance
3220 * @retval None
3221 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3222 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3223 {
3224 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3225 }
3226
3227 /**
3228 * @brief Disable the Master/Slave mode.
3229 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3230 * a timer instance can operate as a slave timer.
3231 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3232 * @param TIMx Timer instance
3233 * @retval None
3234 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3235 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3236 {
3237 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3238 }
3239
3240 /**
3241 * @brief Indicates whether the Master/Slave mode is enabled.
3242 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3243 * a timer instance can operate as a slave timer.
3244 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3245 * @param TIMx Timer instance
3246 * @retval State of bit (1 or 0).
3247 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3248 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3249 {
3250 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3251 }
3252
3253 /**
3254 * @brief Configure the external trigger (ETR) input.
3255 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3256 * a timer instance provides an external trigger input.
3257 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3258 * SMCR ETPS LL_TIM_ConfigETR\n
3259 * SMCR ETF LL_TIM_ConfigETR
3260 * @param TIMx Timer instance
3261 * @param ETRPolarity This parameter can be one of the following values:
3262 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3263 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3264 * @param ETRPrescaler This parameter can be one of the following values:
3265 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3266 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3267 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3268 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3269 * @param ETRFilter This parameter can be one of the following values:
3270 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3271 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3272 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3273 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3274 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3275 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3276 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3277 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3278 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3279 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3280 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3281 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3282 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3283 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3284 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3285 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3286 * @retval None
3287 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3288 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3289 uint32_t ETRFilter)
3290 {
3291 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3292 }
3293
3294 /**
3295 * @}
3296 */
3297
3298 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3299 * @{
3300 */
3301 /**
3302 * @brief Enable the break function.
3303 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3304 * a timer instance provides a break input.
3305 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3306 * @param TIMx Timer instance
3307 * @retval None
3308 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3309 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3310 {
3311 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3312 }
3313
3314 /**
3315 * @brief Disable the break function.
3316 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3317 * @param TIMx Timer instance
3318 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3319 * a timer instance provides a break input.
3320 * @retval None
3321 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3322 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3323 {
3324 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3325 }
3326
3327 /**
3328 * @brief Configure the break input.
3329 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3330 * a timer instance provides a break input.
3331 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3332 * BDTR BKF LL_TIM_ConfigBRK
3333 * @param TIMx Timer instance
3334 * @param BreakPolarity This parameter can be one of the following values:
3335 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3336 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3337 * @param BreakFilter This parameter can be one of the following values:
3338 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3339 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3340 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3341 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3342 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3343 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3344 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3345 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3346 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3347 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3348 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3349 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3350 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3351 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3352 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3353 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3354 * @retval None
3355 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3356 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3357 uint32_t BreakFilter)
3358 {
3359 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3360 }
3361
3362 /**
3363 * @brief Enable the break 2 function.
3364 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3365 * a timer instance provides a second break input.
3366 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3367 * @param TIMx Timer instance
3368 * @retval None
3369 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3370 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3371 {
3372 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3373 }
3374
3375 /**
3376 * @brief Disable the break 2 function.
3377 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3378 * a timer instance provides a second break input.
3379 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3380 * @param TIMx Timer instance
3381 * @retval None
3382 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3383 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3384 {
3385 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3386 }
3387
3388 /**
3389 * @brief Configure the break 2 input.
3390 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3391 * a timer instance provides a second break input.
3392 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3393 * BDTR BK2F LL_TIM_ConfigBRK2
3394 * @param TIMx Timer instance
3395 * @param Break2Polarity This parameter can be one of the following values:
3396 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3397 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3398 * @param Break2Filter This parameter can be one of the following values:
3399 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3400 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3401 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3402 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3403 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3404 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3405 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3406 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3407 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3408 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3409 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3410 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3411 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3412 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3413 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3414 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3415 * @retval None
3416 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3417 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3418 {
3419 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3420 }
3421
3422 /**
3423 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3424 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3425 * a timer instance provides a break input.
3426 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3427 * BDTR OSSR LL_TIM_SetOffStates
3428 * @param TIMx Timer instance
3429 * @param OffStateIdle This parameter can be one of the following values:
3430 * @arg @ref LL_TIM_OSSI_DISABLE
3431 * @arg @ref LL_TIM_OSSI_ENABLE
3432 * @param OffStateRun This parameter can be one of the following values:
3433 * @arg @ref LL_TIM_OSSR_DISABLE
3434 * @arg @ref LL_TIM_OSSR_ENABLE
3435 * @retval None
3436 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3437 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3438 {
3439 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3440 }
3441
3442 /**
3443 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3444 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3445 * a timer instance provides a break input.
3446 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3447 * @param TIMx Timer instance
3448 * @retval None
3449 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3450 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3451 {
3452 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3453 }
3454
3455 /**
3456 * @brief Disable automatic output (MOE can be set only by software).
3457 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3458 * a timer instance provides a break input.
3459 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3460 * @param TIMx Timer instance
3461 * @retval None
3462 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3463 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3464 {
3465 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3466 }
3467
3468 /**
3469 * @brief Indicate whether automatic output is enabled.
3470 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3471 * a timer instance provides a break input.
3472 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3473 * @param TIMx Timer instance
3474 * @retval State of bit (1 or 0).
3475 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3476 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3477 {
3478 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3479 }
3480
3481 /**
3482 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3483 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3484 * software and is reset in case of break or break2 event
3485 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3486 * a timer instance provides a break input.
3487 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3488 * @param TIMx Timer instance
3489 * @retval None
3490 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3491 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3492 {
3493 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3494 }
3495
3496 /**
3497 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3498 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3499 * software and is reset in case of break or break2 event.
3500 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3501 * a timer instance provides a break input.
3502 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3503 * @param TIMx Timer instance
3504 * @retval None
3505 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3506 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3507 {
3508 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3509 }
3510
3511 /**
3512 * @brief Indicates whether outputs are enabled.
3513 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3514 * a timer instance provides a break input.
3515 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3516 * @param TIMx Timer instance
3517 * @retval State of bit (1 or 0).
3518 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3519 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3520 {
3521 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3522 }
3523
3524 #if defined(TIM_BREAK_INPUT_SUPPORT)
3525 /**
3526 * @brief Enable the signals connected to the designated timer break input.
3527 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3528 * or not a timer instance allows for break input selection.
3529 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3530 * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n
3531 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3532 * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource
3533 * @param TIMx Timer instance
3534 * @param BreakInput This parameter can be one of the following values:
3535 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3536 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3537 * @param Source This parameter can be one of the following values:
3538 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3539 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3540 * @retval None
3541 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3542 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3543 {
3544 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3545 SET_BIT(*pReg, Source);
3546 }
3547
3548 /**
3549 * @brief Disable the signals connected to the designated timer break input.
3550 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3551 * or not a timer instance allows for break input selection.
3552 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3553 * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n
3554 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3555 * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource
3556 * @param TIMx Timer instance
3557 * @param BreakInput This parameter can be one of the following values:
3558 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3559 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3560 * @param Source This parameter can be one of the following values:
3561 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3562 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3563 * @retval None
3564 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3565 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3566 {
3567 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3568 CLEAR_BIT(*pReg, Source);
3569 }
3570
3571 /**
3572 * @brief Set the polarity of the break signal for the timer break input.
3573 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3574 * or not a timer instance allows for break input selection.
3575 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3576 * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n
3577 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3578 * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity
3579 * @param TIMx Timer instance
3580 * @param BreakInput This parameter can be one of the following values:
3581 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3582 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3583 * @param Source This parameter can be one of the following values:
3584 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3585 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3586 * @param Polarity This parameter can be one of the following values:
3587 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3588 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3589 * @retval None
3590 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3591 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3592 uint32_t Polarity)
3593 {
3594 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3595 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3596 }
3597 #endif /* TIM_BREAK_INPUT_SUPPORT */
3598 /**
3599 * @}
3600 */
3601
3602 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3603 * @{
3604 */
3605 /**
3606 * @brief Configures the timer DMA burst feature.
3607 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3608 * not a timer instance supports the DMA burst mode.
3609 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3610 * DCR DBA LL_TIM_ConfigDMABurst
3611 * @param TIMx Timer instance
3612 * @param DMABurstBaseAddress This parameter can be one of the following values:
3613 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3614 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3615 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3616 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3617 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3618 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3619 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3620 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3621 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3622 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3623 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3624 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3625 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3626 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3627 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3628 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3629 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3630 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3631 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
3632 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3633 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3634 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3635 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*)
3636 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*)
3637 * (*) value not defined in all devices
3638 * @param DMABurstLength This parameter can be one of the following values:
3639 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3640 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3641 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3642 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3643 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3644 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3645 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3646 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3647 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3648 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3649 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3650 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3651 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3652 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3653 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3654 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3655 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3656 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3657 * @retval None
3658 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3659 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3660 {
3661 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3662 }
3663
3664 /**
3665 * @}
3666 */
3667
3668 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3669 * @{
3670 */
3671 /**
3672 * @brief Remap TIM inputs (input channel, internal/external triggers).
3673 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3674 * a some timer inputs can be remapped.
3675 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3676 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3677 * TIM11_OR TI1_RMP LL_TIM_SetRemap
3678 * @param TIMx Timer instance
3679 * @param Remap Remap param depends on the TIMx. Description available only
3680 * in CHM version of the User Manual (not in .pdf).
3681 * Otherwise see Reference Manual description of OR registers.
3682 *
3683 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3684 *
3685 * TIM2: one of the following values
3686 *
3687 * ITR1_RMP can be one of the following values
3688 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3689 * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
3690 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3691 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3692 *
3693 * TIM5: one of the following values
3694 *
3695 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3696 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3697 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3698 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3699 *
3700 * TIM11: one of the following values
3701 *
3702 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3703 * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX
3704 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE
3705 * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1
3706 *
3707 * @retval None
3708 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3709 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3710 {
3711 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3712 }
3713
3714 /**
3715 * @}
3716 */
3717
3718 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3719 * @{
3720 */
3721 /**
3722 * @brief Clear the update interrupt flag (UIF).
3723 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3724 * @param TIMx Timer instance
3725 * @retval None
3726 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3727 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3728 {
3729 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3730 }
3731
3732 /**
3733 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3734 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3735 * @param TIMx Timer instance
3736 * @retval State of bit (1 or 0).
3737 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3738 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3739 {
3740 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3741 }
3742
3743 /**
3744 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3745 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3746 * @param TIMx Timer instance
3747 * @retval None
3748 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3749 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3750 {
3751 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3752 }
3753
3754 /**
3755 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3756 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3757 * @param TIMx Timer instance
3758 * @retval State of bit (1 or 0).
3759 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3760 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3761 {
3762 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3763 }
3764
3765 /**
3766 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3767 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3768 * @param TIMx Timer instance
3769 * @retval None
3770 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3771 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3772 {
3773 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3774 }
3775
3776 /**
3777 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3778 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3779 * @param TIMx Timer instance
3780 * @retval State of bit (1 or 0).
3781 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3782 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3783 {
3784 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3785 }
3786
3787 /**
3788 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3789 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3790 * @param TIMx Timer instance
3791 * @retval None
3792 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3793 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3794 {
3795 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3796 }
3797
3798 /**
3799 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3800 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3801 * @param TIMx Timer instance
3802 * @retval State of bit (1 or 0).
3803 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3804 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3805 {
3806 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3807 }
3808
3809 /**
3810 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3811 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3812 * @param TIMx Timer instance
3813 * @retval None
3814 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3815 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3816 {
3817 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3818 }
3819
3820 /**
3821 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3822 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3823 * @param TIMx Timer instance
3824 * @retval State of bit (1 or 0).
3825 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)3826 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
3827 {
3828 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3829 }
3830
3831 /**
3832 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
3833 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
3834 * @param TIMx Timer instance
3835 * @retval None
3836 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)3837 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
3838 {
3839 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
3840 }
3841
3842 /**
3843 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
3844 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
3845 * @param TIMx Timer instance
3846 * @retval State of bit (1 or 0).
3847 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)3848 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
3849 {
3850 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
3851 }
3852
3853 /**
3854 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
3855 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
3856 * @param TIMx Timer instance
3857 * @retval None
3858 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)3859 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
3860 {
3861 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
3862 }
3863
3864 /**
3865 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
3866 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
3867 * @param TIMx Timer instance
3868 * @retval State of bit (1 or 0).
3869 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)3870 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
3871 {
3872 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
3873 }
3874
3875 /**
3876 * @brief Clear the commutation interrupt flag (COMIF).
3877 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3878 * @param TIMx Timer instance
3879 * @retval None
3880 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3881 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3882 {
3883 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3884 }
3885
3886 /**
3887 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3888 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3889 * @param TIMx Timer instance
3890 * @retval State of bit (1 or 0).
3891 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)3892 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
3893 {
3894 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3895 }
3896
3897 /**
3898 * @brief Clear the trigger interrupt flag (TIF).
3899 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3900 * @param TIMx Timer instance
3901 * @retval None
3902 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3903 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3904 {
3905 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3906 }
3907
3908 /**
3909 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3910 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3911 * @param TIMx Timer instance
3912 * @retval State of bit (1 or 0).
3913 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)3914 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
3915 {
3916 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3917 }
3918
3919 /**
3920 * @brief Clear the break interrupt flag (BIF).
3921 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3922 * @param TIMx Timer instance
3923 * @retval None
3924 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3925 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3926 {
3927 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3928 }
3929
3930 /**
3931 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3932 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3933 * @param TIMx Timer instance
3934 * @retval State of bit (1 or 0).
3935 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)3936 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
3937 {
3938 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3939 }
3940
3941 /**
3942 * @brief Clear the break 2 interrupt flag (B2IF).
3943 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
3944 * @param TIMx Timer instance
3945 * @retval None
3946 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)3947 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
3948 {
3949 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
3950 }
3951
3952 /**
3953 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
3954 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
3955 * @param TIMx Timer instance
3956 * @retval State of bit (1 or 0).
3957 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)3958 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
3959 {
3960 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
3961 }
3962
3963 /**
3964 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3965 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3966 * @param TIMx Timer instance
3967 * @retval None
3968 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3969 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3970 {
3971 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3972 }
3973
3974 /**
3975 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3976 * (Capture/Compare 1 interrupt is pending).
3977 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3978 * @param TIMx Timer instance
3979 * @retval State of bit (1 or 0).
3980 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)3981 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
3982 {
3983 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3984 }
3985
3986 /**
3987 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3988 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3989 * @param TIMx Timer instance
3990 * @retval None
3991 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3992 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3993 {
3994 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3995 }
3996
3997 /**
3998 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3999 * (Capture/Compare 2 over-capture interrupt is pending).
4000 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4001 * @param TIMx Timer instance
4002 * @retval State of bit (1 or 0).
4003 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4004 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4005 {
4006 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4007 }
4008
4009 /**
4010 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4011 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4012 * @param TIMx Timer instance
4013 * @retval None
4014 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4015 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4016 {
4017 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4018 }
4019
4020 /**
4021 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4022 * (Capture/Compare 3 over-capture interrupt is pending).
4023 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4024 * @param TIMx Timer instance
4025 * @retval State of bit (1 or 0).
4026 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4027 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4028 {
4029 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4030 }
4031
4032 /**
4033 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4034 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4035 * @param TIMx Timer instance
4036 * @retval None
4037 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4038 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4039 {
4040 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4041 }
4042
4043 /**
4044 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4045 * (Capture/Compare 4 over-capture interrupt is pending).
4046 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4047 * @param TIMx Timer instance
4048 * @retval State of bit (1 or 0).
4049 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4050 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4051 {
4052 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4053 }
4054
4055 /**
4056 * @brief Clear the system break interrupt flag (SBIF).
4057 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4058 * @param TIMx Timer instance
4059 * @retval None
4060 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4061 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4062 {
4063 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4064 }
4065
4066 /**
4067 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4068 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4069 * @param TIMx Timer instance
4070 * @retval State of bit (1 or 0).
4071 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4072 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4073 {
4074 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4075 }
4076
4077 /**
4078 * @}
4079 */
4080
4081 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4082 * @{
4083 */
4084 /**
4085 * @brief Enable update interrupt (UIE).
4086 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4087 * @param TIMx Timer instance
4088 * @retval None
4089 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4090 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4091 {
4092 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4093 }
4094
4095 /**
4096 * @brief Disable update interrupt (UIE).
4097 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4098 * @param TIMx Timer instance
4099 * @retval None
4100 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4101 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4102 {
4103 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4104 }
4105
4106 /**
4107 * @brief Indicates whether the update interrupt (UIE) is enabled.
4108 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4109 * @param TIMx Timer instance
4110 * @retval State of bit (1 or 0).
4111 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4112 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4113 {
4114 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4115 }
4116
4117 /**
4118 * @brief Enable capture/compare 1 interrupt (CC1IE).
4119 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4120 * @param TIMx Timer instance
4121 * @retval None
4122 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4123 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4124 {
4125 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4126 }
4127
4128 /**
4129 * @brief Disable capture/compare 1 interrupt (CC1IE).
4130 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4131 * @param TIMx Timer instance
4132 * @retval None
4133 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4134 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4135 {
4136 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4137 }
4138
4139 /**
4140 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4141 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4142 * @param TIMx Timer instance
4143 * @retval State of bit (1 or 0).
4144 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4145 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4146 {
4147 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4148 }
4149
4150 /**
4151 * @brief Enable capture/compare 2 interrupt (CC2IE).
4152 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4153 * @param TIMx Timer instance
4154 * @retval None
4155 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4156 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4157 {
4158 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4159 }
4160
4161 /**
4162 * @brief Disable capture/compare 2 interrupt (CC2IE).
4163 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4164 * @param TIMx Timer instance
4165 * @retval None
4166 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4167 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4168 {
4169 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4170 }
4171
4172 /**
4173 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4174 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4175 * @param TIMx Timer instance
4176 * @retval State of bit (1 or 0).
4177 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4178 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4179 {
4180 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4181 }
4182
4183 /**
4184 * @brief Enable capture/compare 3 interrupt (CC3IE).
4185 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4186 * @param TIMx Timer instance
4187 * @retval None
4188 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4189 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4190 {
4191 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4192 }
4193
4194 /**
4195 * @brief Disable capture/compare 3 interrupt (CC3IE).
4196 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4197 * @param TIMx Timer instance
4198 * @retval None
4199 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4200 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4201 {
4202 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4203 }
4204
4205 /**
4206 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4207 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4208 * @param TIMx Timer instance
4209 * @retval State of bit (1 or 0).
4210 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4211 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4212 {
4213 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4214 }
4215
4216 /**
4217 * @brief Enable capture/compare 4 interrupt (CC4IE).
4218 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4219 * @param TIMx Timer instance
4220 * @retval None
4221 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4222 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4223 {
4224 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4225 }
4226
4227 /**
4228 * @brief Disable capture/compare 4 interrupt (CC4IE).
4229 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4230 * @param TIMx Timer instance
4231 * @retval None
4232 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4233 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4234 {
4235 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4236 }
4237
4238 /**
4239 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4240 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4241 * @param TIMx Timer instance
4242 * @retval State of bit (1 or 0).
4243 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4244 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4245 {
4246 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4247 }
4248
4249 /**
4250 * @brief Enable commutation interrupt (COMIE).
4251 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4252 * @param TIMx Timer instance
4253 * @retval None
4254 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4255 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4256 {
4257 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4258 }
4259
4260 /**
4261 * @brief Disable commutation interrupt (COMIE).
4262 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4263 * @param TIMx Timer instance
4264 * @retval None
4265 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4266 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4267 {
4268 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4269 }
4270
4271 /**
4272 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4273 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4274 * @param TIMx Timer instance
4275 * @retval State of bit (1 or 0).
4276 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4277 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4278 {
4279 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4280 }
4281
4282 /**
4283 * @brief Enable trigger interrupt (TIE).
4284 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4285 * @param TIMx Timer instance
4286 * @retval None
4287 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4288 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4289 {
4290 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4291 }
4292
4293 /**
4294 * @brief Disable trigger interrupt (TIE).
4295 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4296 * @param TIMx Timer instance
4297 * @retval None
4298 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4299 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4300 {
4301 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4302 }
4303
4304 /**
4305 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4306 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4307 * @param TIMx Timer instance
4308 * @retval State of bit (1 or 0).
4309 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4310 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4311 {
4312 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4313 }
4314
4315 /**
4316 * @brief Enable break interrupt (BIE).
4317 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4318 * @param TIMx Timer instance
4319 * @retval None
4320 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4321 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4322 {
4323 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4324 }
4325
4326 /**
4327 * @brief Disable break interrupt (BIE).
4328 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4329 * @param TIMx Timer instance
4330 * @retval None
4331 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4332 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4333 {
4334 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4335 }
4336
4337 /**
4338 * @brief Indicates whether the break interrupt (BIE) is enabled.
4339 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4340 * @param TIMx Timer instance
4341 * @retval State of bit (1 or 0).
4342 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4343 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4344 {
4345 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4346 }
4347
4348 /**
4349 * @}
4350 */
4351
4352 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4353 * @{
4354 */
4355 /**
4356 * @brief Enable update DMA request (UDE).
4357 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4358 * @param TIMx Timer instance
4359 * @retval None
4360 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4361 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4362 {
4363 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4364 }
4365
4366 /**
4367 * @brief Disable update DMA request (UDE).
4368 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4369 * @param TIMx Timer instance
4370 * @retval None
4371 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4372 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4373 {
4374 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4375 }
4376
4377 /**
4378 * @brief Indicates whether the update DMA request (UDE) is enabled.
4379 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4380 * @param TIMx Timer instance
4381 * @retval State of bit (1 or 0).
4382 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4383 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4384 {
4385 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4386 }
4387
4388 /**
4389 * @brief Enable capture/compare 1 DMA request (CC1DE).
4390 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4391 * @param TIMx Timer instance
4392 * @retval None
4393 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4394 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4395 {
4396 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4397 }
4398
4399 /**
4400 * @brief Disable capture/compare 1 DMA request (CC1DE).
4401 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4402 * @param TIMx Timer instance
4403 * @retval None
4404 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4405 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4406 {
4407 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4408 }
4409
4410 /**
4411 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4412 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4413 * @param TIMx Timer instance
4414 * @retval State of bit (1 or 0).
4415 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4416 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4417 {
4418 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4419 }
4420
4421 /**
4422 * @brief Enable capture/compare 2 DMA request (CC2DE).
4423 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4424 * @param TIMx Timer instance
4425 * @retval None
4426 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4427 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4428 {
4429 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4430 }
4431
4432 /**
4433 * @brief Disable capture/compare 2 DMA request (CC2DE).
4434 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4435 * @param TIMx Timer instance
4436 * @retval None
4437 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4438 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4439 {
4440 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4441 }
4442
4443 /**
4444 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4445 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4446 * @param TIMx Timer instance
4447 * @retval State of bit (1 or 0).
4448 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4449 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4450 {
4451 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4452 }
4453
4454 /**
4455 * @brief Enable capture/compare 3 DMA request (CC3DE).
4456 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4457 * @param TIMx Timer instance
4458 * @retval None
4459 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4460 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4461 {
4462 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4463 }
4464
4465 /**
4466 * @brief Disable capture/compare 3 DMA request (CC3DE).
4467 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4468 * @param TIMx Timer instance
4469 * @retval None
4470 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4471 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4472 {
4473 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4474 }
4475
4476 /**
4477 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4478 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4479 * @param TIMx Timer instance
4480 * @retval State of bit (1 or 0).
4481 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4482 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4483 {
4484 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4485 }
4486
4487 /**
4488 * @brief Enable capture/compare 4 DMA request (CC4DE).
4489 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4490 * @param TIMx Timer instance
4491 * @retval None
4492 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4493 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4494 {
4495 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4496 }
4497
4498 /**
4499 * @brief Disable capture/compare 4 DMA request (CC4DE).
4500 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4501 * @param TIMx Timer instance
4502 * @retval None
4503 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4504 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4505 {
4506 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4507 }
4508
4509 /**
4510 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4511 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4512 * @param TIMx Timer instance
4513 * @retval State of bit (1 or 0).
4514 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4515 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4516 {
4517 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4518 }
4519
4520 /**
4521 * @brief Enable commutation DMA request (COMDE).
4522 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4523 * @param TIMx Timer instance
4524 * @retval None
4525 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4526 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4527 {
4528 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4529 }
4530
4531 /**
4532 * @brief Disable commutation DMA request (COMDE).
4533 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4534 * @param TIMx Timer instance
4535 * @retval None
4536 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4537 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4538 {
4539 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4540 }
4541
4542 /**
4543 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4544 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4545 * @param TIMx Timer instance
4546 * @retval State of bit (1 or 0).
4547 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4548 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4549 {
4550 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4551 }
4552
4553 /**
4554 * @brief Enable trigger interrupt (TDE).
4555 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4556 * @param TIMx Timer instance
4557 * @retval None
4558 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4559 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4560 {
4561 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4562 }
4563
4564 /**
4565 * @brief Disable trigger interrupt (TDE).
4566 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4567 * @param TIMx Timer instance
4568 * @retval None
4569 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4570 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4571 {
4572 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4573 }
4574
4575 /**
4576 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4577 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4578 * @param TIMx Timer instance
4579 * @retval State of bit (1 or 0).
4580 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4581 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4582 {
4583 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4584 }
4585
4586 /**
4587 * @}
4588 */
4589
4590 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4591 * @{
4592 */
4593 /**
4594 * @brief Generate an update event.
4595 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4596 * @param TIMx Timer instance
4597 * @retval None
4598 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4599 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4600 {
4601 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4602 }
4603
4604 /**
4605 * @brief Generate Capture/Compare 1 event.
4606 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4607 * @param TIMx Timer instance
4608 * @retval None
4609 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4610 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4611 {
4612 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4613 }
4614
4615 /**
4616 * @brief Generate Capture/Compare 2 event.
4617 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4618 * @param TIMx Timer instance
4619 * @retval None
4620 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4621 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4622 {
4623 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4624 }
4625
4626 /**
4627 * @brief Generate Capture/Compare 3 event.
4628 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4629 * @param TIMx Timer instance
4630 * @retval None
4631 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4632 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4633 {
4634 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4635 }
4636
4637 /**
4638 * @brief Generate Capture/Compare 4 event.
4639 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4640 * @param TIMx Timer instance
4641 * @retval None
4642 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4643 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4644 {
4645 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4646 }
4647
4648 /**
4649 * @brief Generate commutation event.
4650 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4651 * @param TIMx Timer instance
4652 * @retval None
4653 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4654 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4655 {
4656 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4657 }
4658
4659 /**
4660 * @brief Generate trigger event.
4661 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4662 * @param TIMx Timer instance
4663 * @retval None
4664 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4665 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4666 {
4667 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4668 }
4669
4670 /**
4671 * @brief Generate break event.
4672 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4673 * @param TIMx Timer instance
4674 * @retval None
4675 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4676 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4677 {
4678 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4679 }
4680
4681 /**
4682 * @brief Generate break 2 event.
4683 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4684 * @param TIMx Timer instance
4685 * @retval None
4686 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4687 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4688 {
4689 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4690 }
4691
4692 /**
4693 * @}
4694 */
4695
4696 #if defined(USE_FULL_LL_DRIVER)
4697 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4698 * @{
4699 */
4700
4701 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4702 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4703 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4704 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4705 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4706 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4707 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4708 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4709 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4710 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4711 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4712 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4713 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4714 /**
4715 * @}
4716 */
4717 #endif /* USE_FULL_LL_DRIVER */
4718
4719 /**
4720 * @}
4721 */
4722
4723 /**
4724 * @}
4725 */
4726
4727 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
4728
4729 /**
4730 * @}
4731 */
4732
4733 #ifdef __cplusplus
4734 }
4735 #endif
4736
4737 #endif /* __STM32F7xx_LL_TIM_H */
4738
