1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F7xx_LL_SDMMC_H 22 #define STM32F7xx_LL_SDMMC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if defined(SDMMC1) 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32f7xx_hal_def.h" 32 33 /** @addtogroup STM32F7xx_Driver 34 * @{ 35 */ 36 37 /** @addtogroup SDMMC_LL 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief SDMMC Configuration Structure definition 48 */ 49 typedef struct 50 { 51 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 52 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 53 54 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is 55 enabled or disabled. 56 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ 57 58 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 59 disabled when the bus is idle. 60 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 61 62 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 63 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 64 65 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 66 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 67 68 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 69 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 70 71 }SDMMC_InitTypeDef; 72 73 74 /** 75 * @brief SDMMC Command Control structure 76 */ 77 typedef struct 78 { 79 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 80 to a card as part of a command message. If a command 81 contains an argument, it must be loaded into this register 82 before writing the command to the command register. */ 83 84 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 85 Max_Data = 64 */ 86 87 uint32_t Response; /*!< Specifies the SDMMC response type. 88 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 89 90 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 91 enabled or disabled. 92 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 93 94 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 95 is enabled or disabled. 96 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 97 }SDMMC_CmdInitTypeDef; 98 99 100 /** 101 * @brief SDMMC Data Control structure 102 */ 103 typedef struct 104 { 105 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 106 107 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 108 109 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 110 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 111 112 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 113 is a read or write. 114 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 115 116 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 117 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 118 119 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 120 is enabled or disabled. 121 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 122 }SDMMC_DataInitTypeDef; 123 124 /** 125 * @} 126 */ 127 128 /* Exported constants --------------------------------------------------------*/ 129 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 130 * @{ 131 */ 132 #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ 133 #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ 134 #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ 135 #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ 136 #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ 137 #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ 138 #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ 139 #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ 140 #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the 141 number of transferred bytes does not match the block length */ 142 #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ 143 #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ 144 #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ 145 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock 146 command or if there was an attempt to access a locked card */ 147 #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ 148 #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ 149 #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ 150 #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ 151 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ 152 #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ 153 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ 154 #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ 155 #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ 156 #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ 157 #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out 158 of erase sequence command was received */ 159 #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ 160 #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ 161 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ 162 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ 163 #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ 164 #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ 165 #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ 166 #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ 167 #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ 168 169 /** 170 * @brief SDMMC Commands Index 171 */ 172 #define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ 173 #define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ 174 #define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 175 #define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ 176 #define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ 177 #define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 178 operating condition register (OCR) content in the response on the CMD line. */ 179 #define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 180 #define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ 181 #define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 182 and asks the card whether card supports voltage. */ 183 #define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 184 #define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ 185 #define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ 186 #define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ 187 #define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ 188 #define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ 189 #define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ 190 #define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands 191 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 192 for SDHS and SDXC. */ 193 #define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 194 fixed 512 bytes in case of SDHC and SDXC. */ 195 #define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by 196 STOP_TRANSMISSION command. */ 197 #define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 198 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ 199 #define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ 200 #define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 201 fixed 512 bytes in case of SDHC and SDXC. */ 202 #define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 203 #define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ 204 #define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ 205 #define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ 206 #define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ 207 #define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ 208 #define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ 209 #define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ 210 #define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command 211 system set by switch function command (CMD6). */ 212 #define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. 213 Reserved for each command system set by switch function command (CMD6). */ 214 #define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ 215 #define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ 216 #define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ 217 #define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 218 the SET_BLOCK_LEN command. */ 219 #define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather 220 than a standard command. */ 221 #define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card 222 for general purpose/application specific commands. */ 223 #define SDMMC_CMD_NO_CMD 64U /*!< No command */ 224 225 /** 226 * @brief Following commands are SD Card Specific commands. 227 * SDMMC_APP_CMD should be sent before sending these commands. 228 */ 229 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 230 widths are given in SCR register. */ 231 #define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ 232 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 233 32bit+CRC data block. */ 234 #define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 235 send its operating condition register (OCR) content in the response on the CMD line. */ 236 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 237 #define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ 238 #define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ 239 #define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ 240 241 /** 242 * @brief Following commands are SD Card Specific security commands. 243 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 244 */ 245 #define SDMMC_CMD_SD_APP_GET_MKB 43U 246 #define SDMMC_CMD_SD_APP_GET_MID 44U 247 #define SDMMC_CMD_SD_APP_SET_CER_RN1 45U 248 #define SDMMC_CMD_SD_APP_GET_CER_RN2 46U 249 #define SDMMC_CMD_SD_APP_SET_CER_RES2 47U 250 #define SDMMC_CMD_SD_APP_GET_CER_RES1 48U 251 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U 252 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U 253 #define SDMMC_CMD_SD_APP_SECURE_ERASE 38U 254 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U 255 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U 256 257 /** 258 * @brief Masks for errors Card Status R1 (OCR Register) 259 */ 260 #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U 261 #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U 262 #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U 263 #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U 264 #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U 265 #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U 266 #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U 267 #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U 268 #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U 269 #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U 270 #define SDMMC_OCR_CC_ERROR 0x00100000U 271 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U 272 #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U 273 #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U 274 #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U 275 #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U 276 #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U 277 #define SDMMC_OCR_ERASE_RESET 0x00002000U 278 #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U 279 #define SDMMC_OCR_ERRORBITS 0xFDFFE008U 280 281 /** 282 * @brief Masks for R6 Response 283 */ 284 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U 285 #define SDMMC_R6_ILLEGAL_CMD 0x00004000U 286 #define SDMMC_R6_COM_CRC_FAILED 0x00008000U 287 288 #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U 289 #define SDMMC_HIGH_CAPACITY 0x40000000U 290 #define SDMMC_STD_CAPACITY 0x00000000U 291 #define SDMMC_CHECK_PATTERN 0x000001AAU 292 #define SD_SWITCH_1_8V_CAPACITY 0x01000000U 293 294 #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU 295 296 #define SDMMC_MAX_TRIAL 0x0000FFFFU 297 298 #define SDMMC_ALLZERO 0x00000000U 299 300 #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U 301 #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U 302 #define SDMMC_CARD_LOCKED 0x02000000U 303 304 #ifndef SDMMC_DATATIMEOUT 305 #define SDMMC_DATATIMEOUT 0xFFFFFFFFU 306 #endif /* SDMMC_DATATIMEOUT */ 307 308 #define SDMMC_0TO7BITS 0x000000FFU 309 #define SDMMC_8TO15BITS 0x0000FF00U 310 #define SDMMC_16TO23BITS 0x00FF0000U 311 #define SDMMC_24TO31BITS 0xFF000000U 312 #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU 313 314 #define SDMMC_HALFFIFO 0x00000008U 315 #define SDMMC_HALFFIFOBYTES 0x00000020U 316 317 /** 318 * @brief Command Class supported 319 */ 320 #define SDMMC_CCCC_ERASE 0x00000020U 321 322 #define SDMMC_CMDTIMEOUT 5000U /* Command send and response timeout */ 323 #define SDMMC_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ 324 #define SDMMC_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ 325 326 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 327 * @{ 328 */ 329 #define SDMMC_CLOCK_EDGE_RISING 0x00000000U 330 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 331 332 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 333 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 334 /** 335 * @} 336 */ 337 338 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass 339 * @{ 340 */ 341 #define SDMMC_CLOCK_BYPASS_DISABLE 0x00000000U 342 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS 343 344 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ 345 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) 346 /** 347 * @} 348 */ 349 350 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 351 * @{ 352 */ 353 #define SDMMC_CLOCK_POWER_SAVE_DISABLE 0x00000000U 354 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 355 356 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 357 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 358 /** 359 * @} 360 */ 361 362 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 363 * @{ 364 */ 365 #define SDMMC_BUS_WIDE_1B 0x00000000U 366 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 367 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 368 369 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 370 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 371 ((WIDE) == SDMMC_BUS_WIDE_8B)) 372 /** 373 * @} 374 */ 375 376 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 377 * @{ 378 */ 379 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U 380 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 381 382 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 383 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 384 /** 385 * @} 386 */ 387 388 /** @defgroup SDMMC_LL_Clock_Division Clock Division 389 * @{ 390 */ 391 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) 392 /** 393 * @} 394 */ 395 396 /** @defgroup SDMMC_LL_Command_Index Command Index 397 * @{ 398 */ 399 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 400 /** 401 * @} 402 */ 403 404 /** @defgroup SDMMC_LL_Response_Type Response Type 405 * @{ 406 */ 407 #define SDMMC_RESPONSE_NO 0x00000000U 408 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 409 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 410 411 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 412 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 413 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 414 /** 415 * @} 416 */ 417 418 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 419 * @{ 420 */ 421 #define SDMMC_WAIT_NO 0x00000000U 422 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 423 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 424 425 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 426 ((WAIT) == SDMMC_WAIT_IT) || \ 427 ((WAIT) == SDMMC_WAIT_PEND)) 428 /** 429 * @} 430 */ 431 432 /** @defgroup SDMMC_LL_CPSM_State CPSM State 433 * @{ 434 */ 435 #define SDMMC_CPSM_DISABLE 0x00000000U 436 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 437 438 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 439 ((CPSM) == SDMMC_CPSM_ENABLE)) 440 /** 441 * @} 442 */ 443 444 /** @defgroup SDMMC_LL_Response_Registers Response Register 445 * @{ 446 */ 447 #define SDMMC_RESP1 0x00000000U 448 #define SDMMC_RESP2 0x00000004U 449 #define SDMMC_RESP3 0x00000008U 450 #define SDMMC_RESP4 0x0000000CU 451 452 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 453 ((RESP) == SDMMC_RESP2) || \ 454 ((RESP) == SDMMC_RESP3) || \ 455 ((RESP) == SDMMC_RESP4)) 456 /** 457 * @} 458 */ 459 460 /** @defgroup SDMMC_LL_Data_Length Data Length 461 * @{ 462 */ 463 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 464 /** 465 * @} 466 */ 467 468 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 469 * @{ 470 */ 471 #define SDMMC_DATABLOCK_SIZE_1B 0x00000000U 472 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 473 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 474 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 475 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 476 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 477 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 478 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 479 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 480 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 481 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 482 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 483 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 484 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 485 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 486 487 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 488 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 489 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 490 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 491 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 492 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 493 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 494 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 495 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 496 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 497 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 498 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 499 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 500 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 501 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 502 /** 503 * @} 504 */ 505 506 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 507 * @{ 508 */ 509 #define SDMMC_TRANSFER_DIR_TO_CARD 0x00000000U 510 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 511 512 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 513 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 514 /** 515 * @} 516 */ 517 518 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 519 * @{ 520 */ 521 #define SDMMC_TRANSFER_MODE_BLOCK 0x00000000U 522 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE 523 524 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 525 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 526 /** 527 * @} 528 */ 529 530 /** @defgroup SDMMC_LL_DPSM_State DPSM State 531 * @{ 532 */ 533 #define SDMMC_DPSM_DISABLE 0x00000000U 534 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 535 536 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 537 ((DPSM) == SDMMC_DPSM_ENABLE)) 538 /** 539 * @} 540 */ 541 542 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 543 * @{ 544 */ 545 #define SDMMC_READ_WAIT_MODE_DATA2 0x00000000U 546 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 547 548 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 549 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 550 /** 551 * @} 552 */ 553 554 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 555 * @{ 556 */ 557 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 558 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 559 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 560 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 561 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 562 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 563 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 564 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 565 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 566 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 567 #define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE 568 #define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE 569 #define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE 570 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 571 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 572 #define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE 573 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 574 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 575 #define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE 576 #define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE 577 #define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE 578 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 579 /** 580 * @} 581 */ 582 583 /** @defgroup SDMMC_LL_Flags Flags 584 * @{ 585 */ 586 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 587 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 588 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 589 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 590 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 591 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 592 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 593 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 594 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 595 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 596 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT 597 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT 598 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT 599 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 600 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 601 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 602 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 603 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 604 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 605 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL 606 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL 607 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 608 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 609 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 610 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 611 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) 612 613 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 614 SDMMC_FLAG_CMDSENT)) 615 616 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 617 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) 618 /** 619 * @} 620 */ 621 622 /** 623 * @} 624 */ 625 626 /* Exported macro ------------------------------------------------------------*/ 627 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 628 * @{ 629 */ 630 631 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 632 * @brief SDMMC_LL registers bit address in the alias region 633 * @{ 634 */ 635 /* ---------------------- SDMMC registers bit mask --------------------------- */ 636 /* --- CLKCR Register ---*/ 637 /* CLKCR register clear mask */ 638 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 639 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ 640 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 641 642 /* --- DCTRL Register ---*/ 643 /* SDMMC DCTRL Clear Mask */ 644 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 645 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 646 647 /* --- CMD Register ---*/ 648 /* CMD Register clear mask */ 649 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 650 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 651 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) 652 653 /* SDMMC Initialization Frequency (400KHz max) */ 654 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ 655 656 /* SDMMC Data Transfer Frequency (25MHz max) */ 657 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ 658 /** 659 * @} 660 */ 661 662 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 663 * @brief macros to handle interrupts and specific clock configurations 664 * @{ 665 */ 666 667 /** 668 * @brief Enable the SDMMC device. 669 * @param __INSTANCE__: SDMMC Instance 670 * @retval None 671 */ 672 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) 673 674 /** 675 * @brief Disable the SDMMC device. 676 * @param __INSTANCE__: SDMMC Instance 677 * @retval None 678 */ 679 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) 680 681 /** 682 * @brief Enable the SDMMC DMA transfer. 683 * @param __INSTANCE__: SDMMC Instance 684 * @retval None 685 */ 686 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) 687 688 /** 689 * @brief Disable the SDMMC DMA transfer. 690 * @param __INSTANCE__: SDMMC Instance 691 * @retval None 692 */ 693 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) 694 695 /** 696 * @brief Enable the SDMMC device interrupt. 697 * @param __INSTANCE__ : Pointer to SDMMC register base 698 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. 699 * This parameter can be one or a combination of the following values: 700 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 701 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 702 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 703 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 704 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 705 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 706 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 707 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 708 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 709 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 710 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 711 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 712 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 713 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 714 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 715 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 716 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 717 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 718 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 719 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 720 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 721 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 722 * @retval None 723 */ 724 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 725 726 /** 727 * @brief Disable the SDMMC device interrupt. 728 * @param __INSTANCE__ : Pointer to SDMMC register base 729 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. 730 * This parameter can be one or a combination of the following values: 731 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 732 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 733 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 734 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 735 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 736 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 737 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 738 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 739 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 740 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 741 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 742 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 743 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 744 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 745 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 746 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 747 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 748 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 749 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 750 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 751 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 752 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 753 * @retval None 754 */ 755 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 756 757 /** 758 * @brief Checks whether the specified SDMMC flag is set or not. 759 * @param __INSTANCE__ : Pointer to SDMMC register base 760 * @param __FLAG__: specifies the flag to check. 761 * This parameter can be one of the following values: 762 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 763 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 764 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 765 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 766 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 767 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 768 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 769 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 770 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 771 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 772 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress 773 * @arg SDMMC_FLAG_TXACT: Data transmit in progress 774 * @arg SDMMC_FLAG_RXACT: Data receive in progress 775 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 776 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 777 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 778 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 779 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 780 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 781 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO 782 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO 783 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 784 * @retval The new state of SDMMC_FLAG (SET or RESET). 785 */ 786 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 787 788 789 /** 790 * @brief Clears the SDMMC pending flags. 791 * @param __INSTANCE__ : Pointer to SDMMC register base 792 * @param __FLAG__: specifies the flag to clear. 793 * This parameter can be one or a combination of the following values: 794 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 795 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 796 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 797 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 798 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 799 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 800 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 801 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 802 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 803 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 804 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 805 * @retval None 806 */ 807 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 808 809 /** 810 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 811 * @param __INSTANCE__ : Pointer to SDMMC register base 812 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. 813 * This parameter can be one of the following values: 814 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 815 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 816 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 817 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 818 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 819 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 820 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 821 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 822 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 823 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 824 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 825 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 826 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 827 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 828 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 829 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 830 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 831 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 832 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 833 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 834 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 835 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 836 * @retval The new state of SDMMC_IT (SET or RESET). 837 */ 838 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 839 840 /** 841 * @brief Clears the SDMMC's interrupt pending bits. 842 * @param __INSTANCE__ : Pointer to SDMMC register base 843 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 844 * This parameter can be one or a combination of the following values: 845 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 846 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 847 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 848 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 849 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 850 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 851 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 852 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 853 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 854 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 855 * @retval None 856 */ 857 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 858 859 /** 860 * @brief Enable Start the SD I/O Read Wait operation. 861 * @param __INSTANCE__ : Pointer to SDMMC register base 862 * @retval None 863 */ 864 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 865 866 /** 867 * @brief Disable Start the SD I/O Read Wait operations. 868 * @param __INSTANCE__ : Pointer to SDMMC register base 869 * @retval None 870 */ 871 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 872 873 /** 874 * @brief Enable Start the SD I/O Read Wait operation. 875 * @param __INSTANCE__ : Pointer to SDMMC register base 876 * @retval None 877 */ 878 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 879 880 /** 881 * @brief Disable Stop the SD I/O Read Wait operations. 882 * @param __INSTANCE__ : Pointer to SDMMC register base 883 * @retval None 884 */ 885 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 886 887 /** 888 * @brief Enable the SD I/O Mode Operation. 889 * @param __INSTANCE__ : Pointer to SDMMC register base 890 * @retval None 891 */ 892 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 893 894 /** 895 * @brief Disable the SD I/O Mode Operation. 896 * @param __INSTANCE__ : Pointer to SDMMC register base 897 * @retval None 898 */ 899 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 900 901 /** 902 * @brief Enable the SD I/O Suspend command sending. 903 * @param __INSTANCE__ : Pointer to SDMMC register base 904 * @retval None 905 */ 906 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 907 908 /** 909 * @brief Disable the SD I/O Suspend command sending. 910 * @param __INSTANCE__ : Pointer to SDMMC register base 911 * @retval None 912 */ 913 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 914 915 /** 916 * @} 917 */ 918 919 /** 920 * @} 921 */ 922 923 /* Exported functions --------------------------------------------------------*/ 924 /** @addtogroup SDMMC_LL_Exported_Functions 925 * @{ 926 */ 927 928 /* Initialization/de-initialization functions **********************************/ 929 /** @addtogroup HAL_SDMMC_LL_Group1 930 * @{ 931 */ 932 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 933 /** 934 * @} 935 */ 936 937 /* I/O operation functions *****************************************************/ 938 /** @addtogroup HAL_SDMMC_LL_Group2 939 * @{ 940 */ 941 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 942 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 943 /** 944 * @} 945 */ 946 947 /* Peripheral Control functions ************************************************/ 948 /** @addtogroup HAL_SDMMC_LL_Group3 949 * @{ 950 */ 951 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 952 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 953 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 954 955 /* Command path state machine (CPSM) management functions */ 956 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 957 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 958 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 959 960 /* Data path state machine (DPSM) management functions */ 961 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); 962 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 963 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 964 965 /* SDMMC Cards mode management functions */ 966 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 967 968 /* SDMMC Commands management functions */ 969 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 970 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 971 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 972 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 973 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 974 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 975 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 976 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 977 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 978 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx); 979 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 980 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); 981 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 982 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 983 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 984 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 985 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 986 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 987 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 988 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 989 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 990 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 991 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 992 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 993 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 994 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 995 996 /** 997 * @} 998 */ 999 1000 /** 1001 * @} 1002 */ 1003 1004 /** 1005 * @} 1006 */ 1007 1008 /** 1009 * @} 1010 */ 1011 1012 #endif /* SDMMC1 */ 1013 1014 #ifdef __cplusplus 1015 } 1016 #endif 1017 1018 #endif /* STM32F7xx_LL_SDMMC_H */ 1019 1020 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1021
