1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F7xx_HAL_RCC_H 20 #define __STM32F7xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f7xx_hal_def.h" 28 29 /* Include RCC HAL Extended module */ 30 /* (include on top of file since RCC structures are defined in extended file) */ 31 #include "stm32f7xx_hal_rcc_ex.h" 32 33 /** @addtogroup STM32F7xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup RCC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 43 /** @defgroup RCC_Exported_Types RCC Exported Types 44 * @{ 45 */ 46 47 /** 48 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 49 */ 50 typedef struct 51 { 52 uint32_t OscillatorType; /*!< The oscillators to be configured. 53 This parameter can be a value of @ref RCC_Oscillator_Type */ 54 55 uint32_t HSEState; /*!< The new state of the HSE. 56 This parameter can be a value of @ref RCC_HSE_Config */ 57 58 uint32_t LSEState; /*!< The new state of the LSE. 59 This parameter can be a value of @ref RCC_LSE_Config */ 60 61 uint32_t HSIState; /*!< The new state of the HSI. 62 This parameter can be a value of @ref RCC_HSI_Config */ 63 64 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 65 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 66 67 uint32_t LSIState; /*!< The new state of the LSI. 68 This parameter can be a value of @ref RCC_LSI_Config */ 69 70 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 71 72 }RCC_OscInitTypeDef; 73 74 /** 75 * @brief RCC System, AHB and APB buses clock configuration structure definition 76 */ 77 typedef struct 78 { 79 uint32_t ClockType; /*!< The clock to be configured. 80 This parameter can be a value of @ref RCC_System_Clock_Type */ 81 82 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 83 This parameter can be a value of @ref RCC_System_Clock_Source */ 84 85 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 86 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 87 88 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 89 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 90 91 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 92 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 93 94 }RCC_ClkInitTypeDef; 95 96 /** 97 * @} 98 */ 99 100 /* Exported constants --------------------------------------------------------*/ 101 /** @defgroup RCC_Exported_Constants RCC Exported Constants 102 * @{ 103 */ 104 105 /** @defgroup RCC_Oscillator_Type Oscillator Type 106 * @{ 107 */ 108 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) 109 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) 110 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) 111 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) 112 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) 113 /** 114 * @} 115 */ 116 117 /** @defgroup RCC_HSE_Config RCC HSE Config 118 * @{ 119 */ 120 #define RCC_HSE_OFF ((uint32_t)0x00000000U) 121 #define RCC_HSE_ON RCC_CR_HSEON 122 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) 123 /** 124 * @} 125 */ 126 127 /** @defgroup RCC_LSE_Config RCC LSE Config 128 * @{ 129 */ 130 #define RCC_LSE_OFF ((uint32_t)0x00000000U) 131 #define RCC_LSE_ON RCC_BDCR_LSEON 132 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) 133 /** 134 * @} 135 */ 136 137 /** @defgroup RCC_HSI_Config RCC HSI Config 138 * @{ 139 */ 140 #define RCC_HSI_OFF ((uint32_t)0x00000000U) 141 #define RCC_HSI_ON RCC_CR_HSION 142 143 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ 144 /** 145 * @} 146 */ 147 148 /** @defgroup RCC_LSI_Config RCC LSI Config 149 * @{ 150 */ 151 #define RCC_LSI_OFF ((uint32_t)0x00000000U) 152 #define RCC_LSI_ON RCC_CSR_LSION 153 /** 154 * @} 155 */ 156 157 /** @defgroup RCC_PLL_Config RCC PLL Config 158 * @{ 159 */ 160 #define RCC_PLL_NONE ((uint32_t)0x00000000U) 161 #define RCC_PLL_OFF ((uint32_t)0x00000001U) 162 #define RCC_PLL_ON ((uint32_t)0x00000002U) 163 /** 164 * @} 165 */ 166 167 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 168 * @{ 169 */ 170 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) 171 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) 172 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) 173 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) 174 /** 175 * @} 176 */ 177 178 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 179 * @{ 180 */ 181 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI 182 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE 183 /** 184 * @} 185 */ 186 187 /** @defgroup RCC_System_Clock_Type RCC System Clock Type 188 * @{ 189 */ 190 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) 191 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) 192 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) 193 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) 194 /** 195 * @} 196 */ 197 198 /** @defgroup RCC_System_Clock_Source RCC System Clock Source 199 * @{ 200 */ 201 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI 202 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE 203 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL 204 /** 205 * @} 206 */ 207 208 209 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 210 * @{ 211 */ 212 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 213 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 214 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source 220 * @{ 221 */ 222 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 223 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 224 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 225 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 226 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 227 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 228 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 229 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 230 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 231 /** 232 * @} 233 */ 234 235 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source 236 * @{ 237 */ 238 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 239 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 240 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 241 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 242 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 243 /** 244 * @} 245 */ 246 247 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source 248 * @{ 249 */ 250 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) 251 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) 252 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) 253 #define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U) 254 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) 255 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) 256 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) 257 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) 258 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) 259 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) 260 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) 261 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) 262 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) 263 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) 264 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) 265 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) 266 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) 267 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) 268 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) 269 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) 270 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) 271 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) 272 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) 273 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) 274 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) 275 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) 276 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) 277 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) 278 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) 279 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) 280 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) 281 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) 282 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) 283 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) 284 /** 285 * @} 286 */ 287 288 289 290 /** @defgroup RCC_MCO_Index RCC MCO Index 291 * @{ 292 */ 293 #define RCC_MCO1 ((uint32_t)0x00000000U) 294 #define RCC_MCO2 ((uint32_t)0x00000001U) 295 /** 296 * @} 297 */ 298 299 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source 300 * @{ 301 */ 302 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) 303 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 304 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 305 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 306 /** 307 * @} 308 */ 309 310 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source 311 * @{ 312 */ 313 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) 314 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 315 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 316 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 317 /** 318 * @} 319 */ 320 321 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler 322 * @{ 323 */ 324 #define RCC_MCODIV_1 ((uint32_t)0x00000000U) 325 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 326 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) 327 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 328 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE 329 /** 330 * @} 331 */ 332 333 /** @defgroup RCC_Interrupt RCC Interrupt 334 * @{ 335 */ 336 #define RCC_IT_LSIRDY ((uint8_t)0x01U) 337 #define RCC_IT_LSERDY ((uint8_t)0x02U) 338 #define RCC_IT_HSIRDY ((uint8_t)0x04U) 339 #define RCC_IT_HSERDY ((uint8_t)0x08U) 340 #define RCC_IT_PLLRDY ((uint8_t)0x10U) 341 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) 342 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) 343 #define RCC_IT_CSS ((uint8_t)0x80U) 344 /** 345 * @} 346 */ 347 348 /** @defgroup RCC_Flag RCC Flags 349 * Elements values convention: 0XXYYYYYb 350 * - YYYYY : Flag position in the register 351 * - 0XX : Register index 352 * - 01: CR register 353 * - 10: BDCR register 354 * - 11: CSR register 355 * @{ 356 */ 357 /* Flags in the CR register */ 358 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U) 359 #define RCC_FLAG_HSERDY ((uint8_t)0x31U) 360 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U) 361 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) 362 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) 363 364 /* Flags in the BDCR register */ 365 #define RCC_FLAG_LSERDY ((uint8_t)0x41U) 366 367 /* Flags in the CSR register */ 368 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U) 369 #define RCC_FLAG_BORRST ((uint8_t)0x79U) 370 #define RCC_FLAG_PINRST ((uint8_t)0x7AU) 371 #define RCC_FLAG_PORRST ((uint8_t)0x7BU) 372 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU) 373 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) 374 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) 375 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) 376 /** 377 * @} 378 */ 379 380 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations 381 * @{ 382 */ 383 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) 384 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 385 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 386 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV 387 /** 388 * @} 389 */ 390 391 /** 392 * @} 393 */ 394 395 /* Exported macro ------------------------------------------------------------*/ 396 /** @defgroup RCC_Exported_Macros RCC Exported Macros 397 * @{ 398 */ 399 400 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 401 * @brief Enable or disable the AHB1 peripheral clock. 402 * @note After reset, the peripheral clock (used for registers read/write access) 403 * is disabled and the application software has to enable this clock before 404 * using it. 405 * @{ 406 */ 407 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 408 __IO uint32_t tmpreg; \ 409 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 410 /* Delay after an RCC peripheral clock enabling */ \ 411 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 412 UNUSED(tmpreg); \ 413 } while(0) 414 415 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 416 __IO uint32_t tmpreg; \ 417 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 418 /* Delay after an RCC peripheral clock enabling */ \ 419 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 420 UNUSED(tmpreg); \ 421 } while(0) 422 423 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 424 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) 425 426 /** 427 * @} 428 */ 429 430 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 431 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 432 * @note After reset, the peripheral clock (used for registers read/write access) 433 * is disabled and the application software has to enable this clock before 434 * using it. 435 * @{ 436 */ 437 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 438 __IO uint32_t tmpreg; \ 439 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 440 /* Delay after an RCC peripheral clock enabling */ \ 441 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 442 UNUSED(tmpreg); \ 443 } while(0) 444 445 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 446 __IO uint32_t tmpreg; \ 447 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 448 /* Delay after an RCC peripheral clock enabling */ \ 449 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 450 UNUSED(tmpreg); \ 451 } while(0) 452 453 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 454 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 460 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 461 * @note After reset, the peripheral clock (used for registers read/write access) 462 * is disabled and the application software has to enable this clock before 463 * using it. 464 * @{ 465 */ 466 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 467 __IO uint32_t tmpreg; \ 468 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 469 /* Delay after an RCC peripheral clock enabling */ \ 470 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 471 UNUSED(tmpreg); \ 472 } while(0) 473 474 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) 475 476 /** 477 * @} 478 */ 479 480 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 481 * @brief Get the enable or disable status of the AHB1 peripheral clock. 482 * @note After reset, the peripheral clock (used for registers read/write access) 483 * is disabled and the application software has to enable this clock before 484 * using it. 485 * @{ 486 */ 487 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 488 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) 489 490 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 491 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) 492 /** 493 * @} 494 */ 495 496 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 497 * @brief Get the enable or disable status of the APB1 peripheral clock. 498 * @note After reset, the peripheral clock (used for registers read/write access) 499 * is disabled and the application software has to enable this clock before 500 * using it. 501 * @{ 502 */ 503 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 504 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 505 506 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 507 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 508 /** 509 * @} 510 */ 511 512 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 513 * @brief EGet the enable or disable status of the APB2 peripheral clock. 514 * @note After reset, the peripheral clock (used for registers read/write access) 515 * is disabled and the application software has to enable this clock before 516 * using it. 517 * @{ 518 */ 519 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) 520 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) 521 /** 522 * @} 523 */ 524 525 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release 526 * @brief Force or release AHB peripheral reset. 527 * @{ 528 */ 529 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 530 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 531 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) 532 533 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 534 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 535 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) 536 /** 537 * @} 538 */ 539 540 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 541 * @brief Force or release APB1 peripheral reset. 542 * @{ 543 */ 544 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 545 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 546 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 547 548 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 549 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 550 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 551 /** 552 * @} 553 */ 554 555 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 556 * @brief Force or release APB2 peripheral reset. 557 * @{ 558 */ 559 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 560 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) 561 562 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 563 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) 564 565 /** 566 * @} 567 */ 568 569 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable 570 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 571 * power consumption. 572 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 573 * @note By default, all peripheral clocks are enabled during SLEEP mode. 574 * @{ 575 */ 576 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 577 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 578 579 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 580 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) 581 582 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 583 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 584 * power consumption. 585 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 586 * @note By default, all peripheral clocks are enabled during SLEEP mode. 587 */ 588 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) 589 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) 590 591 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) 592 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) 593 594 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 595 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 596 * power consumption. 597 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 598 * @note By default, all peripheral clocks are enabled during SLEEP mode. 599 */ 600 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) 601 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) 602 603 /** 604 * @} 605 */ 606 607 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status 608 * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. 609 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 610 * power consumption. 611 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 612 * @note By default, all peripheral clocks are enabled during SLEEP mode. 613 * @{ 614 */ 615 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) 616 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) 617 618 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) 619 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) 620 /** 621 * @} 622 */ 623 624 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status 625 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. 626 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 627 * power consumption. 628 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 629 * @note By default, all peripheral clocks are enabled during SLEEP mode. 630 * @{ 631 */ 632 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) 633 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) 634 635 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) 636 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) 637 /** 638 * @} 639 */ 640 641 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status 642 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. 643 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 644 * power consumption. 645 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 646 * @note By default, all peripheral clocks are enabled during SLEEP mode. 647 * @{ 648 */ 649 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) 650 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) 651 /** 652 * @} 653 */ 654 655 /** @defgroup RCC_HSI_Configuration HSI Configuration 656 * @{ 657 */ 658 659 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 660 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 661 * It is used (enabled by hardware) as system clock source after startup 662 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 663 * of the HSE used directly or indirectly as system clock (if the Clock 664 * Security System CSS is enabled). 665 * @note HSI can not be stopped if it is used as system clock source. In this case, 666 * you have to select another source of the system clock then stop the HSI. 667 * @note After enabling the HSI, the application software should wait on HSIRDY 668 * flag to be set indicating that HSI clock is stable and can be used as 669 * system clock source. 670 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 671 * clock cycles. 672 */ 673 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) 674 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) 675 676 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 677 * @note The calibration is used to compensate for the variations in voltage 678 * and temperature that influence the frequency of the internal HSI RC. 679 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value. 680 * (default is RCC_HSICALIBRATION_DEFAULT). 681 */ 682 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ 683 RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos)) 684 /** 685 * @} 686 */ 687 688 /** @defgroup RCC_LSI_Configuration LSI Configuration 689 * @{ 690 */ 691 692 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 693 * @note After enabling the LSI, the application software should wait on 694 * LSIRDY flag to be set indicating that LSI clock is stable and can 695 * be used to clock the IWDG and/or the RTC. 696 * @note LSI can not be disabled if the IWDG is running. 697 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 698 * clock cycles. 699 */ 700 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) 701 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) 702 /** 703 * @} 704 */ 705 706 /** @defgroup RCC_HSE_Configuration HSE Configuration 707 * @{ 708 */ 709 /** 710 * @brief Macro to configure the External High Speed oscillator (HSE). 711 * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not 712 * supported by this macro. User should request a transition to HSE Off 713 * first and then HSE On or HSE Bypass. 714 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 715 * software should wait on HSERDY flag to be set indicating that HSE clock 716 * is stable and can be used to clock the PLL and/or system clock. 717 * @note HSE state can not be changed if it is used directly or through the 718 * PLL as system clock. In this case, you have to select another source 719 * of the system clock then change the HSE state (ex. disable it). 720 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 721 * @note This function reset the CSSON bit, so if the clock security system(CSS) 722 * was previously enabled you have to enable it again after calling this 723 * function. 724 * @param __STATE__ specifies the new state of the HSE. 725 * This parameter can be one of the following values: 726 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 727 * 6 HSE oscillator clock cycles. 728 * @arg RCC_HSE_ON: turn ON the HSE oscillator. 729 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. 730 */ 731 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 732 do { \ 733 if ((__STATE__) == RCC_HSE_ON) \ 734 { \ 735 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 736 } \ 737 else if ((__STATE__) == RCC_HSE_OFF) \ 738 { \ 739 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 740 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 741 } \ 742 else if ((__STATE__) == RCC_HSE_BYPASS) \ 743 { \ 744 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 745 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 746 } \ 747 else \ 748 { \ 749 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 750 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 751 } \ 752 } while(0) 753 /** 754 * @} 755 */ 756 757 /** @defgroup RCC_LSE_Configuration LSE Configuration 758 * @{ 759 */ 760 761 /** 762 * @brief Macro to configure the External Low Speed oscillator (LSE). 763 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 764 * User should request a transition to LSE Off first and then LSE On or LSE Bypass. 765 * @note As the LSE is in the Backup domain and write access is denied to 766 * this domain after reset, you have to enable write access using 767 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 768 * (to be done once after reset). 769 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 770 * software should wait on LSERDY flag to be set indicating that LSE clock 771 * is stable and can be used to clock the RTC. 772 * @param __STATE__ specifies the new state of the LSE. 773 * This parameter can be one of the following values: 774 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 775 * 6 LSE oscillator clock cycles. 776 * @arg RCC_LSE_ON: turn ON the LSE oscillator. 777 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. 778 */ 779 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 780 do { \ 781 if((__STATE__) == RCC_LSE_ON) \ 782 { \ 783 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 784 } \ 785 else if((__STATE__) == RCC_LSE_OFF) \ 786 { \ 787 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 788 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 789 } \ 790 else if((__STATE__) == RCC_LSE_BYPASS) \ 791 { \ 792 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 793 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 794 } \ 795 else \ 796 { \ 797 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 798 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 799 } \ 800 } while(0) 801 /** 802 * @} 803 */ 804 805 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration 806 * @{ 807 */ 808 809 /** @brief Macros to enable or disable the RTC clock. 810 * @note These macros must be used only after the RTC clock source was selected. 811 */ 812 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) 813 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) 814 815 /** @brief Macros to configure the RTC clock (RTCCLK). 816 * @note As the RTC clock configuration bits are in the Backup domain and write 817 * access is denied to this domain after reset, you have to enable write 818 * access using the Power Backup Access macro before to configure 819 * the RTC clock source (to be done once after reset). 820 * @note Once the RTC clock is configured it can't be changed unless the 821 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 822 * a Power On Reset (POR). 823 * @param __RTCCLKSource__ specifies the RTC clock source. 824 * This parameter can be one of the following values: 825 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. 826 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 827 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 828 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected 829 * as RTC clock, where x:[2,31] 830 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 831 * work in STOP and STANDBY modes, and can be used as wakeup source. 832 * However, when the HSE clock is used as RTC clock source, the RTC 833 * cannot be used in STOP and STANDBY modes. 834 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 835 * RTC clock source). 836 */ 837 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 838 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) 839 840 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 841 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ 842 } while (0) 843 844 /** @brief Macro to get the RTC clock source. 845 * @retval The clock source can be one of the following values: 846 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 847 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 848 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 849 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 850 */ 851 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 852 853 /** 854 * @brief Get the RTC and HSE clock divider (RTCPRE). 855 * @retval Returned value can be one of the following values: 856 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected 857 * as RTC clock, where x:[2,31] 858 */ 859 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) 860 861 /** @brief Macros to force or release the Backup domain reset. 862 * @note This function resets the RTC peripheral (including the backup registers) 863 * and the RTC clock source selection in RCC_CSR register. 864 * @note The BKPSRAM is not affected by this reset. 865 */ 866 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) 867 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) 868 /** 869 * @} 870 */ 871 872 /** @defgroup RCC_PLL_Configuration PLL Configuration 873 * @{ 874 */ 875 876 /** @brief Macros to enable or disable the main PLL. 877 * @note After enabling the main PLL, the application software should wait on 878 * PLLRDY flag to be set indicating that PLL clock is stable and can 879 * be used as system clock source. 880 * @note The main PLL can not be disabled if it is used as system clock source 881 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 882 */ 883 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 884 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 885 886 /** @brief Macro to configure the PLL clock source. 887 * @note This function must be used only when the main PLL is disabled. 888 * @param __PLLSOURCE__ specifies the PLL entry clock source. 889 * This parameter can be one of the following values: 890 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 891 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 892 * 893 */ 894 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 895 896 /** @brief Macro to configure the PLL multiplication factor. 897 * @note This function must be used only when the main PLL is disabled. 898 * @param __PLLM__ specifies the division factor for PLL VCO input clock 899 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 900 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 901 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 902 * of 2 MHz to limit PLL jitter. 903 * 904 */ 905 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 906 /** 907 * @} 908 */ 909 910 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration 911 * @{ 912 */ 913 914 /** @brief Macro to configure the I2S clock source (I2SCLK). 915 * @note This function must be called before enabling the I2S APB clock. 916 * @param __SOURCE__ specifies the I2S clock source. 917 * This parameter can be one of the following values: 918 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 919 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 920 * used as I2S clock source. 921 */ 922 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ 923 RCC->CFGR |= (__SOURCE__); \ 924 }while(0) 925 926 /** @brief Macros to enable or disable the PLLI2S. 927 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 928 */ 929 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) 930 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) 931 /** 932 * @} 933 */ 934 935 /** @defgroup RCC_Get_Clock_source Get Clock source 936 * @{ 937 */ 938 /** 939 * @brief Macro to configure the system clock source. 940 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. 941 * This parameter can be one of the following values: 942 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 943 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 944 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 945 */ 946 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) 947 948 /** @brief Macro to get the clock source used as system clock. 949 * @retval The clock source used as system clock. The returned value can be one 950 * of the following: 951 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 952 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 953 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 954 */ 955 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) 956 957 /** 958 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. 959 * @note As the LSE is in the Backup domain and write access is denied to 960 * this domain after reset, you have to enable write access using 961 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 962 * (to be done once after reset). 963 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. 964 * This parameter can be one of the following values: 965 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. 966 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. 967 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. 968 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. 969 * @retval None 970 */ 971 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ 972 (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) 973 974 /** @brief Macro to get the oscillator used as PLL clock source. 975 * @retval The oscillator used as PLL clock source. The returned value can be one 976 * of the following: 977 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 978 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 979 */ 980 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 981 /** 982 * @} 983 */ 984 985 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 986 * @{ 987 */ 988 989 /** @brief Macro to configure the MCO1 clock. 990 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 991 * This parameter can be one of the following values: 992 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 993 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 994 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 995 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source 996 * @param __MCODIV__ specifies the MCO clock prescaler. 997 * This parameter can be one of the following values: 998 * @arg RCC_MCODIV_1: no division applied to MCOx clock 999 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 1000 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 1001 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 1002 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 1003 */ 1004 1005 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1006 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1007 1008 /** @brief Macro to configure the MCO2 clock. 1009 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1010 * This parameter can be one of the following values: 1011 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 1012 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source 1013 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 1014 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source 1015 * @param __MCODIV__ specifies the MCO clock prescaler. 1016 * This parameter can be one of the following values: 1017 * @arg RCC_MCODIV_1: no division applied to MCOx clock 1018 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 1019 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 1020 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 1021 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 1022 */ 1023 1024 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1025 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); 1026 /** 1027 * @} 1028 */ 1029 1030 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1031 * @brief macros to manage the specified RCC Flags and interrupts. 1032 * @{ 1033 */ 1034 1035 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 1036 * the selected interrupts). 1037 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1038 * This parameter can be any combination of the following values: 1039 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1040 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1041 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1042 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1043 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1044 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1045 */ 1046 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 1047 1048 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 1049 * the selected interrupts). 1050 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1051 * This parameter can be any combination of the following values: 1052 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1053 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1054 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1055 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1056 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1057 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1058 */ 1059 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 1060 1061 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 1062 * bits to clear the selected interrupt pending bits. 1063 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1064 * This parameter can be any combination of the following values: 1065 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1066 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1067 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1068 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1069 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1070 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1071 * @arg RCC_IT_CSS: Clock Security System interrupt 1072 */ 1073 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 1074 1075 /** @brief Check the RCC's interrupt has occurred or not. 1076 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1077 * This parameter can be one of the following values: 1078 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1079 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1080 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1081 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1082 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1083 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1084 * @arg RCC_IT_CSS: Clock Security System interrupt 1085 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1086 */ 1087 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 1088 1089 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, 1090 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 1091 */ 1092 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 1093 1094 /** @brief Check RCC flag is set or not. 1095 * @param __FLAG__ specifies the flag to check. 1096 * This parameter can be one of the following values: 1097 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. 1098 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. 1099 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. 1100 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. 1101 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. 1102 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. 1103 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. 1104 * @arg RCC_FLAG_PINRST: Pin reset. 1105 * @arg RCC_FLAG_PORRST: POR/PDR reset. 1106 * @arg RCC_FLAG_SFTRST: Software reset. 1107 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. 1108 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. 1109 * @arg RCC_FLAG_LPWRRST: Low Power reset. 1110 * @retval The new state of __FLAG__ (TRUE or FALSE). 1111 */ 1112 #define RCC_FLAG_MASK ((uint8_t)0x1F) 1113 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) 1114 1115 /** 1116 * @} 1117 */ 1118 1119 /** 1120 * @} 1121 */ 1122 1123 /* Include RCC HAL Extension module */ 1124 #include "stm32f7xx_hal_rcc_ex.h" 1125 1126 /* Exported functions --------------------------------------------------------*/ 1127 /** @addtogroup RCC_Exported_Functions 1128 * @{ 1129 */ 1130 1131 /** @addtogroup RCC_Exported_Functions_Group1 1132 * @{ 1133 */ 1134 /* Initialization and de-initialization functions ******************************/ 1135 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1136 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1137 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1138 /** 1139 * @} 1140 */ 1141 1142 /** @addtogroup RCC_Exported_Functions_Group2 1143 * @{ 1144 */ 1145 /* Peripheral Control functions ************************************************/ 1146 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1147 void HAL_RCC_EnableCSS(void); 1148 void HAL_RCC_DisableCSS(void); 1149 uint32_t HAL_RCC_GetSysClockFreq(void); 1150 uint32_t HAL_RCC_GetHCLKFreq(void); 1151 uint32_t HAL_RCC_GetPCLK1Freq(void); 1152 uint32_t HAL_RCC_GetPCLK2Freq(void); 1153 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1154 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1155 1156 /* CSS NMI IRQ handler */ 1157 void HAL_RCC_NMI_IRQHandler(void); 1158 1159 /* User Callbacks in non blocking mode (IT mode) */ 1160 void HAL_RCC_CSSCallback(void); 1161 /** 1162 * @} 1163 */ 1164 1165 /** 1166 * @} 1167 */ 1168 1169 /* Private types -------------------------------------------------------------*/ 1170 /* Private variables ---------------------------------------------------------*/ 1171 /* Private constants ---------------------------------------------------------*/ 1172 /** @defgroup RCC_Private_Constants RCC Private Constants 1173 * @{ 1174 */ 1175 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 1176 #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ 1177 #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ 1178 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ 1179 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ 1180 #define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ 1181 #define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ 1182 1183 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias 1184 * @brief RCC registers bit address alias 1185 * @{ 1186 */ 1187 /* CIR register byte 2 (Bits[15:8]) base address */ 1188 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) 1189 1190 /* CIR register byte 3 (Bits[23:16]) base address */ 1191 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) 1192 1193 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) 1194 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 1195 /** 1196 * @} 1197 */ 1198 /** 1199 * @} 1200 */ 1201 1202 /* Private macros ------------------------------------------------------------*/ 1203 /** @addtogroup RCC_Private_Macros RCC Private Macros 1204 * @{ 1205 */ 1206 1207 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters 1208 * @{ 1209 */ 1210 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) 1211 1212 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 1213 ((HSE) == RCC_HSE_BYPASS)) 1214 1215 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 1216 ((LSE) == RCC_LSE_BYPASS)) 1217 1218 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) 1219 1220 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 1221 1222 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) 1223 1224 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ 1225 ((SOURCE) == RCC_PLLSOURCE_HSE)) 1226 1227 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ 1228 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ 1229 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) 1230 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) 1231 1232 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 1233 1234 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ 1235 ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) 1236 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 1237 1238 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ 1239 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ 1240 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ 1241 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ 1242 ((HCLK) == RCC_SYSCLK_DIV512)) 1243 1244 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) 1245 1246 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ 1247 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ 1248 ((PCLK) == RCC_HCLK_DIV16)) 1249 1250 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) 1251 1252 1253 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 1254 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) 1255 1256 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ 1257 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 1258 1259 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 1260 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 1261 ((DIV) == RCC_MCODIV_5)) 1262 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 1263 1264 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ 1265 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 1266 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 1267 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 1268 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 1269 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 1270 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 1271 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 1272 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 1273 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 1274 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 1275 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 1276 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 1277 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 1278 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 1279 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) 1280 1281 1282 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ 1283 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ 1284 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 1285 ((DRIVE) == RCC_LSEDRIVE_HIGH)) 1286 /** 1287 * @} 1288 */ 1289 1290 /** 1291 * @} 1292 */ 1293 1294 /** 1295 * @} 1296 */ 1297 1298 /** 1299 * @} 1300 */ 1301 1302 #ifdef __cplusplus 1303 } 1304 #endif 1305 1306 #endif /* __STM32F7xx_HAL_RCC_H */ 1307 1308
