1 /**
2   ******************************************************************************
3   * @file    stm32f7xx_hal_adc.h
4   * @author  MCD Application Team
5   * @brief   Header file of ADC HAL extension module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2017 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F7xx_ADC_H
21 #define STM32F7xx_ADC_H
22 
23 #ifdef __cplusplus
24  extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f7xx_hal_def.h"
29 
30 /** @addtogroup STM32F7xx_HAL_Driver
31   * @{
32   */
33 
34 /** @addtogroup ADC
35   * @{
36   */
37 
38 /* Exported types ------------------------------------------------------------*/
39 /** @defgroup ADC_Exported_Types ADC Exported Types
40   * @{
41   */
42 
43 /**
44   * @brief  Structure definition of ADC and regular group initialization
45   * @note   Parameters of this structure are shared within 2 scopes:
46   *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
47   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
48   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
49   *         ADC state can be either:
50   *          - For all parameters: ADC disabled
51   *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
52   *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
53   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
54   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
55   */
56 typedef struct
57 {
58   uint32_t ClockPrescaler;               /*!< Select ADC clock prescaler. The clock is common for
59                                               all the ADCs.
60                                               This parameter can be a value of @ref ADC_ClockPrescaler */
61   uint32_t Resolution;                   /*!< Configures the ADC resolution.
62                                               This parameter can be a value of @ref ADC_Resolution */
63   uint32_t DataAlign;                    /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
64                                               or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
65                                               This parameter can be a value of @ref ADC_Data_Align */
66   uint32_t ScanConvMode;                 /*!< Configures the sequencer of regular and injected groups.
67                                               This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
68                                               If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
69                                                            Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
70                                               If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
71                                                            Scan direction is upward: from rank1 to rank 'n'.
72                                               This parameter can be a value of @ref ADC_Scan_mode.
73                                               This parameter can be set to ENABLE or DISABLE */
74   uint32_t EOCSelection;                 /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
75                                               This parameter can be a value of @ref ADC_EOCSelection.
76                                               Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
77                                                     Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
78                                                     or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
79                                               Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
80                                               If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
81   uint32_t ContinuousConvMode;           /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
82                                               after the selected trigger occurred (software start or external trigger).
83                                               This parameter can be set to ENABLE or DISABLE. */
84   uint32_t NbrOfConversion;              /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
85                                               To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
86                                               This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
87   FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
88                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
89                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
90                                               This parameter can be set to ENABLE or DISABLE. */
91   uint32_t NbrOfDiscConversion;          /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
92                                               If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
93                                               This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
94   uint32_t ExternalTrigConv;             /*!< Selects the external event used to trigger the conversion start of regular group.
95                                               If set to ADC_SOFTWARE_START, external triggers are disabled.
96                                               If set to external trigger source, triggering is on event rising edge by default.
97                                               This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
98   uint32_t ExternalTrigConvEdge;         /*!< Selects the external trigger edge of regular group.
99                                               If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
100                                               This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
101   FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
102                                               or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
103                                               Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
104                                               Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
105                                               This parameter can be set to ENABLE or DISABLE. */
106 }ADC_InitTypeDef;
107 
108 
109 
110 /**
111   * @brief  Structure definition of ADC channel for regular group
112   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
113   *         ADC can be either disabled or enabled without conversion on going on regular group.
114   */
115 typedef struct
116 {
117   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
118                                         This parameter can be a value of @ref ADC_channels */
119   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
120                                         This parameter must be a number between Min_Data = 1 and Max_Data = 16
121                                         This parameter can be a value of @ref ADC_regular_rank */
122   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
123                                         Unit: ADC clock cycles
124                                         Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
125                                         This parameter can be a value of @ref ADC_sampling_times
126                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
127                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
128                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
129                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
130                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
131   uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */
132 }ADC_ChannelConfTypeDef;
133 
134 /**
135   * @brief ADC Configuration multi-mode structure definition
136   */
137 typedef struct
138 {
139   uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
140                                    This parameter can be a value of @ref ADC_analog_watchdog_selection */
141   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
142                                    This parameter must be a 12-bit value. */
143   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
144                                    This parameter must be a 12-bit value. */
145   uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog.
146                                    This parameter has an effect only if watchdog mode is configured on single channel
147                                    This parameter can be a value of @ref ADC_channels */
148   FunctionalState ITMode;     /*!< Specifies whether the analog watchdog is configured
149                                    is interrupt mode or in polling mode.
150                                    This parameter can be set to ENABLE or DISABLE */
151   uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
152 }ADC_AnalogWDGConfTypeDef;
153 
154 /**
155   * @brief  HAL ADC state machine: ADC states definition (bitfields)
156   */
157 /* States of ADC global scope */
158 #define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000U)    /*!< ADC not yet initialized or disabled */
159 #define HAL_ADC_STATE_READY             ((uint32_t)0x00000001U)    /*!< ADC peripheral ready for use */
160 #define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
161 #define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004U)    /*!< TimeOut occurrence */
162 
163 /* States of ADC errors */
164 #define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010U)    /*!< Internal error occurrence */
165 #define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020U)    /*!< Configuration error occurrence */
166 #define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040U)    /*!< DMA error occurrence */
167 
168 /* States of ADC group regular */
169 #define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
170                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
171 #define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200U)    /*!< Conversion data available on group regular */
172 #define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400U)    /*!< Overrun occurrence */
173 
174 /* States of ADC group injected */
175 #define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
176                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
177 #define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000U)    /*!< Conversion data available on group injected */
178 
179 /* States of ADC analog watchdogs */
180 #define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
181 #define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
182 #define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
183 
184 /* States of ADC multi-mode */
185 #define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000U)    /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
186 
187 
188 /**
189   * @brief  ADC handle Structure definition
190   */
191 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
192 typedef struct __ADC_HandleTypeDef
193 #else
194 typedef struct
195 #endif
196 {
197   ADC_TypeDef                   *Instance;                   /*!< Register base address */
198 
199   ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
200 
201   __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
202 
203   DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
204 
205   HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
206 
207   __IO uint32_t                 State;                       /*!< ADC communication state */
208 
209   __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
210 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
211   void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
212   void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
213   void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
214   void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
215   void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */
216   void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
217   void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
218 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
219 }ADC_HandleTypeDef;
220 
221 
222 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
223 /**
224   * @brief  HAL ADC Callback ID enumeration definition
225   */
226 typedef enum
227 {
228   HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
229   HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
230   HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
231   HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
232   HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
233   HAL_ADC_MSPINIT_CB_ID                 = 0x05U,  /*!< ADC Msp Init callback ID          */
234   HAL_ADC_MSPDEINIT_CB_ID               = 0x06U   /*!< ADC Msp DeInit callback ID        */
235 } HAL_ADC_CallbackIDTypeDef;
236 
237 /**
238   * @brief  HAL ADC Callback pointer definition
239   */
240 typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
241 
242 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
243 
244 /**
245   * @}
246   */
247 
248 /* Exported constants --------------------------------------------------------*/
249 /** @defgroup ADC_Exported_Constants ADC Exported Constants
250   * @{
251   */
252 
253 /** @defgroup ADC_Error_Code ADC Error Code
254   * @{
255   */
256 #define HAL_ADC_ERROR_NONE        ((uint32_t)0x00U)   /*!< No error                                              */
257 #define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01U)   /*!< ADC IP internal error: if problem of clocking,
258                                                           enable/disable, erroneous state                       */
259 #define HAL_ADC_ERROR_OVR         ((uint32_t)0x02U)   /*!< Overrun error                                         */
260 #define HAL_ADC_ERROR_DMA         ((uint32_t)0x04U)   /*!< DMA transfer error                                    */
261 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
262 #define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
263 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
264 /**
265   * @}
266   */
267 
268 
269 /** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
270   * @{
271   */
272 #define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000U)
273 #define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
274 #define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
275 #define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
276 /**
277   * @}
278   */
279 
280 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
281   * @{
282   */
283 #define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000U)
284 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
285 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
286 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
287 #define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
288 #define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
289 #define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
290 #define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
291 #define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
292 #define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
293 #define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
294 #define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
295 #define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
296 #define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
297 #define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
298 #define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
299 /**
300   * @}
301   */
302 
303 /** @defgroup ADC_Resolution ADC Resolution
304   * @{
305   */
306 #define ADC_RESOLUTION_12B  ((uint32_t)0x00000000U)
307 #define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
308 #define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
309 #define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
310 /**
311   * @}
312   */
313 
314 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
315   * @{
316   */
317 #define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000U)
318 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
319 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
320 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
321 /**
322   * @}
323   */
324 
325 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
326   * @{
327   */
328 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
329 /*       compatibility with other STM32 devices.                              */
330 
331 
332 #define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000U)
333 #define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
334 #define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
335 #define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
336 #define ADC_EXTERNALTRIGCONV_T5_TRGO   ((uint32_t)ADC_CR2_EXTSEL_2)
337 #define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
338 #define ADC_EXTERNALTRIGCONV_T3_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
339 #define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
340 #define ADC_EXTERNALTRIGCONV_T8_TRGO2  ((uint32_t)ADC_CR2_EXTSEL_3)
341 #define ADC_EXTERNALTRIGCONV_T1_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
342 #define ADC_EXTERNALTRIGCONV_T1_TRGO2  ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
343 #define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
344 #define ADC_EXTERNALTRIGCONV_T4_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
345 #define ADC_EXTERNALTRIGCONV_T6_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
346 
347 #define ADC_EXTERNALTRIGCONV_EXT_IT11  ((uint32_t)ADC_CR2_EXTSEL)
348 #define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)
349 
350 /**
351   * @}
352   */
353 
354 /** @defgroup ADC_Data_Align ADC Data Align
355   * @{
356   */
357 #define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000U)
358 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
359 /**
360   * @}
361   */
362 
363 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
364   * @{
365   */
366 #define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)        /*!< Scan mode disabled */
367 #define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)        /*!< Scan mode enabled  */
368 /**
369   * @}
370   */
371 
372 /** @defgroup ADC_regular_rank ADC group regular sequencer rank
373   * @{
374   */
375 #define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)       /*!< ADC regular conversion rank 1  */
376 #define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)       /*!< ADC regular conversion rank 2  */
377 #define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)       /*!< ADC regular conversion rank 3  */
378 #define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)       /*!< ADC regular conversion rank 4  */
379 #define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)       /*!< ADC regular conversion rank 5  */
380 #define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)       /*!< ADC regular conversion rank 6  */
381 #define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)       /*!< ADC regular conversion rank 7  */
382 #define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)       /*!< ADC regular conversion rank 8  */
383 #define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)       /*!< ADC regular conversion rank 9  */
384 #define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)       /*!< ADC regular conversion rank 10 */
385 #define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)       /*!< ADC regular conversion rank 11 */
386 #define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)       /*!< ADC regular conversion rank 12 */
387 #define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)       /*!< ADC regular conversion rank 13 */
388 #define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)       /*!< ADC regular conversion rank 14 */
389 #define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)       /*!< ADC regular conversion rank 15 */
390 #define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)       /*!< ADC regular conversion rank 16 */
391 /**
392   * @}
393   */
394 
395 /** @defgroup ADC_channels ADC Common Channels
396   * @{
397   */
398 #define ADC_CHANNEL_0           ((uint32_t)0x00000000U)
399 #define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
400 #define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
401 #define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
402 #define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
403 #define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
404 #define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
405 #define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
406 #define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
407 #define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
408 #define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
409 #define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
410 #define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
411 #define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
412 #define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
413 #define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
414 #define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
415 #define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
416 #define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
417 
418 #define ADC_INTERNAL_NONE                  0x80000000U
419 #define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
420 #define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
421 #define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U))
422 /**
423   * @}
424   */
425 
426 /** @defgroup ADC_sampling_times ADC Sampling Times
427   * @{
428   */
429 #define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000U)
430 #define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
431 #define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
432 #define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
433 #define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
434 #define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
435 #define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
436 #define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
437 /**
438   * @}
439   */
440 
441   /** @defgroup ADC_EOCSelection ADC EOC Selection
442   * @{
443   */
444 #define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000U)
445 #define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001U)
446 #define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002U)  /*!< reserved for future use */
447 /**
448   * @}
449   */
450 
451 /** @defgroup ADC_Event_type ADC Event Type
452   * @{
453   */
454 #define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
455 #define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
456 /**
457   * @}
458   */
459 
460 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
461   * @{
462   */
463 #define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
464 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
465 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
466 #define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
467 #define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
468 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
469 #define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000U)
470 /**
471   * @}
472   */
473 
474 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
475   * @{
476   */
477 #define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)
478 #define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE)
479 #define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
480 #define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE)
481 /**
482   * @}
483   */
484 
485 /** @defgroup ADC_flags_definition ADC Flags Definition
486   * @{
487   */
488 #define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
489 #define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
490 #define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
491 #define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
492 #define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
493 #define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
494 /**
495   * @}
496   */
497 
498 /** @defgroup ADC_channels_type ADC Channels Type
499   * @{
500   */
501 #define ADC_ALL_CHANNELS      ((uint32_t)0x00000001U)
502 #define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002U) /*!< reserved for future use */
503 #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
504 /**
505   * @}
506   */
507 
508 /**
509   * @}
510   */
511 
512 /* Exported macro ------------------------------------------------------------*/
513 /** @defgroup ADC_Exported_Macros ADC Exported Macros
514   * @{
515   */
516 
517 /** @brief Reset ADC handle state
518   * @param  __HANDLE__ ADC handle
519   * @retval None
520   */
521 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
522 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
523   do{                                                                          \
524      (__HANDLE__)->State = HAL_ADC_STATE_RESET;                               \
525      (__HANDLE__)->MspInitCallback = NULL;                                     \
526      (__HANDLE__)->MspDeInitCallback = NULL;                                   \
527     } while(0)
528 #else
529 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
530   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
531 #endif
532 
533 /**
534   * @brief  Enable the ADC peripheral.
535   * @param  __HANDLE__ ADC handle
536   * @retval None
537   */
538 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
539 
540 /**
541   * @brief  Disable the ADC peripheral.
542   * @param  __HANDLE__ ADC handle
543   * @retval None
544   */
545 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
546 
547 /**
548   * @brief  Enable the ADC end of conversion interrupt.
549   * @param  __HANDLE__ specifies the ADC Handle.
550   * @param  __INTERRUPT__ ADC Interrupt.
551   * @retval None
552   */
553 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
554 
555 /**
556   * @brief  Disable the ADC end of conversion interrupt.
557   * @param  __HANDLE__ specifies the ADC Handle.
558   * @param  __INTERRUPT__ ADC interrupt.
559   * @retval None
560   */
561 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
562 
563 /** @brief  Check if the specified ADC interrupt source is enabled or disabled.
564   * @param  __HANDLE__ specifies the ADC Handle.
565   * @param  __INTERRUPT__ specifies the ADC interrupt source to check.
566   * @retval The new state of __IT__ (TRUE or FALSE).
567   */
568 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
569 
570 /**
571   * @brief  Clear the ADC's pending flags.
572   * @param  __HANDLE__ specifies the ADC Handle.
573   * @param  __FLAG__ ADC flag.
574   * @retval None
575   */
576 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
577 
578 /**
579   * @brief  Get the selected ADC's flag status.
580   * @param  __HANDLE__ specifies the ADC Handle.
581   * @param  __FLAG__ ADC flag.
582   * @retval None
583   */
584 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
585 
586 /**
587   * @}
588   */
589 
590 /* Include ADC HAL Extension module */
591 #include "stm32f7xx_hal_adc_ex.h"
592 
593 /* Exported functions --------------------------------------------------------*/
594 /** @addtogroup ADC_Exported_Functions
595   * @{
596   */
597 
598 /** @addtogroup ADC_Exported_Functions_Group1
599   * @{
600   */
601 /* Initialization/de-initialization functions ***********************************/
602 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
603 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
604 void       HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
605 void       HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
606 
607 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
608 /* Callbacks Register/UnRegister functions  ***********************************/
609 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
610 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
611 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
612 /**
613   * @}
614   */
615 
616 /** @addtogroup ADC_Exported_Functions_Group2
617   * @{
618   */
619 /* I/O operation functions ******************************************************/
620 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
621 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
622 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
623 
624 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
625 
626 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
627 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
628 
629 void              HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
630 
631 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
632 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
633 
634 uint32_t          HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
635 
636 void       HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
637 void       HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
638 void       HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
639 void       HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
640 /**
641   * @}
642   */
643 
644 /** @addtogroup ADC_Exported_Functions_Group3
645   * @{
646   */
647 /* Peripheral Control functions *************************************************/
648 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
649 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
650 /**
651   * @}
652   */
653 
654 /** @addtogroup ADC_Exported_Functions_Group4
655   * @{
656   */
657 /* Peripheral State functions ***************************************************/
658 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
659 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
660 /**
661   * @}
662   */
663 
664 /**
665   * @}
666   */
667 
668 /* Private types -------------------------------------------------------------*/
669 /* Private variables ---------------------------------------------------------*/
670 /* Private constants ---------------------------------------------------------*/
671 /** @defgroup ADC_Private_Constants ADC Private Constants
672   * @{
673   */
674 /* Delay for ADC stabilization time.                                        */
675 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
676 /* Unit: us                                                                 */
677 #define ADC_STAB_DELAY_US               ((uint32_t) 3U)
678 /* Delay for temperature sensor stabilization time.                         */
679 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
680 /* Unit: us                                                                 */
681 #define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10U)
682 /**
683   * @}
684   */
685 
686 /* Private macros ------------------------------------------------------------*/
687 /** @defgroup ADC_Private_Macros ADC Private Macros
688   * @{
689   */
690 /* Macro reserved for internal HAL driver usage, not intended to be used in
691    code of final user */
692 
693 /**
694   * @brief Verification of ADC state: enabled or disabled
695   * @param __HANDLE__ ADC handle
696   * @retval SET (ADC enabled) or RESET (ADC disabled)
697   */
698 #define ADC_IS_ENABLE(__HANDLE__)                                              \
699   ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
700   ) ? SET : RESET)
701 
702 /**
703   * @brief Test if conversion trigger of regular group is software start
704   *        or external trigger.
705   * @param __HANDLE__ ADC handle
706   * @retval SET (software start) or RESET (external trigger)
707   */
708 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
709   (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
710 
711 /**
712   * @brief Test if conversion trigger of injected group is software start
713   *        or external trigger.
714   * @param __HANDLE__ ADC handle
715   * @retval SET (software start) or RESET (external trigger)
716   */
717 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
718   (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
719 
720 /**
721   * @brief Simultaneously clears and sets specific bits of the handle State
722   * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
723   *        the first parameter is the ADC handle State, the second parameter is the
724   *        bit field to clear, the third and last parameter is the bit field to set.
725   * @retval None
726   */
727 #define ADC_STATE_CLR_SET MODIFY_REG
728 
729 /**
730   * @brief Clear ADC error code (set it to error code: "no error")
731   * @param __HANDLE__ ADC handle
732   * @retval None
733   */
734 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
735   ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
736 
737 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)          || \
738                                  ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
739                                  ((CHANNEL) == ADC_INTERNAL_NONE))
740 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)     (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
741                                                   ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
742                                                   ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
743                                                   ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
744 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
745                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
746                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
747                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
748                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
749                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
750                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
751                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
752                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
753                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
754                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
755                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
756                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
757                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
758                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
759                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
760 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
761                                            ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
762                                            ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
763                                            ((__RESOLUTION__) == ADC_RESOLUTION_6B))
764 #define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
765                                         ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
766                                         ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
767                                         ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
768 #define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \
769                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \
770                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \
771                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
772                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO)  || \
773                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
774                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
775                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \
776                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
777                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \
778                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
779                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
780                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
781                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
782                                       ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
783 																			((__REGTRIG__) == ADC_SOFTWARE_START))
784 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
785                                       ((__ALIGN__) == ADC_DATAALIGN_LEFT))
786 
787 
788 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES)   || \
789                                       ((__TIME__) == ADC_SAMPLETIME_15CYCLES)  || \
790                                       ((__TIME__) == ADC_SAMPLETIME_28CYCLES)  || \
791                                       ((__TIME__) == ADC_SAMPLETIME_56CYCLES)  || \
792                                       ((__TIME__) == ADC_SAMPLETIME_84CYCLES)  || \
793                                       ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
794                                       ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
795                                       ((__TIME__) == ADC_SAMPLETIME_480CYCLES))
796 #define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV)   || \
797                                                ((__EOCSelection__) == ADC_EOC_SEQ_CONV)  || \
798                                                ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
799 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
800                                       ((__EVENT__) == ADC_OVR_EVENT))
801 #define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
802                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
803                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
804                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
805                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
806                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
807                                               ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
808 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
809                                             ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
810                                             ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
811 
812 #define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
813                                        ((__RANK__) == ADC_REGULAR_RANK_2 ) || \
814                                        ((__RANK__) == ADC_REGULAR_RANK_3 ) || \
815                                        ((__RANK__) == ADC_REGULAR_RANK_4 ) || \
816                                        ((__RANK__) == ADC_REGULAR_RANK_5 ) || \
817                                        ((__RANK__) == ADC_REGULAR_RANK_6 ) || \
818                                        ((__RANK__) == ADC_REGULAR_RANK_7 ) || \
819                                        ((__RANK__) == ADC_REGULAR_RANK_8 ) || \
820                                        ((__RANK__) == ADC_REGULAR_RANK_9 ) || \
821                                        ((__RANK__) == ADC_REGULAR_RANK_10) || \
822                                        ((__RANK__) == ADC_REGULAR_RANK_11) || \
823                                        ((__RANK__) == ADC_REGULAR_RANK_12) || \
824                                        ((__RANK__) == ADC_REGULAR_RANK_13) || \
825                                        ((__RANK__) == ADC_REGULAR_RANK_14) || \
826                                        ((__RANK__) == ADC_REGULAR_RANK_15) || \
827                                        ((__RANK__) == ADC_REGULAR_RANK_16))
828 
829 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
830                                          ((__SCAN_MODE__) == ADC_SCAN_ENABLE))
831 
832 #define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
833 #define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
834 #define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
835 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                     \
836    ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
837     (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
838     (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
839     (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
840 
841 /**
842   * @brief  Set ADC Regular channel sequence length.
843   * @param  _NbrOfConversion_ Regular channel sequence length.
844   * @retval None
845   */
846 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
847 
848 /**
849   * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
850   * @param  _SAMPLETIME_ Sample time parameter.
851   * @param  _CHANNELNB_ Channel number.
852   * @retval None
853   */
854 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
855 
856 /**
857   * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
858   * @param  _SAMPLETIME_ Sample time parameter.
859   * @param  _CHANNELNB_ Channel number.
860   * @retval None
861   */
862 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
863 
864 /**
865   * @brief  Set the selected regular channel rank for rank between 1 and 6.
866   * @param  _CHANNELNB_ Channel number.
867   * @param  _RANKNB_ Rank number.
868   * @retval None
869   */
870 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
871 
872 /**
873   * @brief  Set the selected regular channel rank for rank between 7 and 12.
874   * @param  _CHANNELNB_ Channel number.
875   * @param  _RANKNB_ Rank number.
876   * @retval None
877   */
878 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
879 
880 /**
881   * @brief  Set the selected regular channel rank for rank between 13 and 16.
882   * @param  _CHANNELNB_ Channel number.
883   * @param  _RANKNB_ Rank number.
884   * @retval None
885   */
886 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
887 
888 /**
889   * @brief  Enable ADC continuous conversion mode.
890   * @param  _CONTINUOUS_MODE_ Continuous mode.
891   * @retval None
892   */
893 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
894 
895 /**
896   * @brief  Configures the number of discontinuous conversions for the regular group channels.
897   * @param  _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
898   * @retval None
899   */
900 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos)
901 
902 /**
903   * @brief  Enable ADC scan mode.
904   * @param  _SCANCONV_MODE_ Scan conversion mode.
905   * @retval None
906   */
907 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
908 
909 /**
910   * @brief  Enable the ADC end of conversion selection.
911   * @param  _EOCSelection_MODE_ End of conversion selection mode.
912   * @retval None
913   */
914 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
915 
916 /**
917   * @brief  Enable the ADC DMA continuous request.
918   * @param  _DMAContReq_MODE_ DMA continuous request mode.
919   * @retval None
920   */
921 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
922 
923 /**
924   * @brief Return resolution bits in CR1 register.
925   * @param __HANDLE__ ADC handle
926   * @retval None
927   */
928 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
929 
930 /**
931   * @}
932   */
933 
934 /* Private functions ---------------------------------------------------------*/
935 /** @defgroup ADC_Private_Functions ADC Private Functions
936   * @{
937   */
938 
939 /**
940   * @}
941   */
942 
943 /**
944   * @}
945   */
946 
947 /**
948   * @}
949   */
950 
951 #ifdef __cplusplus
952 }
953 #endif
954 
955 #endif /* STM32F7xx_ADC_H */
956 
957 
958