1 /**
2   ******************************************************************************
3   * @file    stm32f756xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2016 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32f756xx
30   * @{
31   */
32 
33 #ifndef __STM32F756xx_H
34 #define __STM32F756xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45  * @brief STM32F7xx Interrupt Number Definition, according to the selected device
46  *        in @ref Library_configuration_section
47  */
48 typedef enum
49 {
50 /******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/
51   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
52   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */
53   BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */
54   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */
55   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */
56   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */
57   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */
58   SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */
59 /******  STM32 specific Interrupt Numbers **********************************************************************/
60   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
61   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
62   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
63   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
64   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
65   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
66   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
67   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
68   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
69   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
70   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
71   DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
72   DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
73   DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
74   DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
75   DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
76   DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
77   DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
78   ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
79   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
80   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
81   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
82   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
83   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
84   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
85   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
86   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
87   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
88   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
89   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
90   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
91   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
92   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
93   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
94   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
95   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
96   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
97   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
98   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
99   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
100   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
101   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
102   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
103   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
104   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
105   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
106   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
107   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
108   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
109   SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
110   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
111   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
112   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
113   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
114   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
115   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
116   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
117   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
118   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
119   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
120   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
121   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
122   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
123   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
124   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
125   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
126   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
127   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
128   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
129   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
130   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
131   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
132   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
133   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
134   OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
135   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
136   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
137   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
138   DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
139   CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
140   HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
141   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
142   UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
143   UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
144   SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
145   SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
146   SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
147   SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
148   LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
149   LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
150   DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
151   SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
152   QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
153   LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
154   CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
155   I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
156   I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
157   SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
158 } IRQn_Type;
159 
160 /**
161   * @}
162   */
163 
164 /**
165  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
166  */
167 #define __CM7_REV                 0x0001U  /*!< Cortex-M7 revision r0p1                       */
168 #define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
169 #define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
170 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
171 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
172 #define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
173 #define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
174 #include "core_cm7.h"                      /*!< Cortex-M7 processor and core peripherals      */
175 
176 
177 #include "system_stm32f7xx.h"
178 #include <stdint.h>
179 
180 /** @addtogroup Peripheral_registers_structures
181   * @{
182   */
183 
184 /**
185   * @brief Analog to Digital Converter
186   */
187 
188 typedef struct
189 {
190   __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
191   __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
192   __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
193   __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
194   __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
195   __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
196   __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
197   __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
198   __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
199   __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
200   __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
201   __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
202   __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
203   __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
204   __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
205   __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
206   __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
207   __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
208   __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
209   __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
210 } ADC_TypeDef;
211 
212 typedef struct
213 {
214   __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
215   __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
216   __IO uint32_t CDR;    /*!< ADC common regular data register for dual
217                              AND triple modes,                            Address offset: ADC1 base address + 0x308 */
218 } ADC_Common_TypeDef;
219 
220 
221 /**
222   * @brief Controller Area Network TxMailBox
223   */
224 
225 typedef struct
226 {
227   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
228   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
229   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
230   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
231 } CAN_TxMailBox_TypeDef;
232 
233 /**
234   * @brief Controller Area Network FIFOMailBox
235   */
236 
237 typedef struct
238 {
239   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
240   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
241   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
242   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
243 } CAN_FIFOMailBox_TypeDef;
244 
245 /**
246   * @brief Controller Area Network FilterRegister
247   */
248 
249 typedef struct
250 {
251   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
252   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
253 } CAN_FilterRegister_TypeDef;
254 
255 /**
256   * @brief Controller Area Network
257   */
258 
259 typedef struct
260 {
261   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
262   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
263   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
264   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
265   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
266   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
267   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
268   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
269   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
270   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
271   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
272   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
273   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
274   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
275   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
276   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
277   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
278   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
279   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
280   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
281   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
282   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
283 } CAN_TypeDef;
284 
285 /**
286   * @brief HDMI-CEC
287   */
288 
289 typedef struct
290 {
291   __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
292   __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
293   __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
294   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
295   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
296   __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
297 }CEC_TypeDef;
298 
299 /**
300   * @brief CRC calculation unit
301   */
302 
303 typedef struct
304 {
305   __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */
306   __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
307   uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */
308   uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */
309   __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */
310   uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */
311   __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
312   __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
313 } CRC_TypeDef;
314 
315 /**
316   * @brief Digital to Analog Converter
317   */
318 
319 typedef struct
320 {
321   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
322   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
323   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
324   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
325   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
326   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
327   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
328   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
329   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
330   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
331   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
332   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
333   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
334   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
335 } DAC_TypeDef;
336 
337 
338 /**
339   * @brief Debug MCU
340   */
341 
342 typedef struct
343 {
344   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
345   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
346   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
347   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
348 }DBGMCU_TypeDef;
349 
350 /**
351   * @brief DCMI
352   */
353 
354 typedef struct
355 {
356   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
357   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
358   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
359   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
360   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
361   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
362   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
363   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
364   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
365   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
366   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
367 } DCMI_TypeDef;
368 
369 /**
370   * @brief DMA Controller
371   */
372 
373 typedef struct
374 {
375   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
376   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
377   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
378   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
379   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
380   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
381 } DMA_Stream_TypeDef;
382 
383 typedef struct
384 {
385   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
386   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
387   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
388   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
389 } DMA_TypeDef;
390 
391 /**
392   * @brief DMA2D Controller
393   */
394 
395 typedef struct
396 {
397   __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
398   __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
399   __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
400   __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
401   __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
402   __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
403   __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
404   __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
405   __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
406   __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
407   __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
408   __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
409   __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
410   __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
411   __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
412   __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
413   __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
414   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
415   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
416   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
417   uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
418   __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
419   __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
420 } DMA2D_TypeDef;
421 
422 
423 /**
424   * @brief Ethernet MAC
425   */
426 
427 typedef struct
428 {
429   __IO uint32_t MACCR;
430   __IO uint32_t MACFFR;
431   __IO uint32_t MACHTHR;
432   __IO uint32_t MACHTLR;
433   __IO uint32_t MACMIIAR;
434   __IO uint32_t MACMIIDR;
435   __IO uint32_t MACFCR;
436   __IO uint32_t MACVLANTR;             /*    8 */
437   uint32_t      RESERVED0[2];
438   __IO uint32_t MACRWUFFR;             /*   11 */
439   __IO uint32_t MACPMTCSR;
440   uint32_t      RESERVED1;
441   __IO uint32_t MACDBGR;
442   __IO uint32_t MACSR;                 /*   15 */
443   __IO uint32_t MACIMR;
444   __IO uint32_t MACA0HR;
445   __IO uint32_t MACA0LR;
446   __IO uint32_t MACA1HR;
447   __IO uint32_t MACA1LR;
448   __IO uint32_t MACA2HR;
449   __IO uint32_t MACA2LR;
450   __IO uint32_t MACA3HR;
451   __IO uint32_t MACA3LR;               /*   24 */
452   uint32_t      RESERVED2[40];
453   __IO uint32_t MMCCR;                 /*   65 */
454   __IO uint32_t MMCRIR;
455   __IO uint32_t MMCTIR;
456   __IO uint32_t MMCRIMR;
457   __IO uint32_t MMCTIMR;               /*   69 */
458   uint32_t      RESERVED3[14];
459   __IO uint32_t MMCTGFSCCR;            /*   84 */
460   __IO uint32_t MMCTGFMSCCR;
461   uint32_t      RESERVED4[5];
462   __IO uint32_t MMCTGFCR;
463   uint32_t      RESERVED5[10];
464   __IO uint32_t MMCRFCECR;
465   __IO uint32_t MMCRFAECR;
466   uint32_t      RESERVED6[10];
467   __IO uint32_t MMCRGUFCR;
468   uint32_t      RESERVED7[334];
469   __IO uint32_t PTPTSCR;
470   __IO uint32_t PTPSSIR;
471   __IO uint32_t PTPTSHR;
472   __IO uint32_t PTPTSLR;
473   __IO uint32_t PTPTSHUR;
474   __IO uint32_t PTPTSLUR;
475   __IO uint32_t PTPTSAR;
476   __IO uint32_t PTPTTHR;
477   __IO uint32_t PTPTTLR;
478   __IO uint32_t RESERVED8;
479   __IO uint32_t PTPTSSR;
480   __IO uint32_t PTPPPSCR;
481   uint32_t      RESERVED9[564];
482   __IO uint32_t DMABMR;
483   __IO uint32_t DMATPDR;
484   __IO uint32_t DMARPDR;
485   __IO uint32_t DMARDLAR;
486   __IO uint32_t DMATDLAR;
487   __IO uint32_t DMASR;
488   __IO uint32_t DMAOMR;
489   __IO uint32_t DMAIER;
490   __IO uint32_t DMAMFBOCR;
491   __IO uint32_t DMARSWTR;
492   uint32_t      RESERVED10[8];
493   __IO uint32_t DMACHTDR;
494   __IO uint32_t DMACHRDR;
495   __IO uint32_t DMACHTBAR;
496   __IO uint32_t DMACHRBAR;
497 } ETH_TypeDef;
498 
499 /**
500   * @brief External Interrupt/Event Controller
501   */
502 
503 typedef struct
504 {
505   __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
506   __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
507   __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
508   __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
509   __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
510   __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
511 } EXTI_TypeDef;
512 
513 /**
514   * @brief FLASH Registers
515   */
516 
517 typedef struct
518 {
519   __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */
520   __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */
521   __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */
522   __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */
523   __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */
524   __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */
525   __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */
526 } FLASH_TypeDef;
527 
528 
529 
530 /**
531   * @brief Flexible Memory Controller
532   */
533 
534 typedef struct
535 {
536   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
537 } FMC_Bank1_TypeDef;
538 
539 /**
540   * @brief Flexible Memory Controller Bank1E
541   */
542 
543 typedef struct
544 {
545   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
546 } FMC_Bank1E_TypeDef;
547 
548 /**
549   * @brief Flexible Memory Controller Bank3
550   */
551 
552 typedef struct
553 {
554   __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
555   __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
556   __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
557   __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
558   uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */
559   __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
560 } FMC_Bank3_TypeDef;
561 
562 /**
563   * @brief Flexible Memory Controller Bank5_6
564   */
565 
566 typedef struct
567 {
568   __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
569   __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
570   __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
571   __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
572   __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
573 } FMC_Bank5_6_TypeDef;
574 
575 
576 /**
577   * @brief General Purpose I/O
578   */
579 
580 typedef struct
581 {
582   __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
583   __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
584   __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
585   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
586   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
587   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
588   __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
589   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
590   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
591 } GPIO_TypeDef;
592 
593 /**
594   * @brief System configuration controller
595   */
596 
597 typedef struct
598 {
599   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
600   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
601   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
602   uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
603   __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
604 } SYSCFG_TypeDef;
605 
606 /**
607   * @brief Inter-integrated Circuit Interface
608   */
609 
610 typedef struct
611 {
612   __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
613   __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
614   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
615   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
616   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
617   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
618   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
619   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
620   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
621   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
622   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
623 } I2C_TypeDef;
624 
625 /**
626   * @brief Independent WATCHDOG
627   */
628 
629 typedef struct
630 {
631   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
632   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
633   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
634   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
635   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
636 } IWDG_TypeDef;
637 
638 
639 /**
640   * @brief LCD-TFT Display Controller
641   */
642 
643 typedef struct
644 {
645   uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
646   __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
647   __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
648   __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
649   __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
650   __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
651   uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
652   __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
653   uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
654   __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
655   uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
656   __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
657   __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
658   __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
659   __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
660   __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
661   __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
662 } LTDC_TypeDef;
663 
664 /**
665   * @brief LCD-TFT Display layer x Controller
666   */
667 
668 typedef struct
669 {
670   __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
671   __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
672   __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
673   __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
674   __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
675   __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
676   __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
677   __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
678   uint32_t      RESERVED0[2];  /*!< Reserved */
679   __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
680   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
681   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
682   uint32_t      RESERVED1[3];  /*!< Reserved */
683   __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
684 
685 } LTDC_Layer_TypeDef;
686 
687 /**
688   * @brief Power Control
689   */
690 
691 typedef struct
692 {
693   __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
694   __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */
695   __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */
696   __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */
697 } PWR_TypeDef;
698 
699 
700 /**
701   * @brief Reset and Clock Control
702   */
703 
704 typedef struct
705 {
706   __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
707   __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
708   __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
709   __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
710   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
711   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
712   __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
713   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
714   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
715   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
716   uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
717   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
718   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
719   __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
720   uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
721   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
722   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
723   uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
724   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
725   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
726   __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
727   uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
728   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
729   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
730   uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
731   __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
732   __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
733   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
734   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
735   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
736   __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
737   __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */
738   __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */
739 
740 } RCC_TypeDef;
741 
742 /**
743   * @brief Real-Time Clock
744   */
745 
746 typedef struct
747 {
748   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
749   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
750   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
751   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
752   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
753   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
754        uint32_t reserved;   /*!< Reserved  */
755   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
756   __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
757   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
758   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
759   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
760   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
761   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
762   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
763   __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
764   __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
765   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
766   __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
767   __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
768   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
769   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
770   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
771   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
772   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
773   __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
774   __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
775   __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
776   __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
777   __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
778   __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
779   __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
780   __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
781   __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
782   __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
783   __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
784   __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
785   __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
786   __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
787   __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
788   __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
789   __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
790   __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
791   __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
792   __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
793   __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
794   __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
795   __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
796   __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
797   __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
798   __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
799   __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
800 } RTC_TypeDef;
801 
802 
803 /**
804   * @brief Serial Audio Interface
805   */
806 
807 typedef struct
808 {
809   __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
810 } SAI_TypeDef;
811 
812 typedef struct
813 {
814   __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
815   __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
816   __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
817   __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
818   __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
819   __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
820   __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
821   __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
822 } SAI_Block_TypeDef;
823 
824 /**
825   * @brief SPDIF-RX Interface
826   */
827 
828 typedef struct
829 {
830   __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
831   __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
832   __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
833   __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
834   __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
835   __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
836   __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
837 } SPDIFRX_TypeDef;
838 
839 /**
840   * @brief SD host Interface
841   */
842 
843 typedef struct
844 {
845   __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
846   __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */
847   __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
848   __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
849   __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
850   __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
851   __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
852   __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
853   __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
854   __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
855   __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
856   __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
857   __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
858   __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
859   __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
860   __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
861   uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
862   __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
863   uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
864   __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
865 } SDMMC_TypeDef;
866 
867 /**
868   * @brief Serial Peripheral Interface
869   */
870 
871 typedef struct
872 {
873   __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
874   __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
875   __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
876   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
877   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
878   __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
879   __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
880   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
881   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
882 } SPI_TypeDef;
883 
884 /**
885   * @brief QUAD Serial Peripheral Interface
886   */
887 
888 typedef struct
889 {
890   __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
891   __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
892   __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
893   __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
894   __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
895   __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
896   __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
897   __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
898   __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
899   __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
900   __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
901   __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
902   __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
903 } QUADSPI_TypeDef;
904 
905 /**
906   * @brief TIM
907   */
908 
909 typedef struct
910 {
911   __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
912   __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
913   __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
914   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
915   __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
916   __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
917   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
918   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
919   __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
920   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
921   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
922   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
923   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
924   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
925   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
926   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
927   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
928   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
929   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
930   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
931   __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
932   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
933   __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */
934   __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */
935 
936 } TIM_TypeDef;
937 
938 /**
939   * @brief LPTIMIMER
940   */
941 typedef struct
942 {
943   __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
944   __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
945   __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
946   __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
947   __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
948   __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
949   __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
950   __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
951 } LPTIM_TypeDef;
952 
953 
954 /**
955   * @brief Universal Synchronous Asynchronous Receiver Transmitter
956   */
957 
958 typedef struct
959 {
960   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
961   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
962   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
963   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
964   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
965   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
966   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
967   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
968   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
969   __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
970   __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
971 } USART_TypeDef;
972 
973 
974 /**
975   * @brief Window WATCHDOG
976   */
977 
978 typedef struct
979 {
980   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
981   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
982   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
983 } WWDG_TypeDef;
984 
985 /**
986   * @brief Crypto Processor
987   */
988 
989 typedef struct
990 {
991   __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
992   __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
993   __IO uint32_t DIN;        /*!< CRYP data input register,                                 Address offset: 0x08 */
994   __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
995   __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
996   __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
997   __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
998   __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
999   __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
1000   __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
1001   __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
1002   __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
1003   __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
1004   __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
1005   __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
1006   __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
1007   __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
1008   __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
1009   __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
1010   __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
1011   __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
1012   __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
1013   __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
1014   __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
1015   __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
1016   __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
1017   __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
1018   __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
1019   __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
1020   __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
1021   __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
1022   __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
1023   __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
1024   __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
1025   __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
1026   __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
1027 } CRYP_TypeDef;
1028 
1029 /**
1030   * @brief HASH
1031   */
1032 
1033 typedef struct
1034 {
1035   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
1036   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
1037   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
1038   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
1039   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
1040   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
1041   uint32_t      RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
1042   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
1043 } HASH_TypeDef;
1044 
1045 /**
1046   * @brief HASH_DIGEST
1047   */
1048 
1049 typedef struct
1050 {
1051   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
1052 } HASH_DIGEST_TypeDef;
1053 
1054 /**
1055   * @brief RNG
1056   */
1057 
1058 typedef struct
1059 {
1060   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
1061   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
1062   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
1063 } RNG_TypeDef;
1064 
1065 /**
1066   * @}
1067   */
1068 
1069 /**
1070   * @brief USB_OTG_Core_Registers
1071   */
1072 typedef struct
1073 {
1074  __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
1075   __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
1076   __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
1077   __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
1078   __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
1079   __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
1080   __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
1081   __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
1082   __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
1083   __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
1084   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
1085   __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
1086   uint32_t Reserved30[2];             /*!< Reserved                                     030h */
1087   __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
1088   __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
1089   uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
1090   __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
1091   uint32_t  Reserved6;                /*!< Reserved                                     050h */
1092   __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
1093   uint32_t  Reserved7;                /*!< Reserved                                     058h */
1094   __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
1095   uint32_t  Reserved43[40];           /*!< Reserved                                 60h-0FFh */
1096   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
1097   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO              104h-13Ch */
1098 } USB_OTG_GlobalTypeDef;
1099 
1100 
1101 /**
1102   * @brief USB_OTG_device_Registers
1103   */
1104 typedef struct
1105 {
1106   __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
1107   __IO uint32_t DCTL;            /*!< dev Control Register         804h */
1108   __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
1109   uint32_t Reserved0C;           /*!< Reserved                     80Ch */
1110   __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
1111   __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
1112   __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
1113   __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
1114   uint32_t  Reserved20;          /*!< Reserved                     820h */
1115   uint32_t Reserved9;            /*!< Reserved                     824h */
1116   __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
1117   __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
1118   __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
1119   __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
1120   __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
1121   __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
1122   uint32_t Reserved40;           /*!< dedicated EP mask            840h */
1123   __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
1124   uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
1125   __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
1126 } USB_OTG_DeviceTypeDef;
1127 
1128 
1129 /**
1130   * @brief USB_OTG_IN_Endpoint-Specific_Register
1131   */
1132 typedef struct
1133 {
1134   __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
1135   uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
1136   __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
1137   uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
1138   __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
1139   __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
1140   __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1141   uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1142 } USB_OTG_INEndpointTypeDef;
1143 
1144 
1145 /**
1146   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1147   */
1148 typedef struct
1149 {
1150   __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
1151   uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
1152   __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
1153   uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
1154   __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
1155   __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
1156   uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1157 } USB_OTG_OUTEndpointTypeDef;
1158 
1159 
1160 /**
1161   * @brief USB_OTG_Host_Mode_Register_Structures
1162   */
1163 typedef struct
1164 {
1165   __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
1166   __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
1167   __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
1168   uint32_t Reserved40C;           /*!< Reserved                             40Ch */
1169   __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
1170   __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
1171   __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
1172 } USB_OTG_HostTypeDef;
1173 
1174 /**
1175   * @brief USB_OTG_Host_Channel_Specific_Registers
1176   */
1177 typedef struct
1178 {
1179   __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
1180   __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
1181   __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
1182   __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
1183   __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
1184   __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
1185   uint32_t Reserved[2];           /*!< Reserved                                      */
1186 } USB_OTG_HostChannelTypeDef;
1187 /**
1188   * @}
1189   */
1190 
1191 
1192 
1193 
1194 /** @addtogroup Peripheral_memory_map
1195   * @{
1196   */
1197 #define RAMITCM_BASE           0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */
1198 #define FLASHITCM_BASE         0x00200000UL /*!< Base address of : (up to 1 MB) embedded FLASH memory  accessible over ITCM              */
1199 #define FLASHAXI_BASE          0x08000000UL /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */
1200 #define RAMDTCM_BASE           0x20000000UL /*!< Base address of : 64KB system data RAM accessible over DTCM                             */
1201 #define PERIPH_BASE            0x40000000UL /*!< Base address of : AHB/ABP Peripherals                                                   */
1202 #define BKPSRAM_BASE           0x40024000UL /*!< Base address of : Backup SRAM(4 KB)                                                     */
1203 #define QSPI_BASE              0x90000000UL /*!< Base address of : QSPI memories  accessible over AXI                                    */
1204 #define FMC_R_BASE             0xA0000000UL /*!< Base address of : FMC Control registers                                                 */
1205 #define QSPI_R_BASE            0xA0001000UL /*!< Base address of : QSPI Control  registers                                               */
1206 #define SRAM1_BASE             0x20010000UL /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */
1207 #define SRAM2_BASE             0x2004C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */
1208 #define FLASH_END              0x080FFFFFUL /*!< FLASH end address */
1209 #define FLASH_OTP_BASE         0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area                            */
1210 #define FLASH_OTP_END          0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area                             */
1211 
1212 /* Legacy define */
1213 #define FLASH_BASE     FLASHAXI_BASE
1214 
1215 /*!< Peripheral memory map */
1216 #define APB1PERIPH_BASE        PERIPH_BASE
1217 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
1218 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
1219 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
1220 
1221 /*!< APB1 peripherals */
1222 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
1223 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
1224 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
1225 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
1226 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
1227 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
1228 #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
1229 #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
1230 #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
1231 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400UL)
1232 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
1233 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
1234 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
1235 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1236 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1237 #define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000UL)
1238 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1239 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
1240 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1241 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1242 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1243 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1244 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
1245 #define I2C4_BASE             (APB1PERIPH_BASE + 0x6000UL)
1246 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
1247 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
1248 #define CEC_BASE              (APB1PERIPH_BASE + 0x6C00UL)
1249 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1250 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
1251 #define UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)
1252 #define UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)
1253 
1254 /*!< APB2 peripherals */
1255 #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
1256 #define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
1257 #define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
1258 #define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
1259 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
1260 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
1261 #define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
1262 #define ADC_BASE              (APB2PERIPH_BASE + 0x2300UL)
1263 #define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00UL)
1264 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1265 #define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)
1266 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
1267 #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
1268 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
1269 #define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
1270 #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
1271 #define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)
1272 #define SPI6_BASE             (APB2PERIPH_BASE + 0x5400UL)
1273 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)
1274 #define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00UL)
1275 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
1276 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
1277 #define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
1278 #define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
1279 #define LTDC_BASE             (APB2PERIPH_BASE + 0x6800UL)
1280 #define LTDC_Layer1_BASE      (LTDC_BASE + 0x0084UL)
1281 #define LTDC_Layer2_BASE      (LTDC_BASE + 0x0104UL)
1282 /*!< AHB1 peripherals */
1283 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
1284 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
1285 #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
1286 #define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
1287 #define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
1288 #define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
1289 #define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
1290 #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
1291 #define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
1292 #define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400UL)
1293 #define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800UL)
1294 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1295 #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
1296 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
1297 #define UID_BASE              0x1FF0F420UL                   /*!< Unique device ID register base address */
1298 #define FLASHSIZE_BASE        0x1FF0F442UL                   /*!< FLASH Size register base address */
1299 #define PACKAGE_BASE          0x1FF0F7E0UL                   /*!< Package size register base address */
1300 /* Legacy define */
1301 #define PACKAGESIZE_BASE      PACKAGE_BASE
1302 
1303 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
1304 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
1305 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
1306 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
1307 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
1308 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
1309 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
1310 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
1311 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
1312 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
1313 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
1314 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
1315 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
1316 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
1317 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
1318 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
1319 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
1320 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
1321 #define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
1322 #define ETH_MAC_BASE          (ETH_BASE)
1323 #define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
1324 #define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
1325 #define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
1326 #define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000UL)
1327 /*!< AHB2 peripherals */
1328 #define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
1329 #define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000UL)
1330 #define HASH_BASE             (AHB2PERIPH_BASE + 0x60400UL)
1331 #define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710UL)
1332 #define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
1333 /*!< FMC Bankx registers base address */
1334 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
1335 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
1336 #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
1337 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
1338 
1339 /* Debug MCU registers base address */
1340 #define DBGMCU_BASE           0xE0042000UL
1341 
1342 /*!< USB registers base address */
1343 #define USB_OTG_HS_PERIPH_BASE               0x40040000UL
1344 #define USB_OTG_FS_PERIPH_BASE               0x50000000UL
1345 
1346 #define USB_OTG_GLOBAL_BASE                  0x0000UL
1347 #define USB_OTG_DEVICE_BASE                  0x0800UL
1348 #define USB_OTG_IN_ENDPOINT_BASE             0x0900UL
1349 #define USB_OTG_OUT_ENDPOINT_BASE            0x0B00UL
1350 #define USB_OTG_EP_REG_SIZE                  0x0020UL
1351 #define USB_OTG_HOST_BASE                    0x0400UL
1352 #define USB_OTG_HOST_PORT_BASE               0x0440UL
1353 #define USB_OTG_HOST_CHANNEL_BASE            0x0500UL
1354 #define USB_OTG_HOST_CHANNEL_SIZE            0x0020UL
1355 #define USB_OTG_PCGCCTL_BASE                 0x0E00UL
1356 #define USB_OTG_FIFO_BASE                    0x1000UL
1357 #define USB_OTG_FIFO_SIZE                    0x1000UL
1358 
1359 /**
1360   * @}
1361   */
1362 
1363 /** @addtogroup Peripheral_declaration
1364   * @{
1365   */
1366 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1367 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1368 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1369 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1370 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1371 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1372 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
1373 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
1374 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
1375 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1376 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1377 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1378 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1379 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1380 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1381 #define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1382 #define USART2              ((USART_TypeDef *) USART2_BASE)
1383 #define USART3              ((USART_TypeDef *) USART3_BASE)
1384 #define UART4               ((USART_TypeDef *) UART4_BASE)
1385 #define UART5               ((USART_TypeDef *) UART5_BASE)
1386 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1387 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1388 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1389 #define I2C4                ((I2C_TypeDef *) I2C4_BASE)
1390 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1391 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1392 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
1393 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1394 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
1395 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1396 #define UART7               ((USART_TypeDef *) UART7_BASE)
1397 #define UART8               ((USART_TypeDef *) UART8_BASE)
1398 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1399 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1400 #define USART1              ((USART_TypeDef *) USART1_BASE)
1401 #define USART6              ((USART_TypeDef *) USART6_BASE)
1402 #define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
1403 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1404 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1405 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1406 #define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC_BASE)
1407 #define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
1408 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1409 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1410 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1411 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1412 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
1413 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
1414 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
1415 #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
1416 #define SPI6                ((SPI_TypeDef *) SPI6_BASE)
1417 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1418 #define SAI2                ((SAI_TypeDef *) SAI2_BASE)
1419 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1420 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1421 #define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1422 #define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1423 #define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
1424 #define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1425 #define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1426 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1427 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1428 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1429 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1430 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1431 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1432 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1433 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1434 #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
1435 #define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
1436 #define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
1437 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1438 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1439 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1440 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1441 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1442 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1443 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1444 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1445 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1446 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1447 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1448 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1449 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1450 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1451 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1452 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1453 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1454 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1455 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1456 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1457 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1458 #define ETH                 ((ETH_TypeDef *) ETH_BASE)
1459 #define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
1460 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
1461 #define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
1462 #define HASH                ((HASH_TypeDef *) HASH_BASE)
1463 #define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1464 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1465 #define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1466 #define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1467 #define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1468 #define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1469 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1470 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1471 #define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1472 #define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1473 
1474 /**
1475   * @}
1476   */
1477 
1478 /** @addtogroup Exported_constants
1479   * @{
1480   */
1481 
1482   /** @addtogroup Hardware_Constant_Definition
1483     * @{
1484     */
1485 #define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */
1486 
1487   /**
1488     * @}
1489     */
1490 
1491   /** @addtogroup Peripheral_Registers_Bits_Definition
1492   * @{
1493   */
1494 
1495 /******************************************************************************/
1496 /*                         Peripheral Registers_Bits_Definition               */
1497 /******************************************************************************/
1498 
1499 /******************************************************************************/
1500 /*                                                                            */
1501 /*                        Analog to Digital Converter                         */
1502 /*                                                                            */
1503 /******************************************************************************/
1504 #define VREFINT_CAL_ADDR_CMSIS                   ((uint16_t*) (0x1FF0F44A))     /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV).                      */
1505 #define TEMPSENSOR_CAL1_ADDR_CMSIS               ((uint16_t*) (0x1FF0F44C))     /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
1506 #define TEMPSENSOR_CAL2_ADDR_CMSIS               ((uint16_t*) (0x1FF0F44E))     /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
1507 
1508 /********************  Bit definition for ADC_SR register  ********************/
1509 #define ADC_SR_AWD_Pos            (0U)
1510 #define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
1511 #define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag                                 */
1512 #define ADC_SR_EOC_Pos            (1U)
1513 #define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
1514 #define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion                                    */
1515 #define ADC_SR_JEOC_Pos           (2U)
1516 #define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
1517 #define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion                   */
1518 #define ADC_SR_JSTRT_Pos          (3U)
1519 #define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
1520 #define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag                          */
1521 #define ADC_SR_STRT_Pos           (4U)
1522 #define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
1523 #define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag                           */
1524 #define ADC_SR_OVR_Pos            (5U)
1525 #define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
1526 #define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag                                         */
1527 
1528 /*******************  Bit definition for ADC_CR1 register  ********************/
1529 #define ADC_CR1_AWDCH_Pos         (0U)
1530 #define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
1531 #define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1532 #define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
1533 #define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
1534 #define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
1535 #define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
1536 #define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
1537 #define ADC_CR1_EOCIE_Pos         (5U)
1538 #define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
1539 #define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC                             */
1540 #define ADC_CR1_AWDIE_Pos         (6U)
1541 #define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
1542 #define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable                    */
1543 #define ADC_CR1_JEOCIE_Pos        (7U)
1544 #define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
1545 #define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels               */
1546 #define ADC_CR1_SCAN_Pos          (8U)
1547 #define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
1548 #define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
1549 #define ADC_CR1_AWDSGL_Pos        (9U)
1550 #define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
1551 #define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
1552 #define ADC_CR1_JAUTO_Pos         (10U)
1553 #define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
1554 #define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion                  */
1555 #define ADC_CR1_DISCEN_Pos        (11U)
1556 #define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
1557 #define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels               */
1558 #define ADC_CR1_JDISCEN_Pos       (12U)
1559 #define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
1560 #define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels              */
1561 #define ADC_CR1_DISCNUM_Pos       (13U)
1562 #define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
1563 #define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1564 #define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
1565 #define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
1566 #define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
1567 #define ADC_CR1_JAWDEN_Pos        (22U)
1568 #define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
1569 #define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels          */
1570 #define ADC_CR1_AWDEN_Pos         (23U)
1571 #define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
1572 #define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels           */
1573 #define ADC_CR1_RES_Pos           (24U)
1574 #define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
1575 #define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution)                           */
1576 #define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
1577 #define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
1578 #define ADC_CR1_OVRIE_Pos         (26U)
1579 #define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
1580 #define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
1581 
1582 /*******************  Bit definition for ADC_CR2 register  ********************/
1583 #define ADC_CR2_ADON_Pos          (0U)
1584 #define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
1585 #define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF                                       */
1586 #define ADC_CR2_CONT_Pos          (1U)
1587 #define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
1588 #define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion                                        */
1589 #define ADC_CR2_DMA_Pos           (8U)
1590 #define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
1591 #define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode                                    */
1592 #define ADC_CR2_DDS_Pos           (9U)
1593 #define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
1594 #define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC)                           */
1595 #define ADC_CR2_EOCS_Pos          (10U)
1596 #define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
1597 #define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection                                  */
1598 #define ADC_CR2_ALIGN_Pos         (11U)
1599 #define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
1600 #define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment                                               */
1601 #define ADC_CR2_JEXTSEL_Pos       (16U)
1602 #define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
1603 #define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1604 #define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
1605 #define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
1606 #define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
1607 #define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
1608 #define ADC_CR2_JEXTEN_Pos        (20U)
1609 #define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
1610 #define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1611 #define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
1612 #define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
1613 #define ADC_CR2_JSWSTART_Pos      (22U)
1614 #define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
1615 #define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
1616 #define ADC_CR2_EXTSEL_Pos        (24U)
1617 #define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
1618 #define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1619 #define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
1620 #define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
1621 #define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
1622 #define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
1623 #define ADC_CR2_EXTEN_Pos         (28U)
1624 #define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
1625 #define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1626 #define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
1627 #define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
1628 #define ADC_CR2_SWSTART_Pos       (30U)
1629 #define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
1630 #define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
1631 
1632 /******************  Bit definition for ADC_SMPR1 register  *******************/
1633 #define ADC_SMPR1_SMP10_Pos       (0U)
1634 #define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
1635 #define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1636 #define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
1637 #define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
1638 #define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
1639 #define ADC_SMPR1_SMP11_Pos       (3U)
1640 #define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
1641 #define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1642 #define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
1643 #define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
1644 #define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
1645 #define ADC_SMPR1_SMP12_Pos       (6U)
1646 #define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
1647 #define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1648 #define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
1649 #define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
1650 #define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
1651 #define ADC_SMPR1_SMP13_Pos       (9U)
1652 #define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
1653 #define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1654 #define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
1655 #define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
1656 #define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
1657 #define ADC_SMPR1_SMP14_Pos       (12U)
1658 #define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
1659 #define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1660 #define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
1661 #define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
1662 #define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
1663 #define ADC_SMPR1_SMP15_Pos       (15U)
1664 #define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
1665 #define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1666 #define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
1667 #define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
1668 #define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
1669 #define ADC_SMPR1_SMP16_Pos       (18U)
1670 #define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
1671 #define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1672 #define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
1673 #define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
1674 #define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
1675 #define ADC_SMPR1_SMP17_Pos       (21U)
1676 #define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
1677 #define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1678 #define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
1679 #define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
1680 #define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
1681 #define ADC_SMPR1_SMP18_Pos       (24U)
1682 #define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
1683 #define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1684 #define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
1685 #define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
1686 #define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
1687 
1688 /******************  Bit definition for ADC_SMPR2 register  *******************/
1689 #define ADC_SMPR2_SMP0_Pos        (0U)
1690 #define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
1691 #define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1692 #define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
1693 #define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
1694 #define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
1695 #define ADC_SMPR2_SMP1_Pos        (3U)
1696 #define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
1697 #define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1698 #define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
1699 #define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
1700 #define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
1701 #define ADC_SMPR2_SMP2_Pos        (6U)
1702 #define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
1703 #define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1704 #define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
1705 #define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
1706 #define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
1707 #define ADC_SMPR2_SMP3_Pos        (9U)
1708 #define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
1709 #define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1710 #define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
1711 #define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
1712 #define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
1713 #define ADC_SMPR2_SMP4_Pos        (12U)
1714 #define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
1715 #define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1716 #define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
1717 #define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
1718 #define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
1719 #define ADC_SMPR2_SMP5_Pos        (15U)
1720 #define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
1721 #define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1722 #define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
1723 #define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
1724 #define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
1725 #define ADC_SMPR2_SMP6_Pos        (18U)
1726 #define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
1727 #define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1728 #define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
1729 #define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
1730 #define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
1731 #define ADC_SMPR2_SMP7_Pos        (21U)
1732 #define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
1733 #define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1734 #define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
1735 #define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
1736 #define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
1737 #define ADC_SMPR2_SMP8_Pos        (24U)
1738 #define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
1739 #define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1740 #define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
1741 #define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
1742 #define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
1743 #define ADC_SMPR2_SMP9_Pos        (27U)
1744 #define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
1745 #define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1746 #define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
1747 #define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
1748 #define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
1749 
1750 /******************  Bit definition for ADC_JOFR1 register  *******************/
1751 #define ADC_JOFR1_JOFFSET1_Pos    (0U)
1752 #define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
1753 #define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
1754 
1755 /******************  Bit definition for ADC_JOFR2 register  *******************/
1756 #define ADC_JOFR2_JOFFSET2_Pos    (0U)
1757 #define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
1758 #define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
1759 
1760 /******************  Bit definition for ADC_JOFR3 register  *******************/
1761 #define ADC_JOFR3_JOFFSET3_Pos    (0U)
1762 #define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
1763 #define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
1764 
1765 /******************  Bit definition for ADC_JOFR4 register  *******************/
1766 #define ADC_JOFR4_JOFFSET4_Pos    (0U)
1767 #define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
1768 #define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
1769 
1770 /*******************  Bit definition for ADC_HTR register  ********************/
1771 #define ADC_HTR_HT_Pos            (0U)
1772 #define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
1773 #define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
1774 
1775 /*******************  Bit definition for ADC_LTR register  ********************/
1776 #define ADC_LTR_LT_Pos            (0U)
1777 #define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
1778 #define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
1779 
1780 /*******************  Bit definition for ADC_SQR1 register  *******************/
1781 #define ADC_SQR1_SQ13_Pos         (0U)
1782 #define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
1783 #define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1784 #define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
1785 #define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
1786 #define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
1787 #define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
1788 #define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
1789 #define ADC_SQR1_SQ14_Pos         (5U)
1790 #define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
1791 #define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1792 #define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
1793 #define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
1794 #define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
1795 #define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
1796 #define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
1797 #define ADC_SQR1_SQ15_Pos         (10U)
1798 #define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
1799 #define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1800 #define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
1801 #define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
1802 #define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
1803 #define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
1804 #define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
1805 #define ADC_SQR1_SQ16_Pos         (15U)
1806 #define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
1807 #define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1808 #define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
1809 #define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
1810 #define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
1811 #define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
1812 #define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
1813 #define ADC_SQR1_L_Pos            (20U)
1814 #define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
1815 #define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
1816 #define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
1817 #define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
1818 #define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
1819 #define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
1820 
1821 /*******************  Bit definition for ADC_SQR2 register  *******************/
1822 #define ADC_SQR2_SQ7_Pos          (0U)
1823 #define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
1824 #define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1825 #define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
1826 #define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
1827 #define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
1828 #define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
1829 #define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
1830 #define ADC_SQR2_SQ8_Pos          (5U)
1831 #define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
1832 #define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1833 #define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
1834 #define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
1835 #define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
1836 #define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
1837 #define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
1838 #define ADC_SQR2_SQ9_Pos          (10U)
1839 #define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
1840 #define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1841 #define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
1842 #define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
1843 #define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
1844 #define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
1845 #define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
1846 #define ADC_SQR2_SQ10_Pos         (15U)
1847 #define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
1848 #define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1849 #define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
1850 #define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
1851 #define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
1852 #define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
1853 #define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
1854 #define ADC_SQR2_SQ11_Pos         (20U)
1855 #define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
1856 #define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1857 #define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
1858 #define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
1859 #define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
1860 #define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
1861 #define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
1862 #define ADC_SQR2_SQ12_Pos         (25U)
1863 #define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
1864 #define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1865 #define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
1866 #define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
1867 #define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
1868 #define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
1869 #define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
1870 
1871 /*******************  Bit definition for ADC_SQR3 register  *******************/
1872 #define ADC_SQR3_SQ1_Pos          (0U)
1873 #define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
1874 #define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1875 #define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
1876 #define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
1877 #define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
1878 #define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
1879 #define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
1880 #define ADC_SQR3_SQ2_Pos          (5U)
1881 #define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
1882 #define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1883 #define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
1884 #define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
1885 #define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
1886 #define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
1887 #define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
1888 #define ADC_SQR3_SQ3_Pos          (10U)
1889 #define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
1890 #define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1891 #define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
1892 #define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
1893 #define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
1894 #define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
1895 #define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
1896 #define ADC_SQR3_SQ4_Pos          (15U)
1897 #define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
1898 #define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1899 #define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
1900 #define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
1901 #define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
1902 #define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
1903 #define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
1904 #define ADC_SQR3_SQ5_Pos          (20U)
1905 #define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
1906 #define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1907 #define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
1908 #define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
1909 #define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
1910 #define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
1911 #define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
1912 #define ADC_SQR3_SQ6_Pos          (25U)
1913 #define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
1914 #define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1915 #define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
1916 #define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
1917 #define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
1918 #define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
1919 #define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
1920 
1921 /*******************  Bit definition for ADC_JSQR register  *******************/
1922 #define ADC_JSQR_JSQ1_Pos         (0U)
1923 #define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
1924 #define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1925 #define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
1926 #define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
1927 #define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
1928 #define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
1929 #define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
1930 #define ADC_JSQR_JSQ2_Pos         (5U)
1931 #define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
1932 #define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1933 #define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
1934 #define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
1935 #define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
1936 #define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
1937 #define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
1938 #define ADC_JSQR_JSQ3_Pos         (10U)
1939 #define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
1940 #define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1941 #define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
1942 #define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
1943 #define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
1944 #define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
1945 #define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
1946 #define ADC_JSQR_JSQ4_Pos         (15U)
1947 #define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
1948 #define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1949 #define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
1950 #define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
1951 #define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
1952 #define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
1953 #define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
1954 #define ADC_JSQR_JL_Pos           (20U)
1955 #define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
1956 #define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
1957 #define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
1958 #define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
1959 
1960 /*******************  Bit definition for ADC_JDR1 register  *******************/
1961 #define ADC_JDR1_JDATA            ((uint16_t)0xFFFFU)                          /*!<Injected data */
1962 
1963 /*******************  Bit definition for ADC_JDR2 register  *******************/
1964 #define ADC_JDR2_JDATA            ((uint16_t)0xFFFFU)                          /*!<Injected data */
1965 
1966 /*******************  Bit definition for ADC_JDR3 register  *******************/
1967 #define ADC_JDR3_JDATA            ((uint16_t)0xFFFFU)                          /*!<Injected data */
1968 
1969 /*******************  Bit definition for ADC_JDR4 register  *******************/
1970 #define ADC_JDR4_JDATA            ((uint16_t)0xFFFFU)                          /*!<Injected data */
1971 
1972 /********************  Bit definition for ADC_DR register  ********************/
1973 #define ADC_DR_DATA_Pos           (0U)
1974 #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1975 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
1976 #define ADC_DR_ADC2DATA_Pos       (16U)
1977 #define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
1978 #define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
1979 
1980 /*******************  Bit definition for ADC_CSR register  ********************/
1981 #define ADC_CSR_AWD1_Pos          (0U)
1982 #define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
1983 #define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag               */
1984 #define ADC_CSR_EOC1_Pos          (1U)
1985 #define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
1986 #define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion                  */
1987 #define ADC_CSR_JEOC1_Pos         (2U)
1988 #define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
1989 #define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
1990 #define ADC_CSR_JSTRT1_Pos        (3U)
1991 #define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
1992 #define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag        */
1993 #define ADC_CSR_STRT1_Pos         (4U)
1994 #define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
1995 #define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag         */
1996 #define ADC_CSR_OVR1_Pos          (5U)
1997 #define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
1998 #define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 Overrun flag                       */
1999 #define ADC_CSR_AWD2_Pos          (8U)
2000 #define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
2001 #define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag               */
2002 #define ADC_CSR_EOC2_Pos          (9U)
2003 #define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
2004 #define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion                  */
2005 #define ADC_CSR_JEOC2_Pos         (10U)
2006 #define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
2007 #define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
2008 #define ADC_CSR_JSTRT2_Pos        (11U)
2009 #define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
2010 #define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag        */
2011 #define ADC_CSR_STRT2_Pos         (12U)
2012 #define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
2013 #define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag         */
2014 #define ADC_CSR_OVR2_Pos          (13U)
2015 #define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
2016 #define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 Overrun flag                       */
2017 #define ADC_CSR_AWD3_Pos          (16U)
2018 #define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
2019 #define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag               */
2020 #define ADC_CSR_EOC3_Pos          (17U)
2021 #define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
2022 #define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion                  */
2023 #define ADC_CSR_JEOC3_Pos         (18U)
2024 #define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
2025 #define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
2026 #define ADC_CSR_JSTRT3_Pos        (19U)
2027 #define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
2028 #define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag        */
2029 #define ADC_CSR_STRT3_Pos         (20U)
2030 #define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
2031 #define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag         */
2032 #define ADC_CSR_OVR3_Pos          (21U)
2033 #define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
2034 #define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 Overrun flag                       */
2035 
2036 /* Legacy defines */
2037 #define  ADC_CSR_DOVR1                       ADC_CSR_OVR1
2038 #define  ADC_CSR_DOVR2                       ADC_CSR_OVR2
2039 #define  ADC_CSR_DOVR3                       ADC_CSR_OVR3
2040 
2041 
2042 /*******************  Bit definition for ADC_CCR register  ********************/
2043 #define ADC_CCR_MULTI_Pos         (0U)
2044 #define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
2045 #define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
2046 #define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
2047 #define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
2048 #define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
2049 #define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
2050 #define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
2051 #define ADC_CCR_DELAY_Pos         (8U)
2052 #define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
2053 #define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
2054 #define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
2055 #define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
2056 #define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
2057 #define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
2058 #define ADC_CCR_DDS_Pos           (13U)
2059 #define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
2060 #define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
2061 #define ADC_CCR_DMA_Pos           (14U)
2062 #define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
2063 #define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
2064 #define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
2065 #define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
2066 #define ADC_CCR_ADCPRE_Pos        (16U)
2067 #define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
2068 #define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
2069 #define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
2070 #define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
2071 #define ADC_CCR_VBATE_Pos         (22U)
2072 #define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
2073 #define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
2074 #define ADC_CCR_TSVREFE_Pos       (23U)
2075 #define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
2076 #define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
2077 
2078 /*******************  Bit definition for ADC_CDR register  ********************/
2079 #define ADC_CDR_DATA1_Pos         (0U)
2080 #define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
2081 #define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
2082 #define ADC_CDR_DATA2_Pos         (16U)
2083 #define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
2084 #define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
2085 
2086 /* Legacy defines */
2087 #define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
2088 #define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
2089 
2090 /******************************************************************************/
2091 /*                                                                            */
2092 /*                         Controller Area Network                            */
2093 /*                                                                            */
2094 /******************************************************************************/
2095 /*!<CAN control and status registers */
2096 /*******************  Bit definition for CAN_MCR register  ********************/
2097 #define CAN_MCR_INRQ_Pos       (0U)
2098 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
2099 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request            */
2100 #define CAN_MCR_SLEEP_Pos      (1U)
2101 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
2102 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request                */
2103 #define CAN_MCR_TXFP_Pos       (2U)
2104 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
2105 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority            */
2106 #define CAN_MCR_RFLM_Pos       (3U)
2107 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
2108 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode          */
2109 #define CAN_MCR_NART_Pos       (4U)
2110 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
2111 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission       */
2112 #define CAN_MCR_AWUM_Pos       (5U)
2113 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
2114 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode             */
2115 #define CAN_MCR_ABOM_Pos       (6U)
2116 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
2117 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management      */
2118 #define CAN_MCR_TTCM_Pos       (7U)
2119 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
2120 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
2121 #define CAN_MCR_RESET_Pos      (15U)
2122 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
2123 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset       */
2124 
2125 /*******************  Bit definition for CAN_MSR register  ********************/
2126 #define CAN_MSR_INAK_Pos       (0U)
2127 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
2128 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge  */
2129 #define CAN_MSR_SLAK_Pos       (1U)
2130 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
2131 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge           */
2132 #define CAN_MSR_ERRI_Pos       (2U)
2133 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
2134 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt             */
2135 #define CAN_MSR_WKUI_Pos       (3U)
2136 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
2137 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt            */
2138 #define CAN_MSR_SLAKI_Pos      (4U)
2139 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
2140 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
2141 #define CAN_MSR_TXM_Pos        (8U)
2142 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
2143 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode               */
2144 #define CAN_MSR_RXM_Pos        (9U)
2145 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
2146 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode                */
2147 #define CAN_MSR_SAMP_Pos       (10U)
2148 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
2149 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point           */
2150 #define CAN_MSR_RX_Pos         (11U)
2151 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
2152 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal               */
2153 
2154 /*******************  Bit definition for CAN_TSR register  ********************/
2155 #define CAN_TSR_RQCP0_Pos      (0U)
2156 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
2157 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0      */
2158 #define CAN_TSR_TXOK0_Pos      (1U)
2159 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
2160 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0     */
2161 #define CAN_TSR_ALST0_Pos      (2U)
2162 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
2163 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0   */
2164 #define CAN_TSR_TERR0_Pos      (3U)
2165 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
2166 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0  */
2167 #define CAN_TSR_ABRQ0_Pos      (7U)
2168 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
2169 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0      */
2170 #define CAN_TSR_RQCP1_Pos      (8U)
2171 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
2172 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1      */
2173 #define CAN_TSR_TXOK1_Pos      (9U)
2174 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
2175 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1     */
2176 #define CAN_TSR_ALST1_Pos      (10U)
2177 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
2178 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1   */
2179 #define CAN_TSR_TERR1_Pos      (11U)
2180 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
2181 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1  */
2182 #define CAN_TSR_ABRQ1_Pos      (15U)
2183 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
2184 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1     */
2185 #define CAN_TSR_RQCP2_Pos      (16U)
2186 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
2187 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2      */
2188 #define CAN_TSR_TXOK2_Pos      (17U)
2189 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
2190 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2    */
2191 #define CAN_TSR_ALST2_Pos      (18U)
2192 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
2193 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2  */
2194 #define CAN_TSR_TERR2_Pos      (19U)
2195 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
2196 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
2197 #define CAN_TSR_ABRQ2_Pos      (23U)
2198 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
2199 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2     */
2200 #define CAN_TSR_CODE_Pos       (24U)
2201 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
2202 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code                    */
2203 
2204 #define CAN_TSR_TME_Pos        (26U)
2205 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
2206 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
2207 #define CAN_TSR_TME0_Pos       (26U)
2208 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
2209 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
2210 #define CAN_TSR_TME1_Pos       (27U)
2211 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
2212 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
2213 #define CAN_TSR_TME2_Pos       (28U)
2214 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
2215 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
2216 
2217 #define CAN_TSR_LOW_Pos        (29U)
2218 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
2219 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
2220 #define CAN_TSR_LOW0_Pos       (29U)
2221 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
2222 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
2223 #define CAN_TSR_LOW1_Pos       (30U)
2224 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
2225 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
2226 #define CAN_TSR_LOW2_Pos       (31U)
2227 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
2228 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
2229 
2230 /*******************  Bit definition for CAN_RF0R register  *******************/
2231 #define CAN_RF0R_FMP0_Pos      (0U)
2232 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
2233 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending        */
2234 #define CAN_RF0R_FULL0_Pos     (3U)
2235 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
2236 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full                   */
2237 #define CAN_RF0R_FOVR0_Pos     (4U)
2238 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
2239 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun                */
2240 #define CAN_RF0R_RFOM0_Pos     (5U)
2241 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
2242 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
2243 
2244 /*******************  Bit definition for CAN_RF1R register  *******************/
2245 #define CAN_RF1R_FMP1_Pos      (0U)
2246 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
2247 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending        */
2248 #define CAN_RF1R_FULL1_Pos     (3U)
2249 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
2250 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full                   */
2251 #define CAN_RF1R_FOVR1_Pos     (4U)
2252 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
2253 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun                */
2254 #define CAN_RF1R_RFOM1_Pos     (5U)
2255 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
2256 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
2257 
2258 /********************  Bit definition for CAN_IER register  *******************/
2259 #define CAN_IER_TMEIE_Pos      (0U)
2260 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
2261 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
2262 #define CAN_IER_FMPIE0_Pos     (1U)
2263 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
2264 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable   */
2265 #define CAN_IER_FFIE0_Pos      (2U)
2266 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
2267 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable              */
2268 #define CAN_IER_FOVIE0_Pos     (3U)
2269 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
2270 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable           */
2271 #define CAN_IER_FMPIE1_Pos     (4U)
2272 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
2273 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable   */
2274 #define CAN_IER_FFIE1_Pos      (5U)
2275 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
2276 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable              */
2277 #define CAN_IER_FOVIE1_Pos     (6U)
2278 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
2279 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable           */
2280 #define CAN_IER_EWGIE_Pos      (8U)
2281 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
2282 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable          */
2283 #define CAN_IER_EPVIE_Pos      (9U)
2284 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
2285 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable          */
2286 #define CAN_IER_BOFIE_Pos      (10U)
2287 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
2288 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable                */
2289 #define CAN_IER_LECIE_Pos      (11U)
2290 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
2291 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable        */
2292 #define CAN_IER_ERRIE_Pos      (15U)
2293 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
2294 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable                  */
2295 #define CAN_IER_WKUIE_Pos      (16U)
2296 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
2297 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable                 */
2298 #define CAN_IER_SLKIE_Pos      (17U)
2299 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
2300 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable                  */
2301 
2302 /********************  Bit definition for CAN_ESR register  *******************/
2303 #define CAN_ESR_EWGF_Pos       (0U)
2304 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
2305 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
2306 #define CAN_ESR_EPVF_Pos       (1U)
2307 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
2308 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
2309 #define CAN_ESR_BOFF_Pos       (2U)
2310 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
2311 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
2312 
2313 #define CAN_ESR_LEC_Pos        (4U)
2314 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
2315 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
2316 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
2317 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
2318 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
2319 
2320 #define CAN_ESR_TEC_Pos        (16U)
2321 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
2322 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2323 #define CAN_ESR_REC_Pos        (24U)
2324 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
2325 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2326 
2327 /*******************  Bit definition for CAN_BTR register  ********************/
2328 #define CAN_BTR_BRP_Pos        (0U)
2329 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
2330 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler           */
2331 #define CAN_BTR_TS1_Pos        (16U)
2332 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
2333 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1                */
2334 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
2335 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
2336 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
2337 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
2338 #define CAN_BTR_TS2_Pos        (20U)
2339 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
2340 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2                */
2341 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
2342 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
2343 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
2344 #define CAN_BTR_SJW_Pos        (24U)
2345 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
2346 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width  */
2347 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
2348 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
2349 #define CAN_BTR_LBKM_Pos       (30U)
2350 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
2351 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug)        */
2352 #define CAN_BTR_SILM_Pos       (31U)
2353 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
2354 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode                   */
2355 
2356 /*!<Mailbox registers */
2357 /******************  Bit definition for CAN_TI0R register  ********************/
2358 #define CAN_TI0R_TXRQ_Pos      (0U)
2359 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
2360 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request                   */
2361 #define CAN_TI0R_RTR_Pos       (1U)
2362 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
2363 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request                */
2364 #define CAN_TI0R_IDE_Pos       (2U)
2365 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
2366 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension                       */
2367 #define CAN_TI0R_EXID_Pos      (3U)
2368 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2369 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier                        */
2370 #define CAN_TI0R_STID_Pos      (21U)
2371 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
2372 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2373 
2374 /******************  Bit definition for CAN_TDT0R register  *******************/
2375 #define CAN_TDT0R_DLC_Pos      (0U)
2376 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
2377 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code     */
2378 #define CAN_TDT0R_TGT_Pos      (8U)
2379 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
2380 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2381 #define CAN_TDT0R_TIME_Pos     (16U)
2382 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2383 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp   */
2384 
2385 /******************  Bit definition for CAN_TDL0R register  *******************/
2386 #define CAN_TDL0R_DATA0_Pos    (0U)
2387 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2388 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2389 #define CAN_TDL0R_DATA1_Pos    (8U)
2390 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2391 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2392 #define CAN_TDL0R_DATA2_Pos    (16U)
2393 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2394 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2395 #define CAN_TDL0R_DATA3_Pos    (24U)
2396 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2397 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2398 
2399 /******************  Bit definition for CAN_TDH0R register  *******************/
2400 #define CAN_TDH0R_DATA4_Pos    (0U)
2401 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2402 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2403 #define CAN_TDH0R_DATA5_Pos    (8U)
2404 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2405 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2406 #define CAN_TDH0R_DATA6_Pos    (16U)
2407 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2408 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2409 #define CAN_TDH0R_DATA7_Pos    (24U)
2410 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2411 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2412 
2413 /*******************  Bit definition for CAN_TI1R register  *******************/
2414 #define CAN_TI1R_TXRQ_Pos      (0U)
2415 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
2416 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request                   */
2417 #define CAN_TI1R_RTR_Pos       (1U)
2418 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
2419 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request                */
2420 #define CAN_TI1R_IDE_Pos       (2U)
2421 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
2422 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension                       */
2423 #define CAN_TI1R_EXID_Pos      (3U)
2424 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2425 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier                        */
2426 #define CAN_TI1R_STID_Pos      (21U)
2427 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
2428 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2429 
2430 /*******************  Bit definition for CAN_TDT1R register  ******************/
2431 #define CAN_TDT1R_DLC_Pos      (0U)
2432 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
2433 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code     */
2434 #define CAN_TDT1R_TGT_Pos      (8U)
2435 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
2436 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2437 #define CAN_TDT1R_TIME_Pos     (16U)
2438 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2439 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp   */
2440 
2441 /*******************  Bit definition for CAN_TDL1R register  ******************/
2442 #define CAN_TDL1R_DATA0_Pos    (0U)
2443 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2444 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2445 #define CAN_TDL1R_DATA1_Pos    (8U)
2446 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2447 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2448 #define CAN_TDL1R_DATA2_Pos    (16U)
2449 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2450 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2451 #define CAN_TDL1R_DATA3_Pos    (24U)
2452 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2453 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2454 
2455 /*******************  Bit definition for CAN_TDH1R register  ******************/
2456 #define CAN_TDH1R_DATA4_Pos    (0U)
2457 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2458 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2459 #define CAN_TDH1R_DATA5_Pos    (8U)
2460 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2461 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2462 #define CAN_TDH1R_DATA6_Pos    (16U)
2463 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2464 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2465 #define CAN_TDH1R_DATA7_Pos    (24U)
2466 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2467 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2468 
2469 /*******************  Bit definition for CAN_TI2R register  *******************/
2470 #define CAN_TI2R_TXRQ_Pos      (0U)
2471 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
2472 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request                   */
2473 #define CAN_TI2R_RTR_Pos       (1U)
2474 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
2475 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request                */
2476 #define CAN_TI2R_IDE_Pos       (2U)
2477 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
2478 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension                       */
2479 #define CAN_TI2R_EXID_Pos      (3U)
2480 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
2481 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier                        */
2482 #define CAN_TI2R_STID_Pos      (21U)
2483 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
2484 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2485 
2486 /*******************  Bit definition for CAN_TDT2R register  ******************/
2487 #define CAN_TDT2R_DLC_Pos      (0U)
2488 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
2489 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code      */
2490 #define CAN_TDT2R_TGT_Pos      (8U)
2491 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
2492 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time  */
2493 #define CAN_TDT2R_TIME_Pos     (16U)
2494 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
2495 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp    */
2496 
2497 /*******************  Bit definition for CAN_TDL2R register  ******************/
2498 #define CAN_TDL2R_DATA0_Pos    (0U)
2499 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
2500 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2501 #define CAN_TDL2R_DATA1_Pos    (8U)
2502 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
2503 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2504 #define CAN_TDL2R_DATA2_Pos    (16U)
2505 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
2506 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2507 #define CAN_TDL2R_DATA3_Pos    (24U)
2508 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
2509 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2510 
2511 /*******************  Bit definition for CAN_TDH2R register  ******************/
2512 #define CAN_TDH2R_DATA4_Pos    (0U)
2513 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
2514 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2515 #define CAN_TDH2R_DATA5_Pos    (8U)
2516 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
2517 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2518 #define CAN_TDH2R_DATA6_Pos    (16U)
2519 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
2520 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2521 #define CAN_TDH2R_DATA7_Pos    (24U)
2522 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
2523 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2524 
2525 /*******************  Bit definition for CAN_RI0R register  *******************/
2526 #define CAN_RI0R_RTR_Pos       (1U)
2527 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
2528 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request                */
2529 #define CAN_RI0R_IDE_Pos       (2U)
2530 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
2531 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension                       */
2532 #define CAN_RI0R_EXID_Pos      (3U)
2533 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2534 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier                        */
2535 #define CAN_RI0R_STID_Pos      (21U)
2536 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
2537 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2538 
2539 /*******************  Bit definition for CAN_RDT0R register  ******************/
2540 #define CAN_RDT0R_DLC_Pos      (0U)
2541 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
2542 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
2543 #define CAN_RDT0R_FMI_Pos      (8U)
2544 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
2545 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
2546 #define CAN_RDT0R_TIME_Pos     (16U)
2547 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2548 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
2549 
2550 /*******************  Bit definition for CAN_RDL0R register  ******************/
2551 #define CAN_RDL0R_DATA0_Pos    (0U)
2552 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2553 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
2554 #define CAN_RDL0R_DATA1_Pos    (8U)
2555 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2556 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
2557 #define CAN_RDL0R_DATA2_Pos    (16U)
2558 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2559 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
2560 #define CAN_RDL0R_DATA3_Pos    (24U)
2561 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2562 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
2563 
2564 /*******************  Bit definition for CAN_RDH0R register  ******************/
2565 #define CAN_RDH0R_DATA4_Pos    (0U)
2566 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2567 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
2568 #define CAN_RDH0R_DATA5_Pos    (8U)
2569 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2570 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
2571 #define CAN_RDH0R_DATA6_Pos    (16U)
2572 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2573 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
2574 #define CAN_RDH0R_DATA7_Pos    (24U)
2575 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2576 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
2577 
2578 /*******************  Bit definition for CAN_RI1R register  *******************/
2579 #define CAN_RI1R_RTR_Pos       (1U)
2580 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
2581 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request                */
2582 #define CAN_RI1R_IDE_Pos       (2U)
2583 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
2584 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension                       */
2585 #define CAN_RI1R_EXID_Pos      (3U)
2586 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2587 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier                        */
2588 #define CAN_RI1R_STID_Pos      (21U)
2589 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
2590 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2591 
2592 /*******************  Bit definition for CAN_RDT1R register  ******************/
2593 #define CAN_RDT1R_DLC_Pos      (0U)
2594 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
2595 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code   */
2596 #define CAN_RDT1R_FMI_Pos      (8U)
2597 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
2598 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
2599 #define CAN_RDT1R_TIME_Pos     (16U)
2600 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2601 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
2602 
2603 /*******************  Bit definition for CAN_RDL1R register  ******************/
2604 #define CAN_RDL1R_DATA0_Pos    (0U)
2605 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2606 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
2607 #define CAN_RDL1R_DATA1_Pos    (8U)
2608 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2609 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
2610 #define CAN_RDL1R_DATA2_Pos    (16U)
2611 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2612 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
2613 #define CAN_RDL1R_DATA3_Pos    (24U)
2614 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2615 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
2616 
2617 /*******************  Bit definition for CAN_RDH1R register  ******************/
2618 #define CAN_RDH1R_DATA4_Pos    (0U)
2619 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2620 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
2621 #define CAN_RDH1R_DATA5_Pos    (8U)
2622 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2623 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
2624 #define CAN_RDH1R_DATA6_Pos    (16U)
2625 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2626 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
2627 #define CAN_RDH1R_DATA7_Pos    (24U)
2628 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2629 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
2630 
2631 /*!<CAN filter registers */
2632 /*******************  Bit definition for CAN_FMR register  ********************/
2633 #define CAN_FMR_FINIT          ((uint8_t)0x01U)                                /*!<Filter Init Mode */
2634 #define CAN_FMR_CAN2SB_Pos     (8U)
2635 #define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
2636 #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
2637 
2638 /*******************  Bit definition for CAN_FM1R register  *******************/
2639 #define CAN_FM1R_FBM_Pos       (0U)
2640 #define CAN_FM1R_FBM_Msk       (0x3FFFUL << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
2641 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
2642 #define CAN_FM1R_FBM0_Pos      (0U)
2643 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
2644 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0  */
2645 #define CAN_FM1R_FBM1_Pos      (1U)
2646 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
2647 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1  */
2648 #define CAN_FM1R_FBM2_Pos      (2U)
2649 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
2650 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2  */
2651 #define CAN_FM1R_FBM3_Pos      (3U)
2652 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
2653 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3  */
2654 #define CAN_FM1R_FBM4_Pos      (4U)
2655 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
2656 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4  */
2657 #define CAN_FM1R_FBM5_Pos      (5U)
2658 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
2659 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5  */
2660 #define CAN_FM1R_FBM6_Pos      (6U)
2661 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
2662 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6  */
2663 #define CAN_FM1R_FBM7_Pos      (7U)
2664 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
2665 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7  */
2666 #define CAN_FM1R_FBM8_Pos      (8U)
2667 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
2668 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8  */
2669 #define CAN_FM1R_FBM9_Pos      (9U)
2670 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
2671 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9  */
2672 #define CAN_FM1R_FBM10_Pos     (10U)
2673 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
2674 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
2675 #define CAN_FM1R_FBM11_Pos     (11U)
2676 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
2677 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
2678 #define CAN_FM1R_FBM12_Pos     (12U)
2679 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
2680 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
2681 #define CAN_FM1R_FBM13_Pos     (13U)
2682 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
2683 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
2684 
2685 /*******************  Bit definition for CAN_FS1R register  *******************/
2686 #define CAN_FS1R_FSC_Pos       (0U)
2687 #define CAN_FS1R_FSC_Msk       (0x3FFFUL << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
2688 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration        */
2689 #define CAN_FS1R_FSC0_Pos      (0U)
2690 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
2691 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0  */
2692 #define CAN_FS1R_FSC1_Pos      (1U)
2693 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
2694 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1  */
2695 #define CAN_FS1R_FSC2_Pos      (2U)
2696 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
2697 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2  */
2698 #define CAN_FS1R_FSC3_Pos      (3U)
2699 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
2700 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3  */
2701 #define CAN_FS1R_FSC4_Pos      (4U)
2702 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
2703 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4  */
2704 #define CAN_FS1R_FSC5_Pos      (5U)
2705 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
2706 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5  */
2707 #define CAN_FS1R_FSC6_Pos      (6U)
2708 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
2709 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6  */
2710 #define CAN_FS1R_FSC7_Pos      (7U)
2711 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
2712 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7  */
2713 #define CAN_FS1R_FSC8_Pos      (8U)
2714 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
2715 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8  */
2716 #define CAN_FS1R_FSC9_Pos      (9U)
2717 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
2718 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9  */
2719 #define CAN_FS1R_FSC10_Pos     (10U)
2720 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
2721 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
2722 #define CAN_FS1R_FSC11_Pos     (11U)
2723 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
2724 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
2725 #define CAN_FS1R_FSC12_Pos     (12U)
2726 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
2727 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
2728 #define CAN_FS1R_FSC13_Pos     (13U)
2729 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
2730 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
2731 
2732 /******************  Bit definition for CAN_FFA1R register  *******************/
2733 #define CAN_FFA1R_FFA_Pos      (0U)
2734 #define CAN_FFA1R_FFA_Msk      (0x3FFFUL << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
2735 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
2736 #define CAN_FFA1R_FFA0_Pos     (0U)
2737 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
2738 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
2739 #define CAN_FFA1R_FFA1_Pos     (1U)
2740 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
2741 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
2742 #define CAN_FFA1R_FFA2_Pos     (2U)
2743 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
2744 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
2745 #define CAN_FFA1R_FFA3_Pos     (3U)
2746 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
2747 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
2748 #define CAN_FFA1R_FFA4_Pos     (4U)
2749 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
2750 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
2751 #define CAN_FFA1R_FFA5_Pos     (5U)
2752 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
2753 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
2754 #define CAN_FFA1R_FFA6_Pos     (6U)
2755 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
2756 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
2757 #define CAN_FFA1R_FFA7_Pos     (7U)
2758 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
2759 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
2760 #define CAN_FFA1R_FFA8_Pos     (8U)
2761 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
2762 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
2763 #define CAN_FFA1R_FFA9_Pos     (9U)
2764 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
2765 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
2766 #define CAN_FFA1R_FFA10_Pos    (10U)
2767 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
2768 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
2769 #define CAN_FFA1R_FFA11_Pos    (11U)
2770 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
2771 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
2772 #define CAN_FFA1R_FFA12_Pos    (12U)
2773 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
2774 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
2775 #define CAN_FFA1R_FFA13_Pos    (13U)
2776 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
2777 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
2778 
2779 /*******************  Bit definition for CAN_FA1R register  *******************/
2780 #define CAN_FA1R_FACT_Pos      (0U)
2781 #define CAN_FA1R_FACT_Msk      (0x3FFFUL << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
2782 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active    */
2783 #define CAN_FA1R_FACT0_Pos     (0U)
2784 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
2785 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active  */
2786 #define CAN_FA1R_FACT1_Pos     (1U)
2787 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
2788 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active  */
2789 #define CAN_FA1R_FACT2_Pos     (2U)
2790 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
2791 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active  */
2792 #define CAN_FA1R_FACT3_Pos     (3U)
2793 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
2794 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active  */
2795 #define CAN_FA1R_FACT4_Pos     (4U)
2796 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
2797 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active  */
2798 #define CAN_FA1R_FACT5_Pos     (5U)
2799 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
2800 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active  */
2801 #define CAN_FA1R_FACT6_Pos     (6U)
2802 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
2803 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active  */
2804 #define CAN_FA1R_FACT7_Pos     (7U)
2805 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
2806 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active  */
2807 #define CAN_FA1R_FACT8_Pos     (8U)
2808 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
2809 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active  */
2810 #define CAN_FA1R_FACT9_Pos     (9U)
2811 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
2812 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active  */
2813 #define CAN_FA1R_FACT10_Pos    (10U)
2814 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
2815 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
2816 #define CAN_FA1R_FACT11_Pos    (11U)
2817 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
2818 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
2819 #define CAN_FA1R_FACT12_Pos    (12U)
2820 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
2821 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
2822 #define CAN_FA1R_FACT13_Pos    (13U)
2823 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
2824 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
2825 
2826 /*******************  Bit definition for CAN_F0R1 register  *******************/
2827 #define CAN_F0R1_FB0_Pos       (0U)
2828 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
2829 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
2830 #define CAN_F0R1_FB1_Pos       (1U)
2831 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
2832 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
2833 #define CAN_F0R1_FB2_Pos       (2U)
2834 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
2835 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
2836 #define CAN_F0R1_FB3_Pos       (3U)
2837 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
2838 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
2839 #define CAN_F0R1_FB4_Pos       (4U)
2840 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
2841 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
2842 #define CAN_F0R1_FB5_Pos       (5U)
2843 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
2844 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
2845 #define CAN_F0R1_FB6_Pos       (6U)
2846 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
2847 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
2848 #define CAN_F0R1_FB7_Pos       (7U)
2849 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
2850 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
2851 #define CAN_F0R1_FB8_Pos       (8U)
2852 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
2853 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
2854 #define CAN_F0R1_FB9_Pos       (9U)
2855 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
2856 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
2857 #define CAN_F0R1_FB10_Pos      (10U)
2858 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
2859 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
2860 #define CAN_F0R1_FB11_Pos      (11U)
2861 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
2862 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
2863 #define CAN_F0R1_FB12_Pos      (12U)
2864 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
2865 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
2866 #define CAN_F0R1_FB13_Pos      (13U)
2867 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
2868 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
2869 #define CAN_F0R1_FB14_Pos      (14U)
2870 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
2871 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
2872 #define CAN_F0R1_FB15_Pos      (15U)
2873 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
2874 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
2875 #define CAN_F0R1_FB16_Pos      (16U)
2876 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
2877 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2878 #define CAN_F0R1_FB17_Pos      (17U)
2879 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
2880 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2881 #define CAN_F0R1_FB18_Pos      (18U)
2882 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
2883 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2884 #define CAN_F0R1_FB19_Pos      (19U)
2885 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
2886 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2887 #define CAN_F0R1_FB20_Pos      (20U)
2888 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
2889 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2890 #define CAN_F0R1_FB21_Pos      (21U)
2891 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
2892 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2893 #define CAN_F0R1_FB22_Pos      (22U)
2894 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
2895 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2896 #define CAN_F0R1_FB23_Pos      (23U)
2897 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
2898 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2899 #define CAN_F0R1_FB24_Pos      (24U)
2900 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
2901 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2902 #define CAN_F0R1_FB25_Pos      (25U)
2903 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
2904 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2905 #define CAN_F0R1_FB26_Pos      (26U)
2906 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
2907 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2908 #define CAN_F0R1_FB27_Pos      (27U)
2909 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
2910 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2911 #define CAN_F0R1_FB28_Pos      (28U)
2912 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
2913 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2914 #define CAN_F0R1_FB29_Pos      (29U)
2915 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
2916 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
2917 #define CAN_F0R1_FB30_Pos      (30U)
2918 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
2919 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
2920 #define CAN_F0R1_FB31_Pos      (31U)
2921 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
2922 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
2923 
2924 /*******************  Bit definition for CAN_F1R1 register  *******************/
2925 #define CAN_F1R1_FB0_Pos       (0U)
2926 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
2927 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
2928 #define CAN_F1R1_FB1_Pos       (1U)
2929 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
2930 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
2931 #define CAN_F1R1_FB2_Pos       (2U)
2932 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
2933 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
2934 #define CAN_F1R1_FB3_Pos       (3U)
2935 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
2936 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
2937 #define CAN_F1R1_FB4_Pos       (4U)
2938 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
2939 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
2940 #define CAN_F1R1_FB5_Pos       (5U)
2941 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
2942 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
2943 #define CAN_F1R1_FB6_Pos       (6U)
2944 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
2945 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
2946 #define CAN_F1R1_FB7_Pos       (7U)
2947 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
2948 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
2949 #define CAN_F1R1_FB8_Pos       (8U)
2950 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
2951 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
2952 #define CAN_F1R1_FB9_Pos       (9U)
2953 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
2954 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
2955 #define CAN_F1R1_FB10_Pos      (10U)
2956 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
2957 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
2958 #define CAN_F1R1_FB11_Pos      (11U)
2959 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
2960 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
2961 #define CAN_F1R1_FB12_Pos      (12U)
2962 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
2963 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
2964 #define CAN_F1R1_FB13_Pos      (13U)
2965 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
2966 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
2967 #define CAN_F1R1_FB14_Pos      (14U)
2968 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
2969 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
2970 #define CAN_F1R1_FB15_Pos      (15U)
2971 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
2972 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
2973 #define CAN_F1R1_FB16_Pos      (16U)
2974 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
2975 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
2976 #define CAN_F1R1_FB17_Pos      (17U)
2977 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
2978 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
2979 #define CAN_F1R1_FB18_Pos      (18U)
2980 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
2981 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
2982 #define CAN_F1R1_FB19_Pos      (19U)
2983 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
2984 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
2985 #define CAN_F1R1_FB20_Pos      (20U)
2986 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
2987 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
2988 #define CAN_F1R1_FB21_Pos      (21U)
2989 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
2990 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
2991 #define CAN_F1R1_FB22_Pos      (22U)
2992 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
2993 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
2994 #define CAN_F1R1_FB23_Pos      (23U)
2995 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
2996 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
2997 #define CAN_F1R1_FB24_Pos      (24U)
2998 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
2999 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
3000 #define CAN_F1R1_FB25_Pos      (25U)
3001 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
3002 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
3003 #define CAN_F1R1_FB26_Pos      (26U)
3004 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
3005 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
3006 #define CAN_F1R1_FB27_Pos      (27U)
3007 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
3008 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
3009 #define CAN_F1R1_FB28_Pos      (28U)
3010 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
3011 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
3012 #define CAN_F1R1_FB29_Pos      (29U)
3013 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
3014 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
3015 #define CAN_F1R1_FB30_Pos      (30U)
3016 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
3017 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
3018 #define CAN_F1R1_FB31_Pos      (31U)
3019 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
3020 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
3021 
3022 /*******************  Bit definition for CAN_F2R1 register  *******************/
3023 #define CAN_F2R1_FB0_Pos       (0U)
3024 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
3025 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
3026 #define CAN_F2R1_FB1_Pos       (1U)
3027 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
3028 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
3029 #define CAN_F2R1_FB2_Pos       (2U)
3030 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
3031 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
3032 #define CAN_F2R1_FB3_Pos       (3U)
3033 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
3034 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
3035 #define CAN_F2R1_FB4_Pos       (4U)
3036 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
3037 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
3038 #define CAN_F2R1_FB5_Pos       (5U)
3039 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
3040 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
3041 #define CAN_F2R1_FB6_Pos       (6U)
3042 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
3043 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
3044 #define CAN_F2R1_FB7_Pos       (7U)
3045 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
3046 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
3047 #define CAN_F2R1_FB8_Pos       (8U)
3048 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
3049 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
3050 #define CAN_F2R1_FB9_Pos       (9U)
3051 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
3052 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
3053 #define CAN_F2R1_FB10_Pos      (10U)
3054 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
3055 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
3056 #define CAN_F2R1_FB11_Pos      (11U)
3057 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
3058 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
3059 #define CAN_F2R1_FB12_Pos      (12U)
3060 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
3061 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
3062 #define CAN_F2R1_FB13_Pos      (13U)
3063 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
3064 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
3065 #define CAN_F2R1_FB14_Pos      (14U)
3066 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
3067 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
3068 #define CAN_F2R1_FB15_Pos      (15U)
3069 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
3070 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
3071 #define CAN_F2R1_FB16_Pos      (16U)
3072 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
3073 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
3074 #define CAN_F2R1_FB17_Pos      (17U)
3075 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
3076 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
3077 #define CAN_F2R1_FB18_Pos      (18U)
3078 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
3079 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
3080 #define CAN_F2R1_FB19_Pos      (19U)
3081 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
3082 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
3083 #define CAN_F2R1_FB20_Pos      (20U)
3084 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
3085 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
3086 #define CAN_F2R1_FB21_Pos      (21U)
3087 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
3088 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
3089 #define CAN_F2R1_FB22_Pos      (22U)
3090 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
3091 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
3092 #define CAN_F2R1_FB23_Pos      (23U)
3093 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
3094 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
3095 #define CAN_F2R1_FB24_Pos      (24U)
3096 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
3097 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
3098 #define CAN_F2R1_FB25_Pos      (25U)
3099 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
3100 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
3101 #define CAN_F2R1_FB26_Pos      (26U)
3102 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
3103 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
3104 #define CAN_F2R1_FB27_Pos      (27U)
3105 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
3106 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
3107 #define CAN_F2R1_FB28_Pos      (28U)
3108 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
3109 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
3110 #define CAN_F2R1_FB29_Pos      (29U)
3111 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
3112 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
3113 #define CAN_F2R1_FB30_Pos      (30U)
3114 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
3115 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
3116 #define CAN_F2R1_FB31_Pos      (31U)
3117 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
3118 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
3119 
3120 /*******************  Bit definition for CAN_F3R1 register  *******************/
3121 #define CAN_F3R1_FB0_Pos       (0U)
3122 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
3123 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
3124 #define CAN_F3R1_FB1_Pos       (1U)
3125 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
3126 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
3127 #define CAN_F3R1_FB2_Pos       (2U)
3128 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
3129 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
3130 #define CAN_F3R1_FB3_Pos       (3U)
3131 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
3132 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
3133 #define CAN_F3R1_FB4_Pos       (4U)
3134 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
3135 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
3136 #define CAN_F3R1_FB5_Pos       (5U)
3137 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
3138 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3139 #define CAN_F3R1_FB6_Pos       (6U)
3140 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
3141 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3142 #define CAN_F3R1_FB7_Pos       (7U)
3143 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
3144 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3145 #define CAN_F3R1_FB8_Pos       (8U)
3146 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
3147 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3148 #define CAN_F3R1_FB9_Pos       (9U)
3149 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3150 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3151 #define CAN_F3R1_FB10_Pos      (10U)
3152 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3153 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3154 #define CAN_F3R1_FB11_Pos      (11U)
3155 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3156 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3157 #define CAN_F3R1_FB12_Pos      (12U)
3158 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3159 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3160 #define CAN_F3R1_FB13_Pos      (13U)
3161 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3162 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3163 #define CAN_F3R1_FB14_Pos      (14U)
3164 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3165 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3166 #define CAN_F3R1_FB15_Pos      (15U)
3167 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3168 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3169 #define CAN_F3R1_FB16_Pos      (16U)
3170 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3171 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3172 #define CAN_F3R1_FB17_Pos      (17U)
3173 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3174 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3175 #define CAN_F3R1_FB18_Pos      (18U)
3176 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3177 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3178 #define CAN_F3R1_FB19_Pos      (19U)
3179 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3180 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3181 #define CAN_F3R1_FB20_Pos      (20U)
3182 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3183 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3184 #define CAN_F3R1_FB21_Pos      (21U)
3185 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3186 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3187 #define CAN_F3R1_FB22_Pos      (22U)
3188 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3189 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3190 #define CAN_F3R1_FB23_Pos      (23U)
3191 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3192 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3193 #define CAN_F3R1_FB24_Pos      (24U)
3194 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3195 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3196 #define CAN_F3R1_FB25_Pos      (25U)
3197 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3198 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3199 #define CAN_F3R1_FB26_Pos      (26U)
3200 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3201 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3202 #define CAN_F3R1_FB27_Pos      (27U)
3203 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3204 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3205 #define CAN_F3R1_FB28_Pos      (28U)
3206 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3207 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3208 #define CAN_F3R1_FB29_Pos      (29U)
3209 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3210 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3211 #define CAN_F3R1_FB30_Pos      (30U)
3212 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3213 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3214 #define CAN_F3R1_FB31_Pos      (31U)
3215 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3216 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3217 
3218 /*******************  Bit definition for CAN_F4R1 register  *******************/
3219 #define CAN_F4R1_FB0_Pos       (0U)
3220 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3221 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3222 #define CAN_F4R1_FB1_Pos       (1U)
3223 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3224 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3225 #define CAN_F4R1_FB2_Pos       (2U)
3226 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3227 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3228 #define CAN_F4R1_FB3_Pos       (3U)
3229 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3230 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3231 #define CAN_F4R1_FB4_Pos       (4U)
3232 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3233 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3234 #define CAN_F4R1_FB5_Pos       (5U)
3235 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3236 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3237 #define CAN_F4R1_FB6_Pos       (6U)
3238 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3239 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3240 #define CAN_F4R1_FB7_Pos       (7U)
3241 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3242 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3243 #define CAN_F4R1_FB8_Pos       (8U)
3244 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3245 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3246 #define CAN_F4R1_FB9_Pos       (9U)
3247 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3248 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3249 #define CAN_F4R1_FB10_Pos      (10U)
3250 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3251 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3252 #define CAN_F4R1_FB11_Pos      (11U)
3253 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3254 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3255 #define CAN_F4R1_FB12_Pos      (12U)
3256 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3257 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3258 #define CAN_F4R1_FB13_Pos      (13U)
3259 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3260 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3261 #define CAN_F4R1_FB14_Pos      (14U)
3262 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3263 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3264 #define CAN_F4R1_FB15_Pos      (15U)
3265 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3266 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3267 #define CAN_F4R1_FB16_Pos      (16U)
3268 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3269 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3270 #define CAN_F4R1_FB17_Pos      (17U)
3271 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3272 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3273 #define CAN_F4R1_FB18_Pos      (18U)
3274 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3275 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3276 #define CAN_F4R1_FB19_Pos      (19U)
3277 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3278 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3279 #define CAN_F4R1_FB20_Pos      (20U)
3280 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3281 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3282 #define CAN_F4R1_FB21_Pos      (21U)
3283 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3284 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3285 #define CAN_F4R1_FB22_Pos      (22U)
3286 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3287 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3288 #define CAN_F4R1_FB23_Pos      (23U)
3289 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3290 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3291 #define CAN_F4R1_FB24_Pos      (24U)
3292 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3293 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3294 #define CAN_F4R1_FB25_Pos      (25U)
3295 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3296 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3297 #define CAN_F4R1_FB26_Pos      (26U)
3298 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3299 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3300 #define CAN_F4R1_FB27_Pos      (27U)
3301 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
3302 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3303 #define CAN_F4R1_FB28_Pos      (28U)
3304 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
3305 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3306 #define CAN_F4R1_FB29_Pos      (29U)
3307 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
3308 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3309 #define CAN_F4R1_FB30_Pos      (30U)
3310 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
3311 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3312 #define CAN_F4R1_FB31_Pos      (31U)
3313 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
3314 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3315 
3316 /*******************  Bit definition for CAN_F5R1 register  *******************/
3317 #define CAN_F5R1_FB0_Pos       (0U)
3318 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
3319 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3320 #define CAN_F5R1_FB1_Pos       (1U)
3321 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
3322 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3323 #define CAN_F5R1_FB2_Pos       (2U)
3324 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
3325 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3326 #define CAN_F5R1_FB3_Pos       (3U)
3327 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
3328 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3329 #define CAN_F5R1_FB4_Pos       (4U)
3330 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
3331 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3332 #define CAN_F5R1_FB5_Pos       (5U)
3333 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
3334 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3335 #define CAN_F5R1_FB6_Pos       (6U)
3336 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
3337 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3338 #define CAN_F5R1_FB7_Pos       (7U)
3339 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
3340 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3341 #define CAN_F5R1_FB8_Pos       (8U)
3342 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
3343 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3344 #define CAN_F5R1_FB9_Pos       (9U)
3345 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
3346 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3347 #define CAN_F5R1_FB10_Pos      (10U)
3348 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
3349 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3350 #define CAN_F5R1_FB11_Pos      (11U)
3351 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
3352 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3353 #define CAN_F5R1_FB12_Pos      (12U)
3354 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
3355 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3356 #define CAN_F5R1_FB13_Pos      (13U)
3357 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
3358 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3359 #define CAN_F5R1_FB14_Pos      (14U)
3360 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
3361 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3362 #define CAN_F5R1_FB15_Pos      (15U)
3363 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
3364 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3365 #define CAN_F5R1_FB16_Pos      (16U)
3366 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
3367 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3368 #define CAN_F5R1_FB17_Pos      (17U)
3369 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
3370 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3371 #define CAN_F5R1_FB18_Pos      (18U)
3372 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
3373 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3374 #define CAN_F5R1_FB19_Pos      (19U)
3375 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
3376 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3377 #define CAN_F5R1_FB20_Pos      (20U)
3378 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
3379 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3380 #define CAN_F5R1_FB21_Pos      (21U)
3381 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
3382 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3383 #define CAN_F5R1_FB22_Pos      (22U)
3384 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
3385 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3386 #define CAN_F5R1_FB23_Pos      (23U)
3387 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
3388 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3389 #define CAN_F5R1_FB24_Pos      (24U)
3390 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
3391 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3392 #define CAN_F5R1_FB25_Pos      (25U)
3393 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
3394 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3395 #define CAN_F5R1_FB26_Pos      (26U)
3396 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
3397 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3398 #define CAN_F5R1_FB27_Pos      (27U)
3399 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
3400 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3401 #define CAN_F5R1_FB28_Pos      (28U)
3402 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
3403 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3404 #define CAN_F5R1_FB29_Pos      (29U)
3405 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
3406 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3407 #define CAN_F5R1_FB30_Pos      (30U)
3408 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
3409 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3410 #define CAN_F5R1_FB31_Pos      (31U)
3411 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
3412 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3413 
3414 /*******************  Bit definition for CAN_F6R1 register  *******************/
3415 #define CAN_F6R1_FB0_Pos       (0U)
3416 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
3417 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3418 #define CAN_F6R1_FB1_Pos       (1U)
3419 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
3420 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3421 #define CAN_F6R1_FB2_Pos       (2U)
3422 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
3423 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3424 #define CAN_F6R1_FB3_Pos       (3U)
3425 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
3426 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3427 #define CAN_F6R1_FB4_Pos       (4U)
3428 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
3429 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3430 #define CAN_F6R1_FB5_Pos       (5U)
3431 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
3432 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3433 #define CAN_F6R1_FB6_Pos       (6U)
3434 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
3435 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3436 #define CAN_F6R1_FB7_Pos       (7U)
3437 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
3438 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3439 #define CAN_F6R1_FB8_Pos       (8U)
3440 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
3441 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3442 #define CAN_F6R1_FB9_Pos       (9U)
3443 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
3444 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3445 #define CAN_F6R1_FB10_Pos      (10U)
3446 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
3447 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3448 #define CAN_F6R1_FB11_Pos      (11U)
3449 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
3450 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3451 #define CAN_F6R1_FB12_Pos      (12U)
3452 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
3453 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3454 #define CAN_F6R1_FB13_Pos      (13U)
3455 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
3456 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3457 #define CAN_F6R1_FB14_Pos      (14U)
3458 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
3459 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3460 #define CAN_F6R1_FB15_Pos      (15U)
3461 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
3462 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3463 #define CAN_F6R1_FB16_Pos      (16U)
3464 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
3465 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3466 #define CAN_F6R1_FB17_Pos      (17U)
3467 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
3468 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3469 #define CAN_F6R1_FB18_Pos      (18U)
3470 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
3471 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3472 #define CAN_F6R1_FB19_Pos      (19U)
3473 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
3474 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3475 #define CAN_F6R1_FB20_Pos      (20U)
3476 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
3477 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3478 #define CAN_F6R1_FB21_Pos      (21U)
3479 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
3480 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3481 #define CAN_F6R1_FB22_Pos      (22U)
3482 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
3483 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3484 #define CAN_F6R1_FB23_Pos      (23U)
3485 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
3486 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3487 #define CAN_F6R1_FB24_Pos      (24U)
3488 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
3489 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3490 #define CAN_F6R1_FB25_Pos      (25U)
3491 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
3492 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3493 #define CAN_F6R1_FB26_Pos      (26U)
3494 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
3495 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3496 #define CAN_F6R1_FB27_Pos      (27U)
3497 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
3498 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3499 #define CAN_F6R1_FB28_Pos      (28U)
3500 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
3501 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3502 #define CAN_F6R1_FB29_Pos      (29U)
3503 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
3504 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3505 #define CAN_F6R1_FB30_Pos      (30U)
3506 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
3507 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3508 #define CAN_F6R1_FB31_Pos      (31U)
3509 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
3510 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3511 
3512 /*******************  Bit definition for CAN_F7R1 register  *******************/
3513 #define CAN_F7R1_FB0_Pos       (0U)
3514 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
3515 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3516 #define CAN_F7R1_FB1_Pos       (1U)
3517 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
3518 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3519 #define CAN_F7R1_FB2_Pos       (2U)
3520 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
3521 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3522 #define CAN_F7R1_FB3_Pos       (3U)
3523 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
3524 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3525 #define CAN_F7R1_FB4_Pos       (4U)
3526 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
3527 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3528 #define CAN_F7R1_FB5_Pos       (5U)
3529 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
3530 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3531 #define CAN_F7R1_FB6_Pos       (6U)
3532 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
3533 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3534 #define CAN_F7R1_FB7_Pos       (7U)
3535 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
3536 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3537 #define CAN_F7R1_FB8_Pos       (8U)
3538 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
3539 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3540 #define CAN_F7R1_FB9_Pos       (9U)
3541 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
3542 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
3543 #define CAN_F7R1_FB10_Pos      (10U)
3544 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
3545 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
3546 #define CAN_F7R1_FB11_Pos      (11U)
3547 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
3548 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
3549 #define CAN_F7R1_FB12_Pos      (12U)
3550 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
3551 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
3552 #define CAN_F7R1_FB13_Pos      (13U)
3553 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
3554 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
3555 #define CAN_F7R1_FB14_Pos      (14U)
3556 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
3557 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
3558 #define CAN_F7R1_FB15_Pos      (15U)
3559 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
3560 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
3561 #define CAN_F7R1_FB16_Pos      (16U)
3562 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
3563 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
3564 #define CAN_F7R1_FB17_Pos      (17U)
3565 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
3566 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
3567 #define CAN_F7R1_FB18_Pos      (18U)
3568 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
3569 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
3570 #define CAN_F7R1_FB19_Pos      (19U)
3571 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
3572 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
3573 #define CAN_F7R1_FB20_Pos      (20U)
3574 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
3575 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
3576 #define CAN_F7R1_FB21_Pos      (21U)
3577 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
3578 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
3579 #define CAN_F7R1_FB22_Pos      (22U)
3580 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
3581 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
3582 #define CAN_F7R1_FB23_Pos      (23U)
3583 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
3584 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
3585 #define CAN_F7R1_FB24_Pos      (24U)
3586 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
3587 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
3588 #define CAN_F7R1_FB25_Pos      (25U)
3589 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
3590 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
3591 #define CAN_F7R1_FB26_Pos      (26U)
3592 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
3593 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
3594 #define CAN_F7R1_FB27_Pos      (27U)
3595 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
3596 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
3597 #define CAN_F7R1_FB28_Pos      (28U)
3598 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
3599 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
3600 #define CAN_F7R1_FB29_Pos      (29U)
3601 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
3602 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
3603 #define CAN_F7R1_FB30_Pos      (30U)
3604 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
3605 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
3606 #define CAN_F7R1_FB31_Pos      (31U)
3607 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
3608 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
3609 
3610 /*******************  Bit definition for CAN_F8R1 register  *******************/
3611 #define CAN_F8R1_FB0_Pos       (0U)
3612 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
3613 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
3614 #define CAN_F8R1_FB1_Pos       (1U)
3615 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
3616 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
3617 #define CAN_F8R1_FB2_Pos       (2U)
3618 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
3619 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
3620 #define CAN_F8R1_FB3_Pos       (3U)
3621 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
3622 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
3623 #define CAN_F8R1_FB4_Pos       (4U)
3624 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
3625 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
3626 #define CAN_F8R1_FB5_Pos       (5U)
3627 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
3628 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
3629 #define CAN_F8R1_FB6_Pos       (6U)
3630 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
3631 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
3632 #define CAN_F8R1_FB7_Pos       (7U)
3633 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
3634 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
3635 #define CAN_F8R1_FB8_Pos       (8U)
3636 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
3637 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
3638 #define CAN_F8R1_FB9_Pos       (9U)
3639 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
3640 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
3641 #define CAN_F8R1_FB10_Pos      (10U)
3642 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
3643 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
3644 #define CAN_F8R1_FB11_Pos      (11U)
3645 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
3646 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
3647 #define CAN_F8R1_FB12_Pos      (12U)
3648 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
3649 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
3650 #define CAN_F8R1_FB13_Pos      (13U)
3651 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
3652 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
3653 #define CAN_F8R1_FB14_Pos      (14U)
3654 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
3655 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
3656 #define CAN_F8R1_FB15_Pos      (15U)
3657 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
3658 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
3659 #define CAN_F8R1_FB16_Pos      (16U)
3660 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
3661 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
3662 #define CAN_F8R1_FB17_Pos      (17U)
3663 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
3664 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
3665 #define CAN_F8R1_FB18_Pos      (18U)
3666 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
3667 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
3668 #define CAN_F8R1_FB19_Pos      (19U)
3669 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
3670 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
3671 #define CAN_F8R1_FB20_Pos      (20U)
3672 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
3673 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
3674 #define CAN_F8R1_FB21_Pos      (21U)
3675 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
3676 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
3677 #define CAN_F8R1_FB22_Pos      (22U)
3678 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
3679 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
3680 #define CAN_F8R1_FB23_Pos      (23U)
3681 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
3682 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
3683 #define CAN_F8R1_FB24_Pos      (24U)
3684 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
3685 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
3686 #define CAN_F8R1_FB25_Pos      (25U)
3687 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
3688 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
3689 #define CAN_F8R1_FB26_Pos      (26U)
3690 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
3691 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
3692 #define CAN_F8R1_FB27_Pos      (27U)
3693 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
3694 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
3695 #define CAN_F8R1_FB28_Pos      (28U)
3696 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
3697 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
3698 #define CAN_F8R1_FB29_Pos      (29U)
3699 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
3700 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
3701 #define CAN_F8R1_FB30_Pos      (30U)
3702 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
3703 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
3704 #define CAN_F8R1_FB31_Pos      (31U)
3705 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
3706 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
3707 
3708 /*******************  Bit definition for CAN_F9R1 register  *******************/
3709 #define CAN_F9R1_FB0_Pos       (0U)
3710 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
3711 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
3712 #define CAN_F9R1_FB1_Pos       (1U)
3713 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
3714 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
3715 #define CAN_F9R1_FB2_Pos       (2U)
3716 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
3717 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
3718 #define CAN_F9R1_FB3_Pos       (3U)
3719 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
3720 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
3721 #define CAN_F9R1_FB4_Pos       (4U)
3722 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
3723 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
3724 #define CAN_F9R1_FB5_Pos       (5U)
3725 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
3726 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
3727 #define CAN_F9R1_FB6_Pos       (6U)
3728 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
3729 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
3730 #define CAN_F9R1_FB7_Pos       (7U)
3731 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
3732 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
3733 #define CAN_F9R1_FB8_Pos       (8U)
3734 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
3735 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
3736 #define CAN_F9R1_FB9_Pos       (9U)
3737 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
3738 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
3739 #define CAN_F9R1_FB10_Pos      (10U)
3740 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
3741 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
3742 #define CAN_F9R1_FB11_Pos      (11U)
3743 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
3744 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
3745 #define CAN_F9R1_FB12_Pos      (12U)
3746 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
3747 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
3748 #define CAN_F9R1_FB13_Pos      (13U)
3749 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
3750 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
3751 #define CAN_F9R1_FB14_Pos      (14U)
3752 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
3753 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
3754 #define CAN_F9R1_FB15_Pos      (15U)
3755 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
3756 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
3757 #define CAN_F9R1_FB16_Pos      (16U)
3758 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
3759 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
3760 #define CAN_F9R1_FB17_Pos      (17U)
3761 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
3762 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
3763 #define CAN_F9R1_FB18_Pos      (18U)
3764 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
3765 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
3766 #define CAN_F9R1_FB19_Pos      (19U)
3767 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
3768 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
3769 #define CAN_F9R1_FB20_Pos      (20U)
3770 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
3771 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
3772 #define CAN_F9R1_FB21_Pos      (21U)
3773 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
3774 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
3775 #define CAN_F9R1_FB22_Pos      (22U)
3776 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
3777 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
3778 #define CAN_F9R1_FB23_Pos      (23U)
3779 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
3780 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
3781 #define CAN_F9R1_FB24_Pos      (24U)
3782 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
3783 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
3784 #define CAN_F9R1_FB25_Pos      (25U)
3785 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
3786 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
3787 #define CAN_F9R1_FB26_Pos      (26U)
3788 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
3789 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
3790 #define CAN_F9R1_FB27_Pos      (27U)
3791 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
3792 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
3793 #define CAN_F9R1_FB28_Pos      (28U)
3794 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
3795 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
3796 #define CAN_F9R1_FB29_Pos      (29U)
3797 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
3798 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
3799 #define CAN_F9R1_FB30_Pos      (30U)
3800 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
3801 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
3802 #define CAN_F9R1_FB31_Pos      (31U)
3803 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
3804 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
3805 
3806 /*******************  Bit definition for CAN_F10R1 register  ******************/
3807 #define CAN_F10R1_FB0_Pos      (0U)
3808 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
3809 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
3810 #define CAN_F10R1_FB1_Pos      (1U)
3811 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
3812 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
3813 #define CAN_F10R1_FB2_Pos      (2U)
3814 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
3815 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
3816 #define CAN_F10R1_FB3_Pos      (3U)
3817 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
3818 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
3819 #define CAN_F10R1_FB4_Pos      (4U)
3820 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
3821 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
3822 #define CAN_F10R1_FB5_Pos      (5U)
3823 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
3824 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
3825 #define CAN_F10R1_FB6_Pos      (6U)
3826 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
3827 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
3828 #define CAN_F10R1_FB7_Pos      (7U)
3829 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
3830 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
3831 #define CAN_F10R1_FB8_Pos      (8U)
3832 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
3833 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
3834 #define CAN_F10R1_FB9_Pos      (9U)
3835 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
3836 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
3837 #define CAN_F10R1_FB10_Pos     (10U)
3838 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
3839 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
3840 #define CAN_F10R1_FB11_Pos     (11U)
3841 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
3842 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
3843 #define CAN_F10R1_FB12_Pos     (12U)
3844 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
3845 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
3846 #define CAN_F10R1_FB13_Pos     (13U)
3847 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
3848 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
3849 #define CAN_F10R1_FB14_Pos     (14U)
3850 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
3851 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
3852 #define CAN_F10R1_FB15_Pos     (15U)
3853 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
3854 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
3855 #define CAN_F10R1_FB16_Pos     (16U)
3856 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
3857 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
3858 #define CAN_F10R1_FB17_Pos     (17U)
3859 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
3860 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
3861 #define CAN_F10R1_FB18_Pos     (18U)
3862 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
3863 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
3864 #define CAN_F10R1_FB19_Pos     (19U)
3865 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
3866 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
3867 #define CAN_F10R1_FB20_Pos     (20U)
3868 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
3869 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
3870 #define CAN_F10R1_FB21_Pos     (21U)
3871 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
3872 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
3873 #define CAN_F10R1_FB22_Pos     (22U)
3874 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
3875 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3876 #define CAN_F10R1_FB23_Pos     (23U)
3877 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
3878 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3879 #define CAN_F10R1_FB24_Pos     (24U)
3880 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
3881 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3882 #define CAN_F10R1_FB25_Pos     (25U)
3883 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
3884 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3885 #define CAN_F10R1_FB26_Pos     (26U)
3886 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
3887 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3888 #define CAN_F10R1_FB27_Pos     (27U)
3889 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
3890 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3891 #define CAN_F10R1_FB28_Pos     (28U)
3892 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
3893 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3894 #define CAN_F10R1_FB29_Pos     (29U)
3895 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
3896 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3897 #define CAN_F10R1_FB30_Pos     (30U)
3898 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
3899 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3900 #define CAN_F10R1_FB31_Pos     (31U)
3901 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
3902 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3903 
3904 /*******************  Bit definition for CAN_F11R1 register  ******************/
3905 #define CAN_F11R1_FB0_Pos      (0U)
3906 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
3907 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3908 #define CAN_F11R1_FB1_Pos      (1U)
3909 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
3910 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3911 #define CAN_F11R1_FB2_Pos      (2U)
3912 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
3913 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3914 #define CAN_F11R1_FB3_Pos      (3U)
3915 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
3916 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
3917 #define CAN_F11R1_FB4_Pos      (4U)
3918 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
3919 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
3920 #define CAN_F11R1_FB5_Pos      (5U)
3921 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
3922 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
3923 #define CAN_F11R1_FB6_Pos      (6U)
3924 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
3925 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
3926 #define CAN_F11R1_FB7_Pos      (7U)
3927 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
3928 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
3929 #define CAN_F11R1_FB8_Pos      (8U)
3930 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
3931 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
3932 #define CAN_F11R1_FB9_Pos      (9U)
3933 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
3934 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
3935 #define CAN_F11R1_FB10_Pos     (10U)
3936 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
3937 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
3938 #define CAN_F11R1_FB11_Pos     (11U)
3939 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
3940 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
3941 #define CAN_F11R1_FB12_Pos     (12U)
3942 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
3943 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
3944 #define CAN_F11R1_FB13_Pos     (13U)
3945 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
3946 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
3947 #define CAN_F11R1_FB14_Pos     (14U)
3948 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
3949 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
3950 #define CAN_F11R1_FB15_Pos     (15U)
3951 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
3952 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
3953 #define CAN_F11R1_FB16_Pos     (16U)
3954 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
3955 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
3956 #define CAN_F11R1_FB17_Pos     (17U)
3957 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
3958 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
3959 #define CAN_F11R1_FB18_Pos     (18U)
3960 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
3961 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
3962 #define CAN_F11R1_FB19_Pos     (19U)
3963 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
3964 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
3965 #define CAN_F11R1_FB20_Pos     (20U)
3966 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
3967 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
3968 #define CAN_F11R1_FB21_Pos     (21U)
3969 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
3970 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
3971 #define CAN_F11R1_FB22_Pos     (22U)
3972 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
3973 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
3974 #define CAN_F11R1_FB23_Pos     (23U)
3975 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
3976 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
3977 #define CAN_F11R1_FB24_Pos     (24U)
3978 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
3979 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
3980 #define CAN_F11R1_FB25_Pos     (25U)
3981 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
3982 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
3983 #define CAN_F11R1_FB26_Pos     (26U)
3984 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
3985 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
3986 #define CAN_F11R1_FB27_Pos     (27U)
3987 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
3988 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
3989 #define CAN_F11R1_FB28_Pos     (28U)
3990 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
3991 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
3992 #define CAN_F11R1_FB29_Pos     (29U)
3993 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
3994 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
3995 #define CAN_F11R1_FB30_Pos     (30U)
3996 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
3997 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
3998 #define CAN_F11R1_FB31_Pos     (31U)
3999 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
4000 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
4001 
4002 /*******************  Bit definition for CAN_F12R1 register  ******************/
4003 #define CAN_F12R1_FB0_Pos      (0U)
4004 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
4005 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
4006 #define CAN_F12R1_FB1_Pos      (1U)
4007 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
4008 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
4009 #define CAN_F12R1_FB2_Pos      (2U)
4010 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
4011 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
4012 #define CAN_F12R1_FB3_Pos      (3U)
4013 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
4014 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
4015 #define CAN_F12R1_FB4_Pos      (4U)
4016 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
4017 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
4018 #define CAN_F12R1_FB5_Pos      (5U)
4019 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
4020 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
4021 #define CAN_F12R1_FB6_Pos      (6U)
4022 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
4023 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
4024 #define CAN_F12R1_FB7_Pos      (7U)
4025 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
4026 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
4027 #define CAN_F12R1_FB8_Pos      (8U)
4028 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
4029 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
4030 #define CAN_F12R1_FB9_Pos      (9U)
4031 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
4032 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
4033 #define CAN_F12R1_FB10_Pos     (10U)
4034 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
4035 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
4036 #define CAN_F12R1_FB11_Pos     (11U)
4037 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
4038 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
4039 #define CAN_F12R1_FB12_Pos     (12U)
4040 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
4041 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
4042 #define CAN_F12R1_FB13_Pos     (13U)
4043 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
4044 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
4045 #define CAN_F12R1_FB14_Pos     (14U)
4046 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
4047 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
4048 #define CAN_F12R1_FB15_Pos     (15U)
4049 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
4050 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
4051 #define CAN_F12R1_FB16_Pos     (16U)
4052 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
4053 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
4054 #define CAN_F12R1_FB17_Pos     (17U)
4055 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
4056 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
4057 #define CAN_F12R1_FB18_Pos     (18U)
4058 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
4059 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
4060 #define CAN_F12R1_FB19_Pos     (19U)
4061 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
4062 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
4063 #define CAN_F12R1_FB20_Pos     (20U)
4064 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
4065 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
4066 #define CAN_F12R1_FB21_Pos     (21U)
4067 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
4068 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
4069 #define CAN_F12R1_FB22_Pos     (22U)
4070 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
4071 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
4072 #define CAN_F12R1_FB23_Pos     (23U)
4073 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
4074 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
4075 #define CAN_F12R1_FB24_Pos     (24U)
4076 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
4077 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
4078 #define CAN_F12R1_FB25_Pos     (25U)
4079 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
4080 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
4081 #define CAN_F12R1_FB26_Pos     (26U)
4082 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
4083 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
4084 #define CAN_F12R1_FB27_Pos     (27U)
4085 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
4086 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
4087 #define CAN_F12R1_FB28_Pos     (28U)
4088 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
4089 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
4090 #define CAN_F12R1_FB29_Pos     (29U)
4091 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
4092 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
4093 #define CAN_F12R1_FB30_Pos     (30U)
4094 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
4095 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
4096 #define CAN_F12R1_FB31_Pos     (31U)
4097 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
4098 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
4099 
4100 /*******************  Bit definition for CAN_F13R1 register  ******************/
4101 #define CAN_F13R1_FB0_Pos      (0U)
4102 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
4103 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
4104 #define CAN_F13R1_FB1_Pos      (1U)
4105 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
4106 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
4107 #define CAN_F13R1_FB2_Pos      (2U)
4108 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
4109 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
4110 #define CAN_F13R1_FB3_Pos      (3U)
4111 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
4112 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
4113 #define CAN_F13R1_FB4_Pos      (4U)
4114 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
4115 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
4116 #define CAN_F13R1_FB5_Pos      (5U)
4117 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
4118 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
4119 #define CAN_F13R1_FB6_Pos      (6U)
4120 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
4121 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
4122 #define CAN_F13R1_FB7_Pos      (7U)
4123 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
4124 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
4125 #define CAN_F13R1_FB8_Pos      (8U)
4126 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
4127 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
4128 #define CAN_F13R1_FB9_Pos      (9U)
4129 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
4130 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
4131 #define CAN_F13R1_FB10_Pos     (10U)
4132 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
4133 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
4134 #define CAN_F13R1_FB11_Pos     (11U)
4135 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
4136 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
4137 #define CAN_F13R1_FB12_Pos     (12U)
4138 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
4139 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4140 #define CAN_F13R1_FB13_Pos     (13U)
4141 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
4142 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4143 #define CAN_F13R1_FB14_Pos     (14U)
4144 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
4145 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4146 #define CAN_F13R1_FB15_Pos     (15U)
4147 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
4148 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4149 #define CAN_F13R1_FB16_Pos     (16U)
4150 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4151 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4152 #define CAN_F13R1_FB17_Pos     (17U)
4153 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4154 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4155 #define CAN_F13R1_FB18_Pos     (18U)
4156 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4157 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4158 #define CAN_F13R1_FB19_Pos     (19U)
4159 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4160 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4161 #define CAN_F13R1_FB20_Pos     (20U)
4162 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4163 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4164 #define CAN_F13R1_FB21_Pos     (21U)
4165 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4166 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4167 #define CAN_F13R1_FB22_Pos     (22U)
4168 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4169 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4170 #define CAN_F13R1_FB23_Pos     (23U)
4171 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4172 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4173 #define CAN_F13R1_FB24_Pos     (24U)
4174 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4175 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4176 #define CAN_F13R1_FB25_Pos     (25U)
4177 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4178 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4179 #define CAN_F13R1_FB26_Pos     (26U)
4180 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4181 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4182 #define CAN_F13R1_FB27_Pos     (27U)
4183 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4184 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4185 #define CAN_F13R1_FB28_Pos     (28U)
4186 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4187 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4188 #define CAN_F13R1_FB29_Pos     (29U)
4189 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4190 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4191 #define CAN_F13R1_FB30_Pos     (30U)
4192 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4193 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4194 #define CAN_F13R1_FB31_Pos     (31U)
4195 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4196 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4197 
4198 /*******************  Bit definition for CAN_F0R2 register  *******************/
4199 #define CAN_F0R2_FB0_Pos       (0U)
4200 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4201 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4202 #define CAN_F0R2_FB1_Pos       (1U)
4203 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4204 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4205 #define CAN_F0R2_FB2_Pos       (2U)
4206 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4207 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4208 #define CAN_F0R2_FB3_Pos       (3U)
4209 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4210 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4211 #define CAN_F0R2_FB4_Pos       (4U)
4212 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4213 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4214 #define CAN_F0R2_FB5_Pos       (5U)
4215 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4216 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4217 #define CAN_F0R2_FB6_Pos       (6U)
4218 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4219 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4220 #define CAN_F0R2_FB7_Pos       (7U)
4221 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4222 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4223 #define CAN_F0R2_FB8_Pos       (8U)
4224 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4225 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4226 #define CAN_F0R2_FB9_Pos       (9U)
4227 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4228 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4229 #define CAN_F0R2_FB10_Pos      (10U)
4230 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4231 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4232 #define CAN_F0R2_FB11_Pos      (11U)
4233 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4234 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4235 #define CAN_F0R2_FB12_Pos      (12U)
4236 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4237 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4238 #define CAN_F0R2_FB13_Pos      (13U)
4239 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4240 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4241 #define CAN_F0R2_FB14_Pos      (14U)
4242 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4243 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4244 #define CAN_F0R2_FB15_Pos      (15U)
4245 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4246 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4247 #define CAN_F0R2_FB16_Pos      (16U)
4248 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4249 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4250 #define CAN_F0R2_FB17_Pos      (17U)
4251 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4252 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4253 #define CAN_F0R2_FB18_Pos      (18U)
4254 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4255 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4256 #define CAN_F0R2_FB19_Pos      (19U)
4257 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4258 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4259 #define CAN_F0R2_FB20_Pos      (20U)
4260 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4261 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4262 #define CAN_F0R2_FB21_Pos      (21U)
4263 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4264 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4265 #define CAN_F0R2_FB22_Pos      (22U)
4266 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4267 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4268 #define CAN_F0R2_FB23_Pos      (23U)
4269 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4270 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4271 #define CAN_F0R2_FB24_Pos      (24U)
4272 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4273 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4274 #define CAN_F0R2_FB25_Pos      (25U)
4275 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4276 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4277 #define CAN_F0R2_FB26_Pos      (26U)
4278 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4279 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4280 #define CAN_F0R2_FB27_Pos      (27U)
4281 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4282 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4283 #define CAN_F0R2_FB28_Pos      (28U)
4284 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4285 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4286 #define CAN_F0R2_FB29_Pos      (29U)
4287 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4288 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4289 #define CAN_F0R2_FB30_Pos      (30U)
4290 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4291 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4292 #define CAN_F0R2_FB31_Pos      (31U)
4293 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4294 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4295 
4296 /*******************  Bit definition for CAN_F1R2 register  *******************/
4297 #define CAN_F1R2_FB0_Pos       (0U)
4298 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4299 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4300 #define CAN_F1R2_FB1_Pos       (1U)
4301 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
4302 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4303 #define CAN_F1R2_FB2_Pos       (2U)
4304 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
4305 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4306 #define CAN_F1R2_FB3_Pos       (3U)
4307 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
4308 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4309 #define CAN_F1R2_FB4_Pos       (4U)
4310 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
4311 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4312 #define CAN_F1R2_FB5_Pos       (5U)
4313 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
4314 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4315 #define CAN_F1R2_FB6_Pos       (6U)
4316 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
4317 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4318 #define CAN_F1R2_FB7_Pos       (7U)
4319 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
4320 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4321 #define CAN_F1R2_FB8_Pos       (8U)
4322 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
4323 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4324 #define CAN_F1R2_FB9_Pos       (9U)
4325 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
4326 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4327 #define CAN_F1R2_FB10_Pos      (10U)
4328 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
4329 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4330 #define CAN_F1R2_FB11_Pos      (11U)
4331 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
4332 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4333 #define CAN_F1R2_FB12_Pos      (12U)
4334 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
4335 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4336 #define CAN_F1R2_FB13_Pos      (13U)
4337 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
4338 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4339 #define CAN_F1R2_FB14_Pos      (14U)
4340 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
4341 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4342 #define CAN_F1R2_FB15_Pos      (15U)
4343 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
4344 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4345 #define CAN_F1R2_FB16_Pos      (16U)
4346 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
4347 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4348 #define CAN_F1R2_FB17_Pos      (17U)
4349 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
4350 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4351 #define CAN_F1R2_FB18_Pos      (18U)
4352 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
4353 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4354 #define CAN_F1R2_FB19_Pos      (19U)
4355 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
4356 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4357 #define CAN_F1R2_FB20_Pos      (20U)
4358 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
4359 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4360 #define CAN_F1R2_FB21_Pos      (21U)
4361 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
4362 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4363 #define CAN_F1R2_FB22_Pos      (22U)
4364 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
4365 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4366 #define CAN_F1R2_FB23_Pos      (23U)
4367 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
4368 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4369 #define CAN_F1R2_FB24_Pos      (24U)
4370 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
4371 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4372 #define CAN_F1R2_FB25_Pos      (25U)
4373 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
4374 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4375 #define CAN_F1R2_FB26_Pos      (26U)
4376 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
4377 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4378 #define CAN_F1R2_FB27_Pos      (27U)
4379 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
4380 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4381 #define CAN_F1R2_FB28_Pos      (28U)
4382 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
4383 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4384 #define CAN_F1R2_FB29_Pos      (29U)
4385 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
4386 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4387 #define CAN_F1R2_FB30_Pos      (30U)
4388 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
4389 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4390 #define CAN_F1R2_FB31_Pos      (31U)
4391 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
4392 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4393 
4394 /*******************  Bit definition for CAN_F2R2 register  *******************/
4395 #define CAN_F2R2_FB0_Pos       (0U)
4396 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
4397 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4398 #define CAN_F2R2_FB1_Pos       (1U)
4399 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
4400 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4401 #define CAN_F2R2_FB2_Pos       (2U)
4402 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
4403 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4404 #define CAN_F2R2_FB3_Pos       (3U)
4405 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
4406 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4407 #define CAN_F2R2_FB4_Pos       (4U)
4408 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
4409 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4410 #define CAN_F2R2_FB5_Pos       (5U)
4411 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
4412 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4413 #define CAN_F2R2_FB6_Pos       (6U)
4414 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
4415 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4416 #define CAN_F2R2_FB7_Pos       (7U)
4417 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
4418 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4419 #define CAN_F2R2_FB8_Pos       (8U)
4420 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
4421 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4422 #define CAN_F2R2_FB9_Pos       (9U)
4423 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
4424 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4425 #define CAN_F2R2_FB10_Pos      (10U)
4426 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
4427 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4428 #define CAN_F2R2_FB11_Pos      (11U)
4429 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
4430 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4431 #define CAN_F2R2_FB12_Pos      (12U)
4432 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
4433 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4434 #define CAN_F2R2_FB13_Pos      (13U)
4435 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
4436 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4437 #define CAN_F2R2_FB14_Pos      (14U)
4438 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
4439 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4440 #define CAN_F2R2_FB15_Pos      (15U)
4441 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
4442 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4443 #define CAN_F2R2_FB16_Pos      (16U)
4444 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
4445 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4446 #define CAN_F2R2_FB17_Pos      (17U)
4447 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
4448 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4449 #define CAN_F2R2_FB18_Pos      (18U)
4450 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
4451 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4452 #define CAN_F2R2_FB19_Pos      (19U)
4453 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
4454 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4455 #define CAN_F2R2_FB20_Pos      (20U)
4456 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
4457 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4458 #define CAN_F2R2_FB21_Pos      (21U)
4459 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
4460 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4461 #define CAN_F2R2_FB22_Pos      (22U)
4462 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
4463 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4464 #define CAN_F2R2_FB23_Pos      (23U)
4465 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
4466 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4467 #define CAN_F2R2_FB24_Pos      (24U)
4468 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
4469 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4470 #define CAN_F2R2_FB25_Pos      (25U)
4471 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
4472 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4473 #define CAN_F2R2_FB26_Pos      (26U)
4474 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
4475 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4476 #define CAN_F2R2_FB27_Pos      (27U)
4477 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
4478 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4479 #define CAN_F2R2_FB28_Pos      (28U)
4480 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
4481 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4482 #define CAN_F2R2_FB29_Pos      (29U)
4483 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
4484 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4485 #define CAN_F2R2_FB30_Pos      (30U)
4486 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
4487 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4488 #define CAN_F2R2_FB31_Pos      (31U)
4489 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
4490 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4491 
4492 /*******************  Bit definition for CAN_F3R2 register  *******************/
4493 #define CAN_F3R2_FB0_Pos       (0U)
4494 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
4495 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4496 #define CAN_F3R2_FB1_Pos       (1U)
4497 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
4498 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4499 #define CAN_F3R2_FB2_Pos       (2U)
4500 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
4501 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4502 #define CAN_F3R2_FB3_Pos       (3U)
4503 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
4504 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4505 #define CAN_F3R2_FB4_Pos       (4U)
4506 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
4507 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4508 #define CAN_F3R2_FB5_Pos       (5U)
4509 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
4510 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4511 #define CAN_F3R2_FB6_Pos       (6U)
4512 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
4513 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4514 #define CAN_F3R2_FB7_Pos       (7U)
4515 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
4516 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4517 #define CAN_F3R2_FB8_Pos       (8U)
4518 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
4519 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4520 #define CAN_F3R2_FB9_Pos       (9U)
4521 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
4522 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4523 #define CAN_F3R2_FB10_Pos      (10U)
4524 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
4525 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4526 #define CAN_F3R2_FB11_Pos      (11U)
4527 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
4528 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4529 #define CAN_F3R2_FB12_Pos      (12U)
4530 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
4531 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4532 #define CAN_F3R2_FB13_Pos      (13U)
4533 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
4534 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4535 #define CAN_F3R2_FB14_Pos      (14U)
4536 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
4537 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4538 #define CAN_F3R2_FB15_Pos      (15U)
4539 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
4540 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4541 #define CAN_F3R2_FB16_Pos      (16U)
4542 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
4543 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
4544 #define CAN_F3R2_FB17_Pos      (17U)
4545 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
4546 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
4547 #define CAN_F3R2_FB18_Pos      (18U)
4548 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
4549 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
4550 #define CAN_F3R2_FB19_Pos      (19U)
4551 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
4552 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
4553 #define CAN_F3R2_FB20_Pos      (20U)
4554 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
4555 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
4556 #define CAN_F3R2_FB21_Pos      (21U)
4557 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
4558 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
4559 #define CAN_F3R2_FB22_Pos      (22U)
4560 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
4561 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
4562 #define CAN_F3R2_FB23_Pos      (23U)
4563 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
4564 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
4565 #define CAN_F3R2_FB24_Pos      (24U)
4566 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
4567 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
4568 #define CAN_F3R2_FB25_Pos      (25U)
4569 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
4570 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
4571 #define CAN_F3R2_FB26_Pos      (26U)
4572 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
4573 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
4574 #define CAN_F3R2_FB27_Pos      (27U)
4575 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
4576 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
4577 #define CAN_F3R2_FB28_Pos      (28U)
4578 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
4579 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
4580 #define CAN_F3R2_FB29_Pos      (29U)
4581 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
4582 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
4583 #define CAN_F3R2_FB30_Pos      (30U)
4584 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
4585 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
4586 #define CAN_F3R2_FB31_Pos      (31U)
4587 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
4588 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
4589 
4590 /*******************  Bit definition for CAN_F4R2 register  *******************/
4591 #define CAN_F4R2_FB0_Pos       (0U)
4592 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
4593 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
4594 #define CAN_F4R2_FB1_Pos       (1U)
4595 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
4596 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
4597 #define CAN_F4R2_FB2_Pos       (2U)
4598 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
4599 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
4600 #define CAN_F4R2_FB3_Pos       (3U)
4601 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
4602 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
4603 #define CAN_F4R2_FB4_Pos       (4U)
4604 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
4605 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
4606 #define CAN_F4R2_FB5_Pos       (5U)
4607 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
4608 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
4609 #define CAN_F4R2_FB6_Pos       (6U)
4610 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
4611 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
4612 #define CAN_F4R2_FB7_Pos       (7U)
4613 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
4614 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
4615 #define CAN_F4R2_FB8_Pos       (8U)
4616 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
4617 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
4618 #define CAN_F4R2_FB9_Pos       (9U)
4619 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
4620 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
4621 #define CAN_F4R2_FB10_Pos      (10U)
4622 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
4623 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
4624 #define CAN_F4R2_FB11_Pos      (11U)
4625 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
4626 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
4627 #define CAN_F4R2_FB12_Pos      (12U)
4628 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
4629 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
4630 #define CAN_F4R2_FB13_Pos      (13U)
4631 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
4632 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
4633 #define CAN_F4R2_FB14_Pos      (14U)
4634 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
4635 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
4636 #define CAN_F4R2_FB15_Pos      (15U)
4637 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
4638 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
4639 #define CAN_F4R2_FB16_Pos      (16U)
4640 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
4641 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
4642 #define CAN_F4R2_FB17_Pos      (17U)
4643 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
4644 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
4645 #define CAN_F4R2_FB18_Pos      (18U)
4646 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
4647 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
4648 #define CAN_F4R2_FB19_Pos      (19U)
4649 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
4650 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
4651 #define CAN_F4R2_FB20_Pos      (20U)
4652 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
4653 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
4654 #define CAN_F4R2_FB21_Pos      (21U)
4655 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
4656 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
4657 #define CAN_F4R2_FB22_Pos      (22U)
4658 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
4659 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
4660 #define CAN_F4R2_FB23_Pos      (23U)
4661 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
4662 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
4663 #define CAN_F4R2_FB24_Pos      (24U)
4664 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
4665 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
4666 #define CAN_F4R2_FB25_Pos      (25U)
4667 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
4668 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
4669 #define CAN_F4R2_FB26_Pos      (26U)
4670 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
4671 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
4672 #define CAN_F4R2_FB27_Pos      (27U)
4673 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
4674 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
4675 #define CAN_F4R2_FB28_Pos      (28U)
4676 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
4677 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
4678 #define CAN_F4R2_FB29_Pos      (29U)
4679 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
4680 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
4681 #define CAN_F4R2_FB30_Pos      (30U)
4682 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
4683 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
4684 #define CAN_F4R2_FB31_Pos      (31U)
4685 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
4686 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
4687 
4688 /*******************  Bit definition for CAN_F5R2 register  *******************/
4689 #define CAN_F5R2_FB0_Pos       (0U)
4690 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
4691 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
4692 #define CAN_F5R2_FB1_Pos       (1U)
4693 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
4694 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
4695 #define CAN_F5R2_FB2_Pos       (2U)
4696 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
4697 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
4698 #define CAN_F5R2_FB3_Pos       (3U)
4699 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
4700 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
4701 #define CAN_F5R2_FB4_Pos       (4U)
4702 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
4703 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
4704 #define CAN_F5R2_FB5_Pos       (5U)
4705 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
4706 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
4707 #define CAN_F5R2_FB6_Pos       (6U)
4708 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
4709 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
4710 #define CAN_F5R2_FB7_Pos       (7U)
4711 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
4712 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
4713 #define CAN_F5R2_FB8_Pos       (8U)
4714 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
4715 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
4716 #define CAN_F5R2_FB9_Pos       (9U)
4717 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
4718 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
4719 #define CAN_F5R2_FB10_Pos      (10U)
4720 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
4721 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
4722 #define CAN_F5R2_FB11_Pos      (11U)
4723 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
4724 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
4725 #define CAN_F5R2_FB12_Pos      (12U)
4726 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
4727 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
4728 #define CAN_F5R2_FB13_Pos      (13U)
4729 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
4730 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
4731 #define CAN_F5R2_FB14_Pos      (14U)
4732 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
4733 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
4734 #define CAN_F5R2_FB15_Pos      (15U)
4735 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
4736 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
4737 #define CAN_F5R2_FB16_Pos      (16U)
4738 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
4739 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
4740 #define CAN_F5R2_FB17_Pos      (17U)
4741 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
4742 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
4743 #define CAN_F5R2_FB18_Pos      (18U)
4744 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
4745 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
4746 #define CAN_F5R2_FB19_Pos      (19U)
4747 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
4748 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
4749 #define CAN_F5R2_FB20_Pos      (20U)
4750 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
4751 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
4752 #define CAN_F5R2_FB21_Pos      (21U)
4753 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
4754 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
4755 #define CAN_F5R2_FB22_Pos      (22U)
4756 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
4757 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
4758 #define CAN_F5R2_FB23_Pos      (23U)
4759 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
4760 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
4761 #define CAN_F5R2_FB24_Pos      (24U)
4762 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
4763 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
4764 #define CAN_F5R2_FB25_Pos      (25U)
4765 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
4766 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
4767 #define CAN_F5R2_FB26_Pos      (26U)
4768 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
4769 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
4770 #define CAN_F5R2_FB27_Pos      (27U)
4771 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
4772 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
4773 #define CAN_F5R2_FB28_Pos      (28U)
4774 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
4775 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
4776 #define CAN_F5R2_FB29_Pos      (29U)
4777 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
4778 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
4779 #define CAN_F5R2_FB30_Pos      (30U)
4780 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
4781 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
4782 #define CAN_F5R2_FB31_Pos      (31U)
4783 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
4784 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
4785 
4786 /*******************  Bit definition for CAN_F6R2 register  *******************/
4787 #define CAN_F6R2_FB0_Pos       (0U)
4788 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
4789 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
4790 #define CAN_F6R2_FB1_Pos       (1U)
4791 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
4792 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
4793 #define CAN_F6R2_FB2_Pos       (2U)
4794 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
4795 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
4796 #define CAN_F6R2_FB3_Pos       (3U)
4797 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
4798 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
4799 #define CAN_F6R2_FB4_Pos       (4U)
4800 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
4801 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
4802 #define CAN_F6R2_FB5_Pos       (5U)
4803 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
4804 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
4805 #define CAN_F6R2_FB6_Pos       (6U)
4806 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
4807 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
4808 #define CAN_F6R2_FB7_Pos       (7U)
4809 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
4810 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
4811 #define CAN_F6R2_FB8_Pos       (8U)
4812 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
4813 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
4814 #define CAN_F6R2_FB9_Pos       (9U)
4815 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
4816 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
4817 #define CAN_F6R2_FB10_Pos      (10U)
4818 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
4819 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
4820 #define CAN_F6R2_FB11_Pos      (11U)
4821 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
4822 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
4823 #define CAN_F6R2_FB12_Pos      (12U)
4824 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
4825 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
4826 #define CAN_F6R2_FB13_Pos      (13U)
4827 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
4828 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
4829 #define CAN_F6R2_FB14_Pos      (14U)
4830 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
4831 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
4832 #define CAN_F6R2_FB15_Pos      (15U)
4833 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
4834 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
4835 #define CAN_F6R2_FB16_Pos      (16U)
4836 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
4837 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
4838 #define CAN_F6R2_FB17_Pos      (17U)
4839 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
4840 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
4841 #define CAN_F6R2_FB18_Pos      (18U)
4842 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
4843 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
4844 #define CAN_F6R2_FB19_Pos      (19U)
4845 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
4846 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
4847 #define CAN_F6R2_FB20_Pos      (20U)
4848 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
4849 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
4850 #define CAN_F6R2_FB21_Pos      (21U)
4851 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
4852 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
4853 #define CAN_F6R2_FB22_Pos      (22U)
4854 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
4855 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
4856 #define CAN_F6R2_FB23_Pos      (23U)
4857 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
4858 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
4859 #define CAN_F6R2_FB24_Pos      (24U)
4860 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
4861 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
4862 #define CAN_F6R2_FB25_Pos      (25U)
4863 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
4864 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
4865 #define CAN_F6R2_FB26_Pos      (26U)
4866 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
4867 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
4868 #define CAN_F6R2_FB27_Pos      (27U)
4869 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
4870 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
4871 #define CAN_F6R2_FB28_Pos      (28U)
4872 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
4873 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
4874 #define CAN_F6R2_FB29_Pos      (29U)
4875 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
4876 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4877 #define CAN_F6R2_FB30_Pos      (30U)
4878 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
4879 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4880 #define CAN_F6R2_FB31_Pos      (31U)
4881 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
4882 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4883 
4884 /*******************  Bit definition for CAN_F7R2 register  *******************/
4885 #define CAN_F7R2_FB0_Pos       (0U)
4886 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
4887 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4888 #define CAN_F7R2_FB1_Pos       (1U)
4889 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
4890 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4891 #define CAN_F7R2_FB2_Pos       (2U)
4892 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
4893 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4894 #define CAN_F7R2_FB3_Pos       (3U)
4895 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
4896 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4897 #define CAN_F7R2_FB4_Pos       (4U)
4898 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
4899 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4900 #define CAN_F7R2_FB5_Pos       (5U)
4901 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
4902 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4903 #define CAN_F7R2_FB6_Pos       (6U)
4904 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
4905 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4906 #define CAN_F7R2_FB7_Pos       (7U)
4907 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
4908 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4909 #define CAN_F7R2_FB8_Pos       (8U)
4910 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
4911 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4912 #define CAN_F7R2_FB9_Pos       (9U)
4913 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
4914 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
4915 #define CAN_F7R2_FB10_Pos      (10U)
4916 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
4917 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
4918 #define CAN_F7R2_FB11_Pos      (11U)
4919 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
4920 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
4921 #define CAN_F7R2_FB12_Pos      (12U)
4922 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
4923 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
4924 #define CAN_F7R2_FB13_Pos      (13U)
4925 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
4926 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
4927 #define CAN_F7R2_FB14_Pos      (14U)
4928 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
4929 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
4930 #define CAN_F7R2_FB15_Pos      (15U)
4931 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
4932 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
4933 #define CAN_F7R2_FB16_Pos      (16U)
4934 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
4935 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
4936 #define CAN_F7R2_FB17_Pos      (17U)
4937 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
4938 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
4939 #define CAN_F7R2_FB18_Pos      (18U)
4940 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
4941 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
4942 #define CAN_F7R2_FB19_Pos      (19U)
4943 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
4944 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
4945 #define CAN_F7R2_FB20_Pos      (20U)
4946 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
4947 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
4948 #define CAN_F7R2_FB21_Pos      (21U)
4949 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
4950 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
4951 #define CAN_F7R2_FB22_Pos      (22U)
4952 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
4953 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
4954 #define CAN_F7R2_FB23_Pos      (23U)
4955 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
4956 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
4957 #define CAN_F7R2_FB24_Pos      (24U)
4958 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
4959 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
4960 #define CAN_F7R2_FB25_Pos      (25U)
4961 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
4962 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
4963 #define CAN_F7R2_FB26_Pos      (26U)
4964 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
4965 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
4966 #define CAN_F7R2_FB27_Pos      (27U)
4967 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
4968 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
4969 #define CAN_F7R2_FB28_Pos      (28U)
4970 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
4971 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
4972 #define CAN_F7R2_FB29_Pos      (29U)
4973 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
4974 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
4975 #define CAN_F7R2_FB30_Pos      (30U)
4976 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
4977 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
4978 #define CAN_F7R2_FB31_Pos      (31U)
4979 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
4980 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
4981 
4982 /*******************  Bit definition for CAN_F8R2 register  *******************/
4983 #define CAN_F8R2_FB0_Pos       (0U)
4984 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
4985 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
4986 #define CAN_F8R2_FB1_Pos       (1U)
4987 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
4988 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
4989 #define CAN_F8R2_FB2_Pos       (2U)
4990 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
4991 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
4992 #define CAN_F8R2_FB3_Pos       (3U)
4993 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
4994 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
4995 #define CAN_F8R2_FB4_Pos       (4U)
4996 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
4997 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
4998 #define CAN_F8R2_FB5_Pos       (5U)
4999 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
5000 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
5001 #define CAN_F8R2_FB6_Pos       (6U)
5002 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
5003 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
5004 #define CAN_F8R2_FB7_Pos       (7U)
5005 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
5006 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
5007 #define CAN_F8R2_FB8_Pos       (8U)
5008 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
5009 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
5010 #define CAN_F8R2_FB9_Pos       (9U)
5011 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
5012 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
5013 #define CAN_F8R2_FB10_Pos      (10U)
5014 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
5015 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
5016 #define CAN_F8R2_FB11_Pos      (11U)
5017 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
5018 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
5019 #define CAN_F8R2_FB12_Pos      (12U)
5020 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
5021 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
5022 #define CAN_F8R2_FB13_Pos      (13U)
5023 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
5024 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
5025 #define CAN_F8R2_FB14_Pos      (14U)
5026 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
5027 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
5028 #define CAN_F8R2_FB15_Pos      (15U)
5029 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
5030 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
5031 #define CAN_F8R2_FB16_Pos      (16U)
5032 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
5033 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
5034 #define CAN_F8R2_FB17_Pos      (17U)
5035 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
5036 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
5037 #define CAN_F8R2_FB18_Pos      (18U)
5038 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
5039 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
5040 #define CAN_F8R2_FB19_Pos      (19U)
5041 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
5042 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
5043 #define CAN_F8R2_FB20_Pos      (20U)
5044 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
5045 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
5046 #define CAN_F8R2_FB21_Pos      (21U)
5047 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
5048 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
5049 #define CAN_F8R2_FB22_Pos      (22U)
5050 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
5051 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
5052 #define CAN_F8R2_FB23_Pos      (23U)
5053 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
5054 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
5055 #define CAN_F8R2_FB24_Pos      (24U)
5056 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
5057 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
5058 #define CAN_F8R2_FB25_Pos      (25U)
5059 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
5060 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
5061 #define CAN_F8R2_FB26_Pos      (26U)
5062 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
5063 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
5064 #define CAN_F8R2_FB27_Pos      (27U)
5065 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
5066 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
5067 #define CAN_F8R2_FB28_Pos      (28U)
5068 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
5069 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
5070 #define CAN_F8R2_FB29_Pos      (29U)
5071 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
5072 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
5073 #define CAN_F8R2_FB30_Pos      (30U)
5074 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
5075 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
5076 #define CAN_F8R2_FB31_Pos      (31U)
5077 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
5078 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
5079 
5080 /*******************  Bit definition for CAN_F9R2 register  *******************/
5081 #define CAN_F9R2_FB0_Pos       (0U)
5082 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
5083 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
5084 #define CAN_F9R2_FB1_Pos       (1U)
5085 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
5086 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
5087 #define CAN_F9R2_FB2_Pos       (2U)
5088 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
5089 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
5090 #define CAN_F9R2_FB3_Pos       (3U)
5091 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
5092 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
5093 #define CAN_F9R2_FB4_Pos       (4U)
5094 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
5095 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
5096 #define CAN_F9R2_FB5_Pos       (5U)
5097 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
5098 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
5099 #define CAN_F9R2_FB6_Pos       (6U)
5100 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
5101 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
5102 #define CAN_F9R2_FB7_Pos       (7U)
5103 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
5104 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
5105 #define CAN_F9R2_FB8_Pos       (8U)
5106 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
5107 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
5108 #define CAN_F9R2_FB9_Pos       (9U)
5109 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
5110 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
5111 #define CAN_F9R2_FB10_Pos      (10U)
5112 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
5113 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
5114 #define CAN_F9R2_FB11_Pos      (11U)
5115 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
5116 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
5117 #define CAN_F9R2_FB12_Pos      (12U)
5118 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
5119 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
5120 #define CAN_F9R2_FB13_Pos      (13U)
5121 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
5122 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
5123 #define CAN_F9R2_FB14_Pos      (14U)
5124 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
5125 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
5126 #define CAN_F9R2_FB15_Pos      (15U)
5127 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
5128 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
5129 #define CAN_F9R2_FB16_Pos      (16U)
5130 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
5131 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
5132 #define CAN_F9R2_FB17_Pos      (17U)
5133 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
5134 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
5135 #define CAN_F9R2_FB18_Pos      (18U)
5136 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
5137 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
5138 #define CAN_F9R2_FB19_Pos      (19U)
5139 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
5140 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5141 #define CAN_F9R2_FB20_Pos      (20U)
5142 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
5143 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5144 #define CAN_F9R2_FB21_Pos      (21U)
5145 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
5146 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5147 #define CAN_F9R2_FB22_Pos      (22U)
5148 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
5149 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5150 #define CAN_F9R2_FB23_Pos      (23U)
5151 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5152 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5153 #define CAN_F9R2_FB24_Pos      (24U)
5154 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5155 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5156 #define CAN_F9R2_FB25_Pos      (25U)
5157 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5158 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5159 #define CAN_F9R2_FB26_Pos      (26U)
5160 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5161 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5162 #define CAN_F9R2_FB27_Pos      (27U)
5163 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5164 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5165 #define CAN_F9R2_FB28_Pos      (28U)
5166 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5167 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5168 #define CAN_F9R2_FB29_Pos      (29U)
5169 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5170 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5171 #define CAN_F9R2_FB30_Pos      (30U)
5172 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5173 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5174 #define CAN_F9R2_FB31_Pos      (31U)
5175 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5176 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5177 
5178 /*******************  Bit definition for CAN_F10R2 register  ******************/
5179 #define CAN_F10R2_FB0_Pos      (0U)
5180 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5181 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5182 #define CAN_F10R2_FB1_Pos      (1U)
5183 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5184 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5185 #define CAN_F10R2_FB2_Pos      (2U)
5186 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5187 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5188 #define CAN_F10R2_FB3_Pos      (3U)
5189 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5190 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5191 #define CAN_F10R2_FB4_Pos      (4U)
5192 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5193 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5194 #define CAN_F10R2_FB5_Pos      (5U)
5195 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5196 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5197 #define CAN_F10R2_FB6_Pos      (6U)
5198 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5199 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5200 #define CAN_F10R2_FB7_Pos      (7U)
5201 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5202 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5203 #define CAN_F10R2_FB8_Pos      (8U)
5204 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5205 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5206 #define CAN_F10R2_FB9_Pos      (9U)
5207 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5208 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5209 #define CAN_F10R2_FB10_Pos     (10U)
5210 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5211 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5212 #define CAN_F10R2_FB11_Pos     (11U)
5213 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5214 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5215 #define CAN_F10R2_FB12_Pos     (12U)
5216 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5217 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5218 #define CAN_F10R2_FB13_Pos     (13U)
5219 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5220 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5221 #define CAN_F10R2_FB14_Pos     (14U)
5222 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5223 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5224 #define CAN_F10R2_FB15_Pos     (15U)
5225 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5226 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5227 #define CAN_F10R2_FB16_Pos     (16U)
5228 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5229 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5230 #define CAN_F10R2_FB17_Pos     (17U)
5231 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5232 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5233 #define CAN_F10R2_FB18_Pos     (18U)
5234 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5235 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5236 #define CAN_F10R2_FB19_Pos     (19U)
5237 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5238 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5239 #define CAN_F10R2_FB20_Pos     (20U)
5240 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5241 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5242 #define CAN_F10R2_FB21_Pos     (21U)
5243 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5244 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5245 #define CAN_F10R2_FB22_Pos     (22U)
5246 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5247 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5248 #define CAN_F10R2_FB23_Pos     (23U)
5249 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5250 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5251 #define CAN_F10R2_FB24_Pos     (24U)
5252 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5253 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5254 #define CAN_F10R2_FB25_Pos     (25U)
5255 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5256 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5257 #define CAN_F10R2_FB26_Pos     (26U)
5258 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5259 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5260 #define CAN_F10R2_FB27_Pos     (27U)
5261 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5262 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5263 #define CAN_F10R2_FB28_Pos     (28U)
5264 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5265 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5266 #define CAN_F10R2_FB29_Pos     (29U)
5267 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5268 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5269 #define CAN_F10R2_FB30_Pos     (30U)
5270 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5271 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5272 #define CAN_F10R2_FB31_Pos     (31U)
5273 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5274 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5275 
5276 /*******************  Bit definition for CAN_F11R2 register  ******************/
5277 #define CAN_F11R2_FB0_Pos      (0U)
5278 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5279 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5280 #define CAN_F11R2_FB1_Pos      (1U)
5281 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5282 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5283 #define CAN_F11R2_FB2_Pos      (2U)
5284 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5285 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5286 #define CAN_F11R2_FB3_Pos      (3U)
5287 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5288 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5289 #define CAN_F11R2_FB4_Pos      (4U)
5290 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5291 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5292 #define CAN_F11R2_FB5_Pos      (5U)
5293 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5294 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5295 #define CAN_F11R2_FB6_Pos      (6U)
5296 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5297 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5298 #define CAN_F11R2_FB7_Pos      (7U)
5299 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5300 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5301 #define CAN_F11R2_FB8_Pos      (8U)
5302 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
5303 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5304 #define CAN_F11R2_FB9_Pos      (9U)
5305 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
5306 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5307 #define CAN_F11R2_FB10_Pos     (10U)
5308 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
5309 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5310 #define CAN_F11R2_FB11_Pos     (11U)
5311 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
5312 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5313 #define CAN_F11R2_FB12_Pos     (12U)
5314 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
5315 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5316 #define CAN_F11R2_FB13_Pos     (13U)
5317 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
5318 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5319 #define CAN_F11R2_FB14_Pos     (14U)
5320 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
5321 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5322 #define CAN_F11R2_FB15_Pos     (15U)
5323 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
5324 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5325 #define CAN_F11R2_FB16_Pos     (16U)
5326 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
5327 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5328 #define CAN_F11R2_FB17_Pos     (17U)
5329 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
5330 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5331 #define CAN_F11R2_FB18_Pos     (18U)
5332 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
5333 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5334 #define CAN_F11R2_FB19_Pos     (19U)
5335 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
5336 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5337 #define CAN_F11R2_FB20_Pos     (20U)
5338 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
5339 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5340 #define CAN_F11R2_FB21_Pos     (21U)
5341 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
5342 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5343 #define CAN_F11R2_FB22_Pos     (22U)
5344 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
5345 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5346 #define CAN_F11R2_FB23_Pos     (23U)
5347 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
5348 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5349 #define CAN_F11R2_FB24_Pos     (24U)
5350 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
5351 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5352 #define CAN_F11R2_FB25_Pos     (25U)
5353 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
5354 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5355 #define CAN_F11R2_FB26_Pos     (26U)
5356 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
5357 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5358 #define CAN_F11R2_FB27_Pos     (27U)
5359 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
5360 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5361 #define CAN_F11R2_FB28_Pos     (28U)
5362 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
5363 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5364 #define CAN_F11R2_FB29_Pos     (29U)
5365 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
5366 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5367 #define CAN_F11R2_FB30_Pos     (30U)
5368 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
5369 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5370 #define CAN_F11R2_FB31_Pos     (31U)
5371 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
5372 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5373 
5374 /*******************  Bit definition for CAN_F12R2 register  ******************/
5375 #define CAN_F12R2_FB0_Pos      (0U)
5376 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
5377 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5378 #define CAN_F12R2_FB1_Pos      (1U)
5379 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
5380 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5381 #define CAN_F12R2_FB2_Pos      (2U)
5382 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
5383 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5384 #define CAN_F12R2_FB3_Pos      (3U)
5385 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
5386 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5387 #define CAN_F12R2_FB4_Pos      (4U)
5388 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
5389 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5390 #define CAN_F12R2_FB5_Pos      (5U)
5391 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
5392 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5393 #define CAN_F12R2_FB6_Pos      (6U)
5394 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
5395 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5396 #define CAN_F12R2_FB7_Pos      (7U)
5397 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
5398 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5399 #define CAN_F12R2_FB8_Pos      (8U)
5400 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
5401 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5402 #define CAN_F12R2_FB9_Pos      (9U)
5403 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
5404 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5405 #define CAN_F12R2_FB10_Pos     (10U)
5406 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
5407 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5408 #define CAN_F12R2_FB11_Pos     (11U)
5409 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
5410 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5411 #define CAN_F12R2_FB12_Pos     (12U)
5412 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
5413 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5414 #define CAN_F12R2_FB13_Pos     (13U)
5415 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
5416 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5417 #define CAN_F12R2_FB14_Pos     (14U)
5418 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
5419 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5420 #define CAN_F12R2_FB15_Pos     (15U)
5421 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
5422 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5423 #define CAN_F12R2_FB16_Pos     (16U)
5424 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
5425 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5426 #define CAN_F12R2_FB17_Pos     (17U)
5427 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
5428 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5429 #define CAN_F12R2_FB18_Pos     (18U)
5430 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
5431 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5432 #define CAN_F12R2_FB19_Pos     (19U)
5433 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
5434 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5435 #define CAN_F12R2_FB20_Pos     (20U)
5436 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
5437 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5438 #define CAN_F12R2_FB21_Pos     (21U)
5439 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
5440 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5441 #define CAN_F12R2_FB22_Pos     (22U)
5442 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
5443 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5444 #define CAN_F12R2_FB23_Pos     (23U)
5445 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
5446 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5447 #define CAN_F12R2_FB24_Pos     (24U)
5448 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
5449 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5450 #define CAN_F12R2_FB25_Pos     (25U)
5451 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
5452 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5453 #define CAN_F12R2_FB26_Pos     (26U)
5454 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
5455 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5456 #define CAN_F12R2_FB27_Pos     (27U)
5457 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
5458 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5459 #define CAN_F12R2_FB28_Pos     (28U)
5460 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
5461 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5462 #define CAN_F12R2_FB29_Pos     (29U)
5463 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
5464 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5465 #define CAN_F12R2_FB30_Pos     (30U)
5466 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
5467 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5468 #define CAN_F12R2_FB31_Pos     (31U)
5469 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
5470 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5471 
5472 /*******************  Bit definition for CAN_F13R2 register  ******************/
5473 #define CAN_F13R2_FB0_Pos      (0U)
5474 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
5475 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5476 #define CAN_F13R2_FB1_Pos      (1U)
5477 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
5478 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5479 #define CAN_F13R2_FB2_Pos      (2U)
5480 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
5481 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5482 #define CAN_F13R2_FB3_Pos      (3U)
5483 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
5484 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5485 #define CAN_F13R2_FB4_Pos      (4U)
5486 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
5487 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5488 #define CAN_F13R2_FB5_Pos      (5U)
5489 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
5490 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5491 #define CAN_F13R2_FB6_Pos      (6U)
5492 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
5493 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5494 #define CAN_F13R2_FB7_Pos      (7U)
5495 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
5496 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5497 #define CAN_F13R2_FB8_Pos      (8U)
5498 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
5499 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5500 #define CAN_F13R2_FB9_Pos      (9U)
5501 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
5502 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5503 #define CAN_F13R2_FB10_Pos     (10U)
5504 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
5505 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5506 #define CAN_F13R2_FB11_Pos     (11U)
5507 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
5508 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5509 #define CAN_F13R2_FB12_Pos     (12U)
5510 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
5511 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5512 #define CAN_F13R2_FB13_Pos     (13U)
5513 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
5514 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5515 #define CAN_F13R2_FB14_Pos     (14U)
5516 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
5517 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5518 #define CAN_F13R2_FB15_Pos     (15U)
5519 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
5520 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5521 #define CAN_F13R2_FB16_Pos     (16U)
5522 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
5523 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5524 #define CAN_F13R2_FB17_Pos     (17U)
5525 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
5526 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5527 #define CAN_F13R2_FB18_Pos     (18U)
5528 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
5529 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5530 #define CAN_F13R2_FB19_Pos     (19U)
5531 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
5532 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5533 #define CAN_F13R2_FB20_Pos     (20U)
5534 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
5535 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5536 #define CAN_F13R2_FB21_Pos     (21U)
5537 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
5538 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5539 #define CAN_F13R2_FB22_Pos     (22U)
5540 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
5541 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
5542 #define CAN_F13R2_FB23_Pos     (23U)
5543 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
5544 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
5545 #define CAN_F13R2_FB24_Pos     (24U)
5546 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
5547 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
5548 #define CAN_F13R2_FB25_Pos     (25U)
5549 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
5550 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
5551 #define CAN_F13R2_FB26_Pos     (26U)
5552 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
5553 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
5554 #define CAN_F13R2_FB27_Pos     (27U)
5555 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
5556 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
5557 #define CAN_F13R2_FB28_Pos     (28U)
5558 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
5559 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
5560 #define CAN_F13R2_FB29_Pos     (29U)
5561 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
5562 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
5563 #define CAN_F13R2_FB30_Pos     (30U)
5564 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
5565 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
5566 #define CAN_F13R2_FB31_Pos     (31U)
5567 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
5568 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
5569 
5570 /******************************************************************************/
5571 /*                                                                            */
5572 /*                                 HDMI-CEC (CEC)                             */
5573 /*                                                                            */
5574 /******************************************************************************/
5575 
5576 /*******************  Bit definition for CEC_CR register  *********************/
5577 #define CEC_CR_CECEN_Pos         (0U)
5578 #define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */
5579 #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                         */
5580 #define CEC_CR_TXSOM_Pos         (1U)
5581 #define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */
5582 #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message            */
5583 #define CEC_CR_TXEOM_Pos         (2U)
5584 #define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */
5585 #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message              */
5586 
5587 /*******************  Bit definition for CEC_CFGR register  *******************/
5588 #define CEC_CFGR_SFT_Pos         (0U)
5589 #define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */
5590 #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time               */
5591 #define CEC_CFGR_RXTOL_Pos       (3U)
5592 #define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */
5593 #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                      */
5594 #define CEC_CFGR_BRESTP_Pos      (4U)
5595 #define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */
5596 #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                        */
5597 #define CEC_CFGR_BREGEN_Pos      (5U)
5598 #define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */
5599 #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation    */
5600 #define CEC_CFGR_LBPEGEN_Pos     (6U)
5601 #define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */
5602 #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Period Error generation   */
5603 #define CEC_CFGR_BRDNOGEN_Pos    (7U)
5604 #define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */
5605 #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast no Error generation  */
5606 #define CEC_CFGR_SFTOPT_Pos      (8U)
5607 #define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */
5608 #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional      */
5609 #define CEC_CFGR_OAR_Pos         (16U)
5610 #define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */
5611 #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                    */
5612 #define CEC_CFGR_LSTN_Pos        (31U)
5613 #define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */
5614 #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                    */
5615 
5616 /*******************  Bit definition for CEC_TXDR register  *******************/
5617 #define CEC_TXDR_TXD_Pos         (0U)
5618 #define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */
5619 #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                        */
5620 
5621 /*******************  Bit definition for CEC_RXDR register  *******************/
5622 #define CEC_RXDR_RXD_Pos         (0U)
5623 #define CEC_RXDR_RXD_Msk         (0xFFU << CEC_RXDR_RXD_Pos)                   /*!< 0x000000FF */
5624 #define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                        */
5625 
5626 /*******************  Bit definition for CEC_ISR register  ********************/
5627 #define CEC_ISR_RXBR_Pos         (0U)
5628 #define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */
5629 #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                   */
5630 #define CEC_ISR_RXEND_Pos        (1U)
5631 #define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */
5632 #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                   */
5633 #define CEC_ISR_RXOVR_Pos        (2U)
5634 #define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */
5635 #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                         */
5636 #define CEC_ISR_BRE_Pos          (3U)
5637 #define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */
5638 #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                */
5639 #define CEC_ISR_SBPE_Pos         (4U)
5640 #define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */
5641 #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error          */
5642 #define CEC_ISR_LBPE_Pos         (5U)
5643 #define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */
5644 #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error           */
5645 #define CEC_ISR_RXACKE_Pos       (6U)
5646 #define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */
5647 #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge             */
5648 #define CEC_ISR_ARBLST_Pos       (7U)
5649 #define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */
5650 #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                   */
5651 #define CEC_ISR_TXBR_Pos         (8U)
5652 #define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */
5653 #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                    */
5654 #define CEC_ISR_TXEND_Pos        (9U)
5655 #define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */
5656 #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                */
5657 #define CEC_ISR_TXUDR_Pos        (10U)
5658 #define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */
5659 #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                 */
5660 #define CEC_ISR_TXERR_Pos        (11U)
5661 #define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */
5662 #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                           */
5663 #define CEC_ISR_TXACKE_Pos       (12U)
5664 #define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */
5665 #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge             */
5666 
5667 /*******************  Bit definition for CEC_IER register  ********************/
5668 #define CEC_IER_RXBRIE_Pos       (0U)
5669 #define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */
5670 #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable         */
5671 #define CEC_IER_RXENDIE_Pos      (1U)
5672 #define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */
5673 #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable         */
5674 #define CEC_IER_RXOVRIE_Pos      (2U)
5675 #define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */
5676 #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable               */
5677 #define CEC_IER_BREIE_Pos        (3U)
5678 #define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */
5679 #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable      */
5680 #define CEC_IER_SBPEIE_Pos       (4U)
5681 #define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */
5682 #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable*/
5683 #define CEC_IER_LBPEIE_Pos       (5U)
5684 #define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */
5685 #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable */
5686 #define CEC_IER_RXACKEIE_Pos     (6U)
5687 #define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */
5688 #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable   */
5689 #define CEC_IER_ARBLSTIE_Pos     (7U)
5690 #define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */
5691 #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable         */
5692 #define CEC_IER_TXBRIE_Pos       (8U)
5693 #define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */
5694 #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable         */
5695 #define CEC_IER_TXENDIE_Pos      (9U)
5696 #define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */
5697 #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable      */
5698 #define CEC_IER_TXUDRIE_Pos      (10U)
5699 #define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */
5700 #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable       */
5701 #define CEC_IER_TXERRIE_Pos      (11U)
5702 #define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */
5703 #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                 */
5704 #define CEC_IER_TXACKEIE_Pos     (12U)
5705 #define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */
5706 #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable   */
5707 
5708 /******************************************************************************/
5709 /*                                                                            */
5710 /*                          CRC calculation unit                              */
5711 /*                                                                            */
5712 /******************************************************************************/
5713 /*******************  Bit definition for CRC_DR register  *********************/
5714 #define CRC_DR_DR_Pos            (0U)
5715 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
5716 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
5717 
5718 /*******************  Bit definition for CRC_IDR register  ********************/
5719 #define CRC_IDR_IDR_Pos          (0U)
5720 #define CRC_IDR_IDR_Msk          (0xFFUL << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
5721 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
5722 
5723 /********************  Bit definition for CRC_CR register  ********************/
5724 #define CRC_CR_RESET_Pos         (0U)
5725 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
5726 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
5727 #define CRC_CR_POLYSIZE_Pos      (3U)
5728 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
5729 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits               */
5730 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
5731 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
5732 #define CRC_CR_REV_IN_Pos        (5U)
5733 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
5734 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits     */
5735 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
5736 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
5737 #define CRC_CR_REV_OUT_Pos       (7U)
5738 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
5739 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits   */
5740 
5741 /*******************  Bit definition for CRC_INIT register  *******************/
5742 #define CRC_INIT_INIT_Pos        (0U)
5743 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
5744 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits         */
5745 
5746 /*******************  Bit definition for CRC_POL register  ********************/
5747 #define CRC_POL_POL_Pos          (0U)
5748 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
5749 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
5750 
5751 /******************************************************************************/
5752 /*                                                                            */
5753 /*                            Crypto Processor                                */
5754 /*                                                                            */
5755 /******************************************************************************/
5756 /******************* Bits definition for CRYP_CR register  ********************/
5757 #define CRYP_CR_ALGODIR_Pos              (2U)
5758 #define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)         /*!< 0x00000004 */
5759 #define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk
5760 
5761 #define CRYP_CR_ALGOMODE_Pos             (3U)
5762 #define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00080038 */
5763 #define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk
5764 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
5765 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
5766 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
5767 #define CRYP_CR_ALGOMODE_TDES_ECB        0x00000000U
5768 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
5769 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5770 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
5771 #define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)
5772 #define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5773 #define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk
5774 #define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)
5775 #define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5776 #define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk
5777 #define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)
5778 #define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5779 #define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk
5780 #define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)
5781 #define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5782 #define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk
5783 #define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)
5784 #define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5785 #define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk
5786 #define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)
5787 #define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5788 #define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk
5789 #define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)
5790 #define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
5791 #define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk
5792 #define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)
5793 #define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
5794 #define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk
5795 
5796 #define CRYP_CR_DATATYPE_Pos             (6U)
5797 #define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x000000C0 */
5798 #define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk
5799 #define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */
5800 #define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */
5801 #define CRYP_CR_KEYSIZE_Pos              (8U)
5802 #define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000300 */
5803 #define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk
5804 #define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */
5805 #define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */
5806 #define CRYP_CR_FFLUSH_Pos               (14U)
5807 #define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)          /*!< 0x00004000 */
5808 #define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk
5809 #define CRYP_CR_CRYPEN_Pos               (15U)
5810 #define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)          /*!< 0x00008000 */
5811 #define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk
5812 
5813 #define CRYP_CR_GCM_CCMPH_Pos            (16U)
5814 #define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00030000 */
5815 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
5816 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
5817 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
5818 #define CRYP_CR_ALGOMODE_3               0x00080000U
5819 
5820 /****************** Bits definition for CRYP_SR register  *********************/
5821 #define CRYP_SR_IFEM_Pos                 (0U)
5822 #define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)            /*!< 0x00000001 */
5823 #define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk
5824 #define CRYP_SR_IFNF_Pos                 (1U)
5825 #define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)            /*!< 0x00000002 */
5826 #define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk
5827 #define CRYP_SR_OFNE_Pos                 (2U)
5828 #define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)            /*!< 0x00000004 */
5829 #define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk
5830 #define CRYP_SR_OFFU_Pos                 (3U)
5831 #define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)            /*!< 0x00000008 */
5832 #define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk
5833 #define CRYP_SR_BUSY_Pos                 (4U)
5834 #define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)            /*!< 0x00000010 */
5835 #define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk
5836 /****************** Bits definition for CRYP_DMACR register  ******************/
5837 #define CRYP_DMACR_DIEN_Pos              (0U)
5838 #define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)         /*!< 0x00000001 */
5839 #define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk
5840 #define CRYP_DMACR_DOEN_Pos              (1U)
5841 #define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)         /*!< 0x00000002 */
5842 #define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk
5843 /*****************  Bits definition for CRYP_IMSCR register  ******************/
5844 #define CRYP_IMSCR_INIM_Pos              (0U)
5845 #define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)         /*!< 0x00000001 */
5846 #define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk
5847 #define CRYP_IMSCR_OUTIM_Pos             (1U)
5848 #define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)        /*!< 0x00000002 */
5849 #define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk
5850 /****************** Bits definition for CRYP_RISR register  *******************/
5851 #define CRYP_RISR_OUTRIS_Pos             (0U)
5852 #define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)        /*!< 0x00000001 */
5853 #define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk
5854 #define CRYP_RISR_INRIS_Pos              (1U)
5855 #define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)         /*!< 0x00000002 */
5856 #define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk
5857 /****************** Bits definition for CRYP_MISR register  *******************/
5858 #define CRYP_MISR_INMIS_Pos              (0U)
5859 #define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)         /*!< 0x00000001 */
5860 #define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk
5861 #define CRYP_MISR_OUTMIS_Pos             (1U)
5862 #define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)        /*!< 0x00000002 */
5863 #define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk
5864 
5865 /******************************************************************************/
5866 /*                                                                            */
5867 /*                      Digital to Analog Converter                           */
5868 /*                                                                            */
5869 /******************************************************************************/
5870 /********************  Bit definition for DAC_CR register  ********************/
5871 #define DAC_CR_EN1_Pos              (0U)
5872 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
5873 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable                         */
5874 #define DAC_CR_BOFF1_Pos            (1U)
5875 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
5876 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable          */
5877 #define DAC_CR_TEN1_Pos             (2U)
5878 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
5879 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable                 */
5880 #define DAC_CR_TSEL1_Pos            (3U)
5881 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
5882 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5883 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5884 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5885 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5886 #define DAC_CR_WAVE1_Pos            (6U)
5887 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
5888 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
5889 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5890 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5891 #define DAC_CR_MAMP1_Pos            (8U)
5892 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
5893 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5894 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5895 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5896 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5897 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5898 #define DAC_CR_DMAEN1_Pos           (12U)
5899 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
5900 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable                     */
5901 #define DAC_CR_DMAUDRIE1_Pos        (13U)
5902 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
5903 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable  */
5904 #define DAC_CR_EN2_Pos              (16U)
5905 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
5906 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable                         */
5907 #define DAC_CR_BOFF2_Pos            (17U)
5908 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
5909 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable          */
5910 #define DAC_CR_TEN2_Pos             (18U)
5911 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
5912 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable                 */
5913 #define DAC_CR_TSEL2_Pos            (19U)
5914 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
5915 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5916 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5917 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5918 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5919 #define DAC_CR_WAVE2_Pos            (22U)
5920 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
5921 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5922 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5923 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5924 #define DAC_CR_MAMP2_Pos            (24U)
5925 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
5926 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5927 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5928 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5929 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5930 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5931 #define DAC_CR_DMAEN2_Pos           (28U)
5932 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
5933 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enable                    */
5934 #define DAC_CR_DMAUDRIE2_Pos        (29U)
5935 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
5936 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable */
5937 
5938 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5939 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5940 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
5941 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5942 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5943 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
5944 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5945 
5946 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5947 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5948 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
5949 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5950 
5951 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5952 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5953 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5954 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5955 
5956 /******************  Bit definition for DAC_DHR8R1 register  ******************/
5957 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5958 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
5959 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5960 
5961 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5962 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5963 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
5964 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5965 
5966 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5967 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5968 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
5969 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5970 
5971 /******************  Bit definition for DAC_DHR8R2 register  ******************/
5972 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5973 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
5974 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5975 
5976 /*****************  Bit definition for DAC_DHR12RD register  ******************/
5977 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5978 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
5979 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5980 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5981 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
5982 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5983 
5984 /*****************  Bit definition for DAC_DHR12LD register  ******************/
5985 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5986 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5987 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5988 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5989 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
5990 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5991 
5992 /******************  Bit definition for DAC_DHR8RD register  ******************/
5993 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5994 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
5995 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5996 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5997 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
5998 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5999 
6000 /*******************  Bit definition for DAC_DOR1 register  *******************/
6001 #define DAC_DOR1_DACC1DOR_Pos       (0U)
6002 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
6003 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
6004 
6005 /*******************  Bit definition for DAC_DOR2 register  *******************/
6006 #define DAC_DOR2_DACC2DOR_Pos       (0U)
6007 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
6008 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
6009 
6010 /********************  Bit definition for DAC_SR register  ********************/
6011 #define DAC_SR_DMAUDR1_Pos          (13U)
6012 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
6013 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
6014 #define DAC_SR_DMAUDR2_Pos          (29U)
6015 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
6016 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
6017 
6018 
6019 /******************************************************************************/
6020 /*                                                                            */
6021 /*                                 Debug MCU                                  */
6022 /*                                                                            */
6023 /******************************************************************************/
6024 
6025 /******************************************************************************/
6026 /*                                                                            */
6027 /*                                    DCMI                                    */
6028 /*                                                                            */
6029 /******************************************************************************/
6030 /********************  Bits definition for DCMI_CR register  ******************/
6031 #define DCMI_CR_CAPTURE_Pos        (0U)
6032 #define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
6033 #define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
6034 #define DCMI_CR_CM_Pos             (1U)
6035 #define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
6036 #define DCMI_CR_CM                 DCMI_CR_CM_Msk
6037 #define DCMI_CR_CROP_Pos           (2U)
6038 #define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
6039 #define DCMI_CR_CROP               DCMI_CR_CROP_Msk
6040 #define DCMI_CR_JPEG_Pos           (3U)
6041 #define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
6042 #define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
6043 #define DCMI_CR_ESS_Pos            (4U)
6044 #define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
6045 #define DCMI_CR_ESS                DCMI_CR_ESS_Msk
6046 #define DCMI_CR_PCKPOL_Pos         (5U)
6047 #define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
6048 #define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
6049 #define DCMI_CR_HSPOL_Pos          (6U)
6050 #define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
6051 #define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
6052 #define DCMI_CR_VSPOL_Pos          (7U)
6053 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
6054 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
6055 #define DCMI_CR_FCRC_0             0x00000100U
6056 #define DCMI_CR_FCRC_1             0x00000200U
6057 #define DCMI_CR_EDM_0              0x00000400U
6058 #define DCMI_CR_EDM_1              0x00000800U
6059 #define DCMI_CR_CRE_Pos            (12U)
6060 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                   /*!< 0x00001000 */
6061 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
6062 #define DCMI_CR_ENABLE_Pos         (14U)
6063 #define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
6064 #define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
6065 #define DCMI_CR_BSM_Pos            (16U)
6066 #define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                   /*!< 0x00030000 */
6067 #define DCMI_CR_BSM                DCMI_CR_BSM_Msk
6068 #define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
6069 #define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
6070 #define DCMI_CR_OEBS_Pos           (18U)
6071 #define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                  /*!< 0x00040000 */
6072 #define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
6073 #define DCMI_CR_LSM_Pos            (19U)
6074 #define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                   /*!< 0x00080000 */
6075 #define DCMI_CR_LSM                DCMI_CR_LSM_Msk
6076 #define DCMI_CR_OELS_Pos           (20U)
6077 #define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                  /*!< 0x00100000 */
6078 #define DCMI_CR_OELS               DCMI_CR_OELS_Msk
6079 
6080 /********************  Bits definition for DCMI_SR register  ******************/
6081 #define DCMI_SR_HSYNC_Pos          (0U)
6082 #define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
6083 #define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
6084 #define DCMI_SR_VSYNC_Pos          (1U)
6085 #define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
6086 #define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
6087 #define DCMI_SR_FNE_Pos            (2U)
6088 #define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
6089 #define DCMI_SR_FNE                DCMI_SR_FNE_Msk
6090 
6091 /********************  Bits definition for DCMI_RIS register   ****************/
6092 #define DCMI_RIS_FRAME_RIS_Pos     (0U)
6093 #define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
6094 #define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
6095 #define DCMI_RIS_OVR_RIS_Pos       (1U)
6096 #define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
6097 #define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
6098 #define DCMI_RIS_ERR_RIS_Pos       (2U)
6099 #define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
6100 #define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
6101 #define DCMI_RIS_VSYNC_RIS_Pos     (3U)
6102 #define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
6103 #define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
6104 #define DCMI_RIS_LINE_RIS_Pos      (4U)
6105 #define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
6106 #define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
6107 
6108 /* Legacy defines */
6109 #define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
6110 #define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
6111 #define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
6112 #define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
6113 #define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
6114 
6115 /********************  Bits definition for DCMI_IER register  *****************/
6116 #define DCMI_IER_FRAME_IE_Pos      (0U)
6117 #define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
6118 #define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
6119 #define DCMI_IER_OVR_IE_Pos        (1U)
6120 #define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
6121 #define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
6122 #define DCMI_IER_ERR_IE_Pos        (2U)
6123 #define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
6124 #define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
6125 #define DCMI_IER_VSYNC_IE_Pos      (3U)
6126 #define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
6127 #define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
6128 #define DCMI_IER_LINE_IE_Pos       (4U)
6129 #define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
6130 #define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
6131 
6132 /* Legacy define */
6133 #define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
6134 
6135 /********************  Bits definition for DCMI_MIS register  *****************/
6136 #define DCMI_MIS_FRAME_MIS_Pos     (0U)
6137 #define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
6138 #define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
6139 #define DCMI_MIS_OVR_MIS_Pos       (1U)
6140 #define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
6141 #define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
6142 #define DCMI_MIS_ERR_MIS_Pos       (2U)
6143 #define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
6144 #define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
6145 #define DCMI_MIS_VSYNC_MIS_Pos     (3U)
6146 #define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
6147 #define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
6148 #define DCMI_MIS_LINE_MIS_Pos      (4U)
6149 #define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
6150 #define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
6151 
6152 /* Legacy defines */
6153 #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
6154 #define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
6155 #define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
6156 #define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
6157 #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
6158 
6159 /********************  Bits definition for DCMI_ICR register  *****************/
6160 #define DCMI_ICR_FRAME_ISC_Pos     (0U)
6161 #define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
6162 #define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
6163 #define DCMI_ICR_OVR_ISC_Pos       (1U)
6164 #define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
6165 #define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
6166 #define DCMI_ICR_ERR_ISC_Pos       (2U)
6167 #define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
6168 #define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
6169 #define DCMI_ICR_VSYNC_ISC_Pos     (3U)
6170 #define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
6171 #define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
6172 #define DCMI_ICR_LINE_ISC_Pos      (4U)
6173 #define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
6174 #define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
6175 
6176 /* Legacy defines */
6177 #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
6178 
6179 /********************  Bits definition for DCMI_ESCR register  ******************/
6180 #define DCMI_ESCR_FSC_Pos          (0U)
6181 #define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
6182 #define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
6183 #define DCMI_ESCR_LSC_Pos          (8U)
6184 #define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
6185 #define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
6186 #define DCMI_ESCR_LEC_Pos          (16U)
6187 #define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
6188 #define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
6189 #define DCMI_ESCR_FEC_Pos          (24U)
6190 #define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
6191 #define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
6192 
6193 /********************  Bits definition for DCMI_ESUR register  ******************/
6194 #define DCMI_ESUR_FSU_Pos          (0U)
6195 #define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
6196 #define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
6197 #define DCMI_ESUR_LSU_Pos          (8U)
6198 #define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
6199 #define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
6200 #define DCMI_ESUR_LEU_Pos          (16U)
6201 #define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
6202 #define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
6203 #define DCMI_ESUR_FEU_Pos          (24U)
6204 #define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
6205 #define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
6206 
6207 /********************  Bits definition for DCMI_CWSTRT register  ******************/
6208 #define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
6209 #define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
6210 #define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
6211 #define DCMI_CWSTRT_VST_Pos        (16U)
6212 #define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
6213 #define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
6214 
6215 /********************  Bits definition for DCMI_CWSIZE register  ******************/
6216 #define DCMI_CWSIZE_CAPCNT_Pos     (0U)
6217 #define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
6218 #define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
6219 #define DCMI_CWSIZE_VLINE_Pos      (16U)
6220 #define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
6221 #define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
6222 
6223 /********************  Bits definition for DCMI_DR register  ******************/
6224 #define DCMI_DR_BYTE0_Pos          (0U)
6225 #define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
6226 #define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
6227 #define DCMI_DR_BYTE1_Pos          (8U)
6228 #define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
6229 #define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
6230 #define DCMI_DR_BYTE2_Pos          (16U)
6231 #define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
6232 #define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
6233 #define DCMI_DR_BYTE3_Pos          (24U)
6234 #define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
6235 #define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
6236 
6237 /******************************************************************************/
6238 /*                                                                            */
6239 /*                             DMA Controller                                 */
6240 /*                                                                            */
6241 /******************************************************************************/
6242 /********************  Bits definition for DMA_SxCR register  *****************/
6243 #define DMA_SxCR_CHSEL_Pos       (25U)
6244 #define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
6245 #define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk
6246 #define DMA_SxCR_CHSEL_0         (0x1UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x02000000 */
6247 #define DMA_SxCR_CHSEL_1         (0x2UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x04000000 */
6248 #define DMA_SxCR_CHSEL_2         (0x4UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x08000000 */
6249 #define DMA_SxCR_MBURST_Pos      (23U)
6250 #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
6251 #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
6252 #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
6253 #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
6254 #define DMA_SxCR_PBURST_Pos      (21U)
6255 #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
6256 #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
6257 #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
6258 #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
6259 #define DMA_SxCR_CT_Pos          (19U)
6260 #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
6261 #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
6262 #define DMA_SxCR_DBM_Pos         (18U)
6263 #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
6264 #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
6265 #define DMA_SxCR_PL_Pos          (16U)
6266 #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
6267 #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
6268 #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
6269 #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
6270 #define DMA_SxCR_PINCOS_Pos      (15U)
6271 #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
6272 #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
6273 #define DMA_SxCR_MSIZE_Pos       (13U)
6274 #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
6275 #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
6276 #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
6277 #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
6278 #define DMA_SxCR_PSIZE_Pos       (11U)
6279 #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
6280 #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
6281 #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
6282 #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
6283 #define DMA_SxCR_MINC_Pos        (10U)
6284 #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
6285 #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
6286 #define DMA_SxCR_PINC_Pos        (9U)
6287 #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
6288 #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
6289 #define DMA_SxCR_CIRC_Pos        (8U)
6290 #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
6291 #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
6292 #define DMA_SxCR_DIR_Pos         (6U)
6293 #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
6294 #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
6295 #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
6296 #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
6297 #define DMA_SxCR_PFCTRL_Pos      (5U)
6298 #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
6299 #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
6300 #define DMA_SxCR_TCIE_Pos        (4U)
6301 #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
6302 #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
6303 #define DMA_SxCR_HTIE_Pos        (3U)
6304 #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
6305 #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
6306 #define DMA_SxCR_TEIE_Pos        (2U)
6307 #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
6308 #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
6309 #define DMA_SxCR_DMEIE_Pos       (1U)
6310 #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
6311 #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
6312 #define DMA_SxCR_EN_Pos          (0U)
6313 #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
6314 #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
6315 
6316 /********************  Bits definition for DMA_SxCNDTR register  **************/
6317 #define DMA_SxNDT_Pos            (0U)
6318 #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
6319 #define DMA_SxNDT                DMA_SxNDT_Msk
6320 #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
6321 #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
6322 #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
6323 #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
6324 #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
6325 #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
6326 #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
6327 #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
6328 #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
6329 #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
6330 #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
6331 #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
6332 #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
6333 #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
6334 #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
6335 #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
6336 
6337 /********************  Bits definition for DMA_SxFCR register  ****************/
6338 #define DMA_SxFCR_FEIE_Pos       (7U)
6339 #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
6340 #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
6341 #define DMA_SxFCR_FS_Pos         (3U)
6342 #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
6343 #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
6344 #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
6345 #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
6346 #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
6347 #define DMA_SxFCR_DMDIS_Pos      (2U)
6348 #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
6349 #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
6350 #define DMA_SxFCR_FTH_Pos        (0U)
6351 #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
6352 #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
6353 #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
6354 #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
6355 
6356 /********************  Bits definition for DMA_LISR register  *****************/
6357 #define DMA_LISR_TCIF3_Pos       (27U)
6358 #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
6359 #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
6360 #define DMA_LISR_HTIF3_Pos       (26U)
6361 #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
6362 #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
6363 #define DMA_LISR_TEIF3_Pos       (25U)
6364 #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
6365 #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
6366 #define DMA_LISR_DMEIF3_Pos      (24U)
6367 #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
6368 #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
6369 #define DMA_LISR_FEIF3_Pos       (22U)
6370 #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
6371 #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
6372 #define DMA_LISR_TCIF2_Pos       (21U)
6373 #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
6374 #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
6375 #define DMA_LISR_HTIF2_Pos       (20U)
6376 #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
6377 #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
6378 #define DMA_LISR_TEIF2_Pos       (19U)
6379 #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
6380 #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
6381 #define DMA_LISR_DMEIF2_Pos      (18U)
6382 #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
6383 #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
6384 #define DMA_LISR_FEIF2_Pos       (16U)
6385 #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
6386 #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
6387 #define DMA_LISR_TCIF1_Pos       (11U)
6388 #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
6389 #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
6390 #define DMA_LISR_HTIF1_Pos       (10U)
6391 #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
6392 #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
6393 #define DMA_LISR_TEIF1_Pos       (9U)
6394 #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
6395 #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
6396 #define DMA_LISR_DMEIF1_Pos      (8U)
6397 #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
6398 #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
6399 #define DMA_LISR_FEIF1_Pos       (6U)
6400 #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
6401 #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
6402 #define DMA_LISR_TCIF0_Pos       (5U)
6403 #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
6404 #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
6405 #define DMA_LISR_HTIF0_Pos       (4U)
6406 #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
6407 #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
6408 #define DMA_LISR_TEIF0_Pos       (3U)
6409 #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
6410 #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
6411 #define DMA_LISR_DMEIF0_Pos      (2U)
6412 #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
6413 #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
6414 #define DMA_LISR_FEIF0_Pos       (0U)
6415 #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
6416 #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
6417 
6418 /********************  Bits definition for DMA_HISR register  *****************/
6419 #define DMA_HISR_TCIF7_Pos       (27U)
6420 #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
6421 #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
6422 #define DMA_HISR_HTIF7_Pos       (26U)
6423 #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
6424 #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
6425 #define DMA_HISR_TEIF7_Pos       (25U)
6426 #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
6427 #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
6428 #define DMA_HISR_DMEIF7_Pos      (24U)
6429 #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
6430 #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
6431 #define DMA_HISR_FEIF7_Pos       (22U)
6432 #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
6433 #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
6434 #define DMA_HISR_TCIF6_Pos       (21U)
6435 #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
6436 #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
6437 #define DMA_HISR_HTIF6_Pos       (20U)
6438 #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
6439 #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
6440 #define DMA_HISR_TEIF6_Pos       (19U)
6441 #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
6442 #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
6443 #define DMA_HISR_DMEIF6_Pos      (18U)
6444 #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
6445 #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
6446 #define DMA_HISR_FEIF6_Pos       (16U)
6447 #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
6448 #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
6449 #define DMA_HISR_TCIF5_Pos       (11U)
6450 #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
6451 #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
6452 #define DMA_HISR_HTIF5_Pos       (10U)
6453 #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
6454 #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
6455 #define DMA_HISR_TEIF5_Pos       (9U)
6456 #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
6457 #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
6458 #define DMA_HISR_DMEIF5_Pos      (8U)
6459 #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
6460 #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
6461 #define DMA_HISR_FEIF5_Pos       (6U)
6462 #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
6463 #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
6464 #define DMA_HISR_TCIF4_Pos       (5U)
6465 #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
6466 #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
6467 #define DMA_HISR_HTIF4_Pos       (4U)
6468 #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
6469 #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
6470 #define DMA_HISR_TEIF4_Pos       (3U)
6471 #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
6472 #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
6473 #define DMA_HISR_DMEIF4_Pos      (2U)
6474 #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
6475 #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
6476 #define DMA_HISR_FEIF4_Pos       (0U)
6477 #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
6478 #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
6479 
6480 /********************  Bits definition for DMA_LIFCR register  ****************/
6481 #define DMA_LIFCR_CTCIF3_Pos     (27U)
6482 #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
6483 #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
6484 #define DMA_LIFCR_CHTIF3_Pos     (26U)
6485 #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
6486 #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
6487 #define DMA_LIFCR_CTEIF3_Pos     (25U)
6488 #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
6489 #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
6490 #define DMA_LIFCR_CDMEIF3_Pos    (24U)
6491 #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
6492 #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
6493 #define DMA_LIFCR_CFEIF3_Pos     (22U)
6494 #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
6495 #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
6496 #define DMA_LIFCR_CTCIF2_Pos     (21U)
6497 #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
6498 #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
6499 #define DMA_LIFCR_CHTIF2_Pos     (20U)
6500 #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
6501 #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
6502 #define DMA_LIFCR_CTEIF2_Pos     (19U)
6503 #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
6504 #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
6505 #define DMA_LIFCR_CDMEIF2_Pos    (18U)
6506 #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
6507 #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
6508 #define DMA_LIFCR_CFEIF2_Pos     (16U)
6509 #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
6510 #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
6511 #define DMA_LIFCR_CTCIF1_Pos     (11U)
6512 #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
6513 #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
6514 #define DMA_LIFCR_CHTIF1_Pos     (10U)
6515 #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
6516 #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
6517 #define DMA_LIFCR_CTEIF1_Pos     (9U)
6518 #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
6519 #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
6520 #define DMA_LIFCR_CDMEIF1_Pos    (8U)
6521 #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
6522 #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
6523 #define DMA_LIFCR_CFEIF1_Pos     (6U)
6524 #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
6525 #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
6526 #define DMA_LIFCR_CTCIF0_Pos     (5U)
6527 #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
6528 #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
6529 #define DMA_LIFCR_CHTIF0_Pos     (4U)
6530 #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
6531 #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
6532 #define DMA_LIFCR_CTEIF0_Pos     (3U)
6533 #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
6534 #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
6535 #define DMA_LIFCR_CDMEIF0_Pos    (2U)
6536 #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
6537 #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
6538 #define DMA_LIFCR_CFEIF0_Pos     (0U)
6539 #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
6540 #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
6541 
6542 /********************  Bits definition for DMA_HIFCR  register  ****************/
6543 #define DMA_HIFCR_CTCIF7_Pos     (27U)
6544 #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
6545 #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
6546 #define DMA_HIFCR_CHTIF7_Pos     (26U)
6547 #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
6548 #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
6549 #define DMA_HIFCR_CTEIF7_Pos     (25U)
6550 #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
6551 #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
6552 #define DMA_HIFCR_CDMEIF7_Pos    (24U)
6553 #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
6554 #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
6555 #define DMA_HIFCR_CFEIF7_Pos     (22U)
6556 #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
6557 #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
6558 #define DMA_HIFCR_CTCIF6_Pos     (21U)
6559 #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
6560 #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
6561 #define DMA_HIFCR_CHTIF6_Pos     (20U)
6562 #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
6563 #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
6564 #define DMA_HIFCR_CTEIF6_Pos     (19U)
6565 #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
6566 #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
6567 #define DMA_HIFCR_CDMEIF6_Pos    (18U)
6568 #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
6569 #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
6570 #define DMA_HIFCR_CFEIF6_Pos     (16U)
6571 #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
6572 #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
6573 #define DMA_HIFCR_CTCIF5_Pos     (11U)
6574 #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
6575 #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
6576 #define DMA_HIFCR_CHTIF5_Pos     (10U)
6577 #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
6578 #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
6579 #define DMA_HIFCR_CTEIF5_Pos     (9U)
6580 #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
6581 #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
6582 #define DMA_HIFCR_CDMEIF5_Pos    (8U)
6583 #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
6584 #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
6585 #define DMA_HIFCR_CFEIF5_Pos     (6U)
6586 #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
6587 #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
6588 #define DMA_HIFCR_CTCIF4_Pos     (5U)
6589 #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
6590 #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
6591 #define DMA_HIFCR_CHTIF4_Pos     (4U)
6592 #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
6593 #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
6594 #define DMA_HIFCR_CTEIF4_Pos     (3U)
6595 #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
6596 #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
6597 #define DMA_HIFCR_CDMEIF4_Pos    (2U)
6598 #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
6599 #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
6600 #define DMA_HIFCR_CFEIF4_Pos     (0U)
6601 #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
6602 #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
6603 
6604 /******************  Bit definition for DMA_SxPAR register  ********************/
6605 #define DMA_SxPAR_PA_Pos         (0U)
6606 #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
6607 #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
6608 
6609 /******************  Bit definition for DMA_SxM0AR register  ********************/
6610 #define DMA_SxM0AR_M0A_Pos       (0U)
6611 #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
6612 #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
6613 
6614 /******************  Bit definition for DMA_SxM1AR register  ********************/
6615 #define DMA_SxM1AR_M1A_Pos       (0U)
6616 #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
6617 #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
6618 
6619 /******************************************************************************/
6620 /*                                                                            */
6621 /*                         AHB Master DMA2D Controller (DMA2D)                */
6622 /*                                                                            */
6623 /******************************************************************************/
6624 /********************  Bit definition for DMA2D_CR register  ******************/
6625 
6626 #define DMA2D_CR_START_Pos         (0U)
6627 #define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)                /*!< 0x00000001 */
6628 #define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */
6629 #define DMA2D_CR_SUSP_Pos          (1U)
6630 #define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */
6631 #define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */
6632 #define DMA2D_CR_ABORT_Pos         (2U)
6633 #define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */
6634 #define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */
6635 #define DMA2D_CR_TEIE_Pos          (8U)
6636 #define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */
6637 #define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */
6638 #define DMA2D_CR_TCIE_Pos          (9U)
6639 #define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */
6640 #define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */
6641 #define DMA2D_CR_TWIE_Pos          (10U)
6642 #define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */
6643 #define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */
6644 #define DMA2D_CR_CAEIE_Pos         (11U)
6645 #define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */
6646 #define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */
6647 #define DMA2D_CR_CTCIE_Pos         (12U)
6648 #define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */
6649 #define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
6650 #define DMA2D_CR_CEIE_Pos          (13U)
6651 #define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */
6652 #define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */
6653 #define DMA2D_CR_MODE_Pos          (16U)
6654 #define DMA2D_CR_MODE_Msk          (0x3UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */
6655 #define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0]                         */
6656 #define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
6657 #define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
6658 
6659 /********************  Bit definition for DMA2D_ISR register  *****************/
6660 
6661 #define DMA2D_ISR_TEIF_Pos         (0U)
6662 #define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */
6663 #define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */
6664 #define DMA2D_ISR_TCIF_Pos         (1U)
6665 #define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */
6666 #define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */
6667 #define DMA2D_ISR_TWIF_Pos         (2U)
6668 #define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */
6669 #define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */
6670 #define DMA2D_ISR_CAEIF_Pos        (3U)
6671 #define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */
6672 #define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */
6673 #define DMA2D_ISR_CTCIF_Pos        (4U)
6674 #define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */
6675 #define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
6676 #define DMA2D_ISR_CEIF_Pos         (5U)
6677 #define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */
6678 #define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */
6679 
6680 /********************  Bit definition for DMA2D_IFCR register  ****************/
6681 
6682 #define DMA2D_IFCR_CTEIF_Pos       (0U)
6683 #define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */
6684 #define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
6685 #define DMA2D_IFCR_CTCIF_Pos       (1U)
6686 #define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */
6687 #define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
6688 #define DMA2D_IFCR_CTWIF_Pos       (2U)
6689 #define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */
6690 #define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
6691 #define DMA2D_IFCR_CAECIF_Pos      (3U)
6692 #define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */
6693 #define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
6694 #define DMA2D_IFCR_CCTCIF_Pos      (4U)
6695 #define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */
6696 #define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
6697 #define DMA2D_IFCR_CCEIF_Pos       (5U)
6698 #define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */
6699 #define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
6700 
6701 /* Legacy defines */
6702 #define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
6703 #define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
6704 #define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
6705 #define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
6706 #define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
6707 #define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
6708 
6709 /********************  Bit definition for DMA2D_FGMAR register  ***************/
6710 
6711 #define DMA2D_FGMAR_MA_Pos         (0U)
6712 #define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
6713 #define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
6714 
6715 /********************  Bit definition for DMA2D_FGOR register  ****************/
6716 
6717 #define DMA2D_FGOR_LO_Pos          (0U)
6718 #define DMA2D_FGOR_LO_Msk          (0x3FFFUL << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */
6719 #define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
6720 
6721 /********************  Bit definition for DMA2D_BGMAR register  ***************/
6722 
6723 #define DMA2D_BGMAR_MA_Pos         (0U)
6724 #define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
6725 #define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
6726 
6727 /********************  Bit definition for DMA2D_BGOR register  ****************/
6728 
6729 #define DMA2D_BGOR_LO_Pos          (0U)
6730 #define DMA2D_BGOR_LO_Msk          (0x3FFFUL << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */
6731 #define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
6732 
6733 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
6734 
6735 #define DMA2D_FGPFCCR_CM_Pos       (0U)
6736 #define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */
6737 #define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
6738 #define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
6739 #define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
6740 #define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
6741 #define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
6742 #define DMA2D_FGPFCCR_CCM_Pos      (4U)
6743 #define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */
6744 #define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
6745 #define DMA2D_FGPFCCR_START_Pos    (5U)
6746 #define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */
6747 #define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
6748 #define DMA2D_FGPFCCR_CS_Pos       (8U)
6749 #define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
6750 #define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
6751 #define DMA2D_FGPFCCR_AM_Pos       (16U)
6752 #define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */
6753 #define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
6754 #define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
6755 #define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
6756 #define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
6757 #define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
6758 #define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
6759 
6760 /********************  Bit definition for DMA2D_FGCOLR register  **************/
6761 
6762 #define DMA2D_FGCOLR_BLUE_Pos      (0U)
6763 #define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */
6764 #define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
6765 #define DMA2D_FGCOLR_GREEN_Pos     (8U)
6766 #define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
6767 #define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
6768 #define DMA2D_FGCOLR_RED_Pos       (16U)
6769 #define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */
6770 #define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
6771 
6772 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
6773 
6774 #define DMA2D_BGPFCCR_CM_Pos       (0U)
6775 #define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */
6776 #define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
6777 #define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
6778 #define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
6779 #define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
6780 #define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */
6781 #define DMA2D_BGPFCCR_CCM_Pos      (4U)
6782 #define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */
6783 #define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
6784 #define DMA2D_BGPFCCR_START_Pos    (5U)
6785 #define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */
6786 #define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
6787 #define DMA2D_BGPFCCR_CS_Pos       (8U)
6788 #define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
6789 #define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
6790 #define DMA2D_BGPFCCR_AM_Pos       (16U)
6791 #define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */
6792 #define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
6793 #define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
6794 #define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
6795 #define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
6796 #define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
6797 #define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
6798 
6799 /********************  Bit definition for DMA2D_BGCOLR register  **************/
6800 
6801 #define DMA2D_BGCOLR_BLUE_Pos      (0U)
6802 #define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */
6803 #define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
6804 #define DMA2D_BGCOLR_GREEN_Pos     (8U)
6805 #define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
6806 #define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
6807 #define DMA2D_BGCOLR_RED_Pos       (16U)
6808 #define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */
6809 #define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
6810 
6811 /********************  Bit definition for DMA2D_FGCMAR register  **************/
6812 
6813 #define DMA2D_FGCMAR_MA_Pos        (0U)
6814 #define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
6815 #define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
6816 
6817 /********************  Bit definition for DMA2D_BGCMAR register  **************/
6818 
6819 #define DMA2D_BGCMAR_MA_Pos        (0U)
6820 #define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
6821 #define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
6822 
6823 /********************  Bit definition for DMA2D_OPFCCR register  **************/
6824 
6825 #define DMA2D_OPFCCR_CM_Pos        (0U)
6826 #define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */
6827 #define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
6828 #define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */
6829 #define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */
6830 #define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */
6831 
6832 /********************  Bit definition for DMA2D_OCOLR register  ***************/
6833 
6834 /*!<Mode_ARGB8888/RGB888 */
6835 
6836 #define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */
6837 #define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */
6838 #define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */
6839 #define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */
6840 
6841 /*!<Mode_RGB565 */
6842 #define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */
6843 #define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */
6844 #define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */
6845 
6846 /*!<Mode_ARGB1555 */
6847 #define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */
6848 #define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */
6849 #define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */
6850 #define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */
6851 
6852 /*!<Mode_ARGB4444 */
6853 #define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */
6854 #define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */
6855 #define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */
6856 #define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */
6857 
6858 /********************  Bit definition for DMA2D_OMAR register  ****************/
6859 
6860 #define DMA2D_OMAR_MA_Pos          (0U)
6861 #define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */
6862 #define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
6863 
6864 /********************  Bit definition for DMA2D_OOR register  *****************/
6865 
6866 #define DMA2D_OOR_LO_Pos           (0U)
6867 #define DMA2D_OOR_LO_Msk           (0x3FFFUL << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */
6868 #define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
6869 
6870 /********************  Bit definition for DMA2D_NLR register  *****************/
6871 
6872 #define DMA2D_NLR_NL_Pos           (0U)
6873 #define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */
6874 #define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
6875 #define DMA2D_NLR_PL_Pos           (16U)
6876 #define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */
6877 #define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
6878 
6879 /********************  Bit definition for DMA2D_LWR register  *****************/
6880 
6881 #define DMA2D_LWR_LW_Pos           (0U)
6882 #define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */
6883 #define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
6884 
6885 /********************  Bit definition for DMA2D_AMTCR register  ***************/
6886 
6887 #define DMA2D_AMTCR_EN_Pos         (0U)
6888 #define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */
6889 #define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
6890 #define DMA2D_AMTCR_DT_Pos         (8U)
6891 #define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
6892 #define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
6893 
6894 
6895 /********************  Bit definition for DMA2D_FGCLUT register  **************/
6896 
6897 /********************  Bit definition for DMA2D_BGCLUT register  **************/
6898 
6899 /******************************************************************************/
6900 /*                                                                            */
6901 /*                    External Interrupt/Event Controller                     */
6902 /*                                                                            */
6903 /******************************************************************************/
6904 /*******************  Bit definition for EXTI_IMR register  *******************/
6905 #define EXTI_IMR_MR0_Pos          (0U)
6906 #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
6907 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
6908 #define EXTI_IMR_MR1_Pos          (1U)
6909 #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
6910 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
6911 #define EXTI_IMR_MR2_Pos          (2U)
6912 #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
6913 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
6914 #define EXTI_IMR_MR3_Pos          (3U)
6915 #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
6916 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
6917 #define EXTI_IMR_MR4_Pos          (4U)
6918 #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
6919 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
6920 #define EXTI_IMR_MR5_Pos          (5U)
6921 #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
6922 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
6923 #define EXTI_IMR_MR6_Pos          (6U)
6924 #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
6925 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
6926 #define EXTI_IMR_MR7_Pos          (7U)
6927 #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
6928 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
6929 #define EXTI_IMR_MR8_Pos          (8U)
6930 #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
6931 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
6932 #define EXTI_IMR_MR9_Pos          (9U)
6933 #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
6934 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
6935 #define EXTI_IMR_MR10_Pos         (10U)
6936 #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
6937 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
6938 #define EXTI_IMR_MR11_Pos         (11U)
6939 #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
6940 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
6941 #define EXTI_IMR_MR12_Pos         (12U)
6942 #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
6943 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
6944 #define EXTI_IMR_MR13_Pos         (13U)
6945 #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
6946 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
6947 #define EXTI_IMR_MR14_Pos         (14U)
6948 #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
6949 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
6950 #define EXTI_IMR_MR15_Pos         (15U)
6951 #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
6952 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
6953 #define EXTI_IMR_MR16_Pos         (16U)
6954 #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
6955 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
6956 #define EXTI_IMR_MR17_Pos         (17U)
6957 #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
6958 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
6959 #define EXTI_IMR_MR18_Pos         (18U)
6960 #define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
6961 #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
6962 #define EXTI_IMR_MR19_Pos         (19U)
6963 #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
6964 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
6965 #define EXTI_IMR_MR20_Pos         (20U)
6966 #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
6967 #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
6968 #define EXTI_IMR_MR21_Pos         (21U)
6969 #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
6970 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
6971 #define EXTI_IMR_MR22_Pos         (22U)
6972 #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
6973 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
6974 #define EXTI_IMR_MR23_Pos         (23U)
6975 #define EXTI_IMR_MR23_Msk         (0x1UL << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */
6976 #define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */
6977 
6978 /* Reference Defines */
6979 #define  EXTI_IMR_IM0                        EXTI_IMR_MR0
6980 #define  EXTI_IMR_IM1                        EXTI_IMR_MR1
6981 #define  EXTI_IMR_IM2                        EXTI_IMR_MR2
6982 #define  EXTI_IMR_IM3                        EXTI_IMR_MR3
6983 #define  EXTI_IMR_IM4                        EXTI_IMR_MR4
6984 #define  EXTI_IMR_IM5                        EXTI_IMR_MR5
6985 #define  EXTI_IMR_IM6                        EXTI_IMR_MR6
6986 #define  EXTI_IMR_IM7                        EXTI_IMR_MR7
6987 #define  EXTI_IMR_IM8                        EXTI_IMR_MR8
6988 #define  EXTI_IMR_IM9                        EXTI_IMR_MR9
6989 #define  EXTI_IMR_IM10                       EXTI_IMR_MR10
6990 #define  EXTI_IMR_IM11                       EXTI_IMR_MR11
6991 #define  EXTI_IMR_IM12                       EXTI_IMR_MR12
6992 #define  EXTI_IMR_IM13                       EXTI_IMR_MR13
6993 #define  EXTI_IMR_IM14                       EXTI_IMR_MR14
6994 #define  EXTI_IMR_IM15                       EXTI_IMR_MR15
6995 #define  EXTI_IMR_IM16                       EXTI_IMR_MR16
6996 #define  EXTI_IMR_IM17                       EXTI_IMR_MR17
6997 #define  EXTI_IMR_IM18                       EXTI_IMR_MR18
6998 #define  EXTI_IMR_IM19                       EXTI_IMR_MR19
6999 #define  EXTI_IMR_IM20                       EXTI_IMR_MR20
7000 #define  EXTI_IMR_IM21                       EXTI_IMR_MR21
7001 #define  EXTI_IMR_IM22                       EXTI_IMR_MR22
7002 #define  EXTI_IMR_IM23                       EXTI_IMR_MR23
7003 
7004 #define EXTI_IMR_IM_Pos           (0U)
7005 #define EXTI_IMR_IM_Msk           (0xFFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x00FFFFFF */
7006 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
7007 
7008 /*******************  Bit definition for EXTI_EMR register  *******************/
7009 #define EXTI_EMR_MR0_Pos          (0U)
7010 #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
7011 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
7012 #define EXTI_EMR_MR1_Pos          (1U)
7013 #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
7014 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
7015 #define EXTI_EMR_MR2_Pos          (2U)
7016 #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
7017 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
7018 #define EXTI_EMR_MR3_Pos          (3U)
7019 #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
7020 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
7021 #define EXTI_EMR_MR4_Pos          (4U)
7022 #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
7023 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
7024 #define EXTI_EMR_MR5_Pos          (5U)
7025 #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
7026 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
7027 #define EXTI_EMR_MR6_Pos          (6U)
7028 #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
7029 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
7030 #define EXTI_EMR_MR7_Pos          (7U)
7031 #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
7032 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
7033 #define EXTI_EMR_MR8_Pos          (8U)
7034 #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
7035 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
7036 #define EXTI_EMR_MR9_Pos          (9U)
7037 #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
7038 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
7039 #define EXTI_EMR_MR10_Pos         (10U)
7040 #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
7041 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
7042 #define EXTI_EMR_MR11_Pos         (11U)
7043 #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
7044 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
7045 #define EXTI_EMR_MR12_Pos         (12U)
7046 #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
7047 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
7048 #define EXTI_EMR_MR13_Pos         (13U)
7049 #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
7050 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
7051 #define EXTI_EMR_MR14_Pos         (14U)
7052 #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
7053 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
7054 #define EXTI_EMR_MR15_Pos         (15U)
7055 #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
7056 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
7057 #define EXTI_EMR_MR16_Pos         (16U)
7058 #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
7059 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
7060 #define EXTI_EMR_MR17_Pos         (17U)
7061 #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
7062 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
7063 #define EXTI_EMR_MR18_Pos         (18U)
7064 #define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
7065 #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
7066 #define EXTI_EMR_MR19_Pos         (19U)
7067 #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
7068 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
7069 #define EXTI_EMR_MR20_Pos         (20U)
7070 #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
7071 #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
7072 #define EXTI_EMR_MR21_Pos         (21U)
7073 #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
7074 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
7075 #define EXTI_EMR_MR22_Pos         (22U)
7076 #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
7077 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
7078 #define EXTI_EMR_MR23_Pos         (23U)
7079 #define EXTI_EMR_MR23_Msk         (0x1UL << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */
7080 #define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */
7081 
7082 /* Reference Defines */
7083 #define  EXTI_EMR_EM0                        EXTI_EMR_MR0
7084 #define  EXTI_EMR_EM1                        EXTI_EMR_MR1
7085 #define  EXTI_EMR_EM2                        EXTI_EMR_MR2
7086 #define  EXTI_EMR_EM3                        EXTI_EMR_MR3
7087 #define  EXTI_EMR_EM4                        EXTI_EMR_MR4
7088 #define  EXTI_EMR_EM5                        EXTI_EMR_MR5
7089 #define  EXTI_EMR_EM6                        EXTI_EMR_MR6
7090 #define  EXTI_EMR_EM7                        EXTI_EMR_MR7
7091 #define  EXTI_EMR_EM8                        EXTI_EMR_MR8
7092 #define  EXTI_EMR_EM9                        EXTI_EMR_MR9
7093 #define  EXTI_EMR_EM10                       EXTI_EMR_MR10
7094 #define  EXTI_EMR_EM11                       EXTI_EMR_MR11
7095 #define  EXTI_EMR_EM12                       EXTI_EMR_MR12
7096 #define  EXTI_EMR_EM13                       EXTI_EMR_MR13
7097 #define  EXTI_EMR_EM14                       EXTI_EMR_MR14
7098 #define  EXTI_EMR_EM15                       EXTI_EMR_MR15
7099 #define  EXTI_EMR_EM16                       EXTI_EMR_MR16
7100 #define  EXTI_EMR_EM17                       EXTI_EMR_MR17
7101 #define  EXTI_EMR_EM18                       EXTI_EMR_MR18
7102 #define  EXTI_EMR_EM19                       EXTI_EMR_MR19
7103 #define  EXTI_EMR_EM20                       EXTI_EMR_MR20
7104 #define  EXTI_EMR_EM21                       EXTI_EMR_MR21
7105 #define  EXTI_EMR_EM22                       EXTI_EMR_MR22
7106 #define  EXTI_EMR_EM23                       EXTI_EMR_MR23
7107 
7108 
7109 /******************  Bit definition for EXTI_RTSR register  *******************/
7110 #define EXTI_RTSR_TR0_Pos         (0U)
7111 #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
7112 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
7113 #define EXTI_RTSR_TR1_Pos         (1U)
7114 #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
7115 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
7116 #define EXTI_RTSR_TR2_Pos         (2U)
7117 #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
7118 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
7119 #define EXTI_RTSR_TR3_Pos         (3U)
7120 #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
7121 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
7122 #define EXTI_RTSR_TR4_Pos         (4U)
7123 #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
7124 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
7125 #define EXTI_RTSR_TR5_Pos         (5U)
7126 #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
7127 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
7128 #define EXTI_RTSR_TR6_Pos         (6U)
7129 #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
7130 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
7131 #define EXTI_RTSR_TR7_Pos         (7U)
7132 #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
7133 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
7134 #define EXTI_RTSR_TR8_Pos         (8U)
7135 #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
7136 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
7137 #define EXTI_RTSR_TR9_Pos         (9U)
7138 #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
7139 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
7140 #define EXTI_RTSR_TR10_Pos        (10U)
7141 #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
7142 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
7143 #define EXTI_RTSR_TR11_Pos        (11U)
7144 #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
7145 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
7146 #define EXTI_RTSR_TR12_Pos        (12U)
7147 #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
7148 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
7149 #define EXTI_RTSR_TR13_Pos        (13U)
7150 #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
7151 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
7152 #define EXTI_RTSR_TR14_Pos        (14U)
7153 #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
7154 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
7155 #define EXTI_RTSR_TR15_Pos        (15U)
7156 #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
7157 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
7158 #define EXTI_RTSR_TR16_Pos        (16U)
7159 #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
7160 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
7161 #define EXTI_RTSR_TR17_Pos        (17U)
7162 #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
7163 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
7164 #define EXTI_RTSR_TR18_Pos        (18U)
7165 #define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
7166 #define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
7167 #define EXTI_RTSR_TR19_Pos        (19U)
7168 #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
7169 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
7170 #define EXTI_RTSR_TR20_Pos        (20U)
7171 #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
7172 #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
7173 #define EXTI_RTSR_TR21_Pos        (21U)
7174 #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
7175 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
7176 #define EXTI_RTSR_TR22_Pos        (22U)
7177 #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
7178 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
7179 #define EXTI_RTSR_TR23_Pos        (23U)
7180 #define EXTI_RTSR_TR23_Msk        (0x1UL << EXTI_RTSR_TR23_Pos)                 /*!< 0x00800000 */
7181 #define EXTI_RTSR_TR23            EXTI_RTSR_TR23_Msk                           /*!< Rising trigger event configuration bit of line 23 */
7182 
7183 /******************  Bit definition for EXTI_FTSR register  *******************/
7184 #define EXTI_FTSR_TR0_Pos         (0U)
7185 #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
7186 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
7187 #define EXTI_FTSR_TR1_Pos         (1U)
7188 #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
7189 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
7190 #define EXTI_FTSR_TR2_Pos         (2U)
7191 #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
7192 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
7193 #define EXTI_FTSR_TR3_Pos         (3U)
7194 #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
7195 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
7196 #define EXTI_FTSR_TR4_Pos         (4U)
7197 #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
7198 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
7199 #define EXTI_FTSR_TR5_Pos         (5U)
7200 #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
7201 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
7202 #define EXTI_FTSR_TR6_Pos         (6U)
7203 #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
7204 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
7205 #define EXTI_FTSR_TR7_Pos         (7U)
7206 #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
7207 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
7208 #define EXTI_FTSR_TR8_Pos         (8U)
7209 #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
7210 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
7211 #define EXTI_FTSR_TR9_Pos         (9U)
7212 #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
7213 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
7214 #define EXTI_FTSR_TR10_Pos        (10U)
7215 #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
7216 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
7217 #define EXTI_FTSR_TR11_Pos        (11U)
7218 #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
7219 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
7220 #define EXTI_FTSR_TR12_Pos        (12U)
7221 #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
7222 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
7223 #define EXTI_FTSR_TR13_Pos        (13U)
7224 #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
7225 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
7226 #define EXTI_FTSR_TR14_Pos        (14U)
7227 #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
7228 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
7229 #define EXTI_FTSR_TR15_Pos        (15U)
7230 #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
7231 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
7232 #define EXTI_FTSR_TR16_Pos        (16U)
7233 #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
7234 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
7235 #define EXTI_FTSR_TR17_Pos        (17U)
7236 #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
7237 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
7238 #define EXTI_FTSR_TR18_Pos        (18U)
7239 #define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
7240 #define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
7241 #define EXTI_FTSR_TR19_Pos        (19U)
7242 #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
7243 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
7244 #define EXTI_FTSR_TR20_Pos        (20U)
7245 #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
7246 #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
7247 #define EXTI_FTSR_TR21_Pos        (21U)
7248 #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
7249 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
7250 #define EXTI_FTSR_TR22_Pos        (22U)
7251 #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
7252 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
7253 #define EXTI_FTSR_TR23_Pos        (23U)
7254 #define EXTI_FTSR_TR23_Msk        (0x1UL << EXTI_FTSR_TR23_Pos)                 /*!< 0x00800000 */
7255 #define EXTI_FTSR_TR23            EXTI_FTSR_TR23_Msk                           /*!< Falling trigger event configuration bit of line 23 */
7256 
7257 /******************  Bit definition for EXTI_SWIER register  ******************/
7258 #define EXTI_SWIER_SWIER0_Pos     (0U)
7259 #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
7260 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
7261 #define EXTI_SWIER_SWIER1_Pos     (1U)
7262 #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
7263 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
7264 #define EXTI_SWIER_SWIER2_Pos     (2U)
7265 #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
7266 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
7267 #define EXTI_SWIER_SWIER3_Pos     (3U)
7268 #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
7269 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
7270 #define EXTI_SWIER_SWIER4_Pos     (4U)
7271 #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
7272 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
7273 #define EXTI_SWIER_SWIER5_Pos     (5U)
7274 #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
7275 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
7276 #define EXTI_SWIER_SWIER6_Pos     (6U)
7277 #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
7278 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
7279 #define EXTI_SWIER_SWIER7_Pos     (7U)
7280 #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
7281 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
7282 #define EXTI_SWIER_SWIER8_Pos     (8U)
7283 #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
7284 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
7285 #define EXTI_SWIER_SWIER9_Pos     (9U)
7286 #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
7287 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
7288 #define EXTI_SWIER_SWIER10_Pos    (10U)
7289 #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
7290 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
7291 #define EXTI_SWIER_SWIER11_Pos    (11U)
7292 #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
7293 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
7294 #define EXTI_SWIER_SWIER12_Pos    (12U)
7295 #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
7296 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
7297 #define EXTI_SWIER_SWIER13_Pos    (13U)
7298 #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
7299 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
7300 #define EXTI_SWIER_SWIER14_Pos    (14U)
7301 #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
7302 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
7303 #define EXTI_SWIER_SWIER15_Pos    (15U)
7304 #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
7305 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
7306 #define EXTI_SWIER_SWIER16_Pos    (16U)
7307 #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
7308 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
7309 #define EXTI_SWIER_SWIER17_Pos    (17U)
7310 #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
7311 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
7312 #define EXTI_SWIER_SWIER18_Pos    (18U)
7313 #define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
7314 #define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
7315 #define EXTI_SWIER_SWIER19_Pos    (19U)
7316 #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
7317 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
7318 #define EXTI_SWIER_SWIER20_Pos    (20U)
7319 #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
7320 #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
7321 #define EXTI_SWIER_SWIER21_Pos    (21U)
7322 #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
7323 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
7324 #define EXTI_SWIER_SWIER22_Pos    (22U)
7325 #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
7326 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
7327 #define EXTI_SWIER_SWIER23_Pos    (23U)
7328 #define EXTI_SWIER_SWIER23_Msk    (0x1UL << EXTI_SWIER_SWIER23_Pos)             /*!< 0x00800000 */
7329 #define EXTI_SWIER_SWIER23        EXTI_SWIER_SWIER23_Msk                       /*!< Software Interrupt on line 23 */
7330 
7331 /*******************  Bit definition for EXTI_PR register  ********************/
7332 #define EXTI_PR_PR0_Pos           (0U)
7333 #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
7334 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
7335 #define EXTI_PR_PR1_Pos           (1U)
7336 #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
7337 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
7338 #define EXTI_PR_PR2_Pos           (2U)
7339 #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
7340 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
7341 #define EXTI_PR_PR3_Pos           (3U)
7342 #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
7343 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
7344 #define EXTI_PR_PR4_Pos           (4U)
7345 #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
7346 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
7347 #define EXTI_PR_PR5_Pos           (5U)
7348 #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
7349 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
7350 #define EXTI_PR_PR6_Pos           (6U)
7351 #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
7352 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
7353 #define EXTI_PR_PR7_Pos           (7U)
7354 #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
7355 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
7356 #define EXTI_PR_PR8_Pos           (8U)
7357 #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
7358 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
7359 #define EXTI_PR_PR9_Pos           (9U)
7360 #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
7361 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
7362 #define EXTI_PR_PR10_Pos          (10U)
7363 #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
7364 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
7365 #define EXTI_PR_PR11_Pos          (11U)
7366 #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
7367 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
7368 #define EXTI_PR_PR12_Pos          (12U)
7369 #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
7370 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
7371 #define EXTI_PR_PR13_Pos          (13U)
7372 #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
7373 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
7374 #define EXTI_PR_PR14_Pos          (14U)
7375 #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
7376 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
7377 #define EXTI_PR_PR15_Pos          (15U)
7378 #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
7379 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
7380 #define EXTI_PR_PR16_Pos          (16U)
7381 #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
7382 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
7383 #define EXTI_PR_PR17_Pos          (17U)
7384 #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
7385 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
7386 #define EXTI_PR_PR18_Pos          (18U)
7387 #define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
7388 #define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
7389 #define EXTI_PR_PR19_Pos          (19U)
7390 #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
7391 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
7392 #define EXTI_PR_PR20_Pos          (20U)
7393 #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
7394 #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
7395 #define EXTI_PR_PR21_Pos          (21U)
7396 #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
7397 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
7398 #define EXTI_PR_PR22_Pos          (22U)
7399 #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
7400 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
7401 #define EXTI_PR_PR23_Pos          (23U)
7402 #define EXTI_PR_PR23_Msk          (0x1UL << EXTI_PR_PR23_Pos)                   /*!< 0x00800000 */
7403 #define EXTI_PR_PR23              EXTI_PR_PR23_Msk                             /*!< Pending bit for line 23 */
7404 
7405 /******************************************************************************/
7406 /*                                                                            */
7407 /*                                    FLASH                                   */
7408 /*                                                                            */
7409 /******************************************************************************/
7410 /*
7411 * @brief FLASH Total Sectors Number
7412 */
7413 #define FLASH_SECTOR_TOTAL  8
7414 
7415 /*******************  Bits definition for FLASH_ACR register  *****************/
7416 #define FLASH_ACR_LATENCY_Pos         (0U)
7417 #define FLASH_ACR_LATENCY_Msk         (0xFUL << FLASH_ACR_LATENCY_Pos)          /*!< 0x0000000F */
7418 #define FLASH_ACR_LATENCY             FLASH_ACR_LATENCY_Msk
7419 #define FLASH_ACR_LATENCY_0WS         0x00000000U
7420 #define FLASH_ACR_LATENCY_1WS         0x00000001U
7421 #define FLASH_ACR_LATENCY_2WS         0x00000002U
7422 #define FLASH_ACR_LATENCY_3WS         0x00000003U
7423 #define FLASH_ACR_LATENCY_4WS         0x00000004U
7424 #define FLASH_ACR_LATENCY_5WS         0x00000005U
7425 #define FLASH_ACR_LATENCY_6WS         0x00000006U
7426 #define FLASH_ACR_LATENCY_7WS         0x00000007U
7427 #define FLASH_ACR_LATENCY_8WS         0x00000008U
7428 #define FLASH_ACR_LATENCY_9WS         0x00000009U
7429 #define FLASH_ACR_LATENCY_10WS        0x0000000AU
7430 #define FLASH_ACR_LATENCY_11WS        0x0000000BU
7431 #define FLASH_ACR_LATENCY_12WS        0x0000000CU
7432 #define FLASH_ACR_LATENCY_13WS        0x0000000DU
7433 #define FLASH_ACR_LATENCY_14WS        0x0000000EU
7434 #define FLASH_ACR_LATENCY_15WS        0x0000000FU
7435 #define FLASH_ACR_PRFTEN_Pos          (8U)
7436 #define FLASH_ACR_PRFTEN_Msk          (0x1UL << FLASH_ACR_PRFTEN_Pos)           /*!< 0x00000100 */
7437 #define FLASH_ACR_PRFTEN              FLASH_ACR_PRFTEN_Msk
7438 #define FLASH_ACR_ARTEN_Pos           (9U)
7439 #define FLASH_ACR_ARTEN_Msk           (0x1UL << FLASH_ACR_ARTEN_Pos)            /*!< 0x00000200 */
7440 #define FLASH_ACR_ARTEN               FLASH_ACR_ARTEN_Msk
7441 #define FLASH_ACR_ARTRST_Pos          (11U)
7442 #define FLASH_ACR_ARTRST_Msk          (0x1UL << FLASH_ACR_ARTRST_Pos)           /*!< 0x00000800 */
7443 #define FLASH_ACR_ARTRST              FLASH_ACR_ARTRST_Msk
7444 
7445 /*******************  Bits definition for FLASH_SR register  ******************/
7446 #define FLASH_SR_EOP_Pos              (0U)
7447 #define FLASH_SR_EOP_Msk              (0x1UL << FLASH_SR_EOP_Pos)               /*!< 0x00000001 */
7448 #define FLASH_SR_EOP                  FLASH_SR_EOP_Msk
7449 #define FLASH_SR_OPERR_Pos            (1U)
7450 #define FLASH_SR_OPERR_Msk            (0x1UL << FLASH_SR_OPERR_Pos)             /*!< 0x00000002 */
7451 #define FLASH_SR_OPERR                FLASH_SR_OPERR_Msk
7452 #define FLASH_SR_WRPERR_Pos           (4U)
7453 #define FLASH_SR_WRPERR_Msk           (0x1UL << FLASH_SR_WRPERR_Pos)            /*!< 0x00000010 */
7454 #define FLASH_SR_WRPERR               FLASH_SR_WRPERR_Msk
7455 #define FLASH_SR_PGAERR_Pos           (5U)
7456 #define FLASH_SR_PGAERR_Msk           (0x1UL << FLASH_SR_PGAERR_Pos)            /*!< 0x00000020 */
7457 #define FLASH_SR_PGAERR               FLASH_SR_PGAERR_Msk
7458 #define FLASH_SR_PGPERR_Pos           (6U)
7459 #define FLASH_SR_PGPERR_Msk           (0x1UL << FLASH_SR_PGPERR_Pos)            /*!< 0x00000040 */
7460 #define FLASH_SR_PGPERR               FLASH_SR_PGPERR_Msk
7461 #define FLASH_SR_ERSERR_Pos           (7U)
7462 #define FLASH_SR_ERSERR_Msk           (0x1UL << FLASH_SR_ERSERR_Pos)            /*!< 0x00000080 */
7463 #define FLASH_SR_ERSERR               FLASH_SR_ERSERR_Msk
7464 #define FLASH_SR_BSY_Pos              (16U)
7465 #define FLASH_SR_BSY_Msk              (0x1UL << FLASH_SR_BSY_Pos)               /*!< 0x00010000 */
7466 #define FLASH_SR_BSY                  FLASH_SR_BSY_Msk
7467 
7468 /*******************  Bits definition for FLASH_CR register  ******************/
7469 #define FLASH_CR_PG_Pos               (0U)
7470 #define FLASH_CR_PG_Msk               (0x1UL << FLASH_CR_PG_Pos)                /*!< 0x00000001 */
7471 #define FLASH_CR_PG                   FLASH_CR_PG_Msk
7472 #define FLASH_CR_SER_Pos              (1U)
7473 #define FLASH_CR_SER_Msk              (0x1UL << FLASH_CR_SER_Pos)               /*!< 0x00000002 */
7474 #define FLASH_CR_SER                  FLASH_CR_SER_Msk
7475 #define FLASH_CR_MER_Pos              (2U)
7476 #define FLASH_CR_MER_Msk              (0x1UL << FLASH_CR_MER_Pos)               /*!< 0x00000004 */
7477 #define FLASH_CR_MER                  FLASH_CR_MER_Msk
7478 #define FLASH_CR_SNB_Pos              (3U)
7479 #define FLASH_CR_SNB_Msk              (0xFUL << FLASH_CR_SNB_Pos)               /*!< 0x00000078 */
7480 #define FLASH_CR_SNB                  FLASH_CR_SNB_Msk
7481 #define FLASH_CR_SNB_0                0x00000008U
7482 #define FLASH_CR_SNB_1                0x00000010U
7483 #define FLASH_CR_SNB_2                0x00000020U
7484 #define FLASH_CR_SNB_3                0x00000040U
7485 #define FLASH_CR_PSIZE_Pos            (8U)
7486 #define FLASH_CR_PSIZE_Msk            (0x3UL << FLASH_CR_PSIZE_Pos)             /*!< 0x00000300 */
7487 #define FLASH_CR_PSIZE                FLASH_CR_PSIZE_Msk
7488 #define FLASH_CR_PSIZE_0              (0x1UL << FLASH_CR_PSIZE_Pos)             /*!< 0x00000100 */
7489 #define FLASH_CR_PSIZE_1              (0x2UL << FLASH_CR_PSIZE_Pos)             /*!< 0x00000200 */
7490 #define FLASH_CR_STRT_Pos             (16U)
7491 #define FLASH_CR_STRT_Msk             (0x1UL << FLASH_CR_STRT_Pos)              /*!< 0x00010000 */
7492 #define FLASH_CR_STRT                 FLASH_CR_STRT_Msk
7493 #define FLASH_CR_EOPIE_Pos            (24U)
7494 #define FLASH_CR_EOPIE_Msk            (0x1UL << FLASH_CR_EOPIE_Pos)             /*!< 0x01000000 */
7495 #define FLASH_CR_EOPIE                FLASH_CR_EOPIE_Msk
7496 #define FLASH_CR_ERRIE_Pos            (25U)
7497 #define FLASH_CR_ERRIE_Msk            (0x1UL << FLASH_CR_ERRIE_Pos)             /*!< 0x02000000 */
7498 #define FLASH_CR_ERRIE                FLASH_CR_ERRIE_Msk
7499 #define FLASH_CR_LOCK_Pos             (31U)
7500 #define FLASH_CR_LOCK_Msk             (0x1UL << FLASH_CR_LOCK_Pos)              /*!< 0x80000000 */
7501 #define FLASH_CR_LOCK                 FLASH_CR_LOCK_Msk
7502 
7503 /*******************  Bits definition for FLASH_OPTCR register  ***************/
7504 #define FLASH_OPTCR_OPTLOCK_Pos       (0U)
7505 #define FLASH_OPTCR_OPTLOCK_Msk       (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)        /*!< 0x00000001 */
7506 #define FLASH_OPTCR_OPTLOCK           FLASH_OPTCR_OPTLOCK_Msk
7507 #define FLASH_OPTCR_OPTSTRT_Pos       (1U)
7508 #define FLASH_OPTCR_OPTSTRT_Msk       (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)        /*!< 0x00000002 */
7509 #define FLASH_OPTCR_OPTSTRT           FLASH_OPTCR_OPTSTRT_Msk
7510 #define FLASH_OPTCR_BOR_LEV_Pos       (2U)
7511 #define FLASH_OPTCR_BOR_LEV_Msk       (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)        /*!< 0x0000000C */
7512 #define FLASH_OPTCR_BOR_LEV           FLASH_OPTCR_BOR_LEV_Msk
7513 #define FLASH_OPTCR_BOR_LEV_0         (0x1UL << FLASH_OPTCR_BOR_LEV_Pos)        /*!< 0x00000004 */
7514 #define FLASH_OPTCR_BOR_LEV_1         (0x2UL << FLASH_OPTCR_BOR_LEV_Pos)        /*!< 0x00000008 */
7515 #define FLASH_OPTCR_WWDG_SW_Pos       (4U)
7516 #define FLASH_OPTCR_WWDG_SW_Msk       (0x1UL << FLASH_OPTCR_WWDG_SW_Pos)        /*!< 0x00000010 */
7517 #define FLASH_OPTCR_WWDG_SW           FLASH_OPTCR_WWDG_SW_Msk
7518 #define FLASH_OPTCR_IWDG_SW_Pos       (5U)
7519 #define FLASH_OPTCR_IWDG_SW_Msk       (0x1UL << FLASH_OPTCR_IWDG_SW_Pos)        /*!< 0x00000020 */
7520 #define FLASH_OPTCR_IWDG_SW           FLASH_OPTCR_IWDG_SW_Msk
7521 #define FLASH_OPTCR_nRST_STOP_Pos     (6U)
7522 #define FLASH_OPTCR_nRST_STOP_Msk     (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)      /*!< 0x00000040 */
7523 #define FLASH_OPTCR_nRST_STOP         FLASH_OPTCR_nRST_STOP_Msk
7524 #define FLASH_OPTCR_nRST_STDBY_Pos    (7U)
7525 #define FLASH_OPTCR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)     /*!< 0x00000080 */
7526 #define FLASH_OPTCR_nRST_STDBY        FLASH_OPTCR_nRST_STDBY_Msk
7527 #define FLASH_OPTCR_RDP_Pos           (8U)
7528 #define FLASH_OPTCR_RDP_Msk           (0xFFUL << FLASH_OPTCR_RDP_Pos)           /*!< 0x0000FF00 */
7529 #define FLASH_OPTCR_RDP               FLASH_OPTCR_RDP_Msk
7530 #define FLASH_OPTCR_RDP_0             (0x01UL << FLASH_OPTCR_RDP_Pos)           /*!< 0x00000100 */
7531 #define FLASH_OPTCR_RDP_1             (0x02UL << FLASH_OPTCR_RDP_Pos)           /*!< 0x00000200 */
7532 #define FLASH_OPTCR_RDP_2             (0x04UL << FLASH_OPTCR_RDP_Pos)           /*!< 0x00000400 */
7533 #define FLASH_OPTCR_RDP_3             (0x08UL << FLASH_OPTCR_RDP_Pos)           /*!< 0x00000800 */
7534 #define FLASH_OPTCR_RDP_4             (0x10UL << FLASH_OPTCR_RDP_Pos)           /*!< 0x00001000 */
7535 #define FLASH_OPTCR_RDP_5             (0x20UL << FLASH_OPTCR_RDP_Pos)           /*!< 0x00002000 */
7536 #define FLASH_OPTCR_RDP_6             (0x40UL << FLASH_OPTCR_RDP_Pos)           /*!< 0x00004000 */
7537 #define FLASH_OPTCR_RDP_7             (0x80UL << FLASH_OPTCR_RDP_Pos)           /*!< 0x00008000 */
7538 #define FLASH_OPTCR_nWRP_Pos          (16U)
7539 #define FLASH_OPTCR_nWRP_Msk          (0xFFUL << FLASH_OPTCR_nWRP_Pos)          /*!< 0x00FF0000 */
7540 #define FLASH_OPTCR_nWRP              FLASH_OPTCR_nWRP_Msk
7541 #define FLASH_OPTCR_nWRP_0            0x00010000U
7542 #define FLASH_OPTCR_nWRP_1            0x00020000U
7543 #define FLASH_OPTCR_nWRP_2            0x00040000U
7544 #define FLASH_OPTCR_nWRP_3            0x00080000U
7545 #define FLASH_OPTCR_nWRP_4            0x00100000U
7546 #define FLASH_OPTCR_nWRP_5            0x00200000U
7547 #define FLASH_OPTCR_nWRP_6            0x00400000U
7548 #define FLASH_OPTCR_nWRP_7            0x00800000U
7549 #define FLASH_OPTCR_IWDG_STDBY_Pos    (30U)
7550 #define FLASH_OPTCR_IWDG_STDBY_Msk    (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos)     /*!< 0x40000000 */
7551 #define FLASH_OPTCR_IWDG_STDBY        FLASH_OPTCR_IWDG_STDBY_Msk
7552 #define FLASH_OPTCR_IWDG_STOP_Pos     (31U)
7553 #define FLASH_OPTCR_IWDG_STOP_Msk     (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos)      /*!< 0x80000000 */
7554 #define FLASH_OPTCR_IWDG_STOP         FLASH_OPTCR_IWDG_STOP_Msk
7555 
7556 /*******************  Bits definition for FLASH_OPTCR1 register  ***************/
7557 #define FLASH_OPTCR1_BOOT_ADD0_Pos    (0U)
7558 #define FLASH_OPTCR1_BOOT_ADD0_Msk    (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos)  /*!< 0x0000FFFF */
7559 #define FLASH_OPTCR1_BOOT_ADD0        FLASH_OPTCR1_BOOT_ADD0_Msk
7560 #define FLASH_OPTCR1_BOOT_ADD1_Pos    (16U)
7561 #define FLASH_OPTCR1_BOOT_ADD1_Msk    (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos)  /*!< 0xFFFF0000 */
7562 #define FLASH_OPTCR1_BOOT_ADD1        FLASH_OPTCR1_BOOT_ADD1_Msk
7563 
7564 
7565 /******************************************************************************/
7566 /*                                                                            */
7567 /*                          Flexible Memory Controller                        */
7568 /*                                                                            */
7569 /******************************************************************************/
7570 /******************  Bit definition for FMC_BCR1 register  *******************/
7571 #define FMC_BCR1_MBKEN_Pos         (0U)
7572 #define FMC_BCR1_MBKEN_Msk         (0x1UL << FMC_BCR1_MBKEN_Pos)                /*!< 0x00000001 */
7573 #define FMC_BCR1_MBKEN             FMC_BCR1_MBKEN_Msk                          /*!<Memory bank enable bit                 */
7574 #define FMC_BCR1_MUXEN_Pos         (1U)
7575 #define FMC_BCR1_MUXEN_Msk         (0x1UL << FMC_BCR1_MUXEN_Pos)                /*!< 0x00000002 */
7576 #define FMC_BCR1_MUXEN             FMC_BCR1_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
7577 #define FMC_BCR1_MTYP_Pos          (2U)
7578 #define FMC_BCR1_MTYP_Msk          (0x3UL << FMC_BCR1_MTYP_Pos)                 /*!< 0x0000000C */
7579 #define FMC_BCR1_MTYP              FMC_BCR1_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
7580 #define FMC_BCR1_MTYP_0            (0x1UL << FMC_BCR1_MTYP_Pos)                 /*!< 0x00000004 */
7581 #define FMC_BCR1_MTYP_1            (0x2UL << FMC_BCR1_MTYP_Pos)                 /*!< 0x00000008 */
7582 #define FMC_BCR1_MWID_Pos          (4U)
7583 #define FMC_BCR1_MWID_Msk          (0x3UL << FMC_BCR1_MWID_Pos)                 /*!< 0x00000030 */
7584 #define FMC_BCR1_MWID              FMC_BCR1_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
7585 #define FMC_BCR1_MWID_0            (0x1UL << FMC_BCR1_MWID_Pos)                 /*!< 0x00000010 */
7586 #define FMC_BCR1_MWID_1            (0x2UL << FMC_BCR1_MWID_Pos)                 /*!< 0x00000020 */
7587 #define FMC_BCR1_FACCEN_Pos        (6U)
7588 #define FMC_BCR1_FACCEN_Msk        (0x1UL << FMC_BCR1_FACCEN_Pos)               /*!< 0x00000040 */
7589 #define FMC_BCR1_FACCEN            FMC_BCR1_FACCEN_Msk                         /*!<Flash access enable        */
7590 #define FMC_BCR1_BURSTEN_Pos       (8U)
7591 #define FMC_BCR1_BURSTEN_Msk       (0x1UL << FMC_BCR1_BURSTEN_Pos)              /*!< 0x00000100 */
7592 #define FMC_BCR1_BURSTEN           FMC_BCR1_BURSTEN_Msk                        /*!<Burst enable bit           */
7593 #define FMC_BCR1_WAITPOL_Pos       (9U)
7594 #define FMC_BCR1_WAITPOL_Msk       (0x1UL << FMC_BCR1_WAITPOL_Pos)              /*!< 0x00000200 */
7595 #define FMC_BCR1_WAITPOL           FMC_BCR1_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
7596 #define FMC_BCR1_WRAPMOD_Pos       (10U)
7597 #define FMC_BCR1_WRAPMOD_Msk       (0x1UL << FMC_BCR1_WRAPMOD_Pos)              /*!< 0x00000400 */
7598 #define FMC_BCR1_WRAPMOD           FMC_BCR1_WRAPMOD_Msk                        /*!<Wrapped burst mode support */
7599 #define FMC_BCR1_WAITCFG_Pos       (11U)
7600 #define FMC_BCR1_WAITCFG_Msk       (0x1UL << FMC_BCR1_WAITCFG_Pos)              /*!< 0x00000800 */
7601 #define FMC_BCR1_WAITCFG           FMC_BCR1_WAITCFG_Msk                        /*!<Wait timing configuration  */
7602 #define FMC_BCR1_WREN_Pos          (12U)
7603 #define FMC_BCR1_WREN_Msk          (0x1UL << FMC_BCR1_WREN_Pos)                 /*!< 0x00001000 */
7604 #define FMC_BCR1_WREN              FMC_BCR1_WREN_Msk                           /*!<Write enable bit           */
7605 #define FMC_BCR1_WAITEN_Pos        (13U)
7606 #define FMC_BCR1_WAITEN_Msk        (0x1UL << FMC_BCR1_WAITEN_Pos)               /*!< 0x00002000 */
7607 #define FMC_BCR1_WAITEN            FMC_BCR1_WAITEN_Msk                         /*!<Wait enable bit            */
7608 #define FMC_BCR1_EXTMOD_Pos        (14U)
7609 #define FMC_BCR1_EXTMOD_Msk        (0x1UL << FMC_BCR1_EXTMOD_Pos)               /*!< 0x00004000 */
7610 #define FMC_BCR1_EXTMOD            FMC_BCR1_EXTMOD_Msk                         /*!<Extended mode enable       */
7611 #define FMC_BCR1_ASYNCWAIT_Pos     (15U)
7612 #define FMC_BCR1_ASYNCWAIT_Msk     (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)            /*!< 0x00008000 */
7613 #define FMC_BCR1_ASYNCWAIT         FMC_BCR1_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
7614 #define FMC_BCR1_CPSIZE_Pos        (16U)
7615 #define FMC_BCR1_CPSIZE_Msk        (0x7UL << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00070000 */
7616 #define FMC_BCR1_CPSIZE            FMC_BCR1_CPSIZE_Msk                         /*!<CRAM page size             */
7617 #define FMC_BCR1_CPSIZE_0          (0x1UL << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00010000 */
7618 #define FMC_BCR1_CPSIZE_1          (0x2UL << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00020000 */
7619 #define FMC_BCR1_CPSIZE_2          (0x4UL << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00040000 */
7620 #define FMC_BCR1_CBURSTRW_Pos      (19U)
7621 #define FMC_BCR1_CBURSTRW_Msk      (0x1UL << FMC_BCR1_CBURSTRW_Pos)             /*!< 0x00080000 */
7622 #define FMC_BCR1_CBURSTRW          FMC_BCR1_CBURSTRW_Msk                       /*!<Write burst enable         */
7623 #define FMC_BCR1_CCLKEN_Pos        (20U)
7624 #define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */
7625 #define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable     */
7626 #define FMC_BCR1_WFDIS_Pos         (21U)
7627 #define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)                /*!< 0x00200000 */
7628 #define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
7629 
7630 /******************  Bit definition for FMC_BCR2 register  *******************/
7631 #define FMC_BCR2_MBKEN_Pos         (0U)
7632 #define FMC_BCR2_MBKEN_Msk         (0x1UL << FMC_BCR2_MBKEN_Pos)                /*!< 0x00000001 */
7633 #define FMC_BCR2_MBKEN             FMC_BCR2_MBKEN_Msk                          /*!<Memory bank enable bit                 */
7634 #define FMC_BCR2_MUXEN_Pos         (1U)
7635 #define FMC_BCR2_MUXEN_Msk         (0x1UL << FMC_BCR2_MUXEN_Pos)                /*!< 0x00000002 */
7636 #define FMC_BCR2_MUXEN             FMC_BCR2_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
7637 #define FMC_BCR2_MTYP_Pos          (2U)
7638 #define FMC_BCR2_MTYP_Msk          (0x3UL << FMC_BCR2_MTYP_Pos)                 /*!< 0x0000000C */
7639 #define FMC_BCR2_MTYP              FMC_BCR2_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
7640 #define FMC_BCR2_MTYP_0            (0x1UL << FMC_BCR2_MTYP_Pos)                 /*!< 0x00000004 */
7641 #define FMC_BCR2_MTYP_1            (0x2UL << FMC_BCR2_MTYP_Pos)                 /*!< 0x00000008 */
7642 #define FMC_BCR2_MWID_Pos          (4U)
7643 #define FMC_BCR2_MWID_Msk          (0x3UL << FMC_BCR2_MWID_Pos)                 /*!< 0x00000030 */
7644 #define FMC_BCR2_MWID              FMC_BCR2_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
7645 #define FMC_BCR2_MWID_0            (0x1UL << FMC_BCR2_MWID_Pos)                 /*!< 0x00000010 */
7646 #define FMC_BCR2_MWID_1            (0x2UL << FMC_BCR2_MWID_Pos)                 /*!< 0x00000020 */
7647 #define FMC_BCR2_FACCEN_Pos        (6U)
7648 #define FMC_BCR2_FACCEN_Msk        (0x1UL << FMC_BCR2_FACCEN_Pos)               /*!< 0x00000040 */
7649 #define FMC_BCR2_FACCEN            FMC_BCR2_FACCEN_Msk                         /*!<Flash access enable        */
7650 #define FMC_BCR2_BURSTEN_Pos       (8U)
7651 #define FMC_BCR2_BURSTEN_Msk       (0x1UL << FMC_BCR2_BURSTEN_Pos)              /*!< 0x00000100 */
7652 #define FMC_BCR2_BURSTEN           FMC_BCR2_BURSTEN_Msk                        /*!<Burst enable bit           */
7653 #define FMC_BCR2_WAITPOL_Pos       (9U)
7654 #define FMC_BCR2_WAITPOL_Msk       (0x1UL << FMC_BCR2_WAITPOL_Pos)              /*!< 0x00000200 */
7655 #define FMC_BCR2_WAITPOL           FMC_BCR2_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
7656 #define FMC_BCR2_WRAPMOD_Pos       (10U)
7657 #define FMC_BCR2_WRAPMOD_Msk       (0x1UL << FMC_BCR2_WRAPMOD_Pos)              /*!< 0x00000400 */
7658 #define FMC_BCR2_WRAPMOD           FMC_BCR2_WRAPMOD_Msk                        /*!<Wrapped burst mode support */
7659 #define FMC_BCR2_WAITCFG_Pos       (11U)
7660 #define FMC_BCR2_WAITCFG_Msk       (0x1UL << FMC_BCR2_WAITCFG_Pos)              /*!< 0x00000800 */
7661 #define FMC_BCR2_WAITCFG           FMC_BCR2_WAITCFG_Msk                        /*!<Wait timing configuration  */
7662 #define FMC_BCR2_WREN_Pos          (12U)
7663 #define FMC_BCR2_WREN_Msk          (0x1UL << FMC_BCR2_WREN_Pos)                 /*!< 0x00001000 */
7664 #define FMC_BCR2_WREN              FMC_BCR2_WREN_Msk                           /*!<Write enable bit           */
7665 #define FMC_BCR2_WAITEN_Pos        (13U)
7666 #define FMC_BCR2_WAITEN_Msk        (0x1UL << FMC_BCR2_WAITEN_Pos)               /*!< 0x00002000 */
7667 #define FMC_BCR2_WAITEN            FMC_BCR2_WAITEN_Msk                         /*!<Wait enable bit            */
7668 #define FMC_BCR2_EXTMOD_Pos        (14U)
7669 #define FMC_BCR2_EXTMOD_Msk        (0x1UL << FMC_BCR2_EXTMOD_Pos)               /*!< 0x00004000 */
7670 #define FMC_BCR2_EXTMOD            FMC_BCR2_EXTMOD_Msk                         /*!<Extended mode enable       */
7671 #define FMC_BCR2_ASYNCWAIT_Pos     (15U)
7672 #define FMC_BCR2_ASYNCWAIT_Msk     (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)            /*!< 0x00008000 */
7673 #define FMC_BCR2_ASYNCWAIT         FMC_BCR2_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
7674 #define FMC_BCR2_CPSIZE_Pos        (16U)
7675 #define FMC_BCR2_CPSIZE_Msk        (0x7UL << FMC_BCR2_CPSIZE_Pos)               /*!< 0x00070000 */
7676 #define FMC_BCR2_CPSIZE            FMC_BCR2_CPSIZE_Msk                         /*!<CRAM page size             */
7677 #define FMC_BCR2_CPSIZE_0          (0x1UL << FMC_BCR2_CPSIZE_Pos)               /*!< 0x00010000 */
7678 #define FMC_BCR2_CPSIZE_1          (0x2UL << FMC_BCR2_CPSIZE_Pos)               /*!< 0x00020000 */
7679 #define FMC_BCR2_CPSIZE_2          (0x4UL << FMC_BCR2_CPSIZE_Pos)               /*!< 0x00040000 */
7680 #define FMC_BCR2_CBURSTRW_Pos      (19U)
7681 #define FMC_BCR2_CBURSTRW_Msk      (0x1UL << FMC_BCR2_CBURSTRW_Pos)             /*!< 0x00080000 */
7682 #define FMC_BCR2_CBURSTRW          FMC_BCR2_CBURSTRW_Msk                       /*!<Write burst enable         */
7683 
7684 /******************  Bit definition for FMC_BCR3 register  *******************/
7685 #define FMC_BCR3_MBKEN_Pos         (0U)
7686 #define FMC_BCR3_MBKEN_Msk         (0x1UL << FMC_BCR3_MBKEN_Pos)                /*!< 0x00000001 */
7687 #define FMC_BCR3_MBKEN             FMC_BCR3_MBKEN_Msk                          /*!<Memory bank enable bit                 */
7688 #define FMC_BCR3_MUXEN_Pos         (1U)
7689 #define FMC_BCR3_MUXEN_Msk         (0x1UL << FMC_BCR3_MUXEN_Pos)                /*!< 0x00000002 */
7690 #define FMC_BCR3_MUXEN             FMC_BCR3_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
7691 #define FMC_BCR3_MTYP_Pos          (2U)
7692 #define FMC_BCR3_MTYP_Msk          (0x3UL << FMC_BCR3_MTYP_Pos)                 /*!< 0x0000000C */
7693 #define FMC_BCR3_MTYP              FMC_BCR3_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
7694 #define FMC_BCR3_MTYP_0            (0x1UL << FMC_BCR3_MTYP_Pos)                 /*!< 0x00000004 */
7695 #define FMC_BCR3_MTYP_1            (0x2UL << FMC_BCR3_MTYP_Pos)                 /*!< 0x00000008 */
7696 #define FMC_BCR3_MWID_Pos          (4U)
7697 #define FMC_BCR3_MWID_Msk          (0x3UL << FMC_BCR3_MWID_Pos)                 /*!< 0x00000030 */
7698 #define FMC_BCR3_MWID              FMC_BCR3_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
7699 #define FMC_BCR3_MWID_0            (0x1UL << FMC_BCR3_MWID_Pos)                 /*!< 0x00000010 */
7700 #define FMC_BCR3_MWID_1            (0x2UL << FMC_BCR3_MWID_Pos)                 /*!< 0x00000020 */
7701 #define FMC_BCR3_FACCEN_Pos        (6U)
7702 #define FMC_BCR3_FACCEN_Msk        (0x1UL << FMC_BCR3_FACCEN_Pos)               /*!< 0x00000040 */
7703 #define FMC_BCR3_FACCEN            FMC_BCR3_FACCEN_Msk                         /*!<Flash access enable        */
7704 #define FMC_BCR3_BURSTEN_Pos       (8U)
7705 #define FMC_BCR3_BURSTEN_Msk       (0x1UL << FMC_BCR3_BURSTEN_Pos)              /*!< 0x00000100 */
7706 #define FMC_BCR3_BURSTEN           FMC_BCR3_BURSTEN_Msk                        /*!<Burst enable bit           */
7707 #define FMC_BCR3_WAITPOL_Pos       (9U)
7708 #define FMC_BCR3_WAITPOL_Msk       (0x1UL << FMC_BCR3_WAITPOL_Pos)              /*!< 0x00000200 */
7709 #define FMC_BCR3_WAITPOL           FMC_BCR3_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
7710 #define FMC_BCR3_WRAPMOD_Pos       (10U)
7711 #define FMC_BCR3_WRAPMOD_Msk       (0x1UL << FMC_BCR3_WRAPMOD_Pos)              /*!< 0x00000400 */
7712 #define FMC_BCR3_WRAPMOD           FMC_BCR3_WRAPMOD_Msk                        /*!<Wrapped burst mode support */
7713 #define FMC_BCR3_WAITCFG_Pos       (11U)
7714 #define FMC_BCR3_WAITCFG_Msk       (0x1UL << FMC_BCR3_WAITCFG_Pos)              /*!< 0x00000800 */
7715 #define FMC_BCR3_WAITCFG           FMC_BCR3_WAITCFG_Msk                        /*!<Wait timing configuration  */
7716 #define FMC_BCR3_WREN_Pos          (12U)
7717 #define FMC_BCR3_WREN_Msk          (0x1UL << FMC_BCR3_WREN_Pos)                 /*!< 0x00001000 */
7718 #define FMC_BCR3_WREN              FMC_BCR3_WREN_Msk                           /*!<Write enable bit           */
7719 #define FMC_BCR3_WAITEN_Pos        (13U)
7720 #define FMC_BCR3_WAITEN_Msk        (0x1UL << FMC_BCR3_WAITEN_Pos)               /*!< 0x00002000 */
7721 #define FMC_BCR3_WAITEN            FMC_BCR3_WAITEN_Msk                         /*!<Wait enable bit            */
7722 #define FMC_BCR3_EXTMOD_Pos        (14U)
7723 #define FMC_BCR3_EXTMOD_Msk        (0x1UL << FMC_BCR3_EXTMOD_Pos)               /*!< 0x00004000 */
7724 #define FMC_BCR3_EXTMOD            FMC_BCR3_EXTMOD_Msk                         /*!<Extended mode enable       */
7725 #define FMC_BCR3_ASYNCWAIT_Pos     (15U)
7726 #define FMC_BCR3_ASYNCWAIT_Msk     (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)            /*!< 0x00008000 */
7727 #define FMC_BCR3_ASYNCWAIT         FMC_BCR3_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
7728 #define FMC_BCR3_CPSIZE_Pos        (16U)
7729 #define FMC_BCR3_CPSIZE_Msk        (0x7UL << FMC_BCR3_CPSIZE_Pos)               /*!< 0x00070000 */
7730 #define FMC_BCR3_CPSIZE            FMC_BCR3_CPSIZE_Msk                         /*!<CRAM page size             */
7731 #define FMC_BCR3_CPSIZE_0          (0x1UL << FMC_BCR3_CPSIZE_Pos)               /*!< 0x00010000 */
7732 #define FMC_BCR3_CPSIZE_1          (0x2UL << FMC_BCR3_CPSIZE_Pos)               /*!< 0x00020000 */
7733 #define FMC_BCR3_CPSIZE_2          (0x4UL << FMC_BCR3_CPSIZE_Pos)               /*!< 0x00040000 */
7734 #define FMC_BCR3_CBURSTRW_Pos      (19U)
7735 #define FMC_BCR3_CBURSTRW_Msk      (0x1UL << FMC_BCR3_CBURSTRW_Pos)             /*!< 0x00080000 */
7736 #define FMC_BCR3_CBURSTRW          FMC_BCR3_CBURSTRW_Msk                       /*!<Write burst enable         */
7737 
7738 /******************  Bit definition for FMC_BCR4 register  *******************/
7739 #define FMC_BCR4_MBKEN_Pos         (0U)
7740 #define FMC_BCR4_MBKEN_Msk         (0x1UL << FMC_BCR4_MBKEN_Pos)                /*!< 0x00000001 */
7741 #define FMC_BCR4_MBKEN             FMC_BCR4_MBKEN_Msk                          /*!<Memory bank enable bit                 */
7742 #define FMC_BCR4_MUXEN_Pos         (1U)
7743 #define FMC_BCR4_MUXEN_Msk         (0x1UL << FMC_BCR4_MUXEN_Pos)                /*!< 0x00000002 */
7744 #define FMC_BCR4_MUXEN             FMC_BCR4_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
7745 #define FMC_BCR4_MTYP_Pos          (2U)
7746 #define FMC_BCR4_MTYP_Msk          (0x3UL << FMC_BCR4_MTYP_Pos)                 /*!< 0x0000000C */
7747 #define FMC_BCR4_MTYP              FMC_BCR4_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
7748 #define FMC_BCR4_MTYP_0            (0x1UL << FMC_BCR4_MTYP_Pos)                 /*!< 0x00000004 */
7749 #define FMC_BCR4_MTYP_1            (0x2UL << FMC_BCR4_MTYP_Pos)                 /*!< 0x00000008 */
7750 #define FMC_BCR4_MWID_Pos          (4U)
7751 #define FMC_BCR4_MWID_Msk          (0x3UL << FMC_BCR4_MWID_Pos)                 /*!< 0x00000030 */
7752 #define FMC_BCR4_MWID              FMC_BCR4_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
7753 #define FMC_BCR4_MWID_0            (0x1UL << FMC_BCR4_MWID_Pos)                 /*!< 0x00000010 */
7754 #define FMC_BCR4_MWID_1            (0x2UL << FMC_BCR4_MWID_Pos)                 /*!< 0x00000020 */
7755 #define FMC_BCR4_FACCEN_Pos        (6U)
7756 #define FMC_BCR4_FACCEN_Msk        (0x1UL << FMC_BCR4_FACCEN_Pos)               /*!< 0x00000040 */
7757 #define FMC_BCR4_FACCEN            FMC_BCR4_FACCEN_Msk                         /*!<Flash access enable        */
7758 #define FMC_BCR4_BURSTEN_Pos       (8U)
7759 #define FMC_BCR4_BURSTEN_Msk       (0x1UL << FMC_BCR4_BURSTEN_Pos)              /*!< 0x00000100 */
7760 #define FMC_BCR4_BURSTEN           FMC_BCR4_BURSTEN_Msk                        /*!<Burst enable bit           */
7761 #define FMC_BCR4_WAITPOL_Pos       (9U)
7762 #define FMC_BCR4_WAITPOL_Msk       (0x1UL << FMC_BCR4_WAITPOL_Pos)              /*!< 0x00000200 */
7763 #define FMC_BCR4_WAITPOL           FMC_BCR4_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
7764 #define FMC_BCR4_WRAPMOD_Pos       (10U)
7765 #define FMC_BCR4_WRAPMOD_Msk       (0x1UL << FMC_BCR4_WRAPMOD_Pos)              /*!< 0x00000400 */
7766 #define FMC_BCR4_WRAPMOD           FMC_BCR4_WRAPMOD_Msk                        /*!<Wrapped burst mode support */
7767 #define FMC_BCR4_WAITCFG_Pos       (11U)
7768 #define FMC_BCR4_WAITCFG_Msk       (0x1UL << FMC_BCR4_WAITCFG_Pos)              /*!< 0x00000800 */
7769 #define FMC_BCR4_WAITCFG           FMC_BCR4_WAITCFG_Msk                        /*!<Wait timing configuration  */
7770 #define FMC_BCR4_WREN_Pos          (12U)
7771 #define FMC_BCR4_WREN_Msk          (0x1UL << FMC_BCR4_WREN_Pos)                 /*!< 0x00001000 */
7772 #define FMC_BCR4_WREN              FMC_BCR4_WREN_Msk                           /*!<Write enable bit           */
7773 #define FMC_BCR4_WAITEN_Pos        (13U)
7774 #define FMC_BCR4_WAITEN_Msk        (0x1UL << FMC_BCR4_WAITEN_Pos)               /*!< 0x00002000 */
7775 #define FMC_BCR4_WAITEN            FMC_BCR4_WAITEN_Msk                         /*!<Wait enable bit            */
7776 #define FMC_BCR4_EXTMOD_Pos        (14U)
7777 #define FMC_BCR4_EXTMOD_Msk        (0x1UL << FMC_BCR4_EXTMOD_Pos)               /*!< 0x00004000 */
7778 #define FMC_BCR4_EXTMOD            FMC_BCR4_EXTMOD_Msk                         /*!<Extended mode enable       */
7779 #define FMC_BCR4_ASYNCWAIT_Pos     (15U)
7780 #define FMC_BCR4_ASYNCWAIT_Msk     (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)            /*!< 0x00008000 */
7781 #define FMC_BCR4_ASYNCWAIT         FMC_BCR4_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
7782 #define FMC_BCR4_CPSIZE_Pos        (16U)
7783 #define FMC_BCR4_CPSIZE_Msk        (0x7UL << FMC_BCR4_CPSIZE_Pos)               /*!< 0x00070000 */
7784 #define FMC_BCR4_CPSIZE            FMC_BCR4_CPSIZE_Msk                         /*!<CRAM page size             */
7785 #define FMC_BCR4_CPSIZE_0          (0x1UL << FMC_BCR4_CPSIZE_Pos)               /*!< 0x00010000 */
7786 #define FMC_BCR4_CPSIZE_1          (0x2UL << FMC_BCR4_CPSIZE_Pos)               /*!< 0x00020000 */
7787 #define FMC_BCR4_CPSIZE_2          (0x4UL << FMC_BCR4_CPSIZE_Pos)               /*!< 0x00040000 */
7788 #define FMC_BCR4_CBURSTRW_Pos      (19U)
7789 #define FMC_BCR4_CBURSTRW_Msk      (0x1UL << FMC_BCR4_CBURSTRW_Pos)             /*!< 0x00080000 */
7790 #define FMC_BCR4_CBURSTRW          FMC_BCR4_CBURSTRW_Msk                       /*!<Write burst enable         */
7791 
7792 /******************  Bit definition for FMC_BTR1 register  ******************/
7793 #define FMC_BTR1_ADDSET_Pos        (0U)
7794 #define FMC_BTR1_ADDSET_Msk        (0xFUL << FMC_BTR1_ADDSET_Pos)               /*!< 0x0000000F */
7795 #define FMC_BTR1_ADDSET            FMC_BTR1_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
7796 #define FMC_BTR1_ADDSET_0          (0x1UL << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000001 */
7797 #define FMC_BTR1_ADDSET_1          (0x2UL << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000002 */
7798 #define FMC_BTR1_ADDSET_2          (0x4UL << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000004 */
7799 #define FMC_BTR1_ADDSET_3          (0x8UL << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000008 */
7800 #define FMC_BTR1_ADDHLD_Pos        (4U)
7801 #define FMC_BTR1_ADDHLD_Msk        (0xFUL << FMC_BTR1_ADDHLD_Pos)               /*!< 0x000000F0 */
7802 #define FMC_BTR1_ADDHLD            FMC_BTR1_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
7803 #define FMC_BTR1_ADDHLD_0          (0x1UL << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000010 */
7804 #define FMC_BTR1_ADDHLD_1          (0x2UL << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000020 */
7805 #define FMC_BTR1_ADDHLD_2          (0x4UL << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000040 */
7806 #define FMC_BTR1_ADDHLD_3          (0x8UL << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000080 */
7807 #define FMC_BTR1_DATAST_Pos        (8U)
7808 #define FMC_BTR1_DATAST_Msk        (0xFFUL << FMC_BTR1_DATAST_Pos)              /*!< 0x0000FF00 */
7809 #define FMC_BTR1_DATAST            FMC_BTR1_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
7810 #define FMC_BTR1_DATAST_0          (0x01UL << FMC_BTR1_DATAST_Pos)              /*!< 0x00000100 */
7811 #define FMC_BTR1_DATAST_1          (0x02UL << FMC_BTR1_DATAST_Pos)              /*!< 0x00000200 */
7812 #define FMC_BTR1_DATAST_2          (0x04UL << FMC_BTR1_DATAST_Pos)              /*!< 0x00000400 */
7813 #define FMC_BTR1_DATAST_3          (0x08UL << FMC_BTR1_DATAST_Pos)              /*!< 0x00000800 */
7814 #define FMC_BTR1_DATAST_4          (0x10UL << FMC_BTR1_DATAST_Pos)              /*!< 0x00001000 */
7815 #define FMC_BTR1_DATAST_5          (0x20UL << FMC_BTR1_DATAST_Pos)              /*!< 0x00002000 */
7816 #define FMC_BTR1_DATAST_6          (0x40UL << FMC_BTR1_DATAST_Pos)              /*!< 0x00004000 */
7817 #define FMC_BTR1_DATAST_7          (0x80UL << FMC_BTR1_DATAST_Pos)              /*!< 0x00008000 */
7818 #define FMC_BTR1_BUSTURN_Pos       (16U)
7819 #define FMC_BTR1_BUSTURN_Msk       (0xFUL << FMC_BTR1_BUSTURN_Pos)              /*!< 0x000F0000 */
7820 #define FMC_BTR1_BUSTURN           FMC_BTR1_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7821 #define FMC_BTR1_BUSTURN_0         (0x1UL << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00010000 */
7822 #define FMC_BTR1_BUSTURN_1         (0x2UL << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00020000 */
7823 #define FMC_BTR1_BUSTURN_2         (0x4UL << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00040000 */
7824 #define FMC_BTR1_BUSTURN_3         (0x8UL << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00080000 */
7825 #define FMC_BTR1_CLKDIV_Pos        (20U)
7826 #define FMC_BTR1_CLKDIV_Msk        (0xFUL << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00F00000 */
7827 #define FMC_BTR1_CLKDIV            FMC_BTR1_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7828 #define FMC_BTR1_CLKDIV_0          (0x1UL << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00100000 */
7829 #define FMC_BTR1_CLKDIV_1          (0x2UL << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00200000 */
7830 #define FMC_BTR1_CLKDIV_2          (0x4UL << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00400000 */
7831 #define FMC_BTR1_CLKDIV_3          (0x8UL << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00800000 */
7832 #define FMC_BTR1_DATLAT_Pos        (24U)
7833 #define FMC_BTR1_DATLAT_Msk        (0xFUL << FMC_BTR1_DATLAT_Pos)               /*!< 0x0F000000 */
7834 #define FMC_BTR1_DATLAT            FMC_BTR1_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
7835 #define FMC_BTR1_DATLAT_0          (0x1UL << FMC_BTR1_DATLAT_Pos)               /*!< 0x01000000 */
7836 #define FMC_BTR1_DATLAT_1          (0x2UL << FMC_BTR1_DATLAT_Pos)               /*!< 0x02000000 */
7837 #define FMC_BTR1_DATLAT_2          (0x4UL << FMC_BTR1_DATLAT_Pos)               /*!< 0x04000000 */
7838 #define FMC_BTR1_DATLAT_3          (0x8UL << FMC_BTR1_DATLAT_Pos)               /*!< 0x08000000 */
7839 #define FMC_BTR1_ACCMOD_Pos        (28U)
7840 #define FMC_BTR1_ACCMOD_Msk        (0x3UL << FMC_BTR1_ACCMOD_Pos)               /*!< 0x30000000 */
7841 #define FMC_BTR1_ACCMOD            FMC_BTR1_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
7842 #define FMC_BTR1_ACCMOD_0          (0x1UL << FMC_BTR1_ACCMOD_Pos)               /*!< 0x10000000 */
7843 #define FMC_BTR1_ACCMOD_1          (0x2UL << FMC_BTR1_ACCMOD_Pos)               /*!< 0x20000000 */
7844 
7845 /******************  Bit definition for FMC_BTR2 register  *******************/
7846 #define FMC_BTR2_ADDSET_Pos        (0U)
7847 #define FMC_BTR2_ADDSET_Msk        (0xFUL << FMC_BTR2_ADDSET_Pos)               /*!< 0x0000000F */
7848 #define FMC_BTR2_ADDSET            FMC_BTR2_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
7849 #define FMC_BTR2_ADDSET_0          (0x1UL << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000001 */
7850 #define FMC_BTR2_ADDSET_1          (0x2UL << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000002 */
7851 #define FMC_BTR2_ADDSET_2          (0x4UL << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000004 */
7852 #define FMC_BTR2_ADDSET_3          (0x8UL << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000008 */
7853 #define FMC_BTR2_ADDHLD_Pos        (4U)
7854 #define FMC_BTR2_ADDHLD_Msk        (0xFUL << FMC_BTR2_ADDHLD_Pos)               /*!< 0x000000F0 */
7855 #define FMC_BTR2_ADDHLD            FMC_BTR2_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7856 #define FMC_BTR2_ADDHLD_0          (0x1UL << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000010 */
7857 #define FMC_BTR2_ADDHLD_1          (0x2UL << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000020 */
7858 #define FMC_BTR2_ADDHLD_2          (0x4UL << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000040 */
7859 #define FMC_BTR2_ADDHLD_3          (0x8UL << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000080 */
7860 #define FMC_BTR2_DATAST_Pos        (8U)
7861 #define FMC_BTR2_DATAST_Msk        (0xFFUL << FMC_BTR2_DATAST_Pos)              /*!< 0x0000FF00 */
7862 #define FMC_BTR2_DATAST            FMC_BTR2_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
7863 #define FMC_BTR2_DATAST_0          (0x01UL << FMC_BTR2_DATAST_Pos)              /*!< 0x00000100 */
7864 #define FMC_BTR2_DATAST_1          (0x02UL << FMC_BTR2_DATAST_Pos)              /*!< 0x00000200 */
7865 #define FMC_BTR2_DATAST_2          (0x04UL << FMC_BTR2_DATAST_Pos)              /*!< 0x00000400 */
7866 #define FMC_BTR2_DATAST_3          (0x08UL << FMC_BTR2_DATAST_Pos)              /*!< 0x00000800 */
7867 #define FMC_BTR2_DATAST_4          (0x10UL << FMC_BTR2_DATAST_Pos)              /*!< 0x00001000 */
7868 #define FMC_BTR2_DATAST_5          (0x20UL << FMC_BTR2_DATAST_Pos)              /*!< 0x00002000 */
7869 #define FMC_BTR2_DATAST_6          (0x40UL << FMC_BTR2_DATAST_Pos)              /*!< 0x00004000 */
7870 #define FMC_BTR2_DATAST_7          (0x80UL << FMC_BTR2_DATAST_Pos)              /*!< 0x00008000 */
7871 #define FMC_BTR2_BUSTURN_Pos       (16U)
7872 #define FMC_BTR2_BUSTURN_Msk       (0xFUL << FMC_BTR2_BUSTURN_Pos)              /*!< 0x000F0000 */
7873 #define FMC_BTR2_BUSTURN           FMC_BTR2_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7874 #define FMC_BTR2_BUSTURN_0         (0x1UL << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00010000 */
7875 #define FMC_BTR2_BUSTURN_1         (0x2UL << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00020000 */
7876 #define FMC_BTR2_BUSTURN_2         (0x4UL << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00040000 */
7877 #define FMC_BTR2_BUSTURN_3         (0x8UL << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00080000 */
7878 #define FMC_BTR2_CLKDIV_Pos        (20U)
7879 #define FMC_BTR2_CLKDIV_Msk        (0xFUL << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00F00000 */
7880 #define FMC_BTR2_CLKDIV            FMC_BTR2_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7881 #define FMC_BTR2_CLKDIV_0          (0x1UL << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00100000 */
7882 #define FMC_BTR2_CLKDIV_1          (0x2UL << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00200000 */
7883 #define FMC_BTR2_CLKDIV_2          (0x4UL << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00400000 */
7884 #define FMC_BTR2_CLKDIV_3          (0x8UL << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00800000 */
7885 #define FMC_BTR2_DATLAT_Pos        (24U)
7886 #define FMC_BTR2_DATLAT_Msk        (0xFUL << FMC_BTR2_DATLAT_Pos)               /*!< 0x0F000000 */
7887 #define FMC_BTR2_DATLAT            FMC_BTR2_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
7888 #define FMC_BTR2_DATLAT_0          (0x1UL << FMC_BTR2_DATLAT_Pos)               /*!< 0x01000000 */
7889 #define FMC_BTR2_DATLAT_1          (0x2UL << FMC_BTR2_DATLAT_Pos)               /*!< 0x02000000 */
7890 #define FMC_BTR2_DATLAT_2          (0x4UL << FMC_BTR2_DATLAT_Pos)               /*!< 0x04000000 */
7891 #define FMC_BTR2_DATLAT_3          (0x8UL << FMC_BTR2_DATLAT_Pos)               /*!< 0x08000000 */
7892 #define FMC_BTR2_ACCMOD_Pos        (28U)
7893 #define FMC_BTR2_ACCMOD_Msk        (0x3UL << FMC_BTR2_ACCMOD_Pos)               /*!< 0x30000000 */
7894 #define FMC_BTR2_ACCMOD            FMC_BTR2_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
7895 #define FMC_BTR2_ACCMOD_0          (0x1UL << FMC_BTR2_ACCMOD_Pos)               /*!< 0x10000000 */
7896 #define FMC_BTR2_ACCMOD_1          (0x2UL << FMC_BTR2_ACCMOD_Pos)               /*!< 0x20000000 */
7897 
7898 /*******************  Bit definition for FMC_BTR3 register  *******************/
7899 #define FMC_BTR3_ADDSET_Pos        (0U)
7900 #define FMC_BTR3_ADDSET_Msk        (0xFUL << FMC_BTR3_ADDSET_Pos)               /*!< 0x0000000F */
7901 #define FMC_BTR3_ADDSET            FMC_BTR3_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
7902 #define FMC_BTR3_ADDSET_0          (0x1UL << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000001 */
7903 #define FMC_BTR3_ADDSET_1          (0x2UL << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000002 */
7904 #define FMC_BTR3_ADDSET_2          (0x4UL << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000004 */
7905 #define FMC_BTR3_ADDSET_3          (0x8UL << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000008 */
7906 #define FMC_BTR3_ADDHLD_Pos        (4U)
7907 #define FMC_BTR3_ADDHLD_Msk        (0xFUL << FMC_BTR3_ADDHLD_Pos)               /*!< 0x000000F0 */
7908 #define FMC_BTR3_ADDHLD            FMC_BTR3_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7909 #define FMC_BTR3_ADDHLD_0          (0x1UL << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000010 */
7910 #define FMC_BTR3_ADDHLD_1          (0x2UL << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000020 */
7911 #define FMC_BTR3_ADDHLD_2          (0x4UL << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000040 */
7912 #define FMC_BTR3_ADDHLD_3          (0x8UL << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000080 */
7913 #define FMC_BTR3_DATAST_Pos        (8U)
7914 #define FMC_BTR3_DATAST_Msk        (0xFFUL << FMC_BTR3_DATAST_Pos)              /*!< 0x0000FF00 */
7915 #define FMC_BTR3_DATAST            FMC_BTR3_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
7916 #define FMC_BTR3_DATAST_0          (0x01UL << FMC_BTR3_DATAST_Pos)              /*!< 0x00000100 */
7917 #define FMC_BTR3_DATAST_1          (0x02UL << FMC_BTR3_DATAST_Pos)              /*!< 0x00000200 */
7918 #define FMC_BTR3_DATAST_2          (0x04UL << FMC_BTR3_DATAST_Pos)              /*!< 0x00000400 */
7919 #define FMC_BTR3_DATAST_3          (0x08UL << FMC_BTR3_DATAST_Pos)              /*!< 0x00000800 */
7920 #define FMC_BTR3_DATAST_4          (0x10UL << FMC_BTR3_DATAST_Pos)              /*!< 0x00001000 */
7921 #define FMC_BTR3_DATAST_5          (0x20UL << FMC_BTR3_DATAST_Pos)              /*!< 0x00002000 */
7922 #define FMC_BTR3_DATAST_6          (0x40UL << FMC_BTR3_DATAST_Pos)              /*!< 0x00004000 */
7923 #define FMC_BTR3_DATAST_7          (0x80UL << FMC_BTR3_DATAST_Pos)              /*!< 0x00008000 */
7924 #define FMC_BTR3_BUSTURN_Pos       (16U)
7925 #define FMC_BTR3_BUSTURN_Msk       (0xFUL << FMC_BTR3_BUSTURN_Pos)              /*!< 0x000F0000 */
7926 #define FMC_BTR3_BUSTURN           FMC_BTR3_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7927 #define FMC_BTR3_BUSTURN_0         (0x1UL << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00010000 */
7928 #define FMC_BTR3_BUSTURN_1         (0x2UL << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00020000 */
7929 #define FMC_BTR3_BUSTURN_2         (0x4UL << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00040000 */
7930 #define FMC_BTR3_BUSTURN_3         (0x8UL << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00080000 */
7931 #define FMC_BTR3_CLKDIV_Pos        (20U)
7932 #define FMC_BTR3_CLKDIV_Msk        (0xFUL << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00F00000 */
7933 #define FMC_BTR3_CLKDIV            FMC_BTR3_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7934 #define FMC_BTR3_CLKDIV_0          (0x1UL << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00100000 */
7935 #define FMC_BTR3_CLKDIV_1          (0x2UL << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00200000 */
7936 #define FMC_BTR3_CLKDIV_2          (0x4UL << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00400000 */
7937 #define FMC_BTR3_CLKDIV_3          (0x8UL << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00800000 */
7938 #define FMC_BTR3_DATLAT_Pos        (24U)
7939 #define FMC_BTR3_DATLAT_Msk        (0xFUL << FMC_BTR3_DATLAT_Pos)               /*!< 0x0F000000 */
7940 #define FMC_BTR3_DATLAT            FMC_BTR3_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
7941 #define FMC_BTR3_DATLAT_0          (0x1UL << FMC_BTR3_DATLAT_Pos)               /*!< 0x01000000 */
7942 #define FMC_BTR3_DATLAT_1          (0x2UL << FMC_BTR3_DATLAT_Pos)               /*!< 0x02000000 */
7943 #define FMC_BTR3_DATLAT_2          (0x4UL << FMC_BTR3_DATLAT_Pos)               /*!< 0x04000000 */
7944 #define FMC_BTR3_DATLAT_3          (0x8UL << FMC_BTR3_DATLAT_Pos)               /*!< 0x08000000 */
7945 #define FMC_BTR3_ACCMOD_Pos        (28U)
7946 #define FMC_BTR3_ACCMOD_Msk        (0x3UL << FMC_BTR3_ACCMOD_Pos)               /*!< 0x30000000 */
7947 #define FMC_BTR3_ACCMOD            FMC_BTR3_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
7948 #define FMC_BTR3_ACCMOD_0          (0x1UL << FMC_BTR3_ACCMOD_Pos)               /*!< 0x10000000 */
7949 #define FMC_BTR3_ACCMOD_1          (0x2UL << FMC_BTR3_ACCMOD_Pos)               /*!< 0x20000000 */
7950 
7951 /******************  Bit definition for FMC_BTR4 register  *******************/
7952 #define FMC_BTR4_ADDSET_Pos        (0U)
7953 #define FMC_BTR4_ADDSET_Msk        (0xFUL << FMC_BTR4_ADDSET_Pos)               /*!< 0x0000000F */
7954 #define FMC_BTR4_ADDSET            FMC_BTR4_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
7955 #define FMC_BTR4_ADDSET_0          (0x1UL << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000001 */
7956 #define FMC_BTR4_ADDSET_1          (0x2UL << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000002 */
7957 #define FMC_BTR4_ADDSET_2          (0x4UL << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000004 */
7958 #define FMC_BTR4_ADDSET_3          (0x8UL << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000008 */
7959 #define FMC_BTR4_ADDHLD_Pos        (4U)
7960 #define FMC_BTR4_ADDHLD_Msk        (0xFUL << FMC_BTR4_ADDHLD_Pos)               /*!< 0x000000F0 */
7961 #define FMC_BTR4_ADDHLD            FMC_BTR4_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7962 #define FMC_BTR4_ADDHLD_0          (0x1UL << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000010 */
7963 #define FMC_BTR4_ADDHLD_1          (0x2UL << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000020 */
7964 #define FMC_BTR4_ADDHLD_2          (0x4UL << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000040 */
7965 #define FMC_BTR4_ADDHLD_3          (0x8UL << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000080 */
7966 #define FMC_BTR4_DATAST_Pos        (8U)
7967 #define FMC_BTR4_DATAST_Msk        (0xFFUL << FMC_BTR4_DATAST_Pos)              /*!< 0x0000FF00 */
7968 #define FMC_BTR4_DATAST            FMC_BTR4_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
7969 #define FMC_BTR4_DATAST_0          (0x01UL << FMC_BTR4_DATAST_Pos)              /*!< 0x00000100 */
7970 #define FMC_BTR4_DATAST_1          (0x02UL << FMC_BTR4_DATAST_Pos)              /*!< 0x00000200 */
7971 #define FMC_BTR4_DATAST_2          (0x04UL << FMC_BTR4_DATAST_Pos)              /*!< 0x00000400 */
7972 #define FMC_BTR4_DATAST_3          (0x08UL << FMC_BTR4_DATAST_Pos)              /*!< 0x00000800 */
7973 #define FMC_BTR4_DATAST_4          (0x10UL << FMC_BTR4_DATAST_Pos)              /*!< 0x00001000 */
7974 #define FMC_BTR4_DATAST_5          (0x20UL << FMC_BTR4_DATAST_Pos)              /*!< 0x00002000 */
7975 #define FMC_BTR4_DATAST_6          (0x40UL << FMC_BTR4_DATAST_Pos)              /*!< 0x00004000 */
7976 #define FMC_BTR4_DATAST_7          (0x80UL << FMC_BTR4_DATAST_Pos)              /*!< 0x00008000 */
7977 #define FMC_BTR4_BUSTURN_Pos       (16U)
7978 #define FMC_BTR4_BUSTURN_Msk       (0xFUL << FMC_BTR4_BUSTURN_Pos)              /*!< 0x000F0000 */
7979 #define FMC_BTR4_BUSTURN           FMC_BTR4_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7980 #define FMC_BTR4_BUSTURN_0         (0x1UL << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00010000 */
7981 #define FMC_BTR4_BUSTURN_1         (0x2UL << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00020000 */
7982 #define FMC_BTR4_BUSTURN_2         (0x4UL << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00040000 */
7983 #define FMC_BTR4_BUSTURN_3         (0x8UL << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00080000 */
7984 #define FMC_BTR4_CLKDIV_Pos        (20U)
7985 #define FMC_BTR4_CLKDIV_Msk        (0xFUL << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00F00000 */
7986 #define FMC_BTR4_CLKDIV            FMC_BTR4_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7987 #define FMC_BTR4_CLKDIV_0          (0x1UL << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00100000 */
7988 #define FMC_BTR4_CLKDIV_1          (0x2UL << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00200000 */
7989 #define FMC_BTR4_CLKDIV_2          (0x4UL << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00400000 */
7990 #define FMC_BTR4_CLKDIV_3          (0x8UL << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00800000 */
7991 #define FMC_BTR4_DATLAT_Pos        (24U)
7992 #define FMC_BTR4_DATLAT_Msk        (0xFUL << FMC_BTR4_DATLAT_Pos)               /*!< 0x0F000000 */
7993 #define FMC_BTR4_DATLAT            FMC_BTR4_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
7994 #define FMC_BTR4_DATLAT_0          (0x1UL << FMC_BTR4_DATLAT_Pos)               /*!< 0x01000000 */
7995 #define FMC_BTR4_DATLAT_1          (0x2UL << FMC_BTR4_DATLAT_Pos)               /*!< 0x02000000 */
7996 #define FMC_BTR4_DATLAT_2          (0x4UL << FMC_BTR4_DATLAT_Pos)               /*!< 0x04000000 */
7997 #define FMC_BTR4_DATLAT_3          (0x8UL << FMC_BTR4_DATLAT_Pos)               /*!< 0x08000000 */
7998 #define FMC_BTR4_ACCMOD_Pos        (28U)
7999 #define FMC_BTR4_ACCMOD_Msk        (0x3UL << FMC_BTR4_ACCMOD_Pos)               /*!< 0x30000000 */
8000 #define FMC_BTR4_ACCMOD            FMC_BTR4_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
8001 #define FMC_BTR4_ACCMOD_0          (0x1UL << FMC_BTR4_ACCMOD_Pos)               /*!< 0x10000000 */
8002 #define FMC_BTR4_ACCMOD_1          (0x2UL << FMC_BTR4_ACCMOD_Pos)               /*!< 0x20000000 */
8003 
8004 /******************  Bit definition for FMC_BWTR1 register  ******************/
8005 #define FMC_BWTR1_ADDSET_Pos       (0U)
8006 #define FMC_BWTR1_ADDSET_Msk       (0xFUL << FMC_BWTR1_ADDSET_Pos)              /*!< 0x0000000F */
8007 #define FMC_BWTR1_ADDSET           FMC_BWTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
8008 #define FMC_BWTR1_ADDSET_0         (0x1UL << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000001 */
8009 #define FMC_BWTR1_ADDSET_1         (0x2UL << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000002 */
8010 #define FMC_BWTR1_ADDSET_2         (0x4UL << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000004 */
8011 #define FMC_BWTR1_ADDSET_3         (0x8UL << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000008 */
8012 #define FMC_BWTR1_ADDHLD_Pos       (4U)
8013 #define FMC_BWTR1_ADDHLD_Msk       (0xFUL << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
8014 #define FMC_BWTR1_ADDHLD           FMC_BWTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8015 #define FMC_BWTR1_ADDHLD_0         (0x1UL << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000010 */
8016 #define FMC_BWTR1_ADDHLD_1         (0x2UL << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000020 */
8017 #define FMC_BWTR1_ADDHLD_2         (0x4UL << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000040 */
8018 #define FMC_BWTR1_ADDHLD_3         (0x8UL << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000080 */
8019 #define FMC_BWTR1_DATAST_Pos       (8U)
8020 #define FMC_BWTR1_DATAST_Msk       (0xFFUL << FMC_BWTR1_DATAST_Pos)             /*!< 0x0000FF00 */
8021 #define FMC_BWTR1_DATAST           FMC_BWTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
8022 #define FMC_BWTR1_DATAST_0         (0x01UL << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000100 */
8023 #define FMC_BWTR1_DATAST_1         (0x02UL << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000200 */
8024 #define FMC_BWTR1_DATAST_2         (0x04UL << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000400 */
8025 #define FMC_BWTR1_DATAST_3         (0x08UL << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000800 */
8026 #define FMC_BWTR1_DATAST_4         (0x10UL << FMC_BWTR1_DATAST_Pos)             /*!< 0x00001000 */
8027 #define FMC_BWTR1_DATAST_5         (0x20UL << FMC_BWTR1_DATAST_Pos)             /*!< 0x00002000 */
8028 #define FMC_BWTR1_DATAST_6         (0x40UL << FMC_BWTR1_DATAST_Pos)             /*!< 0x00004000 */
8029 #define FMC_BWTR1_DATAST_7         (0x80UL << FMC_BWTR1_DATAST_Pos)             /*!< 0x00008000 */
8030 #define FMC_BWTR1_BUSTURN_Pos      (16U)
8031 #define FMC_BWTR1_BUSTURN_Msk      (0xFUL << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
8032 #define FMC_BWTR1_BUSTURN          FMC_BWTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8033 #define FMC_BWTR1_BUSTURN_0        (0x1UL << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00010000 */
8034 #define FMC_BWTR1_BUSTURN_1        (0x2UL << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00020000 */
8035 #define FMC_BWTR1_BUSTURN_2        (0x4UL << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00040000 */
8036 #define FMC_BWTR1_BUSTURN_3        (0x8UL << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00080000 */
8037 #define FMC_BWTR1_ACCMOD_Pos       (28U)
8038 #define FMC_BWTR1_ACCMOD_Msk       (0x3UL << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x30000000 */
8039 #define FMC_BWTR1_ACCMOD           FMC_BWTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
8040 #define FMC_BWTR1_ACCMOD_0         (0x1UL << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x10000000 */
8041 #define FMC_BWTR1_ACCMOD_1         (0x2UL << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x20000000 */
8042 
8043 /******************  Bit definition for FMC_BWTR2 register  ******************/
8044 #define FMC_BWTR2_ADDSET_Pos       (0U)
8045 #define FMC_BWTR2_ADDSET_Msk       (0xFUL << FMC_BWTR2_ADDSET_Pos)              /*!< 0x0000000F */
8046 #define FMC_BWTR2_ADDSET           FMC_BWTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
8047 #define FMC_BWTR2_ADDSET_0         (0x1UL << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000001 */
8048 #define FMC_BWTR2_ADDSET_1         (0x2UL << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000002 */
8049 #define FMC_BWTR2_ADDSET_2         (0x4UL << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000004 */
8050 #define FMC_BWTR2_ADDSET_3         (0x8UL << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000008 */
8051 #define FMC_BWTR2_ADDHLD_Pos       (4U)
8052 #define FMC_BWTR2_ADDHLD_Msk       (0xFUL << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
8053 #define FMC_BWTR2_ADDHLD           FMC_BWTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8054 #define FMC_BWTR2_ADDHLD_0         (0x1UL << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000010 */
8055 #define FMC_BWTR2_ADDHLD_1         (0x2UL << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000020 */
8056 #define FMC_BWTR2_ADDHLD_2         (0x4UL << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000040 */
8057 #define FMC_BWTR2_ADDHLD_3         (0x8UL << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000080 */
8058 #define FMC_BWTR2_DATAST_Pos       (8U)
8059 #define FMC_BWTR2_DATAST_Msk       (0xFFUL << FMC_BWTR2_DATAST_Pos)             /*!< 0x0000FF00 */
8060 #define FMC_BWTR2_DATAST           FMC_BWTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
8061 #define FMC_BWTR2_DATAST_0         (0x01UL << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000100 */
8062 #define FMC_BWTR2_DATAST_1         (0x02UL << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000200 */
8063 #define FMC_BWTR2_DATAST_2         (0x04UL << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000400 */
8064 #define FMC_BWTR2_DATAST_3         (0x08UL << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000800 */
8065 #define FMC_BWTR2_DATAST_4         (0x10UL << FMC_BWTR2_DATAST_Pos)             /*!< 0x00001000 */
8066 #define FMC_BWTR2_DATAST_5         (0x20UL << FMC_BWTR2_DATAST_Pos)             /*!< 0x00002000 */
8067 #define FMC_BWTR2_DATAST_6         (0x40UL << FMC_BWTR2_DATAST_Pos)             /*!< 0x00004000 */
8068 #define FMC_BWTR2_DATAST_7         (0x80UL << FMC_BWTR2_DATAST_Pos)             /*!< 0x00008000 */
8069 #define FMC_BWTR2_BUSTURN_Pos      (16U)
8070 #define FMC_BWTR2_BUSTURN_Msk      (0xFUL << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x000F0000 */
8071 #define FMC_BWTR2_BUSTURN          FMC_BWTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8072 #define FMC_BWTR2_BUSTURN_0        (0x1UL << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x00010000 */
8073 #define FMC_BWTR2_BUSTURN_1        (0x2UL << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x00020000 */
8074 #define FMC_BWTR2_BUSTURN_2        (0x4UL << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x00040000 */
8075 #define FMC_BWTR2_BUSTURN_3        (0x8UL << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x00080000 */
8076 #define FMC_BWTR2_ACCMOD_Pos       (28U)
8077 #define FMC_BWTR2_ACCMOD_Msk       (0x3UL << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x30000000 */
8078 #define FMC_BWTR2_ACCMOD           FMC_BWTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
8079 #define FMC_BWTR2_ACCMOD_0         (0x1UL << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x10000000 */
8080 #define FMC_BWTR2_ACCMOD_1         (0x2UL << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x20000000 */
8081 
8082 /******************  Bit definition for FMC_BWTR3 register  ******************/
8083 #define FMC_BWTR3_ADDSET_Pos       (0U)
8084 #define FMC_BWTR3_ADDSET_Msk       (0xFUL << FMC_BWTR3_ADDSET_Pos)              /*!< 0x0000000F */
8085 #define FMC_BWTR3_ADDSET           FMC_BWTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
8086 #define FMC_BWTR3_ADDSET_0         (0x1UL << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000001 */
8087 #define FMC_BWTR3_ADDSET_1         (0x2UL << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000002 */
8088 #define FMC_BWTR3_ADDSET_2         (0x4UL << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000004 */
8089 #define FMC_BWTR3_ADDSET_3         (0x8UL << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000008 */
8090 #define FMC_BWTR3_ADDHLD_Pos       (4U)
8091 #define FMC_BWTR3_ADDHLD_Msk       (0xFUL << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
8092 #define FMC_BWTR3_ADDHLD           FMC_BWTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8093 #define FMC_BWTR3_ADDHLD_0         (0x1UL << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000010 */
8094 #define FMC_BWTR3_ADDHLD_1         (0x2UL << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000020 */
8095 #define FMC_BWTR3_ADDHLD_2         (0x4UL << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000040 */
8096 #define FMC_BWTR3_ADDHLD_3         (0x8UL << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000080 */
8097 #define FMC_BWTR3_DATAST_Pos       (8U)
8098 #define FMC_BWTR3_DATAST_Msk       (0xFFUL << FMC_BWTR3_DATAST_Pos)             /*!< 0x0000FF00 */
8099 #define FMC_BWTR3_DATAST           FMC_BWTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
8100 #define FMC_BWTR3_DATAST_0         (0x01UL << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000100 */
8101 #define FMC_BWTR3_DATAST_1         (0x02UL << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000200 */
8102 #define FMC_BWTR3_DATAST_2         (0x04UL << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000400 */
8103 #define FMC_BWTR3_DATAST_3         (0x08UL << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000800 */
8104 #define FMC_BWTR3_DATAST_4         (0x10UL << FMC_BWTR3_DATAST_Pos)             /*!< 0x00001000 */
8105 #define FMC_BWTR3_DATAST_5         (0x20UL << FMC_BWTR3_DATAST_Pos)             /*!< 0x00002000 */
8106 #define FMC_BWTR3_DATAST_6         (0x40UL << FMC_BWTR3_DATAST_Pos)             /*!< 0x00004000 */
8107 #define FMC_BWTR3_DATAST_7         (0x80UL << FMC_BWTR3_DATAST_Pos)             /*!< 0x00008000 */
8108 #define FMC_BWTR3_BUSTURN_Pos      (16U)
8109 #define FMC_BWTR3_BUSTURN_Msk      (0xFUL << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x000F0000 */
8110 #define FMC_BWTR3_BUSTURN          FMC_BWTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8111 #define FMC_BWTR3_BUSTURN_0        (0x1UL << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x00010000 */
8112 #define FMC_BWTR3_BUSTURN_1        (0x2UL << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x00020000 */
8113 #define FMC_BWTR3_BUSTURN_2        (0x4UL << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x00040000 */
8114 #define FMC_BWTR3_BUSTURN_3        (0x8UL << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x00080000 */
8115 #define FMC_BWTR3_ACCMOD_Pos       (28U)
8116 #define FMC_BWTR3_ACCMOD_Msk       (0x3UL << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x30000000 */
8117 #define FMC_BWTR3_ACCMOD           FMC_BWTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
8118 #define FMC_BWTR3_ACCMOD_0         (0x1UL << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x10000000 */
8119 #define FMC_BWTR3_ACCMOD_1         (0x2UL << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x20000000 */
8120 
8121 /******************  Bit definition for FMC_BWTR4 register  ******************/
8122 #define FMC_BWTR4_ADDSET_Pos       (0U)
8123 #define FMC_BWTR4_ADDSET_Msk       (0xFUL << FMC_BWTR4_ADDSET_Pos)              /*!< 0x0000000F */
8124 #define FMC_BWTR4_ADDSET           FMC_BWTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
8125 #define FMC_BWTR4_ADDSET_0         (0x1UL << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000001 */
8126 #define FMC_BWTR4_ADDSET_1         (0x2UL << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000002 */
8127 #define FMC_BWTR4_ADDSET_2         (0x4UL << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000004 */
8128 #define FMC_BWTR4_ADDSET_3         (0x8UL << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000008 */
8129 #define FMC_BWTR4_ADDHLD_Pos       (4U)
8130 #define FMC_BWTR4_ADDHLD_Msk       (0xFUL << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
8131 #define FMC_BWTR4_ADDHLD           FMC_BWTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8132 #define FMC_BWTR4_ADDHLD_0         (0x1UL << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000010 */
8133 #define FMC_BWTR4_ADDHLD_1         (0x2UL << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000020 */
8134 #define FMC_BWTR4_ADDHLD_2         (0x4UL << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000040 */
8135 #define FMC_BWTR4_ADDHLD_3         (0x8UL << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000080 */
8136 #define FMC_BWTR4_DATAST_Pos       (8U)
8137 #define FMC_BWTR4_DATAST_Msk       (0xFFUL << FMC_BWTR4_DATAST_Pos)             /*!< 0x0000FF00 */
8138 #define FMC_BWTR4_DATAST           FMC_BWTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
8139 #define FMC_BWTR4_DATAST_0         (0x01UL << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000100 */
8140 #define FMC_BWTR4_DATAST_1         (0x02UL << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000200 */
8141 #define FMC_BWTR4_DATAST_2         (0x04UL << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000400 */
8142 #define FMC_BWTR4_DATAST_3         (0x08UL << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000800 */
8143 #define FMC_BWTR4_DATAST_4         (0x10UL << FMC_BWTR4_DATAST_Pos)             /*!< 0x00001000 */
8144 #define FMC_BWTR4_DATAST_5         (0x20UL << FMC_BWTR4_DATAST_Pos)             /*!< 0x00002000 */
8145 #define FMC_BWTR4_DATAST_6         (0x40UL << FMC_BWTR4_DATAST_Pos)             /*!< 0x00004000 */
8146 #define FMC_BWTR4_DATAST_7         (0x80UL << FMC_BWTR4_DATAST_Pos)             /*!< 0x00008000 */
8147 #define FMC_BWTR4_BUSTURN_Pos      (16U)
8148 #define FMC_BWTR4_BUSTURN_Msk      (0xFUL << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x000F0000 */
8149 #define FMC_BWTR4_BUSTURN          FMC_BWTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8150 #define FMC_BWTR4_BUSTURN_0        (0x1UL << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x00010000 */
8151 #define FMC_BWTR4_BUSTURN_1        (0x2UL << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x00020000 */
8152 #define FMC_BWTR4_BUSTURN_2        (0x4UL << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x00040000 */
8153 #define FMC_BWTR4_BUSTURN_3        (0x8UL << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x00080000 */
8154 #define FMC_BWTR4_ACCMOD_Pos       (28U)
8155 #define FMC_BWTR4_ACCMOD_Msk       (0x3UL << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x30000000 */
8156 #define FMC_BWTR4_ACCMOD           FMC_BWTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
8157 #define FMC_BWTR4_ACCMOD_0         (0x1UL << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x10000000 */
8158 #define FMC_BWTR4_ACCMOD_1         (0x2UL << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x20000000 */
8159 
8160 /******************  Bit definition for FMC_PCR register  *******************/
8161 #define FMC_PCR_PWAITEN_Pos        (1U)
8162 #define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */
8163 #define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
8164 #define FMC_PCR_PBKEN_Pos          (2U)
8165 #define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */
8166 #define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<PC Card/NAND Flash memory bank enable bit */
8167 #define FMC_PCR_PTYP_Pos           (3U)
8168 #define FMC_PCR_PTYP_Msk           (0x1UL << FMC_PCR_PTYP_Pos)                  /*!< 0x00000008 */
8169 #define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */
8170 #define FMC_PCR_PWID_Pos           (4U)
8171 #define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */
8172 #define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
8173 #define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
8174 #define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
8175 #define FMC_PCR_ECCEN_Pos          (6U)
8176 #define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */
8177 #define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
8178 #define FMC_PCR_TCLR_Pos           (9U)
8179 #define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */
8180 #define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
8181 #define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
8182 #define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
8183 #define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
8184 #define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
8185 #define FMC_PCR_TAR_Pos            (13U)
8186 #define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */
8187 #define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
8188 #define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
8189 #define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
8190 #define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
8191 #define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
8192 #define FMC_PCR_ECCPS_Pos          (17U)
8193 #define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x000E0000 */
8194 #define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[2:0] bits (ECC page size)           */
8195 #define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
8196 #define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
8197 #define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
8198 
8199 /*******************  Bit definition for FMC_SR register  *******************/
8200 #define FMC_SR_IRS_Pos             (0U)
8201 #define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                    /*!< 0x00000001 */
8202 #define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
8203 #define FMC_SR_ILS_Pos             (1U)
8204 #define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                    /*!< 0x00000002 */
8205 #define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
8206 #define FMC_SR_IFS_Pos             (2U)
8207 #define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                    /*!< 0x00000004 */
8208 #define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
8209 #define FMC_SR_IREN_Pos            (3U)
8210 #define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                   /*!< 0x00000008 */
8211 #define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
8212 #define FMC_SR_ILEN_Pos            (4U)
8213 #define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                   /*!< 0x00000010 */
8214 #define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
8215 #define FMC_SR_IFEN_Pos            (5U)
8216 #define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                   /*!< 0x00000020 */
8217 #define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
8218 #define FMC_SR_FEMPT_Pos           (6U)
8219 #define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                  /*!< 0x00000040 */
8220 #define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
8221 
8222 /******************  Bit definition for FMC_PMEM register  ******************/
8223 #define FMC_PMEM_MEMSET3_Pos       (0U)
8224 #define FMC_PMEM_MEMSET3_Msk       (0xFFUL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x000000FF */
8225 #define FMC_PMEM_MEMSET3           FMC_PMEM_MEMSET3_Msk                        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
8226 #define FMC_PMEM_MEMSET3_0         (0x01UL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000001 */
8227 #define FMC_PMEM_MEMSET3_1         (0x02UL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000002 */
8228 #define FMC_PMEM_MEMSET3_2         (0x04UL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000004 */
8229 #define FMC_PMEM_MEMSET3_3         (0x08UL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000008 */
8230 #define FMC_PMEM_MEMSET3_4         (0x10UL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000010 */
8231 #define FMC_PMEM_MEMSET3_5         (0x20UL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000020 */
8232 #define FMC_PMEM_MEMSET3_6         (0x40UL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000040 */
8233 #define FMC_PMEM_MEMSET3_7         (0x80UL << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000080 */
8234 #define FMC_PMEM_MEMWAIT3_Pos      (8U)
8235 #define FMC_PMEM_MEMWAIT3_Msk      (0xFFUL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x0000FF00 */
8236 #define FMC_PMEM_MEMWAIT3          FMC_PMEM_MEMWAIT3_Msk                       /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
8237 #define FMC_PMEM_MEMWAIT3_0        (0x01UL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000100 */
8238 #define FMC_PMEM_MEMWAIT3_1        (0x02UL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000200 */
8239 #define FMC_PMEM_MEMWAIT3_2        (0x04UL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000400 */
8240 #define FMC_PMEM_MEMWAIT3_3        (0x08UL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000800 */
8241 #define FMC_PMEM_MEMWAIT3_4        (0x10UL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00001000 */
8242 #define FMC_PMEM_MEMWAIT3_5        (0x20UL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00002000 */
8243 #define FMC_PMEM_MEMWAIT3_6        (0x40UL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00004000 */
8244 #define FMC_PMEM_MEMWAIT3_7        (0x80UL << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00008000 */
8245 #define FMC_PMEM_MEMHOLD3_Pos      (16U)
8246 #define FMC_PMEM_MEMHOLD3_Msk      (0xFFUL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00FF0000 */
8247 #define FMC_PMEM_MEMHOLD3          FMC_PMEM_MEMHOLD3_Msk                       /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
8248 #define FMC_PMEM_MEMHOLD3_0        (0x01UL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00010000 */
8249 #define FMC_PMEM_MEMHOLD3_1        (0x02UL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00020000 */
8250 #define FMC_PMEM_MEMHOLD3_2        (0x04UL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00040000 */
8251 #define FMC_PMEM_MEMHOLD3_3        (0x08UL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00080000 */
8252 #define FMC_PMEM_MEMHOLD3_4        (0x10UL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00100000 */
8253 #define FMC_PMEM_MEMHOLD3_5        (0x20UL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00200000 */
8254 #define FMC_PMEM_MEMHOLD3_6        (0x40UL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00400000 */
8255 #define FMC_PMEM_MEMHOLD3_7        (0x80UL << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00800000 */
8256 #define FMC_PMEM_MEMHIZ3_Pos       (24U)
8257 #define FMC_PMEM_MEMHIZ3_Msk       (0xFFUL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0xFF000000 */
8258 #define FMC_PMEM_MEMHIZ3           FMC_PMEM_MEMHIZ3_Msk                        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
8259 #define FMC_PMEM_MEMHIZ3_0         (0x01UL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x01000000 */
8260 #define FMC_PMEM_MEMHIZ3_1         (0x02UL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x02000000 */
8261 #define FMC_PMEM_MEMHIZ3_2         (0x04UL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x04000000 */
8262 #define FMC_PMEM_MEMHIZ3_3         (0x08UL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x08000000 */
8263 #define FMC_PMEM_MEMHIZ3_4         (0x10UL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x10000000 */
8264 #define FMC_PMEM_MEMHIZ3_5         (0x20UL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x20000000 */
8265 #define FMC_PMEM_MEMHIZ3_6         (0x40UL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x40000000 */
8266 #define FMC_PMEM_MEMHIZ3_7         (0x80UL << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x80000000 */
8267 
8268 /******************  Bit definition for FMC_PATT register  ******************/
8269 #define FMC_PATT_ATTSET3_Pos       (0U)
8270 #define FMC_PATT_ATTSET3_Msk       (0xFFUL << FMC_PATT_ATTSET3_Pos)             /*!< 0x000000FF */
8271 #define FMC_PATT_ATTSET3           FMC_PATT_ATTSET3_Msk                        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
8272 #define FMC_PATT_ATTSET3_0         (0x01UL << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000001 */
8273 #define FMC_PATT_ATTSET3_1         (0x02UL << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000002 */
8274 #define FMC_PATT_ATTSET3_2         (0x04UL << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000004 */
8275 #define FMC_PATT_ATTSET3_3         (0x08UL << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000008 */
8276 #define FMC_PATT_ATTSET3_4         (0x10UL << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000010 */
8277 #define FMC_PATT_ATTSET3_5         (0x20UL << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000020 */
8278 #define FMC_PATT_ATTSET3_6         (0x40UL << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000040 */
8279 #define FMC_PATT_ATTSET3_7         (0x80UL << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000080 */
8280 #define FMC_PATT_ATTWAIT3_Pos      (8U)
8281 #define FMC_PATT_ATTWAIT3_Msk      (0xFFUL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x0000FF00 */
8282 #define FMC_PATT_ATTWAIT3          FMC_PATT_ATTWAIT3_Msk                       /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
8283 #define FMC_PATT_ATTWAIT3_0        (0x01UL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000100 */
8284 #define FMC_PATT_ATTWAIT3_1        (0x02UL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000200 */
8285 #define FMC_PATT_ATTWAIT3_2        (0x04UL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000400 */
8286 #define FMC_PATT_ATTWAIT3_3        (0x08UL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000800 */
8287 #define FMC_PATT_ATTWAIT3_4        (0x10UL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00001000 */
8288 #define FMC_PATT_ATTWAIT3_5        (0x20UL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00002000 */
8289 #define FMC_PATT_ATTWAIT3_6        (0x40UL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00004000 */
8290 #define FMC_PATT_ATTWAIT3_7        (0x80UL << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00008000 */
8291 #define FMC_PATT_ATTHOLD3_Pos      (16U)
8292 #define FMC_PATT_ATTHOLD3_Msk      (0xFFUL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00FF0000 */
8293 #define FMC_PATT_ATTHOLD3          FMC_PATT_ATTHOLD3_Msk                       /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
8294 #define FMC_PATT_ATTHOLD3_0        (0x01UL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00010000 */
8295 #define FMC_PATT_ATTHOLD3_1        (0x02UL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00020000 */
8296 #define FMC_PATT_ATTHOLD3_2        (0x04UL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00040000 */
8297 #define FMC_PATT_ATTHOLD3_3        (0x08UL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00080000 */
8298 #define FMC_PATT_ATTHOLD3_4        (0x10UL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00100000 */
8299 #define FMC_PATT_ATTHOLD3_5        (0x20UL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00200000 */
8300 #define FMC_PATT_ATTHOLD3_6        (0x40UL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00400000 */
8301 #define FMC_PATT_ATTHOLD3_7        (0x80UL << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00800000 */
8302 #define FMC_PATT_ATTHIZ3_Pos       (24U)
8303 #define FMC_PATT_ATTHIZ3_Msk       (0xFFUL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0xFF000000 */
8304 #define FMC_PATT_ATTHIZ3           FMC_PATT_ATTHIZ3_Msk                        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
8305 #define FMC_PATT_ATTHIZ3_0         (0x01UL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x01000000 */
8306 #define FMC_PATT_ATTHIZ3_1         (0x02UL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x02000000 */
8307 #define FMC_PATT_ATTHIZ3_2         (0x04UL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x04000000 */
8308 #define FMC_PATT_ATTHIZ3_3         (0x08UL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x08000000 */
8309 #define FMC_PATT_ATTHIZ3_4         (0x10UL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x10000000 */
8310 #define FMC_PATT_ATTHIZ3_5         (0x20UL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x20000000 */
8311 #define FMC_PATT_ATTHIZ3_6         (0x40UL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x40000000 */
8312 #define FMC_PATT_ATTHIZ3_7         (0x80UL << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x80000000 */
8313 
8314 /******************  Bit definition for FMC_ECCR register  ******************/
8315 #define FMC_ECCR_ECC3_Pos          (0U)
8316 #define FMC_ECCR_ECC3_Msk          (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos)          /*!< 0xFFFFFFFF */
8317 #define FMC_ECCR_ECC3              FMC_ECCR_ECC3_Msk                           /*!<ECC result */
8318 
8319 /******************  Bit definition for FMC_SDCR1 register  ******************/
8320 #define FMC_SDCR1_NC_Pos           (0U)
8321 #define FMC_SDCR1_NC_Msk           (0x3UL << FMC_SDCR1_NC_Pos)                  /*!< 0x00000003 */
8322 #define FMC_SDCR1_NC               FMC_SDCR1_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
8323 #define FMC_SDCR1_NC_0             (0x1UL << FMC_SDCR1_NC_Pos)                  /*!< 0x00000001 */
8324 #define FMC_SDCR1_NC_1             (0x2UL << FMC_SDCR1_NC_Pos)                  /*!< 0x00000002 */
8325 #define FMC_SDCR1_NR_Pos           (2U)
8326 #define FMC_SDCR1_NR_Msk           (0x3UL << FMC_SDCR1_NR_Pos)                  /*!< 0x0000000C */
8327 #define FMC_SDCR1_NR               FMC_SDCR1_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
8328 #define FMC_SDCR1_NR_0             (0x1UL << FMC_SDCR1_NR_Pos)                  /*!< 0x00000004 */
8329 #define FMC_SDCR1_NR_1             (0x2UL << FMC_SDCR1_NR_Pos)                  /*!< 0x00000008 */
8330 #define FMC_SDCR1_MWID_Pos         (4U)
8331 #define FMC_SDCR1_MWID_Msk         (0x3UL << FMC_SDCR1_MWID_Pos)                /*!< 0x00000030 */
8332 #define FMC_SDCR1_MWID             FMC_SDCR1_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
8333 #define FMC_SDCR1_MWID_0           (0x1UL << FMC_SDCR1_MWID_Pos)                /*!< 0x00000010 */
8334 #define FMC_SDCR1_MWID_1           (0x2UL << FMC_SDCR1_MWID_Pos)                /*!< 0x00000020 */
8335 #define FMC_SDCR1_NB_Pos           (6U)
8336 #define FMC_SDCR1_NB_Msk           (0x1UL << FMC_SDCR1_NB_Pos)                  /*!< 0x00000040 */
8337 #define FMC_SDCR1_NB               FMC_SDCR1_NB_Msk                            /*!<Number of internal bank */
8338 #define FMC_SDCR1_CAS_Pos          (7U)
8339 #define FMC_SDCR1_CAS_Msk          (0x3UL << FMC_SDCR1_CAS_Pos)                 /*!< 0x00000180 */
8340 #define FMC_SDCR1_CAS              FMC_SDCR1_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
8341 #define FMC_SDCR1_CAS_0            (0x1UL << FMC_SDCR1_CAS_Pos)                 /*!< 0x00000080 */
8342 #define FMC_SDCR1_CAS_1            (0x2UL << FMC_SDCR1_CAS_Pos)                 /*!< 0x00000100 */
8343 #define FMC_SDCR1_WP_Pos           (9U)
8344 #define FMC_SDCR1_WP_Msk           (0x1UL << FMC_SDCR1_WP_Pos)                  /*!< 0x00000200 */
8345 #define FMC_SDCR1_WP               FMC_SDCR1_WP_Msk                            /*!<Write protection */
8346 #define FMC_SDCR1_SDCLK_Pos        (10U)
8347 #define FMC_SDCR1_SDCLK_Msk        (0x3UL << FMC_SDCR1_SDCLK_Pos)               /*!< 0x00000C00 */
8348 #define FMC_SDCR1_SDCLK            FMC_SDCR1_SDCLK_Msk                         /*!<SDRAM clock configuration */
8349 #define FMC_SDCR1_SDCLK_0          (0x1UL << FMC_SDCR1_SDCLK_Pos)               /*!< 0x00000400 */
8350 #define FMC_SDCR1_SDCLK_1          (0x2UL << FMC_SDCR1_SDCLK_Pos)               /*!< 0x00000800 */
8351 #define FMC_SDCR1_RBURST_Pos       (12U)
8352 #define FMC_SDCR1_RBURST_Msk       (0x1UL << FMC_SDCR1_RBURST_Pos)              /*!< 0x00001000 */
8353 #define FMC_SDCR1_RBURST           FMC_SDCR1_RBURST_Msk                        /*!<Read burst */
8354 #define FMC_SDCR1_RPIPE_Pos        (13U)
8355 #define FMC_SDCR1_RPIPE_Msk        (0x3UL << FMC_SDCR1_RPIPE_Pos)               /*!< 0x00006000 */
8356 #define FMC_SDCR1_RPIPE            FMC_SDCR1_RPIPE_Msk                         /*!<Write protection */
8357 #define FMC_SDCR1_RPIPE_0          (0x1UL << FMC_SDCR1_RPIPE_Pos)               /*!< 0x00002000 */
8358 #define FMC_SDCR1_RPIPE_1          (0x2UL << FMC_SDCR1_RPIPE_Pos)               /*!< 0x00004000 */
8359 
8360 /******************  Bit definition for FMC_SDCR2 register  ******************/
8361 #define FMC_SDCR2_NC_Pos           (0U)
8362 #define FMC_SDCR2_NC_Msk           (0x3UL << FMC_SDCR2_NC_Pos)                  /*!< 0x00000003 */
8363 #define FMC_SDCR2_NC               FMC_SDCR2_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
8364 #define FMC_SDCR2_NC_0             (0x1UL << FMC_SDCR2_NC_Pos)                  /*!< 0x00000001 */
8365 #define FMC_SDCR2_NC_1             (0x2UL << FMC_SDCR2_NC_Pos)                  /*!< 0x00000002 */
8366 #define FMC_SDCR2_NR_Pos           (2U)
8367 #define FMC_SDCR2_NR_Msk           (0x3UL << FMC_SDCR2_NR_Pos)                  /*!< 0x0000000C */
8368 #define FMC_SDCR2_NR               FMC_SDCR2_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
8369 #define FMC_SDCR2_NR_0             (0x1UL << FMC_SDCR2_NR_Pos)                  /*!< 0x00000004 */
8370 #define FMC_SDCR2_NR_1             (0x2UL << FMC_SDCR2_NR_Pos)                  /*!< 0x00000008 */
8371 #define FMC_SDCR2_MWID_Pos         (4U)
8372 #define FMC_SDCR2_MWID_Msk         (0x3UL << FMC_SDCR2_MWID_Pos)                /*!< 0x00000030 */
8373 #define FMC_SDCR2_MWID             FMC_SDCR2_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
8374 #define FMC_SDCR2_MWID_0           (0x1UL << FMC_SDCR2_MWID_Pos)                /*!< 0x00000010 */
8375 #define FMC_SDCR2_MWID_1           (0x2UL << FMC_SDCR2_MWID_Pos)                /*!< 0x00000020 */
8376 #define FMC_SDCR2_NB_Pos           (6U)
8377 #define FMC_SDCR2_NB_Msk           (0x1UL << FMC_SDCR2_NB_Pos)                  /*!< 0x00000040 */
8378 #define FMC_SDCR2_NB               FMC_SDCR2_NB_Msk                            /*!<Number of internal bank */
8379 #define FMC_SDCR2_CAS_Pos          (7U)
8380 #define FMC_SDCR2_CAS_Msk          (0x3UL << FMC_SDCR2_CAS_Pos)                 /*!< 0x00000180 */
8381 #define FMC_SDCR2_CAS              FMC_SDCR2_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
8382 #define FMC_SDCR2_CAS_0            (0x1UL << FMC_SDCR2_CAS_Pos)                 /*!< 0x00000080 */
8383 #define FMC_SDCR2_CAS_1            (0x2UL << FMC_SDCR2_CAS_Pos)                 /*!< 0x00000100 */
8384 #define FMC_SDCR2_WP_Pos           (9U)
8385 #define FMC_SDCR2_WP_Msk           (0x1UL << FMC_SDCR2_WP_Pos)                  /*!< 0x00000200 */
8386 #define FMC_SDCR2_WP               FMC_SDCR2_WP_Msk                            /*!<Write protection */
8387 #define FMC_SDCR2_SDCLK_Pos        (10U)
8388 #define FMC_SDCR2_SDCLK_Msk        (0x3UL << FMC_SDCR2_SDCLK_Pos)               /*!< 0x00000C00 */
8389 #define FMC_SDCR2_SDCLK            FMC_SDCR2_SDCLK_Msk                         /*!<SDCLK[1:0] (SDRAM clock configuration) */
8390 #define FMC_SDCR2_SDCLK_0          (0x1UL << FMC_SDCR2_SDCLK_Pos)               /*!< 0x00000400 */
8391 #define FMC_SDCR2_SDCLK_1          (0x2UL << FMC_SDCR2_SDCLK_Pos)               /*!< 0x00000800 */
8392 #define FMC_SDCR2_RBURST_Pos       (12U)
8393 #define FMC_SDCR2_RBURST_Msk       (0x1UL << FMC_SDCR2_RBURST_Pos)              /*!< 0x00001000 */
8394 #define FMC_SDCR2_RBURST           FMC_SDCR2_RBURST_Msk                        /*!<Read burst */
8395 #define FMC_SDCR2_RPIPE_Pos        (13U)
8396 #define FMC_SDCR2_RPIPE_Msk        (0x3UL << FMC_SDCR2_RPIPE_Pos)               /*!< 0x00006000 */
8397 #define FMC_SDCR2_RPIPE            FMC_SDCR2_RPIPE_Msk                         /*!<RPIPE[1:0](Read pipe) */
8398 #define FMC_SDCR2_RPIPE_0          (0x1UL << FMC_SDCR2_RPIPE_Pos)               /*!< 0x00002000 */
8399 #define FMC_SDCR2_RPIPE_1          (0x2UL << FMC_SDCR2_RPIPE_Pos)               /*!< 0x00004000 */
8400 
8401 /******************  Bit definition for FMC_SDTR1 register  ******************/
8402 #define FMC_SDTR1_TMRD_Pos         (0U)
8403 #define FMC_SDTR1_TMRD_Msk         (0xFUL << FMC_SDTR1_TMRD_Pos)                /*!< 0x0000000F */
8404 #define FMC_SDTR1_TMRD             FMC_SDTR1_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
8405 #define FMC_SDTR1_TMRD_0           (0x1UL << FMC_SDTR1_TMRD_Pos)                /*!< 0x00000001 */
8406 #define FMC_SDTR1_TMRD_1           (0x2UL << FMC_SDTR1_TMRD_Pos)                /*!< 0x00000002 */
8407 #define FMC_SDTR1_TMRD_2           (0x4UL << FMC_SDTR1_TMRD_Pos)                /*!< 0x00000004 */
8408 #define FMC_SDTR1_TMRD_3           (0x8UL << FMC_SDTR1_TMRD_Pos)                /*!< 0x00000008 */
8409 #define FMC_SDTR1_TXSR_Pos         (4U)
8410 #define FMC_SDTR1_TXSR_Msk         (0xFUL << FMC_SDTR1_TXSR_Pos)                /*!< 0x000000F0 */
8411 #define FMC_SDTR1_TXSR             FMC_SDTR1_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
8412 #define FMC_SDTR1_TXSR_0           (0x1UL << FMC_SDTR1_TXSR_Pos)                /*!< 0x00000010 */
8413 #define FMC_SDTR1_TXSR_1           (0x2UL << FMC_SDTR1_TXSR_Pos)                /*!< 0x00000020 */
8414 #define FMC_SDTR1_TXSR_2           (0x4UL << FMC_SDTR1_TXSR_Pos)                /*!< 0x00000040 */
8415 #define FMC_SDTR1_TXSR_3           (0x8UL << FMC_SDTR1_TXSR_Pos)                /*!< 0x00000080 */
8416 #define FMC_SDTR1_TRAS_Pos         (8U)
8417 #define FMC_SDTR1_TRAS_Msk         (0xFUL << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000F00 */
8418 #define FMC_SDTR1_TRAS             FMC_SDTR1_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
8419 #define FMC_SDTR1_TRAS_0           (0x1UL << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000100 */
8420 #define FMC_SDTR1_TRAS_1           (0x2UL << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000200 */
8421 #define FMC_SDTR1_TRAS_2           (0x4UL << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000400 */
8422 #define FMC_SDTR1_TRAS_3           (0x8UL << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000800 */
8423 #define FMC_SDTR1_TRC_Pos          (12U)
8424 #define FMC_SDTR1_TRC_Msk          (0xFUL << FMC_SDTR1_TRC_Pos)                 /*!< 0x0000F000 */
8425 #define FMC_SDTR1_TRC              FMC_SDTR1_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
8426 #define FMC_SDTR1_TRC_0            (0x1UL << FMC_SDTR1_TRC_Pos)                 /*!< 0x00001000 */
8427 #define FMC_SDTR1_TRC_1            (0x2UL << FMC_SDTR1_TRC_Pos)                 /*!< 0x00002000 */
8428 #define FMC_SDTR1_TRC_2            (0x4UL << FMC_SDTR1_TRC_Pos)                 /*!< 0x00004000 */
8429 #define FMC_SDTR1_TWR_Pos          (16U)
8430 #define FMC_SDTR1_TWR_Msk          (0xFUL << FMC_SDTR1_TWR_Pos)                 /*!< 0x000F0000 */
8431 #define FMC_SDTR1_TWR              FMC_SDTR1_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
8432 #define FMC_SDTR1_TWR_0            (0x1UL << FMC_SDTR1_TWR_Pos)                 /*!< 0x00010000 */
8433 #define FMC_SDTR1_TWR_1            (0x2UL << FMC_SDTR1_TWR_Pos)                 /*!< 0x00020000 */
8434 #define FMC_SDTR1_TWR_2            (0x4UL << FMC_SDTR1_TWR_Pos)                 /*!< 0x00040000 */
8435 #define FMC_SDTR1_TRP_Pos          (20U)
8436 #define FMC_SDTR1_TRP_Msk          (0xFUL << FMC_SDTR1_TRP_Pos)                 /*!< 0x00F00000 */
8437 #define FMC_SDTR1_TRP              FMC_SDTR1_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
8438 #define FMC_SDTR1_TRP_0            (0x1UL << FMC_SDTR1_TRP_Pos)                 /*!< 0x00100000 */
8439 #define FMC_SDTR1_TRP_1            (0x2UL << FMC_SDTR1_TRP_Pos)                 /*!< 0x00200000 */
8440 #define FMC_SDTR1_TRP_2            (0x4UL << FMC_SDTR1_TRP_Pos)                 /*!< 0x00400000 */
8441 #define FMC_SDTR1_TRCD_Pos         (24U)
8442 #define FMC_SDTR1_TRCD_Msk         (0xFUL << FMC_SDTR1_TRCD_Pos)                /*!< 0x0F000000 */
8443 #define FMC_SDTR1_TRCD             FMC_SDTR1_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
8444 #define FMC_SDTR1_TRCD_0           (0x1UL << FMC_SDTR1_TRCD_Pos)                /*!< 0x01000000 */
8445 #define FMC_SDTR1_TRCD_1           (0x2UL << FMC_SDTR1_TRCD_Pos)                /*!< 0x02000000 */
8446 #define FMC_SDTR1_TRCD_2           (0x4UL << FMC_SDTR1_TRCD_Pos)                /*!< 0x04000000 */
8447 
8448 /******************  Bit definition for FMC_SDTR2 register  ******************/
8449 #define FMC_SDTR2_TMRD_Pos         (0U)
8450 #define FMC_SDTR2_TMRD_Msk         (0xFUL << FMC_SDTR2_TMRD_Pos)                /*!< 0x0000000F */
8451 #define FMC_SDTR2_TMRD             FMC_SDTR2_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
8452 #define FMC_SDTR2_TMRD_0           (0x1UL << FMC_SDTR2_TMRD_Pos)                /*!< 0x00000001 */
8453 #define FMC_SDTR2_TMRD_1           (0x2UL << FMC_SDTR2_TMRD_Pos)                /*!< 0x00000002 */
8454 #define FMC_SDTR2_TMRD_2           (0x4UL << FMC_SDTR2_TMRD_Pos)                /*!< 0x00000004 */
8455 #define FMC_SDTR2_TMRD_3           (0x8UL << FMC_SDTR2_TMRD_Pos)                /*!< 0x00000008 */
8456 #define FMC_SDTR2_TXSR_Pos         (4U)
8457 #define FMC_SDTR2_TXSR_Msk         (0xFUL << FMC_SDTR2_TXSR_Pos)                /*!< 0x000000F0 */
8458 #define FMC_SDTR2_TXSR             FMC_SDTR2_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
8459 #define FMC_SDTR2_TXSR_0           (0x1UL << FMC_SDTR2_TXSR_Pos)                /*!< 0x00000010 */
8460 #define FMC_SDTR2_TXSR_1           (0x2UL << FMC_SDTR2_TXSR_Pos)                /*!< 0x00000020 */
8461 #define FMC_SDTR2_TXSR_2           (0x4UL << FMC_SDTR2_TXSR_Pos)                /*!< 0x00000040 */
8462 #define FMC_SDTR2_TXSR_3           (0x8UL << FMC_SDTR2_TXSR_Pos)                /*!< 0x00000080 */
8463 #define FMC_SDTR2_TRAS_Pos         (8U)
8464 #define FMC_SDTR2_TRAS_Msk         (0xFUL << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000F00 */
8465 #define FMC_SDTR2_TRAS             FMC_SDTR2_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
8466 #define FMC_SDTR2_TRAS_0           (0x1UL << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000100 */
8467 #define FMC_SDTR2_TRAS_1           (0x2UL << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000200 */
8468 #define FMC_SDTR2_TRAS_2           (0x4UL << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000400 */
8469 #define FMC_SDTR2_TRAS_3           (0x8UL << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000800 */
8470 #define FMC_SDTR2_TRC_Pos          (12U)
8471 #define FMC_SDTR2_TRC_Msk          (0xFUL << FMC_SDTR2_TRC_Pos)                 /*!< 0x0000F000 */
8472 #define FMC_SDTR2_TRC              FMC_SDTR2_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
8473 #define FMC_SDTR2_TRC_0            (0x1UL << FMC_SDTR2_TRC_Pos)                 /*!< 0x00001000 */
8474 #define FMC_SDTR2_TRC_1            (0x2UL << FMC_SDTR2_TRC_Pos)                 /*!< 0x00002000 */
8475 #define FMC_SDTR2_TRC_2            (0x4UL << FMC_SDTR2_TRC_Pos)                 /*!< 0x00004000 */
8476 #define FMC_SDTR2_TWR_Pos          (16U)
8477 #define FMC_SDTR2_TWR_Msk          (0xFUL << FMC_SDTR2_TWR_Pos)                 /*!< 0x000F0000 */
8478 #define FMC_SDTR2_TWR              FMC_SDTR2_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
8479 #define FMC_SDTR2_TWR_0            (0x1UL << FMC_SDTR2_TWR_Pos)                 /*!< 0x00010000 */
8480 #define FMC_SDTR2_TWR_1            (0x2UL << FMC_SDTR2_TWR_Pos)                 /*!< 0x00020000 */
8481 #define FMC_SDTR2_TWR_2            (0x4UL << FMC_SDTR2_TWR_Pos)                 /*!< 0x00040000 */
8482 #define FMC_SDTR2_TRP_Pos          (20U)
8483 #define FMC_SDTR2_TRP_Msk          (0xFUL << FMC_SDTR2_TRP_Pos)                 /*!< 0x00F00000 */
8484 #define FMC_SDTR2_TRP              FMC_SDTR2_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
8485 #define FMC_SDTR2_TRP_0            (0x1UL << FMC_SDTR2_TRP_Pos)                 /*!< 0x00100000 */
8486 #define FMC_SDTR2_TRP_1            (0x2UL << FMC_SDTR2_TRP_Pos)                 /*!< 0x00200000 */
8487 #define FMC_SDTR2_TRP_2            (0x4UL << FMC_SDTR2_TRP_Pos)                 /*!< 0x00400000 */
8488 #define FMC_SDTR2_TRCD_Pos         (24U)
8489 #define FMC_SDTR2_TRCD_Msk         (0xFUL << FMC_SDTR2_TRCD_Pos)                /*!< 0x0F000000 */
8490 #define FMC_SDTR2_TRCD             FMC_SDTR2_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
8491 #define FMC_SDTR2_TRCD_0           (0x1UL << FMC_SDTR2_TRCD_Pos)                /*!< 0x01000000 */
8492 #define FMC_SDTR2_TRCD_1           (0x2UL << FMC_SDTR2_TRCD_Pos)                /*!< 0x02000000 */
8493 #define FMC_SDTR2_TRCD_2           (0x4UL << FMC_SDTR2_TRCD_Pos)                /*!< 0x04000000 */
8494 
8495 /******************  Bit definition for FMC_SDCMR register  ******************/
8496 #define FMC_SDCMR_MODE_Pos         (0U)
8497 #define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000007 */
8498 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
8499 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
8500 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
8501 #define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
8502 #define FMC_SDCMR_CTB2_Pos         (3U)
8503 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)                /*!< 0x00000008 */
8504 #define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
8505 #define FMC_SDCMR_CTB1_Pos         (4U)
8506 #define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)                /*!< 0x00000010 */
8507 #define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
8508 #define FMC_SDCMR_NRFS_Pos         (5U)
8509 #define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)                /*!< 0x000001E0 */
8510 #define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
8511 #define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
8512 #define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
8513 #define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
8514 #define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
8515 #define FMC_SDCMR_MRD_Pos          (9U)
8516 #define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)              /*!< 0x003FFE00 */
8517 #define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
8518 
8519 /******************  Bit definition for FMC_SDRTR register  ******************/
8520 #define FMC_SDRTR_CRE_Pos          (0U)
8521 #define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                 /*!< 0x00000001 */
8522 #define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
8523 #define FMC_SDRTR_COUNT_Pos        (1U)
8524 #define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)            /*!< 0x00003FFE */
8525 #define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
8526 #define FMC_SDRTR_REIE_Pos         (14U)
8527 #define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)                /*!< 0x00004000 */
8528 #define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interrupt enable */
8529 
8530 /******************  Bit definition for FMC_SDSR register  ******************/
8531 #define FMC_SDSR_RE_Pos            (0U)
8532 #define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                   /*!< 0x00000001 */
8533 #define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
8534 #define FMC_SDSR_MODES1_Pos        (1U)
8535 #define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000006 */
8536 #define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
8537 #define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
8538 #define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
8539 #define FMC_SDSR_MODES2_Pos        (3U)
8540 #define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000018 */
8541 #define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
8542 #define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
8543 #define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
8544 #define FMC_SDSR_BUSY_Pos          (5U)
8545 #define FMC_SDSR_BUSY_Msk          (0x1UL << FMC_SDSR_BUSY_Pos)                 /*!< 0x00000020 */
8546 #define FMC_SDSR_BUSY              FMC_SDSR_BUSY_Msk                           /*!<Busy status */
8547 
8548 /******************************************************************************/
8549 /*                                                                            */
8550 /*                            General Purpose I/O                             */
8551 /*                                                                            */
8552 /******************************************************************************/
8553 /******************  Bits definition for GPIO_MODER register  *****************/
8554 #define GPIO_MODER_MODER0_Pos            (0U)
8555 #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
8556 #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
8557 #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
8558 #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
8559 #define GPIO_MODER_MODER1_Pos            (2U)
8560 #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
8561 #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
8562 #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
8563 #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
8564 #define GPIO_MODER_MODER2_Pos            (4U)
8565 #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
8566 #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
8567 #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
8568 #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
8569 #define GPIO_MODER_MODER3_Pos            (6U)
8570 #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
8571 #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
8572 #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
8573 #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
8574 #define GPIO_MODER_MODER4_Pos            (8U)
8575 #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
8576 #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
8577 #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
8578 #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
8579 #define GPIO_MODER_MODER5_Pos            (10U)
8580 #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
8581 #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
8582 #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
8583 #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
8584 #define GPIO_MODER_MODER6_Pos            (12U)
8585 #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
8586 #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
8587 #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
8588 #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
8589 #define GPIO_MODER_MODER7_Pos            (14U)
8590 #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
8591 #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
8592 #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
8593 #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
8594 #define GPIO_MODER_MODER8_Pos            (16U)
8595 #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
8596 #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
8597 #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
8598 #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
8599 #define GPIO_MODER_MODER9_Pos            (18U)
8600 #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
8601 #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
8602 #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
8603 #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
8604 #define GPIO_MODER_MODER10_Pos           (20U)
8605 #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
8606 #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
8607 #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
8608 #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
8609 #define GPIO_MODER_MODER11_Pos           (22U)
8610 #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
8611 #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
8612 #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
8613 #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
8614 #define GPIO_MODER_MODER12_Pos           (24U)
8615 #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
8616 #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
8617 #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
8618 #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
8619 #define GPIO_MODER_MODER13_Pos           (26U)
8620 #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
8621 #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
8622 #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
8623 #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
8624 #define GPIO_MODER_MODER14_Pos           (28U)
8625 #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
8626 #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
8627 #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
8628 #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
8629 #define GPIO_MODER_MODER15_Pos           (30U)
8630 #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
8631 #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
8632 #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
8633 #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
8634 
8635 /******************  Bits definition for GPIO_OTYPER register  ****************/
8636 #define GPIO_OTYPER_OT0_Pos              (0U)
8637 #define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
8638 #define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk
8639 #define GPIO_OTYPER_OT1_Pos              (1U)
8640 #define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
8641 #define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk
8642 #define GPIO_OTYPER_OT2_Pos              (2U)
8643 #define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
8644 #define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk
8645 #define GPIO_OTYPER_OT3_Pos              (3U)
8646 #define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
8647 #define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk
8648 #define GPIO_OTYPER_OT4_Pos              (4U)
8649 #define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
8650 #define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk
8651 #define GPIO_OTYPER_OT5_Pos              (5U)
8652 #define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
8653 #define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk
8654 #define GPIO_OTYPER_OT6_Pos              (6U)
8655 #define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
8656 #define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk
8657 #define GPIO_OTYPER_OT7_Pos              (7U)
8658 #define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
8659 #define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk
8660 #define GPIO_OTYPER_OT8_Pos              (8U)
8661 #define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
8662 #define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk
8663 #define GPIO_OTYPER_OT9_Pos              (9U)
8664 #define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
8665 #define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk
8666 #define GPIO_OTYPER_OT10_Pos             (10U)
8667 #define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
8668 #define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk
8669 #define GPIO_OTYPER_OT11_Pos             (11U)
8670 #define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
8671 #define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk
8672 #define GPIO_OTYPER_OT12_Pos             (12U)
8673 #define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
8674 #define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk
8675 #define GPIO_OTYPER_OT13_Pos             (13U)
8676 #define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
8677 #define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk
8678 #define GPIO_OTYPER_OT14_Pos             (14U)
8679 #define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
8680 #define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk
8681 #define GPIO_OTYPER_OT15_Pos             (15U)
8682 #define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
8683 #define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk
8684 
8685 /* Legacy defines */
8686 #define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
8687 #define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
8688 #define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
8689 #define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
8690 #define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
8691 #define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
8692 #define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
8693 #define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
8694 #define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
8695 #define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
8696 #define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
8697 #define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
8698 #define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
8699 #define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
8700 #define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
8701 #define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
8702 
8703 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
8704 #define GPIO_OSPEEDR_OSPEEDR0_Pos       (0U)
8705 #define GPIO_OSPEEDR_OSPEEDR0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos)  /*!< 0x00000003 */
8706 #define GPIO_OSPEEDR_OSPEEDR0           GPIO_OSPEEDR_OSPEEDR0_Msk
8707 #define GPIO_OSPEEDR_OSPEEDR0_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos)  /*!< 0x00000001 */
8708 #define GPIO_OSPEEDR_OSPEEDR0_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos)  /*!< 0x00000002 */
8709 #define GPIO_OSPEEDR_OSPEEDR1_Pos       (2U)
8710 #define GPIO_OSPEEDR_OSPEEDR1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos)  /*!< 0x0000000C */
8711 #define GPIO_OSPEEDR_OSPEEDR1           GPIO_OSPEEDR_OSPEEDR1_Msk
8712 #define GPIO_OSPEEDR_OSPEEDR1_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos)  /*!< 0x00000004 */
8713 #define GPIO_OSPEEDR_OSPEEDR1_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos)  /*!< 0x00000008 */
8714 #define GPIO_OSPEEDR_OSPEEDR2_Pos       (4U)
8715 #define GPIO_OSPEEDR_OSPEEDR2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos)  /*!< 0x00000030 */
8716 #define GPIO_OSPEEDR_OSPEEDR2           GPIO_OSPEEDR_OSPEEDR2_Msk
8717 #define GPIO_OSPEEDR_OSPEEDR2_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos)  /*!< 0x00000010 */
8718 #define GPIO_OSPEEDR_OSPEEDR2_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos)  /*!< 0x00000020 */
8719 #define GPIO_OSPEEDR_OSPEEDR3_Pos       (6U)
8720 #define GPIO_OSPEEDR_OSPEEDR3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos)  /*!< 0x000000C0 */
8721 #define GPIO_OSPEEDR_OSPEEDR3           GPIO_OSPEEDR_OSPEEDR3_Msk
8722 #define GPIO_OSPEEDR_OSPEEDR3_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos)  /*!< 0x00000040 */
8723 #define GPIO_OSPEEDR_OSPEEDR3_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos)  /*!< 0x00000080 */
8724 #define GPIO_OSPEEDR_OSPEEDR4_Pos       (8U)
8725 #define GPIO_OSPEEDR_OSPEEDR4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos)  /*!< 0x00000300 */
8726 #define GPIO_OSPEEDR_OSPEEDR4           GPIO_OSPEEDR_OSPEEDR4_Msk
8727 #define GPIO_OSPEEDR_OSPEEDR4_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos)  /*!< 0x00000100 */
8728 #define GPIO_OSPEEDR_OSPEEDR4_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos)  /*!< 0x00000200 */
8729 #define GPIO_OSPEEDR_OSPEEDR5_Pos       (10U)
8730 #define GPIO_OSPEEDR_OSPEEDR5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos)  /*!< 0x00000C00 */
8731 #define GPIO_OSPEEDR_OSPEEDR5           GPIO_OSPEEDR_OSPEEDR5_Msk
8732 #define GPIO_OSPEEDR_OSPEEDR5_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos)  /*!< 0x00000400 */
8733 #define GPIO_OSPEEDR_OSPEEDR5_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos)  /*!< 0x00000800 */
8734 #define GPIO_OSPEEDR_OSPEEDR6_Pos       (12U)
8735 #define GPIO_OSPEEDR_OSPEEDR6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos)  /*!< 0x00003000 */
8736 #define GPIO_OSPEEDR_OSPEEDR6           GPIO_OSPEEDR_OSPEEDR6_Msk
8737 #define GPIO_OSPEEDR_OSPEEDR6_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos)  /*!< 0x00001000 */
8738 #define GPIO_OSPEEDR_OSPEEDR6_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos)  /*!< 0x00002000 */
8739 #define GPIO_OSPEEDR_OSPEEDR7_Pos       (14U)
8740 #define GPIO_OSPEEDR_OSPEEDR7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos)  /*!< 0x0000C000 */
8741 #define GPIO_OSPEEDR_OSPEEDR7           GPIO_OSPEEDR_OSPEEDR7_Msk
8742 #define GPIO_OSPEEDR_OSPEEDR7_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos)  /*!< 0x00004000 */
8743 #define GPIO_OSPEEDR_OSPEEDR7_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos)  /*!< 0x00008000 */
8744 #define GPIO_OSPEEDR_OSPEEDR8_Pos       (16U)
8745 #define GPIO_OSPEEDR_OSPEEDR8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos)  /*!< 0x00030000 */
8746 #define GPIO_OSPEEDR_OSPEEDR8           GPIO_OSPEEDR_OSPEEDR8_Msk
8747 #define GPIO_OSPEEDR_OSPEEDR8_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos)  /*!< 0x00010000 */
8748 #define GPIO_OSPEEDR_OSPEEDR8_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos)  /*!< 0x00020000 */
8749 #define GPIO_OSPEEDR_OSPEEDR9_Pos       (18U)
8750 #define GPIO_OSPEEDR_OSPEEDR9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos)  /*!< 0x000C0000 */
8751 #define GPIO_OSPEEDR_OSPEEDR9           GPIO_OSPEEDR_OSPEEDR9_Msk
8752 #define GPIO_OSPEEDR_OSPEEDR9_0         (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos)  /*!< 0x00040000 */
8753 #define GPIO_OSPEEDR_OSPEEDR9_1         (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos)  /*!< 0x00080000 */
8754 #define GPIO_OSPEEDR_OSPEEDR10_Pos      (20U)
8755 #define GPIO_OSPEEDR_OSPEEDR10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
8756 #define GPIO_OSPEEDR_OSPEEDR10          GPIO_OSPEEDR_OSPEEDR10_Msk
8757 #define GPIO_OSPEEDR_OSPEEDR10_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
8758 #define GPIO_OSPEEDR_OSPEEDR10_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
8759 #define GPIO_OSPEEDR_OSPEEDR11_Pos      (22U)
8760 #define GPIO_OSPEEDR_OSPEEDR11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
8761 #define GPIO_OSPEEDR_OSPEEDR11          GPIO_OSPEEDR_OSPEEDR11_Msk
8762 #define GPIO_OSPEEDR_OSPEEDR11_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
8763 #define GPIO_OSPEEDR_OSPEEDR11_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
8764 #define GPIO_OSPEEDR_OSPEEDR12_Pos      (24U)
8765 #define GPIO_OSPEEDR_OSPEEDR12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
8766 #define GPIO_OSPEEDR_OSPEEDR12          GPIO_OSPEEDR_OSPEEDR12_Msk
8767 #define GPIO_OSPEEDR_OSPEEDR12_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
8768 #define GPIO_OSPEEDR_OSPEEDR12_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
8769 #define GPIO_OSPEEDR_OSPEEDR13_Pos      (26U)
8770 #define GPIO_OSPEEDR_OSPEEDR13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
8771 #define GPIO_OSPEEDR_OSPEEDR13          GPIO_OSPEEDR_OSPEEDR13_Msk
8772 #define GPIO_OSPEEDR_OSPEEDR13_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
8773 #define GPIO_OSPEEDR_OSPEEDR13_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
8774 #define GPIO_OSPEEDR_OSPEEDR14_Pos      (28U)
8775 #define GPIO_OSPEEDR_OSPEEDR14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
8776 #define GPIO_OSPEEDR_OSPEEDR14          GPIO_OSPEEDR_OSPEEDR14_Msk
8777 #define GPIO_OSPEEDR_OSPEEDR14_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
8778 #define GPIO_OSPEEDR_OSPEEDR14_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
8779 #define GPIO_OSPEEDR_OSPEEDR15_Pos      (30U)
8780 #define GPIO_OSPEEDR_OSPEEDR15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
8781 #define GPIO_OSPEEDR_OSPEEDR15          GPIO_OSPEEDR_OSPEEDR15_Msk
8782 #define GPIO_OSPEEDR_OSPEEDR15_0        (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
8783 #define GPIO_OSPEEDR_OSPEEDR15_1        (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
8784 
8785 /* legacy defines */
8786 #define GPIO_OSPEEDER_OSPEEDR0_Pos      GPIO_OSPEEDR_OSPEEDR0_Pos
8787 #define GPIO_OSPEEDER_OSPEEDR0_Msk      GPIO_OSPEEDR_OSPEEDR0_Msk
8788 #define GPIO_OSPEEDER_OSPEEDR0          GPIO_OSPEEDR_OSPEEDR0
8789 #define GPIO_OSPEEDER_OSPEEDR0_0        GPIO_OSPEEDR_OSPEEDR0_0
8790 #define GPIO_OSPEEDER_OSPEEDR0_1        GPIO_OSPEEDR_OSPEEDR0_1
8791 #define GPIO_OSPEEDER_OSPEEDR1_Pos      GPIO_OSPEEDR_OSPEEDR1_Pos
8792 #define GPIO_OSPEEDER_OSPEEDR1_Msk      GPIO_OSPEEDR_OSPEEDR1_Msk
8793 #define GPIO_OSPEEDER_OSPEEDR1          GPIO_OSPEEDR_OSPEEDR1
8794 #define GPIO_OSPEEDER_OSPEEDR1_0        GPIO_OSPEEDR_OSPEEDR1_0
8795 #define GPIO_OSPEEDER_OSPEEDR1_1        GPIO_OSPEEDR_OSPEEDR1_1
8796 #define GPIO_OSPEEDER_OSPEEDR2_Pos      GPIO_OSPEEDR_OSPEEDR2_Pos
8797 #define GPIO_OSPEEDER_OSPEEDR2_Msk      GPIO_OSPEEDR_OSPEEDR2_Msk
8798 #define GPIO_OSPEEDER_OSPEEDR2          GPIO_OSPEEDR_OSPEEDR2
8799 #define GPIO_OSPEEDER_OSPEEDR2_0        GPIO_OSPEEDR_OSPEEDR2_0
8800 #define GPIO_OSPEEDER_OSPEEDR2_1        GPIO_OSPEEDR_OSPEEDR2_1
8801 #define GPIO_OSPEEDER_OSPEEDR3_Pos      GPIO_OSPEEDR_OSPEEDR3_Pos
8802 #define GPIO_OSPEEDER_OSPEEDR3_Msk      GPIO_OSPEEDR_OSPEEDR3_Msk
8803 #define GPIO_OSPEEDER_OSPEEDR3          GPIO_OSPEEDR_OSPEEDR3
8804 #define GPIO_OSPEEDER_OSPEEDR3_0        GPIO_OSPEEDR_OSPEEDR3_0
8805 #define GPIO_OSPEEDER_OSPEEDR3_1        GPIO_OSPEEDR_OSPEEDR3_1
8806 #define GPIO_OSPEEDER_OSPEEDR4_Pos      GPIO_OSPEEDR_OSPEEDR4_Pos
8807 #define GPIO_OSPEEDER_OSPEEDR4_Msk      GPIO_OSPEEDR_OSPEEDR4_Msk
8808 #define GPIO_OSPEEDER_OSPEEDR4          GPIO_OSPEEDR_OSPEEDR4
8809 #define GPIO_OSPEEDER_OSPEEDR4_0        GPIO_OSPEEDR_OSPEEDR4_0
8810 #define GPIO_OSPEEDER_OSPEEDR4_1        GPIO_OSPEEDR_OSPEEDR4_1
8811 #define GPIO_OSPEEDER_OSPEEDR5_Pos      GPIO_OSPEEDR_OSPEEDR5_Pos
8812 #define GPIO_OSPEEDER_OSPEEDR5_Msk      GPIO_OSPEEDR_OSPEEDR5_Msk
8813 #define GPIO_OSPEEDER_OSPEEDR5          GPIO_OSPEEDR_OSPEEDR5
8814 #define GPIO_OSPEEDER_OSPEEDR5_0        GPIO_OSPEEDR_OSPEEDR5_0
8815 #define GPIO_OSPEEDER_OSPEEDR5_1        GPIO_OSPEEDR_OSPEEDR5_1
8816 #define GPIO_OSPEEDER_OSPEEDR6_Pos      GPIO_OSPEEDR_OSPEEDR6_Pos
8817 #define GPIO_OSPEEDER_OSPEEDR6_Msk      GPIO_OSPEEDR_OSPEEDR6_Msk
8818 #define GPIO_OSPEEDER_OSPEEDR6          GPIO_OSPEEDR_OSPEEDR6
8819 #define GPIO_OSPEEDER_OSPEEDR6_0        GPIO_OSPEEDR_OSPEEDR6_0
8820 #define GPIO_OSPEEDER_OSPEEDR6_1        GPIO_OSPEEDR_OSPEEDR6_1
8821 #define GPIO_OSPEEDER_OSPEEDR7_Pos      GPIO_OSPEEDR_OSPEEDR7_Pos
8822 #define GPIO_OSPEEDER_OSPEEDR7_Msk      GPIO_OSPEEDR_OSPEEDR7_Msk
8823 #define GPIO_OSPEEDER_OSPEEDR7          GPIO_OSPEEDR_OSPEEDR7
8824 #define GPIO_OSPEEDER_OSPEEDR7_0        GPIO_OSPEEDR_OSPEEDR7_0
8825 #define GPIO_OSPEEDER_OSPEEDR7_1        GPIO_OSPEEDR_OSPEEDR7_1
8826 #define GPIO_OSPEEDER_OSPEEDR8_Pos      GPIO_OSPEEDR_OSPEEDR8_Pos
8827 #define GPIO_OSPEEDER_OSPEEDR8_Msk      GPIO_OSPEEDR_OSPEEDR8_Msk
8828 #define GPIO_OSPEEDER_OSPEEDR8          GPIO_OSPEEDR_OSPEEDR8
8829 #define GPIO_OSPEEDER_OSPEEDR8_0        GPIO_OSPEEDR_OSPEEDR8_0
8830 #define GPIO_OSPEEDER_OSPEEDR8_1        GPIO_OSPEEDR_OSPEEDR8_1
8831 #define GPIO_OSPEEDER_OSPEEDR9_Pos      GPIO_OSPEEDR_OSPEEDR9_Pos
8832 #define GPIO_OSPEEDER_OSPEEDR9_Msk      GPIO_OSPEEDR_OSPEEDR9_Msk
8833 #define GPIO_OSPEEDER_OSPEEDR9          GPIO_OSPEEDR_OSPEEDR9
8834 #define GPIO_OSPEEDER_OSPEEDR9_0        GPIO_OSPEEDR_OSPEEDR9_0
8835 #define GPIO_OSPEEDER_OSPEEDR9_1        GPIO_OSPEEDR_OSPEEDR9_1
8836 #define GPIO_OSPEEDER_OSPEEDR10_Pos     GPIO_OSPEEDR_OSPEEDR10_Pos
8837 #define GPIO_OSPEEDER_OSPEEDR10_Msk     GPIO_OSPEEDR_OSPEEDR10_Msk
8838 #define GPIO_OSPEEDER_OSPEEDR10         GPIO_OSPEEDR_OSPEEDR10
8839 #define GPIO_OSPEEDER_OSPEEDR10_0       GPIO_OSPEEDR_OSPEEDR10_0
8840 #define GPIO_OSPEEDER_OSPEEDR10_1       GPIO_OSPEEDR_OSPEEDR10_1
8841 #define GPIO_OSPEEDER_OSPEEDR11_Pos     GPIO_OSPEEDR_OSPEEDR11_Pos
8842 #define GPIO_OSPEEDER_OSPEEDR11_Msk     GPIO_OSPEEDR_OSPEEDR11_Msk
8843 #define GPIO_OSPEEDER_OSPEEDR11         GPIO_OSPEEDR_OSPEEDR11
8844 #define GPIO_OSPEEDER_OSPEEDR11_0       GPIO_OSPEEDR_OSPEEDR11_0
8845 #define GPIO_OSPEEDER_OSPEEDR11_1       GPIO_OSPEEDR_OSPEEDR11_1
8846 #define GPIO_OSPEEDER_OSPEEDR12_Pos     GPIO_OSPEEDR_OSPEEDR12_Pos
8847 #define GPIO_OSPEEDER_OSPEEDR12_Msk     GPIO_OSPEEDR_OSPEEDR12_Msk
8848 #define GPIO_OSPEEDER_OSPEEDR12         GPIO_OSPEEDR_OSPEEDR12
8849 #define GPIO_OSPEEDER_OSPEEDR12_0       GPIO_OSPEEDR_OSPEEDR12_0
8850 #define GPIO_OSPEEDER_OSPEEDR12_1       GPIO_OSPEEDR_OSPEEDR12_1
8851 #define GPIO_OSPEEDER_OSPEEDR13_Pos     GPIO_OSPEEDR_OSPEEDR13_Pos
8852 #define GPIO_OSPEEDER_OSPEEDR13_Msk     GPIO_OSPEEDR_OSPEEDR13_Msk
8853 #define GPIO_OSPEEDER_OSPEEDR13         GPIO_OSPEEDR_OSPEEDR13
8854 #define GPIO_OSPEEDER_OSPEEDR13_0       GPIO_OSPEEDR_OSPEEDR13_0
8855 #define GPIO_OSPEEDER_OSPEEDR13_1       GPIO_OSPEEDR_OSPEEDR13_1
8856 #define GPIO_OSPEEDER_OSPEEDR14_Pos     GPIO_OSPEEDR_OSPEEDR14_Pos
8857 #define GPIO_OSPEEDER_OSPEEDR14_Msk     GPIO_OSPEEDR_OSPEEDR14_Msk
8858 #define GPIO_OSPEEDER_OSPEEDR14         GPIO_OSPEEDR_OSPEEDR14
8859 #define GPIO_OSPEEDER_OSPEEDR14_0       GPIO_OSPEEDR_OSPEEDR14_0
8860 #define GPIO_OSPEEDER_OSPEEDR14_1       GPIO_OSPEEDR_OSPEEDR14_1
8861 #define GPIO_OSPEEDER_OSPEEDR15_Pos     GPIO_OSPEEDR_OSPEEDR15_Pos
8862 #define GPIO_OSPEEDER_OSPEEDR15_Msk     GPIO_OSPEEDR_OSPEEDR15_Msk
8863 #define GPIO_OSPEEDER_OSPEEDR15         GPIO_OSPEEDR_OSPEEDR15
8864 #define GPIO_OSPEEDER_OSPEEDR15_0       GPIO_OSPEEDR_OSPEEDR15_0
8865 #define GPIO_OSPEEDER_OSPEEDR15_1       GPIO_OSPEEDR_OSPEEDR15_1
8866 
8867 /******************  Bits definition for GPIO_PUPDR register  *****************/
8868 #define GPIO_PUPDR_PUPDR0_Pos            (0U)
8869 #define GPIO_PUPDR_PUPDR0_Msk            (0x3UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000003 */
8870 #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPDR0_Msk
8871 #define GPIO_PUPDR_PUPDR0_0              (0x1UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000001 */
8872 #define GPIO_PUPDR_PUPDR0_1              (0x2UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000002 */
8873 #define GPIO_PUPDR_PUPDR1_Pos            (2U)
8874 #define GPIO_PUPDR_PUPDR1_Msk            (0x3UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x0000000C */
8875 #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPDR1_Msk
8876 #define GPIO_PUPDR_PUPDR1_0              (0x1UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000004 */
8877 #define GPIO_PUPDR_PUPDR1_1              (0x2UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000008 */
8878 #define GPIO_PUPDR_PUPDR2_Pos            (4U)
8879 #define GPIO_PUPDR_PUPDR2_Msk            (0x3UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000030 */
8880 #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPDR2_Msk
8881 #define GPIO_PUPDR_PUPDR2_0              (0x1UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000010 */
8882 #define GPIO_PUPDR_PUPDR2_1              (0x2UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000020 */
8883 #define GPIO_PUPDR_PUPDR3_Pos            (6U)
8884 #define GPIO_PUPDR_PUPDR3_Msk            (0x3UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x000000C0 */
8885 #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPDR3_Msk
8886 #define GPIO_PUPDR_PUPDR3_0              (0x1UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000040 */
8887 #define GPIO_PUPDR_PUPDR3_1              (0x2UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000080 */
8888 #define GPIO_PUPDR_PUPDR4_Pos            (8U)
8889 #define GPIO_PUPDR_PUPDR4_Msk            (0x3UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000300 */
8890 #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPDR4_Msk
8891 #define GPIO_PUPDR_PUPDR4_0              (0x1UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000100 */
8892 #define GPIO_PUPDR_PUPDR4_1              (0x2UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000200 */
8893 #define GPIO_PUPDR_PUPDR5_Pos            (10U)
8894 #define GPIO_PUPDR_PUPDR5_Msk            (0x3UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000C00 */
8895 #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPDR5_Msk
8896 #define GPIO_PUPDR_PUPDR5_0              (0x1UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000400 */
8897 #define GPIO_PUPDR_PUPDR5_1              (0x2UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000800 */
8898 #define GPIO_PUPDR_PUPDR6_Pos            (12U)
8899 #define GPIO_PUPDR_PUPDR6_Msk            (0x3UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00003000 */
8900 #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPDR6_Msk
8901 #define GPIO_PUPDR_PUPDR6_0              (0x1UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00001000 */
8902 #define GPIO_PUPDR_PUPDR6_1              (0x2UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00002000 */
8903 #define GPIO_PUPDR_PUPDR7_Pos            (14U)
8904 #define GPIO_PUPDR_PUPDR7_Msk            (0x3UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x0000C000 */
8905 #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPDR7_Msk
8906 #define GPIO_PUPDR_PUPDR7_0              (0x1UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00004000 */
8907 #define GPIO_PUPDR_PUPDR7_1              (0x2UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00008000 */
8908 #define GPIO_PUPDR_PUPDR8_Pos            (16U)
8909 #define GPIO_PUPDR_PUPDR8_Msk            (0x3UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00030000 */
8910 #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPDR8_Msk
8911 #define GPIO_PUPDR_PUPDR8_0              (0x1UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00010000 */
8912 #define GPIO_PUPDR_PUPDR8_1              (0x2UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00020000 */
8913 #define GPIO_PUPDR_PUPDR9_Pos            (18U)
8914 #define GPIO_PUPDR_PUPDR9_Msk            (0x3UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x000C0000 */
8915 #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPDR9_Msk
8916 #define GPIO_PUPDR_PUPDR9_0              (0x1UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00040000 */
8917 #define GPIO_PUPDR_PUPDR9_1              (0x2UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00080000 */
8918 #define GPIO_PUPDR_PUPDR10_Pos           (20U)
8919 #define GPIO_PUPDR_PUPDR10_Msk           (0x3UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00300000 */
8920 #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPDR10_Msk
8921 #define GPIO_PUPDR_PUPDR10_0             (0x1UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00100000 */
8922 #define GPIO_PUPDR_PUPDR10_1             (0x2UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00200000 */
8923 #define GPIO_PUPDR_PUPDR11_Pos           (22U)
8924 #define GPIO_PUPDR_PUPDR11_Msk           (0x3UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00C00000 */
8925 #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPDR11_Msk
8926 #define GPIO_PUPDR_PUPDR11_0             (0x1UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00400000 */
8927 #define GPIO_PUPDR_PUPDR11_1             (0x2UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00800000 */
8928 #define GPIO_PUPDR_PUPDR12_Pos           (24U)
8929 #define GPIO_PUPDR_PUPDR12_Msk           (0x3UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x03000000 */
8930 #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPDR12_Msk
8931 #define GPIO_PUPDR_PUPDR12_0             (0x1UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x01000000 */
8932 #define GPIO_PUPDR_PUPDR12_1             (0x2UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x02000000 */
8933 #define GPIO_PUPDR_PUPDR13_Pos           (26U)
8934 #define GPIO_PUPDR_PUPDR13_Msk           (0x3UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x0C000000 */
8935 #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPDR13_Msk
8936 #define GPIO_PUPDR_PUPDR13_0             (0x1UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x04000000 */
8937 #define GPIO_PUPDR_PUPDR13_1             (0x2UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x08000000 */
8938 #define GPIO_PUPDR_PUPDR14_Pos           (28U)
8939 #define GPIO_PUPDR_PUPDR14_Msk           (0x3UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x30000000 */
8940 #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPDR14_Msk
8941 #define GPIO_PUPDR_PUPDR14_0             (0x1UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x10000000 */
8942 #define GPIO_PUPDR_PUPDR14_1             (0x2UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x20000000 */
8943 #define GPIO_PUPDR_PUPDR15_Pos           (30U)
8944 #define GPIO_PUPDR_PUPDR15_Msk           (0x3UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0xC0000000 */
8945 #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPDR15_Msk
8946 #define GPIO_PUPDR_PUPDR15_0             (0x1UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x40000000 */
8947 #define GPIO_PUPDR_PUPDR15_1             (0x2UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x80000000 */
8948 
8949 /******************  Bits definition for GPIO_IDR register  *******************/
8950 #define GPIO_IDR_ID0_Pos                 (0U)
8951 #define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
8952 #define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk
8953 #define GPIO_IDR_ID1_Pos                 (1U)
8954 #define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
8955 #define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk
8956 #define GPIO_IDR_ID2_Pos                 (2U)
8957 #define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
8958 #define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk
8959 #define GPIO_IDR_ID3_Pos                 (3U)
8960 #define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
8961 #define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk
8962 #define GPIO_IDR_ID4_Pos                 (4U)
8963 #define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
8964 #define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk
8965 #define GPIO_IDR_ID5_Pos                 (5U)
8966 #define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
8967 #define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk
8968 #define GPIO_IDR_ID6_Pos                 (6U)
8969 #define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
8970 #define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk
8971 #define GPIO_IDR_ID7_Pos                 (7U)
8972 #define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
8973 #define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk
8974 #define GPIO_IDR_ID8_Pos                 (8U)
8975 #define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
8976 #define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk
8977 #define GPIO_IDR_ID9_Pos                 (9U)
8978 #define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
8979 #define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk
8980 #define GPIO_IDR_ID10_Pos                (10U)
8981 #define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
8982 #define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk
8983 #define GPIO_IDR_ID11_Pos                (11U)
8984 #define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
8985 #define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk
8986 #define GPIO_IDR_ID12_Pos                (12U)
8987 #define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
8988 #define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk
8989 #define GPIO_IDR_ID13_Pos                (13U)
8990 #define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
8991 #define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk
8992 #define GPIO_IDR_ID14_Pos                (14U)
8993 #define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
8994 #define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk
8995 #define GPIO_IDR_ID15_Pos                (15U)
8996 #define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
8997 #define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk
8998 
8999 /* Legacy defines */
9000 #define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
9001 #define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
9002 #define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
9003 #define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
9004 #define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
9005 #define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
9006 #define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
9007 #define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
9008 #define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
9009 #define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
9010 #define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
9011 #define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
9012 #define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
9013 #define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
9014 #define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
9015 #define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
9016 
9017 /******************  Bits definition for GPIO_ODR register  *******************/
9018 #define GPIO_ODR_OD0_Pos                 (0U)
9019 #define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
9020 #define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk
9021 #define GPIO_ODR_OD1_Pos                 (1U)
9022 #define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
9023 #define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk
9024 #define GPIO_ODR_OD2_Pos                 (2U)
9025 #define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
9026 #define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk
9027 #define GPIO_ODR_OD3_Pos                 (3U)
9028 #define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
9029 #define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk
9030 #define GPIO_ODR_OD4_Pos                 (4U)
9031 #define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
9032 #define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk
9033 #define GPIO_ODR_OD5_Pos                 (5U)
9034 #define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
9035 #define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk
9036 #define GPIO_ODR_OD6_Pos                 (6U)
9037 #define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
9038 #define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk
9039 #define GPIO_ODR_OD7_Pos                 (7U)
9040 #define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
9041 #define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk
9042 #define GPIO_ODR_OD8_Pos                 (8U)
9043 #define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
9044 #define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk
9045 #define GPIO_ODR_OD9_Pos                 (9U)
9046 #define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
9047 #define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk
9048 #define GPIO_ODR_OD10_Pos                (10U)
9049 #define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
9050 #define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk
9051 #define GPIO_ODR_OD11_Pos                (11U)
9052 #define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
9053 #define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk
9054 #define GPIO_ODR_OD12_Pos                (12U)
9055 #define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
9056 #define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk
9057 #define GPIO_ODR_OD13_Pos                (13U)
9058 #define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
9059 #define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk
9060 #define GPIO_ODR_OD14_Pos                (14U)
9061 #define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
9062 #define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk
9063 #define GPIO_ODR_OD15_Pos                (15U)
9064 #define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
9065 #define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk
9066 
9067 /* Legacy defines */
9068 #define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
9069 #define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
9070 #define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
9071 #define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
9072 #define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
9073 #define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
9074 #define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
9075 #define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
9076 #define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
9077 #define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
9078 #define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
9079 #define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
9080 #define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
9081 #define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
9082 #define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
9083 #define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
9084 
9085 /******************  Bits definition for GPIO_BSRR register  ******************/
9086 #define GPIO_BSRR_BS0_Pos                (0U)
9087 #define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
9088 #define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk
9089 #define GPIO_BSRR_BS1_Pos                (1U)
9090 #define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
9091 #define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk
9092 #define GPIO_BSRR_BS2_Pos                (2U)
9093 #define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
9094 #define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk
9095 #define GPIO_BSRR_BS3_Pos                (3U)
9096 #define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
9097 #define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk
9098 #define GPIO_BSRR_BS4_Pos                (4U)
9099 #define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
9100 #define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk
9101 #define GPIO_BSRR_BS5_Pos                (5U)
9102 #define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
9103 #define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk
9104 #define GPIO_BSRR_BS6_Pos                (6U)
9105 #define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
9106 #define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk
9107 #define GPIO_BSRR_BS7_Pos                (7U)
9108 #define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
9109 #define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk
9110 #define GPIO_BSRR_BS8_Pos                (8U)
9111 #define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
9112 #define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk
9113 #define GPIO_BSRR_BS9_Pos                (9U)
9114 #define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
9115 #define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk
9116 #define GPIO_BSRR_BS10_Pos               (10U)
9117 #define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
9118 #define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk
9119 #define GPIO_BSRR_BS11_Pos               (11U)
9120 #define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
9121 #define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk
9122 #define GPIO_BSRR_BS12_Pos               (12U)
9123 #define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
9124 #define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk
9125 #define GPIO_BSRR_BS13_Pos               (13U)
9126 #define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
9127 #define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk
9128 #define GPIO_BSRR_BS14_Pos               (14U)
9129 #define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
9130 #define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk
9131 #define GPIO_BSRR_BS15_Pos               (15U)
9132 #define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
9133 #define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk
9134 #define GPIO_BSRR_BR0_Pos                (16U)
9135 #define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
9136 #define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk
9137 #define GPIO_BSRR_BR1_Pos                (17U)
9138 #define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
9139 #define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk
9140 #define GPIO_BSRR_BR2_Pos                (18U)
9141 #define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
9142 #define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk
9143 #define GPIO_BSRR_BR3_Pos                (19U)
9144 #define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
9145 #define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk
9146 #define GPIO_BSRR_BR4_Pos                (20U)
9147 #define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
9148 #define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk
9149 #define GPIO_BSRR_BR5_Pos                (21U)
9150 #define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
9151 #define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk
9152 #define GPIO_BSRR_BR6_Pos                (22U)
9153 #define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
9154 #define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk
9155 #define GPIO_BSRR_BR7_Pos                (23U)
9156 #define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
9157 #define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk
9158 #define GPIO_BSRR_BR8_Pos                (24U)
9159 #define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
9160 #define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk
9161 #define GPIO_BSRR_BR9_Pos                (25U)
9162 #define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
9163 #define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk
9164 #define GPIO_BSRR_BR10_Pos               (26U)
9165 #define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
9166 #define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk
9167 #define GPIO_BSRR_BR11_Pos               (27U)
9168 #define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
9169 #define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk
9170 #define GPIO_BSRR_BR12_Pos               (28U)
9171 #define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
9172 #define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk
9173 #define GPIO_BSRR_BR13_Pos               (29U)
9174 #define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
9175 #define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk
9176 #define GPIO_BSRR_BR14_Pos               (30U)
9177 #define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
9178 #define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk
9179 #define GPIO_BSRR_BR15_Pos               (31U)
9180 #define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
9181 #define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk
9182 
9183 /* Legacy defines */
9184 #define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
9185 #define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
9186 #define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
9187 #define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
9188 #define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
9189 #define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
9190 #define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
9191 #define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
9192 #define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
9193 #define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
9194 #define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
9195 #define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
9196 #define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
9197 #define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
9198 #define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
9199 #define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
9200 #define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
9201 #define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
9202 #define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
9203 #define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
9204 #define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
9205 #define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
9206 #define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
9207 #define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
9208 #define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
9209 #define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
9210 #define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
9211 #define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
9212 #define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
9213 #define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
9214 #define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
9215 #define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
9216 
9217 /****************** Bit definition for GPIO_LCKR register *********************/
9218 #define GPIO_LCKR_LCK0_Pos               (0U)
9219 #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
9220 #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
9221 #define GPIO_LCKR_LCK1_Pos               (1U)
9222 #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
9223 #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
9224 #define GPIO_LCKR_LCK2_Pos               (2U)
9225 #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
9226 #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
9227 #define GPIO_LCKR_LCK3_Pos               (3U)
9228 #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
9229 #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
9230 #define GPIO_LCKR_LCK4_Pos               (4U)
9231 #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
9232 #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
9233 #define GPIO_LCKR_LCK5_Pos               (5U)
9234 #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
9235 #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
9236 #define GPIO_LCKR_LCK6_Pos               (6U)
9237 #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
9238 #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
9239 #define GPIO_LCKR_LCK7_Pos               (7U)
9240 #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
9241 #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
9242 #define GPIO_LCKR_LCK8_Pos               (8U)
9243 #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
9244 #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
9245 #define GPIO_LCKR_LCK9_Pos               (9U)
9246 #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
9247 #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
9248 #define GPIO_LCKR_LCK10_Pos              (10U)
9249 #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
9250 #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
9251 #define GPIO_LCKR_LCK11_Pos              (11U)
9252 #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
9253 #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
9254 #define GPIO_LCKR_LCK12_Pos              (12U)
9255 #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
9256 #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
9257 #define GPIO_LCKR_LCK13_Pos              (13U)
9258 #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
9259 #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
9260 #define GPIO_LCKR_LCK14_Pos              (14U)
9261 #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
9262 #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
9263 #define GPIO_LCKR_LCK15_Pos              (15U)
9264 #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
9265 #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
9266 #define GPIO_LCKR_LCKK_Pos               (16U)
9267 #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
9268 #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
9269 
9270 /****************** Bit definition for GPIO_AFRL register *********************/
9271 #define GPIO_AFRL_AFRL0_Pos              (0U)
9272 #define GPIO_AFRL_AFRL0_Msk              (0xFUL << GPIO_AFRL_AFRL0_Pos)         /*!< 0x0000000F */
9273 #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFRL0_Msk
9274 #define GPIO_AFRL_AFRL0_0                (0x1UL << GPIO_AFRL_AFRL0_Pos)         /*!< 0x00000001 */
9275 #define GPIO_AFRL_AFRL0_1                (0x2UL << GPIO_AFRL_AFRL0_Pos)         /*!< 0x00000002 */
9276 #define GPIO_AFRL_AFRL0_2                (0x4UL << GPIO_AFRL_AFRL0_Pos)         /*!< 0x00000004 */
9277 #define GPIO_AFRL_AFRL0_3                (0x8UL << GPIO_AFRL_AFRL0_Pos)         /*!< 0x00000008 */
9278 #define GPIO_AFRL_AFRL1_Pos              (4U)
9279 #define GPIO_AFRL_AFRL1_Msk              (0xFUL << GPIO_AFRL_AFRL1_Pos)         /*!< 0x000000F0 */
9280 #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFRL1_Msk
9281 #define GPIO_AFRL_AFRL1_0                (0x1UL << GPIO_AFRL_AFRL1_Pos)         /*!< 0x00000010 */
9282 #define GPIO_AFRL_AFRL1_1                (0x2UL << GPIO_AFRL_AFRL1_Pos)         /*!< 0x00000020 */
9283 #define GPIO_AFRL_AFRL1_2                (0x4UL << GPIO_AFRL_AFRL1_Pos)         /*!< 0x00000040 */
9284 #define GPIO_AFRL_AFRL1_3                (0x8UL << GPIO_AFRL_AFRL1_Pos)         /*!< 0x00000080 */
9285 #define GPIO_AFRL_AFRL2_Pos              (8U)
9286 #define GPIO_AFRL_AFRL2_Msk              (0xFUL << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000F00 */
9287 #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFRL2_Msk
9288 #define GPIO_AFRL_AFRL2_0                (0x1UL << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000100 */
9289 #define GPIO_AFRL_AFRL2_1                (0x2UL << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000200 */
9290 #define GPIO_AFRL_AFRL2_2                (0x4UL << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000400 */
9291 #define GPIO_AFRL_AFRL2_3                (0x8UL << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000800 */
9292 #define GPIO_AFRL_AFRL3_Pos              (12U)
9293 #define GPIO_AFRL_AFRL3_Msk              (0xFUL << GPIO_AFRL_AFRL3_Pos)         /*!< 0x0000F000 */
9294 #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFRL3_Msk
9295 #define GPIO_AFRL_AFRL3_0                (0x1UL << GPIO_AFRL_AFRL3_Pos)         /*!< 0x00001000 */
9296 #define GPIO_AFRL_AFRL3_1                (0x2UL << GPIO_AFRL_AFRL3_Pos)         /*!< 0x00002000 */
9297 #define GPIO_AFRL_AFRL3_2                (0x4UL << GPIO_AFRL_AFRL3_Pos)         /*!< 0x00004000 */
9298 #define GPIO_AFRL_AFRL3_3                (0x8UL << GPIO_AFRL_AFRL3_Pos)         /*!< 0x00008000 */
9299 #define GPIO_AFRL_AFRL4_Pos              (16U)
9300 #define GPIO_AFRL_AFRL4_Msk              (0xFUL << GPIO_AFRL_AFRL4_Pos)         /*!< 0x000F0000 */
9301 #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFRL4_Msk
9302 #define GPIO_AFRL_AFRL4_0                (0x1UL << GPIO_AFRL_AFRL4_Pos)         /*!< 0x00010000 */
9303 #define GPIO_AFRL_AFRL4_1                (0x2UL << GPIO_AFRL_AFRL4_Pos)         /*!< 0x00020000 */
9304 #define GPIO_AFRL_AFRL4_2                (0x4UL << GPIO_AFRL_AFRL4_Pos)         /*!< 0x00040000 */
9305 #define GPIO_AFRL_AFRL4_3                (0x8UL << GPIO_AFRL_AFRL4_Pos)         /*!< 0x00080000 */
9306 #define GPIO_AFRL_AFRL5_Pos              (20U)
9307 #define GPIO_AFRL_AFRL5_Msk              (0xFUL << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00F00000 */
9308 #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFRL5_Msk
9309 #define GPIO_AFRL_AFRL5_0                (0x1UL << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00100000 */
9310 #define GPIO_AFRL_AFRL5_1                (0x2UL << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00200000 */
9311 #define GPIO_AFRL_AFRL5_2                (0x4UL << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00400000 */
9312 #define GPIO_AFRL_AFRL5_3                (0x8UL << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00800000 */
9313 #define GPIO_AFRL_AFRL6_Pos              (24U)
9314 #define GPIO_AFRL_AFRL6_Msk              (0xFUL << GPIO_AFRL_AFRL6_Pos)         /*!< 0x0F000000 */
9315 #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFRL6_Msk
9316 #define GPIO_AFRL_AFRL6_0                (0x1UL << GPIO_AFRL_AFRL6_Pos)         /*!< 0x01000000 */
9317 #define GPIO_AFRL_AFRL6_1                (0x2UL << GPIO_AFRL_AFRL6_Pos)         /*!< 0x02000000 */
9318 #define GPIO_AFRL_AFRL6_2                (0x4UL << GPIO_AFRL_AFRL6_Pos)         /*!< 0x04000000 */
9319 #define GPIO_AFRL_AFRL6_3                (0x8UL << GPIO_AFRL_AFRL6_Pos)         /*!< 0x08000000 */
9320 #define GPIO_AFRL_AFRL7_Pos              (28U)
9321 #define GPIO_AFRL_AFRL7_Msk              (0xFUL << GPIO_AFRL_AFRL7_Pos)         /*!< 0xF0000000 */
9322 #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFRL7_Msk
9323 #define GPIO_AFRL_AFRL7_0                (0x1UL << GPIO_AFRL_AFRL7_Pos)         /*!< 0x10000000 */
9324 #define GPIO_AFRL_AFRL7_1                (0x2UL << GPIO_AFRL_AFRL7_Pos)         /*!< 0x20000000 */
9325 #define GPIO_AFRL_AFRL7_2                (0x4UL << GPIO_AFRL_AFRL7_Pos)         /*!< 0x40000000 */
9326 #define GPIO_AFRL_AFRL7_3                (0x8UL << GPIO_AFRL_AFRL7_Pos)         /*!< 0x80000000 */
9327 
9328 /****************** Bit definition for GPIO_AFRH register *********************/
9329 #define GPIO_AFRH_AFRH0_Pos              (0U)
9330 #define GPIO_AFRH_AFRH0_Msk              (0xFUL << GPIO_AFRH_AFRH0_Pos)         /*!< 0x0000000F */
9331 #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFRH0_Msk
9332 #define GPIO_AFRH_AFRH0_0                (0x1UL << GPIO_AFRH_AFRH0_Pos)         /*!< 0x00000001 */
9333 #define GPIO_AFRH_AFRH0_1                (0x2UL << GPIO_AFRH_AFRH0_Pos)         /*!< 0x00000002 */
9334 #define GPIO_AFRH_AFRH0_2                (0x4UL << GPIO_AFRH_AFRH0_Pos)         /*!< 0x00000004 */
9335 #define GPIO_AFRH_AFRH0_3                (0x8UL << GPIO_AFRH_AFRH0_Pos)         /*!< 0x00000008 */
9336 #define GPIO_AFRH_AFRH1_Pos              (4U)
9337 #define GPIO_AFRH_AFRH1_Msk              (0xFUL << GPIO_AFRH_AFRH1_Pos)         /*!< 0x000000F0 */
9338 #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFRH1_Msk
9339 #define GPIO_AFRH_AFRH1_0                (0x1UL << GPIO_AFRH_AFRH1_Pos)         /*!< 0x00000010 */
9340 #define GPIO_AFRH_AFRH1_1                (0x2UL << GPIO_AFRH_AFRH1_Pos)         /*!< 0x00000020 */
9341 #define GPIO_AFRH_AFRH1_2                (0x4UL << GPIO_AFRH_AFRH1_Pos)         /*!< 0x00000040 */
9342 #define GPIO_AFRH_AFRH1_3                (0x8UL << GPIO_AFRH_AFRH1_Pos)         /*!< 0x00000080 */
9343 #define GPIO_AFRH_AFRH2_Pos              (8U)
9344 #define GPIO_AFRH_AFRH2_Msk              (0xFUL << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000F00 */
9345 #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFRH2_Msk
9346 #define GPIO_AFRH_AFRH2_0                (0x1UL << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000100 */
9347 #define GPIO_AFRH_AFRH2_1                (0x2UL << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000200 */
9348 #define GPIO_AFRH_AFRH2_2                (0x4UL << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000400 */
9349 #define GPIO_AFRH_AFRH2_3                (0x8UL << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000800 */
9350 #define GPIO_AFRH_AFRH3_Pos              (12U)
9351 #define GPIO_AFRH_AFRH3_Msk              (0xFUL << GPIO_AFRH_AFRH3_Pos)         /*!< 0x0000F000 */
9352 #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFRH3_Msk
9353 #define GPIO_AFRH_AFRH3_0                (0x1UL << GPIO_AFRH_AFRH3_Pos)         /*!< 0x00001000 */
9354 #define GPIO_AFRH_AFRH3_1                (0x2UL << GPIO_AFRH_AFRH3_Pos)         /*!< 0x00002000 */
9355 #define GPIO_AFRH_AFRH3_2                (0x4UL << GPIO_AFRH_AFRH3_Pos)         /*!< 0x00004000 */
9356 #define GPIO_AFRH_AFRH3_3                (0x8UL << GPIO_AFRH_AFRH3_Pos)         /*!< 0x00008000 */
9357 #define GPIO_AFRH_AFRH4_Pos              (16U)
9358 #define GPIO_AFRH_AFRH4_Msk              (0xFUL << GPIO_AFRH_AFRH4_Pos)         /*!< 0x000F0000 */
9359 #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFRH4_Msk
9360 #define GPIO_AFRH_AFRH4_0                (0x1UL << GPIO_AFRH_AFRH4_Pos)         /*!< 0x00010000 */
9361 #define GPIO_AFRH_AFRH4_1                (0x2UL << GPIO_AFRH_AFRH4_Pos)         /*!< 0x00020000 */
9362 #define GPIO_AFRH_AFRH4_2                (0x4UL << GPIO_AFRH_AFRH4_Pos)         /*!< 0x00040000 */
9363 #define GPIO_AFRH_AFRH4_3                (0x8UL << GPIO_AFRH_AFRH4_Pos)         /*!< 0x00080000 */
9364 #define GPIO_AFRH_AFRH5_Pos              (20U)
9365 #define GPIO_AFRH_AFRH5_Msk              (0xFUL << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00F00000 */
9366 #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFRH5_Msk
9367 #define GPIO_AFRH_AFRH5_0                (0x1UL << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00100000 */
9368 #define GPIO_AFRH_AFRH5_1                (0x2UL << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00200000 */
9369 #define GPIO_AFRH_AFRH5_2                (0x4UL << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00400000 */
9370 #define GPIO_AFRH_AFRH5_3                (0x8UL << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00800000 */
9371 #define GPIO_AFRH_AFRH6_Pos              (24U)
9372 #define GPIO_AFRH_AFRH6_Msk              (0xFUL << GPIO_AFRH_AFRH6_Pos)         /*!< 0x0F000000 */
9373 #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFRH6_Msk
9374 #define GPIO_AFRH_AFRH6_0                (0x1UL << GPIO_AFRH_AFRH6_Pos)         /*!< 0x01000000 */
9375 #define GPIO_AFRH_AFRH6_1                (0x2UL << GPIO_AFRH_AFRH6_Pos)         /*!< 0x02000000 */
9376 #define GPIO_AFRH_AFRH6_2                (0x4UL << GPIO_AFRH_AFRH6_Pos)         /*!< 0x04000000 */
9377 #define GPIO_AFRH_AFRH6_3                (0x8UL << GPIO_AFRH_AFRH6_Pos)         /*!< 0x08000000 */
9378 #define GPIO_AFRH_AFRH7_Pos              (28U)
9379 #define GPIO_AFRH_AFRH7_Msk              (0xFUL << GPIO_AFRH_AFRH7_Pos)         /*!< 0xF0000000 */
9380 #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFRH7_Msk
9381 #define GPIO_AFRH_AFRH7_0                (0x1UL << GPIO_AFRH_AFRH7_Pos)         /*!< 0x10000000 */
9382 #define GPIO_AFRH_AFRH7_1                (0x2UL << GPIO_AFRH_AFRH7_Pos)         /*!< 0x20000000 */
9383 #define GPIO_AFRH_AFRH7_2                (0x4UL << GPIO_AFRH_AFRH7_Pos)         /*!< 0x40000000 */
9384 #define GPIO_AFRH_AFRH7_3                (0x8UL << GPIO_AFRH_AFRH7_Pos)         /*!< 0x80000000 */
9385 
9386 /******************************************************************************/
9387 /*                                                                            */
9388 /*                                    HASH                                    */
9389 /*                                                                            */
9390 /******************************************************************************/
9391 /******************  Bits definition for HASH_CR register  ********************/
9392 #define HASH_CR_INIT_Pos          (2U)
9393 #define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                   /*!< 0x00000004 */
9394 #define HASH_CR_INIT              HASH_CR_INIT_Msk
9395 #define HASH_CR_DMAE_Pos          (3U)
9396 #define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                   /*!< 0x00000008 */
9397 #define HASH_CR_DMAE              HASH_CR_DMAE_Msk
9398 #define HASH_CR_DATATYPE_Pos      (4U)
9399 #define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000030 */
9400 #define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk
9401 #define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */
9402 #define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */
9403 #define HASH_CR_MODE_Pos          (6U)
9404 #define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                   /*!< 0x00000040 */
9405 #define HASH_CR_MODE              HASH_CR_MODE_Msk
9406 #define HASH_CR_ALGO_Pos          (7U)
9407 #define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040080 */
9408 #define HASH_CR_ALGO              HASH_CR_ALGO_Msk
9409 #define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */
9410 #define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */
9411 #define HASH_CR_NBW_Pos           (8U)
9412 #define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                    /*!< 0x00000F00 */
9413 #define HASH_CR_NBW               HASH_CR_NBW_Msk
9414 #define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */
9415 #define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */
9416 #define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */
9417 #define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */
9418 #define HASH_CR_DINNE_Pos         (12U)
9419 #define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                  /*!< 0x00001000 */
9420 #define HASH_CR_DINNE             HASH_CR_DINNE_Msk
9421 #define HASH_CR_MDMAT_Pos         (13U)
9422 #define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                  /*!< 0x00002000 */
9423 #define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk
9424 #define HASH_CR_LKEY_Pos          (16U)
9425 #define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                   /*!< 0x00010000 */
9426 #define HASH_CR_LKEY              HASH_CR_LKEY_Msk
9427 
9428 /******************  Bits definition for HASH_STR register  *******************/
9429 #define HASH_STR_NBLW_Pos         (0U)
9430 #define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                 /*!< 0x0000001F */
9431 #define HASH_STR_NBLW             HASH_STR_NBLW_Msk
9432 #define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */
9433 #define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */
9434 #define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */
9435 #define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */
9436 #define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */
9437 #define HASH_STR_DCAL_Pos         (8U)
9438 #define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                  /*!< 0x00000100 */
9439 #define HASH_STR_DCAL             HASH_STR_DCAL_Msk
9440 
9441 /* legacy defines */
9442 #define HASH_STR_NBW                         HASH_STR_NBLW
9443 #define HASH_STR_NBW_0                       HASH_STR_NBLW_0
9444 #define HASH_STR_NBW_1                       HASH_STR_NBLW_1
9445 #define HASH_STR_NBW_2                       HASH_STR_NBLW_2
9446 #define HASH_STR_NBW_3                       HASH_STR_NBLW_3
9447 #define HASH_STR_NBW_4                       HASH_STR_NBLW_4
9448 
9449 /******************  Bits definition for HASH_IMR register  *******************/
9450 #define HASH_IMR_DINIE_Pos        (0U)
9451 #define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                 /*!< 0x00000001 */
9452 #define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk
9453 #define HASH_IMR_DCIE_Pos         (1U)
9454 #define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                  /*!< 0x00000002 */
9455 #define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk
9456 
9457 /* legacy defines */
9458 #define HASH_IMR_DINIM                       HASH_IMR_DINIE
9459 #define HASH_IMR_DCIM                        HASH_IMR_DCIE
9460 /******************  Bits definition for HASH_SR register  ********************/
9461 #define HASH_SR_DINIS_Pos         (0U)
9462 #define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                  /*!< 0x00000001 */
9463 #define HASH_SR_DINIS             HASH_SR_DINIS_Msk
9464 #define HASH_SR_DCIS_Pos          (1U)
9465 #define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                   /*!< 0x00000002 */
9466 #define HASH_SR_DCIS              HASH_SR_DCIS_Msk
9467 #define HASH_SR_DMAS_Pos          (2U)
9468 #define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                   /*!< 0x00000004 */
9469 #define HASH_SR_DMAS              HASH_SR_DMAS_Msk
9470 #define HASH_SR_BUSY_Pos          (3U)
9471 #define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                   /*!< 0x00000008 */
9472 #define HASH_SR_BUSY              HASH_SR_BUSY_Msk
9473 
9474 /******************************************************************************/
9475 /*                                                                            */
9476 /*                      Inter-integrated Circuit Interface (I2C)              */
9477 /*                                                                            */
9478 /******************************************************************************/
9479 /*******************  Bit definition for I2C_CR1 register  *******************/
9480 #define I2C_CR1_PE_Pos               (0U)
9481 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
9482 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
9483 #define I2C_CR1_TXIE_Pos             (1U)
9484 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
9485 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
9486 #define I2C_CR1_RXIE_Pos             (2U)
9487 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
9488 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
9489 #define I2C_CR1_ADDRIE_Pos           (3U)
9490 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
9491 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
9492 #define I2C_CR1_NACKIE_Pos           (4U)
9493 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
9494 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
9495 #define I2C_CR1_STOPIE_Pos           (5U)
9496 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
9497 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
9498 #define I2C_CR1_TCIE_Pos             (6U)
9499 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
9500 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
9501 #define I2C_CR1_ERRIE_Pos            (7U)
9502 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
9503 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
9504 #define I2C_CR1_DNF_Pos              (8U)
9505 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
9506 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
9507 #define I2C_CR1_ANFOFF_Pos           (12U)
9508 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
9509 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
9510 #define I2C_CR1_TXDMAEN_Pos          (14U)
9511 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
9512 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
9513 #define I2C_CR1_RXDMAEN_Pos          (15U)
9514 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
9515 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
9516 #define I2C_CR1_SBC_Pos              (16U)
9517 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
9518 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
9519 #define I2C_CR1_NOSTRETCH_Pos        (17U)
9520 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
9521 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
9522 #define I2C_CR1_GCEN_Pos             (19U)
9523 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
9524 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
9525 #define I2C_CR1_SMBHEN_Pos           (20U)
9526 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
9527 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
9528 #define I2C_CR1_SMBDEN_Pos           (21U)
9529 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
9530 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
9531 #define I2C_CR1_ALERTEN_Pos          (22U)
9532 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
9533 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
9534 #define I2C_CR1_PECEN_Pos            (23U)
9535 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
9536 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
9537 
9538 /* Legacy define */
9539 #define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */
9540 
9541 /******************  Bit definition for I2C_CR2 register  ********************/
9542 #define I2C_CR2_SADD_Pos             (0U)
9543 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
9544 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
9545 #define I2C_CR2_RD_WRN_Pos           (10U)
9546 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
9547 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
9548 #define I2C_CR2_ADD10_Pos            (11U)
9549 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
9550 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
9551 #define I2C_CR2_HEAD10R_Pos          (12U)
9552 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
9553 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
9554 #define I2C_CR2_START_Pos            (13U)
9555 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
9556 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
9557 #define I2C_CR2_STOP_Pos             (14U)
9558 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
9559 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
9560 #define I2C_CR2_NACK_Pos             (15U)
9561 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
9562 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
9563 #define I2C_CR2_NBYTES_Pos           (16U)
9564 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
9565 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
9566 #define I2C_CR2_RELOAD_Pos           (24U)
9567 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
9568 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
9569 #define I2C_CR2_AUTOEND_Pos          (25U)
9570 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
9571 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
9572 #define I2C_CR2_PECBYTE_Pos          (26U)
9573 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
9574 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
9575 
9576 /*******************  Bit definition for I2C_OAR1 register  ******************/
9577 #define I2C_OAR1_OA1_Pos             (0U)
9578 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
9579 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
9580 #define I2C_OAR1_OA1MODE_Pos         (10U)
9581 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
9582 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
9583 #define I2C_OAR1_OA1EN_Pos           (15U)
9584 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
9585 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
9586 
9587 /*******************  Bit definition for I2C_OAR2 register  ******************/
9588 #define I2C_OAR2_OA2_Pos             (1U)
9589 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
9590 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
9591 #define I2C_OAR2_OA2MSK_Pos          (8U)
9592 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
9593 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks     */
9594 #define I2C_OAR2_OA2NOMASK           0x00000000U                               /*!< No mask */
9595 #define I2C_OAR2_OA2MASK01_Pos       (8U)
9596 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
9597 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
9598 #define I2C_OAR2_OA2MASK02_Pos       (9U)
9599 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
9600 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
9601 #define I2C_OAR2_OA2MASK03_Pos       (8U)
9602 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
9603 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
9604 #define I2C_OAR2_OA2MASK04_Pos       (10U)
9605 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
9606 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
9607 #define I2C_OAR2_OA2MASK05_Pos       (8U)
9608 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
9609 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
9610 #define I2C_OAR2_OA2MASK06_Pos       (9U)
9611 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
9612 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
9613 #define I2C_OAR2_OA2MASK07_Pos       (8U)
9614 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
9615 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
9616 #define I2C_OAR2_OA2EN_Pos           (15U)
9617 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
9618 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable    */
9619 
9620 /*******************  Bit definition for I2C_TIMINGR register *******************/
9621 #define I2C_TIMINGR_SCLL_Pos         (0U)
9622 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
9623 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
9624 #define I2C_TIMINGR_SCLH_Pos         (8U)
9625 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
9626 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
9627 #define I2C_TIMINGR_SDADEL_Pos       (16U)
9628 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
9629 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
9630 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
9631 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
9632 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
9633 #define I2C_TIMINGR_PRESC_Pos        (28U)
9634 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
9635 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
9636 
9637 /******************* Bit definition for I2C_TIMEOUTR register *******************/
9638 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
9639 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
9640 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
9641 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
9642 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
9643 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
9644 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
9645 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
9646 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
9647 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
9648 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
9649 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
9650 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
9651 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
9652 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
9653 
9654 /******************  Bit definition for I2C_ISR register  *********************/
9655 #define I2C_ISR_TXE_Pos              (0U)
9656 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
9657 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
9658 #define I2C_ISR_TXIS_Pos             (1U)
9659 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
9660 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
9661 #define I2C_ISR_RXNE_Pos             (2U)
9662 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
9663 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
9664 #define I2C_ISR_ADDR_Pos             (3U)
9665 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
9666 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
9667 #define I2C_ISR_NACKF_Pos            (4U)
9668 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
9669 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
9670 #define I2C_ISR_STOPF_Pos            (5U)
9671 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
9672 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
9673 #define I2C_ISR_TC_Pos               (6U)
9674 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
9675 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
9676 #define I2C_ISR_TCR_Pos              (7U)
9677 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
9678 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
9679 #define I2C_ISR_BERR_Pos             (8U)
9680 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
9681 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
9682 #define I2C_ISR_ARLO_Pos             (9U)
9683 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
9684 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
9685 #define I2C_ISR_OVR_Pos              (10U)
9686 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
9687 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
9688 #define I2C_ISR_PECERR_Pos           (11U)
9689 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
9690 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
9691 #define I2C_ISR_TIMEOUT_Pos          (12U)
9692 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
9693 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
9694 #define I2C_ISR_ALERT_Pos            (13U)
9695 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
9696 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
9697 #define I2C_ISR_BUSY_Pos             (15U)
9698 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
9699 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
9700 #define I2C_ISR_DIR_Pos              (16U)
9701 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
9702 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
9703 #define I2C_ISR_ADDCODE_Pos          (17U)
9704 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
9705 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
9706 
9707 /******************  Bit definition for I2C_ICR register  *********************/
9708 #define I2C_ICR_ADDRCF_Pos           (3U)
9709 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
9710 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag      */
9711 #define I2C_ICR_NACKCF_Pos           (4U)
9712 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
9713 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag                 */
9714 #define I2C_ICR_STOPCF_Pos           (5U)
9715 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
9716 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag       */
9717 #define I2C_ICR_BERRCF_Pos           (8U)
9718 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
9719 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag            */
9720 #define I2C_ICR_ARLOCF_Pos           (9U)
9721 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
9722 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag     */
9723 #define I2C_ICR_OVRCF_Pos            (10U)
9724 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
9725 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag     */
9726 #define I2C_ICR_PECCF_Pos            (11U)
9727 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
9728 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag            */
9729 #define I2C_ICR_TIMOUTCF_Pos         (12U)
9730 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
9731 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag              */
9732 #define I2C_ICR_ALERTCF_Pos          (13U)
9733 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
9734 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag                */
9735 
9736 /******************  Bit definition for I2C_PECR register  *********************/
9737 #define I2C_PECR_PEC_Pos             (0U)
9738 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
9739 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register        */
9740 
9741 /******************  Bit definition for I2C_RXDR register  *********************/
9742 #define I2C_RXDR_RXDATA_Pos          (0U)
9743 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
9744 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data  */
9745 
9746 /******************  Bit definition for I2C_TXDR register  *********************/
9747 #define I2C_TXDR_TXDATA_Pos          (0U)
9748 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
9749 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
9750 
9751 
9752 /******************************************************************************/
9753 /*                                                                            */
9754 /*                           Independent WATCHDOG                             */
9755 /*                                                                            */
9756 /******************************************************************************/
9757 /*******************  Bit definition for IWDG_KR register  ********************/
9758 #define IWDG_KR_KEY_Pos      (0U)
9759 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
9760 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
9761 
9762 /*******************  Bit definition for IWDG_PR register  ********************/
9763 #define IWDG_PR_PR_Pos       (0U)
9764 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
9765 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
9766 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x01 */
9767 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x02 */
9768 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x04 */
9769 
9770 /*******************  Bit definition for IWDG_RLR register  *******************/
9771 #define IWDG_RLR_RL_Pos      (0U)
9772 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
9773 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
9774 
9775 /*******************  Bit definition for IWDG_SR register  ********************/
9776 #define IWDG_SR_PVU_Pos      (0U)
9777 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
9778 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
9779 #define IWDG_SR_RVU_Pos      (1U)
9780 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
9781 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
9782 #define IWDG_SR_WVU_Pos      (2U)
9783 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
9784 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
9785 
9786 /*******************  Bit definition for IWDG_KR register  ********************/
9787 #define IWDG_WINR_WIN_Pos    (0U)
9788 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
9789 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
9790 
9791 /******************************************************************************/
9792 /*                                                                            */
9793 /*                      LCD-TFT Display Controller (LTDC)                     */
9794 /*                                                                            */
9795 /******************************************************************************/
9796 
9797 /********************  Bit definition for LTDC_SSCR register  *****************/
9798 
9799 #define LTDC_SSCR_VSH_Pos            (0U)
9800 #define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)             /*!< 0x000007FF */
9801 #define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
9802 #define LTDC_SSCR_HSW_Pos            (16U)
9803 #define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)             /*!< 0x0FFF0000 */
9804 #define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
9805 
9806 /********************  Bit definition for LTDC_BPCR register  *****************/
9807 
9808 #define LTDC_BPCR_AVBP_Pos           (0U)
9809 #define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)            /*!< 0x000007FF */
9810 #define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
9811 #define LTDC_BPCR_AHBP_Pos           (16U)
9812 #define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)            /*!< 0x0FFF0000 */
9813 #define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
9814 
9815 /********************  Bit definition for LTDC_AWCR register  *****************/
9816 
9817 #define LTDC_AWCR_AAH_Pos            (0U)
9818 #define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)             /*!< 0x000007FF */
9819 #define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active height */
9820 #define LTDC_AWCR_AAW_Pos            (16U)
9821 #define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)             /*!< 0x0FFF0000 */
9822 #define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
9823 
9824 /********************  Bit definition for LTDC_TWCR register  *****************/
9825 
9826 #define LTDC_TWCR_TOTALH_Pos         (0U)
9827 #define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)          /*!< 0x000007FF */
9828 #define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */
9829 #define LTDC_TWCR_TOTALW_Pos         (16U)
9830 #define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)          /*!< 0x0FFF0000 */
9831 #define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
9832 
9833 /********************  Bit definition for LTDC_GCR register  ******************/
9834 
9835 #define LTDC_GCR_LTDCEN_Pos          (0U)
9836 #define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)             /*!< 0x00000001 */
9837 #define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
9838 #define LTDC_GCR_DBW_Pos             (4U)
9839 #define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)                /*!< 0x00000070 */
9840 #define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
9841 #define LTDC_GCR_DGW_Pos             (8U)
9842 #define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)                /*!< 0x00000700 */
9843 #define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
9844 #define LTDC_GCR_DRW_Pos             (12U)
9845 #define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)                /*!< 0x00007000 */
9846 #define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
9847 #define LTDC_GCR_DEN_Pos             (16U)
9848 #define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)                /*!< 0x00010000 */
9849 #define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
9850 #define LTDC_GCR_PCPOL_Pos           (28U)
9851 #define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)              /*!< 0x10000000 */
9852 #define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
9853 #define LTDC_GCR_DEPOL_Pos           (29U)
9854 #define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)              /*!< 0x20000000 */
9855 #define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
9856 #define LTDC_GCR_VSPOL_Pos           (30U)
9857 #define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)              /*!< 0x40000000 */
9858 #define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
9859 #define LTDC_GCR_HSPOL_Pos           (31U)
9860 #define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)              /*!< 0x80000000 */
9861 #define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
9862 
9863 /* Legacy define */
9864 #define LTDC_GCR_DTEN                       LTDC_GCR_DEN
9865 
9866 /********************  Bit definition for LTDC_SRCR register  *****************/
9867 
9868 #define LTDC_SRCR_IMR_Pos            (0U)
9869 #define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)               /*!< 0x00000001 */
9870 #define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
9871 #define LTDC_SRCR_VBR_Pos            (1U)
9872 #define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)               /*!< 0x00000002 */
9873 #define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
9874 
9875 /********************  Bit definition for LTDC_BCCR register  *****************/
9876 
9877 #define LTDC_BCCR_BCBLUE_Pos         (0U)
9878 #define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)           /*!< 0x000000FF */
9879 #define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
9880 #define LTDC_BCCR_BCGREEN_Pos        (8U)
9881 #define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)          /*!< 0x0000FF00 */
9882 #define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
9883 #define LTDC_BCCR_BCRED_Pos          (16U)
9884 #define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)            /*!< 0x00FF0000 */
9885 #define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
9886 
9887 /********************  Bit definition for LTDC_IER register  ******************/
9888 
9889 #define LTDC_IER_LIE_Pos             (0U)
9890 #define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)                /*!< 0x00000001 */
9891 #define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
9892 #define LTDC_IER_FUIE_Pos            (1U)
9893 #define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)               /*!< 0x00000002 */
9894 #define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
9895 #define LTDC_IER_TERRIE_Pos          (2U)
9896 #define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)             /*!< 0x00000004 */
9897 #define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
9898 #define LTDC_IER_RRIE_Pos            (3U)
9899 #define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)               /*!< 0x00000008 */
9900 #define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
9901 
9902 /********************  Bit definition for LTDC_ISR register  ******************/
9903 
9904 #define LTDC_ISR_LIF_Pos             (0U)
9905 #define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)                /*!< 0x00000001 */
9906 #define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
9907 #define LTDC_ISR_FUIF_Pos            (1U)
9908 #define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)               /*!< 0x00000002 */
9909 #define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
9910 #define LTDC_ISR_TERRIF_Pos          (2U)
9911 #define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)             /*!< 0x00000004 */
9912 #define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
9913 #define LTDC_ISR_RRIF_Pos            (3U)
9914 #define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)               /*!< 0x00000008 */
9915 #define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
9916 
9917 /********************  Bit definition for LTDC_ICR register  ******************/
9918 
9919 #define LTDC_ICR_CLIF_Pos            (0U)
9920 #define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)               /*!< 0x00000001 */
9921 #define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
9922 #define LTDC_ICR_CFUIF_Pos           (1U)
9923 #define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)              /*!< 0x00000002 */
9924 #define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
9925 #define LTDC_ICR_CTERRIF_Pos         (2U)
9926 #define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)            /*!< 0x00000004 */
9927 #define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
9928 #define LTDC_ICR_CRRIF_Pos           (3U)
9929 #define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)              /*!< 0x00000008 */
9930 #define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
9931 
9932 /********************  Bit definition for LTDC_LIPCR register  ****************/
9933 
9934 #define LTDC_LIPCR_LIPOS_Pos         (0U)
9935 #define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)          /*!< 0x000007FF */
9936 #define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
9937 
9938 /********************  Bit definition for LTDC_CPSR register  *****************/
9939 
9940 #define LTDC_CPSR_CYPOS_Pos          (0U)
9941 #define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)          /*!< 0x0000FFFF */
9942 #define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
9943 #define LTDC_CPSR_CXPOS_Pos          (16U)
9944 #define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)          /*!< 0xFFFF0000 */
9945 #define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
9946 
9947 /********************  Bit definition for LTDC_CDSR register  *****************/
9948 
9949 #define LTDC_CDSR_VDES_Pos           (0U)
9950 #define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)              /*!< 0x00000001 */
9951 #define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
9952 #define LTDC_CDSR_HDES_Pos           (1U)
9953 #define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)              /*!< 0x00000002 */
9954 #define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
9955 #define LTDC_CDSR_VSYNCS_Pos         (2U)
9956 #define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)            /*!< 0x00000004 */
9957 #define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
9958 #define LTDC_CDSR_HSYNCS_Pos         (3U)
9959 #define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)            /*!< 0x00000008 */
9960 #define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
9961 
9962 /********************  Bit definition for LTDC_LxCR register  *****************/
9963 
9964 #define LTDC_LxCR_LEN_Pos            (0U)
9965 #define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)               /*!< 0x00000001 */
9966 #define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
9967 #define LTDC_LxCR_COLKEN_Pos         (1U)
9968 #define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)            /*!< 0x00000002 */
9969 #define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
9970 #define LTDC_LxCR_CLUTEN_Pos         (4U)
9971 #define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)            /*!< 0x00000010 */
9972 #define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
9973 
9974 /********************  Bit definition for LTDC_LxWHPCR register  **************/
9975 
9976 #define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
9977 #define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)      /*!< 0x00000FFF */
9978 #define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
9979 #define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
9980 #define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0xFFFF0000 */
9981 #define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
9982 
9983 /********************  Bit definition for LTDC_LxWVPCR register  **************/
9984 
9985 #define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
9986 #define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)      /*!< 0x00000FFF */
9987 #define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
9988 #define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
9989 #define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0xFFFF0000 */
9990 #define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
9991 
9992 /********************  Bit definition for LTDC_LxCKCR register  ***************/
9993 
9994 #define LTDC_LxCKCR_CKBLUE_Pos       (0U)
9995 #define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)         /*!< 0x000000FF */
9996 #define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
9997 #define LTDC_LxCKCR_CKGREEN_Pos      (8U)
9998 #define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)        /*!< 0x0000FF00 */
9999 #define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
10000 #define LTDC_LxCKCR_CKRED_Pos        (16U)
10001 #define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)          /*!< 0x00FF0000 */
10002 #define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
10003 
10004 /********************  Bit definition for LTDC_LxPFCR register  ***************/
10005 
10006 #define LTDC_LxPFCR_PF_Pos           (0U)
10007 #define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)              /*!< 0x00000007 */
10008 #define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
10009 
10010 /********************  Bit definition for LTDC_LxCACR register  ***************/
10011 
10012 #define LTDC_LxCACR_CONSTA_Pos       (0U)
10013 #define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)         /*!< 0x000000FF */
10014 #define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
10015 
10016 /********************  Bit definition for LTDC_LxDCCR register  ***************/
10017 
10018 #define LTDC_LxDCCR_DCBLUE_Pos       (0U)
10019 #define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)         /*!< 0x000000FF */
10020 #define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
10021 #define LTDC_LxDCCR_DCGREEN_Pos      (8U)
10022 #define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)        /*!< 0x0000FF00 */
10023 #define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
10024 #define LTDC_LxDCCR_DCRED_Pos        (16U)
10025 #define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)          /*!< 0x00FF0000 */
10026 #define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
10027 #define LTDC_LxDCCR_DCALPHA_Pos      (24U)
10028 #define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)        /*!< 0xFF000000 */
10029 #define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
10030 
10031 /********************  Bit definition for LTDC_LxBFCR register  ***************/
10032 
10033 #define LTDC_LxBFCR_BF2_Pos          (0U)
10034 #define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)             /*!< 0x00000007 */
10035 #define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
10036 #define LTDC_LxBFCR_BF1_Pos          (8U)
10037 #define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)             /*!< 0x00000700 */
10038 #define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
10039 
10040 /********************  Bit definition for LTDC_LxCFBAR register  **************/
10041 
10042 #define LTDC_LxCFBAR_CFBADD_Pos      (0U)
10043 #define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)  /*!< 0xFFFFFFFF */
10044 #define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
10045 
10046 /********************  Bit definition for LTDC_LxCFBLR register  **************/
10047 
10048 #define LTDC_LxCFBLR_CFBLL_Pos       (0U)
10049 #define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)       /*!< 0x00001FFF */
10050 #define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
10051 #define LTDC_LxCFBLR_CFBP_Pos        (16U)
10052 #define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)        /*!< 0x1FFF0000 */
10053 #define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
10054 
10055 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
10056 
10057 #define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
10058 #define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)     /*!< 0x000007FF */
10059 #define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
10060 
10061 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
10062 
10063 #define LTDC_LxCLUTWR_BLUE_Pos       (0U)
10064 #define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)         /*!< 0x000000FF */
10065 #define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
10066 #define LTDC_LxCLUTWR_GREEN_Pos      (8U)
10067 #define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)        /*!< 0x0000FF00 */
10068 #define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
10069 #define LTDC_LxCLUTWR_RED_Pos        (16U)
10070 #define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)          /*!< 0x00FF0000 */
10071 #define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
10072 #define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
10073 #define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)      /*!< 0xFF000000 */
10074 #define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
10075 
10076 /******************************************************************************/
10077 /*                                                                            */
10078 /*                             Power Control                                  */
10079 /*                                                                            */
10080 /******************************************************************************/
10081 /********************  Bit definition for PWR_CR1 register  ********************/
10082 #define PWR_CR1_LPDS_Pos        (0U)
10083 #define PWR_CR1_LPDS_Msk        (0x1UL << PWR_CR1_LPDS_Pos)                     /*!< 0x00000001 */
10084 #define PWR_CR1_LPDS            PWR_CR1_LPDS_Msk                               /*!< Low-Power Deepsleep                 */
10085 #define PWR_CR1_PDDS_Pos        (1U)
10086 #define PWR_CR1_PDDS_Msk        (0x1UL << PWR_CR1_PDDS_Pos)                     /*!< 0x00000002 */
10087 #define PWR_CR1_PDDS            PWR_CR1_PDDS_Msk                               /*!< Power Down Deepsleep                */
10088 #define PWR_CR1_CSBF_Pos        (3U)
10089 #define PWR_CR1_CSBF_Msk        (0x1UL << PWR_CR1_CSBF_Pos)                     /*!< 0x00000008 */
10090 #define PWR_CR1_CSBF            PWR_CR1_CSBF_Msk                               /*!< Clear Standby Flag                  */
10091 #define PWR_CR1_PVDE_Pos        (4U)
10092 #define PWR_CR1_PVDE_Msk        (0x1UL << PWR_CR1_PVDE_Pos)                     /*!< 0x00000010 */
10093 #define PWR_CR1_PVDE            PWR_CR1_PVDE_Msk                               /*!< Power Voltage Detector Enable       */
10094 #define PWR_CR1_PLS_Pos         (5U)
10095 #define PWR_CR1_PLS_Msk         (0x7UL << PWR_CR1_PLS_Pos)                      /*!< 0x000000E0 */
10096 #define PWR_CR1_PLS             PWR_CR1_PLS_Msk                                /*!< PLS[2:0] bits (PVD Level Selection) */
10097 #define PWR_CR1_PLS_0           (0x1UL << PWR_CR1_PLS_Pos)                      /*!< 0x00000020 */
10098 #define PWR_CR1_PLS_1           (0x2UL << PWR_CR1_PLS_Pos)                      /*!< 0x00000040 */
10099 #define PWR_CR1_PLS_2           (0x4UL << PWR_CR1_PLS_Pos)                      /*!< 0x00000080 */
10100 
10101 /*!< PVD level configuration */
10102 #define PWR_CR1_PLS_LEV0        0x00000000U                                    /*!< PVD level 0 */
10103 #define PWR_CR1_PLS_LEV1_Pos    (5U)
10104 #define PWR_CR1_PLS_LEV1_Msk    (0x1UL << PWR_CR1_PLS_LEV1_Pos)                 /*!< 0x00000020 */
10105 #define PWR_CR1_PLS_LEV1        PWR_CR1_PLS_LEV1_Msk                           /*!< PVD level 1 */
10106 #define PWR_CR1_PLS_LEV2_Pos    (6U)
10107 #define PWR_CR1_PLS_LEV2_Msk    (0x1UL << PWR_CR1_PLS_LEV2_Pos)                 /*!< 0x00000040 */
10108 #define PWR_CR1_PLS_LEV2        PWR_CR1_PLS_LEV2_Msk                           /*!< PVD level 2 */
10109 #define PWR_CR1_PLS_LEV3_Pos    (5U)
10110 #define PWR_CR1_PLS_LEV3_Msk    (0x3UL << PWR_CR1_PLS_LEV3_Pos)                 /*!< 0x00000060 */
10111 #define PWR_CR1_PLS_LEV3        PWR_CR1_PLS_LEV3_Msk                           /*!< PVD level 3 */
10112 #define PWR_CR1_PLS_LEV4_Pos    (7U)
10113 #define PWR_CR1_PLS_LEV4_Msk    (0x1UL << PWR_CR1_PLS_LEV4_Pos)                 /*!< 0x00000080 */
10114 #define PWR_CR1_PLS_LEV4        PWR_CR1_PLS_LEV4_Msk                           /*!< PVD level 4 */
10115 #define PWR_CR1_PLS_LEV5_Pos    (5U)
10116 #define PWR_CR1_PLS_LEV5_Msk    (0x5UL << PWR_CR1_PLS_LEV5_Pos)                 /*!< 0x000000A0 */
10117 #define PWR_CR1_PLS_LEV5        PWR_CR1_PLS_LEV5_Msk                           /*!< PVD level 5 */
10118 #define PWR_CR1_PLS_LEV6_Pos    (6U)
10119 #define PWR_CR1_PLS_LEV6_Msk    (0x3UL << PWR_CR1_PLS_LEV6_Pos)                 /*!< 0x000000C0 */
10120 #define PWR_CR1_PLS_LEV6        PWR_CR1_PLS_LEV6_Msk                           /*!< PVD level 6 */
10121 #define PWR_CR1_PLS_LEV7_Pos    (5U)
10122 #define PWR_CR1_PLS_LEV7_Msk    (0x7UL << PWR_CR1_PLS_LEV7_Pos)                 /*!< 0x000000E0 */
10123 #define PWR_CR1_PLS_LEV7        PWR_CR1_PLS_LEV7_Msk                           /*!< PVD level 7 */
10124 #define PWR_CR1_DBP_Pos         (8U)
10125 #define PWR_CR1_DBP_Msk         (0x1UL << PWR_CR1_DBP_Pos)                      /*!< 0x00000100 */
10126 #define PWR_CR1_DBP             PWR_CR1_DBP_Msk                                /*!< Disable Backup Domain write protection                     */
10127 #define PWR_CR1_FPDS_Pos        (9U)
10128 #define PWR_CR1_FPDS_Msk        (0x1UL << PWR_CR1_FPDS_Pos)                     /*!< 0x00000200 */
10129 #define PWR_CR1_FPDS            PWR_CR1_FPDS_Msk                               /*!< Flash power down in Stop mode                              */
10130 #define PWR_CR1_LPUDS_Pos       (10U)
10131 #define PWR_CR1_LPUDS_Msk       (0x1UL << PWR_CR1_LPUDS_Pos)                    /*!< 0x00000400 */
10132 #define PWR_CR1_LPUDS           PWR_CR1_LPUDS_Msk                              /*!< Low-power regulator in deepsleep under-drive mode          */
10133 #define PWR_CR1_MRUDS_Pos       (11U)
10134 #define PWR_CR1_MRUDS_Msk       (0x1UL << PWR_CR1_MRUDS_Pos)                    /*!< 0x00000800 */
10135 #define PWR_CR1_MRUDS           PWR_CR1_MRUDS_Msk                              /*!< Main regulator in deepsleep under-drive mode               */
10136 #define PWR_CR1_ADCDC1_Pos      (13U)
10137 #define PWR_CR1_ADCDC1_Msk      (0x1UL << PWR_CR1_ADCDC1_Pos)                   /*!< 0x00002000 */
10138 #define PWR_CR1_ADCDC1          PWR_CR1_ADCDC1_Msk                             /*!< Refer to AN4073 on how to use this bit */
10139 #define PWR_CR1_VOS_Pos         (14U)
10140 #define PWR_CR1_VOS_Msk         (0x3UL << PWR_CR1_VOS_Pos)                      /*!< 0x0000C000 */
10141 #define PWR_CR1_VOS             PWR_CR1_VOS_Msk                                /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10142 #define PWR_CR1_VOS_0           (0x1UL << PWR_CR1_VOS_Pos)                      /*!< 0x00004000 */
10143 #define PWR_CR1_VOS_1           (0x2UL << PWR_CR1_VOS_Pos)                      /*!< 0x00008000 */
10144 #define PWR_CR1_ODEN_Pos        (16U)
10145 #define PWR_CR1_ODEN_Msk        (0x1UL << PWR_CR1_ODEN_Pos)                     /*!< 0x00010000 */
10146 #define PWR_CR1_ODEN            PWR_CR1_ODEN_Msk                               /*!< Over Drive enable                   */
10147 #define PWR_CR1_ODSWEN_Pos      (17U)
10148 #define PWR_CR1_ODSWEN_Msk      (0x1UL << PWR_CR1_ODSWEN_Pos)                   /*!< 0x00020000 */
10149 #define PWR_CR1_ODSWEN          PWR_CR1_ODSWEN_Msk                             /*!< Over Drive switch enabled           */
10150 #define PWR_CR1_UDEN_Pos        (18U)
10151 #define PWR_CR1_UDEN_Msk        (0x3UL << PWR_CR1_UDEN_Pos)                     /*!< 0x000C0000 */
10152 #define PWR_CR1_UDEN            PWR_CR1_UDEN_Msk                               /*!< Under Drive enable in stop mode     */
10153 #define PWR_CR1_UDEN_0          (0x1UL << PWR_CR1_UDEN_Pos)                     /*!< 0x00040000 */
10154 #define PWR_CR1_UDEN_1          (0x2UL << PWR_CR1_UDEN_Pos)                     /*!< 0x00080000 */
10155 
10156 /*******************  Bit definition for PWR_CSR1 register  ********************/
10157 #define PWR_CSR1_WUIF_Pos       (0U)
10158 #define PWR_CSR1_WUIF_Msk       (0x1UL << PWR_CSR1_WUIF_Pos)                    /*!< 0x00000001 */
10159 #define PWR_CSR1_WUIF           PWR_CSR1_WUIF_Msk                              /*!< Wake up internal Flag                            */
10160 #define PWR_CSR1_SBF_Pos        (1U)
10161 #define PWR_CSR1_SBF_Msk        (0x1UL << PWR_CSR1_SBF_Pos)                     /*!< 0x00000002 */
10162 #define PWR_CSR1_SBF            PWR_CSR1_SBF_Msk                               /*!< Standby Flag                                     */
10163 #define PWR_CSR1_PVDO_Pos       (2U)
10164 #define PWR_CSR1_PVDO_Msk       (0x1UL << PWR_CSR1_PVDO_Pos)                    /*!< 0x00000004 */
10165 #define PWR_CSR1_PVDO           PWR_CSR1_PVDO_Msk                              /*!< PVD Output                                       */
10166 #define PWR_CSR1_BRR_Pos        (3U)
10167 #define PWR_CSR1_BRR_Msk        (0x1UL << PWR_CSR1_BRR_Pos)                     /*!< 0x00000008 */
10168 #define PWR_CSR1_BRR            PWR_CSR1_BRR_Msk                               /*!< Backup regulator ready                           */
10169 #define PWR_CSR1_EIWUP_Pos      (8U)
10170 #define PWR_CSR1_EIWUP_Msk      (0x1UL << PWR_CSR1_EIWUP_Pos)                   /*!< 0x00000100 */
10171 #define PWR_CSR1_EIWUP          PWR_CSR1_EIWUP_Msk                             /*!< Enable internal wakeup                           */
10172 #define PWR_CSR1_BRE_Pos        (9U)
10173 #define PWR_CSR1_BRE_Msk        (0x1UL << PWR_CSR1_BRE_Pos)                     /*!< 0x00000200 */
10174 #define PWR_CSR1_BRE            PWR_CSR1_BRE_Msk                               /*!< Backup regulator enable                          */
10175 #define PWR_CSR1_VOSRDY_Pos     (14U)
10176 #define PWR_CSR1_VOSRDY_Msk     (0x1UL << PWR_CSR1_VOSRDY_Pos)                  /*!< 0x00004000 */
10177 #define PWR_CSR1_VOSRDY         PWR_CSR1_VOSRDY_Msk                            /*!< Regulator voltage scaling output selection ready */
10178 #define PWR_CSR1_ODRDY_Pos      (16U)
10179 #define PWR_CSR1_ODRDY_Msk      (0x1UL << PWR_CSR1_ODRDY_Pos)                   /*!< 0x00010000 */
10180 #define PWR_CSR1_ODRDY          PWR_CSR1_ODRDY_Msk                             /*!< Over Drive generator ready                       */
10181 #define PWR_CSR1_ODSWRDY_Pos    (17U)
10182 #define PWR_CSR1_ODSWRDY_Msk    (0x1UL << PWR_CSR1_ODSWRDY_Pos)                 /*!< 0x00020000 */
10183 #define PWR_CSR1_ODSWRDY        PWR_CSR1_ODSWRDY_Msk                           /*!< Over Drive Switch ready                          */
10184 #define PWR_CSR1_UDRDY_Pos      (18U)
10185 #define PWR_CSR1_UDRDY_Msk      (0x3UL << PWR_CSR1_UDRDY_Pos)                   /*!< 0x000C0000 */
10186 #define PWR_CSR1_UDRDY          PWR_CSR1_UDRDY_Msk                             /*!< Under Drive ready                                */
10187 
10188 /* Legacy define */
10189 #define  PWR_CSR1_UDSWRDY                     PWR_CSR1_UDRDY
10190 
10191 /********************  Bit definition for PWR_CR2 register  ********************/
10192 #define PWR_CR2_CWUPF1_Pos      (0U)
10193 #define PWR_CR2_CWUPF1_Msk      (0x1UL << PWR_CR2_CWUPF1_Pos)                   /*!< 0x00000001 */
10194 #define PWR_CR2_CWUPF1          PWR_CR2_CWUPF1_Msk                             /*!< Clear Wakeup Pin Flag for PA0      */
10195 #define PWR_CR2_CWUPF2_Pos      (1U)
10196 #define PWR_CR2_CWUPF2_Msk      (0x1UL << PWR_CR2_CWUPF2_Pos)                   /*!< 0x00000002 */
10197 #define PWR_CR2_CWUPF2          PWR_CR2_CWUPF2_Msk                             /*!< Clear Wakeup Pin Flag for PA2      */
10198 #define PWR_CR2_CWUPF3_Pos      (2U)
10199 #define PWR_CR2_CWUPF3_Msk      (0x1UL << PWR_CR2_CWUPF3_Pos)                   /*!< 0x00000004 */
10200 #define PWR_CR2_CWUPF3          PWR_CR2_CWUPF3_Msk                             /*!< Clear Wakeup Pin Flag for PC1      */
10201 #define PWR_CR2_CWUPF4_Pos      (3U)
10202 #define PWR_CR2_CWUPF4_Msk      (0x1UL << PWR_CR2_CWUPF4_Pos)                   /*!< 0x00000008 */
10203 #define PWR_CR2_CWUPF4          PWR_CR2_CWUPF4_Msk                             /*!< Clear Wakeup Pin Flag for PC13     */
10204 #define PWR_CR2_CWUPF5_Pos      (4U)
10205 #define PWR_CR2_CWUPF5_Msk      (0x1UL << PWR_CR2_CWUPF5_Pos)                   /*!< 0x00000010 */
10206 #define PWR_CR2_CWUPF5          PWR_CR2_CWUPF5_Msk                             /*!< Clear Wakeup Pin Flag for PI8      */
10207 #define PWR_CR2_CWUPF6_Pos      (5U)
10208 #define PWR_CR2_CWUPF6_Msk      (0x1UL << PWR_CR2_CWUPF6_Pos)                   /*!< 0x00000020 */
10209 #define PWR_CR2_CWUPF6          PWR_CR2_CWUPF6_Msk                             /*!< Clear Wakeup Pin Flag for PI11     */
10210 #define PWR_CR2_WUPP1_Pos       (8U)
10211 #define PWR_CR2_WUPP1_Msk       (0x1UL << PWR_CR2_WUPP1_Pos)                    /*!< 0x00000100 */
10212 #define PWR_CR2_WUPP1           PWR_CR2_WUPP1_Msk                              /*!< Wakeup Pin Polarity bit for PA0    */
10213 #define PWR_CR2_WUPP2_Pos       (9U)
10214 #define PWR_CR2_WUPP2_Msk       (0x1UL << PWR_CR2_WUPP2_Pos)                    /*!< 0x00000200 */
10215 #define PWR_CR2_WUPP2           PWR_CR2_WUPP2_Msk                              /*!< Wakeup Pin Polarity bit for PA2    */
10216 #define PWR_CR2_WUPP3_Pos       (10U)
10217 #define PWR_CR2_WUPP3_Msk       (0x1UL << PWR_CR2_WUPP3_Pos)                    /*!< 0x00000400 */
10218 #define PWR_CR2_WUPP3           PWR_CR2_WUPP3_Msk                              /*!< Wakeup Pin Polarity bit for PC1    */
10219 #define PWR_CR2_WUPP4_Pos       (11U)
10220 #define PWR_CR2_WUPP4_Msk       (0x1UL << PWR_CR2_WUPP4_Pos)                    /*!< 0x00000800 */
10221 #define PWR_CR2_WUPP4           PWR_CR2_WUPP4_Msk                              /*!< Wakeup Pin Polarity bit for PC13   */
10222 #define PWR_CR2_WUPP5_Pos       (12U)
10223 #define PWR_CR2_WUPP5_Msk       (0x1UL << PWR_CR2_WUPP5_Pos)                    /*!< 0x00001000 */
10224 #define PWR_CR2_WUPP5           PWR_CR2_WUPP5_Msk                              /*!< Wakeup Pin Polarity bit for PI8    */
10225 #define PWR_CR2_WUPP6_Pos       (13U)
10226 #define PWR_CR2_WUPP6_Msk       (0x1UL << PWR_CR2_WUPP6_Pos)                    /*!< 0x00002000 */
10227 #define PWR_CR2_WUPP6           PWR_CR2_WUPP6_Msk                              /*!< Wakeup Pin Polarity bit for PI11   */
10228 
10229 /*******************  Bit definition for PWR_CSR2 register  ********************/
10230 #define PWR_CSR2_WUPF1_Pos      (0U)
10231 #define PWR_CSR2_WUPF1_Msk      (0x1UL << PWR_CSR2_WUPF1_Pos)                   /*!< 0x00000001 */
10232 #define PWR_CSR2_WUPF1          PWR_CSR2_WUPF1_Msk                             /*!< Wakeup Pin Flag for PA0            */
10233 #define PWR_CSR2_WUPF2_Pos      (1U)
10234 #define PWR_CSR2_WUPF2_Msk      (0x1UL << PWR_CSR2_WUPF2_Pos)                   /*!< 0x00000002 */
10235 #define PWR_CSR2_WUPF2          PWR_CSR2_WUPF2_Msk                             /*!< Wakeup Pin Flag for PA2            */
10236 #define PWR_CSR2_WUPF3_Pos      (2U)
10237 #define PWR_CSR2_WUPF3_Msk      (0x1UL << PWR_CSR2_WUPF3_Pos)                   /*!< 0x00000004 */
10238 #define PWR_CSR2_WUPF3          PWR_CSR2_WUPF3_Msk                             /*!< Wakeup Pin Flag for PC1            */
10239 #define PWR_CSR2_WUPF4_Pos      (3U)
10240 #define PWR_CSR2_WUPF4_Msk      (0x1UL << PWR_CSR2_WUPF4_Pos)                   /*!< 0x00000008 */
10241 #define PWR_CSR2_WUPF4          PWR_CSR2_WUPF4_Msk                             /*!< Wakeup Pin Flag for PC13           */
10242 #define PWR_CSR2_WUPF5_Pos      (4U)
10243 #define PWR_CSR2_WUPF5_Msk      (0x1UL << PWR_CSR2_WUPF5_Pos)                   /*!< 0x00000010 */
10244 #define PWR_CSR2_WUPF5          PWR_CSR2_WUPF5_Msk                             /*!< Wakeup Pin Flag for PI8            */
10245 #define PWR_CSR2_WUPF6_Pos      (5U)
10246 #define PWR_CSR2_WUPF6_Msk      (0x1UL << PWR_CSR2_WUPF6_Pos)                   /*!< 0x00000020 */
10247 #define PWR_CSR2_WUPF6          PWR_CSR2_WUPF6_Msk                             /*!< Wakeup Pin Flag for PI11           */
10248 #define PWR_CSR2_EWUP1_Pos      (8U)
10249 #define PWR_CSR2_EWUP1_Msk      (0x1UL << PWR_CSR2_EWUP1_Pos)                   /*!< 0x00000100 */
10250 #define PWR_CSR2_EWUP1          PWR_CSR2_EWUP1_Msk                             /*!< Enable Wakeup Pin PA0              */
10251 #define PWR_CSR2_EWUP2_Pos      (9U)
10252 #define PWR_CSR2_EWUP2_Msk      (0x1UL << PWR_CSR2_EWUP2_Pos)                   /*!< 0x00000200 */
10253 #define PWR_CSR2_EWUP2          PWR_CSR2_EWUP2_Msk                             /*!< Enable Wakeup Pin PA2              */
10254 #define PWR_CSR2_EWUP3_Pos      (10U)
10255 #define PWR_CSR2_EWUP3_Msk      (0x1UL << PWR_CSR2_EWUP3_Pos)                   /*!< 0x00000400 */
10256 #define PWR_CSR2_EWUP3          PWR_CSR2_EWUP3_Msk                             /*!< Enable Wakeup Pin PC1              */
10257 #define PWR_CSR2_EWUP4_Pos      (11U)
10258 #define PWR_CSR2_EWUP4_Msk      (0x1UL << PWR_CSR2_EWUP4_Pos)                   /*!< 0x00000800 */
10259 #define PWR_CSR2_EWUP4          PWR_CSR2_EWUP4_Msk                             /*!< Enable Wakeup Pin PC13             */
10260 #define PWR_CSR2_EWUP5_Pos      (12U)
10261 #define PWR_CSR2_EWUP5_Msk      (0x1UL << PWR_CSR2_EWUP5_Pos)                   /*!< 0x00001000 */
10262 #define PWR_CSR2_EWUP5          PWR_CSR2_EWUP5_Msk                             /*!< Enable Wakeup Pin PI8              */
10263 #define PWR_CSR2_EWUP6_Pos      (13U)
10264 #define PWR_CSR2_EWUP6_Msk      (0x1UL << PWR_CSR2_EWUP6_Pos)                   /*!< 0x00002000 */
10265 #define PWR_CSR2_EWUP6          PWR_CSR2_EWUP6_Msk                             /*!< Enable Wakeup Pin PI11             */
10266 
10267 /******************************************************************************/
10268 /*                                                                            */
10269 /*                                    QUADSPI                                 */
10270 /*                                                                            */
10271 /******************************************************************************/
10272 /* QUADSPI IP version */
10273 #define QSPI1_V1_0
10274 /*****************  Bit definition for QUADSPI_CR register  *******************/
10275 #define QUADSPI_CR_EN_Pos                (0U)
10276 #define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */
10277 #define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                            */
10278 #define QUADSPI_CR_ABORT_Pos             (1U)
10279 #define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */
10280 #define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                     */
10281 #define QUADSPI_CR_DMAEN_Pos             (2U)
10282 #define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */
10283 #define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                        */
10284 #define QUADSPI_CR_TCEN_Pos              (3U)
10285 #define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */
10286 #define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable            */
10287 #define QUADSPI_CR_SSHIFT_Pos            (4U)
10288 #define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */
10289 #define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< Sample Shift                      */
10290 #define QUADSPI_CR_DFM_Pos               (6U)
10291 #define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */
10292 #define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                   */
10293 #define QUADSPI_CR_FSEL_Pos              (7U)
10294 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */
10295 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                      */
10296 #define QUADSPI_CR_FTHRES_Pos            (8U)
10297 #define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
10298 #define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level            */
10299 #define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
10300 #define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
10301 #define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
10302 #define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
10303 #define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */
10304 #define QUADSPI_CR_TEIE_Pos              (16U)
10305 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */
10306 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */
10307 #define QUADSPI_CR_TCIE_Pos              (17U)
10308 #define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */
10309 #define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
10310 #define QUADSPI_CR_FTIE_Pos              (18U)
10311 #define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */
10312 #define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */
10313 #define QUADSPI_CR_SMIE_Pos              (19U)
10314 #define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */
10315 #define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */
10316 #define QUADSPI_CR_TOIE_Pos              (20U)
10317 #define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */
10318 #define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */
10319 #define QUADSPI_CR_APMS_Pos              (22U)
10320 #define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */
10321 #define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */
10322 #define QUADSPI_CR_PMM_Pos               (23U)
10323 #define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */
10324 #define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */
10325 #define QUADSPI_CR_PRESCALER_Pos         (24U)
10326 #define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */
10327 #define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */
10328 #define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */
10329 #define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */
10330 #define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */
10331 #define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */
10332 #define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */
10333 #define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */
10334 #define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */
10335 #define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */
10336 
10337 /*****************  Bit definition for QUADSPI_DCR register  ******************/
10338 #define QUADSPI_DCR_CKMODE_Pos           (0U)
10339 #define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */
10340 #define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */
10341 #define QUADSPI_DCR_CSHT_Pos             (8U)
10342 #define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */
10343 #define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
10344 #define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */
10345 #define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */
10346 #define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */
10347 #define QUADSPI_DCR_FSIZE_Pos            (16U)
10348 #define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */
10349 #define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */
10350 #define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */
10351 #define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */
10352 #define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */
10353 #define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */
10354 #define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */
10355 
10356 /******************  Bit definition for QUADSPI_SR register  *******************/
10357 #define QUADSPI_SR_TEF_Pos               (0U)
10358 #define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */
10359 #define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */
10360 #define QUADSPI_SR_TCF_Pos               (1U)
10361 #define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */
10362 #define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
10363 #define QUADSPI_SR_FTF_Pos               (2U)
10364 #define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */
10365 #define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */
10366 #define QUADSPI_SR_SMF_Pos               (3U)
10367 #define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */
10368 #define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */
10369 #define QUADSPI_SR_TOF_Pos               (4U)
10370 #define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */
10371 #define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */
10372 #define QUADSPI_SR_BUSY_Pos              (5U)
10373 #define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */
10374 #define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */
10375 #define QUADSPI_SR_FLEVEL_Pos            (8U)
10376 #define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */
10377 #define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */
10378 #define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */
10379 #define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */
10380 #define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */
10381 #define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */
10382 #define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */
10383 #define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */
10384 
10385 /******************  Bit definition for QUADSPI_FCR register  ******************/
10386 #define QUADSPI_FCR_CTEF_Pos             (0U)
10387 #define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */
10388 #define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */
10389 #define QUADSPI_FCR_CTCF_Pos             (1U)
10390 #define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */
10391 #define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
10392 #define QUADSPI_FCR_CSMF_Pos             (3U)
10393 #define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */
10394 #define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */
10395 #define QUADSPI_FCR_CTOF_Pos             (4U)
10396 #define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */
10397 #define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */
10398 
10399 /******************  Bit definition for QUADSPI_DLR register  ******************/
10400 #define QUADSPI_DLR_DL_Pos               (0U)
10401 #define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */
10402 #define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
10403 
10404 /******************  Bit definition for QUADSPI_CCR register  ******************/
10405 #define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
10406 #define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
10407 #define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction    */
10408 #define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
10409 #define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
10410 #define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
10411 #define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
10412 #define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
10413 #define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
10414 #define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
10415 #define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
10416 #define QUADSPI_CCR_IMODE_Pos            (8U)
10417 #define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */
10418 #define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode      */
10419 #define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */
10420 #define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */
10421 #define QUADSPI_CCR_ADMODE_Pos           (10U)
10422 #define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */
10423 #define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode         */
10424 #define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */
10425 #define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */
10426 #define QUADSPI_CCR_ADSIZE_Pos           (12U)
10427 #define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */
10428 #define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size         */
10429 #define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */
10430 #define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */
10431 #define QUADSPI_CCR_ABMODE_Pos           (14U)
10432 #define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */
10433 #define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode */
10434 #define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */
10435 #define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */
10436 #define QUADSPI_CCR_ABSIZE_Pos           (16U)
10437 #define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */
10438 #define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode     */
10439 #define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */
10440 #define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */
10441 #define QUADSPI_CCR_DCYC_Pos             (18U)
10442 #define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */
10443 #define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles           */
10444 #define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */
10445 #define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */
10446 #define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */
10447 #define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */
10448 #define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */
10449 #define QUADSPI_CCR_DMODE_Pos            (24U)
10450 #define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */
10451 #define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode              */
10452 #define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */
10453 #define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */
10454 #define QUADSPI_CCR_FMODE_Pos            (26U)
10455 #define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */
10456 #define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode        */
10457 #define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */
10458 #define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */
10459 #define QUADSPI_CCR_SIOO_Pos             (28U)
10460 #define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */
10461 #define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */
10462 #define QUADSPI_CCR_DHHC_Pos             (30U)
10463 #define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */
10464 #define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */
10465 #define QUADSPI_CCR_DDRM_Pos             (31U)
10466 #define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */
10467 #define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */
10468 /******************  Bit definition for QUADSPI_AR register  *******************/
10469 #define QUADSPI_AR_ADDRESS_Pos           (0U)
10470 #define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
10471 #define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */
10472 
10473 /******************  Bit definition for QUADSPI_ABR register  ******************/
10474 #define QUADSPI_ABR_ALTERNATE_Pos        (0U)
10475 #define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
10476 #define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */
10477 
10478 /******************  Bit definition for QUADSPI_DR register  *******************/
10479 #define QUADSPI_DR_DATA_Pos              (0U)
10480 #define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */
10481 #define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */
10482 
10483 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
10484 #define QUADSPI_PSMKR_MASK_Pos           (0U)
10485 #define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
10486 #define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */
10487 
10488 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
10489 #define QUADSPI_PSMAR_MATCH_Pos          (0U)
10490 #define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
10491 #define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */
10492 
10493 /******************  Bit definition for QUADSPI_PIR register  *****************/
10494 #define QUADSPI_PIR_INTERVAL_Pos         (0U)
10495 #define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
10496 #define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */
10497 
10498 /******************  Bit definition for QUADSPI_LPTR register  *****************/
10499 #define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
10500 #define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
10501 #define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */
10502 
10503 /******************************************************************************/
10504 /*                                                                            */
10505 /*                         Reset and Clock Control            */
10506 /*                                                                            */
10507 /******************************************************************************/
10508 /********************  Bit definition for RCC_CR register  ********************/
10509 #define RCC_CR_HSION_Pos                   (0U)
10510 #define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
10511 #define RCC_CR_HSION                       RCC_CR_HSION_Msk
10512 #define RCC_CR_HSIRDY_Pos                  (1U)
10513 #define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
10514 #define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk
10515 #define RCC_CR_HSITRIM_Pos                 (3U)
10516 #define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
10517 #define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk
10518 #define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
10519 #define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
10520 #define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
10521 #define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
10522 #define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
10523 #define RCC_CR_HSICAL_Pos                  (8U)
10524 #define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
10525 #define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk
10526 #define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
10527 #define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
10528 #define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
10529 #define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
10530 #define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
10531 #define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
10532 #define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
10533 #define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
10534 #define RCC_CR_HSEON_Pos                   (16U)
10535 #define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
10536 #define RCC_CR_HSEON                       RCC_CR_HSEON_Msk
10537 #define RCC_CR_HSERDY_Pos                  (17U)
10538 #define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
10539 #define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk
10540 #define RCC_CR_HSEBYP_Pos                  (18U)
10541 #define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
10542 #define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk
10543 #define RCC_CR_CSSON_Pos                   (19U)
10544 #define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
10545 #define RCC_CR_CSSON                       RCC_CR_CSSON_Msk
10546 #define RCC_CR_PLLON_Pos                   (24U)
10547 #define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
10548 #define RCC_CR_PLLON                       RCC_CR_PLLON_Msk
10549 #define RCC_CR_PLLRDY_Pos                  (25U)
10550 #define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
10551 #define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk
10552 #define RCC_CR_PLLI2SON_Pos                (26U)
10553 #define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
10554 #define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk
10555 #define RCC_CR_PLLI2SRDY_Pos               (27U)
10556 #define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
10557 #define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk
10558 #define RCC_CR_PLLSAION_Pos                (28U)
10559 #define RCC_CR_PLLSAION_Msk                (0x1UL << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */
10560 #define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk
10561 #define RCC_CR_PLLSAIRDY_Pos               (29U)
10562 #define RCC_CR_PLLSAIRDY_Msk               (0x1UL << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */
10563 #define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk
10564 
10565 /********************  Bit definition for RCC_PLLCFGR register  ***************/
10566 #define RCC_PLLCFGR_PLLM_Pos               (0U)
10567 #define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
10568 #define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk
10569 #define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
10570 #define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
10571 #define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
10572 #define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
10573 #define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
10574 #define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
10575 #define RCC_PLLCFGR_PLLN_Pos               (6U)
10576 #define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
10577 #define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk
10578 #define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
10579 #define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
10580 #define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
10581 #define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
10582 #define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
10583 #define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
10584 #define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
10585 #define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
10586 #define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
10587 #define RCC_PLLCFGR_PLLP_Pos               (16U)
10588 #define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
10589 #define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk
10590 #define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
10591 #define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
10592 #define RCC_PLLCFGR_PLLSRC_Pos             (22U)
10593 #define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
10594 #define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk
10595 #define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)
10596 #define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
10597 #define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk
10598 #define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U
10599 #define RCC_PLLCFGR_PLLQ_Pos               (24U)
10600 #define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
10601 #define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk
10602 #define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
10603 #define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
10604 #define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
10605 #define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
10606 
10607 
10608 /********************  Bit definition for RCC_CFGR register  ******************/
10609 /*!< SW configuration */
10610 #define RCC_CFGR_SW_Pos                    (0U)
10611 #define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
10612 #define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
10613 #define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
10614 #define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
10615 #define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
10616 #define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
10617 #define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
10618 
10619 /*!< SWS configuration */
10620 #define RCC_CFGR_SWS_Pos                   (2U)
10621 #define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
10622 #define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
10623 #define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
10624 #define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
10625 #define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock */
10626 #define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock */
10627 #define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock */
10628 
10629 /*!< HPRE configuration */
10630 #define RCC_CFGR_HPRE_Pos                  (4U)
10631 #define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
10632 #define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
10633 #define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
10634 #define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
10635 #define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
10636 #define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
10637 
10638 #define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided */
10639 #define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2 */
10640 #define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4 */
10641 #define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8 */
10642 #define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16 */
10643 #define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64 */
10644 #define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
10645 #define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
10646 #define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
10647 
10648 /*!< PPRE1 configuration */
10649 #define RCC_CFGR_PPRE1_Pos                 (10U)
10650 #define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
10651 #define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
10652 #define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
10653 #define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
10654 #define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
10655 
10656 #define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided */
10657 #define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2 */
10658 #define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4 */
10659 #define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8 */
10660 #define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
10661 
10662 /*!< PPRE2 configuration */
10663 #define RCC_CFGR_PPRE2_Pos                 (13U)
10664 #define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
10665 #define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
10666 #define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
10667 #define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
10668 #define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
10669 
10670 #define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided */
10671 #define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2 */
10672 #define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4 */
10673 #define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8 */
10674 #define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
10675 
10676 /*!< RTCPRE configuration */
10677 #define RCC_CFGR_RTCPRE_Pos                (16U)
10678 #define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
10679 #define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk
10680 #define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
10681 #define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
10682 #define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
10683 #define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
10684 #define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
10685 
10686 /*!< MCO1 configuration */
10687 #define RCC_CFGR_MCO1_Pos                  (21U)
10688 #define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
10689 #define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk
10690 #define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
10691 #define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
10692 
10693 #define RCC_CFGR_I2SSRC_Pos                (23U)
10694 #define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
10695 #define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk
10696 
10697 #define RCC_CFGR_MCO1PRE_Pos               (24U)
10698 #define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
10699 #define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk
10700 #define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
10701 #define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
10702 #define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
10703 
10704 #define RCC_CFGR_MCO2PRE_Pos               (27U)
10705 #define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
10706 #define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk
10707 #define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
10708 #define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
10709 #define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
10710 
10711 #define RCC_CFGR_MCO2_Pos                  (30U)
10712 #define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
10713 #define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk
10714 #define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
10715 #define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
10716 
10717 /********************  Bit definition for RCC_CIR register  *******************/
10718 #define RCC_CIR_LSIRDYF_Pos                (0U)
10719 #define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
10720 #define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk
10721 #define RCC_CIR_LSERDYF_Pos                (1U)
10722 #define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
10723 #define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk
10724 #define RCC_CIR_HSIRDYF_Pos                (2U)
10725 #define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
10726 #define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk
10727 #define RCC_CIR_HSERDYF_Pos                (3U)
10728 #define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
10729 #define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk
10730 #define RCC_CIR_PLLRDYF_Pos                (4U)
10731 #define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
10732 #define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk
10733 #define RCC_CIR_PLLI2SRDYF_Pos             (5U)
10734 #define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
10735 #define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk
10736 #define RCC_CIR_PLLSAIRDYF_Pos             (6U)
10737 #define RCC_CIR_PLLSAIRDYF_Msk             (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */
10738 #define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk
10739 #define RCC_CIR_CSSF_Pos                   (7U)
10740 #define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
10741 #define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk
10742 #define RCC_CIR_LSIRDYIE_Pos               (8U)
10743 #define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
10744 #define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk
10745 #define RCC_CIR_LSERDYIE_Pos               (9U)
10746 #define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
10747 #define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk
10748 #define RCC_CIR_HSIRDYIE_Pos               (10U)
10749 #define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
10750 #define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk
10751 #define RCC_CIR_HSERDYIE_Pos               (11U)
10752 #define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
10753 #define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk
10754 #define RCC_CIR_PLLRDYIE_Pos               (12U)
10755 #define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
10756 #define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk
10757 #define RCC_CIR_PLLI2SRDYIE_Pos            (13U)
10758 #define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
10759 #define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk
10760 #define RCC_CIR_PLLSAIRDYIE_Pos            (14U)
10761 #define RCC_CIR_PLLSAIRDYIE_Msk            (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */
10762 #define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk
10763 #define RCC_CIR_LSIRDYC_Pos                (16U)
10764 #define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
10765 #define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk
10766 #define RCC_CIR_LSERDYC_Pos                (17U)
10767 #define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
10768 #define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk
10769 #define RCC_CIR_HSIRDYC_Pos                (18U)
10770 #define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
10771 #define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk
10772 #define RCC_CIR_HSERDYC_Pos                (19U)
10773 #define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
10774 #define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk
10775 #define RCC_CIR_PLLRDYC_Pos                (20U)
10776 #define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
10777 #define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk
10778 #define RCC_CIR_PLLI2SRDYC_Pos             (21U)
10779 #define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
10780 #define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk
10781 #define RCC_CIR_PLLSAIRDYC_Pos             (22U)
10782 #define RCC_CIR_PLLSAIRDYC_Msk             (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */
10783 #define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk
10784 #define RCC_CIR_CSSC_Pos                   (23U)
10785 #define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
10786 #define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk
10787 
10788 /********************  Bit definition for RCC_AHB1RSTR register  **************/
10789 #define RCC_AHB1RSTR_GPIOARST_Pos          (0U)
10790 #define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
10791 #define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk
10792 #define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)
10793 #define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
10794 #define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk
10795 #define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)
10796 #define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
10797 #define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk
10798 #define RCC_AHB1RSTR_GPIODRST_Pos          (3U)
10799 #define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
10800 #define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk
10801 #define RCC_AHB1RSTR_GPIOERST_Pos          (4U)
10802 #define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
10803 #define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk
10804 #define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)
10805 #define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
10806 #define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk
10807 #define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)
10808 #define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
10809 #define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk
10810 #define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)
10811 #define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
10812 #define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk
10813 #define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)
10814 #define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
10815 #define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk
10816 #define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)
10817 #define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
10818 #define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk
10819 #define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)
10820 #define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
10821 #define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk
10822 #define RCC_AHB1RSTR_CRCRST_Pos            (12U)
10823 #define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
10824 #define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk
10825 #define RCC_AHB1RSTR_DMA1RST_Pos           (21U)
10826 #define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
10827 #define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk
10828 #define RCC_AHB1RSTR_DMA2RST_Pos           (22U)
10829 #define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
10830 #define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk
10831 #define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)
10832 #define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
10833 #define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk
10834 #define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)
10835 #define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
10836 #define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk
10837 #define RCC_AHB1RSTR_OTGHRST_Pos           (29U)
10838 #define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
10839 #define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk
10840 
10841 /********************  Bit definition for RCC_AHB2RSTR register  **************/
10842 #define RCC_AHB2RSTR_DCMIRST_Pos           (0U)
10843 #define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
10844 #define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk
10845 #define RCC_AHB2RSTR_CRYPRST_Pos           (4U)
10846 #define RCC_AHB2RSTR_CRYPRST_Msk           (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)  /*!< 0x00000010 */
10847 #define RCC_AHB2RSTR_CRYPRST               RCC_AHB2RSTR_CRYPRST_Msk
10848 #define RCC_AHB2RSTR_HASHRST_Pos           (5U)
10849 #define RCC_AHB2RSTR_HASHRST_Msk           (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)  /*!< 0x00000020 */
10850 #define RCC_AHB2RSTR_HASHRST               RCC_AHB2RSTR_HASHRST_Msk
10851 #define RCC_AHB2RSTR_RNGRST_Pos            (6U)
10852 #define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
10853 #define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk
10854 #define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)
10855 #define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
10856 #define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk
10857 
10858 /********************  Bit definition for RCC_AHB3RSTR register  **************/
10859 
10860 #define RCC_AHB3RSTR_FMCRST_Pos            (0U)
10861 #define RCC_AHB3RSTR_FMCRST_Msk            (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */
10862 #define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk
10863 #define RCC_AHB3RSTR_QSPIRST_Pos           (1U)
10864 #define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */
10865 #define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk
10866 
10867 /********************  Bit definition for RCC_APB1RSTR register  **************/
10868 #define RCC_APB1RSTR_TIM2RST_Pos           (0U)
10869 #define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
10870 #define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk
10871 #define RCC_APB1RSTR_TIM3RST_Pos           (1U)
10872 #define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
10873 #define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk
10874 #define RCC_APB1RSTR_TIM4RST_Pos           (2U)
10875 #define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
10876 #define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk
10877 #define RCC_APB1RSTR_TIM5RST_Pos           (3U)
10878 #define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
10879 #define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk
10880 #define RCC_APB1RSTR_TIM6RST_Pos           (4U)
10881 #define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
10882 #define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk
10883 #define RCC_APB1RSTR_TIM7RST_Pos           (5U)
10884 #define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
10885 #define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk
10886 #define RCC_APB1RSTR_TIM12RST_Pos          (6U)
10887 #define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
10888 #define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk
10889 #define RCC_APB1RSTR_TIM13RST_Pos          (7U)
10890 #define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
10891 #define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk
10892 #define RCC_APB1RSTR_TIM14RST_Pos          (8U)
10893 #define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
10894 #define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk
10895 #define RCC_APB1RSTR_LPTIM1RST_Pos         (9U)
10896 #define RCC_APB1RSTR_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
10897 #define RCC_APB1RSTR_LPTIM1RST             RCC_APB1RSTR_LPTIM1RST_Msk
10898 #define RCC_APB1RSTR_WWDGRST_Pos           (11U)
10899 #define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
10900 #define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk
10901 #define RCC_APB1RSTR_SPI2RST_Pos           (14U)
10902 #define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
10903 #define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk
10904 #define RCC_APB1RSTR_SPI3RST_Pos           (15U)
10905 #define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
10906 #define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk
10907 #define RCC_APB1RSTR_SPDIFRXRST_Pos        (16U)
10908 #define RCC_APB1RSTR_SPDIFRXRST_Msk        (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
10909 #define RCC_APB1RSTR_SPDIFRXRST            RCC_APB1RSTR_SPDIFRXRST_Msk
10910 #define RCC_APB1RSTR_USART2RST_Pos         (17U)
10911 #define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
10912 #define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk
10913 #define RCC_APB1RSTR_USART3RST_Pos         (18U)
10914 #define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
10915 #define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk
10916 #define RCC_APB1RSTR_UART4RST_Pos          (19U)
10917 #define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
10918 #define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk
10919 #define RCC_APB1RSTR_UART5RST_Pos          (20U)
10920 #define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
10921 #define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk
10922 #define RCC_APB1RSTR_I2C1RST_Pos           (21U)
10923 #define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
10924 #define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk
10925 #define RCC_APB1RSTR_I2C2RST_Pos           (22U)
10926 #define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
10927 #define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk
10928 #define RCC_APB1RSTR_I2C3RST_Pos           (23U)
10929 #define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
10930 #define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk
10931 #define RCC_APB1RSTR_I2C4RST_Pos           (24U)
10932 #define RCC_APB1RSTR_I2C4RST_Msk           (0x1UL << RCC_APB1RSTR_I2C4RST_Pos)  /*!< 0x01000000 */
10933 #define RCC_APB1RSTR_I2C4RST               RCC_APB1RSTR_I2C4RST_Msk
10934 #define RCC_APB1RSTR_CAN1RST_Pos           (25U)
10935 #define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
10936 #define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk
10937 #define RCC_APB1RSTR_CAN2RST_Pos           (26U)
10938 #define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
10939 #define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk
10940 #define RCC_APB1RSTR_CECRST_Pos            (27U)
10941 #define RCC_APB1RSTR_CECRST_Msk            (0x1UL << RCC_APB1RSTR_CECRST_Pos)   /*!< 0x08000000 */
10942 #define RCC_APB1RSTR_CECRST                RCC_APB1RSTR_CECRST_Msk
10943 #define RCC_APB1RSTR_PWRRST_Pos            (28U)
10944 #define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
10945 #define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk
10946 #define RCC_APB1RSTR_DACRST_Pos            (29U)
10947 #define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
10948 #define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk
10949 #define RCC_APB1RSTR_UART7RST_Pos          (30U)
10950 #define RCC_APB1RSTR_UART7RST_Msk          (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
10951 #define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk
10952 #define RCC_APB1RSTR_UART8RST_Pos          (31U)
10953 #define RCC_APB1RSTR_UART8RST_Msk          (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
10954 #define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk
10955 
10956 /********************  Bit definition for RCC_APB2RSTR register  **************/
10957 #define RCC_APB2RSTR_TIM1RST_Pos           (0U)
10958 #define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
10959 #define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk
10960 #define RCC_APB2RSTR_TIM8RST_Pos           (1U)
10961 #define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
10962 #define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk
10963 #define RCC_APB2RSTR_USART1RST_Pos         (4U)
10964 #define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
10965 #define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk
10966 #define RCC_APB2RSTR_USART6RST_Pos         (5U)
10967 #define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
10968 #define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk
10969 #define RCC_APB2RSTR_ADCRST_Pos            (8U)
10970 #define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
10971 #define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk
10972 #define RCC_APB2RSTR_SDMMC1RST_Pos         (11U)
10973 #define RCC_APB2RSTR_SDMMC1RST_Msk         (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */
10974 #define RCC_APB2RSTR_SDMMC1RST             RCC_APB2RSTR_SDMMC1RST_Msk
10975 #define RCC_APB2RSTR_SPI1RST_Pos           (12U)
10976 #define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
10977 #define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk
10978 #define RCC_APB2RSTR_SPI4RST_Pos           (13U)
10979 #define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */
10980 #define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk
10981 #define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)
10982 #define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
10983 #define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk
10984 #define RCC_APB2RSTR_TIM9RST_Pos           (16U)
10985 #define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
10986 #define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk
10987 #define RCC_APB2RSTR_TIM10RST_Pos          (17U)
10988 #define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
10989 #define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk
10990 #define RCC_APB2RSTR_TIM11RST_Pos          (18U)
10991 #define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
10992 #define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk
10993 #define RCC_APB2RSTR_SPI5RST_Pos           (20U)
10994 #define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */
10995 #define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk
10996 #define RCC_APB2RSTR_SPI6RST_Pos           (21U)
10997 #define RCC_APB2RSTR_SPI6RST_Msk           (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */
10998 #define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk
10999 #define RCC_APB2RSTR_SAI1RST_Pos           (22U)
11000 #define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */
11001 #define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk
11002 #define RCC_APB2RSTR_SAI2RST_Pos           (23U)
11003 #define RCC_APB2RSTR_SAI2RST_Msk           (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)  /*!< 0x00800000 */
11004 #define RCC_APB2RSTR_SAI2RST               RCC_APB2RSTR_SAI2RST_Msk
11005 #define RCC_APB2RSTR_LTDCRST_Pos           (26U)
11006 #define RCC_APB2RSTR_LTDCRST_Msk           (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)  /*!< 0x04000000 */
11007 #define RCC_APB2RSTR_LTDCRST               RCC_APB2RSTR_LTDCRST_Msk
11008 
11009 /********************  Bit definition for RCC_AHB1ENR register  ***************/
11010 #define RCC_AHB1ENR_GPIOAEN_Pos            (0U)
11011 #define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
11012 #define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk
11013 #define RCC_AHB1ENR_GPIOBEN_Pos            (1U)
11014 #define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
11015 #define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk
11016 #define RCC_AHB1ENR_GPIOCEN_Pos            (2U)
11017 #define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
11018 #define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk
11019 #define RCC_AHB1ENR_GPIODEN_Pos            (3U)
11020 #define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
11021 #define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk
11022 #define RCC_AHB1ENR_GPIOEEN_Pos            (4U)
11023 #define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
11024 #define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk
11025 #define RCC_AHB1ENR_GPIOFEN_Pos            (5U)
11026 #define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
11027 #define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk
11028 #define RCC_AHB1ENR_GPIOGEN_Pos            (6U)
11029 #define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
11030 #define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk
11031 #define RCC_AHB1ENR_GPIOHEN_Pos            (7U)
11032 #define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
11033 #define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk
11034 #define RCC_AHB1ENR_GPIOIEN_Pos            (8U)
11035 #define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
11036 #define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk
11037 #define RCC_AHB1ENR_GPIOJEN_Pos            (9U)
11038 #define RCC_AHB1ENR_GPIOJEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */
11039 #define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk
11040 #define RCC_AHB1ENR_GPIOKEN_Pos            (10U)
11041 #define RCC_AHB1ENR_GPIOKEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */
11042 #define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk
11043 #define RCC_AHB1ENR_CRCEN_Pos              (12U)
11044 #define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
11045 #define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk
11046 #define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)
11047 #define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
11048 #define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk
11049 #define RCC_AHB1ENR_DTCMRAMEN_Pos          (20U)
11050 #define RCC_AHB1ENR_DTCMRAMEN_Msk          (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */
11051 #define RCC_AHB1ENR_DTCMRAMEN              RCC_AHB1ENR_DTCMRAMEN_Msk
11052 #define RCC_AHB1ENR_DMA1EN_Pos             (21U)
11053 #define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
11054 #define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk
11055 #define RCC_AHB1ENR_DMA2EN_Pos             (22U)
11056 #define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
11057 #define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk
11058 #define RCC_AHB1ENR_DMA2DEN_Pos            (23U)
11059 #define RCC_AHB1ENR_DMA2DEN_Msk            (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */
11060 #define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk
11061 #define RCC_AHB1ENR_ETHMACEN_Pos           (25U)
11062 #define RCC_AHB1ENR_ETHMACEN_Msk           (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
11063 #define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk
11064 #define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)
11065 #define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
11066 #define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk
11067 #define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)
11068 #define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
11069 #define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk
11070 #define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)
11071 #define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
11072 #define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk
11073 #define RCC_AHB1ENR_OTGHSEN_Pos            (29U)
11074 #define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
11075 #define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk
11076 #define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)
11077 #define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
11078 #define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk
11079 
11080 /********************  Bit definition for RCC_AHB2ENR register  ***************/
11081 #define RCC_AHB2ENR_DCMIEN_Pos             (0U)
11082 #define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
11083 #define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk
11084 #define RCC_AHB2ENR_CRYPEN_Pos             (4U)
11085 #define RCC_AHB2ENR_CRYPEN_Msk             (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)    /*!< 0x00000010 */
11086 #define RCC_AHB2ENR_CRYPEN                 RCC_AHB2ENR_CRYPEN_Msk
11087 #define RCC_AHB2ENR_HASHEN_Pos             (5U)
11088 #define RCC_AHB2ENR_HASHEN_Msk             (0x1UL << RCC_AHB2ENR_HASHEN_Pos)    /*!< 0x00000020 */
11089 #define RCC_AHB2ENR_HASHEN                 RCC_AHB2ENR_HASHEN_Msk
11090 #define RCC_AHB2ENR_RNGEN_Pos              (6U)
11091 #define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
11092 #define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk
11093 #define RCC_AHB2ENR_OTGFSEN_Pos            (7U)
11094 #define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
11095 #define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk
11096 
11097 /********************  Bit definition for RCC_AHB3ENR register  ***************/
11098 #define RCC_AHB3ENR_FMCEN_Pos              (0U)
11099 #define RCC_AHB3ENR_FMCEN_Msk              (0x1UL << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */
11100 #define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk
11101 #define RCC_AHB3ENR_QSPIEN_Pos             (1U)
11102 #define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */
11103 #define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk
11104 
11105 /********************  Bit definition for RCC_APB1ENR register  ***************/
11106 #define RCC_APB1ENR_TIM2EN_Pos             (0U)
11107 #define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
11108 #define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk
11109 #define RCC_APB1ENR_TIM3EN_Pos             (1U)
11110 #define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
11111 #define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk
11112 #define RCC_APB1ENR_TIM4EN_Pos             (2U)
11113 #define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
11114 #define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk
11115 #define RCC_APB1ENR_TIM5EN_Pos             (3U)
11116 #define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
11117 #define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk
11118 #define RCC_APB1ENR_TIM6EN_Pos             (4U)
11119 #define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
11120 #define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk
11121 #define RCC_APB1ENR_TIM7EN_Pos             (5U)
11122 #define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
11123 #define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk
11124 #define RCC_APB1ENR_TIM12EN_Pos            (6U)
11125 #define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
11126 #define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk
11127 #define RCC_APB1ENR_TIM13EN_Pos            (7U)
11128 #define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
11129 #define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk
11130 #define RCC_APB1ENR_TIM14EN_Pos            (8U)
11131 #define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
11132 #define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk
11133 #define RCC_APB1ENR_LPTIM1EN_Pos           (9U)
11134 #define RCC_APB1ENR_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)  /*!< 0x00000200 */
11135 #define RCC_APB1ENR_LPTIM1EN               RCC_APB1ENR_LPTIM1EN_Msk
11136 #define RCC_APB1ENR_WWDGEN_Pos             (11U)
11137 #define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
11138 #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk
11139 #define RCC_APB1ENR_SPI2EN_Pos             (14U)
11140 #define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
11141 #define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk
11142 #define RCC_APB1ENR_SPI3EN_Pos             (15U)
11143 #define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
11144 #define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk
11145 #define RCC_APB1ENR_SPDIFRXEN_Pos          (16U)
11146 #define RCC_APB1ENR_SPDIFRXEN_Msk          (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
11147 #define RCC_APB1ENR_SPDIFRXEN              RCC_APB1ENR_SPDIFRXEN_Msk
11148 #define RCC_APB1ENR_USART2EN_Pos           (17U)
11149 #define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
11150 #define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk
11151 #define RCC_APB1ENR_USART3EN_Pos           (18U)
11152 #define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
11153 #define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk
11154 #define RCC_APB1ENR_UART4EN_Pos            (19U)
11155 #define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
11156 #define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk
11157 #define RCC_APB1ENR_UART5EN_Pos            (20U)
11158 #define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
11159 #define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk
11160 #define RCC_APB1ENR_I2C1EN_Pos             (21U)
11161 #define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
11162 #define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk
11163 #define RCC_APB1ENR_I2C2EN_Pos             (22U)
11164 #define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
11165 #define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk
11166 #define RCC_APB1ENR_I2C3EN_Pos             (23U)
11167 #define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
11168 #define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk
11169 #define RCC_APB1ENR_I2C4EN_Pos             (24U)
11170 #define RCC_APB1ENR_I2C4EN_Msk             (0x1UL << RCC_APB1ENR_I2C4EN_Pos)    /*!< 0x01000000 */
11171 #define RCC_APB1ENR_I2C4EN                 RCC_APB1ENR_I2C4EN_Msk
11172 #define RCC_APB1ENR_CAN1EN_Pos             (25U)
11173 #define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
11174 #define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk
11175 #define RCC_APB1ENR_CAN2EN_Pos             (26U)
11176 #define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
11177 #define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk
11178 #define RCC_APB1ENR_CECEN_Pos              (27U)
11179 #define RCC_APB1ENR_CECEN_Msk              (0x1UL << RCC_APB1ENR_CECEN_Pos)     /*!< 0x08000000 */
11180 #define RCC_APB1ENR_CECEN                  RCC_APB1ENR_CECEN_Msk
11181 #define RCC_APB1ENR_PWREN_Pos              (28U)
11182 #define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
11183 #define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk
11184 #define RCC_APB1ENR_DACEN_Pos              (29U)
11185 #define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
11186 #define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk
11187 #define RCC_APB1ENR_UART7EN_Pos            (30U)
11188 #define RCC_APB1ENR_UART7EN_Msk            (0x1UL << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */
11189 #define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk
11190 #define RCC_APB1ENR_UART8EN_Pos            (31U)
11191 #define RCC_APB1ENR_UART8EN_Msk            (0x1UL << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */
11192 #define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk
11193 
11194 /********************  Bit definition for RCC_APB2ENR register  ***************/
11195 #define RCC_APB2ENR_TIM1EN_Pos             (0U)
11196 #define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
11197 #define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk
11198 #define RCC_APB2ENR_TIM8EN_Pos             (1U)
11199 #define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
11200 #define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk
11201 #define RCC_APB2ENR_USART1EN_Pos           (4U)
11202 #define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
11203 #define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk
11204 #define RCC_APB2ENR_USART6EN_Pos           (5U)
11205 #define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
11206 #define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk
11207 #define RCC_APB2ENR_ADC1EN_Pos             (8U)
11208 #define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
11209 #define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk
11210 #define RCC_APB2ENR_ADC2EN_Pos             (9U)
11211 #define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
11212 #define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk
11213 #define RCC_APB2ENR_ADC3EN_Pos             (10U)
11214 #define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
11215 #define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk
11216 #define RCC_APB2ENR_SDMMC1EN_Pos           (11U)
11217 #define RCC_APB2ENR_SDMMC1EN_Msk           (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)  /*!< 0x00000800 */
11218 #define RCC_APB2ENR_SDMMC1EN               RCC_APB2ENR_SDMMC1EN_Msk
11219 #define RCC_APB2ENR_SPI1EN_Pos             (12U)
11220 #define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
11221 #define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk
11222 #define RCC_APB2ENR_SPI4EN_Pos             (13U)
11223 #define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */
11224 #define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk
11225 #define RCC_APB2ENR_SYSCFGEN_Pos           (14U)
11226 #define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
11227 #define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk
11228 #define RCC_APB2ENR_TIM9EN_Pos             (16U)
11229 #define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
11230 #define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk
11231 #define RCC_APB2ENR_TIM10EN_Pos            (17U)
11232 #define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
11233 #define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk
11234 #define RCC_APB2ENR_TIM11EN_Pos            (18U)
11235 #define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
11236 #define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk
11237 #define RCC_APB2ENR_SPI5EN_Pos             (20U)
11238 #define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */
11239 #define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk
11240 #define RCC_APB2ENR_SPI6EN_Pos             (21U)
11241 #define RCC_APB2ENR_SPI6EN_Msk             (0x1UL << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */
11242 #define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk
11243 #define RCC_APB2ENR_SAI1EN_Pos             (22U)
11244 #define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */
11245 #define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk
11246 #define RCC_APB2ENR_SAI2EN_Pos             (23U)
11247 #define RCC_APB2ENR_SAI2EN_Msk             (0x1UL << RCC_APB2ENR_SAI2EN_Pos)    /*!< 0x00800000 */
11248 #define RCC_APB2ENR_SAI2EN                 RCC_APB2ENR_SAI2EN_Msk
11249 #define RCC_APB2ENR_LTDCEN_Pos             (26U)
11250 #define RCC_APB2ENR_LTDCEN_Msk             (0x1UL << RCC_APB2ENR_LTDCEN_Pos)    /*!< 0x04000000 */
11251 #define RCC_APB2ENR_LTDCEN                 RCC_APB2ENR_LTDCEN_Msk
11252 
11253 /********************  Bit definition for RCC_AHB1LPENR register  *************/
11254 #define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)
11255 #define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
11256 #define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk
11257 #define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)
11258 #define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
11259 #define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk
11260 #define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)
11261 #define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
11262 #define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk
11263 #define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)
11264 #define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
11265 #define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk
11266 #define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)
11267 #define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
11268 #define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk
11269 #define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)
11270 #define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
11271 #define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk
11272 #define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)
11273 #define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
11274 #define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk
11275 #define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)
11276 #define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
11277 #define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk
11278 #define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)
11279 #define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
11280 #define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk
11281 #define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)
11282 #define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
11283 #define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk
11284 #define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)
11285 #define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
11286 #define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk
11287 #define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)
11288 #define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
11289 #define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk
11290 #define RCC_AHB1LPENR_AXILPEN_Pos          (13U)
11291 #define RCC_AHB1LPENR_AXILPEN_Msk          (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */
11292 #define RCC_AHB1LPENR_AXILPEN              RCC_AHB1LPENR_AXILPEN_Msk
11293 #define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)
11294 #define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
11295 #define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk
11296 #define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)
11297 #define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
11298 #define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk
11299 #define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)
11300 #define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
11301 #define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk
11302 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)
11303 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
11304 #define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11305 #define RCC_AHB1LPENR_DTCMLPEN_Pos         (20U)
11306 #define RCC_AHB1LPENR_DTCMLPEN_Msk         (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */
11307 #define RCC_AHB1LPENR_DTCMLPEN             RCC_AHB1LPENR_DTCMLPEN_Msk
11308 #define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)
11309 #define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
11310 #define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk
11311 #define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)
11312 #define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
11313 #define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk
11314 #define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)
11315 #define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
11316 #define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk
11317 #define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)
11318 #define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
11319 #define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk
11320 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)
11321 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
11322 #define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11323 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)
11324 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
11325 #define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11326 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)
11327 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
11328 #define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11329 #define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)
11330 #define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
11331 #define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk
11332 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)
11333 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
11334 #define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11335 
11336 /********************  Bit definition for RCC_AHB2LPENR register  *************/
11337 #define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)
11338 #define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
11339 #define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk
11340 #define RCC_AHB2LPENR_CRYPLPEN_Pos         (4U)
11341 #define RCC_AHB2LPENR_CRYPLPEN_Msk         (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
11342 #define RCC_AHB2LPENR_CRYPLPEN             RCC_AHB2LPENR_CRYPLPEN_Msk
11343 #define RCC_AHB2LPENR_HASHLPEN_Pos         (5U)
11344 #define RCC_AHB2LPENR_HASHLPEN_Msk         (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
11345 #define RCC_AHB2LPENR_HASHLPEN             RCC_AHB2LPENR_HASHLPEN_Msk
11346 #define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)
11347 #define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
11348 #define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk
11349 #define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)
11350 #define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
11351 #define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk
11352 
11353 /********************  Bit definition for RCC_AHB3LPENR register  *************/
11354 #define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)
11355 #define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
11356 #define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk
11357 #define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)
11358 #define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
11359 #define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk
11360 /********************  Bit definition for RCC_APB1LPENR register  *************/
11361 #define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)
11362 #define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
11363 #define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk
11364 #define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)
11365 #define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
11366 #define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk
11367 #define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)
11368 #define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
11369 #define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk
11370 #define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)
11371 #define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
11372 #define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk
11373 #define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)
11374 #define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
11375 #define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk
11376 #define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)
11377 #define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
11378 #define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk
11379 #define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)
11380 #define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
11381 #define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk
11382 #define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)
11383 #define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
11384 #define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk
11385 #define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)
11386 #define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
11387 #define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk
11388 #define RCC_APB1LPENR_LPTIM1LPEN_Pos       (9U)
11389 #define RCC_APB1LPENR_LPTIM1LPEN_Msk       (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
11390 #define RCC_APB1LPENR_LPTIM1LPEN           RCC_APB1LPENR_LPTIM1LPEN_Msk
11391 #define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)
11392 #define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
11393 #define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk
11394 #define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)
11395 #define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
11396 #define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk
11397 #define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)
11398 #define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
11399 #define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk
11400 #define RCC_APB1LPENR_SPDIFRXLPEN_Pos      (16U)
11401 #define RCC_APB1LPENR_SPDIFRXLPEN_Msk      (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
11402 #define RCC_APB1LPENR_SPDIFRXLPEN          RCC_APB1LPENR_SPDIFRXLPEN_Msk
11403 #define RCC_APB1LPENR_USART2LPEN_Pos       (17U)
11404 #define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
11405 #define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk
11406 #define RCC_APB1LPENR_USART3LPEN_Pos       (18U)
11407 #define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
11408 #define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk
11409 #define RCC_APB1LPENR_UART4LPEN_Pos        (19U)
11410 #define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
11411 #define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk
11412 #define RCC_APB1LPENR_UART5LPEN_Pos        (20U)
11413 #define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
11414 #define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk
11415 #define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)
11416 #define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
11417 #define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk
11418 #define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)
11419 #define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
11420 #define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk
11421 #define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)
11422 #define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
11423 #define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk
11424 #define RCC_APB1LPENR_I2C4LPEN_Pos         (24U)
11425 #define RCC_APB1LPENR_I2C4LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C4LPEN_Pos) /*!< 0x01000000 */
11426 #define RCC_APB1LPENR_I2C4LPEN             RCC_APB1LPENR_I2C4LPEN_Msk
11427 #define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)
11428 #define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
11429 #define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk
11430 #define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)
11431 #define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
11432 #define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk
11433 #define RCC_APB1LPENR_CECLPEN_Pos          (27U)
11434 #define RCC_APB1LPENR_CECLPEN_Msk          (0x1UL << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
11435 #define RCC_APB1LPENR_CECLPEN              RCC_APB1LPENR_CECLPEN_Msk
11436 #define RCC_APB1LPENR_PWRLPEN_Pos          (28U)
11437 #define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
11438 #define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk
11439 #define RCC_APB1LPENR_DACLPEN_Pos          (29U)
11440 #define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
11441 #define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk
11442 #define RCC_APB1LPENR_UART7LPEN_Pos        (30U)
11443 #define RCC_APB1LPENR_UART7LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
11444 #define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk
11445 #define RCC_APB1LPENR_UART8LPEN_Pos        (31U)
11446 #define RCC_APB1LPENR_UART8LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
11447 #define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk
11448 
11449 /********************  Bit definition for RCC_APB2LPENR register  *************/
11450 #define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)
11451 #define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
11452 #define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk
11453 #define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)
11454 #define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
11455 #define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk
11456 #define RCC_APB2LPENR_USART1LPEN_Pos       (4U)
11457 #define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
11458 #define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk
11459 #define RCC_APB2LPENR_USART6LPEN_Pos       (5U)
11460 #define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
11461 #define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk
11462 #define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)
11463 #define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
11464 #define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk
11465 #define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)
11466 #define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
11467 #define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk
11468 #define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)
11469 #define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
11470 #define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk
11471 #define RCC_APB2LPENR_SDMMC1LPEN_Pos       (11U)
11472 #define RCC_APB2LPENR_SDMMC1LPEN_Msk       (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */
11473 #define RCC_APB2LPENR_SDMMC1LPEN           RCC_APB2LPENR_SDMMC1LPEN_Msk
11474 #define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)
11475 #define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
11476 #define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk
11477 #define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)
11478 #define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
11479 #define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk
11480 #define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)
11481 #define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
11482 #define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk
11483 #define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)
11484 #define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
11485 #define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk
11486 #define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)
11487 #define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
11488 #define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk
11489 #define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)
11490 #define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
11491 #define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk
11492 #define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)
11493 #define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
11494 #define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk
11495 #define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)
11496 #define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
11497 #define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk
11498 #define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)
11499 #define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
11500 #define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk
11501 #define RCC_APB2LPENR_SAI2LPEN_Pos         (23U)
11502 #define RCC_APB2LPENR_SAI2LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
11503 #define RCC_APB2LPENR_SAI2LPEN             RCC_APB2LPENR_SAI2LPEN_Msk
11504 #define RCC_APB2LPENR_LTDCLPEN_Pos         (26U)
11505 #define RCC_APB2LPENR_LTDCLPEN_Msk         (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
11506 #define RCC_APB2LPENR_LTDCLPEN             RCC_APB2LPENR_LTDCLPEN_Msk
11507 
11508 /********************  Bit definition for RCC_BDCR register  ******************/
11509 #define RCC_BDCR_LSEON_Pos                 (0U)
11510 #define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
11511 #define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk
11512 #define RCC_BDCR_LSERDY_Pos                (1U)
11513 #define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
11514 #define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk
11515 #define RCC_BDCR_LSEBYP_Pos                (2U)
11516 #define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
11517 #define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk
11518 #define RCC_BDCR_LSEDRV_Pos                (3U)
11519 #define RCC_BDCR_LSEDRV_Msk                (0x3UL << RCC_BDCR_LSEDRV_Pos)       /*!< 0x00000018 */
11520 #define RCC_BDCR_LSEDRV                    RCC_BDCR_LSEDRV_Msk
11521 #define RCC_BDCR_LSEDRV_0                  (0x1UL << RCC_BDCR_LSEDRV_Pos)       /*!< 0x00000008 */
11522 #define RCC_BDCR_LSEDRV_1                  (0x2UL << RCC_BDCR_LSEDRV_Pos)       /*!< 0x00000010 */
11523 #define RCC_BDCR_RTCSEL_Pos                (8U)
11524 #define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
11525 #define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk
11526 #define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
11527 #define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
11528 #define RCC_BDCR_RTCEN_Pos                 (15U)
11529 #define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
11530 #define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk
11531 #define RCC_BDCR_BDRST_Pos                 (16U)
11532 #define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
11533 #define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk
11534 
11535 /********************  Bit definition for RCC_CSR register  *******************/
11536 #define RCC_CSR_LSION_Pos                  (0U)
11537 #define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
11538 #define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
11539 #define RCC_CSR_LSIRDY_Pos                 (1U)
11540 #define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
11541 #define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
11542 #define RCC_CSR_RMVF_Pos                   (24U)
11543 #define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
11544 #define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk
11545 #define RCC_CSR_BORRSTF_Pos                (25U)
11546 #define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
11547 #define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk
11548 #define RCC_CSR_PINRSTF_Pos                (26U)
11549 #define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
11550 #define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
11551 #define RCC_CSR_PORRSTF_Pos                (27U)
11552 #define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
11553 #define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk
11554 #define RCC_CSR_SFTRSTF_Pos                (28U)
11555 #define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
11556 #define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk
11557 #define RCC_CSR_IWDGRSTF_Pos               (29U)
11558 #define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
11559 #define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
11560 #define RCC_CSR_WWDGRSTF_Pos               (30U)
11561 #define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
11562 #define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk
11563 #define RCC_CSR_LPWRRSTF_Pos               (31U)
11564 #define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
11565 #define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
11566 
11567 /********************  Bit definition for RCC_SSCGR register  *****************/
11568 #define RCC_SSCGR_MODPER_Pos               (0U)
11569 #define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
11570 #define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk
11571 #define RCC_SSCGR_INCSTEP_Pos              (13U)
11572 #define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
11573 #define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk
11574 #define RCC_SSCGR_SPREADSEL_Pos            (30U)
11575 #define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
11576 #define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk
11577 #define RCC_SSCGR_SSCGEN_Pos               (31U)
11578 #define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
11579 #define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk
11580 
11581 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
11582 #define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)
11583 #define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
11584 #define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk
11585 #define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
11586 #define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
11587 #define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
11588 #define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
11589 #define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
11590 #define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
11591 #define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
11592 #define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
11593 #define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
11594 #define RCC_PLLI2SCFGR_PLLI2SP_Pos         (16U)
11595 #define RCC_PLLI2SCFGR_PLLI2SP_Msk         (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
11596 #define RCC_PLLI2SCFGR_PLLI2SP             RCC_PLLI2SCFGR_PLLI2SP_Msk
11597 #define RCC_PLLI2SCFGR_PLLI2SP_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
11598 #define RCC_PLLI2SCFGR_PLLI2SP_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
11599 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)
11600 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
11601 #define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk
11602 #define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
11603 #define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
11604 #define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
11605 #define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
11606 #define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)
11607 #define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
11608 #define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk
11609 #define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
11610 #define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
11611 #define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
11612 
11613 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
11614 #define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)
11615 #define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
11616 #define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk
11617 #define RCC_PLLSAICFGR_PLLSAIN_0           (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
11618 #define RCC_PLLSAICFGR_PLLSAIN_1           (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
11619 #define RCC_PLLSAICFGR_PLLSAIN_2           (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
11620 #define RCC_PLLSAICFGR_PLLSAIN_3           (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
11621 #define RCC_PLLSAICFGR_PLLSAIN_4           (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
11622 #define RCC_PLLSAICFGR_PLLSAIN_5           (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
11623 #define RCC_PLLSAICFGR_PLLSAIN_6           (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
11624 #define RCC_PLLSAICFGR_PLLSAIN_7           (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
11625 #define RCC_PLLSAICFGR_PLLSAIN_8           (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
11626 #define RCC_PLLSAICFGR_PLLSAIP_Pos         (16U)
11627 #define RCC_PLLSAICFGR_PLLSAIP_Msk         (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
11628 #define RCC_PLLSAICFGR_PLLSAIP             RCC_PLLSAICFGR_PLLSAIP_Msk
11629 #define RCC_PLLSAICFGR_PLLSAIP_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
11630 #define RCC_PLLSAICFGR_PLLSAIP_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
11631 #define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)
11632 #define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
11633 #define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk
11634 #define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
11635 #define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
11636 #define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
11637 #define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
11638 #define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)
11639 #define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
11640 #define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk
11641 #define RCC_PLLSAICFGR_PLLSAIR_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
11642 #define RCC_PLLSAICFGR_PLLSAIR_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
11643 #define RCC_PLLSAICFGR_PLLSAIR_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
11644 
11645 /********************  Bit definition for RCC_DCKCFGR1 register  ***************/
11646 #define RCC_DCKCFGR1_PLLI2SDIVQ_Pos        (0U)
11647 #define RCC_DCKCFGR1_PLLI2SDIVQ_Msk        (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
11648 #define RCC_DCKCFGR1_PLLI2SDIVQ            RCC_DCKCFGR1_PLLI2SDIVQ_Msk
11649 #define RCC_DCKCFGR1_PLLI2SDIVQ_0          (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
11650 #define RCC_DCKCFGR1_PLLI2SDIVQ_1          (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
11651 #define RCC_DCKCFGR1_PLLI2SDIVQ_2          (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
11652 #define RCC_DCKCFGR1_PLLI2SDIVQ_3          (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
11653 #define RCC_DCKCFGR1_PLLI2SDIVQ_4          (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
11654 
11655 #define RCC_DCKCFGR1_PLLSAIDIVQ_Pos        (8U)
11656 #define RCC_DCKCFGR1_PLLSAIDIVQ_Msk        (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
11657 #define RCC_DCKCFGR1_PLLSAIDIVQ            RCC_DCKCFGR1_PLLSAIDIVQ_Msk
11658 #define RCC_DCKCFGR1_PLLSAIDIVQ_0          (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
11659 #define RCC_DCKCFGR1_PLLSAIDIVQ_1          (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
11660 #define RCC_DCKCFGR1_PLLSAIDIVQ_2          (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
11661 #define RCC_DCKCFGR1_PLLSAIDIVQ_3          (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
11662 #define RCC_DCKCFGR1_PLLSAIDIVQ_4          (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
11663 
11664 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos        (16U)
11665 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk        (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11666 #define RCC_DCKCFGR1_PLLSAIDIVR            RCC_DCKCFGR1_PLLSAIDIVR_Msk
11667 #define RCC_DCKCFGR1_PLLSAIDIVR_0          (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11668 #define RCC_DCKCFGR1_PLLSAIDIVR_1          (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
11669 
11670 #define RCC_DCKCFGR1_SAI1SEL_Pos           (20U)
11671 #define RCC_DCKCFGR1_SAI1SEL_Msk           (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos)  /*!< 0x00300000 */
11672 #define RCC_DCKCFGR1_SAI1SEL               RCC_DCKCFGR1_SAI1SEL_Msk
11673 #define RCC_DCKCFGR1_SAI1SEL_0             (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos)  /*!< 0x00100000 */
11674 #define RCC_DCKCFGR1_SAI1SEL_1             (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos)  /*!< 0x00200000 */
11675 
11676 #define RCC_DCKCFGR1_SAI2SEL_Pos           (22U)
11677 #define RCC_DCKCFGR1_SAI2SEL_Msk           (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos)  /*!< 0x00C00000 */
11678 #define RCC_DCKCFGR1_SAI2SEL               RCC_DCKCFGR1_SAI2SEL_Msk
11679 #define RCC_DCKCFGR1_SAI2SEL_0             (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos)  /*!< 0x00400000 */
11680 #define RCC_DCKCFGR1_SAI2SEL_1             (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos)  /*!< 0x00800000 */
11681 
11682 #define RCC_DCKCFGR1_TIMPRE_Pos            (24U)
11683 #define RCC_DCKCFGR1_TIMPRE_Msk            (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos)   /*!< 0x01000000 */
11684 #define RCC_DCKCFGR1_TIMPRE                RCC_DCKCFGR1_TIMPRE_Msk
11685 
11686 /********************  Bit definition for RCC_DCKCFGR2 register  ***************/
11687 #define RCC_DCKCFGR2_USART1SEL_Pos         (0U)
11688 #define RCC_DCKCFGR2_USART1SEL_Msk         (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */
11689 #define RCC_DCKCFGR2_USART1SEL             RCC_DCKCFGR2_USART1SEL_Msk
11690 #define RCC_DCKCFGR2_USART1SEL_0           (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */
11691 #define RCC_DCKCFGR2_USART1SEL_1           (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */
11692 #define RCC_DCKCFGR2_USART2SEL_Pos         (2U)
11693 #define RCC_DCKCFGR2_USART2SEL_Msk         (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */
11694 #define RCC_DCKCFGR2_USART2SEL             RCC_DCKCFGR2_USART2SEL_Msk
11695 #define RCC_DCKCFGR2_USART2SEL_0           (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */
11696 #define RCC_DCKCFGR2_USART2SEL_1           (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */
11697 #define RCC_DCKCFGR2_USART3SEL_Pos         (4U)
11698 #define RCC_DCKCFGR2_USART3SEL_Msk         (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */
11699 #define RCC_DCKCFGR2_USART3SEL             RCC_DCKCFGR2_USART3SEL_Msk
11700 #define RCC_DCKCFGR2_USART3SEL_0           (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */
11701 #define RCC_DCKCFGR2_USART3SEL_1           (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */
11702 #define RCC_DCKCFGR2_UART4SEL_Pos          (6U)
11703 #define RCC_DCKCFGR2_UART4SEL_Msk          (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */
11704 #define RCC_DCKCFGR2_UART4SEL              RCC_DCKCFGR2_UART4SEL_Msk
11705 #define RCC_DCKCFGR2_UART4SEL_0            (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */
11706 #define RCC_DCKCFGR2_UART4SEL_1            (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */
11707 #define RCC_DCKCFGR2_UART5SEL_Pos          (8U)
11708 #define RCC_DCKCFGR2_UART5SEL_Msk          (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */
11709 #define RCC_DCKCFGR2_UART5SEL              RCC_DCKCFGR2_UART5SEL_Msk
11710 #define RCC_DCKCFGR2_UART5SEL_0            (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */
11711 #define RCC_DCKCFGR2_UART5SEL_1            (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */
11712 #define RCC_DCKCFGR2_USART6SEL_Pos         (10U)
11713 #define RCC_DCKCFGR2_USART6SEL_Msk         (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */
11714 #define RCC_DCKCFGR2_USART6SEL             RCC_DCKCFGR2_USART6SEL_Msk
11715 #define RCC_DCKCFGR2_USART6SEL_0           (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */
11716 #define RCC_DCKCFGR2_USART6SEL_1           (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */
11717 #define RCC_DCKCFGR2_UART7SEL_Pos          (12U)
11718 #define RCC_DCKCFGR2_UART7SEL_Msk          (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */
11719 #define RCC_DCKCFGR2_UART7SEL              RCC_DCKCFGR2_UART7SEL_Msk
11720 #define RCC_DCKCFGR2_UART7SEL_0            (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */
11721 #define RCC_DCKCFGR2_UART7SEL_1            (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */
11722 #define RCC_DCKCFGR2_UART8SEL_Pos          (14U)
11723 #define RCC_DCKCFGR2_UART8SEL_Msk          (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */
11724 #define RCC_DCKCFGR2_UART8SEL              RCC_DCKCFGR2_UART8SEL_Msk
11725 #define RCC_DCKCFGR2_UART8SEL_0            (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */
11726 #define RCC_DCKCFGR2_UART8SEL_1            (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */
11727 #define RCC_DCKCFGR2_I2C1SEL_Pos           (16U)
11728 #define RCC_DCKCFGR2_I2C1SEL_Msk           (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos)  /*!< 0x00030000 */
11729 #define RCC_DCKCFGR2_I2C1SEL               RCC_DCKCFGR2_I2C1SEL_Msk
11730 #define RCC_DCKCFGR2_I2C1SEL_0             (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos)  /*!< 0x00010000 */
11731 #define RCC_DCKCFGR2_I2C1SEL_1             (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos)  /*!< 0x00020000 */
11732 #define RCC_DCKCFGR2_I2C2SEL_Pos           (18U)
11733 #define RCC_DCKCFGR2_I2C2SEL_Msk           (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos)  /*!< 0x000C0000 */
11734 #define RCC_DCKCFGR2_I2C2SEL               RCC_DCKCFGR2_I2C2SEL_Msk
11735 #define RCC_DCKCFGR2_I2C2SEL_0             (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos)  /*!< 0x00040000 */
11736 #define RCC_DCKCFGR2_I2C2SEL_1             (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos)  /*!< 0x00080000 */
11737 #define RCC_DCKCFGR2_I2C3SEL_Pos           (20U)
11738 #define RCC_DCKCFGR2_I2C3SEL_Msk           (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos)  /*!< 0x00300000 */
11739 #define RCC_DCKCFGR2_I2C3SEL               RCC_DCKCFGR2_I2C3SEL_Msk
11740 #define RCC_DCKCFGR2_I2C3SEL_0             (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos)  /*!< 0x00100000 */
11741 #define RCC_DCKCFGR2_I2C3SEL_1             (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos)  /*!< 0x00200000 */
11742 #define RCC_DCKCFGR2_I2C4SEL_Pos           (22U)
11743 #define RCC_DCKCFGR2_I2C4SEL_Msk           (0x3UL << RCC_DCKCFGR2_I2C4SEL_Pos)  /*!< 0x00C00000 */
11744 #define RCC_DCKCFGR2_I2C4SEL               RCC_DCKCFGR2_I2C4SEL_Msk
11745 #define RCC_DCKCFGR2_I2C4SEL_0             (0x1UL << RCC_DCKCFGR2_I2C4SEL_Pos)  /*!< 0x00400000 */
11746 #define RCC_DCKCFGR2_I2C4SEL_1             (0x2UL << RCC_DCKCFGR2_I2C4SEL_Pos)  /*!< 0x00800000 */
11747 #define RCC_DCKCFGR2_LPTIM1SEL_Pos         (24U)
11748 #define RCC_DCKCFGR2_LPTIM1SEL_Msk         (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */
11749 #define RCC_DCKCFGR2_LPTIM1SEL             RCC_DCKCFGR2_LPTIM1SEL_Msk
11750 #define RCC_DCKCFGR2_LPTIM1SEL_0           (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */
11751 #define RCC_DCKCFGR2_LPTIM1SEL_1           (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */
11752 #define RCC_DCKCFGR2_CECSEL_Pos            (26U)
11753 #define RCC_DCKCFGR2_CECSEL_Msk            (0x1UL << RCC_DCKCFGR2_CECSEL_Pos)   /*!< 0x04000000 */
11754 #define RCC_DCKCFGR2_CECSEL                RCC_DCKCFGR2_CECSEL_Msk
11755 #define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)
11756 #define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
11757 #define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk
11758 #define RCC_DCKCFGR2_SDMMC1SEL_Pos         (28U)
11759 #define RCC_DCKCFGR2_SDMMC1SEL_Msk         (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */
11760 #define RCC_DCKCFGR2_SDMMC1SEL             RCC_DCKCFGR2_SDMMC1SEL_Msk
11761 
11762 /******************************************************************************/
11763 /*                                                                            */
11764 /*                                    RNG                                     */
11765 /*                                                                            */
11766 /******************************************************************************/
11767 /********************  Bits definition for RNG_CR register  *******************/
11768 #define RNG_CR_RNGEN_Pos    (2U)
11769 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
11770 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
11771 #define RNG_CR_IE_Pos       (3U)
11772 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
11773 #define RNG_CR_IE           RNG_CR_IE_Msk
11774 
11775 /********************  Bits definition for RNG_SR register  *******************/
11776 #define RNG_SR_DRDY_Pos     (0U)
11777 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
11778 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
11779 #define RNG_SR_CECS_Pos     (1U)
11780 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
11781 #define RNG_SR_CECS         RNG_SR_CECS_Msk
11782 #define RNG_SR_SECS_Pos     (2U)
11783 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
11784 #define RNG_SR_SECS         RNG_SR_SECS_Msk
11785 #define RNG_SR_CEIS_Pos     (5U)
11786 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
11787 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
11788 #define RNG_SR_SEIS_Pos     (6U)
11789 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
11790 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
11791 
11792 /******************************************************************************/
11793 /*                                                                            */
11794 /*                           Real-Time Clock (RTC)                            */
11795 /*                                                                            */
11796 /******************************************************************************/
11797 /********************  Bits definition for RTC_TR register  *******************/
11798 #define RTC_TR_PM_Pos                  (22U)
11799 #define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
11800 #define RTC_TR_PM                      RTC_TR_PM_Msk
11801 #define RTC_TR_HT_Pos                  (20U)
11802 #define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
11803 #define RTC_TR_HT                      RTC_TR_HT_Msk
11804 #define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
11805 #define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
11806 #define RTC_TR_HU_Pos                  (16U)
11807 #define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
11808 #define RTC_TR_HU                      RTC_TR_HU_Msk
11809 #define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
11810 #define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
11811 #define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
11812 #define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
11813 #define RTC_TR_MNT_Pos                 (12U)
11814 #define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
11815 #define RTC_TR_MNT                     RTC_TR_MNT_Msk
11816 #define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
11817 #define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
11818 #define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
11819 #define RTC_TR_MNU_Pos                 (8U)
11820 #define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
11821 #define RTC_TR_MNU                     RTC_TR_MNU_Msk
11822 #define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
11823 #define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
11824 #define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
11825 #define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
11826 #define RTC_TR_ST_Pos                  (4U)
11827 #define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
11828 #define RTC_TR_ST                      RTC_TR_ST_Msk
11829 #define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
11830 #define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
11831 #define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
11832 #define RTC_TR_SU_Pos                  (0U)
11833 #define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
11834 #define RTC_TR_SU                      RTC_TR_SU_Msk
11835 #define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
11836 #define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
11837 #define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
11838 #define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
11839 
11840 /********************  Bits definition for RTC_DR register  *******************/
11841 #define RTC_DR_YT_Pos                  (20U)
11842 #define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
11843 #define RTC_DR_YT                      RTC_DR_YT_Msk
11844 #define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
11845 #define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
11846 #define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
11847 #define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
11848 #define RTC_DR_YU_Pos                  (16U)
11849 #define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
11850 #define RTC_DR_YU                      RTC_DR_YU_Msk
11851 #define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
11852 #define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
11853 #define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
11854 #define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
11855 #define RTC_DR_WDU_Pos                 (13U)
11856 #define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
11857 #define RTC_DR_WDU                     RTC_DR_WDU_Msk
11858 #define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
11859 #define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
11860 #define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
11861 #define RTC_DR_MT_Pos                  (12U)
11862 #define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
11863 #define RTC_DR_MT                      RTC_DR_MT_Msk
11864 #define RTC_DR_MU_Pos                  (8U)
11865 #define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
11866 #define RTC_DR_MU                      RTC_DR_MU_Msk
11867 #define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
11868 #define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
11869 #define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
11870 #define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
11871 #define RTC_DR_DT_Pos                  (4U)
11872 #define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
11873 #define RTC_DR_DT                      RTC_DR_DT_Msk
11874 #define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
11875 #define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
11876 #define RTC_DR_DU_Pos                  (0U)
11877 #define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
11878 #define RTC_DR_DU                      RTC_DR_DU_Msk
11879 #define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
11880 #define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
11881 #define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
11882 #define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
11883 
11884 /********************  Bits definition for RTC_CR register  *******************/
11885 #define RTC_CR_ITSE_Pos                (24U)
11886 #define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */
11887 #define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
11888 #define RTC_CR_COE_Pos                 (23U)
11889 #define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
11890 #define RTC_CR_COE                     RTC_CR_COE_Msk
11891 #define RTC_CR_OSEL_Pos                (21U)
11892 #define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
11893 #define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
11894 #define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
11895 #define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
11896 #define RTC_CR_POL_Pos                 (20U)
11897 #define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
11898 #define RTC_CR_POL                     RTC_CR_POL_Msk
11899 #define RTC_CR_COSEL_Pos               (19U)
11900 #define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
11901 #define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
11902 #define RTC_CR_BKP_Pos                 (18U)
11903 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
11904 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
11905 #define RTC_CR_SUB1H_Pos               (17U)
11906 #define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
11907 #define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
11908 #define RTC_CR_ADD1H_Pos               (16U)
11909 #define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
11910 #define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
11911 #define RTC_CR_TSIE_Pos                (15U)
11912 #define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
11913 #define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
11914 #define RTC_CR_WUTIE_Pos               (14U)
11915 #define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
11916 #define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
11917 #define RTC_CR_ALRBIE_Pos              (13U)
11918 #define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
11919 #define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
11920 #define RTC_CR_ALRAIE_Pos              (12U)
11921 #define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
11922 #define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
11923 #define RTC_CR_TSE_Pos                 (11U)
11924 #define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
11925 #define RTC_CR_TSE                     RTC_CR_TSE_Msk
11926 #define RTC_CR_WUTE_Pos                (10U)
11927 #define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
11928 #define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
11929 #define RTC_CR_ALRBE_Pos               (9U)
11930 #define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
11931 #define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
11932 #define RTC_CR_ALRAE_Pos               (8U)
11933 #define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
11934 #define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
11935 #define RTC_CR_FMT_Pos                 (6U)
11936 #define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
11937 #define RTC_CR_FMT                     RTC_CR_FMT_Msk
11938 #define RTC_CR_BYPSHAD_Pos             (5U)
11939 #define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
11940 #define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
11941 #define RTC_CR_REFCKON_Pos             (4U)
11942 #define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
11943 #define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
11944 #define RTC_CR_TSEDGE_Pos              (3U)
11945 #define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
11946 #define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
11947 #define RTC_CR_WUCKSEL_Pos             (0U)
11948 #define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
11949 #define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
11950 #define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
11951 #define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
11952 #define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
11953 
11954 /* Legacy define */
11955 #define RTC_CR_BCK                           RTC_CR_BKP
11956 
11957 /********************  Bits definition for RTC_ISR register  ******************/
11958 #define RTC_ISR_ITSF_Pos               (17U)
11959 #define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */
11960 #define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
11961 #define RTC_ISR_RECALPF_Pos            (16U)
11962 #define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
11963 #define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
11964 #define RTC_ISR_TAMP3F_Pos             (15U)
11965 #define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
11966 #define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
11967 #define RTC_ISR_TAMP2F_Pos             (14U)
11968 #define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
11969 #define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
11970 #define RTC_ISR_TAMP1F_Pos             (13U)
11971 #define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
11972 #define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
11973 #define RTC_ISR_TSOVF_Pos              (12U)
11974 #define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
11975 #define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
11976 #define RTC_ISR_TSF_Pos                (11U)
11977 #define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
11978 #define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
11979 #define RTC_ISR_WUTF_Pos               (10U)
11980 #define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
11981 #define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
11982 #define RTC_ISR_ALRBF_Pos              (9U)
11983 #define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
11984 #define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
11985 #define RTC_ISR_ALRAF_Pos              (8U)
11986 #define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
11987 #define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
11988 #define RTC_ISR_INIT_Pos               (7U)
11989 #define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
11990 #define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
11991 #define RTC_ISR_INITF_Pos              (6U)
11992 #define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
11993 #define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
11994 #define RTC_ISR_RSF_Pos                (5U)
11995 #define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
11996 #define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
11997 #define RTC_ISR_INITS_Pos              (4U)
11998 #define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
11999 #define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
12000 #define RTC_ISR_SHPF_Pos               (3U)
12001 #define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
12002 #define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
12003 #define RTC_ISR_WUTWF_Pos              (2U)
12004 #define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
12005 #define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
12006 #define RTC_ISR_ALRBWF_Pos             (1U)
12007 #define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
12008 #define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
12009 #define RTC_ISR_ALRAWF_Pos             (0U)
12010 #define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
12011 #define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
12012 
12013 /********************  Bits definition for RTC_PRER register  *****************/
12014 #define RTC_PRER_PREDIV_A_Pos          (16U)
12015 #define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
12016 #define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
12017 #define RTC_PRER_PREDIV_S_Pos          (0U)
12018 #define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
12019 #define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
12020 
12021 /********************  Bits definition for RTC_WUTR register  *****************/
12022 #define RTC_WUTR_WUT_Pos               (0U)
12023 #define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
12024 #define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
12025 
12026 /********************  Bits definition for RTC_ALRMAR register  ***************/
12027 #define RTC_ALRMAR_MSK4_Pos            (31U)
12028 #define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
12029 #define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
12030 #define RTC_ALRMAR_WDSEL_Pos           (30U)
12031 #define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
12032 #define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
12033 #define RTC_ALRMAR_DT_Pos              (28U)
12034 #define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
12035 #define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
12036 #define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
12037 #define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
12038 #define RTC_ALRMAR_DU_Pos              (24U)
12039 #define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
12040 #define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
12041 #define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
12042 #define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
12043 #define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
12044 #define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
12045 #define RTC_ALRMAR_MSK3_Pos            (23U)
12046 #define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
12047 #define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
12048 #define RTC_ALRMAR_PM_Pos              (22U)
12049 #define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
12050 #define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
12051 #define RTC_ALRMAR_HT_Pos              (20U)
12052 #define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
12053 #define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
12054 #define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
12055 #define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
12056 #define RTC_ALRMAR_HU_Pos              (16U)
12057 #define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
12058 #define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
12059 #define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
12060 #define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
12061 #define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
12062 #define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
12063 #define RTC_ALRMAR_MSK2_Pos            (15U)
12064 #define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
12065 #define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
12066 #define RTC_ALRMAR_MNT_Pos             (12U)
12067 #define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
12068 #define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
12069 #define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
12070 #define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
12071 #define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
12072 #define RTC_ALRMAR_MNU_Pos             (8U)
12073 #define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
12074 #define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
12075 #define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
12076 #define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
12077 #define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
12078 #define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
12079 #define RTC_ALRMAR_MSK1_Pos            (7U)
12080 #define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
12081 #define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
12082 #define RTC_ALRMAR_ST_Pos              (4U)
12083 #define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
12084 #define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
12085 #define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
12086 #define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
12087 #define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
12088 #define RTC_ALRMAR_SU_Pos              (0U)
12089 #define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
12090 #define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
12091 #define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
12092 #define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
12093 #define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
12094 #define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
12095 
12096 /********************  Bits definition for RTC_ALRMBR register  ***************/
12097 #define RTC_ALRMBR_MSK4_Pos            (31U)
12098 #define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
12099 #define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
12100 #define RTC_ALRMBR_WDSEL_Pos           (30U)
12101 #define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
12102 #define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
12103 #define RTC_ALRMBR_DT_Pos              (28U)
12104 #define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
12105 #define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
12106 #define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
12107 #define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
12108 #define RTC_ALRMBR_DU_Pos              (24U)
12109 #define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
12110 #define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
12111 #define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
12112 #define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
12113 #define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
12114 #define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
12115 #define RTC_ALRMBR_MSK3_Pos            (23U)
12116 #define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
12117 #define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
12118 #define RTC_ALRMBR_PM_Pos              (22U)
12119 #define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
12120 #define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
12121 #define RTC_ALRMBR_HT_Pos              (20U)
12122 #define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
12123 #define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
12124 #define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
12125 #define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
12126 #define RTC_ALRMBR_HU_Pos              (16U)
12127 #define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
12128 #define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
12129 #define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
12130 #define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
12131 #define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
12132 #define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
12133 #define RTC_ALRMBR_MSK2_Pos            (15U)
12134 #define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
12135 #define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
12136 #define RTC_ALRMBR_MNT_Pos             (12U)
12137 #define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
12138 #define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
12139 #define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
12140 #define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
12141 #define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
12142 #define RTC_ALRMBR_MNU_Pos             (8U)
12143 #define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
12144 #define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
12145 #define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
12146 #define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
12147 #define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
12148 #define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
12149 #define RTC_ALRMBR_MSK1_Pos            (7U)
12150 #define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
12151 #define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
12152 #define RTC_ALRMBR_ST_Pos              (4U)
12153 #define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
12154 #define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
12155 #define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
12156 #define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
12157 #define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
12158 #define RTC_ALRMBR_SU_Pos              (0U)
12159 #define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
12160 #define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
12161 #define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
12162 #define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
12163 #define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
12164 #define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
12165 
12166 /********************  Bits definition for RTC_WPR register  ******************/
12167 #define RTC_WPR_KEY_Pos                (0U)
12168 #define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
12169 #define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
12170 
12171 /********************  Bits definition for RTC_SSR register  ******************/
12172 #define RTC_SSR_SS_Pos                 (0U)
12173 #define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
12174 #define RTC_SSR_SS                     RTC_SSR_SS_Msk
12175 
12176 /********************  Bits definition for RTC_SHIFTR register  ***************/
12177 #define RTC_SHIFTR_SUBFS_Pos           (0U)
12178 #define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
12179 #define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
12180 #define RTC_SHIFTR_ADD1S_Pos           (31U)
12181 #define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
12182 #define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
12183 
12184 /********************  Bits definition for RTC_TSTR register  *****************/
12185 #define RTC_TSTR_PM_Pos                (22U)
12186 #define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
12187 #define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
12188 #define RTC_TSTR_HT_Pos                (20U)
12189 #define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
12190 #define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
12191 #define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
12192 #define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
12193 #define RTC_TSTR_HU_Pos                (16U)
12194 #define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
12195 #define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
12196 #define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
12197 #define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
12198 #define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
12199 #define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
12200 #define RTC_TSTR_MNT_Pos               (12U)
12201 #define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
12202 #define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
12203 #define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
12204 #define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
12205 #define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
12206 #define RTC_TSTR_MNU_Pos               (8U)
12207 #define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
12208 #define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
12209 #define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
12210 #define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
12211 #define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
12212 #define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
12213 #define RTC_TSTR_ST_Pos                (4U)
12214 #define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
12215 #define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
12216 #define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
12217 #define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
12218 #define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
12219 #define RTC_TSTR_SU_Pos                (0U)
12220 #define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
12221 #define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
12222 #define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
12223 #define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
12224 #define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
12225 #define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
12226 
12227 /********************  Bits definition for RTC_TSDR register  *****************/
12228 #define RTC_TSDR_WDU_Pos               (13U)
12229 #define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
12230 #define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
12231 #define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
12232 #define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
12233 #define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
12234 #define RTC_TSDR_MT_Pos                (12U)
12235 #define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
12236 #define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
12237 #define RTC_TSDR_MU_Pos                (8U)
12238 #define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
12239 #define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
12240 #define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
12241 #define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
12242 #define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
12243 #define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
12244 #define RTC_TSDR_DT_Pos                (4U)
12245 #define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
12246 #define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
12247 #define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
12248 #define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
12249 #define RTC_TSDR_DU_Pos                (0U)
12250 #define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
12251 #define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
12252 #define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
12253 #define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
12254 #define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
12255 #define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
12256 
12257 /********************  Bits definition for RTC_TSSSR register  ****************/
12258 #define RTC_TSSSR_SS_Pos               (0U)
12259 #define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
12260 #define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
12261 
12262 /********************  Bits definition for RTC_CAL register  *****************/
12263 #define RTC_CALR_CALP_Pos              (15U)
12264 #define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
12265 #define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
12266 #define RTC_CALR_CALW8_Pos             (14U)
12267 #define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
12268 #define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
12269 #define RTC_CALR_CALW16_Pos            (13U)
12270 #define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
12271 #define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
12272 #define RTC_CALR_CALM_Pos              (0U)
12273 #define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
12274 #define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
12275 #define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
12276 #define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
12277 #define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
12278 #define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
12279 #define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
12280 #define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
12281 #define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
12282 #define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
12283 #define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
12284 
12285 /********************  Bits definition for RTC_TAMPCR register  ****************/
12286 #define RTC_TAMPCR_TAMP3MF_Pos         (24U)
12287 #define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
12288 #define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
12289 #define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
12290 #define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
12291 #define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
12292 #define RTC_TAMPCR_TAMP3IE_Pos         (22U)
12293 #define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
12294 #define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
12295 #define RTC_TAMPCR_TAMP2MF_Pos         (21U)
12296 #define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
12297 #define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
12298 #define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
12299 #define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
12300 #define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
12301 #define RTC_TAMPCR_TAMP2IE_Pos         (19U)
12302 #define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
12303 #define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
12304 #define RTC_TAMPCR_TAMP1MF_Pos         (18U)
12305 #define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
12306 #define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
12307 #define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
12308 #define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
12309 #define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
12310 #define RTC_TAMPCR_TAMP1IE_Pos         (16U)
12311 #define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
12312 #define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
12313 #define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
12314 #define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
12315 #define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
12316 #define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
12317 #define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
12318 #define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
12319 #define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
12320 #define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
12321 #define RTC_TAMPCR_TAMPFLT_Pos         (11U)
12322 #define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
12323 #define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
12324 #define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
12325 #define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
12326 #define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
12327 #define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
12328 #define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
12329 #define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
12330 #define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
12331 #define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
12332 #define RTC_TAMPCR_TAMPTS_Pos          (7U)
12333 #define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
12334 #define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
12335 #define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
12336 #define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
12337 #define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
12338 #define RTC_TAMPCR_TAMP3E_Pos          (5U)
12339 #define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
12340 #define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
12341 #define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
12342 #define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
12343 #define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
12344 #define RTC_TAMPCR_TAMP2E_Pos          (3U)
12345 #define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
12346 #define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
12347 #define RTC_TAMPCR_TAMPIE_Pos          (2U)
12348 #define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
12349 #define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
12350 #define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
12351 #define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
12352 #define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
12353 #define RTC_TAMPCR_TAMP1E_Pos          (0U)
12354 #define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
12355 #define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
12356 
12357 /* Legacy defines */
12358 #define RTC_TAMPCR_TAMP3_TRG                  RTC_TAMPCR_TAMP3TRG
12359 #define RTC_TAMPCR_TAMP2_TRG                  RTC_TAMPCR_TAMP2TRG
12360 #define RTC_TAMPCR_TAMP1_TRG                  RTC_TAMPCR_TAMP1TRG
12361 
12362 /********************  Bits definition for RTC_ALRMASSR register  *************/
12363 #define RTC_ALRMASSR_MASKSS_Pos        (24U)
12364 #define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
12365 #define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
12366 #define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
12367 #define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
12368 #define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
12369 #define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
12370 #define RTC_ALRMASSR_SS_Pos            (0U)
12371 #define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
12372 #define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
12373 
12374 /********************  Bits definition for RTC_ALRMBSSR register  *************/
12375 #define RTC_ALRMBSSR_MASKSS_Pos        (24U)
12376 #define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
12377 #define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
12378 #define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
12379 #define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
12380 #define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
12381 #define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
12382 #define RTC_ALRMBSSR_SS_Pos            (0U)
12383 #define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
12384 #define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
12385 
12386 /********************  Bits definition for RTC_OR register  ****************/
12387 #define RTC_OR_TSINSEL_Pos             (1U)
12388 #define RTC_OR_TSINSEL_Msk             (0x3UL << RTC_OR_TSINSEL_Pos)            /*!< 0x00000006 */
12389 #define RTC_OR_TSINSEL                 RTC_OR_TSINSEL_Msk
12390 #define RTC_OR_TSINSEL_0               (0x1UL << RTC_OR_TSINSEL_Pos)            /*!< 0x00000002 */
12391 #define RTC_OR_TSINSEL_1               (0x2UL << RTC_OR_TSINSEL_Pos)            /*!< 0x00000004 */
12392 #define RTC_OR_ALARMOUTTYPE_Pos        (3U)
12393 #define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000008 */
12394 #define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
12395 /* Legacy defines*/
12396 #define RTC_OR_ALARMTYPE               RTC_OR_ALARMOUTTYPE
12397 
12398 /********************  Bits definition for RTC_BKP0R register  ****************/
12399 #define RTC_BKP0R_Pos                  (0U)
12400 #define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
12401 #define RTC_BKP0R                      RTC_BKP0R_Msk
12402 
12403 /********************  Bits definition for RTC_BKP1R register  ****************/
12404 #define RTC_BKP1R_Pos                  (0U)
12405 #define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
12406 #define RTC_BKP1R                      RTC_BKP1R_Msk
12407 
12408 /********************  Bits definition for RTC_BKP2R register  ****************/
12409 #define RTC_BKP2R_Pos                  (0U)
12410 #define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
12411 #define RTC_BKP2R                      RTC_BKP2R_Msk
12412 
12413 /********************  Bits definition for RTC_BKP3R register  ****************/
12414 #define RTC_BKP3R_Pos                  (0U)
12415 #define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
12416 #define RTC_BKP3R                      RTC_BKP3R_Msk
12417 
12418 /********************  Bits definition for RTC_BKP4R register  ****************/
12419 #define RTC_BKP4R_Pos                  (0U)
12420 #define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
12421 #define RTC_BKP4R                      RTC_BKP4R_Msk
12422 
12423 /********************  Bits definition for RTC_BKP5R register  ****************/
12424 #define RTC_BKP5R_Pos                  (0U)
12425 #define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */
12426 #define RTC_BKP5R                      RTC_BKP5R_Msk
12427 
12428 /********************  Bits definition for RTC_BKP6R register  ****************/
12429 #define RTC_BKP6R_Pos                  (0U)
12430 #define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */
12431 #define RTC_BKP6R                      RTC_BKP6R_Msk
12432 
12433 /********************  Bits definition for RTC_BKP7R register  ****************/
12434 #define RTC_BKP7R_Pos                  (0U)
12435 #define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */
12436 #define RTC_BKP7R                      RTC_BKP7R_Msk
12437 
12438 /********************  Bits definition for RTC_BKP8R register  ****************/
12439 #define RTC_BKP8R_Pos                  (0U)
12440 #define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */
12441 #define RTC_BKP8R                      RTC_BKP8R_Msk
12442 
12443 /********************  Bits definition for RTC_BKP9R register  ****************/
12444 #define RTC_BKP9R_Pos                  (0U)
12445 #define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */
12446 #define RTC_BKP9R                      RTC_BKP9R_Msk
12447 
12448 /********************  Bits definition for RTC_BKP10R register  ***************/
12449 #define RTC_BKP10R_Pos                 (0U)
12450 #define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */
12451 #define RTC_BKP10R                     RTC_BKP10R_Msk
12452 
12453 /********************  Bits definition for RTC_BKP11R register  ***************/
12454 #define RTC_BKP11R_Pos                 (0U)
12455 #define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */
12456 #define RTC_BKP11R                     RTC_BKP11R_Msk
12457 
12458 /********************  Bits definition for RTC_BKP12R register  ***************/
12459 #define RTC_BKP12R_Pos                 (0U)
12460 #define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */
12461 #define RTC_BKP12R                     RTC_BKP12R_Msk
12462 
12463 /********************  Bits definition for RTC_BKP13R register  ***************/
12464 #define RTC_BKP13R_Pos                 (0U)
12465 #define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */
12466 #define RTC_BKP13R                     RTC_BKP13R_Msk
12467 
12468 /********************  Bits definition for RTC_BKP14R register  ***************/
12469 #define RTC_BKP14R_Pos                 (0U)
12470 #define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */
12471 #define RTC_BKP14R                     RTC_BKP14R_Msk
12472 
12473 /********************  Bits definition for RTC_BKP15R register  ***************/
12474 #define RTC_BKP15R_Pos                 (0U)
12475 #define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */
12476 #define RTC_BKP15R                     RTC_BKP15R_Msk
12477 
12478 /********************  Bits definition for RTC_BKP16R register  ***************/
12479 #define RTC_BKP16R_Pos                 (0U)
12480 #define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */
12481 #define RTC_BKP16R                     RTC_BKP16R_Msk
12482 
12483 /********************  Bits definition for RTC_BKP17R register  ***************/
12484 #define RTC_BKP17R_Pos                 (0U)
12485 #define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */
12486 #define RTC_BKP17R                     RTC_BKP17R_Msk
12487 
12488 /********************  Bits definition for RTC_BKP18R register  ***************/
12489 #define RTC_BKP18R_Pos                 (0U)
12490 #define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */
12491 #define RTC_BKP18R                     RTC_BKP18R_Msk
12492 
12493 /********************  Bits definition for RTC_BKP19R register  ***************/
12494 #define RTC_BKP19R_Pos                 (0U)
12495 #define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */
12496 #define RTC_BKP19R                     RTC_BKP19R_Msk
12497 
12498 /********************  Bits definition for RTC_BKP20R register  ***************/
12499 #define RTC_BKP20R_Pos                 (0U)
12500 #define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */
12501 #define RTC_BKP20R                     RTC_BKP20R_Msk
12502 
12503 /********************  Bits definition for RTC_BKP21R register  ***************/
12504 #define RTC_BKP21R_Pos                 (0U)
12505 #define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */
12506 #define RTC_BKP21R                     RTC_BKP21R_Msk
12507 
12508 /********************  Bits definition for RTC_BKP22R register  ***************/
12509 #define RTC_BKP22R_Pos                 (0U)
12510 #define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */
12511 #define RTC_BKP22R                     RTC_BKP22R_Msk
12512 
12513 /********************  Bits definition for RTC_BKP23R register  ***************/
12514 #define RTC_BKP23R_Pos                 (0U)
12515 #define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */
12516 #define RTC_BKP23R                     RTC_BKP23R_Msk
12517 
12518 /********************  Bits definition for RTC_BKP24R register  ***************/
12519 #define RTC_BKP24R_Pos                 (0U)
12520 #define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */
12521 #define RTC_BKP24R                     RTC_BKP24R_Msk
12522 
12523 /********************  Bits definition for RTC_BKP25R register  ***************/
12524 #define RTC_BKP25R_Pos                 (0U)
12525 #define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */
12526 #define RTC_BKP25R                     RTC_BKP25R_Msk
12527 
12528 /********************  Bits definition for RTC_BKP26R register  ***************/
12529 #define RTC_BKP26R_Pos                 (0U)
12530 #define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */
12531 #define RTC_BKP26R                     RTC_BKP26R_Msk
12532 
12533 /********************  Bits definition for RTC_BKP27R register  ***************/
12534 #define RTC_BKP27R_Pos                 (0U)
12535 #define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */
12536 #define RTC_BKP27R                     RTC_BKP27R_Msk
12537 
12538 /********************  Bits definition for RTC_BKP28R register  ***************/
12539 #define RTC_BKP28R_Pos                 (0U)
12540 #define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */
12541 #define RTC_BKP28R                     RTC_BKP28R_Msk
12542 
12543 /********************  Bits definition for RTC_BKP29R register  ***************/
12544 #define RTC_BKP29R_Pos                 (0U)
12545 #define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */
12546 #define RTC_BKP29R                     RTC_BKP29R_Msk
12547 
12548 /********************  Bits definition for RTC_BKP30R register  ***************/
12549 #define RTC_BKP30R_Pos                 (0U)
12550 #define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */
12551 #define RTC_BKP30R                     RTC_BKP30R_Msk
12552 
12553 /********************  Bits definition for RTC_BKP31R register  ***************/
12554 #define RTC_BKP31R_Pos                 (0U)
12555 #define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */
12556 #define RTC_BKP31R                     RTC_BKP31R_Msk
12557 
12558 /******************** Number of backup registers ******************************/
12559 #define RTC_BKP_NUMBER                 0x00000020U
12560 
12561 /******************************************************************************/
12562 /*                                                                            */
12563 /*                          Serial Audio Interface                            */
12564 /*                                                                            */
12565 /******************************************************************************/
12566 /********************  Bit definition for SAI_GCR register  *******************/
12567 #define SAI_GCR_SYNCIN_Pos         (0U)
12568 #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
12569 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
12570 #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
12571 #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
12572 
12573 #define SAI_GCR_SYNCOUT_Pos        (4U)
12574 #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
12575 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
12576 #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
12577 #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
12578 
12579 /*******************  Bit definition for SAI_xCR1 register  *******************/
12580 #define SAI_xCR1_MODE_Pos          (0U)
12581 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
12582 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
12583 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
12584 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
12585 
12586 #define SAI_xCR1_PRTCFG_Pos        (2U)
12587 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
12588 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
12589 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
12590 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
12591 
12592 #define SAI_xCR1_DS_Pos            (5U)
12593 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
12594 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
12595 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
12596 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
12597 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
12598 
12599 #define SAI_xCR1_LSBFIRST_Pos      (8U)
12600 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
12601 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
12602 #define SAI_xCR1_CKSTR_Pos         (9U)
12603 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
12604 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
12605 
12606 #define SAI_xCR1_SYNCEN_Pos        (10U)
12607 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
12608 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
12609 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
12610 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
12611 
12612 #define SAI_xCR1_MONO_Pos          (12U)
12613 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
12614 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
12615 #define SAI_xCR1_OUTDRIV_Pos       (13U)
12616 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
12617 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
12618 #define SAI_xCR1_SAIEN_Pos         (16U)
12619 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
12620 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
12621 #define SAI_xCR1_DMAEN_Pos         (17U)
12622 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
12623 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
12624 #define SAI_xCR1_NODIV_Pos         (19U)
12625 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
12626 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
12627 
12628 #define SAI_xCR1_MCKDIV_Pos        (20U)
12629 #define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
12630 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
12631 #define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */
12632 #define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */
12633 #define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */
12634 #define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */
12635 
12636 /*******************  Bit definition for SAI_xCR2 register  *******************/
12637 #define SAI_xCR2_FTH_Pos           (0U)
12638 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
12639 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
12640 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
12641 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
12642 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
12643 
12644 #define SAI_xCR2_FFLUSH_Pos        (3U)
12645 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
12646 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
12647 #define SAI_xCR2_TRIS_Pos          (4U)
12648 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
12649 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
12650 #define SAI_xCR2_MUTE_Pos          (5U)
12651 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
12652 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
12653 #define SAI_xCR2_MUTEVAL_Pos       (6U)
12654 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
12655 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
12656 
12657 #define SAI_xCR2_MUTECNT_Pos       (7U)
12658 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
12659 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
12660 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
12661 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
12662 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
12663 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
12664 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
12665 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
12666 
12667 #define SAI_xCR2_CPL_Pos           (13U)
12668 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
12669 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
12670 
12671 #define SAI_xCR2_COMP_Pos          (14U)
12672 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
12673 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
12674 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
12675 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
12676 
12677 /******************  Bit definition for SAI_xFRCR register  *******************/
12678 #define SAI_xFRCR_FRL_Pos          (0U)
12679 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
12680 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
12681 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
12682 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
12683 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
12684 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
12685 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
12686 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
12687 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
12688 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
12689 
12690 #define SAI_xFRCR_FSALL_Pos        (8U)
12691 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
12692 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
12693 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
12694 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
12695 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
12696 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
12697 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
12698 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
12699 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
12700 
12701 #define SAI_xFRCR_FSDEF_Pos        (16U)
12702 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
12703 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
12704 #define SAI_xFRCR_FSPOL_Pos        (17U)
12705 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
12706 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
12707 #define SAI_xFRCR_FSOFF_Pos        (18U)
12708 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
12709 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
12710 
12711 /* Legacy define */
12712 #define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
12713 
12714 /******************  Bit definition for SAI_xSLOTR register  *******************/
12715 #define SAI_xSLOTR_FBOFF_Pos       (0U)
12716 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
12717 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
12718 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
12719 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
12720 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
12721 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
12722 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
12723 
12724 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
12725 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
12726 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
12727 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
12728 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
12729 
12730 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
12731 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
12732 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
12733 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
12734 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
12735 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
12736 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
12737 
12738 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
12739 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
12740 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
12741 
12742 /*******************  Bit definition for SAI_xIMR register  *******************/
12743 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
12744 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
12745 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
12746 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
12747 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
12748 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
12749 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
12750 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
12751 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
12752 #define SAI_xIMR_FREQIE_Pos        (3U)
12753 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
12754 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
12755 #define SAI_xIMR_CNRDYIE_Pos       (4U)
12756 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
12757 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
12758 #define SAI_xIMR_AFSDETIE_Pos      (5U)
12759 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
12760 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
12761 #define SAI_xIMR_LFSDETIE_Pos      (6U)
12762 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
12763 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
12764 
12765 /********************  Bit definition for SAI_xSR register  *******************/
12766 #define SAI_xSR_OVRUDR_Pos         (0U)
12767 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
12768 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
12769 #define SAI_xSR_MUTEDET_Pos        (1U)
12770 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
12771 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
12772 #define SAI_xSR_WCKCFG_Pos         (2U)
12773 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
12774 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
12775 #define SAI_xSR_FREQ_Pos           (3U)
12776 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
12777 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
12778 #define SAI_xSR_CNRDY_Pos          (4U)
12779 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
12780 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
12781 #define SAI_xSR_AFSDET_Pos         (5U)
12782 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
12783 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
12784 #define SAI_xSR_LFSDET_Pos         (6U)
12785 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
12786 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
12787 
12788 #define SAI_xSR_FLVL_Pos           (16U)
12789 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
12790 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
12791 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
12792 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
12793 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
12794 
12795 /******************  Bit definition for SAI_xCLRFR register  ******************/
12796 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
12797 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
12798 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
12799 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
12800 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
12801 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
12802 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
12803 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
12804 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
12805 #define SAI_xCLRFR_CFREQ_Pos       (3U)
12806 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
12807 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
12808 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
12809 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
12810 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
12811 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
12812 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
12813 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
12814 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
12815 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
12816 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
12817 
12818 /******************  Bit definition for SAI_xDR register  *********************/
12819 #define SAI_xDR_DATA_Pos           (0U)
12820 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
12821 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
12822 
12823 /******************************************************************************/
12824 /*                                                                            */
12825 /*                              SPDIF-RX Interface                            */
12826 /*                                                                            */
12827 /******************************************************************************/
12828 /********************  Bit definition for SPDIF_CR register  *******************/
12829 #define SPDIFRX_CR_SPDIFEN_Pos      (0U)
12830 #define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)           /*!< 0x00000003 */
12831 #define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
12832 #define SPDIFRX_CR_RXDMAEN_Pos      (2U)
12833 #define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)           /*!< 0x00000004 */
12834 #define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
12835 #define SPDIFRX_CR_RXSTEO_Pos       (3U)
12836 #define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)            /*!< 0x00000008 */
12837 #define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
12838 #define SPDIFRX_CR_DRFMT_Pos        (4U)
12839 #define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)             /*!< 0x00000030 */
12840 #define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
12841 #define SPDIFRX_CR_PMSK_Pos         (6U)
12842 #define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)              /*!< 0x00000040 */
12843 #define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
12844 #define SPDIFRX_CR_VMSK_Pos         (7U)
12845 #define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)              /*!< 0x00000080 */
12846 #define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
12847 #define SPDIFRX_CR_CUMSK_Pos        (8U)
12848 #define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)             /*!< 0x00000100 */
12849 #define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
12850 #define SPDIFRX_CR_PTMSK_Pos        (9U)
12851 #define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)             /*!< 0x00000200 */
12852 #define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
12853 #define SPDIFRX_CR_CBDMAEN_Pos      (10U)
12854 #define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)           /*!< 0x00000400 */
12855 #define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
12856 #define SPDIFRX_CR_CHSEL_Pos        (11U)
12857 #define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)             /*!< 0x00000800 */
12858 #define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
12859 #define SPDIFRX_CR_NBTR_Pos         (12U)
12860 #define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)              /*!< 0x00003000 */
12861 #define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
12862 #define SPDIFRX_CR_WFA_Pos          (14U)
12863 #define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)               /*!< 0x00004000 */
12864 #define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
12865 #define SPDIFRX_CR_INSEL_Pos        (16U)
12866 #define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)             /*!< 0x00070000 */
12867 #define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
12868 
12869 /*******************  Bit definition for SPDIFRX_IMR register  *******************/
12870 #define SPDIFRX_IMR_RXNEIE_Pos      (0U)
12871 #define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)           /*!< 0x00000001 */
12872 #define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
12873 #define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
12874 #define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)          /*!< 0x00000002 */
12875 #define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
12876 #define SPDIFRX_IMR_PERRIE_Pos      (2U)
12877 #define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)           /*!< 0x00000004 */
12878 #define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
12879 #define SPDIFRX_IMR_OVRIE_Pos       (3U)
12880 #define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)            /*!< 0x00000008 */
12881 #define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
12882 #define SPDIFRX_IMR_SBLKIE_Pos      (4U)
12883 #define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)           /*!< 0x00000010 */
12884 #define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
12885 #define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
12886 #define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)          /*!< 0x00000020 */
12887 #define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
12888 #define SPDIFRX_IMR_IFEIE_Pos       (6U)
12889 #define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)            /*!< 0x00000040 */
12890 #define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
12891 
12892 /*******************  Bit definition for SPDIFRX_SR register  *******************/
12893 #define SPDIFRX_SR_RXNE_Pos         (0U)
12894 #define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)              /*!< 0x00000001 */
12895 #define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
12896 #define SPDIFRX_SR_CSRNE_Pos        (1U)
12897 #define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)             /*!< 0x00000002 */
12898 #define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
12899 #define SPDIFRX_SR_PERR_Pos         (2U)
12900 #define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)              /*!< 0x00000004 */
12901 #define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
12902 #define SPDIFRX_SR_OVR_Pos          (3U)
12903 #define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)               /*!< 0x00000008 */
12904 #define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
12905 #define SPDIFRX_SR_SBD_Pos          (4U)
12906 #define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)               /*!< 0x00000010 */
12907 #define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
12908 #define SPDIFRX_SR_SYNCD_Pos        (5U)
12909 #define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)             /*!< 0x00000020 */
12910 #define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
12911 #define SPDIFRX_SR_FERR_Pos         (6U)
12912 #define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)              /*!< 0x00000040 */
12913 #define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
12914 #define SPDIFRX_SR_SERR_Pos         (7U)
12915 #define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)              /*!< 0x00000080 */
12916 #define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
12917 #define SPDIFRX_SR_TERR_Pos         (8U)
12918 #define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)              /*!< 0x00000100 */
12919 #define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
12920 #define SPDIFRX_SR_WIDTH5_Pos       (16U)
12921 #define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)         /*!< 0x7FFF0000 */
12922 #define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
12923 
12924 /*******************  Bit definition for SPDIFRX_IFCR register  *******************/
12925 #define SPDIFRX_IFCR_PERRCF_Pos     (2U)
12926 #define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)          /*!< 0x00000004 */
12927 #define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
12928 #define SPDIFRX_IFCR_OVRCF_Pos      (3U)
12929 #define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)           /*!< 0x00000008 */
12930 #define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
12931 #define SPDIFRX_IFCR_SBDCF_Pos      (4U)
12932 #define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)           /*!< 0x00000010 */
12933 #define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
12934 #define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
12935 #define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)         /*!< 0x00000020 */
12936 #define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
12937 
12938 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
12939 #define SPDIFRX_DR0_DR_Pos          (0U)
12940 #define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)          /*!< 0x00FFFFFF */
12941 #define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
12942 #define SPDIFRX_DR0_PE_Pos          (24U)
12943 #define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)               /*!< 0x01000000 */
12944 #define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
12945 #define SPDIFRX_DR0_V_Pos           (25U)
12946 #define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)                /*!< 0x02000000 */
12947 #define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
12948 #define SPDIFRX_DR0_U_Pos           (26U)
12949 #define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)                /*!< 0x04000000 */
12950 #define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
12951 #define SPDIFRX_DR0_C_Pos           (27U)
12952 #define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)                /*!< 0x08000000 */
12953 #define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
12954 #define SPDIFRX_DR0_PT_Pos          (28U)
12955 #define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)               /*!< 0x30000000 */
12956 #define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
12957 
12958 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
12959 #define SPDIFRX_DR1_DR_Pos          (8U)
12960 #define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)          /*!< 0xFFFFFF00 */
12961 #define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
12962 #define SPDIFRX_DR1_PT_Pos          (4U)
12963 #define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)               /*!< 0x00000030 */
12964 #define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
12965 #define SPDIFRX_DR1_C_Pos           (3U)
12966 #define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)                /*!< 0x00000008 */
12967 #define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
12968 #define SPDIFRX_DR1_U_Pos           (2U)
12969 #define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)                /*!< 0x00000004 */
12970 #define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
12971 #define SPDIFRX_DR1_V_Pos           (1U)
12972 #define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)                /*!< 0x00000002 */
12973 #define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
12974 #define SPDIFRX_DR1_PE_Pos          (0U)
12975 #define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)               /*!< 0x00000001 */
12976 #define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
12977 
12978 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
12979 #define SPDIFRX_DR1_DRNL1_Pos       (16U)
12980 #define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)         /*!< 0xFFFF0000 */
12981 #define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
12982 #define SPDIFRX_DR1_DRNL2_Pos       (0U)
12983 #define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)         /*!< 0x0000FFFF */
12984 #define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
12985 
12986 /*******************  Bit definition for SPDIFRX_CSR register   *******************/
12987 #define SPDIFRX_CSR_USR_Pos         (0U)
12988 #define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)           /*!< 0x0000FFFF */
12989 #define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
12990 #define SPDIFRX_CSR_CS_Pos          (16U)
12991 #define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)              /*!< 0x00FF0000 */
12992 #define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
12993 #define SPDIFRX_CSR_SOB_Pos         (24U)
12994 #define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)              /*!< 0x01000000 */
12995 #define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
12996 
12997 /*******************  Bit definition for SPDIFRX_DIR register    *******************/
12998 #define SPDIFRX_DIR_THI_Pos         (0U)
12999 #define SPDIFRX_DIR_THI_Msk         (0x13FFUL << SPDIFRX_DIR_THI_Pos)           /*!< 0x000013FF */
13000 #define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
13001 #define SPDIFRX_DIR_TLO_Pos         (16U)
13002 #define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)           /*!< 0x1FFF0000 */
13003 #define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
13004 
13005 /******************************************************************************/
13006 /*                                                                            */
13007 /*                          SD host Interface                                 */
13008 /*                                                                            */
13009 /******************************************************************************/
13010 /******************  Bit definition for SDMMC_POWER register  ******************/
13011 #define SDMMC_POWER_PWRCTRL_Pos         (0U)
13012 #define SDMMC_POWER_PWRCTRL_Msk         (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
13013 #define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
13014 #define SDMMC_POWER_PWRCTRL_0           (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x01 */
13015 #define SDMMC_POWER_PWRCTRL_1           (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x02 */
13016 
13017 /******************  Bit definition for SDMMC_CLKCR register  ******************/
13018 #define SDMMC_CLKCR_CLKDIV_Pos          (0U)
13019 #define SDMMC_CLKCR_CLKDIV_Msk          (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */
13020 #define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
13021 #define SDMMC_CLKCR_CLKEN_Pos           (8U)
13022 #define SDMMC_CLKCR_CLKEN_Msk           (0x1UL << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */
13023 #define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */
13024 #define SDMMC_CLKCR_PWRSAV_Pos          (9U)
13025 #define SDMMC_CLKCR_PWRSAV_Msk          (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */
13026 #define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
13027 #define SDMMC_CLKCR_BYPASS_Pos          (10U)
13028 #define SDMMC_CLKCR_BYPASS_Msk          (0x1UL << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */
13029 #define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */
13030 
13031 #define SDMMC_CLKCR_WIDBUS_Pos          (11U)
13032 #define SDMMC_CLKCR_WIDBUS_Msk          (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */
13033 #define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
13034 #define SDMMC_CLKCR_WIDBUS_0            (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0800 */
13035 #define SDMMC_CLKCR_WIDBUS_1            (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x1000 */
13036 
13037 #define SDMMC_CLKCR_NEGEDGE_Pos         (13U)
13038 #define SDMMC_CLKCR_NEGEDGE_Msk         (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */
13039 #define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
13040 #define SDMMC_CLKCR_HWFC_EN_Pos         (14U)
13041 #define SDMMC_CLKCR_HWFC_EN_Msk         (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */
13042 #define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */
13043 
13044 /*******************  Bit definition for SDMMC_ARG register  *******************/
13045 #define SDMMC_ARG_CMDARG_Pos            (0U)
13046 #define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
13047 #define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
13048 
13049 /*******************  Bit definition for SDMMC_CMD register  *******************/
13050 #define SDMMC_CMD_CMDINDEX_Pos          (0U)
13051 #define SDMMC_CMD_CMDINDEX_Msk          (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
13052 #define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
13053 
13054 #define SDMMC_CMD_WAITRESP_Pos          (6U)
13055 #define SDMMC_CMD_WAITRESP_Msk          (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */
13056 #define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
13057 #define SDMMC_CMD_WAITRESP_0            (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x0040 */
13058 #define SDMMC_CMD_WAITRESP_1            (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x0080 */
13059 
13060 #define SDMMC_CMD_WAITINT_Pos           (8U)
13061 #define SDMMC_CMD_WAITINT_Msk           (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */
13062 #define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
13063 #define SDMMC_CMD_WAITPEND_Pos          (9U)
13064 #define SDMMC_CMD_WAITPEND_Msk          (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */
13065 #define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
13066 #define SDMMC_CMD_CPSMEN_Pos            (10U)
13067 #define SDMMC_CMD_CPSMEN_Msk            (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */
13068 #define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
13069 #define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)
13070 #define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */
13071 #define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */
13072 
13073 /*****************  Bit definition for SDMMC_RESPCMD register  *****************/
13074 #define SDMMC_RESPCMD_RESPCMD_Pos       (0U)
13075 #define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
13076 #define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
13077 
13078 /******************  Bit definition for SDMMC_RESP0 register  ******************/
13079 #define SDMMC_RESP0_CARDSTATUS0_Pos     (0U)
13080 #define SDMMC_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
13081 #define SDMMC_RESP0_CARDSTATUS0         SDMMC_RESP0_CARDSTATUS0_Msk            /*!<Card Status */
13082 
13083 /******************  Bit definition for SDMMC_RESP1 register  ******************/
13084 #define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)
13085 #define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
13086 #define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
13087 
13088 /******************  Bit definition for SDMMC_RESP2 register  ******************/
13089 #define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)
13090 #define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
13091 #define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
13092 
13093 /******************  Bit definition for SDMMC_RESP3 register  ******************/
13094 #define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)
13095 #define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
13096 #define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
13097 
13098 /******************  Bit definition for SDMMC_RESP4 register  ******************/
13099 #define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)
13100 #define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
13101 #define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
13102 
13103 /******************  Bit definition for SDMMC_DTIMER register  *****************/
13104 #define SDMMC_DTIMER_DATATIME_Pos       (0U)
13105 #define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
13106 #define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
13107 
13108 /******************  Bit definition for SDMMC_DLEN register  *******************/
13109 #define SDMMC_DLEN_DATALENGTH_Pos       (0U)
13110 #define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
13111 #define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
13112 
13113 /******************  Bit definition for SDMMC_DCTRL register  ******************/
13114 #define SDMMC_DCTRL_DTEN_Pos            (0U)
13115 #define SDMMC_DCTRL_DTEN_Msk            (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
13116 #define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */
13117 #define SDMMC_DCTRL_DTDIR_Pos           (1U)
13118 #define SDMMC_DCTRL_DTDIR_Msk           (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
13119 #define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */
13120 #define SDMMC_DCTRL_DTMODE_Pos          (2U)
13121 #define SDMMC_DCTRL_DTMODE_Msk          (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
13122 #define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */
13123 #define SDMMC_DCTRL_DMAEN_Pos           (3U)
13124 #define SDMMC_DCTRL_DMAEN_Msk           (0x1UL << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */
13125 #define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */
13126 
13127 #define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)
13128 #define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
13129 #define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
13130 #define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0010 */
13131 #define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0020 */
13132 #define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0040 */
13133 #define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0080 */
13134 
13135 #define SDMMC_DCTRL_RWSTART_Pos         (8U)
13136 #define SDMMC_DCTRL_RWSTART_Msk         (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
13137 #define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */
13138 #define SDMMC_DCTRL_RWSTOP_Pos          (9U)
13139 #define SDMMC_DCTRL_RWSTOP_Msk          (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
13140 #define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */
13141 #define SDMMC_DCTRL_RWMOD_Pos           (10U)
13142 #define SDMMC_DCTRL_RWMOD_Msk           (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
13143 #define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */
13144 #define SDMMC_DCTRL_SDIOEN_Pos          (11U)
13145 #define SDMMC_DCTRL_SDIOEN_Msk          (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
13146 #define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */
13147 
13148 /******************  Bit definition for SDMMC_DCOUNT register  *****************/
13149 #define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)
13150 #define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
13151 #define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
13152 
13153 /******************  Bit definition for SDMMC_STA register  ********************/
13154 #define SDMMC_STA_CCRCFAIL_Pos          (0U)
13155 #define SDMMC_STA_CCRCFAIL_Msk          (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
13156 #define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
13157 #define SDMMC_STA_DCRCFAIL_Pos          (1U)
13158 #define SDMMC_STA_DCRCFAIL_Msk          (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
13159 #define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
13160 #define SDMMC_STA_CTIMEOUT_Pos          (2U)
13161 #define SDMMC_STA_CTIMEOUT_Msk          (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
13162 #define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
13163 #define SDMMC_STA_DTIMEOUT_Pos          (3U)
13164 #define SDMMC_STA_DTIMEOUT_Msk          (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
13165 #define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
13166 #define SDMMC_STA_TXUNDERR_Pos          (4U)
13167 #define SDMMC_STA_TXUNDERR_Msk          (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
13168 #define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
13169 #define SDMMC_STA_RXOVERR_Pos           (5U)
13170 #define SDMMC_STA_RXOVERR_Msk           (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
13171 #define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
13172 #define SDMMC_STA_CMDREND_Pos           (6U)
13173 #define SDMMC_STA_CMDREND_Msk           (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
13174 #define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
13175 #define SDMMC_STA_CMDSENT_Pos           (7U)
13176 #define SDMMC_STA_CMDSENT_Msk           (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
13177 #define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
13178 #define SDMMC_STA_DATAEND_Pos           (8U)
13179 #define SDMMC_STA_DATAEND_Msk           (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
13180 #define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
13181 #define SDMMC_STA_DBCKEND_Pos           (10U)
13182 #define SDMMC_STA_DBCKEND_Msk           (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
13183 #define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
13184 #define SDMMC_STA_CMDACT_Pos            (11U)
13185 #define SDMMC_STA_CMDACT_Msk            (0x1UL << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */
13186 #define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */
13187 #define SDMMC_STA_TXACT_Pos             (12U)
13188 #define SDMMC_STA_TXACT_Msk             (0x1UL << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */
13189 #define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */
13190 #define SDMMC_STA_RXACT_Pos             (13U)
13191 #define SDMMC_STA_RXACT_Msk             (0x1UL << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */
13192 #define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */
13193 #define SDMMC_STA_TXFIFOHE_Pos          (14U)
13194 #define SDMMC_STA_TXFIFOHE_Msk          (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
13195 #define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
13196 #define SDMMC_STA_RXFIFOHF_Pos          (15U)
13197 #define SDMMC_STA_RXFIFOHF_Msk          (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
13198 #define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
13199 #define SDMMC_STA_TXFIFOF_Pos           (16U)
13200 #define SDMMC_STA_TXFIFOF_Msk           (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
13201 #define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
13202 #define SDMMC_STA_RXFIFOF_Pos           (17U)
13203 #define SDMMC_STA_RXFIFOF_Msk           (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
13204 #define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
13205 #define SDMMC_STA_TXFIFOE_Pos           (18U)
13206 #define SDMMC_STA_TXFIFOE_Msk           (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
13207 #define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
13208 #define SDMMC_STA_RXFIFOE_Pos           (19U)
13209 #define SDMMC_STA_RXFIFOE_Msk           (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
13210 #define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
13211 #define SDMMC_STA_TXDAVL_Pos            (20U)
13212 #define SDMMC_STA_TXDAVL_Msk            (0x1UL << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */
13213 #define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */
13214 #define SDMMC_STA_RXDAVL_Pos            (21U)
13215 #define SDMMC_STA_RXDAVL_Msk            (0x1UL << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */
13216 #define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */
13217 #define SDMMC_STA_SDIOIT_Pos            (22U)
13218 #define SDMMC_STA_SDIOIT_Msk            (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
13219 #define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDMMC interrupt received                       */
13220 
13221 /*******************  Bit definition for SDMMC_ICR register  *******************/
13222 #define SDMMC_ICR_CCRCFAILC_Pos         (0U)
13223 #define SDMMC_ICR_CCRCFAILC_Msk         (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
13224 #define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
13225 #define SDMMC_ICR_DCRCFAILC_Pos         (1U)
13226 #define SDMMC_ICR_DCRCFAILC_Msk         (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
13227 #define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
13228 #define SDMMC_ICR_CTIMEOUTC_Pos         (2U)
13229 #define SDMMC_ICR_CTIMEOUTC_Msk         (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
13230 #define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
13231 #define SDMMC_ICR_DTIMEOUTC_Pos         (3U)
13232 #define SDMMC_ICR_DTIMEOUTC_Msk         (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
13233 #define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
13234 #define SDMMC_ICR_TXUNDERRC_Pos         (4U)
13235 #define SDMMC_ICR_TXUNDERRC_Msk         (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
13236 #define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
13237 #define SDMMC_ICR_RXOVERRC_Pos          (5U)
13238 #define SDMMC_ICR_RXOVERRC_Msk          (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
13239 #define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
13240 #define SDMMC_ICR_CMDRENDC_Pos          (6U)
13241 #define SDMMC_ICR_CMDRENDC_Msk          (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
13242 #define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
13243 #define SDMMC_ICR_CMDSENTC_Pos          (7U)
13244 #define SDMMC_ICR_CMDSENTC_Msk          (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
13245 #define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
13246 #define SDMMC_ICR_DATAENDC_Pos          (8U)
13247 #define SDMMC_ICR_DATAENDC_Msk          (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
13248 #define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
13249 #define SDMMC_ICR_DBCKENDC_Pos          (10U)
13250 #define SDMMC_ICR_DBCKENDC_Msk          (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
13251 #define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
13252 #define SDMMC_ICR_SDIOITC_Pos           (22U)
13253 #define SDMMC_ICR_SDIOITC_Msk           (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
13254 #define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDMMCIT flag clear bit   */
13255 
13256 /******************  Bit definition for SDMMC_MASK register  *******************/
13257 #define SDMMC_MASK_CCRCFAILIE_Pos       (0U)
13258 #define SDMMC_MASK_CCRCFAILIE_Msk       (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
13259 #define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
13260 #define SDMMC_MASK_DCRCFAILIE_Pos       (1U)
13261 #define SDMMC_MASK_DCRCFAILIE_Msk       (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
13262 #define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
13263 #define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)
13264 #define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
13265 #define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
13266 #define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)
13267 #define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
13268 #define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
13269 #define SDMMC_MASK_TXUNDERRIE_Pos       (4U)
13270 #define SDMMC_MASK_TXUNDERRIE_Msk       (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
13271 #define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
13272 #define SDMMC_MASK_RXOVERRIE_Pos        (5U)
13273 #define SDMMC_MASK_RXOVERRIE_Msk        (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
13274 #define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
13275 #define SDMMC_MASK_CMDRENDIE_Pos        (6U)
13276 #define SDMMC_MASK_CMDRENDIE_Msk        (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
13277 #define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
13278 #define SDMMC_MASK_CMDSENTIE_Pos        (7U)
13279 #define SDMMC_MASK_CMDSENTIE_Msk        (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
13280 #define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
13281 #define SDMMC_MASK_DATAENDIE_Pos        (8U)
13282 #define SDMMC_MASK_DATAENDIE_Msk        (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
13283 #define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
13284 #define SDMMC_MASK_DBCKENDIE_Pos        (10U)
13285 #define SDMMC_MASK_DBCKENDIE_Msk        (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
13286 #define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
13287 #define SDMMC_MASK_CMDACTIE_Pos         (11U)
13288 #define SDMMC_MASK_CMDACTIE_Msk         (0x1UL << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */
13289 #define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */
13290 #define SDMMC_MASK_TXACTIE_Pos          (12U)
13291 #define SDMMC_MASK_TXACTIE_Msk          (0x1UL << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */
13292 #define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */
13293 #define SDMMC_MASK_RXACTIE_Pos          (13U)
13294 #define SDMMC_MASK_RXACTIE_Msk          (0x1UL << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */
13295 #define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */
13296 #define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)
13297 #define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
13298 #define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
13299 #define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)
13300 #define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
13301 #define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
13302 #define SDMMC_MASK_TXFIFOFIE_Pos        (16U)
13303 #define SDMMC_MASK_TXFIFOFIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */
13304 #define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */
13305 #define SDMMC_MASK_RXFIFOFIE_Pos        (17U)
13306 #define SDMMC_MASK_RXFIFOFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
13307 #define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
13308 #define SDMMC_MASK_TXFIFOEIE_Pos        (18U)
13309 #define SDMMC_MASK_TXFIFOEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
13310 #define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
13311 #define SDMMC_MASK_RXFIFOEIE_Pos        (19U)
13312 #define SDMMC_MASK_RXFIFOEIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */
13313 #define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */
13314 #define SDMMC_MASK_TXDAVLIE_Pos         (20U)
13315 #define SDMMC_MASK_TXDAVLIE_Msk         (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */
13316 #define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */
13317 #define SDMMC_MASK_RXDAVLIE_Pos         (21U)
13318 #define SDMMC_MASK_RXDAVLIE_Msk         (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */
13319 #define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */
13320 #define SDMMC_MASK_SDIOITIE_Pos         (22U)
13321 #define SDMMC_MASK_SDIOITIE_Msk         (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
13322 #define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */
13323 
13324 /*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
13325 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)
13326 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
13327 #define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
13328 
13329 /******************  Bit definition for SDMMC_FIFO register  *******************/
13330 #define SDMMC_FIFO_FIFODATA_Pos         (0U)
13331 #define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
13332 #define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
13333 
13334 /******************************************************************************/
13335 /*                                                                            */
13336 /*                        Serial Peripheral Interface (SPI)                   */
13337 /*                                                                            */
13338 /******************************************************************************/
13339 /*******************  Bit definition for SPI_CR1 register  ********************/
13340 #define SPI_CR1_CPHA_Pos            (0U)
13341 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
13342 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase                        */
13343 #define SPI_CR1_CPOL_Pos            (1U)
13344 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
13345 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity                     */
13346 #define SPI_CR1_MSTR_Pos            (2U)
13347 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
13348 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection                   */
13349 #define SPI_CR1_BR_Pos              (3U)
13350 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
13351 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control)   */
13352 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
13353 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
13354 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
13355 #define SPI_CR1_SPE_Pos             (6U)
13356 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
13357 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable                          */
13358 #define SPI_CR1_LSBFIRST_Pos        (7U)
13359 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
13360 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format                        */
13361 #define SPI_CR1_SSI_Pos             (8U)
13362 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
13363 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select               */
13364 #define SPI_CR1_SSM_Pos             (9U)
13365 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
13366 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management           */
13367 #define SPI_CR1_RXONLY_Pos          (10U)
13368 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
13369 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only                        */
13370 #define SPI_CR1_CRCL_Pos            (11U)
13371 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                 /*!< 0x00000800 */
13372 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length                          */
13373 #define SPI_CR1_CRCNEXT_Pos         (12U)
13374 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
13375 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next                   */
13376 #define SPI_CR1_CRCEN_Pos           (13U)
13377 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
13378 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable     */
13379 #define SPI_CR1_BIDIOE_Pos          (14U)
13380 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
13381 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
13382 #define SPI_CR1_BIDIMODE_Pos        (15U)
13383 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
13384 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable      */
13385 
13386 /*******************  Bit definition for SPI_CR2 register  ********************/
13387 #define SPI_CR2_RXDMAEN_Pos         (0U)
13388 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
13389 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable                 */
13390 #define SPI_CR2_TXDMAEN_Pos         (1U)
13391 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
13392 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable                 */
13393 #define SPI_CR2_SSOE_Pos            (2U)
13394 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
13395 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable                     */
13396 #define SPI_CR2_NSSP_Pos            (3U)
13397 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                 /*!< 0x00000008 */
13398 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable          */
13399 #define SPI_CR2_FRF_Pos             (4U)
13400 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
13401 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable                  */
13402 #define SPI_CR2_ERRIE_Pos           (5U)
13403 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
13404 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable               */
13405 #define SPI_CR2_RXNEIE_Pos          (6U)
13406 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
13407 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
13408 #define SPI_CR2_TXEIE_Pos           (7U)
13409 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
13410 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable     */
13411 #define SPI_CR2_DS_Pos              (8U)
13412 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                   /*!< 0x00000F00 */
13413 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size                    */
13414 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                   /*!< 0x00000100 */
13415 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                   /*!< 0x00000200 */
13416 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                   /*!< 0x00000400 */
13417 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                   /*!< 0x00000800 */
13418 #define SPI_CR2_FRXTH_Pos           (12U)
13419 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)                /*!< 0x00001000 */
13420 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold           */
13421 #define SPI_CR2_LDMARX_Pos          (13U)
13422 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)               /*!< 0x00002000 */
13423 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception    */
13424 #define SPI_CR2_LDMATX_Pos          (14U)
13425 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)               /*!< 0x00004000 */
13426 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
13427 
13428 /********************  Bit definition for SPI_SR register  ********************/
13429 #define SPI_SR_RXNE_Pos             (0U)
13430 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
13431 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty  */
13432 #define SPI_SR_TXE_Pos              (1U)
13433 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
13434 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty     */
13435 #define SPI_SR_CHSIDE_Pos           (2U)
13436 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
13437 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side              */
13438 #define SPI_SR_UDR_Pos              (3U)
13439 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
13440 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag             */
13441 #define SPI_SR_CRCERR_Pos           (4U)
13442 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
13443 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag            */
13444 #define SPI_SR_MODF_Pos             (5U)
13445 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
13446 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault                */
13447 #define SPI_SR_OVR_Pos              (6U)
13448 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
13449 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag              */
13450 #define SPI_SR_BSY_Pos              (7U)
13451 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
13452 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag                 */
13453 #define SPI_SR_FRE_Pos              (8U)
13454 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
13455 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error     */
13456 #define SPI_SR_FRLVL_Pos            (9U)
13457 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000600 */
13458 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level      */
13459 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000200 */
13460 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000400 */
13461 #define SPI_SR_FTLVL_Pos            (11U)
13462 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001800 */
13463 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level   */
13464 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00000800 */
13465 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001000 */
13466 
13467 /********************  Bit definition for SPI_DR register  ********************/
13468 #define SPI_DR_DR_Pos               (0U)
13469 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
13470 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
13471 
13472 /*******************  Bit definition for SPI_CRCPR register  ******************/
13473 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
13474 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
13475 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
13476 
13477 /******************  Bit definition for SPI_RXCRCR register  ******************/
13478 #define SPI_RXCRCR_RXCRC_Pos        (0U)
13479 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
13480 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
13481 
13482 /******************  Bit definition for SPI_TXCRCR register  ******************/
13483 #define SPI_TXCRCR_TXCRC_Pos        (0U)
13484 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
13485 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
13486 
13487 /******************  Bit definition for SPI_I2SCFGR register  *****************/
13488 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
13489 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
13490 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
13491 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
13492 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
13493 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
13494 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
13495 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
13496 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
13497 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
13498 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity                       */
13499 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
13500 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
13501 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection)         */
13502 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
13503 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
13504 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
13505 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
13506 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
13507 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
13508 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
13509 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode)         */
13510 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
13511 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
13512 #define SPI_I2SCFGR_I2SE_Pos        (10U)
13513 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
13514 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable                                        */
13515 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
13516 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
13517 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection                                */
13518 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
13519 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
13520 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable                        */
13521 
13522 /******************  Bit definition for SPI_I2SPR register  *******************/
13523 #define SPI_I2SPR_I2SDIV_Pos        (0U)
13524 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
13525 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
13526 #define SPI_I2SPR_ODD_Pos           (8U)
13527 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
13528 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
13529 #define SPI_I2SPR_MCKOE_Pos         (9U)
13530 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
13531 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
13532 
13533 
13534 /******************************************************************************/
13535 /*                                                                            */
13536 /*                                 SYSCFG                                     */
13537 /*                                                                            */
13538 /******************************************************************************/
13539 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
13540 #define SYSCFG_MEMRMP_MEM_BOOT_Pos      (0U)
13541 #define SYSCFG_MEMRMP_MEM_BOOT_Msk      (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos)   /*!< 0x00000001 */
13542 #define SYSCFG_MEMRMP_MEM_BOOT          SYSCFG_MEMRMP_MEM_BOOT_Msk             /*!< Boot information after Reset */
13543 
13544 
13545 #define SYSCFG_MEMRMP_SWP_FMC_Pos       (10U)
13546 #define SYSCFG_MEMRMP_SWP_FMC_Msk       (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)    /*!< 0x00000C00 */
13547 #define SYSCFG_MEMRMP_SWP_FMC           SYSCFG_MEMRMP_SWP_FMC_Msk              /*!< FMC Memory Mapping swapping */
13548 #define SYSCFG_MEMRMP_SWP_FMC_0         (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)    /*!< 0x00000400 */
13549 #define SYSCFG_MEMRMP_SWP_FMC_1         (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos)    /*!< 0x00000800 */
13550 
13551 /******************  Bit definition for SYSCFG_PMC register  ******************/
13552 #define SYSCFG_PMC_I2C1_FMP_Pos         (0U)
13553 #define SYSCFG_PMC_I2C1_FMP_Msk         (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos)      /*!< 0x00000001 */
13554 #define SYSCFG_PMC_I2C1_FMP             SYSCFG_PMC_I2C1_FMP_Msk                /*!< I2C1_FMP I2C1 Fast Mode + Enable */
13555 #define SYSCFG_PMC_I2C2_FMP_Pos         (1U)
13556 #define SYSCFG_PMC_I2C2_FMP_Msk         (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos)      /*!< 0x00000002 */
13557 #define SYSCFG_PMC_I2C2_FMP             SYSCFG_PMC_I2C2_FMP_Msk                /*!< I2C2_FMP I2C2 Fast Mode + Enable */
13558 #define SYSCFG_PMC_I2C3_FMP_Pos         (2U)
13559 #define SYSCFG_PMC_I2C3_FMP_Msk         (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos)      /*!< 0x00000004 */
13560 #define SYSCFG_PMC_I2C3_FMP             SYSCFG_PMC_I2C3_FMP_Msk                /*!< I2C3_FMP I2C3 Fast Mode + Enable */
13561 #define SYSCFG_PMC_I2C4_FMP_Pos         (3U)
13562 #define SYSCFG_PMC_I2C4_FMP_Msk         (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos)      /*!< 0x00000008 */
13563 #define SYSCFG_PMC_I2C4_FMP             SYSCFG_PMC_I2C4_FMP_Msk                /*!< I2C4_FMP I2C4 Fast Mode + Enable */
13564 #define SYSCFG_PMC_I2C_PB6_FMP_Pos      (4U)
13565 #define SYSCFG_PMC_I2C_PB6_FMP_Msk      (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos)   /*!< 0x00000010 */
13566 #define SYSCFG_PMC_I2C_PB6_FMP          SYSCFG_PMC_I2C_PB6_FMP_Msk             /*!< PB6_FMP Fast Mode + Enable */
13567 #define SYSCFG_PMC_I2C_PB7_FMP_Pos      (5U)
13568 #define SYSCFG_PMC_I2C_PB7_FMP_Msk      (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos)   /*!< 0x00000020 */
13569 #define SYSCFG_PMC_I2C_PB7_FMP          SYSCFG_PMC_I2C_PB7_FMP_Msk             /*!< PB7_FMP Fast Mode + Enable */
13570 #define SYSCFG_PMC_I2C_PB8_FMP_Pos      (6U)
13571 #define SYSCFG_PMC_I2C_PB8_FMP_Msk      (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos)   /*!< 0x00000040 */
13572 #define SYSCFG_PMC_I2C_PB8_FMP          SYSCFG_PMC_I2C_PB8_FMP_Msk             /*!< PB8_FMP Fast Mode + Enable */
13573 #define SYSCFG_PMC_I2C_PB9_FMP_Pos      (7U)
13574 #define SYSCFG_PMC_I2C_PB9_FMP_Msk      (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos)   /*!< 0x00000080 */
13575 #define SYSCFG_PMC_I2C_PB9_FMP          SYSCFG_PMC_I2C_PB9_FMP_Msk             /*!< PB9_FMP Fast Mode + Enable */
13576 
13577 #define SYSCFG_PMC_ADCxDC2_Pos          (16U)
13578 #define SYSCFG_PMC_ADCxDC2_Msk          (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)       /*!< 0x00070000 */
13579 #define SYSCFG_PMC_ADCxDC2              SYSCFG_PMC_ADCxDC2_Msk                 /*!< Refer to AN4073 on how to use this bit  */
13580 #define SYSCFG_PMC_ADC1DC2_Pos          (16U)
13581 #define SYSCFG_PMC_ADC1DC2_Msk          (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)       /*!< 0x00010000 */
13582 #define SYSCFG_PMC_ADC1DC2              SYSCFG_PMC_ADC1DC2_Msk                 /*!< Refer to AN4073 on how to use this bit  */
13583 #define SYSCFG_PMC_ADC2DC2_Pos          (17U)
13584 #define SYSCFG_PMC_ADC2DC2_Msk          (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)       /*!< 0x00020000 */
13585 #define SYSCFG_PMC_ADC2DC2              SYSCFG_PMC_ADC2DC2_Msk                 /*!< Refer to AN4073 on how to use this bit  */
13586 #define SYSCFG_PMC_ADC3DC2_Pos          (18U)
13587 #define SYSCFG_PMC_ADC3DC2_Msk          (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)       /*!< 0x00040000 */
13588 #define SYSCFG_PMC_ADC3DC2              SYSCFG_PMC_ADC3DC2_Msk                 /*!< Refer to AN4073 on how to use this bit  */
13589 
13590 #define SYSCFG_PMC_MII_RMII_SEL_Pos     (23U)
13591 #define SYSCFG_PMC_MII_RMII_SEL_Msk     (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)  /*!< 0x00800000 */
13592 #define SYSCFG_PMC_MII_RMII_SEL         SYSCFG_PMC_MII_RMII_SEL_Msk            /*!<Ethernet PHY interface selection */
13593 
13594 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
13595 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
13596 #define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
13597 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
13598 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
13599 #define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
13600 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
13601 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
13602 #define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
13603 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
13604 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
13605 #define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
13606 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
13607 /**
13608   * @brief   EXTI0 configuration
13609   */
13610 #define SYSCFG_EXTICR1_EXTI0_PA         0x0000U                                /*!<PA[0] pin */
13611 #define SYSCFG_EXTICR1_EXTI0_PB         0x0001U                                /*!<PB[0] pin */
13612 #define SYSCFG_EXTICR1_EXTI0_PC         0x0002U                                /*!<PC[0] pin */
13613 #define SYSCFG_EXTICR1_EXTI0_PD         0x0003U                                /*!<PD[0] pin */
13614 #define SYSCFG_EXTICR1_EXTI0_PE         0x0004U                                /*!<PE[0] pin */
13615 #define SYSCFG_EXTICR1_EXTI0_PF         0x0005U                                /*!<PF[0] pin */
13616 #define SYSCFG_EXTICR1_EXTI0_PG         0x0006U                                /*!<PG[0] pin */
13617 #define SYSCFG_EXTICR1_EXTI0_PH         0x0007U                                /*!<PH[0] pin */
13618 #define SYSCFG_EXTICR1_EXTI0_PI         0x0008U                                /*!<PI[0] pin */
13619 #define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U                                /*!<PJ[0] pin */
13620 #define SYSCFG_EXTICR1_EXTI0_PK         0x000AU                                /*!<PK[0] pin */
13621 
13622 /**
13623   * @brief   EXTI1 configuration
13624   */
13625 #define SYSCFG_EXTICR1_EXTI1_PA         0x0000U                                /*!<PA[1] pin */
13626 #define SYSCFG_EXTICR1_EXTI1_PB         0x0010U                                /*!<PB[1] pin */
13627 #define SYSCFG_EXTICR1_EXTI1_PC         0x0020U                                /*!<PC[1] pin */
13628 #define SYSCFG_EXTICR1_EXTI1_PD         0x0030U                                /*!<PD[1] pin */
13629 #define SYSCFG_EXTICR1_EXTI1_PE         0x0040U                                /*!<PE[1] pin */
13630 #define SYSCFG_EXTICR1_EXTI1_PF         0x0050U                                /*!<PF[1] pin */
13631 #define SYSCFG_EXTICR1_EXTI1_PG         0x0060U                                /*!<PG[1] pin */
13632 #define SYSCFG_EXTICR1_EXTI1_PH         0x0070U                                /*!<PH[1] pin */
13633 #define SYSCFG_EXTICR1_EXTI1_PI         0x0080U                                /*!<PI[1] pin */
13634 #define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U                                /*!<PJ[1] pin */
13635 #define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U                                /*!<PK[1] pin */
13636 
13637 /**
13638   * @brief   EXTI2 configuration
13639   */
13640 #define SYSCFG_EXTICR1_EXTI2_PA         0x0000U                                /*!<PA[2] pin */
13641 #define SYSCFG_EXTICR1_EXTI2_PB         0x0100U                                /*!<PB[2] pin */
13642 #define SYSCFG_EXTICR1_EXTI2_PC         0x0200U                                /*!<PC[2] pin */
13643 #define SYSCFG_EXTICR1_EXTI2_PD         0x0300U                                /*!<PD[2] pin */
13644 #define SYSCFG_EXTICR1_EXTI2_PE         0x0400U                                /*!<PE[2] pin */
13645 #define SYSCFG_EXTICR1_EXTI2_PF         0x0500U                                /*!<PF[2] pin */
13646 #define SYSCFG_EXTICR1_EXTI2_PG         0x0600U                                /*!<PG[2] pin */
13647 #define SYSCFG_EXTICR1_EXTI2_PH         0x0700U                                /*!<PH[2] pin */
13648 #define SYSCFG_EXTICR1_EXTI2_PI         0x0800U                                /*!<PI[2] pin */
13649 #define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U                                /*!<PJ[2] pin */
13650 #define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U                                /*!<PK[2] pin */
13651 
13652 /**
13653   * @brief   EXTI3 configuration
13654   */
13655 #define SYSCFG_EXTICR1_EXTI3_PA         0x0000U                                /*!<PA[3] pin */
13656 #define SYSCFG_EXTICR1_EXTI3_PB         0x1000U                                /*!<PB[3] pin */
13657 #define SYSCFG_EXTICR1_EXTI3_PC         0x2000U                                /*!<PC[3] pin */
13658 #define SYSCFG_EXTICR1_EXTI3_PD         0x3000U                                /*!<PD[3] pin */
13659 #define SYSCFG_EXTICR1_EXTI3_PE         0x4000U                                /*!<PE[3] pin */
13660 #define SYSCFG_EXTICR1_EXTI3_PF         0x5000U                                /*!<PF[3] pin */
13661 #define SYSCFG_EXTICR1_EXTI3_PG         0x6000U                                /*!<PG[3] pin */
13662 #define SYSCFG_EXTICR1_EXTI3_PH         0x7000U                                /*!<PH[3] pin */
13663 #define SYSCFG_EXTICR1_EXTI3_PI         0x8000U                                /*!<PI[3] pin */
13664 #define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U                                /*!<PJ[3] pin */
13665 #define SYSCFG_EXTICR1_EXTI3_PK         0xA000U                                /*!<PK[3] pin */
13666 
13667 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
13668 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
13669 #define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
13670 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
13671 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
13672 #define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
13673 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
13674 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
13675 #define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
13676 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
13677 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
13678 #define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
13679 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
13680 /**
13681   * @brief   EXTI4 configuration
13682   */
13683 #define SYSCFG_EXTICR2_EXTI4_PA         0x0000U                                /*!<PA[4] pin */
13684 #define SYSCFG_EXTICR2_EXTI4_PB         0x0001U                                /*!<PB[4] pin */
13685 #define SYSCFG_EXTICR2_EXTI4_PC         0x0002U                                /*!<PC[4] pin */
13686 #define SYSCFG_EXTICR2_EXTI4_PD         0x0003U                                /*!<PD[4] pin */
13687 #define SYSCFG_EXTICR2_EXTI4_PE         0x0004U                                /*!<PE[4] pin */
13688 #define SYSCFG_EXTICR2_EXTI4_PF         0x0005U                                /*!<PF[4] pin */
13689 #define SYSCFG_EXTICR2_EXTI4_PG         0x0006U                                /*!<PG[4] pin */
13690 #define SYSCFG_EXTICR2_EXTI4_PH         0x0007U                                /*!<PH[4] pin */
13691 #define SYSCFG_EXTICR2_EXTI4_PI         0x0008U                                /*!<PI[4] pin */
13692 #define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U                                /*!<PJ[4] pin */
13693 #define SYSCFG_EXTICR2_EXTI4_PK         0x000AU                                /*!<PK[4] pin */
13694 
13695 /**
13696   * @brief   EXTI5 configuration
13697   */
13698 #define SYSCFG_EXTICR2_EXTI5_PA         0x0000U                                /*!<PA[5] pin */
13699 #define SYSCFG_EXTICR2_EXTI5_PB         0x0010U                                /*!<PB[5] pin */
13700 #define SYSCFG_EXTICR2_EXTI5_PC         0x0020U                                /*!<PC[5] pin */
13701 #define SYSCFG_EXTICR2_EXTI5_PD         0x0030U                                /*!<PD[5] pin */
13702 #define SYSCFG_EXTICR2_EXTI5_PE         0x0040U                                /*!<PE[5] pin */
13703 #define SYSCFG_EXTICR2_EXTI5_PF         0x0050U                                /*!<PF[5] pin */
13704 #define SYSCFG_EXTICR2_EXTI5_PG         0x0060U                                /*!<PG[5] pin */
13705 #define SYSCFG_EXTICR2_EXTI5_PH         0x0070U                                /*!<PH[5] pin */
13706 #define SYSCFG_EXTICR2_EXTI5_PI         0x0080U                                /*!<PI[5] pin */
13707 #define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U                                /*!<PJ[5] pin */
13708 #define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U                                /*!<PK[5] pin */
13709 
13710 /**
13711   * @brief   EXTI6 configuration
13712   */
13713 #define SYSCFG_EXTICR2_EXTI6_PA         0x0000U                                /*!<PA[6] pin */
13714 #define SYSCFG_EXTICR2_EXTI6_PB         0x0100U                                /*!<PB[6] pin */
13715 #define SYSCFG_EXTICR2_EXTI6_PC         0x0200U                                /*!<PC[6] pin */
13716 #define SYSCFG_EXTICR2_EXTI6_PD         0x0300U                                /*!<PD[6] pin */
13717 #define SYSCFG_EXTICR2_EXTI6_PE         0x0400U                                /*!<PE[6] pin */
13718 #define SYSCFG_EXTICR2_EXTI6_PF         0x0500U                                /*!<PF[6] pin */
13719 #define SYSCFG_EXTICR2_EXTI6_PG         0x0600U                                /*!<PG[6] pin */
13720 #define SYSCFG_EXTICR2_EXTI6_PH         0x0700U                                /*!<PH[6] pin */
13721 #define SYSCFG_EXTICR2_EXTI6_PI         0x0800U                                /*!<PI[6] pin */
13722 #define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U                                /*!<PJ[6] pin */
13723 #define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U                                /*!<PK[6] pin */
13724 
13725 /**
13726   * @brief   EXTI7 configuration
13727   */
13728 #define SYSCFG_EXTICR2_EXTI7_PA         0x0000U                                /*!<PA[7] pin */
13729 #define SYSCFG_EXTICR2_EXTI7_PB         0x1000U                                /*!<PB[7] pin */
13730 #define SYSCFG_EXTICR2_EXTI7_PC         0x2000U                                /*!<PC[7] pin */
13731 #define SYSCFG_EXTICR2_EXTI7_PD         0x3000U                                /*!<PD[7] pin */
13732 #define SYSCFG_EXTICR2_EXTI7_PE         0x4000U                                /*!<PE[7] pin */
13733 #define SYSCFG_EXTICR2_EXTI7_PF         0x5000U                                /*!<PF[7] pin */
13734 #define SYSCFG_EXTICR2_EXTI7_PG         0x6000U                                /*!<PG[7] pin */
13735 #define SYSCFG_EXTICR2_EXTI7_PH         0x7000U                                /*!<PH[7] pin */
13736 #define SYSCFG_EXTICR2_EXTI7_PI         0x8000U                                /*!<PI[7] pin */
13737 #define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U                                /*!<PJ[7] pin */
13738 #define SYSCFG_EXTICR2_EXTI7_PK         0xA000U                                /*!<PK[7] pin */
13739 
13740 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
13741 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
13742 #define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
13743 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
13744 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
13745 #define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
13746 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
13747 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
13748 #define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
13749 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
13750 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
13751 #define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
13752 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
13753 
13754 /**
13755   * @brief   EXTI8 configuration
13756   */
13757 #define SYSCFG_EXTICR3_EXTI8_PA         0x0000U                                /*!<PA[8] pin */
13758 #define SYSCFG_EXTICR3_EXTI8_PB         0x0001U                                /*!<PB[8] pin */
13759 #define SYSCFG_EXTICR3_EXTI8_PC         0x0002U                                /*!<PC[8] pin */
13760 #define SYSCFG_EXTICR3_EXTI8_PD         0x0003U                                /*!<PD[8] pin */
13761 #define SYSCFG_EXTICR3_EXTI8_PE         0x0004U                                /*!<PE[8] pin */
13762 #define SYSCFG_EXTICR3_EXTI8_PF         0x0005U                                /*!<PF[8] pin */
13763 #define SYSCFG_EXTICR3_EXTI8_PG         0x0006U                                /*!<PG[8] pin */
13764 #define SYSCFG_EXTICR3_EXTI8_PH         0x0007U                                /*!<PH[8] pin */
13765 #define SYSCFG_EXTICR3_EXTI8_PI         0x0008U                                /*!<PI[8] pin */
13766 #define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U                                /*!<PJ[8] pin */
13767 
13768 /**
13769   * @brief   EXTI9 configuration
13770   */
13771 #define SYSCFG_EXTICR3_EXTI9_PA         0x0000U                                /*!<PA[9] pin */
13772 #define SYSCFG_EXTICR3_EXTI9_PB         0x0010U                                /*!<PB[9] pin */
13773 #define SYSCFG_EXTICR3_EXTI9_PC         0x0020U                                /*!<PC[9] pin */
13774 #define SYSCFG_EXTICR3_EXTI9_PD         0x0030U                                /*!<PD[9] pin */
13775 #define SYSCFG_EXTICR3_EXTI9_PE         0x0040U                                /*!<PE[9] pin */
13776 #define SYSCFG_EXTICR3_EXTI9_PF         0x0050U                                /*!<PF[9] pin */
13777 #define SYSCFG_EXTICR3_EXTI9_PG         0x0060U                                /*!<PG[9] pin */
13778 #define SYSCFG_EXTICR3_EXTI9_PH         0x0070U                                /*!<PH[9] pin */
13779 #define SYSCFG_EXTICR3_EXTI9_PI         0x0080U                                /*!<PI[9] pin */
13780 #define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U                                /*!<PJ[9] pin */
13781 
13782 /**
13783   * @brief   EXTI10 configuration
13784   */
13785 #define SYSCFG_EXTICR3_EXTI10_PA        0x0000U                                /*!<PA[10] pin */
13786 #define SYSCFG_EXTICR3_EXTI10_PB        0x0100U                                /*!<PB[10] pin */
13787 #define SYSCFG_EXTICR3_EXTI10_PC        0x0200U                                /*!<PC[10] pin */
13788 #define SYSCFG_EXTICR3_EXTI10_PD        0x0300U                                /*!<PD[10] pin */
13789 #define SYSCFG_EXTICR3_EXTI10_PE        0x0400U                                /*!<PE[10] pin */
13790 #define SYSCFG_EXTICR3_EXTI10_PF        0x0500U                                /*!<PF[10] pin */
13791 #define SYSCFG_EXTICR3_EXTI10_PG        0x0600U                                /*!<PG[10] pin */
13792 #define SYSCFG_EXTICR3_EXTI10_PH        0x0700U                                /*!<PH[10] pin */
13793 #define SYSCFG_EXTICR3_EXTI10_PI        0x0800U                                /*!<PI[10] pin */
13794 #define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U                                /*!<PJ[10] pin */
13795 
13796 /**
13797   * @brief   EXTI11 configuration
13798   */
13799 #define SYSCFG_EXTICR3_EXTI11_PA        0x0000U                                /*!<PA[11] pin */
13800 #define SYSCFG_EXTICR3_EXTI11_PB        0x1000U                                /*!<PB[11] pin */
13801 #define SYSCFG_EXTICR3_EXTI11_PC        0x2000U                                /*!<PC[11] pin */
13802 #define SYSCFG_EXTICR3_EXTI11_PD        0x3000U                                /*!<PD[11] pin */
13803 #define SYSCFG_EXTICR3_EXTI11_PE        0x4000U                                /*!<PE[11] pin */
13804 #define SYSCFG_EXTICR3_EXTI11_PF        0x5000U                                /*!<PF[11] pin */
13805 #define SYSCFG_EXTICR3_EXTI11_PG        0x6000U                                /*!<PG[11] pin */
13806 #define SYSCFG_EXTICR3_EXTI11_PH        0x7000U                                /*!<PH[11] pin */
13807 #define SYSCFG_EXTICR3_EXTI11_PI        0x8000U                                /*!<PI[11] pin */
13808 #define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U                                /*!<PJ[11] pin */
13809 
13810 
13811 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
13812 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
13813 #define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
13814 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
13815 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
13816 #define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
13817 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
13818 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
13819 #define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
13820 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
13821 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
13822 #define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
13823 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
13824 /**
13825   * @brief   EXTI12 configuration
13826   */
13827 #define SYSCFG_EXTICR4_EXTI12_PA        0x0000U                                /*!<PA[12] pin */
13828 #define SYSCFG_EXTICR4_EXTI12_PB        0x0001U                                /*!<PB[12] pin */
13829 #define SYSCFG_EXTICR4_EXTI12_PC        0x0002U                                /*!<PC[12] pin */
13830 #define SYSCFG_EXTICR4_EXTI12_PD        0x0003U                                /*!<PD[12] pin */
13831 #define SYSCFG_EXTICR4_EXTI12_PE        0x0004U                                /*!<PE[12] pin */
13832 #define SYSCFG_EXTICR4_EXTI12_PF        0x0005U                                /*!<PF[12] pin */
13833 #define SYSCFG_EXTICR4_EXTI12_PG        0x0006U                                /*!<PG[12] pin */
13834 #define SYSCFG_EXTICR4_EXTI12_PH        0x0007U                                /*!<PH[12] pin */
13835 #define SYSCFG_EXTICR4_EXTI12_PI        0x0008U                                /*!<PI[12] pin */
13836 #define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U                                /*!<PJ[12] pin */
13837 
13838 /**
13839   * @brief   EXTI13 configuration
13840   */
13841 #define SYSCFG_EXTICR4_EXTI13_PA        0x0000U                                /*!<PA[13] pin */
13842 #define SYSCFG_EXTICR4_EXTI13_PB        0x0010U                                /*!<PB[13] pin */
13843 #define SYSCFG_EXTICR4_EXTI13_PC        0x0020U                                /*!<PC[13] pin */
13844 #define SYSCFG_EXTICR4_EXTI13_PD        0x0030U                                /*!<PD[13] pin */
13845 #define SYSCFG_EXTICR4_EXTI13_PE        0x0040U                                /*!<PE[13] pin */
13846 #define SYSCFG_EXTICR4_EXTI13_PF        0x0050U                                /*!<PF[13] pin */
13847 #define SYSCFG_EXTICR4_EXTI13_PG        0x0060U                                /*!<PG[13] pin */
13848 #define SYSCFG_EXTICR4_EXTI13_PH        0x0070U                                /*!<PH[13] pin */
13849 #define SYSCFG_EXTICR4_EXTI13_PI        0x0080U                                /*!<PI[13] pin */
13850 #define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U                                /*!<PJ[13] pin */
13851 
13852 /**
13853   * @brief   EXTI14 configuration
13854   */
13855 #define SYSCFG_EXTICR4_EXTI14_PA        0x0000U                                /*!<PA[14] pin */
13856 #define SYSCFG_EXTICR4_EXTI14_PB        0x0100U                                /*!<PB[14] pin */
13857 #define SYSCFG_EXTICR4_EXTI14_PC        0x0200U                                /*!<PC[14] pin */
13858 #define SYSCFG_EXTICR4_EXTI14_PD        0x0300U                                /*!<PD[14] pin */
13859 #define SYSCFG_EXTICR4_EXTI14_PE        0x0400U                                /*!<PE[14] pin */
13860 #define SYSCFG_EXTICR4_EXTI14_PF        0x0500U                                /*!<PF[14] pin */
13861 #define SYSCFG_EXTICR4_EXTI14_PG        0x0600U                                /*!<PG[14] pin */
13862 #define SYSCFG_EXTICR4_EXTI14_PH        0x0700U                                /*!<PH[14] pin */
13863 #define SYSCFG_EXTICR4_EXTI14_PI        0x0800U                                /*!<PI[14] pin */
13864 #define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U                                /*!<PJ[14] pin */
13865 
13866 /**
13867   * @brief   EXTI15 configuration
13868   */
13869 #define SYSCFG_EXTICR4_EXTI15_PA        0x0000U                                /*!<PA[15] pin */
13870 #define SYSCFG_EXTICR4_EXTI15_PB        0x1000U                                /*!<PB[15] pin */
13871 #define SYSCFG_EXTICR4_EXTI15_PC        0x2000U                                /*!<PC[15] pin */
13872 #define SYSCFG_EXTICR4_EXTI15_PD        0x3000U                                /*!<PD[15] pin */
13873 #define SYSCFG_EXTICR4_EXTI15_PE        0x4000U                                /*!<PE[15] pin */
13874 #define SYSCFG_EXTICR4_EXTI15_PF        0x5000U                                /*!<PF[15] pin */
13875 #define SYSCFG_EXTICR4_EXTI15_PG        0x6000U                                /*!<PG[15] pin */
13876 #define SYSCFG_EXTICR4_EXTI15_PH        0x7000U                                /*!<PH[15] pin */
13877 #define SYSCFG_EXTICR4_EXTI15_PI        0x8000U                                /*!<PI[15] pin */
13878 #define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U                                /*!<PJ[15] pin */
13879 
13880 
13881 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
13882 #define SYSCFG_CMPCR_CMP_PD_Pos         (0U)
13883 #define SYSCFG_CMPCR_CMP_PD_Msk         (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)      /*!< 0x00000001 */
13884 #define SYSCFG_CMPCR_CMP_PD             SYSCFG_CMPCR_CMP_PD_Msk                /*!<Compensation cell power-down */
13885 #define SYSCFG_CMPCR_READY_Pos          (8U)
13886 #define SYSCFG_CMPCR_READY_Msk          (0x1UL << SYSCFG_CMPCR_READY_Pos)       /*!< 0x00000100 */
13887 #define SYSCFG_CMPCR_READY              SYSCFG_CMPCR_READY_Msk                 /*!<Compensation cell ready flag */
13888 
13889 /******************************************************************************/
13890 /*                                                                            */
13891 /*                                    TIM                                     */
13892 /*                                                                            */
13893 /******************************************************************************/
13894 /*******************  Bit definition for TIM_CR1 register  ********************/
13895 #define TIM_CR1_CEN_Pos           (0U)
13896 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
13897 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
13898 #define TIM_CR1_UDIS_Pos          (1U)
13899 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
13900 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
13901 #define TIM_CR1_URS_Pos           (2U)
13902 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
13903 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
13904 #define TIM_CR1_OPM_Pos           (3U)
13905 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
13906 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
13907 #define TIM_CR1_DIR_Pos           (4U)
13908 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
13909 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
13910 
13911 #define TIM_CR1_CMS_Pos           (5U)
13912 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
13913 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
13914 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
13915 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
13916 
13917 #define TIM_CR1_ARPE_Pos          (7U)
13918 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
13919 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
13920 
13921 #define TIM_CR1_CKD_Pos           (8U)
13922 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
13923 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
13924 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
13925 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
13926 #define TIM_CR1_UIFREMAP_Pos      (11U)
13927 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
13928 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<UIF status bit */
13929 
13930 /*******************  Bit definition for TIM_CR2 register  ********************/
13931 #define TIM_CR2_CCPC_Pos          (0U)
13932 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
13933 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
13934 #define TIM_CR2_CCUS_Pos          (2U)
13935 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
13936 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
13937 #define TIM_CR2_CCDS_Pos          (3U)
13938 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
13939 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
13940 
13941 #define TIM_CR2_OIS5_Pos          (16U)
13942 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
13943 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
13944 #define TIM_CR2_OIS6_Pos          (18U)
13945 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
13946 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
13947 
13948 #define TIM_CR2_MMS_Pos           (4U)
13949 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
13950 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
13951 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
13952 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
13953 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
13954 
13955 #define TIM_CR2_MMS2_Pos          (20U)
13956 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
13957 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
13958 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
13959 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
13960 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
13961 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
13962 
13963 #define TIM_CR2_TI1S_Pos          (7U)
13964 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
13965 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
13966 #define TIM_CR2_OIS1_Pos          (8U)
13967 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
13968 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
13969 #define TIM_CR2_OIS1N_Pos         (9U)
13970 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
13971 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
13972 #define TIM_CR2_OIS2_Pos          (10U)
13973 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
13974 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
13975 #define TIM_CR2_OIS2N_Pos         (11U)
13976 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
13977 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
13978 #define TIM_CR2_OIS3_Pos          (12U)
13979 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
13980 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
13981 #define TIM_CR2_OIS3N_Pos         (13U)
13982 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
13983 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
13984 #define TIM_CR2_OIS4_Pos          (14U)
13985 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
13986 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
13987 
13988 /*******************  Bit definition for TIM_SMCR register  *******************/
13989 #define TIM_SMCR_SMS_Pos          (0U)
13990 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
13991 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
13992 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
13993 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
13994 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
13995 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
13996 
13997 #define TIM_SMCR_TS_Pos           (4U)
13998 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
13999 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
14000 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
14001 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
14002 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
14003 
14004 #define TIM_SMCR_MSM_Pos          (7U)
14005 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
14006 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
14007 
14008 #define TIM_SMCR_ETF_Pos          (8U)
14009 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
14010 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
14011 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
14012 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
14013 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
14014 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
14015 
14016 #define TIM_SMCR_ETPS_Pos         (12U)
14017 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
14018 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
14019 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
14020 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
14021 
14022 #define TIM_SMCR_ECE_Pos          (14U)
14023 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
14024 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
14025 #define TIM_SMCR_ETP_Pos          (15U)
14026 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
14027 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
14028 
14029 /*******************  Bit definition for TIM_DIER register  *******************/
14030 #define TIM_DIER_UIE_Pos          (0U)
14031 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
14032 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
14033 #define TIM_DIER_CC1IE_Pos        (1U)
14034 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
14035 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
14036 #define TIM_DIER_CC2IE_Pos        (2U)
14037 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
14038 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
14039 #define TIM_DIER_CC3IE_Pos        (3U)
14040 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
14041 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
14042 #define TIM_DIER_CC4IE_Pos        (4U)
14043 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
14044 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
14045 #define TIM_DIER_COMIE_Pos        (5U)
14046 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
14047 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
14048 #define TIM_DIER_TIE_Pos          (6U)
14049 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
14050 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
14051 #define TIM_DIER_BIE_Pos          (7U)
14052 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
14053 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
14054 #define TIM_DIER_UDE_Pos          (8U)
14055 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
14056 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
14057 #define TIM_DIER_CC1DE_Pos        (9U)
14058 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
14059 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
14060 #define TIM_DIER_CC2DE_Pos        (10U)
14061 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
14062 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
14063 #define TIM_DIER_CC3DE_Pos        (11U)
14064 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
14065 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
14066 #define TIM_DIER_CC4DE_Pos        (12U)
14067 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
14068 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
14069 #define TIM_DIER_COMDE_Pos        (13U)
14070 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
14071 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
14072 #define TIM_DIER_TDE_Pos          (14U)
14073 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
14074 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
14075 
14076 /********************  Bit definition for TIM_SR register  ********************/
14077 #define TIM_SR_UIF_Pos            (0U)
14078 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
14079 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
14080 #define TIM_SR_CC1IF_Pos          (1U)
14081 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
14082 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
14083 #define TIM_SR_CC2IF_Pos          (2U)
14084 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
14085 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
14086 #define TIM_SR_CC3IF_Pos          (3U)
14087 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
14088 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
14089 #define TIM_SR_CC4IF_Pos          (4U)
14090 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
14091 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
14092 #define TIM_SR_COMIF_Pos          (5U)
14093 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
14094 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
14095 #define TIM_SR_TIF_Pos            (6U)
14096 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
14097 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
14098 #define TIM_SR_BIF_Pos            (7U)
14099 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
14100 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
14101 #define TIM_SR_B2IF_Pos           (8U)
14102 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
14103 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag               */
14104 #define TIM_SR_CC1OF_Pos          (9U)
14105 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
14106 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
14107 #define TIM_SR_CC2OF_Pos          (10U)
14108 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
14109 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
14110 #define TIM_SR_CC3OF_Pos          (11U)
14111 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
14112 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
14113 #define TIM_SR_CC4OF_Pos          (12U)
14114 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
14115 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
14116 #define TIM_SR_SBIF_Pos           (13U)
14117 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
14118 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
14119 #define TIM_SR_CC5IF_Pos          (16U)
14120 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
14121 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
14122 #define TIM_SR_CC6IF_Pos          (17U)
14123 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
14124 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
14125 
14126 /*******************  Bit definition for TIM_EGR register  ********************/
14127 #define TIM_EGR_UG_Pos            (0U)
14128 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
14129 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
14130 #define TIM_EGR_CC1G_Pos          (1U)
14131 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
14132 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
14133 #define TIM_EGR_CC2G_Pos          (2U)
14134 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
14135 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
14136 #define TIM_EGR_CC3G_Pos          (3U)
14137 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
14138 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
14139 #define TIM_EGR_CC4G_Pos          (4U)
14140 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
14141 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
14142 #define TIM_EGR_COMG_Pos          (5U)
14143 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
14144 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
14145 #define TIM_EGR_TG_Pos            (6U)
14146 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
14147 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
14148 #define TIM_EGR_BG_Pos            (7U)
14149 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
14150 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
14151 #define TIM_EGR_B2G_Pos           (8U)
14152 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
14153 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break2 Generation                          */
14154 
14155 /******************  Bit definition for TIM_CCMR1 register  *******************/
14156 #define TIM_CCMR1_CC1S_Pos        (0U)
14157 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
14158 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
14159 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
14160 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
14161 
14162 #define TIM_CCMR1_OC1FE_Pos       (2U)
14163 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
14164 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
14165 #define TIM_CCMR1_OC1PE_Pos       (3U)
14166 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
14167 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
14168 
14169 #define TIM_CCMR1_OC1M_Pos        (4U)
14170 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
14171 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
14172 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
14173 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
14174 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
14175 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
14176 
14177 #define TIM_CCMR1_OC1CE_Pos       (7U)
14178 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
14179 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
14180 
14181 #define TIM_CCMR1_CC2S_Pos        (8U)
14182 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
14183 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
14184 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
14185 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
14186 
14187 #define TIM_CCMR1_OC2FE_Pos       (10U)
14188 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
14189 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
14190 #define TIM_CCMR1_OC2PE_Pos       (11U)
14191 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
14192 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
14193 
14194 #define TIM_CCMR1_OC2M_Pos        (12U)
14195 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
14196 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
14197 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
14198 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
14199 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
14200 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
14201 
14202 #define TIM_CCMR1_OC2CE_Pos       (15U)
14203 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
14204 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
14205 
14206 /*----------------------------------------------------------------------------*/
14207 
14208 #define TIM_CCMR1_IC1PSC_Pos      (2U)
14209 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
14210 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
14211 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
14212 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
14213 
14214 #define TIM_CCMR1_IC1F_Pos        (4U)
14215 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
14216 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
14217 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
14218 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
14219 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
14220 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
14221 
14222 #define TIM_CCMR1_IC2PSC_Pos      (10U)
14223 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
14224 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
14225 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
14226 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
14227 
14228 #define TIM_CCMR1_IC2F_Pos        (12U)
14229 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
14230 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
14231 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
14232 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
14233 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
14234 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
14235 
14236 /******************  Bit definition for TIM_CCMR2 register  *******************/
14237 #define TIM_CCMR2_CC3S_Pos        (0U)
14238 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
14239 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
14240 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
14241 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
14242 
14243 #define TIM_CCMR2_OC3FE_Pos       (2U)
14244 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
14245 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
14246 #define TIM_CCMR2_OC3PE_Pos       (3U)
14247 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
14248 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
14249 
14250 #define TIM_CCMR2_OC3M_Pos        (4U)
14251 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
14252 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
14253 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
14254 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
14255 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
14256 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
14257 
14258 
14259 
14260 #define TIM_CCMR2_OC3CE_Pos       (7U)
14261 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
14262 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
14263 
14264 #define TIM_CCMR2_CC4S_Pos        (8U)
14265 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
14266 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
14267 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
14268 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
14269 
14270 #define TIM_CCMR2_OC4FE_Pos       (10U)
14271 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
14272 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
14273 #define TIM_CCMR2_OC4PE_Pos       (11U)
14274 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
14275 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
14276 
14277 #define TIM_CCMR2_OC4M_Pos        (12U)
14278 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
14279 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
14280 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
14281 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
14282 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
14283 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
14284 
14285 #define TIM_CCMR2_OC4CE_Pos       (15U)
14286 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
14287 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
14288 
14289 /*----------------------------------------------------------------------------*/
14290 
14291 #define TIM_CCMR2_IC3PSC_Pos      (2U)
14292 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
14293 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
14294 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
14295 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
14296 
14297 #define TIM_CCMR2_IC3F_Pos        (4U)
14298 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
14299 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
14300 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
14301 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
14302 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
14303 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
14304 
14305 #define TIM_CCMR2_IC4PSC_Pos      (10U)
14306 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
14307 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
14308 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
14309 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
14310 
14311 #define TIM_CCMR2_IC4F_Pos        (12U)
14312 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
14313 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
14314 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
14315 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
14316 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
14317 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
14318 
14319 /*******************  Bit definition for TIM_CCER register  *******************/
14320 #define TIM_CCER_CC1E_Pos         (0U)
14321 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
14322 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
14323 #define TIM_CCER_CC1P_Pos         (1U)
14324 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
14325 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
14326 #define TIM_CCER_CC1NE_Pos        (2U)
14327 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
14328 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
14329 #define TIM_CCER_CC1NP_Pos        (3U)
14330 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
14331 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
14332 #define TIM_CCER_CC2E_Pos         (4U)
14333 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
14334 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
14335 #define TIM_CCER_CC2P_Pos         (5U)
14336 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
14337 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
14338 #define TIM_CCER_CC2NE_Pos        (6U)
14339 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
14340 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
14341 #define TIM_CCER_CC2NP_Pos        (7U)
14342 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
14343 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
14344 #define TIM_CCER_CC3E_Pos         (8U)
14345 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
14346 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
14347 #define TIM_CCER_CC3P_Pos         (9U)
14348 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
14349 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
14350 #define TIM_CCER_CC3NE_Pos        (10U)
14351 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
14352 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
14353 #define TIM_CCER_CC3NP_Pos        (11U)
14354 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
14355 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
14356 #define TIM_CCER_CC4E_Pos         (12U)
14357 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
14358 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
14359 #define TIM_CCER_CC4P_Pos         (13U)
14360 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
14361 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
14362 #define TIM_CCER_CC4NP_Pos        (15U)
14363 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
14364 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
14365 #define TIM_CCER_CC5E_Pos         (16U)
14366 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
14367 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
14368 #define TIM_CCER_CC5P_Pos         (17U)
14369 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
14370 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
14371 #define TIM_CCER_CC6E_Pos         (20U)
14372 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
14373 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
14374 #define TIM_CCER_CC6P_Pos         (21U)
14375 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
14376 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
14377 
14378 
14379 /*******************  Bit definition for TIM_CNT register  ********************/
14380 #define TIM_CNT_CNT_Pos           (0U)
14381 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
14382 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value            */
14383 #define TIM_CNT_UIFCPY_Pos        (31U)
14384 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
14385 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
14386 
14387 /*******************  Bit definition for TIM_PSC register  ********************/
14388 #define TIM_PSC_PSC_Pos           (0U)
14389 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
14390 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
14391 
14392 /*******************  Bit definition for TIM_ARR register  ********************/
14393 #define TIM_ARR_ARR_Pos           (0U)
14394 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
14395 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
14396 
14397 /*******************  Bit definition for TIM_RCR register  ********************/
14398 #define TIM_RCR_REP_Pos           (0U)
14399 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
14400 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
14401 
14402 /*******************  Bit definition for TIM_CCR1 register  *******************/
14403 #define TIM_CCR1_CCR1_Pos         (0U)
14404 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
14405 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
14406 
14407 /*******************  Bit definition for TIM_CCR2 register  *******************/
14408 #define TIM_CCR2_CCR2_Pos         (0U)
14409 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
14410 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
14411 
14412 /*******************  Bit definition for TIM_CCR3 register  *******************/
14413 #define TIM_CCR3_CCR3_Pos         (0U)
14414 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
14415 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
14416 
14417 /*******************  Bit definition for TIM_CCR4 register  *******************/
14418 #define TIM_CCR4_CCR4_Pos         (0U)
14419 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
14420 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
14421 
14422 /*******************  Bit definition for TIM_BDTR register  *******************/
14423 #define TIM_BDTR_DTG_Pos          (0U)
14424 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
14425 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
14426 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
14427 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
14428 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
14429 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
14430 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
14431 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
14432 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
14433 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
14434 
14435 #define TIM_BDTR_LOCK_Pos         (8U)
14436 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
14437 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
14438 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
14439 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
14440 
14441 #define TIM_BDTR_OSSI_Pos         (10U)
14442 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
14443 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
14444 #define TIM_BDTR_OSSR_Pos         (11U)
14445 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
14446 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
14447 #define TIM_BDTR_BKE_Pos          (12U)
14448 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
14449 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
14450 #define TIM_BDTR_BKP_Pos          (13U)
14451 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
14452 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
14453 #define TIM_BDTR_AOE_Pos          (14U)
14454 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
14455 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
14456 #define TIM_BDTR_MOE_Pos          (15U)
14457 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
14458 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
14459 #define TIM_BDTR_BKF_Pos          (16U)
14460 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
14461 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
14462 #define TIM_BDTR_BK2F_Pos         (20U)
14463 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
14464 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
14465 #define TIM_BDTR_BK2E_Pos         (24U)
14466 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
14467 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
14468 #define TIM_BDTR_BK2P_Pos         (25U)
14469 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
14470 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
14471 
14472 /*******************  Bit definition for TIM_DCR register  ********************/
14473 #define TIM_DCR_DBA_Pos           (0U)
14474 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
14475 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
14476 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
14477 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
14478 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
14479 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
14480 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
14481 
14482 #define TIM_DCR_DBL_Pos           (8U)
14483 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
14484 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
14485 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
14486 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
14487 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
14488 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
14489 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
14490 
14491 /*******************  Bit definition for TIM_DMAR register  *******************/
14492 #define TIM_DMAR_DMAB_Pos         (0U)
14493 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
14494 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
14495 
14496 /*******************  Bit definition for TIM_OR register  *********************/
14497 #define TIM_OR_TI4_RMP_Pos        (6U)
14498 #define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
14499 #define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
14500 #define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
14501 #define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
14502 #define TIM_OR_ITR1_RMP_Pos       (10U)
14503 #define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
14504 #define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
14505 #define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
14506 #define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
14507 
14508 /*******************  Bit definition for TIM2_OR register  *******************/
14509 #define TIM2_OR_ITR1_RMP_Pos      (10U)
14510 #define TIM2_OR_ITR1_RMP_Msk      (0x3UL << TIM2_OR_ITR1_RMP_Pos)               /*!< 0x00000C00 */
14511 #define TIM2_OR_ITR1_RMP          TIM2_OR_ITR1_RMP_Msk                         /*!<TIM2 Internal trigger 1 remap */
14512 #define TIM2_OR_ITR1_RMP_0        (0x1UL << TIM2_OR_ITR1_RMP_Pos)               /*!< 0x00000400 */
14513 #define TIM2_OR_ITR1_RMP_1        (0x2UL << TIM2_OR_ITR1_RMP_Pos)               /*!< 0x00000800 */
14514 
14515 /*******************  Bit definition for TIM5_OR register  *******************/
14516 #define TIM5_OR_TI4_RMP_Pos      (6U)
14517 #define TIM5_OR_TI4_RMP_Msk      (0x3UL << TIM5_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
14518 #define TIM5_OR_TI4_RMP          TIM5_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */
14519 #define TIM5_OR_TI4_RMP_0        (0x1UL << TIM5_OR_TI4_RMP_Pos)                 /*!< 0x00000040 */
14520 #define TIM5_OR_TI4_RMP_1        (0x2UL << TIM5_OR_TI4_RMP_Pos)                 /*!< 0x00000080 */
14521 
14522 /*******************  Bit definition for TIM11_OR register  *******************/
14523 #define TIM11_OR_TI1_RMP_Pos      (0U)
14524 #define TIM11_OR_TI1_RMP_Msk      (0x3UL << TIM11_OR_TI1_RMP_Pos)               /*!< 0x00000003 */
14525 #define TIM11_OR_TI1_RMP          TIM11_OR_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
14526 #define TIM11_OR_TI1_RMP_0        (0x1UL << TIM11_OR_TI1_RMP_Pos)               /*!< 0x00000001 */
14527 #define TIM11_OR_TI1_RMP_1        (0x2UL << TIM11_OR_TI1_RMP_Pos)               /*!< 0x00000002 */
14528 
14529 /******************  Bit definition for TIM_CCMR3 register  *******************/
14530 #define TIM_CCMR3_OC5FE_Pos       (2U)
14531 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
14532 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
14533 #define TIM_CCMR3_OC5PE_Pos       (3U)
14534 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
14535 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
14536 
14537 #define TIM_CCMR3_OC5M_Pos        (4U)
14538 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
14539 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
14540 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
14541 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
14542 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
14543 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
14544 
14545 #define TIM_CCMR3_OC5CE_Pos       (7U)
14546 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
14547 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
14548 
14549 #define TIM_CCMR3_OC6FE_Pos       (10U)
14550 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
14551 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
14552 #define TIM_CCMR3_OC6PE_Pos       (11U)
14553 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
14554 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
14555 
14556 #define TIM_CCMR3_OC6M_Pos        (12U)
14557 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
14558 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
14559 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
14560 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
14561 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
14562 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
14563 
14564 #define TIM_CCMR3_OC6CE_Pos       (15U)
14565 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
14566 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
14567 
14568 /*******************  Bit definition for TIM_CCR5 register  *******************/
14569 #define TIM_CCR5_CCR5_Pos         (0U)
14570 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
14571 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
14572 #define TIM_CCR5_GC5C1_Pos        (29U)
14573 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
14574 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
14575 #define TIM_CCR5_GC5C2_Pos        (30U)
14576 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
14577 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
14578 #define TIM_CCR5_GC5C3_Pos        (31U)
14579 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
14580 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
14581 
14582 /*******************  Bit definition for TIM_CCR6 register  *******************/
14583 #define  TIM_CCR6_CCR6           ((uint16_t)0xFFFFU)                           /*!<Capture/Compare 6 Value */
14584 
14585 
14586 /******************************************************************************/
14587 /*                                                                            */
14588 /*                         Low Power Timer (LPTIM)                            */
14589 /*                                                                            */
14590 /******************************************************************************/
14591 /******************  Bit definition for LPTIM_ISR register  *******************/
14592 #define LPTIM_ISR_CMPM_Pos          (0U)
14593 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
14594 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match                       */
14595 #define LPTIM_ISR_ARRM_Pos          (1U)
14596 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
14597 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match                    */
14598 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
14599 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
14600 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event         */
14601 #define LPTIM_ISR_CMPOK_Pos         (3U)
14602 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
14603 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK          */
14604 #define LPTIM_ISR_ARROK_Pos         (4U)
14605 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
14606 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK       */
14607 #define LPTIM_ISR_UP_Pos            (5U)
14608 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
14609 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
14610 #define LPTIM_ISR_DOWN_Pos          (6U)
14611 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
14612 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
14613 
14614 /******************  Bit definition for LPTIM_ICR register  *******************/
14615 #define LPTIM_ICR_CMPMCF_Pos        (0U)
14616 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
14617 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag                       */
14618 #define LPTIM_ICR_ARRMCF_Pos        (1U)
14619 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
14620 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag                    */
14621 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
14622 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
14623 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag         */
14624 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
14625 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
14626 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag          */
14627 #define LPTIM_ICR_ARROKCF_Pos       (4U)
14628 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
14629 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag       */
14630 #define LPTIM_ICR_UPCF_Pos          (5U)
14631 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
14632 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
14633 #define LPTIM_ICR_DOWNCF_Pos        (6U)
14634 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
14635 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
14636 
14637 /******************  Bit definition for LPTIM_IER register *******************/
14638 #define LPTIM_IER_CMPMIE_Pos        (0U)
14639 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
14640 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable                       */
14641 #define LPTIM_IER_ARRMIE_Pos        (1U)
14642 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
14643 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable                    */
14644 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
14645 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
14646 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable         */
14647 #define LPTIM_IER_CMPOKIE_Pos       (3U)
14648 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
14649 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable          */
14650 #define LPTIM_IER_ARROKIE_Pos       (4U)
14651 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
14652 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable       */
14653 #define LPTIM_IER_UPIE_Pos          (5U)
14654 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
14655 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
14656 #define LPTIM_IER_DOWNIE_Pos        (6U)
14657 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
14658 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
14659 
14660 /******************  Bit definition for LPTIM_CFGR register*******************/
14661 #define LPTIM_CFGR_CKSEL_Pos        (0U)
14662 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
14663 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
14664 
14665 #define LPTIM_CFGR_CKPOL_Pos        (1U)
14666 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
14667 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
14668 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
14669 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
14670 
14671 #define LPTIM_CFGR_CKFLT_Pos        (3U)
14672 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
14673 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
14674 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
14675 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
14676 
14677 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
14678 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
14679 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
14680 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
14681 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
14682 
14683 #define LPTIM_CFGR_PRESC_Pos        (9U)
14684 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
14685 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
14686 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
14687 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
14688 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
14689 
14690 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
14691 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
14692 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
14693 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
14694 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
14695 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
14696 
14697 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
14698 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
14699 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
14700 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
14701 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
14702 
14703 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
14704 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
14705 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable           */
14706 #define LPTIM_CFGR_WAVE_Pos         (20U)
14707 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
14708 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape          */
14709 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
14710 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
14711 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
14712 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
14713 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
14714 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode         */
14715 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
14716 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
14717 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable     */
14718 #define LPTIM_CFGR_ENC_Pos          (24U)
14719 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
14720 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable     */
14721 
14722 /******************  Bit definition for LPTIM_CR register  ********************/
14723 #define LPTIM_CR_ENABLE_Pos         (0U)
14724 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
14725 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable                 */
14726 #define LPTIM_CR_SNGSTRT_Pos        (1U)
14727 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
14728 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode     */
14729 #define LPTIM_CR_CNTSTRT_Pos        (2U)
14730 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
14731 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
14732 
14733 /******************  Bit definition for LPTIM_CMP register *******************/
14734 #define LPTIM_CMP_CMP_Pos           (0U)
14735 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
14736 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register     */
14737 
14738 /******************  Bit definition for LPTIM_ARR register *******************/
14739 #define LPTIM_ARR_ARR_Pos           (0U)
14740 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
14741 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
14742 
14743 /******************  Bit definition for LPTIM_CNT register *******************/
14744 #define LPTIM_CNT_CNT_Pos           (0U)
14745 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
14746 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register     */
14747 /******************************************************************************/
14748 /*                                                                            */
14749 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
14750 /*                                                                            */
14751 /******************************************************************************/
14752 /******************  Bit definition for USART_CR1 register  *******************/
14753 #define USART_CR1_UE_Pos              (0U)
14754 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
14755 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable                                    */
14756 #define USART_CR1_RE_Pos              (2U)
14757 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
14758 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable                                 */
14759 #define USART_CR1_TE_Pos              (3U)
14760 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
14761 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable                              */
14762 #define USART_CR1_IDLEIE_Pos          (4U)
14763 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
14764 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable                           */
14765 #define USART_CR1_RXNEIE_Pos          (5U)
14766 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
14767 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable                           */
14768 #define USART_CR1_TCIE_Pos            (6U)
14769 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
14770 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable          */
14771 #define USART_CR1_TXEIE_Pos           (7U)
14772 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
14773 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable                            */
14774 #define USART_CR1_PEIE_Pos            (8U)
14775 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
14776 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable                             */
14777 #define USART_CR1_PS_Pos              (9U)
14778 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
14779 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection                                */
14780 #define USART_CR1_PCE_Pos             (10U)
14781 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
14782 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable                           */
14783 #define USART_CR1_WAKE_Pos            (11U)
14784 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
14785 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method                          */
14786 #define USART_CR1_M_Pos               (12U)
14787 #define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
14788 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length                                     */
14789 #define USART_CR1_M0                  (0x00001UL << USART_CR1_M_Pos)            /*!< 0x00001000 */
14790 #define USART_CR1_MME_Pos             (13U)
14791 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
14792 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable                                */
14793 #define USART_CR1_CMIE_Pos            (14U)
14794 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
14795 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable                */
14796 #define USART_CR1_OVER8_Pos           (15U)
14797 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
14798 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode            */
14799 #define USART_CR1_DEDT_Pos            (16U)
14800 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
14801 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
14802 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
14803 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
14804 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
14805 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
14806 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
14807 #define USART_CR1_DEAT_Pos            (21U)
14808 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
14809 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */
14810 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
14811 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
14812 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
14813 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
14814 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
14815 #define USART_CR1_RTOIE_Pos           (26U)
14816 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
14817 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
14818 #define USART_CR1_EOBIE_Pos           (27U)
14819 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
14820 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable     */
14821 #define USART_CR1_M1                  0x10000000U                              /*!< Word length - Bit 1               */
14822 
14823 /* Legacy defines */
14824 #define  USART_CR1_M_0                       USART_CR1_M0          /*!< Word length - Bit 0               */
14825 #define  USART_CR1_M_1                       USART_CR1_M1          /*!< Word length - Bit 1               */
14826 
14827 /******************  Bit definition for USART_CR2 register  *******************/
14828 #define USART_CR2_ADDM7_Pos           (4U)
14829 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
14830 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection       */
14831 #define USART_CR2_LBDL_Pos            (5U)
14832 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
14833 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length             */
14834 #define USART_CR2_LBDIE_Pos           (6U)
14835 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
14836 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable   */
14837 #define USART_CR2_LBCL_Pos            (8U)
14838 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
14839 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse                   */
14840 #define USART_CR2_CPHA_Pos            (9U)
14841 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
14842 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase                            */
14843 #define USART_CR2_CPOL_Pos            (10U)
14844 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
14845 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity                         */
14846 #define USART_CR2_CLKEN_Pos           (11U)
14847 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
14848 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable                           */
14849 #define USART_CR2_STOP_Pos            (12U)
14850 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
14851 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits)             */
14852 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
14853 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
14854 #define USART_CR2_LINEN_Pos           (14U)
14855 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
14856 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable                        */
14857 #define USART_CR2_SWAP_Pos            (15U)
14858 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
14859 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins                        */
14860 #define USART_CR2_RXINV_Pos           (16U)
14861 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
14862 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion          */
14863 #define USART_CR2_TXINV_Pos           (17U)
14864 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
14865 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion          */
14866 #define USART_CR2_DATAINV_Pos         (18U)
14867 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
14868 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion                  */
14869 #define USART_CR2_MSBFIRST_Pos        (19U)
14870 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
14871 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First             */
14872 #define USART_CR2_ABREN_Pos           (20U)
14873 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
14874 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable                  */
14875 #define USART_CR2_ABRMODE_Pos         (21U)
14876 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
14877 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
14878 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
14879 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
14880 #define USART_CR2_RTOEN_Pos           (23U)
14881 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
14882 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable  */
14883 #define USART_CR2_ADD_Pos             (24U)
14884 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
14885 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
14886 
14887 /******************  Bit definition for USART_CR3 register  *******************/
14888 #define USART_CR3_EIE_Pos             (0U)
14889 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
14890 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable                         */
14891 #define USART_CR3_IREN_Pos            (1U)
14892 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
14893 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable                               */
14894 #define USART_CR3_IRLP_Pos            (2U)
14895 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
14896 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power                                 */
14897 #define USART_CR3_HDSEL_Pos           (3U)
14898 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
14899 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection                          */
14900 #define USART_CR3_NACK_Pos            (4U)
14901 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
14902 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable                          */
14903 #define USART_CR3_SCEN_Pos            (5U)
14904 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
14905 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable                          */
14906 #define USART_CR3_DMAR_Pos            (6U)
14907 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
14908 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver                            */
14909 #define USART_CR3_DMAT_Pos            (7U)
14910 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
14911 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter                         */
14912 #define USART_CR3_RTSE_Pos            (8U)
14913 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
14914 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable                                     */
14915 #define USART_CR3_CTSE_Pos            (9U)
14916 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
14917 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable                                     */
14918 #define USART_CR3_CTSIE_Pos           (10U)
14919 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
14920 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable                           */
14921 #define USART_CR3_ONEBIT_Pos          (11U)
14922 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
14923 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable                   */
14924 #define USART_CR3_OVRDIS_Pos          (12U)
14925 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
14926 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable                                */
14927 #define USART_CR3_DDRE_Pos            (13U)
14928 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
14929 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error                 */
14930 #define USART_CR3_DEM_Pos             (14U)
14931 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
14932 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode                             */
14933 #define USART_CR3_DEP_Pos             (15U)
14934 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
14935 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection               */
14936 #define USART_CR3_SCARCNT_Pos         (17U)
14937 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
14938 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
14939 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
14940 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
14941 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
14942 
14943 /******************  Bit definition for USART_BRR register  *******************/
14944 #define USART_BRR_DIV_FRACTION_Pos    (0U)
14945 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
14946 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
14947 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
14948 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
14949 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
14950 
14951 /******************  Bit definition for USART_GTPR register  ******************/
14952 #define USART_GTPR_PSC_Pos            (0U)
14953 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
14954 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
14955 #define USART_GTPR_GT_Pos             (8U)
14956 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
14957 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
14958 
14959 
14960 /*******************  Bit definition for USART_RTOR register  *****************/
14961 #define USART_RTOR_RTO_Pos            (0U)
14962 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
14963 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
14964 #define USART_RTOR_BLEN_Pos           (24U)
14965 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
14966 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
14967 
14968 /*******************  Bit definition for USART_RQR register  ******************/
14969 #define USART_RQR_ABRRQ_Pos           (0U)
14970 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
14971 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request      */
14972 #define USART_RQR_SBKRQ_Pos           (1U)
14973 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
14974 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request          */
14975 #define USART_RQR_MMRQ_Pos            (2U)
14976 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
14977 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request           */
14978 #define USART_RQR_RXFRQ_Pos           (3U)
14979 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
14980 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request  */
14981 #define USART_RQR_TXFRQ_Pos           (4U)
14982 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
14983 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
14984 
14985 /*******************  Bit definition for USART_ISR register  ******************/
14986 #define USART_ISR_PE_Pos              (0U)
14987 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
14988 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error                        */
14989 #define USART_ISR_FE_Pos              (1U)
14990 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
14991 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error                       */
14992 #define USART_ISR_NE_Pos              (2U)
14993 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
14994 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag                 */
14995 #define USART_ISR_ORE_Pos             (3U)
14996 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
14997 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error                       */
14998 #define USART_ISR_IDLE_Pos            (4U)
14999 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
15000 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected                  */
15001 #define USART_ISR_RXNE_Pos            (5U)
15002 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
15003 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty        */
15004 #define USART_ISR_TC_Pos              (6U)
15005 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
15006 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete               */
15007 #define USART_ISR_TXE_Pos             (7U)
15008 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
15009 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty        */
15010 #define USART_ISR_LBDF_Pos            (8U)
15011 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
15012 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag            */
15013 #define USART_ISR_CTSIF_Pos           (9U)
15014 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
15015 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag                  */
15016 #define USART_ISR_CTS_Pos             (10U)
15017 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
15018 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag                            */
15019 #define USART_ISR_RTOF_Pos            (11U)
15020 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
15021 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out                   */
15022 #define USART_ISR_EOBF_Pos            (12U)
15023 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
15024 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag                   */
15025 #define USART_ISR_ABRE_Pos            (14U)
15026 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
15027 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error                */
15028 #define USART_ISR_ABRF_Pos            (15U)
15029 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
15030 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag                 */
15031 #define USART_ISR_BUSY_Pos            (16U)
15032 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
15033 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag                           */
15034 #define USART_ISR_CMF_Pos             (17U)
15035 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
15036 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag                */
15037 #define USART_ISR_SBKF_Pos            (18U)
15038 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
15039 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag                     */
15040 #define USART_ISR_RWU_Pos             (19U)
15041 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
15042 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
15043 #define USART_ISR_TEACK_Pos           (21U)
15044 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
15045 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag    */
15046 /* Legacy define */
15047 #define  USART_ISR_LBD                       USART_ISR_LBDF
15048 
15049 /*******************  Bit definition for USART_ICR register  ******************/
15050 #define USART_ICR_PECF_Pos            (0U)
15051 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
15052 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag             */
15053 #define USART_ICR_FECF_Pos            (1U)
15054 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
15055 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag            */
15056 #define USART_ICR_NCF_Pos             (2U)
15057 #define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
15058 #define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag           */
15059 #define USART_ICR_ORECF_Pos           (3U)
15060 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
15061 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag            */
15062 #define USART_ICR_IDLECF_Pos          (4U)
15063 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
15064 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag       */
15065 #define USART_ICR_TCCF_Pos            (6U)
15066 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
15067 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag    */
15068 #define USART_ICR_LBDCF_Pos           (8U)
15069 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
15070 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag      */
15071 #define USART_ICR_CTSCF_Pos           (9U)
15072 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
15073 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag            */
15074 #define USART_ICR_RTOCF_Pos           (11U)
15075 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
15076 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag        */
15077 #define USART_ICR_EOBCF_Pos           (12U)
15078 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
15079 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag             */
15080 #define USART_ICR_CMCF_Pos            (17U)
15081 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
15082 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag          */
15083 
15084 /*******************  Bit definition for USART_RDR register  ******************/
15085 #define USART_RDR_RDR_Pos             (0U)
15086 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
15087 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
15088 
15089 /*******************  Bit definition for USART_TDR register  ******************/
15090 #define USART_TDR_TDR_Pos             (0U)
15091 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
15092 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
15093 
15094 /******************************************************************************/
15095 /*                                                                            */
15096 /*                            Window WATCHDOG                                 */
15097 /*                                                                            */
15098 /******************************************************************************/
15099 /*******************  Bit definition for WWDG_CR register  ********************/
15100 #define WWDG_CR_T_Pos           (0U)
15101 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
15102 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
15103 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
15104 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
15105 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
15106 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
15107 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
15108 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
15109 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
15110 
15111 /* Legacy defines */
15112 #define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */
15113 #define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */
15114 #define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */
15115 #define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */
15116 #define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */
15117 #define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */
15118 #define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */
15119 
15120 #define WWDG_CR_WDGA_Pos        (7U)
15121 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
15122 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
15123 
15124 /*******************  Bit definition for WWDG_CFR register  *******************/
15125 #define WWDG_CFR_W_Pos          (0U)
15126 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
15127 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
15128 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
15129 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
15130 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
15131 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
15132 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
15133 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
15134 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
15135 
15136 /* Legacy defines */
15137 #define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */
15138 #define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */
15139 #define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */
15140 #define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */
15141 #define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */
15142 #define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */
15143 #define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */
15144 
15145 #define WWDG_CFR_WDGTB_Pos      (7U)
15146 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
15147 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
15148 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
15149 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
15150 
15151 /* Legacy defines */
15152 #define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */
15153 #define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */
15154 
15155 #define WWDG_CFR_EWI_Pos        (9U)
15156 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
15157 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
15158 
15159 /*******************  Bit definition for WWDG_SR register  ********************/
15160 #define WWDG_SR_EWIF_Pos        (0U)
15161 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
15162 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
15163 
15164 /******************************************************************************/
15165 /*                                                                            */
15166 /*                                DBG                                         */
15167 /*                                                                            */
15168 /******************************************************************************/
15169 /********************  Bit definition for DBGMCU_IDCODE register  *************/
15170 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
15171 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
15172 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
15173 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
15174 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
15175 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
15176 
15177 /********************  Bit definition for DBGMCU_CR register  *****************/
15178 #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
15179 #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
15180 #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
15181 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
15182 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
15183 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
15184 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
15185 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
15186 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
15187 #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
15188 #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
15189 #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
15190 
15191 #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
15192 #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
15193 #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
15194 #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
15195 #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
15196 
15197 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
15198 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
15199 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
15200 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
15201 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
15202 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
15203 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
15204 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)
15205 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
15206 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
15207 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)
15208 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
15209 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
15210 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
15211 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
15212 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
15213 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
15214 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
15215 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
15216 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)
15217 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
15218 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
15219 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)
15220 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
15221 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
15222 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
15223 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
15224 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
15225 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos           (9U)
15226 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk           (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
15227 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP               DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
15228 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
15229 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
15230 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
15231 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
15232 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
15233 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
15234 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
15235 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
15236 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
15237 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
15238 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
15239 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
15240 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
15241 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
15242 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
15243 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)
15244 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
15245 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
15246 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)
15247 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
15248 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
15249 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)
15250 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
15251 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
15252 
15253 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
15254 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
15255 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
15256 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
15257 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)
15258 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
15259 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
15260 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)
15261 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
15262 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
15263 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)
15264 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
15265 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
15266 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)
15267 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
15268 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
15269 
15270 /******************************************************************************/
15271 /*                                                                            */
15272 /*                Ethernet MAC Registers bits definitions                     */
15273 /*                                                                            */
15274 /******************************************************************************/
15275 /* Bit definition for Ethernet MAC Control Register register */
15276 #define ETH_MACCR_CSTF_Pos                            (25U)
15277 #define ETH_MACCR_CSTF_Msk                            (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
15278 #define ETH_MACCR_CSTF                                ETH_MACCR_CSTF_Msk       /* CRC stripping for Type frames */
15279 #define ETH_MACCR_WD_Pos                              (23U)
15280 #define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
15281 #define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
15282 #define ETH_MACCR_JD_Pos                              (22U)
15283 #define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
15284 #define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
15285 #define ETH_MACCR_IFG_Pos                             (17U)
15286 #define ETH_MACCR_IFG_Msk                             (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
15287 #define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
15288 #define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
15289 #define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
15290 #define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
15291 #define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
15292 #define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
15293 #define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
15294 #define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
15295 #define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
15296 #define ETH_MACCR_CSD_Pos                             (16U)
15297 #define ETH_MACCR_CSD_Msk                             (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
15298 #define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
15299 #define ETH_MACCR_FES_Pos                             (14U)
15300 #define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
15301 #define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
15302 #define ETH_MACCR_ROD_Pos                             (13U)
15303 #define ETH_MACCR_ROD_Msk                             (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
15304 #define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
15305 #define ETH_MACCR_LM_Pos                              (12U)
15306 #define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
15307 #define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
15308 #define ETH_MACCR_DM_Pos                              (11U)
15309 #define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
15310 #define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
15311 #define ETH_MACCR_IPCO_Pos                            (10U)
15312 #define ETH_MACCR_IPCO_Msk                            (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
15313 #define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
15314 #define ETH_MACCR_RD_Pos                              (9U)
15315 #define ETH_MACCR_RD_Msk                              (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
15316 #define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
15317 #define ETH_MACCR_APCS_Pos                            (7U)
15318 #define ETH_MACCR_APCS_Msk                            (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
15319 #define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
15320 #define ETH_MACCR_BL_Pos                              (5U)
15321 #define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
15322 #define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
15323                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
15324 #define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
15325 #define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
15326 #define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
15327 #define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */
15328 #define ETH_MACCR_DC_Pos                              (4U)
15329 #define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
15330 #define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
15331 #define ETH_MACCR_TE_Pos                              (3U)
15332 #define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
15333 #define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
15334 #define ETH_MACCR_RE_Pos                              (2U)
15335 #define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
15336 #define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
15337 
15338 /* Bit definition for Ethernet MAC Frame Filter Register */
15339 #define ETH_MACFFR_RA_Pos                             (31U)
15340 #define ETH_MACFFR_RA_Msk                             (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
15341 #define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
15342 #define ETH_MACFFR_HPF_Pos                            (10U)
15343 #define ETH_MACFFR_HPF_Msk                            (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
15344 #define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
15345 #define ETH_MACFFR_SAF_Pos                            (9U)
15346 #define ETH_MACFFR_SAF_Msk                            (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
15347 #define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
15348 #define ETH_MACFFR_SAIF_Pos                           (8U)
15349 #define ETH_MACFFR_SAIF_Msk                           (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
15350 #define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */
15351 #define ETH_MACFFR_PCF_Pos                            (6U)
15352 #define ETH_MACFFR_PCF_Msk                            (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
15353 #define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
15354 #define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)
15355 #define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
15356 #define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
15357 #define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)
15358 #define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
15359 #define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
15360 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)
15361 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
15362 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
15363 #define ETH_MACFFR_BFD_Pos                            (5U)
15364 #define ETH_MACFFR_BFD_Msk                            (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
15365 #define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */
15366 #define ETH_MACFFR_PAM_Pos                            (4U)
15367 #define ETH_MACFFR_PAM_Msk                            (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
15368 #define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
15369 #define ETH_MACFFR_DAIF_Pos                           (3U)
15370 #define ETH_MACFFR_DAIF_Msk                           (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
15371 #define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
15372 #define ETH_MACFFR_HM_Pos                             (2U)
15373 #define ETH_MACFFR_HM_Msk                             (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
15374 #define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */
15375 #define ETH_MACFFR_HU_Pos                             (1U)
15376 #define ETH_MACFFR_HU_Msk                             (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
15377 #define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
15378 #define ETH_MACFFR_PM_Pos                             (0U)
15379 #define ETH_MACFFR_PM_Msk                             (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
15380 #define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
15381 
15382 /* Bit definition for Ethernet MAC Hash Table High Register */
15383 #define ETH_MACHTHR_HTH_Pos                           (0U)
15384 #define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
15385 #define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
15386 
15387 /* Bit definition for Ethernet MAC Hash Table Low Register */
15388 #define ETH_MACHTLR_HTL_Pos                           (0U)
15389 #define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
15390 #define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
15391 
15392 /* Bit definition for Ethernet MAC MII Address Register */
15393 #define ETH_MACMIIAR_PA_Pos                           (11U)
15394 #define ETH_MACMIIAR_PA_Msk                           (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
15395 #define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
15396 #define ETH_MACMIIAR_MR_Pos                           (6U)
15397 #define ETH_MACMIIAR_MR_Msk                           (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
15398 #define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
15399 #define ETH_MACMIIAR_CR_Pos                           (2U)
15400 #define ETH_MACMIIAR_CR_Msk                           (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
15401 #define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
15402 #define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
15403 #define ETH_MACMIIAR_CR_Div62_Pos                     (2U)
15404 #define ETH_MACMIIAR_CR_Div62_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
15405 #define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
15406 #define ETH_MACMIIAR_CR_Div16_Pos                     (3U)
15407 #define ETH_MACMIIAR_CR_Div16_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
15408 #define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
15409 #define ETH_MACMIIAR_CR_Div26_Pos                     (2U)
15410 #define ETH_MACMIIAR_CR_Div26_Msk                     (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
15411 #define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
15412 #define ETH_MACMIIAR_CR_Div102_Pos                    (4U)
15413 #define ETH_MACMIIAR_CR_Div102_Msk                    (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
15414 #define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
15415 #define ETH_MACMIIAR_MW_Pos                           (1U)
15416 #define ETH_MACMIIAR_MW_Msk                           (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
15417 #define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
15418 #define ETH_MACMIIAR_MB_Pos                           (0U)
15419 #define ETH_MACMIIAR_MB_Msk                           (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
15420 #define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy */
15421 
15422 /* Bit definition for Ethernet MAC MII Data Register */
15423 #define ETH_MACMIIDR_MD_Pos                           (0U)
15424 #define ETH_MACMIIDR_MD_Msk                           (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
15425 #define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
15426 
15427 /* Bit definition for Ethernet MAC Flow Control Register */
15428 #define ETH_MACFCR_PT_Pos                             (16U)
15429 #define ETH_MACFCR_PT_Msk                             (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
15430 #define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
15431 #define ETH_MACFCR_ZQPD_Pos                           (7U)
15432 #define ETH_MACFCR_ZQPD_Msk                           (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
15433 #define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
15434 #define ETH_MACFCR_PLT_Pos                            (4U)
15435 #define ETH_MACFCR_PLT_Msk                            (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
15436 #define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
15437 #define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times */
15438 #define ETH_MACFCR_PLT_Minus28_Pos                    (4U)
15439 #define ETH_MACFCR_PLT_Minus28_Msk                    (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
15440 #define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
15441 #define ETH_MACFCR_PLT_Minus144_Pos                   (5U)
15442 #define ETH_MACFCR_PLT_Minus144_Msk                   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
15443 #define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
15444 #define ETH_MACFCR_PLT_Minus256_Pos                   (4U)
15445 #define ETH_MACFCR_PLT_Minus256_Msk                   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
15446 #define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
15447 #define ETH_MACFCR_UPFD_Pos                           (3U)
15448 #define ETH_MACFCR_UPFD_Msk                           (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
15449 #define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
15450 #define ETH_MACFCR_RFCE_Pos                           (2U)
15451 #define ETH_MACFCR_RFCE_Msk                           (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
15452 #define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
15453 #define ETH_MACFCR_TFCE_Pos                           (1U)
15454 #define ETH_MACFCR_TFCE_Msk                           (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
15455 #define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
15456 #define ETH_MACFCR_FCBBPA_Pos                         (0U)
15457 #define ETH_MACFCR_FCBBPA_Msk                         (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
15458 #define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
15459 
15460 /* Bit definition for Ethernet MAC VLAN Tag Register */
15461 #define ETH_MACVLANTR_VLANTC_Pos                      (16U)
15462 #define ETH_MACVLANTR_VLANTC_Msk                      (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
15463 #define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
15464 #define ETH_MACVLANTR_VLANTI_Pos                      (0U)
15465 #define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
15466 #define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
15467 
15468 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
15469 #define ETH_MACRWUFFR_D_Pos                           (0U)
15470 #define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
15471 #define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
15472 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
15473    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
15474 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
15475    Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
15476    Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
15477    Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
15478    Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
15479                               RSVD - Filter1 Command - RSVD - Filter0 Command
15480    Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
15481    Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
15482    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
15483 
15484 /* Bit definition for Ethernet MAC PMT Control and Status Register */
15485 #define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)
15486 #define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
15487 #define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
15488 #define ETH_MACPMTCSR_GU_Pos                          (9U)
15489 #define ETH_MACPMTCSR_GU_Msk                          (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
15490 #define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast */
15491 #define ETH_MACPMTCSR_WFR_Pos                         (6U)
15492 #define ETH_MACPMTCSR_WFR_Msk                         (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
15493 #define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received */
15494 #define ETH_MACPMTCSR_MPR_Pos                         (5U)
15495 #define ETH_MACPMTCSR_MPR_Msk                         (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
15496 #define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received */
15497 #define ETH_MACPMTCSR_WFE_Pos                         (2U)
15498 #define ETH_MACPMTCSR_WFE_Msk                         (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
15499 #define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable */
15500 #define ETH_MACPMTCSR_MPE_Pos                         (1U)
15501 #define ETH_MACPMTCSR_MPE_Msk                         (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
15502 #define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable */
15503 #define ETH_MACPMTCSR_PD_Pos                          (0U)
15504 #define ETH_MACPMTCSR_PD_Msk                          (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
15505 #define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down */
15506 
15507 /* Bit definition for Ethernet MAC debug Register */
15508 #define ETH_MACDBGR_TFF_Pos                           (25U)
15509 #define ETH_MACDBGR_TFF_Msk                           (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
15510 #define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
15511 #define ETH_MACDBGR_TFNE_Pos                          (24U)
15512 #define ETH_MACDBGR_TFNE_Msk                          (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
15513 #define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
15514 #define ETH_MACDBGR_TPWA_Pos                          (22U)
15515 #define ETH_MACDBGR_TPWA_Msk                          (0x1UL << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
15516 #define ETH_MACDBGR_TPWA                              ETH_MACDBGR_TPWA_Msk     /* Tx FIFO write active                                                    */
15517 #define ETH_MACDBGR_TFRS_Pos                          (20U)
15518 #define ETH_MACDBGR_TFRS_Msk                          (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
15519 #define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
15520 #define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)
15521 #define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
15522 #define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
15523 #define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)
15524 #define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
15525 #define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
15526 #define ETH_MACDBGR_TFRS_READ_Pos                     (20U)
15527 #define ETH_MACDBGR_TFRS_READ_Msk                     (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
15528 #define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
15529 #define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
15530 #define ETH_MACDBGR_MTP_Pos                           (19U)
15531 #define ETH_MACDBGR_MTP_Msk                           (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
15532 #define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
15533 #define ETH_MACDBGR_MTFCS_Pos                         (17U)
15534 #define ETH_MACDBGR_MTFCS_Msk                         (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
15535 #define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
15536 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)
15537 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
15538 #define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
15539 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)
15540 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
15541 #define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
15542 #define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)
15543 #define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
15544 #define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
15545 #define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
15546 #define ETH_MACDBGR_MMTEA_Pos                         (16U)
15547 #define ETH_MACDBGR_MMTEA_Msk                         (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
15548 #define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
15549 #define ETH_MACDBGR_RFFL_Pos                          (8U)
15550 #define ETH_MACDBGR_RFFL_Msk                          (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
15551 #define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
15552 #define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)
15553 #define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
15554 #define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
15555 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)
15556 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
15557 #define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
15558 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)
15559 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
15560 #define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
15561 #define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
15562 #define ETH_MACDBGR_RFRCS_Pos                         (5U)
15563 #define ETH_MACDBGR_RFRCS_Msk                         (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
15564 #define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
15565 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)
15566 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
15567 #define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
15568 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)
15569 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
15570 #define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
15571 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)
15572 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
15573 #define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
15574 #define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
15575 #define ETH_MACDBGR_RFWRA_Pos                         (4U)
15576 #define ETH_MACDBGR_RFWRA_Msk                         (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
15577 #define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
15578 #define ETH_MACDBGR_MSFRWCS_Pos                       (1U)
15579 #define ETH_MACDBGR_MSFRWCS_Msk                       (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
15580 #define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
15581 #define ETH_MACDBGR_MSFRWCS_1                         (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
15582 #define ETH_MACDBGR_MSFRWCS_0                         (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
15583 #define ETH_MACDBGR_MMRPEA_Pos                        (0U)
15584 #define ETH_MACDBGR_MMRPEA_Msk                        (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
15585 #define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
15586 
15587 /* Bit definition for Ethernet MAC Status Register */
15588 #define ETH_MACSR_TSTS_Pos                            (9U)
15589 #define ETH_MACSR_TSTS_Msk                            (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
15590 #define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
15591 #define ETH_MACSR_MMCTS_Pos                           (6U)
15592 #define ETH_MACSR_MMCTS_Msk                           (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
15593 #define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status */
15594 #define ETH_MACSR_MMMCRS_Pos                          (5U)
15595 #define ETH_MACSR_MMMCRS_Msk                          (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
15596 #define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status */
15597 #define ETH_MACSR_MMCS_Pos                            (4U)
15598 #define ETH_MACSR_MMCS_Msk                            (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
15599 #define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status */
15600 #define ETH_MACSR_PMTS_Pos                            (3U)
15601 #define ETH_MACSR_PMTS_Msk                            (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
15602 #define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status */
15603 
15604 /* Bit definition for Ethernet MAC Interrupt Mask Register */
15605 #define ETH_MACIMR_TSTIM_Pos                          (9U)
15606 #define ETH_MACIMR_TSTIM_Msk                          (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
15607 #define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
15608 #define ETH_MACIMR_PMTIM_Pos                          (3U)
15609 #define ETH_MACIMR_PMTIM_Msk                          (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
15610 #define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask */
15611 
15612 /* Bit definition for Ethernet MAC Address0 High Register */
15613 #define ETH_MACA0HR_MACA0H_Pos                        (0U)
15614 #define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
15615 #define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
15616 
15617 /* Bit definition for Ethernet MAC Address0 Low Register */
15618 #define ETH_MACA0LR_MACA0L_Pos                        (0U)
15619 #define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
15620 #define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
15621 
15622 /* Bit definition for Ethernet MAC Address1 High Register */
15623 #define ETH_MACA1HR_AE_Pos                            (31U)
15624 #define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
15625 #define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
15626 #define ETH_MACA1HR_SA_Pos                            (30U)
15627 #define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
15628 #define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
15629 #define ETH_MACA1HR_MBC_Pos                           (24U)
15630 #define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
15631 #define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
15632 #define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
15633 #define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */
15634 #define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
15635 #define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
15636 #define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */
15637 #define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0] */
15638 #define ETH_MACA1HR_MACA1H_Pos                        (0U)
15639 #define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
15640 #define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
15641 
15642 /* Bit definition for Ethernet MAC Address1 Low Register */
15643 #define ETH_MACA1LR_MACA1L_Pos                        (0U)
15644 #define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
15645 #define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
15646 
15647 /* Bit definition for Ethernet MAC Address2 High Register */
15648 #define ETH_MACA2HR_AE_Pos                            (31U)
15649 #define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
15650 #define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
15651 #define ETH_MACA2HR_SA_Pos                            (30U)
15652 #define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
15653 #define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
15654 #define ETH_MACA2HR_MBC_Pos                           (24U)
15655 #define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
15656 #define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
15657 #define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
15658 #define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */
15659 #define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
15660 #define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
15661 #define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */
15662 #define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70] */
15663 #define ETH_MACA2HR_MACA2H_Pos                        (0U)
15664 #define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
15665 #define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
15666 
15667 /* Bit definition for Ethernet MAC Address2 Low Register */
15668 #define ETH_MACA2LR_MACA2L_Pos                        (0U)
15669 #define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
15670 #define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
15671 
15672 /* Bit definition for Ethernet MAC Address3 High Register */
15673 #define ETH_MACA3HR_AE_Pos                            (31U)
15674 #define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
15675 #define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
15676 #define ETH_MACA3HR_SA_Pos                            (30U)
15677 #define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
15678 #define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
15679 #define ETH_MACA3HR_MBC_Pos                           (24U)
15680 #define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
15681 #define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
15682 #define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
15683 #define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */
15684 #define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
15685 #define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
15686 #define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */
15687 #define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70] */
15688 #define ETH_MACA3HR_MACA3H_Pos                        (0U)
15689 #define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
15690 #define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
15691 
15692 /* Bit definition for Ethernet MAC Address3 Low Register */
15693 #define ETH_MACA3LR_MACA3L_Pos                        (0U)
15694 #define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
15695 #define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
15696 
15697 /******************************************************************************/
15698 /*                Ethernet MMC Registers bits definition                      */
15699 /******************************************************************************/
15700 
15701 /* Bit definition for Ethernet MMC Control Register */
15702 #define ETH_MMCCR_MCFHP_Pos                           (5U)
15703 #define ETH_MMCCR_MCFHP_Msk                           (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
15704 #define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
15705 #define ETH_MMCCR_MCP_Pos                             (4U)
15706 #define ETH_MMCCR_MCP_Msk                             (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
15707 #define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset */
15708 #define ETH_MMCCR_MCF_Pos                             (3U)
15709 #define ETH_MMCCR_MCF_Msk                             (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
15710 #define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze */
15711 #define ETH_MMCCR_ROR_Pos                             (2U)
15712 #define ETH_MMCCR_ROR_Msk                             (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
15713 #define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read */
15714 #define ETH_MMCCR_CSR_Pos                             (1U)
15715 #define ETH_MMCCR_CSR_Msk                             (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
15716 #define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover */
15717 #define ETH_MMCCR_CR_Pos                              (0U)
15718 #define ETH_MMCCR_CR_Msk                              (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
15719 #define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset */
15720 
15721 /* Bit definition for Ethernet MMC Receive Interrupt Register */
15722 #define ETH_MMCRIR_RGUFS_Pos                          (17U)
15723 #define ETH_MMCRIR_RGUFS_Msk                          (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
15724 #define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
15725 #define ETH_MMCRIR_RFAES_Pos                          (6U)
15726 #define ETH_MMCRIR_RFAES_Msk                          (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
15727 #define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
15728 #define ETH_MMCRIR_RFCES_Pos                          (5U)
15729 #define ETH_MMCRIR_RFCES_Msk                          (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
15730 #define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
15731 
15732 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
15733 #define ETH_MMCTIR_TGFS_Pos                           (21U)
15734 #define ETH_MMCTIR_TGFS_Msk                           (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
15735 #define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
15736 #define ETH_MMCTIR_TGFMSCS_Pos                        (15U)
15737 #define ETH_MMCTIR_TGFMSCS_Msk                        (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
15738 #define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
15739 #define ETH_MMCTIR_TGFSCS_Pos                         (14U)
15740 #define ETH_MMCTIR_TGFSCS_Msk                         (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
15741 #define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
15742 
15743 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
15744 #define ETH_MMCRIMR_RGUFM_Pos                         (17U)
15745 #define ETH_MMCRIMR_RGUFM_Msk                         (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
15746 #define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
15747 #define ETH_MMCRIMR_RFAEM_Pos                         (6U)
15748 #define ETH_MMCRIMR_RFAEM_Msk                         (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
15749 #define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
15750 #define ETH_MMCRIMR_RFCEM_Pos                         (5U)
15751 #define ETH_MMCRIMR_RFCEM_Msk                         (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
15752 #define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
15753 
15754 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
15755 #define ETH_MMCTIMR_TGFM_Pos                          (21U)
15756 #define ETH_MMCTIMR_TGFM_Msk                          (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
15757 #define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
15758 #define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)
15759 #define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
15760 #define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
15761 #define ETH_MMCTIMR_TGFSCM_Pos                        (14U)
15762 #define ETH_MMCTIMR_TGFSCM_Msk                        (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
15763 #define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
15764 
15765 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
15766 #define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)
15767 #define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
15768 #define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
15769 
15770 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
15771 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)
15772 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
15773 #define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
15774 
15775 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
15776 #define ETH_MMCTGFCR_TGFC_Pos                         (0U)
15777 #define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
15778 #define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
15779 
15780 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
15781 #define ETH_MMCRFCECR_RFCEC_Pos                       (0U)
15782 #define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
15783 #define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
15784 
15785 /* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
15786 #define ETH_MMCRFAECR_RFAEC_Pos                       (0U)
15787 #define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
15788 #define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
15789 
15790 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
15791 #define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)
15792 #define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
15793 #define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
15794 
15795 /******************************************************************************/
15796 /*               Ethernet PTP Registers bits definition                       */
15797 /******************************************************************************/
15798 
15799 /* Bit definition for Ethernet PTP Time Stamp Control Register */
15800 #define ETH_PTPTSCR_TSPFFMAE_Pos                      (18U)
15801 #define ETH_PTPTSCR_TSPFFMAE_Msk                      (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
15802 #define ETH_PTPTSCR_TSPFFMAE                          ETH_PTPTSCR_TSPFFMAE_Msk  /* Time stamp PTP frame filtering MAC address enable */
15803 #define ETH_PTPTSCR_TSCNT_Pos                         (16U)
15804 #define ETH_PTPTSCR_TSCNT_Msk                         (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
15805 #define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
15806 #define ETH_PTPTSCR_TSSMRME_Pos                       (15U)
15807 #define ETH_PTPTSCR_TSSMRME_Msk                       (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
15808 #define ETH_PTPTSCR_TSSMRME                           ETH_PTPTSCR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
15809 #define ETH_PTPTSCR_TSSEME_Pos                        (14U)
15810 #define ETH_PTPTSCR_TSSEME_Msk                        (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
15811 #define ETH_PTPTSCR_TSSEME                            ETH_PTPTSCR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
15812 #define ETH_PTPTSCR_TSSIPV4FE_Pos                     (13U)
15813 #define ETH_PTPTSCR_TSSIPV4FE_Msk                     (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
15814 #define ETH_PTPTSCR_TSSIPV4FE                         ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15815 #define ETH_PTPTSCR_TSSIPV6FE_Pos                     (12U)
15816 #define ETH_PTPTSCR_TSSIPV6FE_Msk                     (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
15817 #define ETH_PTPTSCR_TSSIPV6FE                         ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15818 #define ETH_PTPTSCR_TSSPTPOEFE_Pos                    (11U)
15819 #define ETH_PTPTSCR_TSSPTPOEFE_Msk                    (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
15820 #define ETH_PTPTSCR_TSSPTPOEFE                        ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15821 #define ETH_PTPTSCR_TSPTPPSV2E_Pos                    (10U)
15822 #define ETH_PTPTSCR_TSPTPPSV2E_Msk                    (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
15823 #define ETH_PTPTSCR_TSPTPPSV2E                        ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15824 #define ETH_PTPTSCR_TSSSR_Pos                         (9U)
15825 #define ETH_PTPTSCR_TSSSR_Msk                         (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
15826 #define ETH_PTPTSCR_TSSSR                             ETH_PTPTSCR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
15827 #define ETH_PTPTSCR_TSSARFE_Pos                       (8U)
15828 #define ETH_PTPTSCR_TSSARFE_Msk                       (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
15829 #define ETH_PTPTSCR_TSSARFE                           ETH_PTPTSCR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
15830 
15831 #define ETH_PTPTSCR_TSARU_Pos                         (5U)
15832 #define ETH_PTPTSCR_TSARU_Msk                         (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
15833 #define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
15834 #define ETH_PTPTSCR_TSITE_Pos                         (4U)
15835 #define ETH_PTPTSCR_TSITE_Msk                         (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
15836 #define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
15837 #define ETH_PTPTSCR_TSSTU_Pos                         (3U)
15838 #define ETH_PTPTSCR_TSSTU_Msk                         (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
15839 #define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
15840 #define ETH_PTPTSCR_TSSTI_Pos                         (2U)
15841 #define ETH_PTPTSCR_TSSTI_Msk                         (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
15842 #define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
15843 #define ETH_PTPTSCR_TSFCU_Pos                         (1U)
15844 #define ETH_PTPTSCR_TSFCU_Msk                         (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
15845 #define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
15846 #define ETH_PTPTSCR_TSE_Pos                           (0U)
15847 #define ETH_PTPTSCR_TSE_Msk                           (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
15848 #define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
15849 
15850 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
15851 #define ETH_PTPSSIR_STSSI_Pos                         (0U)
15852 #define ETH_PTPSSIR_STSSI_Msk                         (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
15853 #define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
15854 
15855 /* Bit definition for Ethernet PTP Time Stamp High Register */
15856 #define ETH_PTPTSHR_STS_Pos                           (0U)
15857 #define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
15858 #define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
15859 
15860 /* Bit definition for Ethernet PTP Time Stamp Low Register */
15861 #define ETH_PTPTSLR_STPNS_Pos                         (31U)
15862 #define ETH_PTPTSLR_STPNS_Msk                         (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
15863 #define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
15864 #define ETH_PTPTSLR_STSS_Pos                          (0U)
15865 #define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
15866 #define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
15867 
15868 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
15869 #define ETH_PTPTSHUR_TSUS_Pos                         (0U)
15870 #define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
15871 #define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
15872 
15873 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
15874 #define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)
15875 #define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
15876 #define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
15877 #define ETH_PTPTSLUR_TSUSS_Pos                        (0U)
15878 #define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
15879 #define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
15880 
15881 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
15882 #define ETH_PTPTSAR_TSA_Pos                           (0U)
15883 #define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
15884 #define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
15885 
15886 /* Bit definition for Ethernet PTP Target Time High Register */
15887 #define ETH_PTPTTHR_TTSH_Pos                          (0U)
15888 #define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
15889 #define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
15890 
15891 /* Bit definition for Ethernet PTP Target Time Low Register */
15892 #define ETH_PTPTTLR_TTSL_Pos                          (0U)
15893 #define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
15894 #define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
15895 
15896 /* Bit definition for Ethernet PTP Time Stamp Status Register */
15897 #define ETH_PTPTSSR_TSTTR_Pos                         (5U)
15898 #define ETH_PTPTSSR_TSTTR_Msk                         (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
15899 #define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
15900 #define ETH_PTPTSSR_TSSO_Pos                          (4U)
15901 #define ETH_PTPTSSR_TSSO_Msk                          (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
15902 #define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
15903 
15904 /* Bit definition for Ethernet PTP PPS Control Register */
15905 #define ETH_PTPPPSCR_PPSFREQ_Pos                      (0U)
15906 #define ETH_PTPPPSCR_PPSFREQ_Msk                      (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15907 #define ETH_PTPPPSCR_PPSFREQ                          ETH_PTPPPSCR_PPSFREQ_Msk    /*  PPS frequency selection */
15908 
15909 /******************************************************************************/
15910 /*                 Ethernet DMA Registers bits definition                     */
15911 /******************************************************************************/
15912 
15913 /* Bit definition for Ethernet DMA Bus Mode Register */
15914 #define ETH_DMABMR_MB_Pos                             (26U)
15915 #define ETH_DMABMR_MB_Msk                             (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
15916 #define ETH_DMABMR_MB                                 ETH_DMABMR_MB_Msk       /* Mixed Burst */
15917 #define ETH_DMABMR_AAB_Pos                            (25U)
15918 #define ETH_DMABMR_AAB_Msk                            (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
15919 #define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
15920 #define ETH_DMABMR_FPM_Pos                            (24U)
15921 #define ETH_DMABMR_FPM_Msk                            (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
15922 #define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
15923 #define ETH_DMABMR_USP_Pos                            (23U)
15924 #define ETH_DMABMR_USP_Msk                            (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
15925 #define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
15926 #define ETH_DMABMR_RDP_Pos                            (17U)
15927 #define ETH_DMABMR_RDP_Msk                            (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
15928 #define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
15929 #define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
15930 #define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
15931 #define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15932 #define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15933 #define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15934 #define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15935 #define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15936 #define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15937 #define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15938 #define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15939 #define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
15940 #define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
15941 #define ETH_DMABMR_FB_Pos                             (16U)
15942 #define ETH_DMABMR_FB_Msk                             (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
15943 #define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
15944 #define ETH_DMABMR_RTPR_Pos                           (14U)
15945 #define ETH_DMABMR_RTPR_Msk                           (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
15946 #define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
15947 #define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
15948 #define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
15949 #define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
15950 #define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */
15951 #define ETH_DMABMR_PBL_Pos                            (8U)
15952 #define ETH_DMABMR_PBL_Msk                            (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
15953 #define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
15954 #define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
15955 #define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
15956 #define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15957 #define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15958 #define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15959 #define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15960 #define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15961 #define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15962 #define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15963 #define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15964 #define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
15965 #define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
15966 #define ETH_DMABMR_EDE_Pos                            (7U)
15967 #define ETH_DMABMR_EDE_Msk                            (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
15968 #define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
15969 #define ETH_DMABMR_DSL_Pos                            (2U)
15970 #define ETH_DMABMR_DSL_Msk                            (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
15971 #define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
15972 #define ETH_DMABMR_DA_Pos                             (1U)
15973 #define ETH_DMABMR_DA_Msk                             (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
15974 #define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
15975 #define ETH_DMABMR_SR_Pos                             (0U)
15976 #define ETH_DMABMR_SR_Msk                             (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
15977 #define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
15978 
15979 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
15980 #define ETH_DMATPDR_TPD_Pos                           (0U)
15981 #define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
15982 #define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
15983 
15984 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
15985 #define ETH_DMARPDR_RPD_Pos                           (0U)
15986 #define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
15987 #define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
15988 
15989 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
15990 #define ETH_DMARDLAR_SRL_Pos                          (0U)
15991 #define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
15992 #define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
15993 
15994 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
15995 #define ETH_DMATDLAR_STL_Pos                          (0U)
15996 #define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
15997 #define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
15998 
15999 /* Bit definition for Ethernet DMA Status Register */
16000 #define ETH_DMASR_TSTS_Pos                            (29U)
16001 #define ETH_DMASR_TSTS_Msk                            (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
16002 #define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
16003 #define ETH_DMASR_PMTS_Pos                            (28U)
16004 #define ETH_DMASR_PMTS_Msk                            (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
16005 #define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
16006 #define ETH_DMASR_MMCS_Pos                            (27U)
16007 #define ETH_DMASR_MMCS_Msk                            (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
16008 #define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
16009 #define ETH_DMASR_EBS_Pos                             (23U)
16010 #define ETH_DMASR_EBS_Msk                             (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
16011 #define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
16012   /* combination with EBS[2:0] for GetFlagStatus function */
16013 #define ETH_DMASR_EBS_DescAccess_Pos                  (25U)
16014 #define ETH_DMASR_EBS_DescAccess_Msk                  (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
16015 #define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
16016 #define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)
16017 #define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
16018 #define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
16019 #define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)
16020 #define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
16021 #define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
16022 #define ETH_DMASR_TPS_Pos                             (20U)
16023 #define ETH_DMASR_TPS_Msk                             (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
16024 #define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
16025 #define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
16026 #define ETH_DMASR_TPS_Fetching_Pos                    (20U)
16027 #define ETH_DMASR_TPS_Fetching_Msk                    (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
16028 #define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
16029 #define ETH_DMASR_TPS_Waiting_Pos                     (21U)
16030 #define ETH_DMASR_TPS_Waiting_Msk                     (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
16031 #define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
16032 #define ETH_DMASR_TPS_Reading_Pos                     (20U)
16033 #define ETH_DMASR_TPS_Reading_Msk                     (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
16034 #define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
16035 #define ETH_DMASR_TPS_Suspended_Pos                   (21U)
16036 #define ETH_DMASR_TPS_Suspended_Msk                   (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
16037 #define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
16038 #define ETH_DMASR_TPS_Closing_Pos                     (20U)
16039 #define ETH_DMASR_TPS_Closing_Msk                     (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
16040 #define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
16041 #define ETH_DMASR_RPS_Pos                             (17U)
16042 #define ETH_DMASR_RPS_Msk                             (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
16043 #define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
16044 #define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
16045 #define ETH_DMASR_RPS_Fetching_Pos                    (17U)
16046 #define ETH_DMASR_RPS_Fetching_Msk                    (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
16047 #define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
16048 #define ETH_DMASR_RPS_Waiting_Pos                     (17U)
16049 #define ETH_DMASR_RPS_Waiting_Msk                     (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
16050 #define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
16051 #define ETH_DMASR_RPS_Suspended_Pos                   (19U)
16052 #define ETH_DMASR_RPS_Suspended_Msk                   (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
16053 #define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
16054 #define ETH_DMASR_RPS_Closing_Pos                     (17U)
16055 #define ETH_DMASR_RPS_Closing_Msk                     (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
16056 #define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
16057 #define ETH_DMASR_RPS_Queuing_Pos                     (17U)
16058 #define ETH_DMASR_RPS_Queuing_Msk                     (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
16059 #define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
16060 #define ETH_DMASR_NIS_Pos                             (16U)
16061 #define ETH_DMASR_NIS_Msk                             (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
16062 #define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
16063 #define ETH_DMASR_AIS_Pos                             (15U)
16064 #define ETH_DMASR_AIS_Msk                             (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
16065 #define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
16066 #define ETH_DMASR_ERS_Pos                             (14U)
16067 #define ETH_DMASR_ERS_Msk                             (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
16068 #define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
16069 #define ETH_DMASR_FBES_Pos                            (13U)
16070 #define ETH_DMASR_FBES_Msk                            (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
16071 #define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
16072 #define ETH_DMASR_ETS_Pos                             (10U)
16073 #define ETH_DMASR_ETS_Msk                             (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
16074 #define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
16075 #define ETH_DMASR_RWTS_Pos                            (9U)
16076 #define ETH_DMASR_RWTS_Msk                            (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
16077 #define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
16078 #define ETH_DMASR_RPSS_Pos                            (8U)
16079 #define ETH_DMASR_RPSS_Msk                            (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
16080 #define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
16081 #define ETH_DMASR_RBUS_Pos                            (7U)
16082 #define ETH_DMASR_RBUS_Msk                            (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
16083 #define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
16084 #define ETH_DMASR_RS_Pos                              (6U)
16085 #define ETH_DMASR_RS_Msk                              (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
16086 #define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
16087 #define ETH_DMASR_TUS_Pos                             (5U)
16088 #define ETH_DMASR_TUS_Msk                             (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
16089 #define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
16090 #define ETH_DMASR_ROS_Pos                             (4U)
16091 #define ETH_DMASR_ROS_Msk                             (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
16092 #define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
16093 #define ETH_DMASR_TJTS_Pos                            (3U)
16094 #define ETH_DMASR_TJTS_Msk                            (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
16095 #define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
16096 #define ETH_DMASR_TBUS_Pos                            (2U)
16097 #define ETH_DMASR_TBUS_Msk                            (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
16098 #define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
16099 #define ETH_DMASR_TPSS_Pos                            (1U)
16100 #define ETH_DMASR_TPSS_Msk                            (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
16101 #define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
16102 #define ETH_DMASR_TS_Pos                              (0U)
16103 #define ETH_DMASR_TS_Msk                              (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
16104 #define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
16105 
16106 /* Bit definition for Ethernet DMA Operation Mode Register */
16107 #define ETH_DMAOMR_DTCEFD_Pos                         (26U)
16108 #define ETH_DMAOMR_DTCEFD_Msk                         (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
16109 #define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
16110 #define ETH_DMAOMR_RSF_Pos                            (25U)
16111 #define ETH_DMAOMR_RSF_Msk                            (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
16112 #define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
16113 #define ETH_DMAOMR_DFRF_Pos                           (24U)
16114 #define ETH_DMAOMR_DFRF_Msk                           (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
16115 #define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
16116 #define ETH_DMAOMR_TSF_Pos                            (21U)
16117 #define ETH_DMAOMR_TSF_Msk                            (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
16118 #define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
16119 #define ETH_DMAOMR_FTF_Pos                            (20U)
16120 #define ETH_DMAOMR_FTF_Msk                            (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
16121 #define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
16122 #define ETH_DMAOMR_TTC_Pos                            (14U)
16123 #define ETH_DMAOMR_TTC_Msk                            (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
16124 #define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
16125 #define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
16126 #define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
16127 #define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
16128 #define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
16129 #define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
16130 #define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
16131 #define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
16132 #define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
16133 #define ETH_DMAOMR_ST_Pos                             (13U)
16134 #define ETH_DMAOMR_ST_Msk                             (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
16135 #define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
16136 #define ETH_DMAOMR_FEF_Pos                            (7U)
16137 #define ETH_DMAOMR_FEF_Msk                            (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
16138 #define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
16139 #define ETH_DMAOMR_FUGF_Pos                           (6U)
16140 #define ETH_DMAOMR_FUGF_Msk                           (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
16141 #define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
16142 #define ETH_DMAOMR_RTC_Pos                            (3U)
16143 #define ETH_DMAOMR_RTC_Msk                            (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
16144 #define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
16145 #define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
16146 #define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
16147 #define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
16148 #define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
16149 #define ETH_DMAOMR_OSF_Pos                            (2U)
16150 #define ETH_DMAOMR_OSF_Msk                            (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
16151 #define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
16152 #define ETH_DMAOMR_SR_Pos                             (1U)
16153 #define ETH_DMAOMR_SR_Msk                             (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
16154 #define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
16155 
16156 /* Bit definition for Ethernet DMA Interrupt Enable Register */
16157 #define ETH_DMAIER_NISE_Pos                           (16U)
16158 #define ETH_DMAIER_NISE_Msk                           (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
16159 #define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
16160 #define ETH_DMAIER_AISE_Pos                           (15U)
16161 #define ETH_DMAIER_AISE_Msk                           (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
16162 #define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
16163 #define ETH_DMAIER_ERIE_Pos                           (14U)
16164 #define ETH_DMAIER_ERIE_Msk                           (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
16165 #define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
16166 #define ETH_DMAIER_FBEIE_Pos                          (13U)
16167 #define ETH_DMAIER_FBEIE_Msk                          (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
16168 #define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
16169 #define ETH_DMAIER_ETIE_Pos                           (10U)
16170 #define ETH_DMAIER_ETIE_Msk                           (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
16171 #define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
16172 #define ETH_DMAIER_RWTIE_Pos                          (9U)
16173 #define ETH_DMAIER_RWTIE_Msk                          (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
16174 #define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
16175 #define ETH_DMAIER_RPSIE_Pos                          (8U)
16176 #define ETH_DMAIER_RPSIE_Msk                          (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
16177 #define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
16178 #define ETH_DMAIER_RBUIE_Pos                          (7U)
16179 #define ETH_DMAIER_RBUIE_Msk                          (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
16180 #define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
16181 #define ETH_DMAIER_RIE_Pos                            (6U)
16182 #define ETH_DMAIER_RIE_Msk                            (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
16183 #define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
16184 #define ETH_DMAIER_TUIE_Pos                           (5U)
16185 #define ETH_DMAIER_TUIE_Msk                           (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
16186 #define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
16187 #define ETH_DMAIER_ROIE_Pos                           (4U)
16188 #define ETH_DMAIER_ROIE_Msk                           (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
16189 #define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
16190 #define ETH_DMAIER_TJTIE_Pos                          (3U)
16191 #define ETH_DMAIER_TJTIE_Msk                          (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
16192 #define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
16193 #define ETH_DMAIER_TBUIE_Pos                          (2U)
16194 #define ETH_DMAIER_TBUIE_Msk                          (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
16195 #define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
16196 #define ETH_DMAIER_TPSIE_Pos                          (1U)
16197 #define ETH_DMAIER_TPSIE_Msk                          (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
16198 #define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
16199 #define ETH_DMAIER_TIE_Pos                            (0U)
16200 #define ETH_DMAIER_TIE_Msk                            (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
16201 #define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
16202 
16203 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
16204 #define ETH_DMAMFBOCR_OFOC_Pos                        (28U)
16205 #define ETH_DMAMFBOCR_OFOC_Msk                        (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
16206 #define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
16207 #define ETH_DMAMFBOCR_MFA_Pos                         (17U)
16208 #define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
16209 #define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
16210 #define ETH_DMAMFBOCR_OMFC_Pos                        (16U)
16211 #define ETH_DMAMFBOCR_OMFC_Msk                        (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
16212 #define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
16213 #define ETH_DMAMFBOCR_MFC_Pos                         (0U)
16214 #define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
16215 #define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
16216 
16217 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
16218 #define ETH_DMACHTDR_HTDAP_Pos                        (0U)
16219 #define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
16220 #define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
16221 
16222 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
16223 #define ETH_DMACHRDR_HRDAP_Pos                        (0U)
16224 #define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
16225 #define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
16226 
16227 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
16228 #define ETH_DMACHTBAR_HTBAP_Pos                       (0U)
16229 #define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
16230 #define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
16231 
16232 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
16233 #define ETH_DMACHRBAR_HRBAP_Pos                       (0U)
16234 #define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
16235 #define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
16236 
16237 /******************************************************************************/
16238 /*                                                                            */
16239 /*                                       USB_OTG                              */
16240 /*                                                                            */
16241 /******************************************************************************/
16242 /********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
16243 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
16244 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
16245 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
16246 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
16247 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
16248 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
16249 #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
16250 #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
16251 #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
16252 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
16253 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
16254 #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
16255 #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
16256 #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
16257 #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
16258 #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
16259 #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
16260 #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
16261 #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
16262 #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
16263 #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
16264 #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
16265 #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
16266 #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
16267 #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
16268 #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
16269 #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
16270 #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
16271 #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
16272 #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
16273 #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
16274 #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
16275 #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
16276 #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
16277 #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
16278 #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
16279 #define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
16280 #define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
16281 #define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
16282 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
16283 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
16284 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
16285 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
16286 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
16287 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
16288 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
16289 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
16290 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
16291 #define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
16292 #define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
16293 #define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
16294 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
16295 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
16296 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
16297 
16298 /********************  Bit definition for USB_OTG_HCFG register  ********************/
16299 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
16300 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
16301 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
16302 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
16303 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
16304 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
16305 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
16306 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
16307 
16308 /********************  Bit definition for USB_OTG_DCFG register  ********************/
16309 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
16310 #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
16311 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
16312 #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
16313 #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
16314 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
16315 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
16316 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
16317 
16318 #define USB_OTG_DCFG_DAD_Pos                     (4U)
16319 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
16320 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
16321 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
16322 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
16323 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
16324 #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
16325 #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
16326 #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
16327 #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
16328 
16329 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
16330 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
16331 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
16332 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
16333 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
16334 
16335 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
16336 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
16337 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
16338 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
16339 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
16340 
16341 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
16342 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
16343 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
16344 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
16345 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
16346 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
16347 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
16348 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
16349 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
16350 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
16351 
16352 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
16353 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
16354 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
16355 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
16356 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
16357 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
16358 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
16359 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
16360 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
16361 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
16362 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
16363 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
16364 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
16365 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
16366 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
16367 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
16368 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
16369 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
16370 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
16371 #define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)
16372 #define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
16373 #define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */
16374 
16375 /********************  Bit definition for USB_OTG_DCTL register  ********************/
16376 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
16377 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
16378 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
16379 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
16380 #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
16381 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
16382 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
16383 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
16384 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
16385 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
16386 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
16387 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
16388 
16389 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
16390 #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
16391 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
16392 #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
16393 #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
16394 #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
16395 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
16396 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
16397 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
16398 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
16399 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
16400 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
16401 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
16402 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
16403 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
16404 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
16405 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
16406 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
16407 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
16408 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
16409 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
16410 
16411 /********************  Bit definition for USB_OTG_HFIR register  ********************/
16412 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
16413 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
16414 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
16415 
16416 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
16417 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
16418 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
16419 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
16420 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
16421 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
16422 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
16423 
16424 /********************  Bit definition for USB_OTG_DSTS register  ********************/
16425 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
16426 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
16427 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
16428 
16429 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
16430 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
16431 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
16432 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
16433 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
16434 #define USB_OTG_DSTS_EERR_Pos                    (3U)
16435 #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
16436 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
16437 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
16438 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
16439 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
16440 
16441 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
16442 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
16443 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
16444 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
16445 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
16446 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
16447 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
16448 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
16449 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
16450 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
16451 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
16452 #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
16453 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
16454 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
16455 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
16456 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
16457 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
16458 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
16459 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
16460 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
16461 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
16462 
16463 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
16464 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
16465 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
16466 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
16467 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
16468 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
16469 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
16470 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
16471 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
16472 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
16473 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
16474 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
16475 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
16476 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
16477 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
16478 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
16479 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
16480 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
16481 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
16482 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
16483 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
16484 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
16485 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
16486 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
16487 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
16488 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
16489 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
16490 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
16491 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
16492 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
16493 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
16494 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
16495 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
16496 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
16497 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
16498 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
16499 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
16500 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
16501 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
16502 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
16503 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
16504 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
16505 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
16506 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
16507 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
16508 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
16509 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
16510 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
16511 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
16512 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
16513 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
16514 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
16515 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
16516 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
16517 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
16518 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
16519 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
16520 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
16521 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
16522 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
16523 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
16524 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
16525 
16526 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
16527 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
16528 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
16529 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
16530 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
16531 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
16532 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
16533 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
16534 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
16535 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
16536 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
16537 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
16538 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
16539 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
16540 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
16541 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
16542 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
16543 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
16544 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
16545 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
16546 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
16547 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
16548 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
16549 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
16550 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
16551 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
16552 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
16553 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
16554 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
16555 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
16556 
16557 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
16558 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
16559 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
16560 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
16561 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
16562 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
16563 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
16564 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
16565 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
16566 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
16567 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
16568 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
16569 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
16570 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
16571 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
16572 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
16573 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
16574 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
16575 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
16576 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
16577 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
16578 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
16579 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
16580 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
16581 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
16582 
16583 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
16584 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
16585 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
16586 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
16587 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
16588 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
16589 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
16590 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
16591 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
16592 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
16593 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
16594 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
16595 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
16596 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
16597 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
16598 
16599 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
16600 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
16601 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
16602 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
16603 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
16604 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
16605 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
16606 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
16607 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
16608 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
16609 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
16610 
16611 /********************  Bit definition for USB_OTG_HAINT register  ********************/
16612 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
16613 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
16614 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
16615 
16616 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
16617 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
16618 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
16619 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
16620 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
16621 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
16622 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
16623 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
16624 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
16625 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask    */
16626 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
16627 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
16628 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
16629 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
16630 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
16631 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
16632 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
16633 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
16634 #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
16635 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
16636 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
16637 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
16638 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
16639 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
16640 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
16641 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
16642 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
16643 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
16644 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
16645 #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
16646 #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
16647 #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
16648 #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
16649 #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
16650 #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
16651 #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
16652 #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                           */
16653 
16654 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
16655 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
16656 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
16657 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
16658 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
16659 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
16660 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
16661 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
16662 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
16663 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
16664 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
16665 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
16666 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
16667 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
16668 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
16669 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
16670 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
16671 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
16672 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
16673 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
16674 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
16675 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
16676 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
16677 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
16678 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
16679 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
16680 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
16681 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
16682 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
16683 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
16684 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
16685 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
16686 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
16687 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
16688 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
16689 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
16690 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
16691 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
16692 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
16693 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
16694 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
16695 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
16696 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
16697 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
16698 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
16699 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
16700 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
16701 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
16702 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
16703 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
16704 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
16705 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
16706 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
16707 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
16708 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
16709 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
16710 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
16711 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
16712 #define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
16713 #define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
16714 #define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
16715 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
16716 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
16717 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
16718 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
16719 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
16720 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
16721 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
16722 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
16723 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
16724 #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
16725 #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
16726 #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
16727 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
16728 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
16729 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
16730 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
16731 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
16732 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
16733 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
16734 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
16735 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
16736 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
16737 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
16738 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
16739 
16740 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
16741 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
16742 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
16743 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
16744 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
16745 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
16746 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
16747 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
16748 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
16749 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
16750 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
16751 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
16752 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
16753 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
16754 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
16755 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
16756 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
16757 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
16758 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
16759 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
16760 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
16761 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
16762 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
16763 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
16764 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
16765 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
16766 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
16767 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
16768 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
16769 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
16770 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
16771 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
16772 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
16773 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
16774 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
16775 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
16776 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
16777 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
16778 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
16779 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
16780 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
16781 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
16782 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
16783 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
16784 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
16785 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
16786 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
16787 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
16788 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
16789 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
16790 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
16791 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
16792 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
16793 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
16794 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
16795 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
16796 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
16797 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
16798 #define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
16799 #define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
16800 #define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                       */
16801 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
16802 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
16803 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
16804 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
16805 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
16806 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
16807 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
16808 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
16809 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
16810 #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
16811 #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
16812 #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
16813 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
16814 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
16815 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
16816 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
16817 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
16818 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
16819 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
16820 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
16821 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
16822 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
16823 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
16824 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
16825 
16826 /********************  Bit definition for USB_OTG_DAINT register  ********************/
16827 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
16828 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
16829 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
16830 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
16831 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
16832 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
16833 
16834 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
16835 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
16836 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
16837 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
16838 
16839 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
16840 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
16841 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
16842 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
16843 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
16844 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
16845 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
16846 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
16847 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
16848 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
16849 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
16850 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
16851 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
16852 
16853 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
16854 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
16855 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
16856 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
16857 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
16858 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
16859 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
16860 
16861 /********************  Bit definition for OTG register  ********************/
16862 
16863 #define USB_OTG_CHNUM_Pos                        (0U)
16864 #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
16865 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
16866 #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
16867 #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
16868 #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
16869 #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
16870 #define USB_OTG_BCNT_Pos                         (4U)
16871 #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
16872 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
16873 
16874 #define USB_OTG_DPID_Pos                         (15U)
16875 #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
16876 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
16877 #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
16878 #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
16879 
16880 #define USB_OTG_PKTSTS_Pos                       (17U)
16881 #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
16882 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
16883 #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
16884 #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
16885 #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
16886 #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
16887 
16888 #define USB_OTG_EPNUM_Pos                        (0U)
16889 #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
16890 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
16891 #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
16892 #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
16893 #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
16894 #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
16895 
16896 #define USB_OTG_FRMNUM_Pos                       (21U)
16897 #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
16898 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
16899 #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
16900 #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
16901 #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
16902 #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
16903 
16904 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
16905 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
16906 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
16907 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
16908 
16909 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
16910 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
16911 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
16912 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
16913 
16914 /********************  Bit definition for OTG register  ********************/
16915 #define USB_OTG_NPTXFSA_Pos                      (0U)
16916 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
16917 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
16918 #define USB_OTG_NPTXFD_Pos                       (16U)
16919 #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
16920 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
16921 #define USB_OTG_TX0FSA_Pos                       (0U)
16922 #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
16923 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
16924 #define USB_OTG_TX0FD_Pos                        (16U)
16925 #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
16926 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
16927 
16928 /********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
16929 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
16930 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
16931 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
16932 
16933 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
16934 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
16935 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
16936 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
16937 
16938 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
16939 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
16940 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
16941 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
16942 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
16943 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
16944 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
16945 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
16946 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
16947 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
16948 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
16949 
16950 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
16951 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
16952 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
16953 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
16954 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
16955 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
16956 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
16957 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
16958 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
16959 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
16960 
16961 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
16962 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
16963 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
16964 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
16965 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
16966 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
16967 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
16968 
16969 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
16970 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
16971 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
16972 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
16973 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
16974 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
16975 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
16976 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
16977 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
16978 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
16979 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
16980 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
16981 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
16982 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
16983 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
16984 
16985 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
16986 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
16987 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
16988 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
16989 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
16990 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
16991 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
16992 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
16993 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
16994 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
16995 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
16996 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
16997 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
16998 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
16999 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
17000 
17001 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
17002 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
17003 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
17004 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
17005 
17006 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
17007 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
17008 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
17009 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
17010 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
17011 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
17012 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
17013 
17014 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
17015 #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
17016 #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
17017 #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
17018 #define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
17019 #define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
17020 #define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */
17021 
17022 /********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
17023 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
17024 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
17025 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
17026 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
17027 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
17028 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
17029 
17030 /********************  Bit definition for USB_OTG_CID register  ********************/
17031 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
17032 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
17033 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
17034 
17035 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
17036 #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
17037 #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
17038 #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
17039 #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
17040 #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
17041 #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
17042 #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
17043 #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
17044 #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
17045 #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
17046 #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
17047 #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
17048 #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
17049 #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
17050 #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
17051 #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
17052 #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
17053 #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
17054 #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
17055 #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
17056 #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
17057 #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
17058 #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
17059 #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
17060 #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
17061 #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
17062 #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
17063 #define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
17064 #define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
17065 #define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
17066 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
17067 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
17068 #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
17069 #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
17070 #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
17071 #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
17072 #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
17073 #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
17074 #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
17075 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
17076 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
17077 #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
17078 #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
17079 #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
17080 #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
17081 
17082 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
17083 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
17084 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
17085 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
17086 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
17087 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
17088 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
17089 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
17090 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
17091 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
17092 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
17093 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
17094 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
17095 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
17096 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
17097 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
17098 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
17099 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
17100 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
17101 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
17102 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
17103 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
17104 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
17105 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
17106 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
17107 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
17108 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
17109 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
17110 
17111 /********************  Bit definition for USB_OTG_HPRT register  ********************/
17112 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
17113 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
17114 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
17115 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
17116 #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
17117 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
17118 #define USB_OTG_HPRT_PENA_Pos                    (2U)
17119 #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
17120 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
17121 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
17122 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
17123 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
17124 #define USB_OTG_HPRT_POCA_Pos                    (4U)
17125 #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
17126 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
17127 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
17128 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
17129 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
17130 #define USB_OTG_HPRT_PRES_Pos                    (6U)
17131 #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
17132 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
17133 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
17134 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
17135 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
17136 #define USB_OTG_HPRT_PRST_Pos                    (8U)
17137 #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
17138 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
17139 
17140 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
17141 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
17142 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
17143 #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
17144 #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
17145 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
17146 #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
17147 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
17148 
17149 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
17150 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
17151 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
17152 #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
17153 #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
17154 #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
17155 #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
17156 
17157 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
17158 #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
17159 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
17160 #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
17161 #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
17162 
17163 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
17164 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
17165 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
17166 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
17167 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
17168 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
17169 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
17170 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
17171 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
17172 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
17173 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
17174 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
17175 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
17176 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
17177 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
17178 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
17179 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
17180 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
17181 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
17182 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
17183 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
17184 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
17185 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
17186 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
17187 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
17188 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
17189 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
17190 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
17191 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
17192 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
17193 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
17194 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
17195 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
17196 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
17197 
17198 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
17199 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
17200 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
17201 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
17202 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
17203 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
17204 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
17205 
17206 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
17207 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
17208 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
17209 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
17210 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
17211 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
17212 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
17213 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
17214 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
17215 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
17216 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
17217 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
17218 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
17219 
17220 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
17221 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
17222 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
17223 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
17224 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
17225 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
17226 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
17227 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
17228 
17229 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
17230 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
17231 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
17232 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
17233 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
17234 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
17235 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
17236 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
17237 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
17238 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
17239 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
17240 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
17241 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
17242 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
17243 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
17244 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
17245 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
17246 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
17247 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
17248 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
17249 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
17250 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
17251 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
17252 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
17253 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
17254 
17255 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
17256 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
17257 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
17258 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
17259 
17260 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
17261 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
17262 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
17263 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
17264 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
17265 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
17266 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
17267 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
17268 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
17269 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
17270 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
17271 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
17272 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
17273 
17274 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
17275 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
17276 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
17277 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
17278 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
17279 
17280 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
17281 #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
17282 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
17283 #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
17284 #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
17285 
17286 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
17287 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
17288 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
17289 #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
17290 #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
17291 #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
17292 #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
17293 #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
17294 #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
17295 #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
17296 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
17297 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
17298 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
17299 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
17300 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
17301 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
17302 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
17303 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
17304 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
17305 
17306 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
17307 
17308 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
17309 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
17310 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
17311 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
17312 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
17313 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
17314 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
17315 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
17316 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
17317 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
17318 
17319 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
17320 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
17321 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
17322 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
17323 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
17324 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
17325 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
17326 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
17327 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
17328 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
17329 
17330 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
17331 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
17332 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
17333 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
17334 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
17335 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
17336 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
17337 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
17338 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
17339 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
17340 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
17341 
17342 /********************  Bit definition for USB_OTG_HCINT register  ********************/
17343 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
17344 #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
17345 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
17346 #define USB_OTG_HCINT_CHH_Pos                    (1U)
17347 #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
17348 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
17349 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
17350 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
17351 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
17352 #define USB_OTG_HCINT_STALL_Pos                  (3U)
17353 #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
17354 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
17355 #define USB_OTG_HCINT_NAK_Pos                    (4U)
17356 #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
17357 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
17358 #define USB_OTG_HCINT_ACK_Pos                    (5U)
17359 #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
17360 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
17361 #define USB_OTG_HCINT_NYET_Pos                   (6U)
17362 #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
17363 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
17364 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
17365 #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
17366 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
17367 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
17368 #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
17369 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
17370 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
17371 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
17372 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
17373 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
17374 #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
17375 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
17376 
17377 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
17378 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
17379 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
17380 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
17381 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
17382 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
17383 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
17384 #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
17385 #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
17386 #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
17387 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
17388 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
17389 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
17390 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
17391 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
17392 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
17393 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
17394 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
17395 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
17396 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
17397 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
17398 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
17399 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
17400 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
17401 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
17402 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
17403 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
17404 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
17405 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
17406 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
17407 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
17408 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
17409 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
17410 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
17411 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
17412 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
17413 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
17414 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
17415 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
17416 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
17417 
17418 /********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
17419 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
17420 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
17421 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
17422 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
17423 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
17424 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
17425 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
17426 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
17427 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
17428 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
17429 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
17430 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
17431 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
17432 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
17433 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
17434 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
17435 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
17436 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
17437 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
17438 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
17439 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
17440 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
17441 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
17442 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
17443 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
17444 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
17445 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
17446 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
17447 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
17448 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
17449 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
17450 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
17451 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
17452 
17453 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
17454 
17455 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
17456 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17457 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
17458 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
17459 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17460 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
17461 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
17462 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
17463 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
17464 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
17465 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
17466 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17467 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
17468 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
17469 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17470 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
17471 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
17472 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
17473 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
17474 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
17475 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
17476 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
17477 #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
17478 #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
17479 
17480 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
17481 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
17482 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
17483 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
17484 
17485 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
17486 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
17487 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
17488 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
17489 
17490 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
17491 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
17492 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
17493 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
17494 
17495 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
17496 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
17497 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
17498 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
17499 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
17500 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
17501 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
17502 
17503 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
17504 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
17505 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
17506 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
17507 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
17508 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
17509 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
17510 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
17511 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
17512 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
17513 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
17514 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
17515 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
17516 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
17517 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
17518 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
17519 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
17520 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
17521 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
17522 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
17523 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
17524 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
17525 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
17526 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
17527 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
17528 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
17529 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
17530 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
17531 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
17532 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
17533 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
17534 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
17535 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
17536 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
17537 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
17538 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
17539 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
17540 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
17541 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
17542 
17543 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
17544 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
17545 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
17546 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
17547 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
17548 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
17549 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
17550 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
17551 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
17552 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
17553 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
17554 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
17555 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
17556 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
17557 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
17558 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
17559 #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
17560 #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
17561 #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
17562 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
17563 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
17564 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
17565 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
17566 #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
17567 #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
17568 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
17569 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
17570 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
17571 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
17572 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
17573 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
17574 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
17575 #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
17576 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
17577 
17578 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
17579 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
17580 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17581 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
17582 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
17583 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17584 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
17585 
17586 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
17587 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
17588 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
17589 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
17590 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
17591 
17592 /********************  Bit definition for PCGCCTL register  ********************/
17593 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
17594 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
17595 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
17596 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
17597 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
17598 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
17599 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
17600 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
17601 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
17602 
17603 
17604 
17605 
17606 /**
17607   * @}
17608   */
17609 
17610 /**
17611   * @}
17612   */
17613 
17614 /** @addtogroup Exported_macros
17615   * @{
17616   */
17617 
17618 /******************************* ADC Instances ********************************/
17619 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
17620                                        ((__INSTANCE__) == ADC2) || \
17621                                        ((__INSTANCE__) == ADC3))
17622 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
17623 
17624 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
17625 
17626 /******************************* CAN Instances ********************************/
17627 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
17628                                            ((__INSTANCE__) == CAN2))
17629 /******************************* CRC Instances ********************************/
17630 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
17631 
17632 /******************************* DAC Instances ********************************/
17633 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
17634 
17635 /******************************* DCMI Instances *******************************/
17636 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
17637 
17638 
17639 /******************************* DMA2D Instances *******************************/
17640 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
17641 
17642 /******************************** DMA Instances *******************************/
17643 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
17644                                               ((__INSTANCE__) == DMA1_Stream1) || \
17645                                               ((__INSTANCE__) == DMA1_Stream2) || \
17646                                               ((__INSTANCE__) == DMA1_Stream3) || \
17647                                               ((__INSTANCE__) == DMA1_Stream4) || \
17648                                               ((__INSTANCE__) == DMA1_Stream5) || \
17649                                               ((__INSTANCE__) == DMA1_Stream6) || \
17650                                               ((__INSTANCE__) == DMA1_Stream7) || \
17651                                               ((__INSTANCE__) == DMA2_Stream0) || \
17652                                               ((__INSTANCE__) == DMA2_Stream1) || \
17653                                               ((__INSTANCE__) == DMA2_Stream2) || \
17654                                               ((__INSTANCE__) == DMA2_Stream3) || \
17655                                               ((__INSTANCE__) == DMA2_Stream4) || \
17656                                               ((__INSTANCE__) == DMA2_Stream5) || \
17657                                               ((__INSTANCE__) == DMA2_Stream6) || \
17658                                               ((__INSTANCE__) == DMA2_Stream7))
17659 
17660 /******************************* GPIO Instances *******************************/
17661 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
17662                                             ((__INSTANCE__) == GPIOB) || \
17663                                             ((__INSTANCE__) == GPIOC) || \
17664                                             ((__INSTANCE__) == GPIOD) || \
17665                                             ((__INSTANCE__) == GPIOE) || \
17666                                             ((__INSTANCE__) == GPIOF) || \
17667                                             ((__INSTANCE__) == GPIOG) || \
17668                                             ((__INSTANCE__) == GPIOH) || \
17669                                             ((__INSTANCE__) == GPIOI) || \
17670                                             ((__INSTANCE__) == GPIOJ) || \
17671                                             ((__INSTANCE__) == GPIOK))
17672 
17673 #define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \
17674                                              ((__INSTANCE__) == GPIOB) || \
17675                                              ((__INSTANCE__) == GPIOC) || \
17676                                              ((__INSTANCE__) == GPIOD) || \
17677                                              ((__INSTANCE__) == GPIOE) || \
17678                                              ((__INSTANCE__) == GPIOF) || \
17679                                              ((__INSTANCE__) == GPIOG) || \
17680                                              ((__INSTANCE__) == GPIOH) || \
17681                                              ((__INSTANCE__) == GPIOI) || \
17682                                              ((__INSTANCE__) == GPIOJ) || \
17683                                              ((__INSTANCE__) == GPIOK))
17684 
17685 /****************************** CEC Instances *********************************/
17686 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
17687 
17688 /****************************** QSPI Instances *********************************/
17689 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
17690 
17691 
17692 /******************************** I2C Instances *******************************/
17693 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
17694                                            ((__INSTANCE__) == I2C2) || \
17695                                            ((__INSTANCE__) == I2C3) || \
17696                                            ((__INSTANCE__) == I2C4))
17697 
17698 /****************************** SMBUS Instances *******************************/
17699 #define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
17700                                              ((__INSTANCE__) == I2C2) || \
17701                                              ((__INSTANCE__) == I2C3) || \
17702                                              ((__INSTANCE__) == I2C4))
17703 
17704 
17705 /******************************** I2S Instances *******************************/
17706 #define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \
17707                                             ((__INSTANCE__) == SPI2) || \
17708                                             ((__INSTANCE__) == SPI3))
17709 
17710 /******************************* LPTIM Instances ********************************/
17711 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
17712 
17713 /****************************** LTDC Instances ********************************/
17714 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)
17715 
17716 
17717 
17718 
17719 /******************************* RNG Instances ********************************/
17720 #define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)
17721 
17722 /****************************** RTC Instances *********************************/
17723 #define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)
17724 
17725 /******************************* SAI Instances ********************************/
17726 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
17727                                          ((__PERIPH__) == SAI1_Block_B) || \
17728                                          ((__PERIPH__) == SAI2_Block_A) || \
17729                                          ((__PERIPH__) == SAI2_Block_B))
17730 /* Legacy define */
17731 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
17732 
17733 /******************************** SDMMC Instances *******************************/
17734 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
17735 
17736 /****************************** SPDIFRX Instances *********************************/
17737 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
17738 
17739 /******************************** SPI Instances *******************************/
17740 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
17741                                            ((__INSTANCE__) == SPI2) || \
17742                                            ((__INSTANCE__) == SPI3) || \
17743                                            ((__INSTANCE__) == SPI4) || \
17744                                            ((__INSTANCE__) == SPI5) || \
17745                                            ((__INSTANCE__) == SPI6))
17746 
17747 /****************** TIM Instances : All supported instances *******************/
17748 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
17749                                    ((__INSTANCE__) == TIM2)   || \
17750                                    ((__INSTANCE__) == TIM3)   || \
17751                                    ((__INSTANCE__) == TIM4)   || \
17752                                    ((__INSTANCE__) == TIM5)   || \
17753                                    ((__INSTANCE__) == TIM6)   || \
17754                                    ((__INSTANCE__) == TIM7)   || \
17755                                    ((__INSTANCE__) == TIM8)   || \
17756                                    ((__INSTANCE__) == TIM9)   || \
17757                                    ((__INSTANCE__) == TIM10)  || \
17758                                    ((__INSTANCE__) == TIM11)  || \
17759                                    ((__INSTANCE__) == TIM12)  || \
17760                                    ((__INSTANCE__) == TIM13)  || \
17761                                    ((__INSTANCE__) == TIM14))
17762 
17763 /****************** TIM Instances : supporting 32 bits counter ****************/
17764 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)   || \
17765                                                ((__INSTANCE__) == TIM5))
17766 
17767 /****************** TIM Instances : supporting the break function *************/
17768 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
17769                                             ((INSTANCE) == TIM8))
17770 
17771 /************** TIM Instances : supporting Break source selection *************/
17772 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
17773                                                ((INSTANCE) == TIM8))
17774 
17775 /****************** TIM Instances : supporting 2 break inputs *****************/
17776 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
17777                                             ((INSTANCE) == TIM8))
17778 
17779 /************* TIM Instances : at least 1 capture/compare channel *************/
17780 #define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
17781                                          ((__INSTANCE__) == TIM2)  || \
17782                                          ((__INSTANCE__) == TIM3)  || \
17783                                          ((__INSTANCE__) == TIM4)  || \
17784                                          ((__INSTANCE__) == TIM5)  || \
17785                                          ((__INSTANCE__) == TIM8)  || \
17786                                          ((__INSTANCE__) == TIM9)  || \
17787                                          ((__INSTANCE__) == TIM10) || \
17788                                          ((__INSTANCE__) == TIM11) || \
17789                                          ((__INSTANCE__) == TIM12) || \
17790                                          ((__INSTANCE__) == TIM13) || \
17791                                          ((__INSTANCE__) == TIM14))
17792 
17793 /************ TIM Instances : at least 2 capture/compare channels *************/
17794 #define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \
17795                                          ((__INSTANCE__) == TIM2)  || \
17796                                          ((__INSTANCE__) == TIM3)  || \
17797                                          ((__INSTANCE__) == TIM4)  || \
17798                                          ((__INSTANCE__) == TIM5)  || \
17799                                          ((__INSTANCE__) == TIM8)  || \
17800                                          ((__INSTANCE__) == TIM9)  || \
17801                                          ((__INSTANCE__) == TIM12))
17802 
17803 /************ TIM Instances : at least 3 capture/compare channels *************/
17804 #define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
17805                                          ((__INSTANCE__) == TIM2) || \
17806                                          ((__INSTANCE__) == TIM3) || \
17807                                          ((__INSTANCE__) == TIM4) || \
17808                                          ((__INSTANCE__) == TIM5) || \
17809                                          ((__INSTANCE__) == TIM8))
17810 
17811 /************ TIM Instances : at least 4 capture/compare channels *************/
17812 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17813                                        ((__INSTANCE__) == TIM2) || \
17814                                        ((__INSTANCE__) == TIM3) || \
17815                                        ((__INSTANCE__) == TIM4) || \
17816                                        ((__INSTANCE__) == TIM5) || \
17817                                        ((__INSTANCE__) == TIM8))
17818 
17819 /****************** TIM Instances : at least 5 capture/compare channels *******/
17820 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)   || \
17821                                          ((__INSTANCE__) == TIM8))
17822 
17823 /****************** TIM Instances : at least 6 capture/compare channels *******/
17824 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)   || \
17825                                          ((__INSTANCE__) == TIM8))
17826 
17827 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
17828 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)    (((__INSTANCE__) == TIM1)   || \
17829                                             ((__INSTANCE__) == TIM8))
17830 
17831 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
17832 #define IS_TIM_DMA_INSTANCE(__INSTANCE__)      (((__INSTANCE__) == TIM1)   || \
17833                                             ((__INSTANCE__) == TIM8)   || \
17834                                             ((__INSTANCE__) == TIM2)   || \
17835                                             ((__INSTANCE__) == TIM3)   || \
17836                                             ((__INSTANCE__) == TIM4)   || \
17837                                             ((__INSTANCE__) == TIM5)   || \
17838                                             ((__INSTANCE__) == TIM6)   || \
17839                                             ((__INSTANCE__) == TIM7))
17840 
17841 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
17842 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17843                                               ((__INSTANCE__) == TIM2) || \
17844                                               ((__INSTANCE__) == TIM3) || \
17845                                               ((__INSTANCE__) == TIM4) || \
17846                                               ((__INSTANCE__) == TIM5) || \
17847                                               ((__INSTANCE__) == TIM8))
17848 
17849 /******************** TIM Instances : DMA burst feature ***********************/
17850 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
17851                                              ((__INSTANCE__) == TIM2) || \
17852                                              ((__INSTANCE__) == TIM3) || \
17853                                              ((__INSTANCE__) == TIM4) || \
17854                                              ((__INSTANCE__) == TIM5) || \
17855                                              ((__INSTANCE__) == TIM8))
17856 
17857 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
17858 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
17859                                        (((__INSTANCE__) == TIM1)    || \
17860                                         ((__INSTANCE__) == TIM8))
17861 
17862 /****************** TIM Instances : supporting counting mode selection ********/
17863 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
17864                                                         ((__INSTANCE__) == TIM2) || \
17865                                                         ((__INSTANCE__) == TIM3) || \
17866                                                         ((__INSTANCE__) == TIM4) || \
17867                                                         ((__INSTANCE__) == TIM5) || \
17868                                                         ((__INSTANCE__) == TIM8))
17869 
17870 /****************** TIM Instances : supporting encoder interface **************/
17871 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
17872                                                       ((__INSTANCE__) == TIM2)  || \
17873                                                       ((__INSTANCE__) == TIM3)  || \
17874                                                       ((__INSTANCE__) == TIM4)  || \
17875                                                       ((__INSTANCE__) == TIM5)  || \
17876                                                       ((__INSTANCE__) == TIM8))
17877 
17878 /****************** TIM Instances : supporting OCxREF clear *******************/
17879 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
17880                                   (((__INSTANCE__) == TIM2)    || \
17881                                    ((__INSTANCE__) == TIM3)    || \
17882                                    ((__INSTANCE__) == TIM4)    || \
17883                                    ((__INSTANCE__) == TIM5))
17884 
17885 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
17886 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
17887                                                  (((__INSTANCE__) == TIM1)    || \
17888                                                   ((__INSTANCE__) == TIM2)    || \
17889                                                   ((__INSTANCE__) == TIM3)    || \
17890                                                   ((__INSTANCE__) == TIM4)    || \
17891                                                   ((__INSTANCE__) == TIM5)    || \
17892                                                   ((__INSTANCE__) == TIM8))
17893 
17894 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
17895 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
17896                                                    (((__INSTANCE__) == TIM1)    || \
17897                                                     ((__INSTANCE__) == TIM2)    || \
17898                                                     ((__INSTANCE__) == TIM3)    || \
17899                                                     ((__INSTANCE__) == TIM4)    || \
17900                                                     ((__INSTANCE__) == TIM5)    || \
17901                                                     ((__INSTANCE__) == TIM8))
17902 
17903 /******************** TIM Instances : Advanced-control timers *****************/
17904 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17905                                             ((__INSTANCE__) == TIM8))
17906 
17907 /******************* TIM Instances : Timer input XOR function *****************/
17908 #define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \
17909                                          ((__INSTANCE__) == TIM2) || \
17910                                          ((__INSTANCE__) == TIM3) || \
17911                                          ((__INSTANCE__) == TIM4) || \
17912                                          ((__INSTANCE__) == TIM5) || \
17913                                          ((__INSTANCE__) == TIM8))
17914 
17915 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
17916 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17917                                           ((__INSTANCE__) == TIM2) || \
17918                                           ((__INSTANCE__) == TIM3) || \
17919                                           ((__INSTANCE__) == TIM4) || \
17920                                           ((__INSTANCE__) == TIM5) || \
17921                                           ((__INSTANCE__) == TIM6) || \
17922                                           ((__INSTANCE__) == TIM7) || \
17923                                           ((__INSTANCE__) == TIM8))
17924 
17925 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
17926 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17927                                          ((__INSTANCE__) == TIM2) || \
17928                                          ((__INSTANCE__) == TIM3) || \
17929                                          ((__INSTANCE__) == TIM4) || \
17930                                          ((__INSTANCE__) == TIM5) || \
17931                                          ((__INSTANCE__) == TIM8) || \
17932                                          ((__INSTANCE__) == TIM9) || \
17933                                          ((__INSTANCE__) == TIM12))
17934 
17935 /***************** TIM Instances : external trigger input available ************/
17936 #define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \
17937                                         ((__INSTANCE__) == TIM2) || \
17938                                         ((__INSTANCE__) == TIM3) || \
17939                                         ((__INSTANCE__) == TIM4) || \
17940                                         ((__INSTANCE__) == TIM5) || \
17941                                         ((__INSTANCE__) == TIM8))
17942 
17943 /****************** TIM Instances : remapping capability **********************/
17944 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \
17945                                          ((__INSTANCE__) == TIM5)  || \
17946                                          ((__INSTANCE__) == TIM11))
17947 
17948 /******************* TIM Instances : output(s) available **********************/
17949 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
17950     ((((__INSTANCE__) == TIM1) &&                  \
17951      (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
17952       ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
17953       ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
17954       ((__CHANNEL__) == TIM_CHANNEL_4) ||          \
17955       ((__CHANNEL__) == TIM_CHANNEL_5) ||          \
17956       ((__CHANNEL__) == TIM_CHANNEL_6)))           \
17957     ||                                         \
17958     (((__INSTANCE__) == TIM2) &&                   \
17959      (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
17960       ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
17961       ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
17962       ((__CHANNEL__) == TIM_CHANNEL_4)))           \
17963     ||                                         \
17964     (((__INSTANCE__) == TIM3) &&                   \
17965      (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
17966       ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
17967       ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
17968       ((__CHANNEL__) == TIM_CHANNEL_4)))           \
17969     ||                                         \
17970     (((__INSTANCE__) == TIM4) &&                   \
17971      (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
17972       ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
17973       ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
17974       ((__CHANNEL__) == TIM_CHANNEL_4)))           \
17975     ||                                         \
17976     (((__INSTANCE__) == TIM5) &&                   \
17977      (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
17978       ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
17979       ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
17980       ((__CHANNEL__) == TIM_CHANNEL_4)))           \
17981     ||                                         \
17982     (((__INSTANCE__) == TIM8) &&                   \
17983      (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
17984       ((__CHANNEL__) == TIM_CHANNEL_2) ||          \
17985       ((__CHANNEL__) == TIM_CHANNEL_3) ||          \
17986       ((__CHANNEL__) == TIM_CHANNEL_4) ||          \
17987       ((__CHANNEL__) == TIM_CHANNEL_5) ||          \
17988       ((__CHANNEL__) == TIM_CHANNEL_6)))           \
17989     ||                                         \
17990     (((__INSTANCE__) == TIM9) &&                   \
17991      (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
17992       ((__CHANNEL__) == TIM_CHANNEL_2)))           \
17993     ||                                         \
17994     (((__INSTANCE__) == TIM10) &&                  \
17995      (((__CHANNEL__) == TIM_CHANNEL_1)))           \
17996     ||                                         \
17997     (((__INSTANCE__) == TIM11) &&                  \
17998      (((__CHANNEL__) == TIM_CHANNEL_1)))           \
17999     ||                                         \
18000     (((__INSTANCE__) == TIM12) &&                  \
18001      (((__CHANNEL__) == TIM_CHANNEL_1) ||          \
18002       ((__CHANNEL__) == TIM_CHANNEL_2)))           \
18003     ||                                         \
18004     (((__INSTANCE__) == TIM13) &&                  \
18005      (((__CHANNEL__) == TIM_CHANNEL_1)))           \
18006     ||                                         \
18007     (((__INSTANCE__) == TIM14) &&                  \
18008      (((__CHANNEL__) == TIM_CHANNEL_1))))
18009 
18010 /************ TIM Instances : complementary output(s) available ***************/
18011 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
18012    ((((__INSTANCE__) == TIM1) &&                    \
18013      (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
18014       ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
18015       ((__CHANNEL__) == TIM_CHANNEL_3)))            \
18016     ||                                          \
18017     (((__INSTANCE__) == TIM8) &&                    \
18018      (((__CHANNEL__) == TIM_CHANNEL_1) ||           \
18019       ((__CHANNEL__) == TIM_CHANNEL_2) ||           \
18020       ((__CHANNEL__) == TIM_CHANNEL_3))))
18021 
18022 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
18023 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
18024   (((__INSTANCE__) == TIM1)    || \
18025    ((__INSTANCE__) == TIM8) )
18026 
18027 /****************** TIM Instances : supporting clock division *****************/
18028 #define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)    || \
18029                                                     ((__INSTANCE__) == TIM2)    || \
18030                                                     ((__INSTANCE__) == TIM3)    || \
18031                                                     ((__INSTANCE__) == TIM4)    || \
18032                                                     ((__INSTANCE__) == TIM5)    || \
18033                                                     ((__INSTANCE__) == TIM8)    || \
18034                                                     ((__INSTANCE__) == TIM9)    || \
18035                                                     ((__INSTANCE__) == TIM10)   || \
18036                                                     ((__INSTANCE__) == TIM11)   || \
18037                                                     ((__INSTANCE__) == TIM12)   || \
18038                                                     ((__INSTANCE__) == TIM13)   || \
18039                                                     ((__INSTANCE__) == TIM14))
18040 
18041 /****************** TIM Instances : supporting repetition counter *************/
18042 #define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
18043                                                         ((__INSTANCE__) == TIM8))
18044 
18045 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
18046 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
18047                                                         ((__INSTANCE__) == TIM2) || \
18048                                                         ((__INSTANCE__) == TIM3) || \
18049                                                         ((__INSTANCE__) == TIM4) || \
18050                                                         ((__INSTANCE__) == TIM5) || \
18051                                                         ((__INSTANCE__) == TIM8) || \
18052                                                         ((__INSTANCE__) == TIM9) || \
18053                                                         ((__INSTANCE__) == TIM12))
18054 
18055 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
18056 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
18057                                                         ((__INSTANCE__) == TIM2) || \
18058                                                         ((__INSTANCE__) == TIM3) || \
18059                                                         ((__INSTANCE__) == TIM4) || \
18060                                                         ((__INSTANCE__) == TIM5) || \
18061                                                         ((__INSTANCE__) == TIM8))
18062 
18063 /****************** TIM Instances : supporting Hall sensor interface **********/
18064 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
18065                                                          ((__INSTANCE__) == TIM2)   || \
18066                                                          ((__INSTANCE__) == TIM3)   || \
18067                                                          ((__INSTANCE__) == TIM4)   || \
18068                                                          ((__INSTANCE__) == TIM5)   || \
18069                                                          ((__INSTANCE__) == TIM8))
18070 
18071 /****************** TIM Instances : supporting commutation event generation ***/
18072 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \
18073                                                          ((__INSTANCE__) == TIM8))
18074 
18075 /******************** USART Instances : Synchronous mode **********************/
18076 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18077                                          ((__INSTANCE__) == USART2) || \
18078                                          ((__INSTANCE__) == USART3) || \
18079                                          ((__INSTANCE__) == USART6))
18080 
18081 /******************** UART Instances : Asynchronous mode **********************/
18082 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18083                                     ((__INSTANCE__) == USART2) || \
18084                                     ((__INSTANCE__) == USART3) || \
18085                                     ((__INSTANCE__) == UART4)  || \
18086                                     ((__INSTANCE__) == UART5)  || \
18087                                     ((__INSTANCE__) == USART6) || \
18088                                     ((__INSTANCE__) == UART7)  || \
18089                                     ((__INSTANCE__) == UART8))
18090 
18091 /****************** UART Instances : Auto Baud Rate detection ****************/
18092 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18093                                     ((__INSTANCE__) == USART2) || \
18094                                     ((__INSTANCE__) == USART3) || \
18095                                     ((__INSTANCE__) == USART6))
18096 
18097 /****************** UART Instances : Driver Enable *****************/
18098 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18099                                     ((__INSTANCE__) == USART2) || \
18100                                     ((__INSTANCE__) == USART3) || \
18101                                     ((__INSTANCE__) == UART4)  || \
18102                                     ((__INSTANCE__) == UART5)  || \
18103                                     ((__INSTANCE__) == USART6) || \
18104                                     ((__INSTANCE__) == UART7)  || \
18105                                     ((__INSTANCE__) == UART8))
18106 
18107 /******************** UART Instances : Half-Duplex mode **********************/
18108 #define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == USART1) || \
18109                                     ((__INSTANCE__) == USART2) || \
18110                                     ((__INSTANCE__) == USART3) || \
18111                                     ((__INSTANCE__) == UART4)  || \
18112                                     ((__INSTANCE__) == UART5)  || \
18113                                     ((__INSTANCE__) == USART6) || \
18114                                     ((__INSTANCE__) == UART7)  || \
18115                                     ((__INSTANCE__) == UART8))
18116 
18117 /****************** UART Instances : Hardware Flow control ********************/
18118 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18119                                     ((__INSTANCE__) == USART2) || \
18120                                     ((__INSTANCE__) == USART3) || \
18121                                     ((__INSTANCE__) == UART4)  || \
18122                                     ((__INSTANCE__) == UART5)  || \
18123                                     ((__INSTANCE__) == USART6) || \
18124                                     ((__INSTANCE__) == UART7)  || \
18125                                     ((__INSTANCE__) == UART8))
18126 
18127 /******************** UART Instances : LIN mode **********************/
18128 #define IS_UART_LIN_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == USART1) || \
18129                                     ((__INSTANCE__) == USART2) || \
18130                                     ((__INSTANCE__) == USART3) || \
18131                                     ((__INSTANCE__) == UART4)  || \
18132                                     ((__INSTANCE__) == UART5)  || \
18133                                     ((__INSTANCE__) == USART6) || \
18134                                     ((__INSTANCE__) == UART7)  || \
18135                                     ((__INSTANCE__) == UART8))
18136 
18137 /********************* UART Instances : Smart card mode ***********************/
18138 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18139                                          ((__INSTANCE__) == USART2) || \
18140                                          ((__INSTANCE__) == USART3) || \
18141                                          ((__INSTANCE__) == USART6))
18142 
18143 /*********************** UART Instances : IRDA mode ***************************/
18144 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18145                                     ((__INSTANCE__) == USART2) || \
18146                                     ((__INSTANCE__) == USART3) || \
18147                                     ((__INSTANCE__) == UART4)  || \
18148                                     ((__INSTANCE__) == UART5)  || \
18149                                     ((__INSTANCE__) == USART6) || \
18150                                     ((__INSTANCE__) == UART7)  || \
18151                                     ((__INSTANCE__) == UART8))
18152 
18153 /****************************** IWDG Instances ********************************/
18154 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)
18155 
18156 /****************************** WWDG Instances ********************************/
18157 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)
18158 
18159 /*********************** PCD Instances ****************************************/
18160 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
18161                                        ((INSTANCE) == USB_OTG_HS))
18162 
18163 /*********************** HCD Instances ****************************************/
18164 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
18165                                        ((INSTANCE) == USB_OTG_HS))
18166 
18167 /******************************************************************************/
18168 /*  For a painless codes migration between the STM32F7xx device product       */
18169 /*  lines, the aliases defined below are put in place to overcome the         */
18170 /*  differences in the interrupt handlers and IRQn definitions.               */
18171 /*  No need to update developed interrupt code when moving across             */
18172 /*  product lines within the same STM32F7 Family                              */
18173 /******************************************************************************/
18174 
18175 /* Aliases for __IRQn */
18176 #define RNG_IRQn              HASH_RNG_IRQn
18177 
18178 /* Aliases for __IRQHandler */
18179 #define RNG_IRQHandler        HASH_RNG_IRQHandler
18180 
18181 /**
18182   * @}
18183   */
18184 
18185 /**
18186   * @}
18187   */
18188 
18189 /**
18190   * @}
18191   */
18192 
18193 #ifdef __cplusplus
18194 }
18195 #endif /* __cplusplus */
18196 
18197 #endif /* __STM32F756xx_H */
18198 
18199 
18200