1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F4xx_LL_TIM_H
21 #define __STM32F4xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U /* 6: TIMx_CH4 */
54 };
55
56 static const uint8_t SHIFT_TAB_OCxx[] =
57 {
58 0U, /* 0: OC1M, OC1FE, OC1PE */
59 0U, /* 1: - NA */
60 8U, /* 2: OC2M, OC2FE, OC2PE */
61 0U, /* 3: - NA */
62 0U, /* 4: OC3M, OC3FE, OC3PE */
63 0U, /* 5: - NA */
64 8U /* 6: OC4M, OC4FE, OC4PE */
65 };
66
67 static const uint8_t SHIFT_TAB_ICxx[] =
68 {
69 0U, /* 0: CC1S, IC1PSC, IC1F */
70 0U, /* 1: - NA */
71 8U, /* 2: CC2S, IC2PSC, IC2F */
72 0U, /* 3: - NA */
73 0U, /* 4: CC3S, IC3PSC, IC3F */
74 0U, /* 5: - NA */
75 8U /* 6: CC4S, IC4PSC, IC4F */
76 };
77
78 static const uint8_t SHIFT_TAB_CCxP[] =
79 {
80 0U, /* 0: CC1P */
81 2U, /* 1: CC1NP */
82 4U, /* 2: CC2P */
83 6U, /* 3: CC2NP */
84 8U, /* 4: CC3P */
85 10U, /* 5: CC3NP */
86 12U /* 6: CC4P */
87 };
88
89 static const uint8_t SHIFT_TAB_OISx[] =
90 {
91 0U, /* 0: OIS1 */
92 1U, /* 1: OIS1N */
93 2U, /* 2: OIS2 */
94 3U, /* 3: OIS2N */
95 4U, /* 4: OIS3 */
96 5U, /* 5: OIS3N */
97 6U /* 6: OIS4 */
98 };
99 /**
100 * @}
101 */
102
103 /* Private constants ---------------------------------------------------------*/
104 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
105 * @{
106 */
107
108
109 /* Remap mask definitions */
110 #define TIMx_OR_RMP_SHIFT 16U
111 #define TIMx_OR_RMP_MASK 0x0000FFFFU
112 #define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
113 #define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
114 #define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
115
116 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
117 #define DT_DELAY_1 ((uint8_t)0x7F)
118 #define DT_DELAY_2 ((uint8_t)0x3F)
119 #define DT_DELAY_3 ((uint8_t)0x1F)
120 #define DT_DELAY_4 ((uint8_t)0x1F)
121
122 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
123 #define DT_RANGE_1 ((uint8_t)0x00)
124 #define DT_RANGE_2 ((uint8_t)0x80)
125 #define DT_RANGE_3 ((uint8_t)0xC0)
126 #define DT_RANGE_4 ((uint8_t)0xE0)
127
128
129 /**
130 * @}
131 */
132
133 /* Private macros ------------------------------------------------------------*/
134 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
135 * @{
136 */
137 /** @brief Convert channel id into channel index.
138 * @param __CHANNEL__ This parameter can be one of the following values:
139 * @arg @ref LL_TIM_CHANNEL_CH1
140 * @arg @ref LL_TIM_CHANNEL_CH1N
141 * @arg @ref LL_TIM_CHANNEL_CH2
142 * @arg @ref LL_TIM_CHANNEL_CH2N
143 * @arg @ref LL_TIM_CHANNEL_CH3
144 * @arg @ref LL_TIM_CHANNEL_CH3N
145 * @arg @ref LL_TIM_CHANNEL_CH4
146 * @retval none
147 */
148 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
149 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
150 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
151 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
152 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
153 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
154 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
155
156 /** @brief Calculate the deadtime sampling period(in ps).
157 * @param __TIMCLK__ timer input clock frequency (in Hz).
158 * @param __CKD__ This parameter can be one of the following values:
159 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
160 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
161 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
162 * @retval none
163 */
164 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
165 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
166 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
167 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
168 /**
169 * @}
170 */
171
172
173 /* Exported types ------------------------------------------------------------*/
174 #if defined(USE_FULL_LL_DRIVER)
175 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
176 * @{
177 */
178
179 /**
180 * @brief TIM Time Base configuration structure definition.
181 */
182 typedef struct
183 {
184 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
185 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
186
187 This feature can be modified afterwards using unitary function
188 @ref LL_TIM_SetPrescaler().*/
189
190 uint32_t CounterMode; /*!< Specifies the counter mode.
191 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
192
193 This feature can be modified afterwards using unitary function
194 @ref LL_TIM_SetCounterMode().*/
195
196 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
197 Auto-Reload Register at the next update event.
198 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
199 Some timer instances may support 32 bits counters. In that case this parameter must
200 be a number between 0x0000 and 0xFFFFFFFF.
201
202 This feature can be modified afterwards using unitary function
203 @ref LL_TIM_SetAutoReload().*/
204
205 uint32_t ClockDivision; /*!< Specifies the clock division.
206 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
207
208 This feature can be modified afterwards using unitary function
209 @ref LL_TIM_SetClockDivision().*/
210
211 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
212 reaches zero, an update event is generated and counting restarts
213 from the RCR value (N).
214 This means in PWM mode that (N+1) corresponds to:
215 - the number of PWM periods in edge-aligned mode
216 - the number of half PWM period in center-aligned mode
217 GP timers: this parameter must be a number between Min_Data = 0x00 and
218 Max_Data = 0xFF.
219 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
220 Max_Data = 0xFFFF.
221
222 This feature can be modified afterwards using unitary function
223 @ref LL_TIM_SetRepetitionCounter().*/
224 } LL_TIM_InitTypeDef;
225
226 /**
227 * @brief TIM Output Compare configuration structure definition.
228 */
229 typedef struct
230 {
231 uint32_t OCMode; /*!< Specifies the output mode.
232 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
233
234 This feature can be modified afterwards using unitary function
235 @ref LL_TIM_OC_SetMode().*/
236
237 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
238 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
239
240 This feature can be modified afterwards using unitary functions
241 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
242
243 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
244 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
245
246 This feature can be modified afterwards using unitary functions
247 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
248
249 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
250 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
251
252 This feature can be modified afterwards using unitary function
253 LL_TIM_OC_SetCompareCHx (x=1..6).*/
254
255 uint32_t OCPolarity; /*!< Specifies the output polarity.
256 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
257
258 This feature can be modified afterwards using unitary function
259 @ref LL_TIM_OC_SetPolarity().*/
260
261 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
262 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_OC_SetPolarity().*/
266
267
268 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
269 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
270
271 This feature can be modified afterwards using unitary function
272 @ref LL_TIM_OC_SetIdleState().*/
273
274 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
275 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
276
277 This feature can be modified afterwards using unitary function
278 @ref LL_TIM_OC_SetIdleState().*/
279 } LL_TIM_OC_InitTypeDef;
280
281 /**
282 * @brief TIM Input Capture configuration structure definition.
283 */
284
285 typedef struct
286 {
287
288 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
289 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
290
291 This feature can be modified afterwards using unitary function
292 @ref LL_TIM_IC_SetPolarity().*/
293
294 uint32_t ICActiveInput; /*!< Specifies the input.
295 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
296
297 This feature can be modified afterwards using unitary function
298 @ref LL_TIM_IC_SetActiveInput().*/
299
300 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
301 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
302
303 This feature can be modified afterwards using unitary function
304 @ref LL_TIM_IC_SetPrescaler().*/
305
306 uint32_t ICFilter; /*!< Specifies the input capture filter.
307 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
308
309 This feature can be modified afterwards using unitary function
310 @ref LL_TIM_IC_SetFilter().*/
311 } LL_TIM_IC_InitTypeDef;
312
313
314 /**
315 * @brief TIM Encoder interface configuration structure definition.
316 */
317 typedef struct
318 {
319 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
320 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
321
322 This feature can be modified afterwards using unitary function
323 @ref LL_TIM_SetEncoderMode().*/
324
325 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
326 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
327
328 This feature can be modified afterwards using unitary function
329 @ref LL_TIM_IC_SetPolarity().*/
330
331 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
332 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
333
334 This feature can be modified afterwards using unitary function
335 @ref LL_TIM_IC_SetActiveInput().*/
336
337 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
338 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
339
340 This feature can be modified afterwards using unitary function
341 @ref LL_TIM_IC_SetPrescaler().*/
342
343 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
344 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
345
346 This feature can be modified afterwards using unitary function
347 @ref LL_TIM_IC_SetFilter().*/
348
349 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
350 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_IC_SetPolarity().*/
354
355 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
356 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_IC_SetActiveInput().*/
360
361 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
362 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetPrescaler().*/
366
367 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
368 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetFilter().*/
372
373 } LL_TIM_ENCODER_InitTypeDef;
374
375 /**
376 * @brief TIM Hall sensor interface configuration structure definition.
377 */
378 typedef struct
379 {
380
381 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
382 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
383
384 This feature can be modified afterwards using unitary function
385 @ref LL_TIM_IC_SetPolarity().*/
386
387 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
388 Prescaler must be set to get a maximum counter period longer than the
389 time interval between 2 consecutive changes on the Hall inputs.
390 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
391
392 This feature can be modified afterwards using unitary function
393 @ref LL_TIM_IC_SetPrescaler().*/
394
395 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
396 This parameter can be a value of
397 @ref TIM_LL_EC_IC_FILTER.
398
399 This feature can be modified afterwards using unitary function
400 @ref LL_TIM_IC_SetFilter().*/
401
402 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
403 A positive pulse (TRGO event) is generated with a programmable delay every time
404 a change occurs on the Hall inputs.
405 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
406
407 This feature can be modified afterwards using unitary function
408 @ref LL_TIM_OC_SetCompareCH2().*/
409 } LL_TIM_HALLSENSOR_InitTypeDef;
410
411 /**
412 * @brief BDTR (Break and Dead Time) structure definition
413 */
414 typedef struct
415 {
416 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
417 This parameter can be a value of @ref TIM_LL_EC_OSSR
418
419 This feature can be modified afterwards using unitary function
420 @ref LL_TIM_SetOffStates()
421
422 @note This bit-field cannot be modified as long as LOCK level 2 has been
423 programmed. */
424
425 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
426 This parameter can be a value of @ref TIM_LL_EC_OSSI
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_SetOffStates()
430
431 @note This bit-field cannot be modified as long as LOCK level 2 has been
432 programmed. */
433
434 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
435 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
436
437 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
438 register has been written, their content is frozen until the next reset.*/
439
440 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
441 switching-on of the outputs.
442 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
443
444 This feature can be modified afterwards using unitary function
445 @ref LL_TIM_OC_SetDeadTime()
446
447 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
448 programmed. */
449
450 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
451 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
452
453 This feature can be modified afterwards using unitary functions
454 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
455
456 @note This bit-field can not be modified as long as LOCK level 1 has been
457 programmed. */
458
459 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
460 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
461
462 This feature can be modified afterwards using unitary function
463 @ref LL_TIM_ConfigBRK()
464
465 @note This bit-field can not be modified as long as LOCK level 1 has been
466 programmed. */
467
468 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
469 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
470
471 This feature can be modified afterwards using unitary functions
472 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
473
474 @note This bit-field can not be modified as long as LOCK level 1 has been
475 programmed. */
476 } LL_TIM_BDTR_InitTypeDef;
477
478 /**
479 * @}
480 */
481 #endif /* USE_FULL_LL_DRIVER */
482
483 /* Exported constants --------------------------------------------------------*/
484 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
485 * @{
486 */
487
488 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
489 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
490 * @{
491 */
492 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
493 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
494 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
495 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
496 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
497 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
498 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
499 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
500 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
501 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
502 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
503 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
504 /**
505 * @}
506 */
507
508 #if defined(USE_FULL_LL_DRIVER)
509 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
510 * @{
511 */
512 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
513 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
514 /**
515 * @}
516 */
517
518 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
519 * @{
520 */
521 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
522 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
523 /**
524 * @}
525 */
526 #endif /* USE_FULL_LL_DRIVER */
527
528 /** @defgroup TIM_LL_EC_IT IT Defines
529 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
530 * @{
531 */
532 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
533 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
534 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
535 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
536 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
537 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
538 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
539 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
540 /**
541 * @}
542 */
543
544 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
545 * @{
546 */
547 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
548 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
549 /**
550 * @}
551 */
552
553 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
554 * @{
555 */
556 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
557 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
558 /**
559 * @}
560 */
561
562 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
563 * @{
564 */
565 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
566 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
567 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
568 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
569 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
570 /**
571 * @}
572 */
573
574 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
575 * @{
576 */
577 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
578 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
579 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
580 /**
581 * @}
582 */
583
584 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
585 * @{
586 */
587 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
588 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
589 /**
590 * @}
591 */
592
593 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
594 * @{
595 */
596 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
597 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
598 /**
599 * @}
600 */
601
602 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
603 * @{
604 */
605 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
606 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
612 * @{
613 */
614 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
615 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
616 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
617 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
618 /**
619 * @}
620 */
621
622 /** @defgroup TIM_LL_EC_CHANNEL Channel
623 * @{
624 */
625 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
626 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
627 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
628 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
629 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
630 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
631 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
632 /**
633 * @}
634 */
635
636 #if defined(USE_FULL_LL_DRIVER)
637 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
638 * @{
639 */
640 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
641 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
642 /**
643 * @}
644 */
645 #endif /* USE_FULL_LL_DRIVER */
646
647 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
648 * @{
649 */
650 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
651 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
652 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
653 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
654 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
655 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
656 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
657 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
663 * @{
664 */
665 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
666 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
672 * @{
673 */
674 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
675 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
676 /**
677 * @}
678 */
679
680
681 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
682 * @{
683 */
684 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
685 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
686 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
692 * @{
693 */
694 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
695 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
696 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
697 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
703 * @{
704 */
705 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
706 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
707 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
708 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
709 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
710 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
711 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
712 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
713 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
714 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
715 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
716 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
717 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
718 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
719 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
720 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
721 /**
722 * @}
723 */
724
725 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
726 * @{
727 */
728 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
729 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
730 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
731 /**
732 * @}
733 */
734
735 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
736 * @{
737 */
738 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
739 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
740 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
741 /**
742 * @}
743 */
744
745 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
746 * @{
747 */
748 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
749 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
750 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
751 /**
752 * @}
753 */
754
755 /** @defgroup TIM_LL_EC_TRGO Trigger Output
756 * @{
757 */
758 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
759 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
760 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
761 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
762 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
763 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
764 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
765 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
766 /**
767 * @}
768 */
769
770
771 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
772 * @{
773 */
774 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
775 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
776 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
777 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
778 /**
779 * @}
780 */
781
782 /** @defgroup TIM_LL_EC_TS Trigger Selection
783 * @{
784 */
785 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
786 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
787 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
788 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
789 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
790 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
791 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
792 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
793 /**
794 * @}
795 */
796
797 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
798 * @{
799 */
800 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
801 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
802 /**
803 * @}
804 */
805
806 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
807 * @{
808 */
809 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
810 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
811 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
812 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
813 /**
814 * @}
815 */
816
817 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
818 * @{
819 */
820 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
821 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
822 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
823 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
824 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
825 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
826 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
827 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
828 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
829 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
830 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
831 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
832 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
833 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
834 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
835 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
836 /**
837 * @}
838 */
839
840
841 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
842 * @{
843 */
844 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
845 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
846 /**
847 * @}
848 */
849
850
851
852
853 /** @defgroup TIM_LL_EC_OSSI OSSI
854 * @{
855 */
856 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
857 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
858 /**
859 * @}
860 */
861
862 /** @defgroup TIM_LL_EC_OSSR OSSR
863 * @{
864 */
865 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
866 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
867 /**
868 * @}
869 */
870
871
872 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
873 * @{
874 */
875 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
876 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
877 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
878 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
879 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
880 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
881 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
882 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
883 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
884 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
885 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
886 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
887 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
888 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
889 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
890 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
891 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
892 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
893 /**
894 * @}
895 */
896
897 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
898 * @{
899 */
900 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
901 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
902 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
903 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
904 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
905 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
906 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
907 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
908 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
909 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
910 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
911 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
912 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
913 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
914 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
915 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
916 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
917 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
918 /**
919 * @}
920 */
921
922
923 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
924 * @{
925 */
926 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
927 #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
928 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
929 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
930 /**
931 * @}
932 */
933
934 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
935 * @{
936 */
937 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
938 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
939 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
940 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
941 /**
942 * @}
943 */
944
945 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
946 * @{
947 */
948 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
949 #if defined(SPDIFRX)
950 #define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
951
952 /* Legacy define */
953 #define LL_TIM_TIM11_TI1_RMP_GPIO1 LL_TIM_TIM11_TI1_RMP_SPDIFRX /*!< Legacy define for LL_TIM_TIM11_TI1_RMP_SPDIFRX */
954
955 #else
956 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
957 #endif /* SPDIFRX */
958 #define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
959 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */
960 /**
961 * @}
962 */
963 #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
964
965 #define LL_TIM_LPTIM_REMAP_MASK 0x10000000U
966
967 #define LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM9_ITR1 is connected to TIM3 TRGO */
968 #define LL_TIM_TIM9_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9_ITR1 is connected to LPTIM1 output */
969
970 #define LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM5_ITR1 is connected to TIM3 TRGO */
971 #define LL_TIM_TIM5_ITR1_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5_ITR1 is connected to LPTIM1 output */
972
973 #define LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO LL_TIM_LPTIM_REMAP_MASK /*!< TIM1_ITR2 is connected to TIM3 TRGO */
974 #define LL_TIM_TIM1_ITR2_RMP_LPTIM (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1_ITR2 is connected to LPTIM1 output */
975
976 #endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
977
978
979 /**
980 * @}
981 */
982
983 /* Exported macro ------------------------------------------------------------*/
984 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
985 * @{
986 */
987
988 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
989 * @{
990 */
991 /**
992 * @brief Write a value in TIM register.
993 * @param __INSTANCE__ TIM Instance
994 * @param __REG__ Register to be written
995 * @param __VALUE__ Value to be written in the register
996 * @retval None
997 */
998 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
999
1000 /**
1001 * @brief Read a value in TIM register.
1002 * @param __INSTANCE__ TIM Instance
1003 * @param __REG__ Register to be read
1004 * @retval Register value
1005 */
1006 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1007 /**
1008 * @}
1009 */
1010
1011 /**
1012 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1013 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1014 * @param __TIMCLK__ timer input clock frequency (in Hz)
1015 * @param __CKD__ This parameter can be one of the following values:
1016 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1017 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1018 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1019 * @param __DT__ deadtime duration (in ns)
1020 * @retval DTG[0:7]
1021 */
1022 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1023 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1024 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1025 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1026 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1027 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1028 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1029 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1030 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1031 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1032 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1033 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1034 0U)
1035
1036 /**
1037 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1038 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1039 * @param __TIMCLK__ timer input clock frequency (in Hz)
1040 * @param __CNTCLK__ counter clock frequency (in Hz)
1041 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1042 */
1043 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1044 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1045
1046 /**
1047 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1048 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1049 * @param __TIMCLK__ timer input clock frequency (in Hz)
1050 * @param __PSC__ prescaler
1051 * @param __FREQ__ output signal frequency (in Hz)
1052 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1053 */
1054 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1055 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1056
1057 /**
1058 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1059 * active/inactive delay.
1060 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1061 * @param __TIMCLK__ timer input clock frequency (in Hz)
1062 * @param __PSC__ prescaler
1063 * @param __DELAY__ timer output compare active/inactive delay (in us)
1064 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1065 */
1066 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1067 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1068 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1069
1070 /**
1071 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1072 * (when the timer operates in one pulse mode).
1073 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1074 * @param __TIMCLK__ timer input clock frequency (in Hz)
1075 * @param __PSC__ prescaler
1076 * @param __DELAY__ timer output compare active/inactive delay (in us)
1077 * @param __PULSE__ pulse duration (in us)
1078 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1079 */
1080 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1081 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1082 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1083
1084 /**
1085 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1086 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1087 * @param __ICPSC__ This parameter can be one of the following values:
1088 * @arg @ref LL_TIM_ICPSC_DIV1
1089 * @arg @ref LL_TIM_ICPSC_DIV2
1090 * @arg @ref LL_TIM_ICPSC_DIV4
1091 * @arg @ref LL_TIM_ICPSC_DIV8
1092 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1093 */
1094 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1095 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1096
1097
1098 /**
1099 * @}
1100 */
1101
1102 /* Exported functions --------------------------------------------------------*/
1103 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1104 * @{
1105 */
1106
1107 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1108 * @{
1109 */
1110 /**
1111 * @brief Enable timer counter.
1112 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1113 * @param TIMx Timer instance
1114 * @retval None
1115 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1116 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1117 {
1118 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1119 }
1120
1121 /**
1122 * @brief Disable timer counter.
1123 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1124 * @param TIMx Timer instance
1125 * @retval None
1126 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1127 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1128 {
1129 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1130 }
1131
1132 /**
1133 * @brief Indicates whether the timer counter is enabled.
1134 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1135 * @param TIMx Timer instance
1136 * @retval State of bit (1 or 0).
1137 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1138 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1139 {
1140 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1141 }
1142
1143 /**
1144 * @brief Enable update event generation.
1145 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1146 * @param TIMx Timer instance
1147 * @retval None
1148 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1149 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1150 {
1151 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1152 }
1153
1154 /**
1155 * @brief Disable update event generation.
1156 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1157 * @param TIMx Timer instance
1158 * @retval None
1159 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1160 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1161 {
1162 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1163 }
1164
1165 /**
1166 * @brief Indicates whether update event generation is enabled.
1167 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1168 * @param TIMx Timer instance
1169 * @retval Inverted state of bit (0 or 1).
1170 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1171 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1172 {
1173 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1174 }
1175
1176 /**
1177 * @brief Set update event source
1178 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1179 * generate an update interrupt or DMA request if enabled:
1180 * - Counter overflow/underflow
1181 * - Setting the UG bit
1182 * - Update generation through the slave mode controller
1183 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1184 * overflow/underflow generates an update interrupt or DMA request if enabled.
1185 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1186 * @param TIMx Timer instance
1187 * @param UpdateSource This parameter can be one of the following values:
1188 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1189 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1190 * @retval None
1191 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1192 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1193 {
1194 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1195 }
1196
1197 /**
1198 * @brief Get actual event update source
1199 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1200 * @param TIMx Timer instance
1201 * @retval Returned value can be one of the following values:
1202 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1203 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1204 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1205 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1206 {
1207 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1208 }
1209
1210 /**
1211 * @brief Set one pulse mode (one shot v.s. repetitive).
1212 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1213 * @param TIMx Timer instance
1214 * @param OnePulseMode This parameter can be one of the following values:
1215 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1216 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1217 * @retval None
1218 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1219 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1220 {
1221 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1222 }
1223
1224 /**
1225 * @brief Get actual one pulse mode.
1226 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1227 * @param TIMx Timer instance
1228 * @retval Returned value can be one of the following values:
1229 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1230 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1231 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1232 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1233 {
1234 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1235 }
1236
1237 /**
1238 * @brief Set the timer counter counting mode.
1239 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1240 * check whether or not the counter mode selection feature is supported
1241 * by a timer instance.
1242 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1243 * requires a timer reset to avoid unexpected direction
1244 * due to DIR bit readonly in center aligned mode.
1245 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1246 * CR1 CMS LL_TIM_SetCounterMode
1247 * @param TIMx Timer instance
1248 * @param CounterMode This parameter can be one of the following values:
1249 * @arg @ref LL_TIM_COUNTERMODE_UP
1250 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1251 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1252 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1253 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1254 * @retval None
1255 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1256 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1257 {
1258 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1259 }
1260
1261 /**
1262 * @brief Get actual counter mode.
1263 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1264 * check whether or not the counter mode selection feature is supported
1265 * by a timer instance.
1266 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1267 * CR1 CMS LL_TIM_GetCounterMode
1268 * @param TIMx Timer instance
1269 * @retval Returned value can be one of the following values:
1270 * @arg @ref LL_TIM_COUNTERMODE_UP
1271 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1272 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1273 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1274 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1275 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1276 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1277 {
1278 uint32_t counter_mode;
1279
1280 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1281
1282 if (counter_mode == 0U)
1283 {
1284 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1285 }
1286
1287 return counter_mode;
1288 }
1289
1290 /**
1291 * @brief Enable auto-reload (ARR) preload.
1292 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1293 * @param TIMx Timer instance
1294 * @retval None
1295 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1296 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1297 {
1298 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1299 }
1300
1301 /**
1302 * @brief Disable auto-reload (ARR) preload.
1303 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1304 * @param TIMx Timer instance
1305 * @retval None
1306 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1307 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1308 {
1309 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1310 }
1311
1312 /**
1313 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1314 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1315 * @param TIMx Timer instance
1316 * @retval State of bit (1 or 0).
1317 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1318 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1319 {
1320 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1321 }
1322
1323 /**
1324 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1325 * (when supported) and the digital filters.
1326 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1327 * whether or not the clock division feature is supported by the timer
1328 * instance.
1329 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1330 * @param TIMx Timer instance
1331 * @param ClockDivision This parameter can be one of the following values:
1332 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1333 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1334 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1335 * @retval None
1336 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1337 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1338 {
1339 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1340 }
1341
1342 /**
1343 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1344 * generators (when supported) and the digital filters.
1345 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1346 * whether or not the clock division feature is supported by the timer
1347 * instance.
1348 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1349 * @param TIMx Timer instance
1350 * @retval Returned value can be one of the following values:
1351 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1352 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1353 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1354 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1355 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1356 {
1357 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1358 }
1359
1360 /**
1361 * @brief Set the counter value.
1362 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1363 * whether or not a timer instance supports a 32 bits counter.
1364 * @rmtoll CNT CNT LL_TIM_SetCounter
1365 * @param TIMx Timer instance
1366 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1367 * @retval None
1368 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1369 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1370 {
1371 WRITE_REG(TIMx->CNT, Counter);
1372 }
1373
1374 /**
1375 * @brief Get the counter value.
1376 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1377 * whether or not a timer instance supports a 32 bits counter.
1378 * @rmtoll CNT CNT LL_TIM_GetCounter
1379 * @param TIMx Timer instance
1380 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1381 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1382 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1383 {
1384 return (uint32_t)(READ_REG(TIMx->CNT));
1385 }
1386
1387 /**
1388 * @brief Get the current direction of the counter
1389 * @rmtoll CR1 DIR LL_TIM_GetDirection
1390 * @param TIMx Timer instance
1391 * @retval Returned value can be one of the following values:
1392 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1393 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1394 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1395 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1396 {
1397 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1398 }
1399
1400 /**
1401 * @brief Set the prescaler value.
1402 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1403 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1404 * prescaler ratio is taken into account at the next update event.
1405 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1406 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1407 * @param TIMx Timer instance
1408 * @param Prescaler between Min_Data=0 and Max_Data=65535
1409 * @retval None
1410 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1411 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1412 {
1413 WRITE_REG(TIMx->PSC, Prescaler);
1414 }
1415
1416 /**
1417 * @brief Get the prescaler value.
1418 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1419 * @param TIMx Timer instance
1420 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1421 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1422 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1423 {
1424 return (uint32_t)(READ_REG(TIMx->PSC));
1425 }
1426
1427 /**
1428 * @brief Set the auto-reload value.
1429 * @note The counter is blocked while the auto-reload value is null.
1430 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1431 * whether or not a timer instance supports a 32 bits counter.
1432 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1433 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1434 * @param TIMx Timer instance
1435 * @param AutoReload between Min_Data=0 and Max_Data=65535
1436 * @retval None
1437 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1438 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1439 {
1440 WRITE_REG(TIMx->ARR, AutoReload);
1441 }
1442
1443 /**
1444 * @brief Get the auto-reload value.
1445 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1446 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1447 * whether or not a timer instance supports a 32 bits counter.
1448 * @param TIMx Timer instance
1449 * @retval Auto-reload value
1450 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1451 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1452 {
1453 return (uint32_t)(READ_REG(TIMx->ARR));
1454 }
1455
1456 /**
1457 * @brief Set the repetition counter value.
1458 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1459 * whether or not a timer instance supports a repetition counter.
1460 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1461 * @param TIMx Timer instance
1462 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1463 * @retval None
1464 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1465 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1466 {
1467 WRITE_REG(TIMx->RCR, RepetitionCounter);
1468 }
1469
1470 /**
1471 * @brief Get the repetition counter value.
1472 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1473 * whether or not a timer instance supports a repetition counter.
1474 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1475 * @param TIMx Timer instance
1476 * @retval Repetition counter value
1477 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1478 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1479 {
1480 return (uint32_t)(READ_REG(TIMx->RCR));
1481 }
1482
1483 /**
1484 * @}
1485 */
1486
1487 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1488 * @{
1489 */
1490 /**
1491 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1492 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1493 * they are updated only when a commutation event (COM) occurs.
1494 * @note Only on channels that have a complementary output.
1495 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1496 * whether or not a timer instance is able to generate a commutation event.
1497 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1498 * @param TIMx Timer instance
1499 * @retval None
1500 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1501 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1502 {
1503 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1504 }
1505
1506 /**
1507 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1508 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1509 * whether or not a timer instance is able to generate a commutation event.
1510 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1511 * @param TIMx Timer instance
1512 * @retval None
1513 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1514 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1515 {
1516 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1517 }
1518
1519 /**
1520 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1521 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1522 * @param TIMx Timer instance
1523 * @retval State of bit (1 or 0).
1524 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1525 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1526 {
1527 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1528 }
1529
1530 /**
1531 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1532 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1533 * whether or not a timer instance is able to generate a commutation event.
1534 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1535 * @param TIMx Timer instance
1536 * @param CCUpdateSource This parameter can be one of the following values:
1537 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1538 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1539 * @retval None
1540 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1541 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1542 {
1543 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1544 }
1545
1546 /**
1547 * @brief Set the trigger of the capture/compare DMA request.
1548 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1549 * @param TIMx Timer instance
1550 * @param DMAReqTrigger This parameter can be one of the following values:
1551 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1552 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1553 * @retval None
1554 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1555 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1556 {
1557 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1558 }
1559
1560 /**
1561 * @brief Get actual trigger of the capture/compare DMA request.
1562 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1563 * @param TIMx Timer instance
1564 * @retval Returned value can be one of the following values:
1565 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1566 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1567 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1568 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1569 {
1570 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1571 }
1572
1573 /**
1574 * @brief Set the lock level to freeze the
1575 * configuration of several capture/compare parameters.
1576 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1577 * the lock mechanism is supported by a timer instance.
1578 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1579 * @param TIMx Timer instance
1580 * @param LockLevel This parameter can be one of the following values:
1581 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1582 * @arg @ref LL_TIM_LOCKLEVEL_1
1583 * @arg @ref LL_TIM_LOCKLEVEL_2
1584 * @arg @ref LL_TIM_LOCKLEVEL_3
1585 * @retval None
1586 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1587 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1588 {
1589 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1590 }
1591
1592 /**
1593 * @brief Enable capture/compare channels.
1594 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1595 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1596 * CCER CC2E LL_TIM_CC_EnableChannel\n
1597 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1598 * CCER CC3E LL_TIM_CC_EnableChannel\n
1599 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1600 * CCER CC4E LL_TIM_CC_EnableChannel
1601 * @param TIMx Timer instance
1602 * @param Channels This parameter can be a combination of the following values:
1603 * @arg @ref LL_TIM_CHANNEL_CH1
1604 * @arg @ref LL_TIM_CHANNEL_CH1N
1605 * @arg @ref LL_TIM_CHANNEL_CH2
1606 * @arg @ref LL_TIM_CHANNEL_CH2N
1607 * @arg @ref LL_TIM_CHANNEL_CH3
1608 * @arg @ref LL_TIM_CHANNEL_CH3N
1609 * @arg @ref LL_TIM_CHANNEL_CH4
1610 * @retval None
1611 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1612 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1613 {
1614 SET_BIT(TIMx->CCER, Channels);
1615 }
1616
1617 /**
1618 * @brief Disable capture/compare channels.
1619 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1620 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1621 * CCER CC2E LL_TIM_CC_DisableChannel\n
1622 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1623 * CCER CC3E LL_TIM_CC_DisableChannel\n
1624 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1625 * CCER CC4E LL_TIM_CC_DisableChannel
1626 * @param TIMx Timer instance
1627 * @param Channels This parameter can be a combination of the following values:
1628 * @arg @ref LL_TIM_CHANNEL_CH1
1629 * @arg @ref LL_TIM_CHANNEL_CH1N
1630 * @arg @ref LL_TIM_CHANNEL_CH2
1631 * @arg @ref LL_TIM_CHANNEL_CH2N
1632 * @arg @ref LL_TIM_CHANNEL_CH3
1633 * @arg @ref LL_TIM_CHANNEL_CH3N
1634 * @arg @ref LL_TIM_CHANNEL_CH4
1635 * @retval None
1636 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1637 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1638 {
1639 CLEAR_BIT(TIMx->CCER, Channels);
1640 }
1641
1642 /**
1643 * @brief Indicate whether channel(s) is(are) enabled.
1644 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1645 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1646 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1647 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1648 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1649 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1650 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1651 * @param TIMx Timer instance
1652 * @param Channels This parameter can be a combination of the following values:
1653 * @arg @ref LL_TIM_CHANNEL_CH1
1654 * @arg @ref LL_TIM_CHANNEL_CH1N
1655 * @arg @ref LL_TIM_CHANNEL_CH2
1656 * @arg @ref LL_TIM_CHANNEL_CH2N
1657 * @arg @ref LL_TIM_CHANNEL_CH3
1658 * @arg @ref LL_TIM_CHANNEL_CH3N
1659 * @arg @ref LL_TIM_CHANNEL_CH4
1660 * @retval State of bit (1 or 0).
1661 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1662 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1663 {
1664 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1665 }
1666
1667 /**
1668 * @}
1669 */
1670
1671 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1672 * @{
1673 */
1674 /**
1675 * @brief Configure an output channel.
1676 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1677 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1678 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1679 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1680 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1681 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1682 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1683 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1684 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1685 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1686 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1687 * CR2 OIS4 LL_TIM_OC_ConfigOutput
1688 * @param TIMx Timer instance
1689 * @param Channel This parameter can be one of the following values:
1690 * @arg @ref LL_TIM_CHANNEL_CH1
1691 * @arg @ref LL_TIM_CHANNEL_CH2
1692 * @arg @ref LL_TIM_CHANNEL_CH3
1693 * @arg @ref LL_TIM_CHANNEL_CH4
1694 * @param Configuration This parameter must be a combination of all the following values:
1695 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1696 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1697 * @retval None
1698 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1699 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1700 {
1701 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1702 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1703 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1704 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1705 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1706 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1707 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1708 }
1709
1710 /**
1711 * @brief Define the behavior of the output reference signal OCxREF from which
1712 * OCx and OCxN (when relevant) are derived.
1713 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1714 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1715 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1716 * CCMR2 OC4M LL_TIM_OC_SetMode
1717 * @param TIMx Timer instance
1718 * @param Channel This parameter can be one of the following values:
1719 * @arg @ref LL_TIM_CHANNEL_CH1
1720 * @arg @ref LL_TIM_CHANNEL_CH2
1721 * @arg @ref LL_TIM_CHANNEL_CH3
1722 * @arg @ref LL_TIM_CHANNEL_CH4
1723 * @param Mode This parameter can be one of the following values:
1724 * @arg @ref LL_TIM_OCMODE_FROZEN
1725 * @arg @ref LL_TIM_OCMODE_ACTIVE
1726 * @arg @ref LL_TIM_OCMODE_INACTIVE
1727 * @arg @ref LL_TIM_OCMODE_TOGGLE
1728 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1729 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1730 * @arg @ref LL_TIM_OCMODE_PWM1
1731 * @arg @ref LL_TIM_OCMODE_PWM2
1732 * @retval None
1733 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1734 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1735 {
1736 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1737 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1738 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1739 }
1740
1741 /**
1742 * @brief Get the output compare mode of an output channel.
1743 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1744 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1745 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1746 * CCMR2 OC4M LL_TIM_OC_GetMode
1747 * @param TIMx Timer instance
1748 * @param Channel This parameter can be one of the following values:
1749 * @arg @ref LL_TIM_CHANNEL_CH1
1750 * @arg @ref LL_TIM_CHANNEL_CH2
1751 * @arg @ref LL_TIM_CHANNEL_CH3
1752 * @arg @ref LL_TIM_CHANNEL_CH4
1753 * @retval Returned value can be one of the following values:
1754 * @arg @ref LL_TIM_OCMODE_FROZEN
1755 * @arg @ref LL_TIM_OCMODE_ACTIVE
1756 * @arg @ref LL_TIM_OCMODE_INACTIVE
1757 * @arg @ref LL_TIM_OCMODE_TOGGLE
1758 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1759 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1760 * @arg @ref LL_TIM_OCMODE_PWM1
1761 * @arg @ref LL_TIM_OCMODE_PWM2
1762 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)1763 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
1764 {
1765 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1766 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1767 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1768 }
1769
1770 /**
1771 * @brief Set the polarity of an output channel.
1772 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1773 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1774 * CCER CC2P LL_TIM_OC_SetPolarity\n
1775 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1776 * CCER CC3P LL_TIM_OC_SetPolarity\n
1777 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1778 * CCER CC4P LL_TIM_OC_SetPolarity
1779 * @param TIMx Timer instance
1780 * @param Channel This parameter can be one of the following values:
1781 * @arg @ref LL_TIM_CHANNEL_CH1
1782 * @arg @ref LL_TIM_CHANNEL_CH1N
1783 * @arg @ref LL_TIM_CHANNEL_CH2
1784 * @arg @ref LL_TIM_CHANNEL_CH2N
1785 * @arg @ref LL_TIM_CHANNEL_CH3
1786 * @arg @ref LL_TIM_CHANNEL_CH3N
1787 * @arg @ref LL_TIM_CHANNEL_CH4
1788 * @param Polarity This parameter can be one of the following values:
1789 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1790 * @arg @ref LL_TIM_OCPOLARITY_LOW
1791 * @retval None
1792 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1793 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1794 {
1795 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1796 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1797 }
1798
1799 /**
1800 * @brief Get the polarity of an output channel.
1801 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1802 * CCER CC1NP LL_TIM_OC_GetPolarity\n
1803 * CCER CC2P LL_TIM_OC_GetPolarity\n
1804 * CCER CC2NP LL_TIM_OC_GetPolarity\n
1805 * CCER CC3P LL_TIM_OC_GetPolarity\n
1806 * CCER CC3NP LL_TIM_OC_GetPolarity\n
1807 * CCER CC4P LL_TIM_OC_GetPolarity
1808 * @param TIMx Timer instance
1809 * @param Channel This parameter can be one of the following values:
1810 * @arg @ref LL_TIM_CHANNEL_CH1
1811 * @arg @ref LL_TIM_CHANNEL_CH1N
1812 * @arg @ref LL_TIM_CHANNEL_CH2
1813 * @arg @ref LL_TIM_CHANNEL_CH2N
1814 * @arg @ref LL_TIM_CHANNEL_CH3
1815 * @arg @ref LL_TIM_CHANNEL_CH3N
1816 * @arg @ref LL_TIM_CHANNEL_CH4
1817 * @retval Returned value can be one of the following values:
1818 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1819 * @arg @ref LL_TIM_OCPOLARITY_LOW
1820 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)1821 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
1822 {
1823 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1824 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1825 }
1826
1827 /**
1828 * @brief Set the IDLE state of an output channel
1829 * @note This function is significant only for the timer instances
1830 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
1831 * can be used to check whether or not a timer instance provides
1832 * a break input.
1833 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1834 * CR2 OIS1N LL_TIM_OC_SetIdleState\n
1835 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
1836 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
1837 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
1838 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
1839 * CR2 OIS4 LL_TIM_OC_SetIdleState
1840 * @param TIMx Timer instance
1841 * @param Channel This parameter can be one of the following values:
1842 * @arg @ref LL_TIM_CHANNEL_CH1
1843 * @arg @ref LL_TIM_CHANNEL_CH1N
1844 * @arg @ref LL_TIM_CHANNEL_CH2
1845 * @arg @ref LL_TIM_CHANNEL_CH2N
1846 * @arg @ref LL_TIM_CHANNEL_CH3
1847 * @arg @ref LL_TIM_CHANNEL_CH3N
1848 * @arg @ref LL_TIM_CHANNEL_CH4
1849 * @param IdleState This parameter can be one of the following values:
1850 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1851 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1852 * @retval None
1853 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)1854 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1855 {
1856 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1857 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1858 }
1859
1860 /**
1861 * @brief Get the IDLE state of an output channel
1862 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1863 * CR2 OIS1N LL_TIM_OC_GetIdleState\n
1864 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
1865 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
1866 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
1867 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
1868 * CR2 OIS4 LL_TIM_OC_GetIdleState
1869 * @param TIMx Timer instance
1870 * @param Channel This parameter can be one of the following values:
1871 * @arg @ref LL_TIM_CHANNEL_CH1
1872 * @arg @ref LL_TIM_CHANNEL_CH1N
1873 * @arg @ref LL_TIM_CHANNEL_CH2
1874 * @arg @ref LL_TIM_CHANNEL_CH2N
1875 * @arg @ref LL_TIM_CHANNEL_CH3
1876 * @arg @ref LL_TIM_CHANNEL_CH3N
1877 * @arg @ref LL_TIM_CHANNEL_CH4
1878 * @retval Returned value can be one of the following values:
1879 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1880 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1881 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)1882 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
1883 {
1884 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1885 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1886 }
1887
1888 /**
1889 * @brief Enable fast mode for the output channel.
1890 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1891 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1892 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1893 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1894 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1895 * @param TIMx Timer instance
1896 * @param Channel This parameter can be one of the following values:
1897 * @arg @ref LL_TIM_CHANNEL_CH1
1898 * @arg @ref LL_TIM_CHANNEL_CH2
1899 * @arg @ref LL_TIM_CHANNEL_CH3
1900 * @arg @ref LL_TIM_CHANNEL_CH4
1901 * @retval None
1902 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1903 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1904 {
1905 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1906 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1907 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1908
1909 }
1910
1911 /**
1912 * @brief Disable fast mode for the output channel.
1913 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1914 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1915 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1916 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1917 * @param TIMx Timer instance
1918 * @param Channel This parameter can be one of the following values:
1919 * @arg @ref LL_TIM_CHANNEL_CH1
1920 * @arg @ref LL_TIM_CHANNEL_CH2
1921 * @arg @ref LL_TIM_CHANNEL_CH3
1922 * @arg @ref LL_TIM_CHANNEL_CH4
1923 * @retval None
1924 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1925 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1926 {
1927 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1928 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1929 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1930
1931 }
1932
1933 /**
1934 * @brief Indicates whether fast mode is enabled for the output channel.
1935 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1936 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1937 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1938 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1939 * @param TIMx Timer instance
1940 * @param Channel This parameter can be one of the following values:
1941 * @arg @ref LL_TIM_CHANNEL_CH1
1942 * @arg @ref LL_TIM_CHANNEL_CH2
1943 * @arg @ref LL_TIM_CHANNEL_CH3
1944 * @arg @ref LL_TIM_CHANNEL_CH4
1945 * @retval State of bit (1 or 0).
1946 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)1947 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
1948 {
1949 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1950 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1951 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1952 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1953 }
1954
1955 /**
1956 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1957 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1958 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1959 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1960 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1961 * @param TIMx Timer instance
1962 * @param Channel This parameter can be one of the following values:
1963 * @arg @ref LL_TIM_CHANNEL_CH1
1964 * @arg @ref LL_TIM_CHANNEL_CH2
1965 * @arg @ref LL_TIM_CHANNEL_CH3
1966 * @arg @ref LL_TIM_CHANNEL_CH4
1967 * @retval None
1968 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1969 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1970 {
1971 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1972 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1973 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1974 }
1975
1976 /**
1977 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1978 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1979 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1980 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1981 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1982 * @param TIMx Timer instance
1983 * @param Channel This parameter can be one of the following values:
1984 * @arg @ref LL_TIM_CHANNEL_CH1
1985 * @arg @ref LL_TIM_CHANNEL_CH2
1986 * @arg @ref LL_TIM_CHANNEL_CH3
1987 * @arg @ref LL_TIM_CHANNEL_CH4
1988 * @retval None
1989 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1990 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1991 {
1992 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1993 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1994 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1995 }
1996
1997 /**
1998 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1999 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2000 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2001 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2002 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2003 * @param TIMx Timer instance
2004 * @param Channel This parameter can be one of the following values:
2005 * @arg @ref LL_TIM_CHANNEL_CH1
2006 * @arg @ref LL_TIM_CHANNEL_CH2
2007 * @arg @ref LL_TIM_CHANNEL_CH3
2008 * @arg @ref LL_TIM_CHANNEL_CH4
2009 * @retval State of bit (1 or 0).
2010 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2011 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2012 {
2013 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2014 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2015 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2016 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2017 }
2018
2019 /**
2020 * @brief Enable clearing the output channel on an external event.
2021 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2022 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2023 * or not a timer instance can clear the OCxREF signal on an external event.
2024 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2025 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2026 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2027 * CCMR2 OC4CE LL_TIM_OC_EnableClear
2028 * @param TIMx Timer instance
2029 * @param Channel This parameter can be one of the following values:
2030 * @arg @ref LL_TIM_CHANNEL_CH1
2031 * @arg @ref LL_TIM_CHANNEL_CH2
2032 * @arg @ref LL_TIM_CHANNEL_CH3
2033 * @arg @ref LL_TIM_CHANNEL_CH4
2034 * @retval None
2035 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2036 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2037 {
2038 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2039 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2040 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2041 }
2042
2043 /**
2044 * @brief Disable clearing the output channel on an external event.
2045 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2046 * or not a timer instance can clear the OCxREF signal on an external event.
2047 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2048 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2049 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2050 * CCMR2 OC4CE LL_TIM_OC_DisableClear
2051 * @param TIMx Timer instance
2052 * @param Channel This parameter can be one of the following values:
2053 * @arg @ref LL_TIM_CHANNEL_CH1
2054 * @arg @ref LL_TIM_CHANNEL_CH2
2055 * @arg @ref LL_TIM_CHANNEL_CH3
2056 * @arg @ref LL_TIM_CHANNEL_CH4
2057 * @retval None
2058 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2059 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2060 {
2061 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2062 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2063 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2064 }
2065
2066 /**
2067 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2068 * @note This function enables clearing the output channel on an external event.
2069 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2070 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2071 * or not a timer instance can clear the OCxREF signal on an external event.
2072 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2073 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2074 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2075 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2076 * @param TIMx Timer instance
2077 * @param Channel This parameter can be one of the following values:
2078 * @arg @ref LL_TIM_CHANNEL_CH1
2079 * @arg @ref LL_TIM_CHANNEL_CH2
2080 * @arg @ref LL_TIM_CHANNEL_CH3
2081 * @arg @ref LL_TIM_CHANNEL_CH4
2082 * @retval State of bit (1 or 0).
2083 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2084 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2085 {
2086 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2087 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2088 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2089 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2090 }
2091
2092 /**
2093 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2094 * the Ocx and OCxN signals).
2095 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2096 * dead-time insertion feature is supported by a timer instance.
2097 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2098 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2099 * @param TIMx Timer instance
2100 * @param DeadTime between Min_Data=0 and Max_Data=255
2101 * @retval None
2102 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2103 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2104 {
2105 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2106 }
2107
2108 /**
2109 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2110 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2111 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2112 * whether or not a timer instance supports a 32 bits counter.
2113 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2114 * output channel 1 is supported by a timer instance.
2115 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2116 * @param TIMx Timer instance
2117 * @param CompareValue between Min_Data=0 and Max_Data=65535
2118 * @retval None
2119 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2120 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2121 {
2122 WRITE_REG(TIMx->CCR1, CompareValue);
2123 }
2124
2125 /**
2126 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2127 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2128 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2129 * whether or not a timer instance supports a 32 bits counter.
2130 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2131 * output channel 2 is supported by a timer instance.
2132 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2133 * @param TIMx Timer instance
2134 * @param CompareValue between Min_Data=0 and Max_Data=65535
2135 * @retval None
2136 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2137 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2138 {
2139 WRITE_REG(TIMx->CCR2, CompareValue);
2140 }
2141
2142 /**
2143 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2144 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2145 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2146 * whether or not a timer instance supports a 32 bits counter.
2147 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2148 * output channel is supported by a timer instance.
2149 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2150 * @param TIMx Timer instance
2151 * @param CompareValue between Min_Data=0 and Max_Data=65535
2152 * @retval None
2153 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2154 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2155 {
2156 WRITE_REG(TIMx->CCR3, CompareValue);
2157 }
2158
2159 /**
2160 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2161 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2162 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2163 * whether or not a timer instance supports a 32 bits counter.
2164 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2165 * output channel 4 is supported by a timer instance.
2166 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2167 * @param TIMx Timer instance
2168 * @param CompareValue between Min_Data=0 and Max_Data=65535
2169 * @retval None
2170 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2171 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2172 {
2173 WRITE_REG(TIMx->CCR4, CompareValue);
2174 }
2175
2176 /**
2177 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2178 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2179 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2180 * whether or not a timer instance supports a 32 bits counter.
2181 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2182 * output channel 1 is supported by a timer instance.
2183 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2184 * @param TIMx Timer instance
2185 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2186 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2187 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2188 {
2189 return (uint32_t)(READ_REG(TIMx->CCR1));
2190 }
2191
2192 /**
2193 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2194 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2195 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2196 * whether or not a timer instance supports a 32 bits counter.
2197 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2198 * output channel 2 is supported by a timer instance.
2199 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2200 * @param TIMx Timer instance
2201 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2202 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2203 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2204 {
2205 return (uint32_t)(READ_REG(TIMx->CCR2));
2206 }
2207
2208 /**
2209 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2210 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2211 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2212 * whether or not a timer instance supports a 32 bits counter.
2213 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2214 * output channel 3 is supported by a timer instance.
2215 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2216 * @param TIMx Timer instance
2217 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2218 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2219 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2220 {
2221 return (uint32_t)(READ_REG(TIMx->CCR3));
2222 }
2223
2224 /**
2225 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2226 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2227 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2228 * whether or not a timer instance supports a 32 bits counter.
2229 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2230 * output channel 4 is supported by a timer instance.
2231 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2232 * @param TIMx Timer instance
2233 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2234 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2235 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2236 {
2237 return (uint32_t)(READ_REG(TIMx->CCR4));
2238 }
2239
2240 /**
2241 * @}
2242 */
2243
2244 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2245 * @{
2246 */
2247 /**
2248 * @brief Configure input channel.
2249 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2250 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2251 * CCMR1 IC1F LL_TIM_IC_Config\n
2252 * CCMR1 CC2S LL_TIM_IC_Config\n
2253 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2254 * CCMR1 IC2F LL_TIM_IC_Config\n
2255 * CCMR2 CC3S LL_TIM_IC_Config\n
2256 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2257 * CCMR2 IC3F LL_TIM_IC_Config\n
2258 * CCMR2 CC4S LL_TIM_IC_Config\n
2259 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2260 * CCMR2 IC4F LL_TIM_IC_Config\n
2261 * CCER CC1P LL_TIM_IC_Config\n
2262 * CCER CC1NP LL_TIM_IC_Config\n
2263 * CCER CC2P LL_TIM_IC_Config\n
2264 * CCER CC2NP LL_TIM_IC_Config\n
2265 * CCER CC3P LL_TIM_IC_Config\n
2266 * CCER CC3NP LL_TIM_IC_Config\n
2267 * CCER CC4P LL_TIM_IC_Config\n
2268 * CCER CC4NP LL_TIM_IC_Config
2269 * @param TIMx Timer instance
2270 * @param Channel This parameter can be one of the following values:
2271 * @arg @ref LL_TIM_CHANNEL_CH1
2272 * @arg @ref LL_TIM_CHANNEL_CH2
2273 * @arg @ref LL_TIM_CHANNEL_CH3
2274 * @arg @ref LL_TIM_CHANNEL_CH4
2275 * @param Configuration This parameter must be a combination of all the following values:
2276 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2277 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2278 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2279 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2280 * @retval None
2281 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2282 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2283 {
2284 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2285 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2286 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2287 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2288 << SHIFT_TAB_ICxx[iChannel]);
2289 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2290 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2291 }
2292
2293 /**
2294 * @brief Set the active input.
2295 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2296 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2297 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2298 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2299 * @param TIMx Timer instance
2300 * @param Channel This parameter can be one of the following values:
2301 * @arg @ref LL_TIM_CHANNEL_CH1
2302 * @arg @ref LL_TIM_CHANNEL_CH2
2303 * @arg @ref LL_TIM_CHANNEL_CH3
2304 * @arg @ref LL_TIM_CHANNEL_CH4
2305 * @param ICActiveInput This parameter can be one of the following values:
2306 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2307 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2308 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2309 * @retval None
2310 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2311 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2312 {
2313 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2314 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2315 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2316 }
2317
2318 /**
2319 * @brief Get the current active input.
2320 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2321 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2322 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2323 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2324 * @param TIMx Timer instance
2325 * @param Channel This parameter can be one of the following values:
2326 * @arg @ref LL_TIM_CHANNEL_CH1
2327 * @arg @ref LL_TIM_CHANNEL_CH2
2328 * @arg @ref LL_TIM_CHANNEL_CH3
2329 * @arg @ref LL_TIM_CHANNEL_CH4
2330 * @retval Returned value can be one of the following values:
2331 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2332 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2333 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2334 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2335 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2336 {
2337 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2338 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2339 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2340 }
2341
2342 /**
2343 * @brief Set the prescaler of input channel.
2344 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2345 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2346 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2347 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2348 * @param TIMx Timer instance
2349 * @param Channel This parameter can be one of the following values:
2350 * @arg @ref LL_TIM_CHANNEL_CH1
2351 * @arg @ref LL_TIM_CHANNEL_CH2
2352 * @arg @ref LL_TIM_CHANNEL_CH3
2353 * @arg @ref LL_TIM_CHANNEL_CH4
2354 * @param ICPrescaler This parameter can be one of the following values:
2355 * @arg @ref LL_TIM_ICPSC_DIV1
2356 * @arg @ref LL_TIM_ICPSC_DIV2
2357 * @arg @ref LL_TIM_ICPSC_DIV4
2358 * @arg @ref LL_TIM_ICPSC_DIV8
2359 * @retval None
2360 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2361 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2362 {
2363 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2364 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2365 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2366 }
2367
2368 /**
2369 * @brief Get the current prescaler value acting on an input channel.
2370 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2371 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2372 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2373 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2374 * @param TIMx Timer instance
2375 * @param Channel This parameter can be one of the following values:
2376 * @arg @ref LL_TIM_CHANNEL_CH1
2377 * @arg @ref LL_TIM_CHANNEL_CH2
2378 * @arg @ref LL_TIM_CHANNEL_CH3
2379 * @arg @ref LL_TIM_CHANNEL_CH4
2380 * @retval Returned value can be one of the following values:
2381 * @arg @ref LL_TIM_ICPSC_DIV1
2382 * @arg @ref LL_TIM_ICPSC_DIV2
2383 * @arg @ref LL_TIM_ICPSC_DIV4
2384 * @arg @ref LL_TIM_ICPSC_DIV8
2385 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2386 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2387 {
2388 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2389 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2390 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2391 }
2392
2393 /**
2394 * @brief Set the input filter duration.
2395 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2396 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2397 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2398 * CCMR2 IC4F LL_TIM_IC_SetFilter
2399 * @param TIMx Timer instance
2400 * @param Channel This parameter can be one of the following values:
2401 * @arg @ref LL_TIM_CHANNEL_CH1
2402 * @arg @ref LL_TIM_CHANNEL_CH2
2403 * @arg @ref LL_TIM_CHANNEL_CH3
2404 * @arg @ref LL_TIM_CHANNEL_CH4
2405 * @param ICFilter This parameter can be one of the following values:
2406 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2407 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2408 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2409 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2410 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2411 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2412 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2413 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2414 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2415 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2416 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2417 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2418 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2419 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2420 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2421 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2422 * @retval None
2423 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2424 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2425 {
2426 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2427 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2428 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2429 }
2430
2431 /**
2432 * @brief Get the input filter duration.
2433 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2434 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2435 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2436 * CCMR2 IC4F LL_TIM_IC_GetFilter
2437 * @param TIMx Timer instance
2438 * @param Channel This parameter can be one of the following values:
2439 * @arg @ref LL_TIM_CHANNEL_CH1
2440 * @arg @ref LL_TIM_CHANNEL_CH2
2441 * @arg @ref LL_TIM_CHANNEL_CH3
2442 * @arg @ref LL_TIM_CHANNEL_CH4
2443 * @retval Returned value can be one of the following values:
2444 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2445 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2446 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2447 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2448 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2449 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2450 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2451 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2452 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2453 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2454 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2455 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2456 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2457 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2458 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2459 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2460 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2461 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2462 {
2463 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2464 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2465 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2466 }
2467
2468 /**
2469 * @brief Set the input channel polarity.
2470 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2471 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2472 * CCER CC2P LL_TIM_IC_SetPolarity\n
2473 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2474 * CCER CC3P LL_TIM_IC_SetPolarity\n
2475 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2476 * CCER CC4P LL_TIM_IC_SetPolarity\n
2477 * CCER CC4NP LL_TIM_IC_SetPolarity
2478 * @param TIMx Timer instance
2479 * @param Channel This parameter can be one of the following values:
2480 * @arg @ref LL_TIM_CHANNEL_CH1
2481 * @arg @ref LL_TIM_CHANNEL_CH2
2482 * @arg @ref LL_TIM_CHANNEL_CH3
2483 * @arg @ref LL_TIM_CHANNEL_CH4
2484 * @param ICPolarity This parameter can be one of the following values:
2485 * @arg @ref LL_TIM_IC_POLARITY_RISING
2486 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2487 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2488 * @retval None
2489 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2490 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2491 {
2492 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2493 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2494 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2495 }
2496
2497 /**
2498 * @brief Get the current input channel polarity.
2499 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2500 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2501 * CCER CC2P LL_TIM_IC_GetPolarity\n
2502 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2503 * CCER CC3P LL_TIM_IC_GetPolarity\n
2504 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2505 * CCER CC4P LL_TIM_IC_GetPolarity\n
2506 * CCER CC4NP LL_TIM_IC_GetPolarity
2507 * @param TIMx Timer instance
2508 * @param Channel This parameter can be one of the following values:
2509 * @arg @ref LL_TIM_CHANNEL_CH1
2510 * @arg @ref LL_TIM_CHANNEL_CH2
2511 * @arg @ref LL_TIM_CHANNEL_CH3
2512 * @arg @ref LL_TIM_CHANNEL_CH4
2513 * @retval Returned value can be one of the following values:
2514 * @arg @ref LL_TIM_IC_POLARITY_RISING
2515 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2516 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2517 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2518 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2519 {
2520 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2521 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2522 SHIFT_TAB_CCxP[iChannel]);
2523 }
2524
2525 /**
2526 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2527 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2528 * a timer instance provides an XOR input.
2529 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2530 * @param TIMx Timer instance
2531 * @retval None
2532 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2533 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2534 {
2535 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2536 }
2537
2538 /**
2539 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2540 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2541 * a timer instance provides an XOR input.
2542 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2543 * @param TIMx Timer instance
2544 * @retval None
2545 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2546 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2547 {
2548 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2549 }
2550
2551 /**
2552 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2553 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2554 * a timer instance provides an XOR input.
2555 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2556 * @param TIMx Timer instance
2557 * @retval State of bit (1 or 0).
2558 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)2559 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
2560 {
2561 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2562 }
2563
2564 /**
2565 * @brief Get captured value for input channel 1.
2566 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2567 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2568 * whether or not a timer instance supports a 32 bits counter.
2569 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2570 * input channel 1 is supported by a timer instance.
2571 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2572 * @param TIMx Timer instance
2573 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2574 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)2575 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
2576 {
2577 return (uint32_t)(READ_REG(TIMx->CCR1));
2578 }
2579
2580 /**
2581 * @brief Get captured value for input channel 2.
2582 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2583 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2584 * whether or not a timer instance supports a 32 bits counter.
2585 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2586 * input channel 2 is supported by a timer instance.
2587 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2588 * @param TIMx Timer instance
2589 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2590 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)2591 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
2592 {
2593 return (uint32_t)(READ_REG(TIMx->CCR2));
2594 }
2595
2596 /**
2597 * @brief Get captured value for input channel 3.
2598 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2599 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2600 * whether or not a timer instance supports a 32 bits counter.
2601 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2602 * input channel 3 is supported by a timer instance.
2603 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2604 * @param TIMx Timer instance
2605 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2606 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)2607 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
2608 {
2609 return (uint32_t)(READ_REG(TIMx->CCR3));
2610 }
2611
2612 /**
2613 * @brief Get captured value for input channel 4.
2614 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2615 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2616 * whether or not a timer instance supports a 32 bits counter.
2617 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2618 * input channel 4 is supported by a timer instance.
2619 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2620 * @param TIMx Timer instance
2621 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2622 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)2623 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
2624 {
2625 return (uint32_t)(READ_REG(TIMx->CCR4));
2626 }
2627
2628 /**
2629 * @}
2630 */
2631
2632 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2633 * @{
2634 */
2635 /**
2636 * @brief Enable external clock mode 2.
2637 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2638 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2639 * whether or not a timer instance supports external clock mode2.
2640 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2641 * @param TIMx Timer instance
2642 * @retval None
2643 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2644 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2645 {
2646 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2647 }
2648
2649 /**
2650 * @brief Disable external clock mode 2.
2651 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2652 * whether or not a timer instance supports external clock mode2.
2653 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2654 * @param TIMx Timer instance
2655 * @retval None
2656 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2657 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2658 {
2659 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2660 }
2661
2662 /**
2663 * @brief Indicate whether external clock mode 2 is enabled.
2664 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2665 * whether or not a timer instance supports external clock mode2.
2666 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2667 * @param TIMx Timer instance
2668 * @retval State of bit (1 or 0).
2669 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)2670 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
2671 {
2672 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2673 }
2674
2675 /**
2676 * @brief Set the clock source of the counter clock.
2677 * @note when selected clock source is external clock mode 1, the timer input
2678 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2679 * function. This timer input must be configured by calling
2680 * the @ref LL_TIM_IC_Config() function.
2681 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2682 * whether or not a timer instance supports external clock mode1.
2683 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2684 * whether or not a timer instance supports external clock mode2.
2685 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2686 * SMCR ECE LL_TIM_SetClockSource
2687 * @param TIMx Timer instance
2688 * @param ClockSource This parameter can be one of the following values:
2689 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2690 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2691 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2692 * @retval None
2693 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2694 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2695 {
2696 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2697 }
2698
2699 /**
2700 * @brief Set the encoder interface mode.
2701 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2702 * whether or not a timer instance supports the encoder mode.
2703 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2704 * @param TIMx Timer instance
2705 * @param EncoderMode This parameter can be one of the following values:
2706 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2707 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2708 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2709 * @retval None
2710 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2711 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2712 {
2713 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2714 }
2715
2716 /**
2717 * @}
2718 */
2719
2720 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2721 * @{
2722 */
2723 /**
2724 * @brief Set the trigger output (TRGO) used for timer synchronization .
2725 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2726 * whether or not a timer instance can operate as a master timer.
2727 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2728 * @param TIMx Timer instance
2729 * @param TimerSynchronization This parameter can be one of the following values:
2730 * @arg @ref LL_TIM_TRGO_RESET
2731 * @arg @ref LL_TIM_TRGO_ENABLE
2732 * @arg @ref LL_TIM_TRGO_UPDATE
2733 * @arg @ref LL_TIM_TRGO_CC1IF
2734 * @arg @ref LL_TIM_TRGO_OC1REF
2735 * @arg @ref LL_TIM_TRGO_OC2REF
2736 * @arg @ref LL_TIM_TRGO_OC3REF
2737 * @arg @ref LL_TIM_TRGO_OC4REF
2738 * @retval None
2739 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2740 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2741 {
2742 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2743 }
2744
2745 /**
2746 * @brief Set the synchronization mode of a slave timer.
2747 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2748 * a timer instance can operate as a slave timer.
2749 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2750 * @param TIMx Timer instance
2751 * @param SlaveMode This parameter can be one of the following values:
2752 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2753 * @arg @ref LL_TIM_SLAVEMODE_RESET
2754 * @arg @ref LL_TIM_SLAVEMODE_GATED
2755 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2756 * @retval None
2757 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2758 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2759 {
2760 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2761 }
2762
2763 /**
2764 * @brief Set the selects the trigger input to be used to synchronize the counter.
2765 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2766 * a timer instance can operate as a slave timer.
2767 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2768 * @param TIMx Timer instance
2769 * @param TriggerInput This parameter can be one of the following values:
2770 * @arg @ref LL_TIM_TS_ITR0
2771 * @arg @ref LL_TIM_TS_ITR1
2772 * @arg @ref LL_TIM_TS_ITR2
2773 * @arg @ref LL_TIM_TS_ITR3
2774 * @arg @ref LL_TIM_TS_TI1F_ED
2775 * @arg @ref LL_TIM_TS_TI1FP1
2776 * @arg @ref LL_TIM_TS_TI2FP2
2777 * @arg @ref LL_TIM_TS_ETRF
2778 * @retval None
2779 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2780 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2781 {
2782 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2783 }
2784
2785 /**
2786 * @brief Enable the Master/Slave mode.
2787 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2788 * a timer instance can operate as a slave timer.
2789 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2790 * @param TIMx Timer instance
2791 * @retval None
2792 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2793 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2794 {
2795 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2796 }
2797
2798 /**
2799 * @brief Disable the Master/Slave mode.
2800 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2801 * a timer instance can operate as a slave timer.
2802 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2803 * @param TIMx Timer instance
2804 * @retval None
2805 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2806 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2807 {
2808 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2809 }
2810
2811 /**
2812 * @brief Indicates whether the Master/Slave mode is enabled.
2813 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2814 * a timer instance can operate as a slave timer.
2815 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2816 * @param TIMx Timer instance
2817 * @retval State of bit (1 or 0).
2818 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)2819 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
2820 {
2821 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2822 }
2823
2824 /**
2825 * @brief Configure the external trigger (ETR) input.
2826 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2827 * a timer instance provides an external trigger input.
2828 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2829 * SMCR ETPS LL_TIM_ConfigETR\n
2830 * SMCR ETF LL_TIM_ConfigETR
2831 * @param TIMx Timer instance
2832 * @param ETRPolarity This parameter can be one of the following values:
2833 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2834 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2835 * @param ETRPrescaler This parameter can be one of the following values:
2836 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2837 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2838 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2839 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2840 * @param ETRFilter This parameter can be one of the following values:
2841 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2842 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2843 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2844 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2845 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2846 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2847 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2848 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2849 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2850 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2851 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2852 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2853 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2854 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2855 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2856 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2857 * @retval None
2858 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2859 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2860 uint32_t ETRFilter)
2861 {
2862 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2863 }
2864
2865 /**
2866 * @}
2867 */
2868
2869 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
2870 * @{
2871 */
2872 /**
2873 * @brief Enable the break function.
2874 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2875 * a timer instance provides a break input.
2876 * @rmtoll BDTR BKE LL_TIM_EnableBRK
2877 * @param TIMx Timer instance
2878 * @retval None
2879 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)2880 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2881 {
2882 __IO uint32_t tmpreg;
2883 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2884 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2885 tmpreg = READ_REG(TIMx->BDTR);
2886 (void)(tmpreg);
2887 }
2888
2889 /**
2890 * @brief Disable the break function.
2891 * @rmtoll BDTR BKE LL_TIM_DisableBRK
2892 * @param TIMx Timer instance
2893 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2894 * a timer instance provides a break input.
2895 * @retval None
2896 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)2897 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2898 {
2899 __IO uint32_t tmpreg;
2900 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2901 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2902 tmpreg = READ_REG(TIMx->BDTR);
2903 (void)(tmpreg);
2904 }
2905
2906 /**
2907 * @brief Configure the break input.
2908 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2909 * a timer instance provides a break input.
2910 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
2911 * @param TIMx Timer instance
2912 * @param BreakPolarity This parameter can be one of the following values:
2913 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
2914 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2915 * @retval None
2916 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)2917 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2918 {
2919 __IO uint32_t tmpreg;
2920 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2921 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
2922 tmpreg = READ_REG(TIMx->BDTR);
2923 (void)(tmpreg);
2924 }
2925
2926 /**
2927 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2928 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2929 * a timer instance provides a break input.
2930 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2931 * BDTR OSSR LL_TIM_SetOffStates
2932 * @param TIMx Timer instance
2933 * @param OffStateIdle This parameter can be one of the following values:
2934 * @arg @ref LL_TIM_OSSI_DISABLE
2935 * @arg @ref LL_TIM_OSSI_ENABLE
2936 * @param OffStateRun This parameter can be one of the following values:
2937 * @arg @ref LL_TIM_OSSR_DISABLE
2938 * @arg @ref LL_TIM_OSSR_ENABLE
2939 * @retval None
2940 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)2941 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2942 {
2943 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
2944 }
2945
2946 /**
2947 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2948 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2949 * a timer instance provides a break input.
2950 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2951 * @param TIMx Timer instance
2952 * @retval None
2953 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)2954 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2955 {
2956 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2957 }
2958
2959 /**
2960 * @brief Disable automatic output (MOE can be set only by software).
2961 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2962 * a timer instance provides a break input.
2963 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2964 * @param TIMx Timer instance
2965 * @retval None
2966 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)2967 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2968 {
2969 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2970 }
2971
2972 /**
2973 * @brief Indicate whether automatic output is enabled.
2974 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2975 * a timer instance provides a break input.
2976 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2977 * @param TIMx Timer instance
2978 * @retval State of bit (1 or 0).
2979 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)2980 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
2981 {
2982 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2983 }
2984
2985 /**
2986 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2987 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2988 * software and is reset in case of break or break2 event
2989 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2990 * a timer instance provides a break input.
2991 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2992 * @param TIMx Timer instance
2993 * @retval None
2994 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)2995 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2996 {
2997 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2998 }
2999
3000 /**
3001 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3002 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3003 * software and is reset in case of break or break2 event.
3004 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3005 * a timer instance provides a break input.
3006 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3007 * @param TIMx Timer instance
3008 * @retval None
3009 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3010 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3011 {
3012 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3013 }
3014
3015 /**
3016 * @brief Indicates whether outputs are enabled.
3017 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3018 * a timer instance provides a break input.
3019 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3020 * @param TIMx Timer instance
3021 * @retval State of bit (1 or 0).
3022 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3023 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3024 {
3025 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3026 }
3027
3028 /**
3029 * @}
3030 */
3031
3032 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3033 * @{
3034 */
3035 /**
3036 * @brief Configures the timer DMA burst feature.
3037 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3038 * not a timer instance supports the DMA burst mode.
3039 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3040 * DCR DBA LL_TIM_ConfigDMABurst
3041 * @param TIMx Timer instance
3042 * @param DMABurstBaseAddress This parameter can be one of the following values:
3043 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3044 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3045 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3046 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3047 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3048 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3049 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3050 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3051 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3052 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3053 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3054 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3055 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3056 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3057 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3058 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3059 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3060 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3061 * @param DMABurstLength This parameter can be one of the following values:
3062 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3063 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3064 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3065 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3066 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3067 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3068 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3069 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3070 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3071 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3072 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3073 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3074 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3075 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3076 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3077 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3078 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3079 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3080 * @retval None
3081 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3082 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3083 {
3084 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3085 }
3086
3087 /**
3088 * @}
3089 */
3090
3091 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3092 * @{
3093 */
3094 /**
3095 * @brief Remap TIM inputs (input channel, internal/external triggers).
3096 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3097 * a some timer inputs can be remapped.
3098 * @rmtoll TIM1_OR ITR2_RMP LL_TIM_SetRemap\n
3099 * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3100 * TIM5_OR ITR1_RMP LL_TIM_SetRemap\n
3101 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3102 * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
3103 * TIM11_OR TI1_RMP LL_TIM_SetRemap\n
3104 * LPTIM1_OR OR LL_TIM_SetRemap
3105 * @param TIMx Timer instance
3106 * @param Remap Remap param depends on the TIMx. Description available only
3107 * in CHM version of the User Manual (not in .pdf).
3108 * Otherwise see Reference Manual description of OR registers.
3109 *
3110 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3111 *
3112 * TIM1: one of the following values
3113 *
3114 * ITR2_RMP can be one of the following values
3115 * @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*)
3116 * @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*)
3117 *
3118 * TIM2: one of the following values
3119 *
3120 * ITR1_RMP can be one of the following values
3121 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3122 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3123 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3124 *
3125 * TIM5: one of the following values
3126 *
3127 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3128 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3129 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3130 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3131 * @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*)
3132 * @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*)
3133 *
3134 * TIM9: one of the following values
3135 *
3136 * ITR1_RMP can be one of the following values
3137 * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*)
3138 * @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*)
3139 *
3140 * TIM11: one of the following values
3141 *
3142 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3143 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*)
3144 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
3145 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
3146 * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*)
3147 *
3148 * (*) Value not defined in all devices. \n
3149 *
3150 * @retval None
3151 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3152 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3153 {
3154 #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
3155 if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK)
3156 {
3157 /* Connect TIMx internal trigger to LPTIM1 output */
3158 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);
3159 MODIFY_REG(LPTIM1->OR,
3160 (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),
3161 Remap & ~(LL_TIM_LPTIM_REMAP_MASK));
3162 }
3163 else
3164 {
3165 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3166 }
3167 #else
3168 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3169 #endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
3170 }
3171
3172 /**
3173 * @}
3174 */
3175
3176 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3177 * @{
3178 */
3179 /**
3180 * @brief Clear the update interrupt flag (UIF).
3181 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3182 * @param TIMx Timer instance
3183 * @retval None
3184 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3185 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3186 {
3187 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3188 }
3189
3190 /**
3191 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3192 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3193 * @param TIMx Timer instance
3194 * @retval State of bit (1 or 0).
3195 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3196 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3197 {
3198 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3199 }
3200
3201 /**
3202 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3203 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3204 * @param TIMx Timer instance
3205 * @retval None
3206 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3207 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3208 {
3209 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3210 }
3211
3212 /**
3213 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3214 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3215 * @param TIMx Timer instance
3216 * @retval State of bit (1 or 0).
3217 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3218 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3219 {
3220 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3221 }
3222
3223 /**
3224 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3225 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3226 * @param TIMx Timer instance
3227 * @retval None
3228 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3229 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3230 {
3231 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3232 }
3233
3234 /**
3235 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3236 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3237 * @param TIMx Timer instance
3238 * @retval State of bit (1 or 0).
3239 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3240 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3241 {
3242 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3243 }
3244
3245 /**
3246 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3247 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3248 * @param TIMx Timer instance
3249 * @retval None
3250 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3251 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3252 {
3253 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3254 }
3255
3256 /**
3257 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3258 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3259 * @param TIMx Timer instance
3260 * @retval State of bit (1 or 0).
3261 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3262 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3263 {
3264 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3265 }
3266
3267 /**
3268 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3269 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3270 * @param TIMx Timer instance
3271 * @retval None
3272 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3273 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3274 {
3275 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3276 }
3277
3278 /**
3279 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3280 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3281 * @param TIMx Timer instance
3282 * @retval State of bit (1 or 0).
3283 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)3284 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
3285 {
3286 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3287 }
3288
3289 /**
3290 * @brief Clear the commutation interrupt flag (COMIF).
3291 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3292 * @param TIMx Timer instance
3293 * @retval None
3294 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3295 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3296 {
3297 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3298 }
3299
3300 /**
3301 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3302 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3303 * @param TIMx Timer instance
3304 * @retval State of bit (1 or 0).
3305 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)3306 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
3307 {
3308 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3309 }
3310
3311 /**
3312 * @brief Clear the trigger interrupt flag (TIF).
3313 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3314 * @param TIMx Timer instance
3315 * @retval None
3316 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3317 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3318 {
3319 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3320 }
3321
3322 /**
3323 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3324 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3325 * @param TIMx Timer instance
3326 * @retval State of bit (1 or 0).
3327 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)3328 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
3329 {
3330 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3331 }
3332
3333 /**
3334 * @brief Clear the break interrupt flag (BIF).
3335 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3336 * @param TIMx Timer instance
3337 * @retval None
3338 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3339 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3340 {
3341 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3342 }
3343
3344 /**
3345 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3346 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3347 * @param TIMx Timer instance
3348 * @retval State of bit (1 or 0).
3349 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)3350 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
3351 {
3352 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3353 }
3354
3355 /**
3356 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3357 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3358 * @param TIMx Timer instance
3359 * @retval None
3360 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3361 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3362 {
3363 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3364 }
3365
3366 /**
3367 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3368 * (Capture/Compare 1 interrupt is pending).
3369 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3370 * @param TIMx Timer instance
3371 * @retval State of bit (1 or 0).
3372 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)3373 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
3374 {
3375 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3376 }
3377
3378 /**
3379 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3380 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3381 * @param TIMx Timer instance
3382 * @retval None
3383 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3384 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3385 {
3386 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3387 }
3388
3389 /**
3390 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3391 * (Capture/Compare 2 over-capture interrupt is pending).
3392 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3393 * @param TIMx Timer instance
3394 * @retval State of bit (1 or 0).
3395 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)3396 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
3397 {
3398 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3399 }
3400
3401 /**
3402 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3403 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3404 * @param TIMx Timer instance
3405 * @retval None
3406 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3407 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3408 {
3409 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3410 }
3411
3412 /**
3413 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
3414 * (Capture/Compare 3 over-capture interrupt is pending).
3415 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3416 * @param TIMx Timer instance
3417 * @retval State of bit (1 or 0).
3418 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)3419 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
3420 {
3421 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3422 }
3423
3424 /**
3425 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3426 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3427 * @param TIMx Timer instance
3428 * @retval None
3429 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3430 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3431 {
3432 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3433 }
3434
3435 /**
3436 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
3437 * (Capture/Compare 4 over-capture interrupt is pending).
3438 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3439 * @param TIMx Timer instance
3440 * @retval State of bit (1 or 0).
3441 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)3442 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
3443 {
3444 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3445 }
3446
3447 /**
3448 * @}
3449 */
3450
3451 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3452 * @{
3453 */
3454 /**
3455 * @brief Enable update interrupt (UIE).
3456 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3457 * @param TIMx Timer instance
3458 * @retval None
3459 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3460 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3461 {
3462 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3463 }
3464
3465 /**
3466 * @brief Disable update interrupt (UIE).
3467 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3468 * @param TIMx Timer instance
3469 * @retval None
3470 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3471 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3472 {
3473 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3474 }
3475
3476 /**
3477 * @brief Indicates whether the update interrupt (UIE) is enabled.
3478 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3479 * @param TIMx Timer instance
3480 * @retval State of bit (1 or 0).
3481 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)3482 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
3483 {
3484 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
3485 }
3486
3487 /**
3488 * @brief Enable capture/compare 1 interrupt (CC1IE).
3489 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3490 * @param TIMx Timer instance
3491 * @retval None
3492 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)3493 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3494 {
3495 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3496 }
3497
3498 /**
3499 * @brief Disable capture/compare 1 interrupt (CC1IE).
3500 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3501 * @param TIMx Timer instance
3502 * @retval None
3503 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)3504 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3505 {
3506 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3507 }
3508
3509 /**
3510 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3511 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3512 * @param TIMx Timer instance
3513 * @retval State of bit (1 or 0).
3514 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)3515 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
3516 {
3517 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
3518 }
3519
3520 /**
3521 * @brief Enable capture/compare 2 interrupt (CC2IE).
3522 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3523 * @param TIMx Timer instance
3524 * @retval None
3525 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)3526 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3527 {
3528 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3529 }
3530
3531 /**
3532 * @brief Disable capture/compare 2 interrupt (CC2IE).
3533 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3534 * @param TIMx Timer instance
3535 * @retval None
3536 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)3537 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3538 {
3539 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3540 }
3541
3542 /**
3543 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3544 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3545 * @param TIMx Timer instance
3546 * @retval State of bit (1 or 0).
3547 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)3548 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
3549 {
3550 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
3551 }
3552
3553 /**
3554 * @brief Enable capture/compare 3 interrupt (CC3IE).
3555 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3556 * @param TIMx Timer instance
3557 * @retval None
3558 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)3559 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3560 {
3561 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3562 }
3563
3564 /**
3565 * @brief Disable capture/compare 3 interrupt (CC3IE).
3566 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3567 * @param TIMx Timer instance
3568 * @retval None
3569 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)3570 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3571 {
3572 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3573 }
3574
3575 /**
3576 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3577 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3578 * @param TIMx Timer instance
3579 * @retval State of bit (1 or 0).
3580 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)3581 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
3582 {
3583 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
3584 }
3585
3586 /**
3587 * @brief Enable capture/compare 4 interrupt (CC4IE).
3588 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3589 * @param TIMx Timer instance
3590 * @retval None
3591 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)3592 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3593 {
3594 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3595 }
3596
3597 /**
3598 * @brief Disable capture/compare 4 interrupt (CC4IE).
3599 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3600 * @param TIMx Timer instance
3601 * @retval None
3602 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)3603 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3604 {
3605 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3606 }
3607
3608 /**
3609 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3610 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3611 * @param TIMx Timer instance
3612 * @retval State of bit (1 or 0).
3613 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)3614 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
3615 {
3616 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
3617 }
3618
3619 /**
3620 * @brief Enable commutation interrupt (COMIE).
3621 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3622 * @param TIMx Timer instance
3623 * @retval None
3624 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)3625 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3626 {
3627 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3628 }
3629
3630 /**
3631 * @brief Disable commutation interrupt (COMIE).
3632 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3633 * @param TIMx Timer instance
3634 * @retval None
3635 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)3636 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3637 {
3638 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3639 }
3640
3641 /**
3642 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3643 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3644 * @param TIMx Timer instance
3645 * @retval State of bit (1 or 0).
3646 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)3647 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
3648 {
3649 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
3650 }
3651
3652 /**
3653 * @brief Enable trigger interrupt (TIE).
3654 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3655 * @param TIMx Timer instance
3656 * @retval None
3657 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)3658 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3659 {
3660 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3661 }
3662
3663 /**
3664 * @brief Disable trigger interrupt (TIE).
3665 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3666 * @param TIMx Timer instance
3667 * @retval None
3668 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)3669 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3670 {
3671 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3672 }
3673
3674 /**
3675 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3676 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3677 * @param TIMx Timer instance
3678 * @retval State of bit (1 or 0).
3679 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)3680 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
3681 {
3682 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
3683 }
3684
3685 /**
3686 * @brief Enable break interrupt (BIE).
3687 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3688 * @param TIMx Timer instance
3689 * @retval None
3690 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)3691 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3692 {
3693 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3694 }
3695
3696 /**
3697 * @brief Disable break interrupt (BIE).
3698 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3699 * @param TIMx Timer instance
3700 * @retval None
3701 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)3702 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3703 {
3704 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3705 }
3706
3707 /**
3708 * @brief Indicates whether the break interrupt (BIE) is enabled.
3709 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3710 * @param TIMx Timer instance
3711 * @retval State of bit (1 or 0).
3712 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)3713 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
3714 {
3715 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
3716 }
3717
3718 /**
3719 * @}
3720 */
3721
3722 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
3723 * @{
3724 */
3725 /**
3726 * @brief Enable update DMA request (UDE).
3727 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3728 * @param TIMx Timer instance
3729 * @retval None
3730 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3731 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3732 {
3733 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3734 }
3735
3736 /**
3737 * @brief Disable update DMA request (UDE).
3738 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3739 * @param TIMx Timer instance
3740 * @retval None
3741 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3742 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3743 {
3744 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3745 }
3746
3747 /**
3748 * @brief Indicates whether the update DMA request (UDE) is enabled.
3749 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3750 * @param TIMx Timer instance
3751 * @retval State of bit (1 or 0).
3752 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)3753 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
3754 {
3755 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3756 }
3757
3758 /**
3759 * @brief Enable capture/compare 1 DMA request (CC1DE).
3760 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3761 * @param TIMx Timer instance
3762 * @retval None
3763 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3764 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3765 {
3766 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3767 }
3768
3769 /**
3770 * @brief Disable capture/compare 1 DMA request (CC1DE).
3771 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3772 * @param TIMx Timer instance
3773 * @retval None
3774 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3775 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3776 {
3777 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3778 }
3779
3780 /**
3781 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3782 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3783 * @param TIMx Timer instance
3784 * @retval State of bit (1 or 0).
3785 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)3786 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
3787 {
3788 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3789 }
3790
3791 /**
3792 * @brief Enable capture/compare 2 DMA request (CC2DE).
3793 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3794 * @param TIMx Timer instance
3795 * @retval None
3796 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3797 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3798 {
3799 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3800 }
3801
3802 /**
3803 * @brief Disable capture/compare 2 DMA request (CC2DE).
3804 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3805 * @param TIMx Timer instance
3806 * @retval None
3807 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3808 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3809 {
3810 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3811 }
3812
3813 /**
3814 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3815 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3816 * @param TIMx Timer instance
3817 * @retval State of bit (1 or 0).
3818 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)3819 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
3820 {
3821 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3822 }
3823
3824 /**
3825 * @brief Enable capture/compare 3 DMA request (CC3DE).
3826 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3827 * @param TIMx Timer instance
3828 * @retval None
3829 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3830 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3831 {
3832 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3833 }
3834
3835 /**
3836 * @brief Disable capture/compare 3 DMA request (CC3DE).
3837 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3838 * @param TIMx Timer instance
3839 * @retval None
3840 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3841 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3842 {
3843 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3844 }
3845
3846 /**
3847 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3848 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3849 * @param TIMx Timer instance
3850 * @retval State of bit (1 or 0).
3851 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)3852 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
3853 {
3854 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3855 }
3856
3857 /**
3858 * @brief Enable capture/compare 4 DMA request (CC4DE).
3859 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3860 * @param TIMx Timer instance
3861 * @retval None
3862 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3863 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3864 {
3865 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3866 }
3867
3868 /**
3869 * @brief Disable capture/compare 4 DMA request (CC4DE).
3870 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3871 * @param TIMx Timer instance
3872 * @retval None
3873 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3874 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3875 {
3876 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3877 }
3878
3879 /**
3880 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3881 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3882 * @param TIMx Timer instance
3883 * @retval State of bit (1 or 0).
3884 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)3885 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
3886 {
3887 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3888 }
3889
3890 /**
3891 * @brief Enable commutation DMA request (COMDE).
3892 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3893 * @param TIMx Timer instance
3894 * @retval None
3895 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)3896 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3897 {
3898 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3899 }
3900
3901 /**
3902 * @brief Disable commutation DMA request (COMDE).
3903 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3904 * @param TIMx Timer instance
3905 * @retval None
3906 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)3907 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3908 {
3909 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3910 }
3911
3912 /**
3913 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3914 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3915 * @param TIMx Timer instance
3916 * @retval State of bit (1 or 0).
3917 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)3918 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
3919 {
3920 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
3921 }
3922
3923 /**
3924 * @brief Enable trigger interrupt (TDE).
3925 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3926 * @param TIMx Timer instance
3927 * @retval None
3928 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3929 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3930 {
3931 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3932 }
3933
3934 /**
3935 * @brief Disable trigger interrupt (TDE).
3936 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3937 * @param TIMx Timer instance
3938 * @retval None
3939 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3940 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3941 {
3942 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3943 }
3944
3945 /**
3946 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3947 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3948 * @param TIMx Timer instance
3949 * @retval State of bit (1 or 0).
3950 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)3951 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
3952 {
3953 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3954 }
3955
3956 /**
3957 * @}
3958 */
3959
3960 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3961 * @{
3962 */
3963 /**
3964 * @brief Generate an update event.
3965 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3966 * @param TIMx Timer instance
3967 * @retval None
3968 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3969 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3970 {
3971 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3972 }
3973
3974 /**
3975 * @brief Generate Capture/Compare 1 event.
3976 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3977 * @param TIMx Timer instance
3978 * @retval None
3979 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3980 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3981 {
3982 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3983 }
3984
3985 /**
3986 * @brief Generate Capture/Compare 2 event.
3987 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3988 * @param TIMx Timer instance
3989 * @retval None
3990 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3991 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3992 {
3993 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3994 }
3995
3996 /**
3997 * @brief Generate Capture/Compare 3 event.
3998 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3999 * @param TIMx Timer instance
4000 * @retval None
4001 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4002 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4003 {
4004 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4005 }
4006
4007 /**
4008 * @brief Generate Capture/Compare 4 event.
4009 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4010 * @param TIMx Timer instance
4011 * @retval None
4012 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4013 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4014 {
4015 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4016 }
4017
4018 /**
4019 * @brief Generate commutation event.
4020 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4021 * @param TIMx Timer instance
4022 * @retval None
4023 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4024 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4025 {
4026 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4027 }
4028
4029 /**
4030 * @brief Generate trigger event.
4031 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4032 * @param TIMx Timer instance
4033 * @retval None
4034 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4035 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4036 {
4037 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4038 }
4039
4040 /**
4041 * @brief Generate break event.
4042 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4043 * @param TIMx Timer instance
4044 * @retval None
4045 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4046 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4047 {
4048 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4049 }
4050
4051 /**
4052 * @}
4053 */
4054
4055 #if defined(USE_FULL_LL_DRIVER)
4056 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4057 * @{
4058 */
4059
4060 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4061 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4062 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4063 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4064 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4065 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4066 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4067 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4068 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4069 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4070 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4071 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4072 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4073 /**
4074 * @}
4075 */
4076 #endif /* USE_FULL_LL_DRIVER */
4077
4078 /**
4079 * @}
4080 */
4081
4082 /**
4083 * @}
4084 */
4085
4086 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
4087
4088 /**
4089 * @}
4090 */
4091
4092 #ifdef __cplusplus
4093 }
4094 #endif
4095
4096 #endif /* __STM32F4xx_LL_TIM_H */
4097
