1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F4xx_LL_ADC_H
21 #define __STM32F4xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET 0x00000000UL
56 #define ADC_SQR2_REGOFFSET 0x00000100UL
57 #define ADC_SQR3_REGOFFSET 0x00000200UL
58 #define ADC_SQR4_REGOFFSET 0x00000300UL
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
61 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
62
63 /* Definition of ADC group regular sequencer bits information to be inserted */
64 /* into ADC group regular sequencer ranks literals definition. */
65 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
66 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
67 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
68 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
69 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
70 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
71 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
72 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
73 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
74 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
75 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
76 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
77 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
78 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
79 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
80 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
81
82 /* Internal mask for ADC group injected sequencer: */
83 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
84 /* - data register offset */
85 /* - offset register offset */
86 /* - sequencer rank bits position into the selected register */
87
88 /* Internal register offset for ADC group injected data register */
89 /* (offset placed into a spare area of literal definition) */
90 #define ADC_JDR1_REGOFFSET 0x00000000UL
91 #define ADC_JDR2_REGOFFSET 0x00000100UL
92 #define ADC_JDR3_REGOFFSET 0x00000200UL
93 #define ADC_JDR4_REGOFFSET 0x00000300UL
94
95 /* Internal register offset for ADC group injected offset configuration */
96 /* (offset placed into a spare area of literal definition) */
97 #define ADC_JOFR1_REGOFFSET 0x00000000UL
98 #define ADC_JOFR2_REGOFFSET 0x00001000UL
99 #define ADC_JOFR3_REGOFFSET 0x00002000UL
100 #define ADC_JOFR4_REGOFFSET 0x00003000UL
101
102 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
103 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
104 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
105
106 /* Internal mask for ADC group regular trigger: */
107 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
108 /* - regular trigger source */
109 /* - regular trigger edge */
110 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
111
112 /* Mask containing trigger source masks for each of possible */
113 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
114 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
115 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | \
116 ((ADC_CR2_EXTSEL) >> (4UL * 1UL)) | \
117 ((ADC_CR2_EXTSEL) >> (4UL * 2UL)) | \
118 ((ADC_CR2_EXTSEL) >> (4UL * 3UL)))
119
120 /* Mask containing trigger edge masks for each of possible */
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | \
124 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
127
128 /* Definition of ADC group regular trigger bits information. */
129 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
130 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
131
132
133
134 /* Internal mask for ADC group injected trigger: */
135 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
136 /* - injected trigger source */
137 /* - injected trigger edge */
138 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
139
140 /* Mask containing trigger source masks for each of possible */
141 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
142 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
143 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | \
144 ((ADC_CR2_JEXTSEL) >> (4UL * 1UL)) | \
145 ((ADC_CR2_JEXTSEL) >> (4UL * 2UL)) | \
146 ((ADC_CR2_JEXTSEL) >> (4UL * 3UL)))
147
148 /* Mask containing trigger edge masks for each of possible */
149 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
150 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
151 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | \
152 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
155
156 /* Definition of ADC group injected trigger bits information. */
157 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
158 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
159
160 /* Internal mask for ADC channel: */
161 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
162 /* - channel identifier defined by number */
163 /* - channel differentiation between external channels (connected to */
164 /* GPIO pins) and internal channels (connected to internal paths) */
165 /* - channel sampling time defined by SMPRx register offset */
166 /* and SMPx bits positions into SMPRx register */
167 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
168 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
169 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
170 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
171 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
172
173 /* Channel differentiation between external and internal channels */
174 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL /* Marker of internal channel */
175 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
176 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
177 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
178
179 /* Internal register offset for ADC channel sampling time configuration */
180 /* (offset placed into a spare area of literal definition) */
181 #define ADC_SMPR1_REGOFFSET 0x00000000UL
182 #define ADC_SMPR2_REGOFFSET 0x02000000UL
183 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
184
185 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL
186 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
187
188 /* Definition of channels ID number information to be inserted into */
189 /* channels literals definition. */
190 #define ADC_CHANNEL_0_NUMBER 0x00000000UL
191 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
192 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
193 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
194 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
195 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
196 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
197 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
198 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
199 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
200 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
201 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
202 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
203 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
204 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
205 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
206 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
207 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
208 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
209
210 /* Definition of channels sampling time information to be inserted into */
211 /* channels literals definition. */
212 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
213 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
214 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
215 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
216 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
217 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
218 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
219 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
220 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
221 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
222 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
223 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
224 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
225 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
226 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
227 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
228 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
229 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
230 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
231
232 /* Internal mask for ADC analog watchdog: */
233 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
234 /* (concatenation of multiple bits used in different analog watchdogs, */
235 /* (feature of several watchdogs not available on all STM32 families)). */
236 /* - analog watchdog 1: monitored channel defined by number, */
237 /* selection of ADC group (ADC groups regular and-or injected). */
238
239 /* Internal register offset for ADC analog watchdog channel configuration */
240 #define ADC_AWD_CR1_REGOFFSET 0x00000000UL
241
242 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
243
244 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
245 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
246
247 /* Internal register offset for ADC analog watchdog threshold configuration */
248 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000UL
249 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001UL
250 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
251
252 /* ADC registers bits positions */
253 #define ADC_CR1_RES_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
254 #define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
255
256 /* ADC internal channels related definitions */
257 /* Internal voltage reference VrefInt */
258 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
259 #define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
260 /* Temperature sensor */
261 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
262 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
263 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
264 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
265 #define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
266
267 /**
268 * @}
269 */
270
271
272 /* Private macros ------------------------------------------------------------*/
273 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
274 * @{
275 */
276
277 /**
278 * @brief Driver macro reserved for internal use: isolate bits with the
279 * selected mask and shift them to the register LSB
280 * (shift mask on register position bit 0).
281 * @param __BITS__ Bits in register 32 bits
282 * @param __MASK__ Mask in register 32 bits
283 * @retval Bits in register 32 bits
284 */
285 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
286 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
287
288 /**
289 * @brief Driver macro reserved for internal use: set a pointer to
290 * a register from a register basis from which an offset
291 * is applied.
292 * @param __REG__ Register basis from which the offset is applied.
293 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
294 * @retval Pointer to register address
295 */
296 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
297 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
298
299 /**
300 * @}
301 */
302
303
304 /* Exported types ------------------------------------------------------------*/
305 #if defined(USE_FULL_LL_DRIVER)
306 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
307 * @{
308 */
309
310 /**
311 * @brief Structure definition of some features of ADC common parameters
312 * and multimode
313 * (all ADC instances belonging to the same ADC common instance).
314 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
315 * is conditioned to ADC instances state (all ADC instances
316 * sharing the same ADC common instance):
317 * All ADC instances sharing the same ADC common instance must be
318 * disabled.
319 */
320 typedef struct
321 {
322 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
323 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
324
325 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
326
327 #if defined(ADC_MULTIMODE_SUPPORT)
328 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
329 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
330
331 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
332
333 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
334 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
335
336 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
337
338 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
339 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
340
341 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
342 #endif /* ADC_MULTIMODE_SUPPORT */
343
344 } LL_ADC_CommonInitTypeDef;
345
346 /**
347 * @brief Structure definition of some features of ADC instance.
348 * @note These parameters have an impact on ADC scope: ADC instance.
349 * Affects both group regular and group injected (availability
350 * of ADC group injected depends on STM32 families).
351 * Refer to corresponding unitary functions into
352 * @ref ADC_LL_EF_Configuration_ADC_Instance .
353 * @note The setting of these parameters by function @ref LL_ADC_Init()
354 * is conditioned to ADC state:
355 * ADC instance must be disabled.
356 * This condition is applied to all ADC features, for efficiency
357 * and compatibility over all STM32 families. However, the different
358 * features can be set under different ADC state conditions
359 * (setting possible with ADC enabled without conversion on going,
360 * ADC enabled with conversion on going, ...)
361 * Each feature can be updated afterwards with a unitary function
362 * and potentially with ADC in a different state than disabled,
363 * refer to description of each function for setting
364 * conditioned to ADC state.
365 */
366 typedef struct
367 {
368 uint32_t Resolution; /*!< Set ADC resolution.
369 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
370
371 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
372
373 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
374 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
375
376 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
377
378 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
379 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
380
381 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
382
383 } LL_ADC_InitTypeDef;
384
385 /**
386 * @brief Structure definition of some features of ADC group regular.
387 * @note These parameters have an impact on ADC scope: ADC group regular.
388 * Refer to corresponding unitary functions into
389 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
390 * (functions with prefix "REG").
391 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
392 * is conditioned to ADC state:
393 * ADC instance must be disabled.
394 * This condition is applied to all ADC features, for efficiency
395 * and compatibility over all STM32 families. However, the different
396 * features can be set under different ADC state conditions
397 * (setting possible with ADC enabled without conversion on going,
398 * ADC enabled with conversion on going, ...)
399 * Each feature can be updated afterwards with a unitary function
400 * and potentially with ADC in a different state than disabled,
401 * refer to description of each function for setting
402 * conditioned to ADC state.
403 */
404 typedef struct
405 {
406 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
407 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
408 @note On this STM32 series, setting of external trigger edge is performed
409 using function @ref LL_ADC_REG_StartConversionExtTrig().
410
411 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
412
413 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
414 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
415 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
416
417 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
418
419 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
420 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
421 @note This parameter has an effect only if group regular sequencer is enabled
422 (scan length of 2 ranks or more).
423
424 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
425
426 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
427 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
428 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
429
430 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
431
432 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
433 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
434
435 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
436
437 } LL_ADC_REG_InitTypeDef;
438
439 /**
440 * @brief Structure definition of some features of ADC group injected.
441 * @note These parameters have an impact on ADC scope: ADC group injected.
442 * Refer to corresponding unitary functions into
443 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
444 * (functions with prefix "INJ").
445 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
446 * is conditioned to ADC state:
447 * ADC instance must be disabled.
448 * This condition is applied to all ADC features, for efficiency
449 * and compatibility over all STM32 families. However, the different
450 * features can be set under different ADC state conditions
451 * (setting possible with ADC enabled without conversion on going,
452 * ADC enabled with conversion on going, ...)
453 * Each feature can be updated afterwards with a unitary function
454 * and potentially with ADC in a different state than disabled,
455 * refer to description of each function for setting
456 * conditioned to ADC state.
457 */
458 typedef struct
459 {
460 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
461 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
462 @note On this STM32 series, setting of external trigger edge is performed
463 using function @ref LL_ADC_INJ_StartConversionExtTrig().
464
465 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
466
467 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
468 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
469 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
470
471 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
472
473 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
474 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
475 @note This parameter has an effect only if group injected sequencer is enabled
476 (scan length of 2 ranks or more).
477
478 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
479
480 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
481 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
482 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
483
484 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
485
486 } LL_ADC_INJ_InitTypeDef;
487
488 /**
489 * @}
490 */
491 #endif /* USE_FULL_LL_DRIVER */
492
493 /* Exported constants --------------------------------------------------------*/
494 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
495 * @{
496 */
497
498 /** @defgroup ADC_LL_EC_FLAG ADC flags
499 * @brief Flags defines which can be used with LL_ADC_ReadReg function
500 * @{
501 */
502 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
503 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
504 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
505 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
506 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
507 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
508 #if defined(ADC_MULTIMODE_SUPPORT)
509 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
510 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
511 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
512 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
513 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
514 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
515 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
516 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
517 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
518 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
519 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
520 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
521 #endif
522 /**
523 * @}
524 */
525
526 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
527 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
528 * @{
529 */
530 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
531 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
532 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
533 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
534 /**
535 * @}
536 */
537
538 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
539 * @{
540 */
541 /* List of ADC registers intended to be used (most commonly) with */
542 /* DMA transfer. */
543 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
544 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000UL /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
545 #if defined(ADC_MULTIMODE_SUPPORT)
546 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001UL /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
547 #endif
548 /**
549 * @}
550 */
551
552 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
553 * @{
554 */
555 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000UL /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
556 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
557 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
558 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
559 /**
560 * @}
561 */
562
563 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
564 * @{
565 */
566 /* Note: Other measurement paths to internal channels may be available */
567 /* (connections to other peripherals). */
568 /* If they are not listed below, they do not require any specific */
569 /* path enable. In this case, Access to measurement path is done */
570 /* only by selecting the corresponding ADC internal channel. */
571 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000UL /*!< ADC measurement paths all disabled */
572 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
573 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
574 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
575 /**
576 * @}
577 */
578
579 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
580 * @{
581 */
582 #define LL_ADC_RESOLUTION_12B 0x00000000UL /*!< ADC resolution 12 bits */
583 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
584 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
585 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
586 /**
587 * @}
588 */
589
590 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
591 * @{
592 */
593 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000UL /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
594 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
595 /**
596 * @}
597 */
598
599 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
600 * @{
601 */
602 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
603 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
604 /**
605 * @}
606 */
607
608 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
609 * @{
610 */
611 #define LL_ADC_GROUP_REGULAR 0x00000001UL /*!< ADC group regular (available on all STM32 devices) */
612 #define LL_ADC_GROUP_INJECTED 0x00000002UL /*!< ADC group injected (not available on all STM32 devices)*/
613 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003UL /*!< ADC both groups regular and injected */
614 /**
615 * @}
616 */
617
618 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
619 * @{
620 */
621 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
622 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
623 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
624 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
625 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
626 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
627 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
628 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
629 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
630 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
631 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
632 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
633 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
634 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
635 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
636 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
637 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
638 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
639 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
640 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */
641 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */
642 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
643 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */
644 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
645 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
646 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
647 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
648 /**
649 * @}
650 */
651
652 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
653 * @{
654 */
655 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000UL /*!< ADC group regular conversion trigger internal: SW start. */
656 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
657 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
658 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
659 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
660 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
661 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
662 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
663 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
664 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
665 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
666 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
667 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
668 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
669 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
670 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
671 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
672 /**
673 * @}
674 */
675
676 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
677 * @{
678 */
679 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
680 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
681 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
682 /**
683 * @}
684 */
685
686 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
687 * @{
688 */
689 #define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */
690 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
691 /**
692 * @}
693 */
694
695 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
696 * @{
697 */
698 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000UL /*!< ADC conversions are not transferred by DMA */
699 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
700 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
701 /**
702 * @}
703 */
704
705 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
706 * @{
707 */
708 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000UL /*!< ADC flag EOC (end of unitary conversion) selected */
709 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
710 /**
711 * @}
712 */
713
714 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
715 * @{
716 */
717 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
718 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
719 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
720 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
721 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
722 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
723 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
724 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
725 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
726 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
727 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
728 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
729 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
730 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
731 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
732 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
733 /**
734 * @}
735 */
736
737 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
738 * @{
739 */
740 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group regular sequencer discontinuous mode disable */
741 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
742 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
743 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
744 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
745 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
746 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
747 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
748 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
749 /**
750 * @}
751 */
752
753 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
754 * @{
755 */
756 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
757 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
758 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
759 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
760 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
761 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
762 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
763 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
764 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
765 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
766 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
767 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
768 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
769 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
770 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
771 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
772 /**
773 * @}
774 */
775
776 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
777 * @{
778 */
779 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000UL /*!< ADC group injected conversion trigger internal: SW start. */
780 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
781 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
782 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
783 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
784 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
785 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
786 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
787 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
788 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
789 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
790 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
791 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
792 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
793 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
794 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
795 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
796 /**
797 * @}
798 */
799
800 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
801 * @{
802 */
803 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
804 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
805 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
806 /**
807 * @}
808 */
809
810 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
811 * @{
812 */
813 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
814 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
815 /**
816 * @}
817 */
818
819
820 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
821 * @{
822 */
823 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
824 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
825 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
826 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
827 /**
828 * @}
829 */
830
831 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
832 * @{
833 */
834 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group injected sequencer discontinuous mode disable */
835 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
836 /**
837 * @}
838 */
839
840 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
841 * @{
842 */
843 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001UL) /*!< ADC group injected sequencer rank 1 */
844 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002UL) /*!< ADC group injected sequencer rank 2 */
845 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003UL) /*!< ADC group injected sequencer rank 3 */
846 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004UL) /*!< ADC group injected sequencer rank 4 */
847 /**
848 * @}
849 */
850
851 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
852 * @{
853 */
854 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000UL /*!< Sampling time 3 ADC clock cycles */
855 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
856 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
857 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
858 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
859 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
860 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
861 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
862 /**
863 * @}
864 */
865
866 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
867 * @{
868 */
869 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
870 /**
871 * @}
872 */
873
874 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
875 * @{
876 */
877 #define LL_ADC_AWD_DISABLE 0x00000000UL /*!< ADC analog watchdog monitoring disabled */
878 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
879 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
880 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
881 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
882 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
883 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
884 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
885 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
886 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
887 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
888 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
889 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
890 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
891 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
892 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
893 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
894 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
895 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
896 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
897 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
898 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
899 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
900 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
901 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
902 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
903 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
904 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
905 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
906 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
907 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
908 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
909 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
910 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
911 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
912 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
913 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
914 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
915 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
916 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
917 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
918 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
919 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
920 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
921 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
922 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
923 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
924 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
925 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
926 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
927 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
928 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
929 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
930 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
931 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
932 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
933 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
934 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
935 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
936 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
937 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
938 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
939 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
940 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
941 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
942 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
943 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
944 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
945 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
946 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
947 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
948 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
949 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
950 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
951 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
952 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
953 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
954 /**
955 * @}
956 */
957
958 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
959 * @{
960 */
961 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
962 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
963 /**
964 * @}
965 */
966
967 #if defined(ADC_MULTIMODE_SUPPORT)
968 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
969 * @{
970 */
971 #define LL_ADC_MULTI_INDEPENDENT 0x00000000UL /*!< ADC dual mode disabled (ADC independent mode) */
972 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
973 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
974 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
975 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
976 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
977 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
978 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
979 #if defined(ADC3)
980 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
981 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
982 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
983 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
984 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
985 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
986 #endif
987 /**
988 * @}
989 */
990
991 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
992 * @{
993 */
994 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000UL /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
995 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
996 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
997 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
998 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
999 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
1000 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1001 /**
1002 * @}
1003 */
1004
1005 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1006 * @{
1007 */
1008 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000UL /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
1009 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1010 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1011 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1012 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1013 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1014 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1015 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1016 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
1017 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
1018 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
1019 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
1020 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
1021 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
1022 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
1023 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
1024 /**
1025 * @}
1026 */
1027
1028 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1029 * @{
1030 */
1031 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1032 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1033 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1034 /**
1035 * @}
1036 */
1037
1038 #endif /* ADC_MULTIMODE_SUPPORT */
1039
1040
1041 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1042 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1043 * not timeout values.
1044 * For details on delays values, refer to descriptions in source code
1045 * above each literal definition.
1046 * @{
1047 */
1048
1049 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1050 /* not timeout values. */
1051 /* Timeout values for ADC operations are dependent to device clock */
1052 /* configuration (system clock versus ADC clock), */
1053 /* and therefore must be defined in user application. */
1054 /* Indications for estimation of ADC timeout delays, for this */
1055 /* STM32 series: */
1056 /* - ADC enable time: maximum delay is 2us */
1057 /* (refer to device datasheet, parameter "tSTAB") */
1058 /* - ADC conversion time: duration depending on ADC clock and ADC */
1059 /* configuration. */
1060 /* (refer to device reference manual, section "Timing") */
1061
1062 /* Delay for internal voltage reference stabilization time. */
1063 /* Delay set to maximum value (refer to device datasheet, */
1064 /* parameter "tSTART"). */
1065 /* Unit: us */
1066 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */
1067
1068 /* Delay for temperature sensor stabilization time. */
1069 /* Literal set to maximum value (refer to device datasheet, */
1070 /* parameter "tSTART"). */
1071 /* Unit: us */
1072 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */
1073
1074 /**
1075 * @}
1076 */
1077
1078 /**
1079 * @}
1080 */
1081
1082
1083 /* Exported macro ------------------------------------------------------------*/
1084 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1085 * @{
1086 */
1087
1088 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1089 * @{
1090 */
1091
1092 /**
1093 * @brief Write a value in ADC register
1094 * @param __INSTANCE__ ADC Instance
1095 * @param __REG__ Register to be written
1096 * @param __VALUE__ Value to be written in the register
1097 * @retval None
1098 */
1099 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1100
1101 /**
1102 * @brief Read a value in ADC register
1103 * @param __INSTANCE__ ADC Instance
1104 * @param __REG__ Register to be read
1105 * @retval Register value
1106 */
1107 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1108 /**
1109 * @}
1110 */
1111
1112 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1113 * @{
1114 */
1115
1116 /**
1117 * @brief Helper macro to get ADC channel number in decimal format
1118 * from literals LL_ADC_CHANNEL_x.
1119 * @note Example:
1120 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1121 * will return decimal number "4".
1122 * @note The input can be a value from functions where a channel
1123 * number is returned, either defined with number
1124 * or with bitfield (only one bit must be set).
1125 * @param __CHANNEL__ This parameter can be one of the following values:
1126 * @arg @ref LL_ADC_CHANNEL_0
1127 * @arg @ref LL_ADC_CHANNEL_1
1128 * @arg @ref LL_ADC_CHANNEL_2
1129 * @arg @ref LL_ADC_CHANNEL_3
1130 * @arg @ref LL_ADC_CHANNEL_4
1131 * @arg @ref LL_ADC_CHANNEL_5
1132 * @arg @ref LL_ADC_CHANNEL_6
1133 * @arg @ref LL_ADC_CHANNEL_7
1134 * @arg @ref LL_ADC_CHANNEL_8
1135 * @arg @ref LL_ADC_CHANNEL_9
1136 * @arg @ref LL_ADC_CHANNEL_10
1137 * @arg @ref LL_ADC_CHANNEL_11
1138 * @arg @ref LL_ADC_CHANNEL_12
1139 * @arg @ref LL_ADC_CHANNEL_13
1140 * @arg @ref LL_ADC_CHANNEL_14
1141 * @arg @ref LL_ADC_CHANNEL_15
1142 * @arg @ref LL_ADC_CHANNEL_16
1143 * @arg @ref LL_ADC_CHANNEL_17
1144 * @arg @ref LL_ADC_CHANNEL_18
1145 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1146 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1147 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1148 *
1149 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1150 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1151 * @retval Value between Min_Data=0 and Max_Data=18
1152 */
1153 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1154 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1155
1156 /**
1157 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1158 * from number in decimal format.
1159 * @note Example:
1160 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1161 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1162 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1163 * @retval Returned value can be one of the following values:
1164 * @arg @ref LL_ADC_CHANNEL_0
1165 * @arg @ref LL_ADC_CHANNEL_1
1166 * @arg @ref LL_ADC_CHANNEL_2
1167 * @arg @ref LL_ADC_CHANNEL_3
1168 * @arg @ref LL_ADC_CHANNEL_4
1169 * @arg @ref LL_ADC_CHANNEL_5
1170 * @arg @ref LL_ADC_CHANNEL_6
1171 * @arg @ref LL_ADC_CHANNEL_7
1172 * @arg @ref LL_ADC_CHANNEL_8
1173 * @arg @ref LL_ADC_CHANNEL_9
1174 * @arg @ref LL_ADC_CHANNEL_10
1175 * @arg @ref LL_ADC_CHANNEL_11
1176 * @arg @ref LL_ADC_CHANNEL_12
1177 * @arg @ref LL_ADC_CHANNEL_13
1178 * @arg @ref LL_ADC_CHANNEL_14
1179 * @arg @ref LL_ADC_CHANNEL_15
1180 * @arg @ref LL_ADC_CHANNEL_16
1181 * @arg @ref LL_ADC_CHANNEL_17
1182 * @arg @ref LL_ADC_CHANNEL_18
1183 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1184 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1185 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1186 *
1187 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1188 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1189 * (1) For ADC channel read back from ADC register,
1190 * comparison with internal channel parameter to be done
1191 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1192 */
1193 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1194 (((__DECIMAL_NB__) <= 9UL) \
1195 ? ( \
1196 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1197 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1198 ) \
1199 : \
1200 ( \
1201 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1202 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1203 ) \
1204 )
1205
1206 /**
1207 * @brief Helper macro to determine whether the selected channel
1208 * corresponds to literal definitions of driver.
1209 * @note The different literal definitions of ADC channels are:
1210 * - ADC internal channel:
1211 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1212 * - ADC external channel (channel connected to a GPIO pin):
1213 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1214 * @note The channel parameter must be a value defined from literal
1215 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1216 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1217 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1218 * must not be a value from functions where a channel number is
1219 * returned from ADC registers,
1220 * because internal and external channels share the same channel
1221 * number in ADC registers. The differentiation is made only with
1222 * parameters definitions of driver.
1223 * @param __CHANNEL__ This parameter can be one of the following values:
1224 * @arg @ref LL_ADC_CHANNEL_0
1225 * @arg @ref LL_ADC_CHANNEL_1
1226 * @arg @ref LL_ADC_CHANNEL_2
1227 * @arg @ref LL_ADC_CHANNEL_3
1228 * @arg @ref LL_ADC_CHANNEL_4
1229 * @arg @ref LL_ADC_CHANNEL_5
1230 * @arg @ref LL_ADC_CHANNEL_6
1231 * @arg @ref LL_ADC_CHANNEL_7
1232 * @arg @ref LL_ADC_CHANNEL_8
1233 * @arg @ref LL_ADC_CHANNEL_9
1234 * @arg @ref LL_ADC_CHANNEL_10
1235 * @arg @ref LL_ADC_CHANNEL_11
1236 * @arg @ref LL_ADC_CHANNEL_12
1237 * @arg @ref LL_ADC_CHANNEL_13
1238 * @arg @ref LL_ADC_CHANNEL_14
1239 * @arg @ref LL_ADC_CHANNEL_15
1240 * @arg @ref LL_ADC_CHANNEL_16
1241 * @arg @ref LL_ADC_CHANNEL_17
1242 * @arg @ref LL_ADC_CHANNEL_18
1243 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1244 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1245 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1246 *
1247 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1248 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1249 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1250 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1251 */
1252 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1253 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1254
1255 /**
1256 * @brief Helper macro to convert a channel defined from parameter
1257 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1258 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1259 * to its equivalent parameter definition of a ADC external channel
1260 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1261 * @note The channel parameter can be, additionally to a value
1262 * defined from parameter definition of a ADC internal channel
1263 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1264 * a value defined from parameter definition of
1265 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1266 * or a value from functions where a channel number is returned
1267 * from ADC registers.
1268 * @param __CHANNEL__ This parameter can be one of the following values:
1269 * @arg @ref LL_ADC_CHANNEL_0
1270 * @arg @ref LL_ADC_CHANNEL_1
1271 * @arg @ref LL_ADC_CHANNEL_2
1272 * @arg @ref LL_ADC_CHANNEL_3
1273 * @arg @ref LL_ADC_CHANNEL_4
1274 * @arg @ref LL_ADC_CHANNEL_5
1275 * @arg @ref LL_ADC_CHANNEL_6
1276 * @arg @ref LL_ADC_CHANNEL_7
1277 * @arg @ref LL_ADC_CHANNEL_8
1278 * @arg @ref LL_ADC_CHANNEL_9
1279 * @arg @ref LL_ADC_CHANNEL_10
1280 * @arg @ref LL_ADC_CHANNEL_11
1281 * @arg @ref LL_ADC_CHANNEL_12
1282 * @arg @ref LL_ADC_CHANNEL_13
1283 * @arg @ref LL_ADC_CHANNEL_14
1284 * @arg @ref LL_ADC_CHANNEL_15
1285 * @arg @ref LL_ADC_CHANNEL_16
1286 * @arg @ref LL_ADC_CHANNEL_17
1287 * @arg @ref LL_ADC_CHANNEL_18
1288 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1289 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1290 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1291 *
1292 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1293 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1294 * @retval Returned value can be one of the following values:
1295 * @arg @ref LL_ADC_CHANNEL_0
1296 * @arg @ref LL_ADC_CHANNEL_1
1297 * @arg @ref LL_ADC_CHANNEL_2
1298 * @arg @ref LL_ADC_CHANNEL_3
1299 * @arg @ref LL_ADC_CHANNEL_4
1300 * @arg @ref LL_ADC_CHANNEL_5
1301 * @arg @ref LL_ADC_CHANNEL_6
1302 * @arg @ref LL_ADC_CHANNEL_7
1303 * @arg @ref LL_ADC_CHANNEL_8
1304 * @arg @ref LL_ADC_CHANNEL_9
1305 * @arg @ref LL_ADC_CHANNEL_10
1306 * @arg @ref LL_ADC_CHANNEL_11
1307 * @arg @ref LL_ADC_CHANNEL_12
1308 * @arg @ref LL_ADC_CHANNEL_13
1309 * @arg @ref LL_ADC_CHANNEL_14
1310 * @arg @ref LL_ADC_CHANNEL_15
1311 * @arg @ref LL_ADC_CHANNEL_16
1312 * @arg @ref LL_ADC_CHANNEL_17
1313 * @arg @ref LL_ADC_CHANNEL_18
1314 */
1315 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1316 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1317
1318 /**
1319 * @brief Helper macro to determine whether the internal channel
1320 * selected is available on the ADC instance selected.
1321 * @note The channel parameter must be a value defined from parameter
1322 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1323 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1324 * must not be a value defined from parameter definition of
1325 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1326 * or a value from functions where a channel number is
1327 * returned from ADC registers,
1328 * because internal and external channels share the same channel
1329 * number in ADC registers. The differentiation is made only with
1330 * parameters definitions of driver.
1331 * @param __ADC_INSTANCE__ ADC instance
1332 * @param __CHANNEL__ This parameter can be one of the following values:
1333 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1334 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1335 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1336 *
1337 * (1) On STM32F4, parameter available only on ADC instance: ADC1.
1338 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1339 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1340 * Value "1" if the internal channel selected is available on the ADC instance selected.
1341 */
1342 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1343 ( \
1344 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1345 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1346 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1347 )
1348 /**
1349 * @brief Helper macro to define ADC analog watchdog parameter:
1350 * define a single channel to monitor with analog watchdog
1351 * from sequencer channel and groups definition.
1352 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1353 * Example:
1354 * LL_ADC_SetAnalogWDMonitChannels(
1355 * ADC1, LL_ADC_AWD1,
1356 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1357 * @param __CHANNEL__ This parameter can be one of the following values:
1358 * @arg @ref LL_ADC_CHANNEL_0
1359 * @arg @ref LL_ADC_CHANNEL_1
1360 * @arg @ref LL_ADC_CHANNEL_2
1361 * @arg @ref LL_ADC_CHANNEL_3
1362 * @arg @ref LL_ADC_CHANNEL_4
1363 * @arg @ref LL_ADC_CHANNEL_5
1364 * @arg @ref LL_ADC_CHANNEL_6
1365 * @arg @ref LL_ADC_CHANNEL_7
1366 * @arg @ref LL_ADC_CHANNEL_8
1367 * @arg @ref LL_ADC_CHANNEL_9
1368 * @arg @ref LL_ADC_CHANNEL_10
1369 * @arg @ref LL_ADC_CHANNEL_11
1370 * @arg @ref LL_ADC_CHANNEL_12
1371 * @arg @ref LL_ADC_CHANNEL_13
1372 * @arg @ref LL_ADC_CHANNEL_14
1373 * @arg @ref LL_ADC_CHANNEL_15
1374 * @arg @ref LL_ADC_CHANNEL_16
1375 * @arg @ref LL_ADC_CHANNEL_17
1376 * @arg @ref LL_ADC_CHANNEL_18
1377 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1378 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1379 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1380 *
1381 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1382 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1383 * (1) For ADC channel read back from ADC register,
1384 * comparison with internal channel parameter to be done
1385 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1386 * @param __GROUP__ This parameter can be one of the following values:
1387 * @arg @ref LL_ADC_GROUP_REGULAR
1388 * @arg @ref LL_ADC_GROUP_INJECTED
1389 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1390 * @retval Returned value can be one of the following values:
1391 * @arg @ref LL_ADC_AWD_DISABLE
1392 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1393 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1394 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1395 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1396 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1397 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1398 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1399 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1400 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1401 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1402 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1403 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1404 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1405 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1406 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1407 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1408 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1409 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1410 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1411 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1412 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1413 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1414 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1415 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1416 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1417 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1418 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1419 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1420 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1421 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1422 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1423 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1424 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1425 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1426 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1427 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1428 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1429 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1430 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1431 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1432 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1433 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1434 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1435 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1436 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1437 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1438 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1439 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1440 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1441 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1442 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1443 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1444 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1445 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1446 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1447 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1448 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1449 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1450 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
1451 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1452 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1453 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1454 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1455 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
1456 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
1457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
1458 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1459 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
1460 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1461 *
1462 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1463 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1464 */
1465 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1466 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1467 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1468 : \
1469 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1470 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1471 : \
1472 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1473 )
1474
1475 /**
1476 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1477 * or low in function of ADC resolution, when ADC resolution is
1478 * different of 12 bits.
1479 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1480 * Example, with a ADC resolution of 8 bits, to set the value of
1481 * analog watchdog threshold high (on 8 bits):
1482 * LL_ADC_SetAnalogWDThresholds
1483 * (< ADCx param >,
1484 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1485 * );
1486 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1487 * @arg @ref LL_ADC_RESOLUTION_12B
1488 * @arg @ref LL_ADC_RESOLUTION_10B
1489 * @arg @ref LL_ADC_RESOLUTION_8B
1490 * @arg @ref LL_ADC_RESOLUTION_6B
1491 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1492 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1493 */
1494 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1495 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
1496
1497 /**
1498 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1499 * or low in function of ADC resolution, when ADC resolution is
1500 * different of 12 bits.
1501 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1502 * Example, with a ADC resolution of 8 bits, to get the value of
1503 * analog watchdog threshold high (on 8 bits):
1504 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1505 * (LL_ADC_RESOLUTION_8B,
1506 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1507 * );
1508 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1509 * @arg @ref LL_ADC_RESOLUTION_12B
1510 * @arg @ref LL_ADC_RESOLUTION_10B
1511 * @arg @ref LL_ADC_RESOLUTION_8B
1512 * @arg @ref LL_ADC_RESOLUTION_6B
1513 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1514 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1515 */
1516 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1517 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
1518
1519 #if defined(ADC_MULTIMODE_SUPPORT)
1520 /**
1521 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1522 * or ADC slave from raw value with both ADC conversion data concatenated.
1523 * @note This macro is intended to be used when multimode transfer by DMA
1524 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1525 * In this case the transferred data need to processed with this macro
1526 * to separate the conversion data of ADC master and ADC slave.
1527 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1528 * @arg @ref LL_ADC_MULTI_MASTER
1529 * @arg @ref LL_ADC_MULTI_SLAVE
1530 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1531 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1532 */
1533 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1534 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1535 #endif
1536
1537 /**
1538 * @brief Helper macro to select the ADC common instance
1539 * to which is belonging the selected ADC instance.
1540 * @note ADC common register instance can be used for:
1541 * - Set parameters common to several ADC instances
1542 * - Multimode (for devices with several ADC instances)
1543 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1544 * @param __ADCx__ ADC instance
1545 * @retval ADC common register instance
1546 */
1547 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1548 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1549 (ADC123_COMMON)
1550 #elif defined(ADC1) && defined(ADC2)
1551 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1552 (ADC12_COMMON)
1553 #else
1554 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1555 (ADC1_COMMON)
1556 #endif
1557
1558 /**
1559 * @brief Helper macro to check if all ADC instances sharing the same
1560 * ADC common instance are disabled.
1561 * @note This check is required by functions with setting conditioned to
1562 * ADC state:
1563 * All ADC instances of the ADC common group must be disabled.
1564 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1565 * @note On devices with only 1 ADC common instance, parameter of this macro
1566 * is useless and can be ignored (parameter kept for compatibility
1567 * with devices featuring several ADC common instances).
1568 * @param __ADCXY_COMMON__ ADC common instance
1569 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1570 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1571 * are disabled.
1572 * Value "1" if at least one ADC instance sharing the same ADC common instance
1573 * is enabled.
1574 */
1575 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1576 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1577 (LL_ADC_IsEnabled(ADC1) | \
1578 LL_ADC_IsEnabled(ADC2) | \
1579 LL_ADC_IsEnabled(ADC3) )
1580 #elif defined(ADC1) && defined(ADC2)
1581 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1582 (LL_ADC_IsEnabled(ADC1) | \
1583 LL_ADC_IsEnabled(ADC2) )
1584 #else
1585 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1586 (LL_ADC_IsEnabled(ADC1))
1587 #endif
1588
1589 /**
1590 * @brief Helper macro to define the ADC conversion data full-scale digital
1591 * value corresponding to the selected ADC resolution.
1592 * @note ADC conversion data full-scale corresponds to voltage range
1593 * determined by analog voltage references Vref+ and Vref-
1594 * (refer to reference manual).
1595 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1596 * @arg @ref LL_ADC_RESOLUTION_12B
1597 * @arg @ref LL_ADC_RESOLUTION_10B
1598 * @arg @ref LL_ADC_RESOLUTION_8B
1599 * @arg @ref LL_ADC_RESOLUTION_6B
1600 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1601 */
1602 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1603 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))
1604
1605 /**
1606 * @brief Helper macro to convert the ADC conversion data from
1607 * a resolution to another resolution.
1608 * @param __DATA__ ADC conversion data to be converted
1609 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1610 * This parameter can be one of the following values:
1611 * @arg @ref LL_ADC_RESOLUTION_12B
1612 * @arg @ref LL_ADC_RESOLUTION_10B
1613 * @arg @ref LL_ADC_RESOLUTION_8B
1614 * @arg @ref LL_ADC_RESOLUTION_6B
1615 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1616 * This parameter can be one of the following values:
1617 * @arg @ref LL_ADC_RESOLUTION_12B
1618 * @arg @ref LL_ADC_RESOLUTION_10B
1619 * @arg @ref LL_ADC_RESOLUTION_8B
1620 * @arg @ref LL_ADC_RESOLUTION_6B
1621 * @retval ADC conversion data to the requested resolution
1622 */
1623 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1624 (((__DATA__) \
1625 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) \
1626 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)) \
1627 )
1628
1629 /**
1630 * @brief Helper macro to calculate the voltage (unit: mVolt)
1631 * corresponding to a ADC conversion data (unit: digital value).
1632 * @note Analog reference voltage (Vref+) must be either known from
1633 * user board environment or can be calculated using ADC measurement
1634 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1635 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1636 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1637 * (unit: digital value).
1638 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1639 * @arg @ref LL_ADC_RESOLUTION_12B
1640 * @arg @ref LL_ADC_RESOLUTION_10B
1641 * @arg @ref LL_ADC_RESOLUTION_8B
1642 * @arg @ref LL_ADC_RESOLUTION_6B
1643 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1644 */
1645 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1646 __ADC_DATA__,\
1647 __ADC_RESOLUTION__) \
1648 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1649 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1650 )
1651
1652 /**
1653 * @brief Helper macro to calculate analog reference voltage (Vref+)
1654 * (unit: mVolt) from ADC conversion data of internal voltage
1655 * reference VrefInt.
1656 * @note Computation is using VrefInt calibration value
1657 * stored in system memory for each device during production.
1658 * @note This voltage depends on user board environment: voltage level
1659 * connected to pin Vref+.
1660 * On devices with small package, the pin Vref+ is not present
1661 * and internally bonded to pin Vdda.
1662 * @note On this STM32 series, calibration data of internal voltage reference
1663 * VrefInt corresponds to a resolution of 12 bits,
1664 * this is the recommended ADC resolution to convert voltage of
1665 * internal voltage reference VrefInt.
1666 * Otherwise, this macro performs the processing to scale
1667 * ADC conversion data to 12 bits.
1668 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1669 * of internal voltage reference VrefInt (unit: digital value).
1670 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1671 * @arg @ref LL_ADC_RESOLUTION_12B
1672 * @arg @ref LL_ADC_RESOLUTION_10B
1673 * @arg @ref LL_ADC_RESOLUTION_8B
1674 * @arg @ref LL_ADC_RESOLUTION_6B
1675 * @retval Analog reference voltage (unit: mV)
1676 */
1677 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1678 __ADC_RESOLUTION__) \
1679 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1680 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1681 (__ADC_RESOLUTION__), \
1682 LL_ADC_RESOLUTION_12B))
1683
1684 /* Note: On device STM32F4x9, calibration parameter TS_CAL2 is not available. */
1685 /* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
1686 /* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */
1687 #if !defined(STM32F469) && !defined(STM32F479xx) && !defined(STM32F429xx) && !defined(STM32F439xx)
1688 /**
1689 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1690 * from ADC conversion data of internal temperature sensor.
1691 * @note Computation is using temperature sensor calibration values
1692 * stored in system memory for each device during production.
1693 * @note Calculation formula:
1694 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1695 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1696 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1697 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1698 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1699 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1700 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1701 * TEMP_DEGC_CAL1 (calibrated in factory)
1702 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1703 * TEMP_DEGC_CAL2 (calibrated in factory)
1704 * Caution: Calculation relevancy under reserve that calibration
1705 * parameters are correct (address and data).
1706 * To calculate temperature using temperature sensor
1707 * datasheet typical values (generic values less, therefore
1708 * less accurate than calibrated values),
1709 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1710 * @note As calculation input, the analog reference voltage (Vref+) must be
1711 * defined as it impacts the ADC LSB equivalent voltage.
1712 * @note Analog reference voltage (Vref+) must be either known from
1713 * user board environment or can be calculated using ADC measurement
1714 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1715 * @note On this STM32 series, calibration data of temperature sensor
1716 * corresponds to a resolution of 12 bits,
1717 * this is the recommended ADC resolution to convert voltage of
1718 * temperature sensor.
1719 * Otherwise, this macro performs the processing to scale
1720 * ADC conversion data to 12 bits.
1721 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1722 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1723 * temperature sensor (unit: digital value).
1724 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1725 * sensor voltage has been measured.
1726 * This parameter can be one of the following values:
1727 * @arg @ref LL_ADC_RESOLUTION_12B
1728 * @arg @ref LL_ADC_RESOLUTION_10B
1729 * @arg @ref LL_ADC_RESOLUTION_8B
1730 * @arg @ref LL_ADC_RESOLUTION_6B
1731 * @retval Temperature (unit: degree Celsius)
1732 */
1733 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1734 __TEMPSENSOR_ADC_DATA__,\
1735 __ADC_RESOLUTION__) \
1736 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1737 (__ADC_RESOLUTION__), \
1738 LL_ADC_RESOLUTION_12B) \
1739 * (__VREFANALOG_VOLTAGE__)) \
1740 / TEMPSENSOR_CAL_VREFANALOG) \
1741 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1742 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1743 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1744 ) + TEMPSENSOR_CAL1_TEMP \
1745 )
1746 #endif
1747
1748 /**
1749 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1750 * from ADC conversion data of internal temperature sensor.
1751 * @note Computation is using temperature sensor typical values
1752 * (refer to device datasheet).
1753 * @note Calculation formula:
1754 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1755 * / Avg_Slope + CALx_TEMP
1756 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1757 * (unit: digital value)
1758 * Avg_Slope = temperature sensor slope
1759 * (unit: uV/Degree Celsius)
1760 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1761 * temperature CALx_TEMP (unit: mV)
1762 * Caution: Calculation relevancy under reserve the temperature sensor
1763 * of the current device has characteristics in line with
1764 * datasheet typical values.
1765 * If temperature sensor calibration values are available on
1766 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1767 * temperature calculation will be more accurate using
1768 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1769 * @note As calculation input, the analog reference voltage (Vref+) must be
1770 * defined as it impacts the ADC LSB equivalent voltage.
1771 * @note Analog reference voltage (Vref+) must be either known from
1772 * user board environment or can be calculated using ADC measurement
1773 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1774 * @note ADC measurement data must correspond to a resolution of 12bits
1775 * (full scale digital value 4095). If not the case, the data must be
1776 * preliminarily rescaled to an equivalent resolution of 12 bits.
1777 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
1778 * On STM32F4, refer to device datasheet parameter "Avg_Slope".
1779 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
1780 * On STM32F4, refer to device datasheet parameter "V25".
1781 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
1782 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV)
1783 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value).
1784 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1785 * This parameter can be one of the following values:
1786 * @arg @ref LL_ADC_RESOLUTION_12B
1787 * @arg @ref LL_ADC_RESOLUTION_10B
1788 * @arg @ref LL_ADC_RESOLUTION_8B
1789 * @arg @ref LL_ADC_RESOLUTION_6B
1790 * @retval Temperature (unit: degree Celsius)
1791 */
1792 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1793 __TEMPSENSOR_TYP_CALX_V__,\
1794 __TEMPSENSOR_CALX_TEMP__,\
1795 __VREFANALOG_VOLTAGE__,\
1796 __TEMPSENSOR_ADC_DATA__,\
1797 __ADC_RESOLUTION__) \
1798 ((( ( \
1799 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1800 * 1000) \
1801 - \
1802 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1803 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1804 * 1000) \
1805 ) \
1806 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1807 ) + (__TEMPSENSOR_CALX_TEMP__) \
1808 )
1809
1810 /**
1811 * @}
1812 */
1813
1814 /**
1815 * @}
1816 */
1817
1818
1819 /* Exported functions --------------------------------------------------------*/
1820 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1821 * @{
1822 */
1823
1824 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1825 * @{
1826 */
1827 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1828 /* configuration of ADC instance, groups and multimode (if available): */
1829 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1830
1831 /**
1832 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1833 * ADC register address from ADC instance and a list of ADC registers
1834 * intended to be used (most commonly) with DMA transfer.
1835 * @note These ADC registers are data registers:
1836 * when ADC conversion data is available in ADC data registers,
1837 * ADC generates a DMA transfer request.
1838 * @note This macro is intended to be used with LL DMA driver, refer to
1839 * function "LL_DMA_ConfigAddresses()".
1840 * Example:
1841 * LL_DMA_ConfigAddresses(DMA1,
1842 * LL_DMA_CHANNEL_1,
1843 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1844 * (uint32_t)&< array or variable >,
1845 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1846 * @note For devices with several ADC: in multimode, some devices
1847 * use a different data register outside of ADC instance scope
1848 * (common data register). This macro manages this register difference,
1849 * only ADC instance has to be set as parameter.
1850 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
1851 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
1852 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
1853 * @param ADCx ADC instance
1854 * @param Register This parameter can be one of the following values:
1855 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1856 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1857 *
1858 * (1) Available on devices with several ADC instances.
1859 * @retval ADC register address
1860 */
1861 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1862 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1863 {
1864 uint32_t data_reg_addr = 0UL;
1865
1866 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1867 {
1868 /* Retrieve address of register DR */
1869 data_reg_addr = (uint32_t)&(ADCx->DR);
1870 }
1871 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1872 {
1873 /* Retrieve address of register CDR */
1874 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1875 }
1876
1877 return data_reg_addr;
1878 }
1879 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1880 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1881 {
1882 /* Retrieve address of register DR */
1883 return (uint32_t)&(ADCx->DR);
1884 }
1885 #endif
1886
1887 /**
1888 * @}
1889 */
1890
1891 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1892 * @{
1893 */
1894
1895 /**
1896 * @brief Set parameter common to several ADC: Clock source and prescaler.
1897 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
1898 * @param ADCxy_COMMON ADC common instance
1899 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1900 * @param CommonClock This parameter can be one of the following values:
1901 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1902 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1903 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1904 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1905 * @retval None
1906 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1907 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1908 {
1909 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1910 }
1911
1912 /**
1913 * @brief Get parameter common to several ADC: Clock source and prescaler.
1914 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
1915 * @param ADCxy_COMMON ADC common instance
1916 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1917 * @retval Returned value can be one of the following values:
1918 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1919 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1920 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1921 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1922 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)1923 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1924 {
1925 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1926 }
1927
1928 /**
1929 * @brief Set parameter common to several ADC: measurement path to internal
1930 * channels (VrefInt, temperature sensor, ...).
1931 * @note One or several values can be selected.
1932 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1933 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1934 * @note Stabilization time of measurement path to internal channel:
1935 * After enabling internal paths, before starting ADC conversion,
1936 * a delay is required for internal voltage reference and
1937 * temperature sensor stabilization time.
1938 * Refer to device datasheet.
1939 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1940 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1941 * @note ADC internal channel sampling time constraint:
1942 * For ADC conversion of internal channels,
1943 * a sampling time minimum value is required.
1944 * Refer to device datasheet.
1945 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
1946 * CCR VBATE LL_ADC_SetCommonPathInternalCh
1947 * @param ADCxy_COMMON ADC common instance
1948 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1949 * @param PathInternal This parameter can be a combination of the following values:
1950 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1951 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1952 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1953 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1954 * @retval None
1955 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1956 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1957 {
1958 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1959 }
1960
1961 /**
1962 * @brief Get parameter common to several ADC: measurement path to internal
1963 * channels (VrefInt, temperature sensor, ...).
1964 * @note One or several values can be selected.
1965 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1966 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1967 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
1968 * CCR VBATE LL_ADC_GetCommonPathInternalCh
1969 * @param ADCxy_COMMON ADC common instance
1970 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1971 * @retval Returned value can be a combination of the following values:
1972 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1973 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1974 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1975 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1976 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1977 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1978 {
1979 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1980 }
1981
1982 /**
1983 * @}
1984 */
1985
1986 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1987 * @{
1988 */
1989
1990 /**
1991 * @brief Set ADC resolution.
1992 * Refer to reference manual for alignments formats
1993 * dependencies to ADC resolutions.
1994 * @rmtoll CR1 RES LL_ADC_SetResolution
1995 * @param ADCx ADC instance
1996 * @param Resolution This parameter can be one of the following values:
1997 * @arg @ref LL_ADC_RESOLUTION_12B
1998 * @arg @ref LL_ADC_RESOLUTION_10B
1999 * @arg @ref LL_ADC_RESOLUTION_8B
2000 * @arg @ref LL_ADC_RESOLUTION_6B
2001 * @retval None
2002 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2003 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2004 {
2005 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
2006 }
2007
2008 /**
2009 * @brief Get ADC resolution.
2010 * Refer to reference manual for alignments formats
2011 * dependencies to ADC resolutions.
2012 * @rmtoll CR1 RES LL_ADC_GetResolution
2013 * @param ADCx ADC instance
2014 * @retval Returned value can be one of the following values:
2015 * @arg @ref LL_ADC_RESOLUTION_12B
2016 * @arg @ref LL_ADC_RESOLUTION_10B
2017 * @arg @ref LL_ADC_RESOLUTION_8B
2018 * @arg @ref LL_ADC_RESOLUTION_6B
2019 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2020 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2021 {
2022 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
2023 }
2024
2025 /**
2026 * @brief Set ADC conversion data alignment.
2027 * @note Refer to reference manual for alignments formats
2028 * dependencies to ADC resolutions.
2029 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2030 * @param ADCx ADC instance
2031 * @param DataAlignment This parameter can be one of the following values:
2032 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2033 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2034 * @retval None
2035 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2036 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2037 {
2038 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
2039 }
2040
2041 /**
2042 * @brief Get ADC conversion data alignment.
2043 * @note Refer to reference manual for alignments formats
2044 * dependencies to ADC resolutions.
2045 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2046 * @param ADCx ADC instance
2047 * @retval Returned value can be one of the following values:
2048 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2049 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2050 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2051 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2052 {
2053 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
2054 }
2055
2056 /**
2057 * @brief Set ADC sequencers scan mode, for all ADC groups
2058 * (group regular, group injected).
2059 * @note According to sequencers scan mode :
2060 * - If disabled: ADC conversion is performed in unitary conversion
2061 * mode (one channel converted, that defined in rank 1).
2062 * Configuration of sequencers of all ADC groups
2063 * (sequencer scan length, ...) is discarded: equivalent to
2064 * scan length of 1 rank.
2065 * - If enabled: ADC conversions are performed in sequence conversions
2066 * mode, according to configuration of sequencers of
2067 * each ADC group (sequencer scan length, ...).
2068 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2069 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2070 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
2071 * @param ADCx ADC instance
2072 * @param ScanMode This parameter can be one of the following values:
2073 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2074 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2075 * @retval None
2076 */
LL_ADC_SetSequencersScanMode(ADC_TypeDef * ADCx,uint32_t ScanMode)2077 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
2078 {
2079 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
2080 }
2081
2082 /**
2083 * @brief Get ADC sequencers scan mode, for all ADC groups
2084 * (group regular, group injected).
2085 * @note According to sequencers scan mode :
2086 * - If disabled: ADC conversion is performed in unitary conversion
2087 * mode (one channel converted, that defined in rank 1).
2088 * Configuration of sequencers of all ADC groups
2089 * (sequencer scan length, ...) is discarded: equivalent to
2090 * scan length of 1 rank.
2091 * - If enabled: ADC conversions are performed in sequence conversions
2092 * mode, according to configuration of sequencers of
2093 * each ADC group (sequencer scan length, ...).
2094 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2095 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2096 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
2097 * @param ADCx ADC instance
2098 * @retval Returned value can be one of the following values:
2099 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2100 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2101 */
LL_ADC_GetSequencersScanMode(ADC_TypeDef * ADCx)2102 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
2103 {
2104 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2105 }
2106
2107 /**
2108 * @}
2109 */
2110
2111 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2112 * @{
2113 */
2114
2115 /**
2116 * @brief Set ADC group regular conversion trigger source:
2117 * internal (SW start) or from external IP (timer event,
2118 * external interrupt line).
2119 * @note On this STM32 series, setting of external trigger edge is performed
2120 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2121 * @note Availability of parameters of trigger sources from timer
2122 * depends on timers availability on the selected device.
2123 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
2124 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
2125 * @param ADCx ADC instance
2126 * @param TriggerSource This parameter can be one of the following values:
2127 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2128 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2129 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2130 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2131 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2132 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2133 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2134 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2135 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2136 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2137 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2138 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2139 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2140 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2141 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2142 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2143 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2144 * @retval None
2145 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2146 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2147 {
2148 /* Note: On this STM32 series, ADC group regular external trigger edge */
2149 /* is used to perform a ADC conversion start. */
2150 /* This function does not set external trigger edge. */
2151 /* This feature is set using function */
2152 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2153 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2154 }
2155
2156 /**
2157 * @brief Get ADC group regular conversion trigger source:
2158 * internal (SW start) or from external IP (timer event,
2159 * external interrupt line).
2160 * @note To determine whether group regular trigger source is
2161 * internal (SW start) or external, without detail
2162 * of which peripheral is selected as external trigger,
2163 * (equivalent to
2164 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2165 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2166 * @note Availability of parameters of trigger sources from timer
2167 * depends on timers availability on the selected device.
2168 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2169 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2170 * @param ADCx ADC instance
2171 * @retval Returned value can be one of the following values:
2172 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2173 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2174 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2175 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2176 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2177 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2178 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2179 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2180 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2181 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2182 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2183 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2184 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2185 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2186 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2187 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2188 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2189 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2190 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2191 {
2192 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2193
2194 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2195 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2196 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2197
2198 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2199 /* to match with triggers literals definition. */
2200 return ((TriggerSource
2201 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2202 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2203 );
2204 }
2205
2206 /**
2207 * @brief Get ADC group regular conversion trigger source internal (SW start)
2208 or external.
2209 * @note In case of group regular trigger source set to external trigger,
2210 * to determine which peripheral is selected as external trigger,
2211 * use function @ref LL_ADC_REG_GetTriggerSource().
2212 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2213 * @param ADCx ADC instance
2214 * @retval Value "0" if trigger source external trigger
2215 * Value "1" if trigger source SW start.
2216 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2217 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2218 {
2219 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2220 }
2221
2222 /**
2223 * @brief Get ADC group regular conversion trigger polarity.
2224 * @note Applicable only for trigger source set to external trigger.
2225 * @note On this STM32 series, setting of external trigger edge is performed
2226 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2227 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2228 * @param ADCx ADC instance
2229 * @retval Returned value can be one of the following values:
2230 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2231 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2232 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2233 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2234 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2235 {
2236 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2237 }
2238
2239
2240 /**
2241 * @brief Set ADC group regular sequencer length and scan direction.
2242 * @note Description of ADC group regular sequencer features:
2243 * - For devices with sequencer fully configurable
2244 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2245 * sequencer length and each rank affectation to a channel
2246 * are configurable.
2247 * This function performs configuration of:
2248 * - Sequence length: Number of ranks in the scan sequence.
2249 * - Sequence direction: Unless specified in parameters, sequencer
2250 * scan direction is forward (from rank 1 to rank n).
2251 * Sequencer ranks are selected using
2252 * function "LL_ADC_REG_SetSequencerRanks()".
2253 * - For devices with sequencer not fully configurable
2254 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2255 * sequencer length and each rank affectation to a channel
2256 * are defined by channel number.
2257 * This function performs configuration of:
2258 * - Sequence length: Number of ranks in the scan sequence is
2259 * defined by number of channels set in the sequence,
2260 * rank of each channel is fixed by channel HW number.
2261 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2262 * - Sequence direction: Unless specified in parameters, sequencer
2263 * scan direction is forward (from lowest channel number to
2264 * highest channel number).
2265 * Sequencer ranks are selected using
2266 * function "LL_ADC_REG_SetSequencerChannels()".
2267 * @note On this STM32 series, group regular sequencer configuration
2268 * is conditioned to ADC instance sequencer mode.
2269 * If ADC instance sequencer mode is disabled, sequencers of
2270 * all groups (group regular, group injected) can be configured
2271 * but their execution is disabled (limited to rank 1).
2272 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2273 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2274 * ADC conversion on only 1 channel.
2275 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2276 * @param ADCx ADC instance
2277 * @param SequencerNbRanks This parameter can be one of the following values:
2278 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2279 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2280 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2281 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2282 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2283 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2284 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2285 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2286 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2287 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2288 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2289 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2290 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2291 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2292 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2293 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2294 * @retval None
2295 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2296 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2297 {
2298 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2299 }
2300
2301 /**
2302 * @brief Get ADC group regular sequencer length and scan direction.
2303 * @note Description of ADC group regular sequencer features:
2304 * - For devices with sequencer fully configurable
2305 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2306 * sequencer length and each rank affectation to a channel
2307 * are configurable.
2308 * This function retrieves:
2309 * - Sequence length: Number of ranks in the scan sequence.
2310 * - Sequence direction: Unless specified in parameters, sequencer
2311 * scan direction is forward (from rank 1 to rank n).
2312 * Sequencer ranks are selected using
2313 * function "LL_ADC_REG_SetSequencerRanks()".
2314 * - For devices with sequencer not fully configurable
2315 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2316 * sequencer length and each rank affectation to a channel
2317 * are defined by channel number.
2318 * This function retrieves:
2319 * - Sequence length: Number of ranks in the scan sequence is
2320 * defined by number of channels set in the sequence,
2321 * rank of each channel is fixed by channel HW number.
2322 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2323 * - Sequence direction: Unless specified in parameters, sequencer
2324 * scan direction is forward (from lowest channel number to
2325 * highest channel number).
2326 * Sequencer ranks are selected using
2327 * function "LL_ADC_REG_SetSequencerChannels()".
2328 * @note On this STM32 series, group regular sequencer configuration
2329 * is conditioned to ADC instance sequencer mode.
2330 * If ADC instance sequencer mode is disabled, sequencers of
2331 * all groups (group regular, group injected) can be configured
2332 * but their execution is disabled (limited to rank 1).
2333 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2334 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2335 * ADC conversion on only 1 channel.
2336 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2337 * @param ADCx ADC instance
2338 * @retval Returned value can be one of the following values:
2339 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2340 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2341 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2342 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2343 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2344 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2345 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2346 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2347 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2348 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2349 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2350 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2351 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2352 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2353 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2354 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2355 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)2356 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2357 {
2358 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2359 }
2360
2361 /**
2362 * @brief Set ADC group regular sequencer discontinuous mode:
2363 * sequence subdivided and scan conversions interrupted every selected
2364 * number of ranks.
2365 * @note It is not possible to enable both ADC group regular
2366 * continuous mode and sequencer discontinuous mode.
2367 * @note It is not possible to enable both ADC auto-injected mode
2368 * and ADC group regular sequencer discontinuous mode.
2369 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2370 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2371 * @param ADCx ADC instance
2372 * @param SeqDiscont This parameter can be one of the following values:
2373 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2374 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2375 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2376 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2377 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2378 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2379 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2380 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2381 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2382 * @retval None
2383 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2384 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2385 {
2386 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2387 }
2388
2389 /**
2390 * @brief Get ADC group regular sequencer discontinuous mode:
2391 * sequence subdivided and scan conversions interrupted every selected
2392 * number of ranks.
2393 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2394 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2395 * @param ADCx ADC instance
2396 * @retval Returned value can be one of the following values:
2397 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2398 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2399 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2400 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2401 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2402 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2403 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2404 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2405 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2406 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2407 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2408 {
2409 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2410 }
2411
2412 /**
2413 * @brief Set ADC group regular sequence: channel on the selected
2414 * scan sequence rank.
2415 * @note This function performs configuration of:
2416 * - Channels ordering into each rank of scan sequence:
2417 * whatever channel can be placed into whatever rank.
2418 * @note On this STM32 series, ADC group regular sequencer is
2419 * fully configurable: sequencer length and each rank
2420 * affectation to a channel are configurable.
2421 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2422 * @note Depending on devices and packages, some channels may not be available.
2423 * Refer to device datasheet for channels availability.
2424 * @note On this STM32 series, to measure internal channels (VrefInt,
2425 * TempSensor, ...), measurement paths to internal channels must be
2426 * enabled separately.
2427 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2428 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2429 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2430 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2431 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2432 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2433 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2434 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2435 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2436 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2437 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2438 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2439 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2440 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2441 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2442 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2443 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2444 * @param ADCx ADC instance
2445 * @param Rank This parameter can be one of the following values:
2446 * @arg @ref LL_ADC_REG_RANK_1
2447 * @arg @ref LL_ADC_REG_RANK_2
2448 * @arg @ref LL_ADC_REG_RANK_3
2449 * @arg @ref LL_ADC_REG_RANK_4
2450 * @arg @ref LL_ADC_REG_RANK_5
2451 * @arg @ref LL_ADC_REG_RANK_6
2452 * @arg @ref LL_ADC_REG_RANK_7
2453 * @arg @ref LL_ADC_REG_RANK_8
2454 * @arg @ref LL_ADC_REG_RANK_9
2455 * @arg @ref LL_ADC_REG_RANK_10
2456 * @arg @ref LL_ADC_REG_RANK_11
2457 * @arg @ref LL_ADC_REG_RANK_12
2458 * @arg @ref LL_ADC_REG_RANK_13
2459 * @arg @ref LL_ADC_REG_RANK_14
2460 * @arg @ref LL_ADC_REG_RANK_15
2461 * @arg @ref LL_ADC_REG_RANK_16
2462 * @param Channel This parameter can be one of the following values:
2463 * @arg @ref LL_ADC_CHANNEL_0
2464 * @arg @ref LL_ADC_CHANNEL_1
2465 * @arg @ref LL_ADC_CHANNEL_2
2466 * @arg @ref LL_ADC_CHANNEL_3
2467 * @arg @ref LL_ADC_CHANNEL_4
2468 * @arg @ref LL_ADC_CHANNEL_5
2469 * @arg @ref LL_ADC_CHANNEL_6
2470 * @arg @ref LL_ADC_CHANNEL_7
2471 * @arg @ref LL_ADC_CHANNEL_8
2472 * @arg @ref LL_ADC_CHANNEL_9
2473 * @arg @ref LL_ADC_CHANNEL_10
2474 * @arg @ref LL_ADC_CHANNEL_11
2475 * @arg @ref LL_ADC_CHANNEL_12
2476 * @arg @ref LL_ADC_CHANNEL_13
2477 * @arg @ref LL_ADC_CHANNEL_14
2478 * @arg @ref LL_ADC_CHANNEL_15
2479 * @arg @ref LL_ADC_CHANNEL_16
2480 * @arg @ref LL_ADC_CHANNEL_17
2481 * @arg @ref LL_ADC_CHANNEL_18
2482 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2483 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2484 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2485 *
2486 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2487 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2488 * @retval None
2489 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2490 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2491 {
2492 /* Set bits with content of parameter "Channel" with bits position */
2493 /* in register and register position depending on parameter "Rank". */
2494 /* Parameters "Rank" and "Channel" are used with masks because containing */
2495 /* other bits reserved for other purpose. */
2496 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2497
2498 MODIFY_REG(*preg,
2499 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2500 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2501 }
2502
2503 /**
2504 * @brief Get ADC group regular sequence: channel on the selected
2505 * scan sequence rank.
2506 * @note On this STM32 series, ADC group regular sequencer is
2507 * fully configurable: sequencer length and each rank
2508 * affectation to a channel are configurable.
2509 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2510 * @note Depending on devices and packages, some channels may not be available.
2511 * Refer to device datasheet for channels availability.
2512 * @note Usage of the returned channel number:
2513 * - To reinject this channel into another function LL_ADC_xxx:
2514 * the returned channel number is only partly formatted on definition
2515 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2516 * with parts of literals LL_ADC_CHANNEL_x or using
2517 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2518 * Then the selected literal LL_ADC_CHANNEL_x can be used
2519 * as parameter for another function.
2520 * - To get the channel number in decimal format:
2521 * process the returned value with the helper macro
2522 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2523 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2524 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2525 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2526 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2527 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2528 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2529 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2530 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2531 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2532 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2533 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2534 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2535 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2536 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2537 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2538 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2539 * @param ADCx ADC instance
2540 * @param Rank This parameter can be one of the following values:
2541 * @arg @ref LL_ADC_REG_RANK_1
2542 * @arg @ref LL_ADC_REG_RANK_2
2543 * @arg @ref LL_ADC_REG_RANK_3
2544 * @arg @ref LL_ADC_REG_RANK_4
2545 * @arg @ref LL_ADC_REG_RANK_5
2546 * @arg @ref LL_ADC_REG_RANK_6
2547 * @arg @ref LL_ADC_REG_RANK_7
2548 * @arg @ref LL_ADC_REG_RANK_8
2549 * @arg @ref LL_ADC_REG_RANK_9
2550 * @arg @ref LL_ADC_REG_RANK_10
2551 * @arg @ref LL_ADC_REG_RANK_11
2552 * @arg @ref LL_ADC_REG_RANK_12
2553 * @arg @ref LL_ADC_REG_RANK_13
2554 * @arg @ref LL_ADC_REG_RANK_14
2555 * @arg @ref LL_ADC_REG_RANK_15
2556 * @arg @ref LL_ADC_REG_RANK_16
2557 * @retval Returned value can be one of the following values:
2558 * @arg @ref LL_ADC_CHANNEL_0
2559 * @arg @ref LL_ADC_CHANNEL_1
2560 * @arg @ref LL_ADC_CHANNEL_2
2561 * @arg @ref LL_ADC_CHANNEL_3
2562 * @arg @ref LL_ADC_CHANNEL_4
2563 * @arg @ref LL_ADC_CHANNEL_5
2564 * @arg @ref LL_ADC_CHANNEL_6
2565 * @arg @ref LL_ADC_CHANNEL_7
2566 * @arg @ref LL_ADC_CHANNEL_8
2567 * @arg @ref LL_ADC_CHANNEL_9
2568 * @arg @ref LL_ADC_CHANNEL_10
2569 * @arg @ref LL_ADC_CHANNEL_11
2570 * @arg @ref LL_ADC_CHANNEL_12
2571 * @arg @ref LL_ADC_CHANNEL_13
2572 * @arg @ref LL_ADC_CHANNEL_14
2573 * @arg @ref LL_ADC_CHANNEL_15
2574 * @arg @ref LL_ADC_CHANNEL_16
2575 * @arg @ref LL_ADC_CHANNEL_17
2576 * @arg @ref LL_ADC_CHANNEL_18
2577 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2578 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2579 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2580 *
2581 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2582 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2583 * (1) For ADC channel read back from ADC register,
2584 * comparison with internal channel parameter to be done
2585 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2586 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)2587 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2588 {
2589 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2590
2591 return (uint32_t) (READ_BIT(*preg,
2592 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2593 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2594 );
2595 }
2596
2597 /**
2598 * @brief Set ADC continuous conversion mode on ADC group regular.
2599 * @note Description of ADC continuous conversion mode:
2600 * - single mode: one conversion per trigger
2601 * - continuous mode: after the first trigger, following
2602 * conversions launched successively automatically.
2603 * @note It is not possible to enable both ADC group regular
2604 * continuous mode and sequencer discontinuous mode.
2605 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2606 * @param ADCx ADC instance
2607 * @param Continuous This parameter can be one of the following values:
2608 * @arg @ref LL_ADC_REG_CONV_SINGLE
2609 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2610 * @retval None
2611 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)2612 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2613 {
2614 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2615 }
2616
2617 /**
2618 * @brief Get ADC continuous conversion mode on ADC group regular.
2619 * @note Description of ADC continuous conversion mode:
2620 * - single mode: one conversion per trigger
2621 * - continuous mode: after the first trigger, following
2622 * conversions launched successively automatically.
2623 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2624 * @param ADCx ADC instance
2625 * @retval Returned value can be one of the following values:
2626 * @arg @ref LL_ADC_REG_CONV_SINGLE
2627 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2628 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)2629 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2630 {
2631 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2632 }
2633
2634 /**
2635 * @brief Set ADC group regular conversion data transfer: no transfer or
2636 * transfer by DMA, and DMA requests mode.
2637 * @note If transfer by DMA selected, specifies the DMA requests
2638 * mode:
2639 * - Limited mode (One shot mode): DMA transfer requests are stopped
2640 * when number of DMA data transfers (number of
2641 * ADC conversions) is reached.
2642 * This ADC mode is intended to be used with DMA mode non-circular.
2643 * - Unlimited mode: DMA transfer requests are unlimited,
2644 * whatever number of DMA data transfers (number of
2645 * ADC conversions).
2646 * This ADC mode is intended to be used with DMA mode circular.
2647 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2648 * mode non-circular:
2649 * when DMA transfers size will be reached, DMA will stop transfers of
2650 * ADC conversions data ADC will raise an overrun error
2651 * (overrun flag and interruption if enabled).
2652 * @note For devices with several ADC instances: ADC multimode DMA
2653 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
2654 * @note To configure DMA source address (peripheral address),
2655 * use function @ref LL_ADC_DMA_GetRegAddr().
2656 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
2657 * CR2 DDS LL_ADC_REG_SetDMATransfer
2658 * @param ADCx ADC instance
2659 * @param DMATransfer This parameter can be one of the following values:
2660 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2661 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2662 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2663 * @retval None
2664 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)2665 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2666 {
2667 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2668 }
2669
2670 /**
2671 * @brief Get ADC group regular conversion data transfer: no transfer or
2672 * transfer by DMA, and DMA requests mode.
2673 * @note If transfer by DMA selected, specifies the DMA requests
2674 * mode:
2675 * - Limited mode (One shot mode): DMA transfer requests are stopped
2676 * when number of DMA data transfers (number of
2677 * ADC conversions) is reached.
2678 * This ADC mode is intended to be used with DMA mode non-circular.
2679 * - Unlimited mode: DMA transfer requests are unlimited,
2680 * whatever number of DMA data transfers (number of
2681 * ADC conversions).
2682 * This ADC mode is intended to be used with DMA mode circular.
2683 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2684 * mode non-circular:
2685 * when DMA transfers size will be reached, DMA will stop transfers of
2686 * ADC conversions data ADC will raise an overrun error
2687 * (overrun flag and interruption if enabled).
2688 * @note For devices with several ADC instances: ADC multimode DMA
2689 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
2690 * @note To configure DMA source address (peripheral address),
2691 * use function @ref LL_ADC_DMA_GetRegAddr().
2692 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
2693 * CR2 DDS LL_ADC_REG_GetDMATransfer
2694 * @param ADCx ADC instance
2695 * @retval Returned value can be one of the following values:
2696 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2697 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2698 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2699 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)2700 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2701 {
2702 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2703 }
2704
2705 /**
2706 * @brief Specify which ADC flag between EOC (end of unitary conversion)
2707 * or EOS (end of sequence conversions) is used to indicate
2708 * the end of conversion.
2709 * @note This feature is aimed to be set when using ADC with
2710 * programming model by polling or interruption
2711 * (programming model by DMA usually uses DMA interruptions
2712 * to indicate end of conversion and data transfer).
2713 * @note For ADC group injected, end of conversion (flag&IT) is raised
2714 * only at the end of the sequence.
2715 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
2716 * @param ADCx ADC instance
2717 * @param EocSelection This parameter can be one of the following values:
2718 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2719 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2720 * @retval None
2721 */
LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef * ADCx,uint32_t EocSelection)2722 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2723 {
2724 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2725 }
2726
2727 /**
2728 * @brief Get which ADC flag between EOC (end of unitary conversion)
2729 * or EOS (end of sequence conversions) is used to indicate
2730 * the end of conversion.
2731 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
2732 * @param ADCx ADC instance
2733 * @retval Returned value can be one of the following values:
2734 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2735 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2736 */
LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef * ADCx)2737 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
2738 {
2739 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2740 }
2741
2742 /**
2743 * @}
2744 */
2745
2746 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2747 * @{
2748 */
2749
2750 /**
2751 * @brief Set ADC group injected conversion trigger source:
2752 * internal (SW start) or from external IP (timer event,
2753 * external interrupt line).
2754 * @note On this STM32 series, setting of external trigger edge is performed
2755 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
2756 * @note Availability of parameters of trigger sources from timer
2757 * depends on timers availability on the selected device.
2758 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
2759 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
2760 * @param ADCx ADC instance
2761 * @param TriggerSource This parameter can be one of the following values:
2762 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2763 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2764 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2765 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2766 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2767 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2768 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2769 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2770 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2771 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2772 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2773 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2774 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2775 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2776 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2777 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2778 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2779 * @retval None
2780 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2781 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2782 {
2783 /* Note: On this STM32 series, ADC group injected external trigger edge */
2784 /* is used to perform a ADC conversion start. */
2785 /* This function does not set external trigger edge. */
2786 /* This feature is set using function */
2787 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2788 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2789 }
2790
2791 /**
2792 * @brief Get ADC group injected conversion trigger source:
2793 * internal (SW start) or from external IP (timer event,
2794 * external interrupt line).
2795 * @note To determine whether group injected trigger source is
2796 * internal (SW start) or external, without detail
2797 * of which peripheral is selected as external trigger,
2798 * (equivalent to
2799 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2800 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2801 * @note Availability of parameters of trigger sources from timer
2802 * depends on timers availability on the selected device.
2803 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
2804 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
2805 * @param ADCx ADC instance
2806 * @retval Returned value can be one of the following values:
2807 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2808 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2809 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2810 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2811 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2812 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2813 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2814 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2815 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2816 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2817 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2818 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2819 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2820 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2821 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2822 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2823 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2824 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)2825 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
2826 {
2827 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2828
2829 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2830 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2831 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2832
2833 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2834 /* to match with triggers literals definition. */
2835 return ((TriggerSource
2836 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2837 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2838 );
2839 }
2840
2841 /**
2842 * @brief Get ADC group injected conversion trigger source internal (SW start)
2843 or external
2844 * @note In case of group injected trigger source set to external trigger,
2845 * to determine which peripheral is selected as external trigger,
2846 * use function @ref LL_ADC_INJ_GetTriggerSource.
2847 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
2848 * @param ADCx ADC instance
2849 * @retval Value "0" if trigger source external trigger
2850 * Value "1" if trigger source SW start.
2851 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2852 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2853 {
2854 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2855 }
2856
2857 /**
2858 * @brief Get ADC group injected conversion trigger polarity.
2859 * Applicable only for trigger source set to external trigger.
2860 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
2861 * @param ADCx ADC instance
2862 * @retval Returned value can be one of the following values:
2863 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
2864 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
2865 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
2866 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)2867 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
2868 {
2869 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2870 }
2871
2872 /**
2873 * @brief Set ADC group injected sequencer length and scan direction.
2874 * @note This function performs configuration of:
2875 * - Sequence length: Number of ranks in the scan sequence.
2876 * - Sequence direction: Unless specified in parameters, sequencer
2877 * scan direction is forward (from rank 1 to rank n).
2878 * @note On this STM32 series, group injected sequencer configuration
2879 * is conditioned to ADC instance sequencer mode.
2880 * If ADC instance sequencer mode is disabled, sequencers of
2881 * all groups (group regular, group injected) can be configured
2882 * but their execution is disabled (limited to rank 1).
2883 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2884 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2885 * ADC conversion on only 1 channel.
2886 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2887 * @param ADCx ADC instance
2888 * @param SequencerNbRanks This parameter can be one of the following values:
2889 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2890 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2891 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2892 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2893 * @retval None
2894 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2895 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2896 {
2897 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2898 }
2899
2900 /**
2901 * @brief Get ADC group injected sequencer length and scan direction.
2902 * @note This function retrieves:
2903 * - Sequence length: Number of ranks in the scan sequence.
2904 * - Sequence direction: Unless specified in parameters, sequencer
2905 * scan direction is forward (from rank 1 to rank n).
2906 * @note On this STM32 series, group injected sequencer configuration
2907 * is conditioned to ADC instance sequencer mode.
2908 * If ADC instance sequencer mode is disabled, sequencers of
2909 * all groups (group regular, group injected) can be configured
2910 * but their execution is disabled (limited to rank 1).
2911 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2912 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2913 * ADC conversion on only 1 channel.
2914 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2915 * @param ADCx ADC instance
2916 * @retval Returned value can be one of the following values:
2917 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2918 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2919 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2920 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2921 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)2922 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
2923 {
2924 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2925 }
2926
2927 /**
2928 * @brief Set ADC group injected sequencer discontinuous mode:
2929 * sequence subdivided and scan conversions interrupted every selected
2930 * number of ranks.
2931 * @note It is not possible to enable both ADC group injected
2932 * auto-injected mode and sequencer discontinuous mode.
2933 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2934 * @param ADCx ADC instance
2935 * @param SeqDiscont This parameter can be one of the following values:
2936 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2937 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2938 * @retval None
2939 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2940 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2941 {
2942 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2943 }
2944
2945 /**
2946 * @brief Get ADC group injected sequencer discontinuous mode:
2947 * sequence subdivided and scan conversions interrupted every selected
2948 * number of ranks.
2949 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2950 * @param ADCx ADC instance
2951 * @retval Returned value can be one of the following values:
2952 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2953 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2954 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)2955 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
2956 {
2957 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2958 }
2959
2960 /**
2961 * @brief Set ADC group injected sequence: channel on the selected
2962 * sequence rank.
2963 * @note Depending on devices and packages, some channels may not be available.
2964 * Refer to device datasheet for channels availability.
2965 * @note On this STM32 series, to measure internal channels (VrefInt,
2966 * TempSensor, ...), measurement paths to internal channels must be
2967 * enabled separately.
2968 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2969 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2970 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2971 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2972 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2973 * @param ADCx ADC instance
2974 * @param Rank This parameter can be one of the following values:
2975 * @arg @ref LL_ADC_INJ_RANK_1
2976 * @arg @ref LL_ADC_INJ_RANK_2
2977 * @arg @ref LL_ADC_INJ_RANK_3
2978 * @arg @ref LL_ADC_INJ_RANK_4
2979 * @param Channel This parameter can be one of the following values:
2980 * @arg @ref LL_ADC_CHANNEL_0
2981 * @arg @ref LL_ADC_CHANNEL_1
2982 * @arg @ref LL_ADC_CHANNEL_2
2983 * @arg @ref LL_ADC_CHANNEL_3
2984 * @arg @ref LL_ADC_CHANNEL_4
2985 * @arg @ref LL_ADC_CHANNEL_5
2986 * @arg @ref LL_ADC_CHANNEL_6
2987 * @arg @ref LL_ADC_CHANNEL_7
2988 * @arg @ref LL_ADC_CHANNEL_8
2989 * @arg @ref LL_ADC_CHANNEL_9
2990 * @arg @ref LL_ADC_CHANNEL_10
2991 * @arg @ref LL_ADC_CHANNEL_11
2992 * @arg @ref LL_ADC_CHANNEL_12
2993 * @arg @ref LL_ADC_CHANNEL_13
2994 * @arg @ref LL_ADC_CHANNEL_14
2995 * @arg @ref LL_ADC_CHANNEL_15
2996 * @arg @ref LL_ADC_CHANNEL_16
2997 * @arg @ref LL_ADC_CHANNEL_17
2998 * @arg @ref LL_ADC_CHANNEL_18
2999 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3000 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3001 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3002 *
3003 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3004 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3005 * @retval None
3006 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3007 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3008 {
3009 /* Set bits with content of parameter "Channel" with bits position */
3010 /* in register depending on parameter "Rank". */
3011 /* Parameters "Rank" and "Channel" are used with masks because containing */
3012 /* other bits reserved for other purpose. */
3013 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
3014
3015 MODIFY_REG(ADCx->JSQR,
3016 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))),
3017 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))));
3018 }
3019
3020 /**
3021 * @brief Get ADC group injected sequence: channel on the selected
3022 * sequence rank.
3023 * @note Depending on devices and packages, some channels may not be available.
3024 * Refer to device datasheet for channels availability.
3025 * @note Usage of the returned channel number:
3026 * - To reinject this channel into another function LL_ADC_xxx:
3027 * the returned channel number is only partly formatted on definition
3028 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3029 * with parts of literals LL_ADC_CHANNEL_x or using
3030 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3031 * Then the selected literal LL_ADC_CHANNEL_x can be used
3032 * as parameter for another function.
3033 * - To get the channel number in decimal format:
3034 * process the returned value with the helper macro
3035 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3036 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
3037 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
3038 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
3039 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
3040 * @param ADCx ADC instance
3041 * @param Rank This parameter can be one of the following values:
3042 * @arg @ref LL_ADC_INJ_RANK_1
3043 * @arg @ref LL_ADC_INJ_RANK_2
3044 * @arg @ref LL_ADC_INJ_RANK_3
3045 * @arg @ref LL_ADC_INJ_RANK_4
3046 * @retval Returned value can be one of the following values:
3047 * @arg @ref LL_ADC_CHANNEL_0
3048 * @arg @ref LL_ADC_CHANNEL_1
3049 * @arg @ref LL_ADC_CHANNEL_2
3050 * @arg @ref LL_ADC_CHANNEL_3
3051 * @arg @ref LL_ADC_CHANNEL_4
3052 * @arg @ref LL_ADC_CHANNEL_5
3053 * @arg @ref LL_ADC_CHANNEL_6
3054 * @arg @ref LL_ADC_CHANNEL_7
3055 * @arg @ref LL_ADC_CHANNEL_8
3056 * @arg @ref LL_ADC_CHANNEL_9
3057 * @arg @ref LL_ADC_CHANNEL_10
3058 * @arg @ref LL_ADC_CHANNEL_11
3059 * @arg @ref LL_ADC_CHANNEL_12
3060 * @arg @ref LL_ADC_CHANNEL_13
3061 * @arg @ref LL_ADC_CHANNEL_14
3062 * @arg @ref LL_ADC_CHANNEL_15
3063 * @arg @ref LL_ADC_CHANNEL_16
3064 * @arg @ref LL_ADC_CHANNEL_17
3065 * @arg @ref LL_ADC_CHANNEL_18
3066 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3067 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3068 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3069 *
3070 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3071 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
3072 * (1) For ADC channel read back from ADC register,
3073 * comparison with internal channel parameter to be done
3074 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3075 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3076 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3077 {
3078 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
3079
3080 return (uint32_t)(READ_BIT(ADCx->JSQR,
3081 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))))
3082 >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))
3083 );
3084 }
3085
3086 /**
3087 * @brief Set ADC group injected conversion trigger:
3088 * independent or from ADC group regular.
3089 * @note This mode can be used to extend number of data registers
3090 * updated after one ADC conversion trigger and with data
3091 * permanently kept (not erased by successive conversions of scan of
3092 * ADC sequencer ranks), up to 5 data registers:
3093 * 1 data register on ADC group regular, 4 data registers
3094 * on ADC group injected.
3095 * @note If ADC group injected injected trigger source is set to an
3096 * external trigger, this feature must be must be set to
3097 * independent trigger.
3098 * ADC group injected automatic trigger is compliant only with
3099 * group injected trigger source set to SW start, without any
3100 * further action on ADC group injected conversion start or stop:
3101 * in this case, ADC group injected is controlled only
3102 * from ADC group regular.
3103 * @note It is not possible to enable both ADC group injected
3104 * auto-injected mode and sequencer discontinuous mode.
3105 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
3106 * @param ADCx ADC instance
3107 * @param TrigAuto This parameter can be one of the following values:
3108 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3109 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3110 * @retval None
3111 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)3112 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3113 {
3114 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3115 }
3116
3117 /**
3118 * @brief Get ADC group injected conversion trigger:
3119 * independent or from ADC group regular.
3120 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
3121 * @param ADCx ADC instance
3122 * @retval Returned value can be one of the following values:
3123 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3124 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3125 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)3126 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
3127 {
3128 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3129 }
3130
3131 /**
3132 * @brief Set ADC group injected offset.
3133 * @note It sets:
3134 * - ADC group injected rank to which the offset programmed
3135 * will be applied
3136 * - Offset level (offset to be subtracted from the raw
3137 * converted data).
3138 * Caution: Offset format is dependent to ADC resolution:
3139 * offset has to be left-aligned on bit 11, the LSB (right bits)
3140 * are set to 0.
3141 * @note Offset cannot be enabled or disabled.
3142 * To emulate offset disabled, set an offset value equal to 0.
3143 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
3144 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
3145 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
3146 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
3147 * @param ADCx ADC instance
3148 * @param Rank This parameter can be one of the following values:
3149 * @arg @ref LL_ADC_INJ_RANK_1
3150 * @arg @ref LL_ADC_INJ_RANK_2
3151 * @arg @ref LL_ADC_INJ_RANK_3
3152 * @arg @ref LL_ADC_INJ_RANK_4
3153 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3154 * @retval None
3155 */
LL_ADC_INJ_SetOffset(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t OffsetLevel)3156 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3157 {
3158 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3159
3160 MODIFY_REG(*preg,
3161 ADC_JOFR1_JOFFSET1,
3162 OffsetLevel);
3163 }
3164
3165 /**
3166 * @brief Get ADC group injected offset.
3167 * @note It gives offset level (offset to be subtracted from the raw converted data).
3168 * Caution: Offset format is dependent to ADC resolution:
3169 * offset has to be left-aligned on bit 11, the LSB (right bits)
3170 * are set to 0.
3171 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3172 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3173 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3174 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3175 * @param ADCx ADC instance
3176 * @param Rank This parameter can be one of the following values:
3177 * @arg @ref LL_ADC_INJ_RANK_1
3178 * @arg @ref LL_ADC_INJ_RANK_2
3179 * @arg @ref LL_ADC_INJ_RANK_3
3180 * @arg @ref LL_ADC_INJ_RANK_4
3181 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3182 */
LL_ADC_INJ_GetOffset(ADC_TypeDef * ADCx,uint32_t Rank)3183 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
3184 {
3185 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3186
3187 return (uint32_t)(READ_BIT(*preg,
3188 ADC_JOFR1_JOFFSET1)
3189 );
3190 }
3191
3192 /**
3193 * @}
3194 */
3195
3196 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3197 * @{
3198 */
3199
3200 /**
3201 * @brief Set sampling time of the selected ADC channel
3202 * Unit: ADC clock cycles.
3203 * @note On this device, sampling time is on channel scope: independently
3204 * of channel mapped on ADC group regular or injected.
3205 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3206 * converted:
3207 * sampling time constraints must be respected (sampling time can be
3208 * adjusted in function of ADC clock frequency and sampling time
3209 * setting).
3210 * Refer to device datasheet for timings values (parameters TS_vrefint,
3211 * TS_temp, ...).
3212 * @note Conversion time is the addition of sampling time and processing time.
3213 * Refer to reference manual for ADC processing time of
3214 * this STM32 series.
3215 * @note In case of ADC conversion of internal channel (VrefInt,
3216 * temperature sensor, ...), a sampling time minimum value
3217 * is required.
3218 * Refer to device datasheet.
3219 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
3220 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
3221 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
3222 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
3223 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
3224 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
3225 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
3226 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
3227 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
3228 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
3229 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
3230 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
3231 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
3232 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
3233 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
3234 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
3235 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
3236 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
3237 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
3238 * @param ADCx ADC instance
3239 * @param Channel This parameter can be one of the following values:
3240 * @arg @ref LL_ADC_CHANNEL_0
3241 * @arg @ref LL_ADC_CHANNEL_1
3242 * @arg @ref LL_ADC_CHANNEL_2
3243 * @arg @ref LL_ADC_CHANNEL_3
3244 * @arg @ref LL_ADC_CHANNEL_4
3245 * @arg @ref LL_ADC_CHANNEL_5
3246 * @arg @ref LL_ADC_CHANNEL_6
3247 * @arg @ref LL_ADC_CHANNEL_7
3248 * @arg @ref LL_ADC_CHANNEL_8
3249 * @arg @ref LL_ADC_CHANNEL_9
3250 * @arg @ref LL_ADC_CHANNEL_10
3251 * @arg @ref LL_ADC_CHANNEL_11
3252 * @arg @ref LL_ADC_CHANNEL_12
3253 * @arg @ref LL_ADC_CHANNEL_13
3254 * @arg @ref LL_ADC_CHANNEL_14
3255 * @arg @ref LL_ADC_CHANNEL_15
3256 * @arg @ref LL_ADC_CHANNEL_16
3257 * @arg @ref LL_ADC_CHANNEL_17
3258 * @arg @ref LL_ADC_CHANNEL_18
3259 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3260 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3261 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3262 *
3263 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3264 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3265 * @param SamplingTime This parameter can be one of the following values:
3266 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3267 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3268 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3269 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3270 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3271 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3272 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3273 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3274 * @retval None
3275 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)3276 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3277 {
3278 /* Set bits with content of parameter "SamplingTime" with bits position */
3279 /* in register and register position depending on parameter "Channel". */
3280 /* Parameter "Channel" is used with masks because containing */
3281 /* other bits reserved for other purpose. */
3282 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3283
3284 MODIFY_REG(*preg,
3285 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3286 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3287 }
3288
3289 /**
3290 * @brief Get sampling time of the selected ADC channel
3291 * Unit: ADC clock cycles.
3292 * @note On this device, sampling time is on channel scope: independently
3293 * of channel mapped on ADC group regular or injected.
3294 * @note Conversion time is the addition of sampling time and processing time.
3295 * Refer to reference manual for ADC processing time of
3296 * this STM32 series.
3297 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
3298 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
3299 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
3300 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
3301 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
3302 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
3303 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
3304 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
3305 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
3306 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
3307 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
3308 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
3309 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
3310 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
3311 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
3312 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
3313 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
3314 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
3315 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
3316 * @param ADCx ADC instance
3317 * @param Channel This parameter can be one of the following values:
3318 * @arg @ref LL_ADC_CHANNEL_0
3319 * @arg @ref LL_ADC_CHANNEL_1
3320 * @arg @ref LL_ADC_CHANNEL_2
3321 * @arg @ref LL_ADC_CHANNEL_3
3322 * @arg @ref LL_ADC_CHANNEL_4
3323 * @arg @ref LL_ADC_CHANNEL_5
3324 * @arg @ref LL_ADC_CHANNEL_6
3325 * @arg @ref LL_ADC_CHANNEL_7
3326 * @arg @ref LL_ADC_CHANNEL_8
3327 * @arg @ref LL_ADC_CHANNEL_9
3328 * @arg @ref LL_ADC_CHANNEL_10
3329 * @arg @ref LL_ADC_CHANNEL_11
3330 * @arg @ref LL_ADC_CHANNEL_12
3331 * @arg @ref LL_ADC_CHANNEL_13
3332 * @arg @ref LL_ADC_CHANNEL_14
3333 * @arg @ref LL_ADC_CHANNEL_15
3334 * @arg @ref LL_ADC_CHANNEL_16
3335 * @arg @ref LL_ADC_CHANNEL_17
3336 * @arg @ref LL_ADC_CHANNEL_18
3337 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3338 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3339 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3340 *
3341 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3342 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3343 * @retval Returned value can be one of the following values:
3344 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3345 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3346 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3347 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3348 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3349 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3350 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3351 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3352 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)3353 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3354 {
3355 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3356
3357 return (uint32_t)(READ_BIT(*preg,
3358 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3359 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3360 );
3361 }
3362
3363 /**
3364 * @}
3365 */
3366
3367 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3368 * @{
3369 */
3370
3371 /**
3372 * @brief Set ADC analog watchdog monitored channels:
3373 * a single channel or all channels,
3374 * on ADC groups regular and-or injected.
3375 * @note Once monitored channels are selected, analog watchdog
3376 * is enabled.
3377 * @note In case of need to define a single channel to monitor
3378 * with analog watchdog from sequencer channel definition,
3379 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3380 * @note On this STM32 series, there is only 1 kind of analog watchdog
3381 * instance:
3382 * - AWD standard (instance AWD1):
3383 * - channels monitored: can monitor 1 channel or all channels.
3384 * - groups monitored: ADC groups regular and-or injected.
3385 * - resolution: resolution is not limited (corresponds to
3386 * ADC resolution configured).
3387 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3388 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3389 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
3390 * @param ADCx ADC instance
3391 * @param AWDChannelGroup This parameter can be one of the following values:
3392 * @arg @ref LL_ADC_AWD_DISABLE
3393 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3394 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3395 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3396 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3397 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3398 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3399 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3400 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3401 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3402 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3403 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3404 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3405 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3406 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3407 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3408 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3409 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3410 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3411 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3412 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3413 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3414 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3415 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3416 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3417 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3418 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3419 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3420 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3421 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3422 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3423 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3424 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3425 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3426 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3427 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3428 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3429 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3430 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3431 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3432 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3433 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3434 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3435 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3436 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3437 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3438 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3439 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3440 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3441 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3442 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3443 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3444 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3445 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3446 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3447 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3448 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3449 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3450 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3451 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3452 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3453 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3454 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3455 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3456 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
3457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
3458 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
3459 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
3460 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
3461 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
3462 *
3463 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3464 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3465 * @retval None
3466 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)3467 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3468 {
3469 MODIFY_REG(ADCx->CR1,
3470 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3471 AWDChannelGroup);
3472 }
3473
3474 /**
3475 * @brief Get ADC analog watchdog monitored channel.
3476 * @note Usage of the returned channel number:
3477 * - To reinject this channel into another function LL_ADC_xxx:
3478 * the returned channel number is only partly formatted on definition
3479 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3480 * with parts of literals LL_ADC_CHANNEL_x or using
3481 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3482 * Then the selected literal LL_ADC_CHANNEL_x can be used
3483 * as parameter for another function.
3484 * - To get the channel number in decimal format:
3485 * process the returned value with the helper macro
3486 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3487 * Applicable only when the analog watchdog is set to monitor
3488 * one channel.
3489 * @note On this STM32 series, there is only 1 kind of analog watchdog
3490 * instance:
3491 * - AWD standard (instance AWD1):
3492 * - channels monitored: can monitor 1 channel or all channels.
3493 * - groups monitored: ADC groups regular and-or injected.
3494 * - resolution: resolution is not limited (corresponds to
3495 * ADC resolution configured).
3496 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3497 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3498 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3499 * @param ADCx ADC instance
3500 * @retval Returned value can be one of the following values:
3501 * @arg @ref LL_ADC_AWD_DISABLE
3502 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3503 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3504 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3505 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3506 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3507 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3508 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3509 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3510 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3511 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3512 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3513 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3514 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3515 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3516 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3517 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3518 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3519 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3520 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3521 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3522 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3523 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3524 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3525 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3526 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3527 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3528 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3529 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3530 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3531 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3532 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3533 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3534 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3535 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3536 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3537 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3538 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3539 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3540 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3541 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3542 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3543 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3544 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3545 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3546 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3547 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3548 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3549 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3550 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3551 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3552 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3553 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3554 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3555 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3556 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3557 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3558 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3559 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3560 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3561 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3562 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx)3563 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3564 {
3565 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3566 }
3567
3568 /**
3569 * @brief Set ADC analog watchdog threshold value of threshold
3570 * high or low.
3571 * @note In case of ADC resolution different of 12 bits,
3572 * analog watchdog thresholds data require a specific shift.
3573 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3574 * @note On this STM32 series, there is only 1 kind of analog watchdog
3575 * instance:
3576 * - AWD standard (instance AWD1):
3577 * - channels monitored: can monitor 1 channel or all channels.
3578 * - groups monitored: ADC groups regular and-or injected.
3579 * - resolution: resolution is not limited (corresponds to
3580 * ADC resolution configured).
3581 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3582 * LTR LT LL_ADC_SetAnalogWDThresholds
3583 * @param ADCx ADC instance
3584 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3585 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3586 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3587 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3588 * @retval None
3589 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3590 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3591 {
3592 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3593
3594 MODIFY_REG(*preg,
3595 ADC_HTR_HT,
3596 AWDThresholdValue);
3597 }
3598
3599 /**
3600 * @brief Get ADC analog watchdog threshold value of threshold high or
3601 * threshold low.
3602 * @note In case of ADC resolution different of 12 bits,
3603 * analog watchdog thresholds data require a specific shift.
3604 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3605 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3606 * LTR LT LL_ADC_GetAnalogWDThresholds
3607 * @param ADCx ADC instance
3608 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3609 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3610 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3611 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3612 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)3613 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3614 {
3615 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3616
3617 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3618 }
3619
3620 /**
3621 * @}
3622 */
3623
3624 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3625 * @{
3626 */
3627
3628 #if defined(ADC_MULTIMODE_SUPPORT)
3629 /**
3630 * @brief Set ADC multimode configuration to operate in independent mode
3631 * or multimode (for devices with several ADC instances).
3632 * @note If multimode configuration: the selected ADC instance is
3633 * either master or slave depending on hardware.
3634 * Refer to reference manual.
3635 * @rmtoll CCR MULTI LL_ADC_SetMultimode
3636 * @param ADCxy_COMMON ADC common instance
3637 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3638 * @param Multimode This parameter can be one of the following values:
3639 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3640 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3641 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3642 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3643 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3644 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3645 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3646 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3647 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3648 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3649 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3650 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3651 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3652 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3653 * @retval None
3654 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)3655 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3656 {
3657 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3658 }
3659
3660 /**
3661 * @brief Get ADC multimode configuration to operate in independent mode
3662 * or multimode (for devices with several ADC instances).
3663 * @note If multimode configuration: the selected ADC instance is
3664 * either master or slave depending on hardware.
3665 * Refer to reference manual.
3666 * @rmtoll CCR MULTI LL_ADC_GetMultimode
3667 * @param ADCxy_COMMON ADC common instance
3668 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3669 * @retval Returned value can be one of the following values:
3670 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3671 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3672 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3673 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3674 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3675 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3676 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3677 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3678 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3679 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3680 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3681 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3682 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3683 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3684 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)3685 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
3686 {
3687 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3688 }
3689
3690 /**
3691 * @brief Set ADC multimode conversion data transfer: no transfer
3692 * or transfer by DMA.
3693 * @note If ADC multimode transfer by DMA is not selected:
3694 * each ADC uses its own DMA channel, with its individual
3695 * DMA transfer settings.
3696 * If ADC multimode transfer by DMA is selected:
3697 * One DMA channel is used for both ADC (DMA of ADC master)
3698 * Specifies the DMA requests mode:
3699 * - Limited mode (One shot mode): DMA transfer requests are stopped
3700 * when number of DMA data transfers (number of
3701 * ADC conversions) is reached.
3702 * This ADC mode is intended to be used with DMA mode non-circular.
3703 * - Unlimited mode: DMA transfer requests are unlimited,
3704 * whatever number of DMA data transfers (number of
3705 * ADC conversions).
3706 * This ADC mode is intended to be used with DMA mode circular.
3707 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3708 * mode non-circular:
3709 * when DMA transfers size will be reached, DMA will stop transfers of
3710 * ADC conversions data ADC will raise an overrun error
3711 * (overrun flag and interruption if enabled).
3712 * @note How to retrieve multimode conversion data:
3713 * Whatever multimode transfer by DMA setting: using function
3714 * @ref LL_ADC_REG_ReadMultiConversionData32().
3715 * If ADC multimode transfer by DMA is selected: conversion data
3716 * is a raw data with ADC master and slave concatenated.
3717 * A macro is available to get the conversion data of
3718 * ADC master or ADC slave: see helper macro
3719 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3720 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
3721 * CCR DDS LL_ADC_SetMultiDMATransfer
3722 * @param ADCxy_COMMON ADC common instance
3723 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3724 * @param MultiDMATransfer This parameter can be one of the following values:
3725 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3726 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3727 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3728 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3729 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3730 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3731 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3732 * @retval None
3733 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)3734 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3735 {
3736 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3737 }
3738
3739 /**
3740 * @brief Get ADC multimode conversion data transfer: no transfer
3741 * or transfer by DMA.
3742 * @note If ADC multimode transfer by DMA is not selected:
3743 * each ADC uses its own DMA channel, with its individual
3744 * DMA transfer settings.
3745 * If ADC multimode transfer by DMA is selected:
3746 * One DMA channel is used for both ADC (DMA of ADC master)
3747 * Specifies the DMA requests mode:
3748 * - Limited mode (One shot mode): DMA transfer requests are stopped
3749 * when number of DMA data transfers (number of
3750 * ADC conversions) is reached.
3751 * This ADC mode is intended to be used with DMA mode non-circular.
3752 * - Unlimited mode: DMA transfer requests are unlimited,
3753 * whatever number of DMA data transfers (number of
3754 * ADC conversions).
3755 * This ADC mode is intended to be used with DMA mode circular.
3756 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3757 * mode non-circular:
3758 * when DMA transfers size will be reached, DMA will stop transfers of
3759 * ADC conversions data ADC will raise an overrun error
3760 * (overrun flag and interruption if enabled).
3761 * @note How to retrieve multimode conversion data:
3762 * Whatever multimode transfer by DMA setting: using function
3763 * @ref LL_ADC_REG_ReadMultiConversionData32().
3764 * If ADC multimode transfer by DMA is selected: conversion data
3765 * is a raw data with ADC master and slave concatenated.
3766 * A macro is available to get the conversion data of
3767 * ADC master or ADC slave: see helper macro
3768 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3769 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
3770 * CCR DDS LL_ADC_GetMultiDMATransfer
3771 * @param ADCxy_COMMON ADC common instance
3772 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3773 * @retval Returned value can be one of the following values:
3774 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3775 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3776 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3777 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3778 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3779 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3780 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3781 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)3782 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
3783 {
3784 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3785 }
3786
3787 /**
3788 * @brief Set ADC multimode delay between 2 sampling phases.
3789 * @note The sampling delay range depends on ADC resolution:
3790 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
3791 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
3792 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
3793 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
3794 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
3795 * @param ADCxy_COMMON ADC common instance
3796 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3797 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
3798 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3799 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3800 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3801 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3802 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3803 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3804 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3805 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3806 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3807 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3808 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3809 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3810 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3811 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3812 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3813 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3814 * @retval None
3815 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)3816 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3817 {
3818 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3819 }
3820
3821 /**
3822 * @brief Get ADC multimode delay between 2 sampling phases.
3823 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
3824 * @param ADCxy_COMMON ADC common instance
3825 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3826 * @retval Returned value can be one of the following values:
3827 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3828 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3829 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3830 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3831 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3832 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3833 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3834 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3835 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3836 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3837 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3838 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3839 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3840 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3841 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3842 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3843 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)3844 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
3845 {
3846 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3847 }
3848 #endif /* ADC_MULTIMODE_SUPPORT */
3849
3850 /**
3851 * @}
3852 */
3853 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3854 * @{
3855 */
3856
3857 /**
3858 * @brief Enable the selected ADC instance.
3859 * @note On this STM32 series, after ADC enable, a delay for
3860 * ADC internal analog stabilization is required before performing a
3861 * ADC conversion start.
3862 * Refer to device datasheet, parameter tSTAB.
3863 * @rmtoll CR2 ADON LL_ADC_Enable
3864 * @param ADCx ADC instance
3865 * @retval None
3866 */
LL_ADC_Enable(ADC_TypeDef * ADCx)3867 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3868 {
3869 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3870 }
3871
3872 /**
3873 * @brief Disable the selected ADC instance.
3874 * @rmtoll CR2 ADON LL_ADC_Disable
3875 * @param ADCx ADC instance
3876 * @retval None
3877 */
LL_ADC_Disable(ADC_TypeDef * ADCx)3878 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3879 {
3880 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3881 }
3882
3883 /**
3884 * @brief Get the selected ADC instance enable state.
3885 * @rmtoll CR2 ADON LL_ADC_IsEnabled
3886 * @param ADCx ADC instance
3887 * @retval 0: ADC is disabled, 1: ADC is enabled.
3888 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)3889 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3890 {
3891 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3892 }
3893
3894 /**
3895 * @}
3896 */
3897
3898 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3899 * @{
3900 */
3901
3902 /**
3903 * @brief Start ADC group regular conversion.
3904 * @note On this STM32 series, this function is relevant only for
3905 * internal trigger (SW start), not for external trigger:
3906 * - If ADC trigger has been set to software start, ADC conversion
3907 * starts immediately.
3908 * - If ADC trigger has been set to external trigger, ADC conversion
3909 * start must be performed using function
3910 * @ref LL_ADC_REG_StartConversionExtTrig().
3911 * (if external trigger edge would have been set during ADC other
3912 * settings, ADC conversion would start at trigger event
3913 * as soon as ADC is enabled).
3914 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3915 * @param ADCx ADC instance
3916 * @retval None
3917 */
LL_ADC_REG_StartConversionSWStart(ADC_TypeDef * ADCx)3918 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3919 {
3920 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3921 }
3922
3923 /**
3924 * @brief Start ADC group regular conversion from external trigger.
3925 * @note ADC conversion will start at next trigger event (on the selected
3926 * trigger edge) following the ADC start conversion command.
3927 * @note On this STM32 series, this function is relevant for
3928 * ADC conversion start from external trigger.
3929 * If internal trigger (SW start) is needed, perform ADC conversion
3930 * start using function @ref LL_ADC_REG_StartConversionSWStart().
3931 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3932 * @param ExternalTriggerEdge This parameter can be one of the following values:
3933 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3934 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3935 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3936 * @param ADCx ADC instance
3937 * @retval None
3938 */
LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3939 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3940 {
3941 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3942 }
3943
3944 /**
3945 * @brief Stop ADC group regular conversion from external trigger.
3946 * @note No more ADC conversion will start at next trigger event
3947 * following the ADC stop conversion command.
3948 * If a conversion is on-going, it will be completed.
3949 * @note On this STM32 series, there is no specific command
3950 * to stop a conversion on-going or to stop ADC converting
3951 * in continuous mode. These actions can be performed
3952 * using function @ref LL_ADC_Disable().
3953 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
3954 * @param ADCx ADC instance
3955 * @retval None
3956 */
LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef * ADCx)3957 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3958 {
3959 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3960 }
3961
3962 /**
3963 * @brief Get ADC group regular conversion data, range fit for
3964 * all ADC configurations: all ADC resolutions and
3965 * all oversampling increased data width (for devices
3966 * with feature oversampling).
3967 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3968 * @param ADCx ADC instance
3969 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3970 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)3971 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3972 {
3973 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3974 }
3975
3976 /**
3977 * @brief Get ADC group regular conversion data, range fit for
3978 * ADC resolution 12 bits.
3979 * @note For devices with feature oversampling: Oversampling
3980 * can increase data width, function for extended range
3981 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3982 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3983 * @param ADCx ADC instance
3984 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3985 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)3986 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3987 {
3988 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3989 }
3990
3991 /**
3992 * @brief Get ADC group regular conversion data, range fit for
3993 * ADC resolution 10 bits.
3994 * @note For devices with feature oversampling: Oversampling
3995 * can increase data width, function for extended range
3996 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3997 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
3998 * @param ADCx ADC instance
3999 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4000 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)4001 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
4002 {
4003 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4004 }
4005
4006 /**
4007 * @brief Get ADC group regular conversion data, range fit for
4008 * ADC resolution 8 bits.
4009 * @note For devices with feature oversampling: Oversampling
4010 * can increase data width, function for extended range
4011 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4012 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
4013 * @param ADCx ADC instance
4014 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4015 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)4016 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
4017 {
4018 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4019 }
4020
4021 /**
4022 * @brief Get ADC group regular conversion data, range fit for
4023 * ADC resolution 6 bits.
4024 * @note For devices with feature oversampling: Oversampling
4025 * can increase data width, function for extended range
4026 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4027 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
4028 * @param ADCx ADC instance
4029 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4030 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)4031 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
4032 {
4033 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4034 }
4035
4036 #if defined(ADC_MULTIMODE_SUPPORT)
4037 /**
4038 * @brief Get ADC multimode conversion data of ADC master, ADC slave
4039 * or raw data with ADC master and slave concatenated.
4040 * @note If raw data with ADC master and slave concatenated is retrieved,
4041 * a macro is available to get the conversion data of
4042 * ADC master or ADC slave: see helper macro
4043 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
4044 * (however this macro is mainly intended for multimode
4045 * transfer by DMA, because this function can do the same
4046 * by getting multimode conversion data of ADC master or ADC slave
4047 * separately).
4048 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
4049 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
4050 * @param ADCxy_COMMON ADC common instance
4051 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4052 * @param ConversionData This parameter can be one of the following values:
4053 * @arg @ref LL_ADC_MULTI_MASTER
4054 * @arg @ref LL_ADC_MULTI_SLAVE
4055 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
4056 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4057 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)4058 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
4059 {
4060 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
4061 ADC_DR_ADC2DATA)
4062 >> POSITION_VAL(ConversionData)
4063 );
4064 }
4065 #endif /* ADC_MULTIMODE_SUPPORT */
4066
4067 /**
4068 * @}
4069 */
4070
4071 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
4072 * @{
4073 */
4074
4075 /**
4076 * @brief Start ADC group injected conversion.
4077 * @note On this STM32 series, this function is relevant only for
4078 * internal trigger (SW start), not for external trigger:
4079 * - If ADC trigger has been set to software start, ADC conversion
4080 * starts immediately.
4081 * - If ADC trigger has been set to external trigger, ADC conversion
4082 * start must be performed using function
4083 * @ref LL_ADC_INJ_StartConversionExtTrig().
4084 * (if external trigger edge would have been set during ADC other
4085 * settings, ADC conversion would start at trigger event
4086 * as soon as ADC is enabled).
4087 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
4088 * @param ADCx ADC instance
4089 * @retval None
4090 */
LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef * ADCx)4091 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4092 {
4093 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4094 }
4095
4096 /**
4097 * @brief Start ADC group injected conversion from external trigger.
4098 * @note ADC conversion will start at next trigger event (on the selected
4099 * trigger edge) following the ADC start conversion command.
4100 * @note On this STM32 series, this function is relevant for
4101 * ADC conversion start from external trigger.
4102 * If internal trigger (SW start) is needed, perform ADC conversion
4103 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
4104 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
4105 * @param ExternalTriggerEdge This parameter can be one of the following values:
4106 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4107 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4108 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4109 * @param ADCx ADC instance
4110 * @retval None
4111 */
LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4112 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4113 {
4114 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4115 }
4116
4117 /**
4118 * @brief Stop ADC group injected conversion from external trigger.
4119 * @note No more ADC conversion will start at next trigger event
4120 * following the ADC stop conversion command.
4121 * If a conversion is on-going, it will be completed.
4122 * @note On this STM32 series, there is no specific command
4123 * to stop a conversion on-going or to stop ADC converting
4124 * in continuous mode. These actions can be performed
4125 * using function @ref LL_ADC_Disable().
4126 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
4127 * @param ADCx ADC instance
4128 * @retval None
4129 */
LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef * ADCx)4130 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4131 {
4132 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4133 }
4134
4135 /**
4136 * @brief Get ADC group regular conversion data, range fit for
4137 * all ADC configurations: all ADC resolutions and
4138 * all oversampling increased data width (for devices
4139 * with feature oversampling).
4140 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
4141 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
4142 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
4143 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
4144 * @param ADCx ADC instance
4145 * @param Rank This parameter can be one of the following values:
4146 * @arg @ref LL_ADC_INJ_RANK_1
4147 * @arg @ref LL_ADC_INJ_RANK_2
4148 * @arg @ref LL_ADC_INJ_RANK_3
4149 * @arg @ref LL_ADC_INJ_RANK_4
4150 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4151 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)4152 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
4153 {
4154 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4155
4156 return (uint32_t)(READ_BIT(*preg,
4157 ADC_JDR1_JDATA)
4158 );
4159 }
4160
4161 /**
4162 * @brief Get ADC group injected conversion data, range fit for
4163 * ADC resolution 12 bits.
4164 * @note For devices with feature oversampling: Oversampling
4165 * can increase data width, function for extended range
4166 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4167 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4168 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4169 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4170 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4171 * @param ADCx ADC instance
4172 * @param Rank This parameter can be one of the following values:
4173 * @arg @ref LL_ADC_INJ_RANK_1
4174 * @arg @ref LL_ADC_INJ_RANK_2
4175 * @arg @ref LL_ADC_INJ_RANK_3
4176 * @arg @ref LL_ADC_INJ_RANK_4
4177 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4178 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)4179 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
4180 {
4181 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4182
4183 return (uint16_t)(READ_BIT(*preg,
4184 ADC_JDR1_JDATA)
4185 );
4186 }
4187
4188 /**
4189 * @brief Get ADC group injected conversion data, range fit for
4190 * ADC resolution 10 bits.
4191 * @note For devices with feature oversampling: Oversampling
4192 * can increase data width, function for extended range
4193 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4194 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4195 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4196 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4197 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4198 * @param ADCx ADC instance
4199 * @param Rank This parameter can be one of the following values:
4200 * @arg @ref LL_ADC_INJ_RANK_1
4201 * @arg @ref LL_ADC_INJ_RANK_2
4202 * @arg @ref LL_ADC_INJ_RANK_3
4203 * @arg @ref LL_ADC_INJ_RANK_4
4204 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4205 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)4206 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
4207 {
4208 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4209
4210 return (uint16_t)(READ_BIT(*preg,
4211 ADC_JDR1_JDATA)
4212 );
4213 }
4214
4215 /**
4216 * @brief Get ADC group injected conversion data, range fit for
4217 * ADC resolution 8 bits.
4218 * @note For devices with feature oversampling: Oversampling
4219 * can increase data width, function for extended range
4220 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4221 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4222 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4223 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4224 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4225 * @param ADCx ADC instance
4226 * @param Rank This parameter can be one of the following values:
4227 * @arg @ref LL_ADC_INJ_RANK_1
4228 * @arg @ref LL_ADC_INJ_RANK_2
4229 * @arg @ref LL_ADC_INJ_RANK_3
4230 * @arg @ref LL_ADC_INJ_RANK_4
4231 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4232 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)4233 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
4234 {
4235 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4236
4237 return (uint8_t)(READ_BIT(*preg,
4238 ADC_JDR1_JDATA)
4239 );
4240 }
4241
4242 /**
4243 * @brief Get ADC group injected conversion data, range fit for
4244 * ADC resolution 6 bits.
4245 * @note For devices with feature oversampling: Oversampling
4246 * can increase data width, function for extended range
4247 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4248 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4249 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4250 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4251 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4252 * @param ADCx ADC instance
4253 * @param Rank This parameter can be one of the following values:
4254 * @arg @ref LL_ADC_INJ_RANK_1
4255 * @arg @ref LL_ADC_INJ_RANK_2
4256 * @arg @ref LL_ADC_INJ_RANK_3
4257 * @arg @ref LL_ADC_INJ_RANK_4
4258 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4259 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)4260 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
4261 {
4262 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4263
4264 return (uint8_t)(READ_BIT(*preg,
4265 ADC_JDR1_JDATA)
4266 );
4267 }
4268
4269 /**
4270 * @}
4271 */
4272
4273 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4274 * @{
4275 */
4276
4277 /**
4278 * @brief Get flag ADC group regular end of unitary conversion
4279 * or end of sequence conversions, depending on
4280 * ADC configuration.
4281 * @note To configure flag of end of conversion,
4282 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4283 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4284 * @param ADCx ADC instance
4285 * @retval State of bit (1 or 0).
4286 */
LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef * ADCx)4287 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
4288 {
4289 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4290 }
4291
4292 /**
4293 * @brief Get flag ADC group regular overrun.
4294 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4295 * @param ADCx ADC instance
4296 * @retval State of bit (1 or 0).
4297 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)4298 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4299 {
4300 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4301 }
4302
4303
4304 /**
4305 * @brief Get flag ADC group injected end of sequence conversions.
4306 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4307 * @param ADCx ADC instance
4308 * @retval State of bit (1 or 0).
4309 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)4310 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
4311 {
4312 /* Note: on this STM32 series, there is no flag ADC group injected */
4313 /* end of unitary conversion. */
4314 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4315 /* in other STM32 families). */
4316 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4317 }
4318
4319 /**
4320 * @brief Get flag ADC analog watchdog 1 flag
4321 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4322 * @param ADCx ADC instance
4323 * @retval State of bit (1 or 0).
4324 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)4325 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4326 {
4327 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4328 }
4329
4330 /**
4331 * @brief Clear flag ADC group regular end of unitary conversion
4332 * or end of sequence conversions, depending on
4333 * ADC configuration.
4334 * @note To configure flag of end of conversion,
4335 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4336 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4337 * @param ADCx ADC instance
4338 * @retval None
4339 */
LL_ADC_ClearFlag_EOCS(ADC_TypeDef * ADCx)4340 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4341 {
4342 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4343 }
4344
4345 /**
4346 * @brief Clear flag ADC group regular overrun.
4347 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4348 * @param ADCx ADC instance
4349 * @retval None
4350 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4351 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4352 {
4353 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4354 }
4355
4356
4357 /**
4358 * @brief Clear flag ADC group injected end of sequence conversions.
4359 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4360 * @param ADCx ADC instance
4361 * @retval None
4362 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)4363 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4364 {
4365 /* Note: on this STM32 series, there is no flag ADC group injected */
4366 /* end of unitary conversion. */
4367 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4368 /* in other STM32 families). */
4369 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4370 }
4371
4372 /**
4373 * @brief Clear flag ADC analog watchdog 1.
4374 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4375 * @param ADCx ADC instance
4376 * @retval None
4377 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4378 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4379 {
4380 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4381 }
4382
4383 #if defined(ADC_MULTIMODE_SUPPORT)
4384 /**
4385 * @brief Get flag multimode ADC group regular end of unitary conversion
4386 * or end of sequence conversions, depending on
4387 * ADC configuration, of the ADC master.
4388 * @note To configure flag of end of conversion,
4389 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4390 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
4391 * @param ADCxy_COMMON ADC common instance
4392 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4393 * @retval State of bit (1 or 0).
4394 */
LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4395 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4396 {
4397 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_MST) == (LL_ADC_FLAG_EOCS_MST));
4398 }
4399
4400 /**
4401 * @brief Get flag multimode ADC group regular end of unitary conversion
4402 * or end of sequence conversions, depending on
4403 * ADC configuration, of the ADC slave 1.
4404 * @note To configure flag of end of conversion,
4405 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4406 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
4407 * @param ADCxy_COMMON ADC common instance
4408 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4409 * @retval State of bit (1 or 0).
4410 */
LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4411 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4412 {
4413 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4414 }
4415
4416 /**
4417 * @brief Get flag multimode ADC group regular end of unitary conversion
4418 * or end of sequence conversions, depending on
4419 * ADC configuration, of the ADC slave 2.
4420 * @note To configure flag of end of conversion,
4421 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4422 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
4423 * @param ADCxy_COMMON ADC common instance
4424 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4425 * @retval State of bit (1 or 0).
4426 */
LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4427 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4428 {
4429 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4430 }
4431 /**
4432 * @brief Get flag multimode ADC group regular overrun of the ADC master.
4433 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
4434 * @param ADCxy_COMMON ADC common instance
4435 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4436 * @retval State of bit (1 or 0).
4437 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4438 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4439 {
4440 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4441 }
4442
4443 /**
4444 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
4445 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
4446 * @param ADCxy_COMMON ADC common instance
4447 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4448 * @retval State of bit (1 or 0).
4449 */
LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4450 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4451 {
4452 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4453 }
4454
4455 /**
4456 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
4457 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
4458 * @param ADCxy_COMMON ADC common instance
4459 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4460 * @retval State of bit (1 or 0).
4461 */
LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4462 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4463 {
4464 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4465 }
4466
4467
4468 /**
4469 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
4470 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_JEOS
4471 * @param ADCxy_COMMON ADC common instance
4472 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4473 * @retval State of bit (1 or 0).
4474 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4475 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4476 {
4477 /* Note: on this STM32 series, there is no flag ADC group injected */
4478 /* end of unitary conversion. */
4479 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4480 /* in other STM32 families). */
4481 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4482 }
4483
4484 /**
4485 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
4486 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
4487 * @param ADCxy_COMMON ADC common instance
4488 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4489 * @retval State of bit (1 or 0).
4490 */
LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4491 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4492 {
4493 /* Note: on this STM32 series, there is no flag ADC group injected */
4494 /* end of unitary conversion. */
4495 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4496 /* in other STM32 families). */
4497 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4498 }
4499
4500 /**
4501 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
4502 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
4503 * @param ADCxy_COMMON ADC common instance
4504 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4505 * @retval State of bit (1 or 0).
4506 */
LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4507 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4508 {
4509 /* Note: on this STM32 series, there is no flag ADC group injected */
4510 /* end of unitary conversion. */
4511 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4512 /* in other STM32 families). */
4513 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4514 }
4515
4516 /**
4517 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
4518 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
4519 * @param ADCxy_COMMON ADC common instance
4520 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4521 * @retval State of bit (1 or 0).
4522 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4523 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4524 {
4525 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4526 }
4527
4528 /**
4529 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
4530 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
4531 * @param ADCxy_COMMON ADC common instance
4532 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4533 * @retval State of bit (1 or 0).
4534 */
LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4535 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4536 {
4537 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4538 }
4539
4540 /**
4541 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
4542 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
4543 * @param ADCxy_COMMON ADC common instance
4544 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4545 * @retval State of bit (1 or 0).
4546 */
LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4547 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4548 {
4549 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4550 }
4551
4552 #endif /* ADC_MULTIMODE_SUPPORT */
4553
4554 /**
4555 * @}
4556 */
4557
4558 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4559 * @{
4560 */
4561
4562 /**
4563 * @brief Enable interruption ADC group regular end of unitary conversion
4564 * or end of sequence conversions, depending on
4565 * ADC configuration.
4566 * @note To configure flag of end of conversion,
4567 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4568 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4569 * @param ADCx ADC instance
4570 * @retval None
4571 */
LL_ADC_EnableIT_EOCS(ADC_TypeDef * ADCx)4572 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4573 {
4574 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4575 }
4576
4577 /**
4578 * @brief Enable ADC group regular interruption overrun.
4579 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4580 * @param ADCx ADC instance
4581 * @retval None
4582 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4583 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4584 {
4585 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4586 }
4587
4588
4589 /**
4590 * @brief Enable interruption ADC group injected end of sequence conversions.
4591 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4592 * @param ADCx ADC instance
4593 * @retval None
4594 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)4595 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4596 {
4597 /* Note: on this STM32 series, there is no flag ADC group injected */
4598 /* end of unitary conversion. */
4599 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4600 /* in other STM32 families). */
4601 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4602 }
4603
4604 /**
4605 * @brief Enable interruption ADC analog watchdog 1.
4606 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4607 * @param ADCx ADC instance
4608 * @retval None
4609 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4610 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4611 {
4612 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4613 }
4614
4615 /**
4616 * @brief Disable interruption ADC group regular end of unitary conversion
4617 * or end of sequence conversions, depending on
4618 * ADC configuration.
4619 * @note To configure flag of end of conversion,
4620 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4621 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
4622 * @param ADCx ADC instance
4623 * @retval None
4624 */
LL_ADC_DisableIT_EOCS(ADC_TypeDef * ADCx)4625 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4626 {
4627 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4628 }
4629
4630 /**
4631 * @brief Disable interruption ADC group regular overrun.
4632 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
4633 * @param ADCx ADC instance
4634 * @retval None
4635 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4636 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4637 {
4638 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4639 }
4640
4641
4642 /**
4643 * @brief Disable interruption ADC group injected end of sequence conversions.
4644 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4645 * @param ADCx ADC instance
4646 * @retval None
4647 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)4648 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4649 {
4650 /* Note: on this STM32 series, there is no flag ADC group injected */
4651 /* end of unitary conversion. */
4652 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4653 /* in other STM32 families). */
4654 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4655 }
4656
4657 /**
4658 * @brief Disable interruption ADC analog watchdog 1.
4659 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4660 * @param ADCx ADC instance
4661 * @retval None
4662 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4663 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4664 {
4665 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4666 }
4667
4668 /**
4669 * @brief Get state of interruption ADC group regular end of unitary conversion
4670 * or end of sequence conversions, depending on
4671 * ADC configuration.
4672 * @note To configure flag of end of conversion,
4673 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4674 * (0: interrupt disabled, 1: interrupt enabled)
4675 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
4676 * @param ADCx ADC instance
4677 * @retval State of bit (1 or 0).
4678 */
LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef * ADCx)4679 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
4680 {
4681 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4682 }
4683
4684 /**
4685 * @brief Get state of interruption ADC group regular overrun
4686 * (0: interrupt disabled, 1: interrupt enabled).
4687 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
4688 * @param ADCx ADC instance
4689 * @retval State of bit (1 or 0).
4690 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)4691 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
4692 {
4693 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4694 }
4695
4696
4697 /**
4698 * @brief Get state of interruption ADC group injected end of sequence conversions
4699 * (0: interrupt disabled, 1: interrupt enabled).
4700 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4701 * @param ADCx ADC instance
4702 * @retval State of bit (1 or 0).
4703 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)4704 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
4705 {
4706 /* Note: on this STM32 series, there is no flag ADC group injected */
4707 /* end of unitary conversion. */
4708 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4709 /* in other STM32 families). */
4710 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4711 }
4712
4713 /**
4714 * @brief Get state of interruption ADC analog watchdog 1
4715 * (0: interrupt disabled, 1: interrupt enabled).
4716 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4717 * @param ADCx ADC instance
4718 * @retval State of bit (1 or 0).
4719 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)4720 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
4721 {
4722 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4723 }
4724
4725 /**
4726 * @}
4727 */
4728
4729 #if defined(USE_FULL_LL_DRIVER)
4730 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4731 * @{
4732 */
4733
4734 /* Initialization of some features of ADC common parameters and multimode */
4735 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4736 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4737 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4738
4739 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
4740 /* (availability of ADC group injected depends on STM32 families) */
4741 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4742
4743 /* Initialization of some features of ADC instance */
4744 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4745 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4746
4747 /* Initialization of some features of ADC instance and ADC group regular */
4748 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4749 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4750
4751 /* Initialization of some features of ADC instance and ADC group injected */
4752 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4753 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4754
4755 /**
4756 * @}
4757 */
4758 #endif /* USE_FULL_LL_DRIVER */
4759
4760 /**
4761 * @}
4762 */
4763
4764 /**
4765 * @}
4766 */
4767
4768 #endif /* ADC1 || ADC2 || ADC3 */
4769
4770 /**
4771 * @}
4772 */
4773
4774 #ifdef __cplusplus
4775 }
4776 #endif
4777
4778 #endif /* __STM32F4xx_LL_ADC_H */
4779
4780
