1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_nand.h 4 * @author MCD Application Team 5 * @brief Header file of NAND HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_NAND_H 21 #define STM32F4xx_HAL_NAND_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #if defined(FSMC_Bank2_3) 31 #include "stm32f4xx_ll_fsmc.h" 32 #else 33 #include "stm32f4xx_ll_fmc.h" 34 #endif /* FSMC_Bank2_3 */ 35 36 /** @addtogroup STM32F4xx_HAL_Driver 37 * @{ 38 */ 39 40 /** @addtogroup NAND 41 * @{ 42 */ 43 44 /* Exported typedef ----------------------------------------------------------*/ 45 /* Exported types ------------------------------------------------------------*/ 46 /** @defgroup NAND_Exported_Types NAND Exported Types 47 * @{ 48 */ 49 50 /** 51 * @brief HAL NAND State structures definition 52 */ 53 typedef enum 54 { 55 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 56 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 57 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 58 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 59 } HAL_NAND_StateTypeDef; 60 61 /** 62 * @brief NAND Memory electronic signature Structure definition 63 */ 64 typedef struct 65 { 66 /*<! NAND memory electronic signature maker and device IDs */ 67 68 uint8_t Maker_Id; 69 70 uint8_t Device_Id; 71 72 uint8_t Third_Id; 73 74 uint8_t Fourth_Id; 75 } NAND_IDTypeDef; 76 77 /** 78 * @brief NAND Memory address Structure definition 79 */ 80 typedef struct 81 { 82 uint16_t Page; /*!< NAND memory Page address */ 83 84 uint16_t Plane; /*!< NAND memory Zone address */ 85 86 uint16_t Block; /*!< NAND memory Block address */ 87 88 } NAND_AddressTypeDef; 89 90 /** 91 * @brief NAND Memory info Structure definition 92 */ 93 typedef struct 94 { 95 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 96 for 8 bits addressing or words for 16 bits addressing */ 97 98 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 99 for 8 bits addressing or words for 16 bits addressing */ 100 101 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 102 103 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 104 105 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 106 107 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 108 109 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 110 parameter is mandatory for some NAND parts after the read 111 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 112 This parameter could be ENABLE or DISABLE 113 Please check the Read Mode sequence in the NAND device datasheet */ 114 } NAND_DeviceConfigTypeDef; 115 116 /** 117 * @brief NAND handle Structure definition 118 */ 119 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 120 typedef struct __NAND_HandleTypeDef 121 #else 122 typedef struct 123 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 124 { 125 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 126 127 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 128 129 HAL_LockTypeDef Lock; /*!< NAND locking object */ 130 131 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 132 133 NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */ 134 135 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 136 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ 137 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ 138 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ 139 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 140 } NAND_HandleTypeDef; 141 142 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 143 /** 144 * @brief HAL NAND Callback ID enumeration definition 145 */ 146 typedef enum 147 { 148 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ 149 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ 150 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ 151 } HAL_NAND_CallbackIDTypeDef; 152 153 /** 154 * @brief HAL NAND Callback pointer definition 155 */ 156 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); 157 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 158 159 /** 160 * @} 161 */ 162 163 /* Exported constants --------------------------------------------------------*/ 164 /* Exported macro ------------------------------------------------------------*/ 165 /** @defgroup NAND_Exported_Macros NAND Exported Macros 166 * @{ 167 */ 168 169 /** @brief Reset NAND handle state 170 * @param __HANDLE__ specifies the NAND handle. 171 * @retval None 172 */ 173 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 174 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ 175 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ 176 (__HANDLE__)->MspInitCallback = NULL; \ 177 (__HANDLE__)->MspDeInitCallback = NULL; \ 178 } while(0) 179 #else 180 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 181 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 182 183 /** 184 * @} 185 */ 186 187 /* Exported functions --------------------------------------------------------*/ 188 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 189 * @{ 190 */ 191 192 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 193 * @{ 194 */ 195 196 /* Initialization/de-initialization functions ********************************/ 197 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, 198 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 199 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 200 201 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 202 203 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 204 205 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 206 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 207 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 208 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 209 210 /** 211 * @} 212 */ 213 214 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 215 * @{ 216 */ 217 218 /* IO operation functions ****************************************************/ 219 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 220 221 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 222 uint8_t *pBuffer, uint32_t NumPageToRead); 223 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 224 const uint8_t *pBuffer, uint32_t NumPageToWrite); 225 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 226 uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 227 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 228 const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 229 230 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 231 uint16_t *pBuffer, uint32_t NumPageToRead); 232 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 233 const uint16_t *pBuffer, uint32_t NumPageToWrite); 234 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 235 uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 236 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, 237 const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 238 239 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress); 240 241 uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 242 243 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 244 /* NAND callback registering/unregistering */ 245 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, 246 pNAND_CallbackTypeDef pCallback); 247 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); 248 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 249 250 /** 251 * @} 252 */ 253 254 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 255 * @{ 256 */ 257 258 /* NAND Control functions ****************************************************/ 259 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 260 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 261 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 262 263 /** 264 * @} 265 */ 266 267 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 268 * @{ 269 */ 270 /* NAND State functions *******************************************************/ 271 HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand); 272 uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); 273 /** 274 * @} 275 */ 276 277 /** 278 * @} 279 */ 280 281 /* Private types -------------------------------------------------------------*/ 282 /* Private variables ---------------------------------------------------------*/ 283 /* Private constants ---------------------------------------------------------*/ 284 /** @defgroup NAND_Private_Constants NAND Private Constants 285 * @{ 286 */ 287 #if defined(FMC_Bank2_3) 288 #define NAND_DEVICE1 0x70000000UL 289 #define NAND_DEVICE2 0x80000000UL 290 #else 291 #define NAND_DEVICE 0x80000000UL 292 #endif /* NAND_SECOND_BANK */ 293 #define NAND_WRITE_TIMEOUT 0x01000000UL 294 295 #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ 296 #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ 297 298 #define NAND_CMD_AREA_A ((uint8_t)0x00) 299 #define NAND_CMD_AREA_B ((uint8_t)0x01) 300 #define NAND_CMD_AREA_C ((uint8_t)0x50) 301 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) 302 303 #define NAND_CMD_WRITE0 ((uint8_t)0x80) 304 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) 305 #define NAND_CMD_ERASE0 ((uint8_t)0x60) 306 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) 307 #define NAND_CMD_READID ((uint8_t)0x90) 308 #define NAND_CMD_STATUS ((uint8_t)0x70) 309 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) 310 #define NAND_CMD_RESET ((uint8_t)0xFF) 311 312 /* NAND memory status */ 313 #define NAND_VALID_ADDRESS 0x00000100UL 314 #define NAND_INVALID_ADDRESS 0x00000200UL 315 #define NAND_TIMEOUT_ERROR 0x00000400UL 316 #define NAND_BUSY 0x00000000UL 317 #define NAND_ERROR 0x00000001UL 318 #define NAND_READY 0x00000040UL 319 /** 320 * @} 321 */ 322 323 /* Private macros ------------------------------------------------------------*/ 324 /** @defgroup NAND_Private_Macros NAND Private Macros 325 * @{ 326 */ 327 328 /** 329 * @brief NAND memory address computation. 330 * @param __ADDRESS__ NAND memory address. 331 * @param __HANDLE__ NAND handle. 332 * @retval NAND Raw address value 333 */ 334 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ 335 (((__ADDRESS__)->Block + \ 336 (((__ADDRESS__)->Plane) * \ 337 ((__HANDLE__)->Config.PlaneSize))) * \ 338 ((__HANDLE__)->Config.BlockSize))) 339 340 /** 341 * @brief NAND memory Column address computation. 342 * @param __HANDLE__ NAND handle. 343 * @retval NAND Raw address value 344 */ 345 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 346 347 /** 348 * @brief NAND memory address cycling. 349 * @param __ADDRESS__ NAND memory address. 350 * @retval NAND address cycling value. 351 */ 352 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 353 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 354 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 355 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 356 357 /** 358 * @brief NAND memory Columns cycling. 359 * @param __ADDRESS__ NAND memory address. 360 * @retval NAND Column address cycling value. 361 */ 362 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ 363 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 364 365 /** 366 * @} 367 */ 368 369 /** 370 * @} 371 */ 372 373 /** 374 * @} 375 */ 376 377 /** 378 * @} 379 */ 380 381 #endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */ 382 383 #ifdef __cplusplus 384 } 385 #endif 386 387 #endif /* STM32F4xx_HAL_NAND_H */ 388
