1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file containing functions prototypes of ADC HAL library. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F4xx_ADC_H 21 #define __STM32F4xx_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f4xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32f4xx_ll_adc.h" 32 33 /** @addtogroup STM32F4xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief Structure definition of ADC and regular group initialization 48 * @note Parameters of this structure are shared within 2 scopes: 49 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. 50 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 51 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 52 * ADC state can be either: 53 * - For all parameters: ADC disabled 54 * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. 55 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. 56 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 57 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 58 */ 59 typedef struct 60 { 61 uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for 62 all the ADCs. 63 This parameter can be a value of @ref ADC_ClockPrescaler */ 64 uint32_t Resolution; /*!< Configures the ADC resolution. 65 This parameter can be a value of @ref ADC_Resolution */ 66 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 67 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 68 This parameter can be a value of @ref ADC_Data_align */ 69 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 70 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 71 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 72 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 73 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 74 Scan direction is upward: from rank1 to rank 'n'. 75 This parameter can be set to ENABLE or DISABLE */ 76 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 77 This parameter can be a value of @ref ADC_EOCSelection. 78 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. 79 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) 80 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. 81 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). 82 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ 83 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 84 after the selected trigger occurred (software start or external trigger). 85 This parameter can be set to ENABLE or DISABLE. */ 86 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 87 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 88 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ 89 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 90 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 91 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 92 This parameter can be set to ENABLE or DISABLE. */ 93 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 94 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 95 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 96 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 97 If set to ADC_SOFTWARE_START, external triggers are disabled. 98 If set to external trigger source, triggering is on event rising edge by default. 99 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ 100 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 101 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 102 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 103 FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 104 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 105 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 106 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 107 This parameter can be set to ENABLE or DISABLE. */ 108 }ADC_InitTypeDef; 109 110 111 112 /** 113 * @brief Structure definition of ADC channel for regular group 114 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 115 * ADC can be either disabled or enabled without conversion on going on regular group. 116 */ 117 typedef struct 118 { 119 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 120 This parameter can be a value of @ref ADC_channels */ 121 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 122 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 123 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 124 Unit: ADC clock cycles 125 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 126 This parameter can be a value of @ref ADC_sampling_times 127 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 128 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 129 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 130 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 131 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 132 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ 133 }ADC_ChannelConfTypeDef; 134 135 /** 136 * @brief ADC Configuration multi-mode structure definition 137 */ 138 typedef struct 139 { 140 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. 141 This parameter can be a value of @ref ADC_analog_watchdog_selection */ 142 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 143 This parameter must be a 12-bit value. */ 144 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 145 This parameter must be a 12-bit value. */ 146 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. 147 This parameter has an effect only if watchdog mode is configured on single channel 148 This parameter can be a value of @ref ADC_channels */ 149 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured 150 is interrupt mode or in polling mode. 151 This parameter can be set to ENABLE or DISABLE */ 152 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 153 }ADC_AnalogWDGConfTypeDef; 154 155 /** 156 * @brief HAL ADC state machine: ADC states definition (bitfields) 157 */ 158 /* States of ADC global scope */ 159 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ 160 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ 161 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ 162 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ 163 164 /* States of ADC errors */ 165 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ 166 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ 167 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ 168 169 /* States of ADC group regular */ 170 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 171 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 172 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ 173 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */ 174 175 /* States of ADC group injected */ 176 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 177 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 178 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ 179 180 /* States of ADC analog watchdogs */ 181 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ 182 #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */ 183 #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */ 184 185 /* States of ADC multi-mode */ 186 #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */ 187 188 189 /** 190 * @brief ADC handle Structure definition 191 */ 192 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 193 typedef struct __ADC_HandleTypeDef 194 #else 195 typedef struct 196 #endif 197 { 198 ADC_TypeDef *Instance; /*!< Register base address */ 199 200 ADC_InitTypeDef Init; /*!< ADC required parameters */ 201 202 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ 203 204 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 205 206 HAL_LockTypeDef Lock; /*!< ADC locking object */ 207 208 __IO uint32_t State; /*!< ADC communication state */ 209 210 __IO uint32_t ErrorCode; /*!< ADC Error code */ 211 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 212 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 213 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 214 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 215 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 216 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 217 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 218 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 219 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 220 }ADC_HandleTypeDef; 221 222 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 223 /** 224 * @brief HAL ADC Callback ID enumeration definition 225 */ 226 typedef enum 227 { 228 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 229 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 230 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 231 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 232 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 233 HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ 234 HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ 235 } HAL_ADC_CallbackIDTypeDef; 236 237 /** 238 * @brief HAL ADC Callback pointer definition 239 */ 240 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 241 242 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 243 244 /** 245 * @} 246 */ 247 248 /* Exported constants --------------------------------------------------------*/ 249 /** @defgroup ADC_Exported_Constants ADC Exported Constants 250 * @{ 251 */ 252 253 /** @defgroup ADC_Error_Code ADC Error Code 254 * @{ 255 */ 256 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ 257 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, 258 enable/disable, erroneous state */ 259 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ 260 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ 261 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 262 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 263 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 264 /** 265 * @} 266 */ 267 268 269 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler 270 * @{ 271 */ 272 #define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U 273 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) 274 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) 275 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) 276 /** 277 * @} 278 */ 279 280 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases 281 * @{ 282 */ 283 #define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U 284 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) 285 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) 286 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 287 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) 288 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 289 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 290 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 291 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) 292 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) 293 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) 294 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 295 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) 296 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 297 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 298 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) 299 /** 300 * @} 301 */ 302 303 /** @defgroup ADC_Resolution ADC Resolution 304 * @{ 305 */ 306 #define ADC_RESOLUTION_12B 0x00000000U 307 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) 308 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) 309 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) 310 /** 311 * @} 312 */ 313 314 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular 315 * @{ 316 */ 317 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U 318 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) 319 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) 320 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) 321 /** 322 * @} 323 */ 324 325 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular 326 * @{ 327 */ 328 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ 329 /* compatibility with other STM32 devices. */ 330 #define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U 331 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) 332 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) 333 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 334 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) 335 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 336 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 337 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 338 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) 339 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) 340 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) 341 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 342 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) 343 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 344 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 345 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) 346 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U) 347 /** 348 * @} 349 */ 350 351 /** @defgroup ADC_Data_align ADC Data Align 352 * @{ 353 */ 354 #define ADC_DATAALIGN_RIGHT 0x00000000U 355 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 356 /** 357 * @} 358 */ 359 360 /** @defgroup ADC_channels ADC Common Channels 361 * @{ 362 */ 363 #define ADC_CHANNEL_0 0x00000000U 364 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) 365 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) 366 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 367 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) 368 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 369 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 370 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 371 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) 372 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) 373 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) 374 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 375 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) 376 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 377 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 378 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 379 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) 380 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) 381 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) 382 383 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) 384 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) 385 /** 386 * @} 387 */ 388 389 /** @defgroup ADC_sampling_times ADC Sampling Times 390 * @{ 391 */ 392 #define ADC_SAMPLETIME_3CYCLES 0x00000000U 393 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) 394 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) 395 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) 396 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) 397 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) 398 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) 399 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) 400 /** 401 * @} 402 */ 403 404 /** @defgroup ADC_EOCSelection ADC EOC Selection 405 * @{ 406 */ 407 #define ADC_EOC_SEQ_CONV 0x00000000U 408 #define ADC_EOC_SINGLE_CONV 0x00000001U 409 #define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */ 410 /** 411 * @} 412 */ 413 414 /** @defgroup ADC_Event_type ADC Event Type 415 * @{ 416 */ 417 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) 418 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) 419 /** 420 * @} 421 */ 422 423 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection 424 * @{ 425 */ 426 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 427 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 428 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 429 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) 430 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) 431 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 432 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U 433 /** 434 * @} 435 */ 436 437 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition 438 * @{ 439 */ 440 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) 441 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) 442 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) 443 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) 444 /** 445 * @} 446 */ 447 448 /** @defgroup ADC_flags_definition ADC Flags Definition 449 * @{ 450 */ 451 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) 452 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) 453 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) 454 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) 455 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) 456 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) 457 /** 458 * @} 459 */ 460 461 /** @defgroup ADC_channels_type ADC Channels Type 462 * @{ 463 */ 464 #define ADC_ALL_CHANNELS 0x00000001U 465 #define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */ 466 #define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */ 467 /** 468 * @} 469 */ 470 471 /** 472 * @} 473 */ 474 475 /* Exported macro ------------------------------------------------------------*/ 476 /** @defgroup ADC_Exported_Macros ADC Exported Macros 477 * @{ 478 */ 479 480 /** @brief Reset ADC handle state 481 * @param __HANDLE__ ADC handle 482 * @retval None 483 */ 484 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 485 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 486 do{ \ 487 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 488 (__HANDLE__)->MspInitCallback = NULL; \ 489 (__HANDLE__)->MspDeInitCallback = NULL; \ 490 } while(0) 491 #else 492 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 493 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 494 #endif 495 496 /** 497 * @brief Enable the ADC peripheral. 498 * @param __HANDLE__ ADC handle 499 * @retval None 500 */ 501 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) 502 503 /** 504 * @brief Disable the ADC peripheral. 505 * @param __HANDLE__ ADC handle 506 * @retval None 507 */ 508 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) 509 510 /** 511 * @brief Enable the ADC end of conversion interrupt. 512 * @param __HANDLE__ specifies the ADC Handle. 513 * @param __INTERRUPT__ ADC Interrupt. 514 * @retval None 515 */ 516 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) 517 518 /** 519 * @brief Disable the ADC end of conversion interrupt. 520 * @param __HANDLE__ specifies the ADC Handle. 521 * @param __INTERRUPT__ ADC interrupt. 522 * @retval None 523 */ 524 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) 525 526 /** @brief Check if the specified ADC interrupt source is enabled or disabled. 527 * @param __HANDLE__ specifies the ADC Handle. 528 * @param __INTERRUPT__ specifies the ADC interrupt source to check. 529 * @retval The new state of __IT__ (TRUE or FALSE). 530 */ 531 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 532 533 /** 534 * @brief Clear the ADC's pending flags. 535 * @param __HANDLE__ specifies the ADC Handle. 536 * @param __FLAG__ ADC flag. 537 * @retval None 538 */ 539 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) 540 541 /** 542 * @brief Get the selected ADC's flag status. 543 * @param __HANDLE__ specifies the ADC Handle. 544 * @param __FLAG__ ADC flag. 545 * @retval None 546 */ 547 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 548 549 /** 550 * @} 551 */ 552 553 /* Include ADC HAL Extension module */ 554 #include "stm32f4xx_hal_adc_ex.h" 555 556 /* Exported functions --------------------------------------------------------*/ 557 /** @addtogroup ADC_Exported_Functions 558 * @{ 559 */ 560 561 /** @addtogroup ADC_Exported_Functions_Group1 562 * @{ 563 */ 564 /* Initialization/de-initialization functions ***********************************/ 565 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 566 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 567 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 568 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 569 570 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 571 /* Callbacks Register/UnRegister functions ***********************************/ 572 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 573 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 574 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 575 /** 576 * @} 577 */ 578 579 /** @addtogroup ADC_Exported_Functions_Group2 580 * @{ 581 */ 582 /* I/O operation functions ******************************************************/ 583 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 584 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 585 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 586 587 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 588 589 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 590 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 591 592 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 593 594 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 595 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 596 597 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 598 599 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 600 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 601 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 602 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 603 /** 604 * @} 605 */ 606 607 /** @addtogroup ADC_Exported_Functions_Group3 608 * @{ 609 */ 610 /* Peripheral Control functions *************************************************/ 611 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 612 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 613 /** 614 * @} 615 */ 616 617 /** @addtogroup ADC_Exported_Functions_Group4 618 * @{ 619 */ 620 /* Peripheral State functions ***************************************************/ 621 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 622 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 623 /** 624 * @} 625 */ 626 627 /** 628 * @} 629 */ 630 /* Private types -------------------------------------------------------------*/ 631 /* Private variables ---------------------------------------------------------*/ 632 /* Private constants ---------------------------------------------------------*/ 633 /** @defgroup ADC_Private_Constants ADC Private Constants 634 * @{ 635 */ 636 /* Delay for ADC stabilization time. */ 637 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ 638 /* Unit: us */ 639 #define ADC_STAB_DELAY_US 3U 640 /* Delay for temperature sensor stabilization time. */ 641 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ 642 /* Unit: us */ 643 #define ADC_TEMPSENSOR_DELAY_US 10U 644 /** 645 * @} 646 */ 647 648 /* Private macro ------------------------------------------------------------*/ 649 650 /** @defgroup ADC_Private_Macros ADC Private Macros 651 * @{ 652 */ 653 /* Macro reserved for internal HAL driver usage, not intended to be used in 654 code of final user */ 655 656 /** 657 * @brief Verification of ADC state: enabled or disabled 658 * @param __HANDLE__ ADC handle 659 * @retval SET (ADC enabled) or RESET (ADC disabled) 660 */ 661 #define ADC_IS_ENABLE(__HANDLE__) \ 662 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ 663 ) ? SET : RESET) 664 665 /** 666 * @brief Test if conversion trigger of regular group is software start 667 * or external trigger. 668 * @param __HANDLE__ ADC handle 669 * @retval SET (software start) or RESET (external trigger) 670 */ 671 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 672 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 673 674 /** 675 * @brief Test if conversion trigger of injected group is software start 676 * or external trigger. 677 * @param __HANDLE__ ADC handle 678 * @retval SET (software start) or RESET (external trigger) 679 */ 680 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 681 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) 682 683 /** 684 * @brief Simultaneously clears and sets specific bits of the handle State 685 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 686 * the first parameter is the ADC handle State, the second parameter is the 687 * bit field to clear, the third and last parameter is the bit field to set. 688 * @retval None 689 */ 690 #define ADC_STATE_CLR_SET MODIFY_REG 691 692 /** 693 * @brief Clear ADC error code (set it to error code: "no error") 694 * @param __HANDLE__ ADC handle 695 * @retval None 696 */ 697 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 698 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 699 700 701 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 702 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 703 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ 704 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8)) 705 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 706 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 707 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 708 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 709 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 710 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 711 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 712 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ 713 ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ 714 ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ 715 ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ 716 ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ 717 ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ 718 ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ 719 ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ 720 ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) 721 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 722 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 723 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 724 ((RESOLUTION) == ADC_RESOLUTION_6B)) 725 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 726 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 727 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 728 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) 729 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 730 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 731 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 732 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 733 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 734 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ 735 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 736 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 737 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 738 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 739 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ 740 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ 741 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ 742 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ 743 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ 744 ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \ 745 ((REGTRIG) == ADC_SOFTWARE_START)) 746 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 747 ((ALIGN) == ADC_DATAALIGN_LEFT)) 748 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ 749 ((TIME) == ADC_SAMPLETIME_15CYCLES) || \ 750 ((TIME) == ADC_SAMPLETIME_28CYCLES) || \ 751 ((TIME) == ADC_SAMPLETIME_56CYCLES) || \ 752 ((TIME) == ADC_SAMPLETIME_84CYCLES) || \ 753 ((TIME) == ADC_SAMPLETIME_112CYCLES) || \ 754 ((TIME) == ADC_SAMPLETIME_144CYCLES) || \ 755 ((TIME) == ADC_SAMPLETIME_480CYCLES)) 756 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ 757 ((EOCSelection) == ADC_EOC_SEQ_CONV) || \ 758 ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) 759 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 760 ((EVENT) == ADC_OVR_EVENT)) 761 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 762 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 763 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 764 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 765 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 766 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ 767 ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) 768 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ 769 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ 770 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) 771 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU) 772 773 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) 774 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U))) 775 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 776 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 777 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \ 778 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \ 779 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \ 780 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU))) 781 782 /** 783 * @brief Set ADC Regular channel sequence length. 784 * @param _NbrOfConversion_ Regular channel sequence length. 785 * @retval None 786 */ 787 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) 788 789 /** 790 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 791 * @param _SAMPLETIME_ Sample time parameter. 792 * @param _CHANNELNB_ Channel number. 793 * @retval None 794 */ 795 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) 796 797 /** 798 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 799 * @param _SAMPLETIME_ Sample time parameter. 800 * @param _CHANNELNB_ Channel number. 801 * @retval None 802 */ 803 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) 804 805 /** 806 * @brief Set the selected regular channel rank for rank between 1 and 6. 807 * @param _CHANNELNB_ Channel number. 808 * @param _RANKNB_ Rank number. 809 * @retval None 810 */ 811 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) 812 813 /** 814 * @brief Set the selected regular channel rank for rank between 7 and 12. 815 * @param _CHANNELNB_ Channel number. 816 * @param _RANKNB_ Rank number. 817 * @retval None 818 */ 819 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) 820 821 /** 822 * @brief Set the selected regular channel rank for rank between 13 and 16. 823 * @param _CHANNELNB_ Channel number. 824 * @param _RANKNB_ Rank number. 825 * @retval None 826 */ 827 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) 828 829 /** 830 * @brief Enable ADC continuous conversion mode. 831 * @param _CONTINUOUS_MODE_ Continuous mode. 832 * @retval None 833 */ 834 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) 835 836 /** 837 * @brief Configures the number of discontinuous conversions for the regular group channels. 838 * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. 839 * @retval None 840 */ 841 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) 842 843 /** 844 * @brief Enable ADC scan mode. 845 * @param _SCANCONV_MODE_ Scan conversion mode. 846 * @retval None 847 */ 848 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) 849 850 /** 851 * @brief Enable the ADC end of conversion selection. 852 * @param _EOCSelection_MODE_ End of conversion selection mode. 853 * @retval None 854 */ 855 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) 856 857 /** 858 * @brief Enable the ADC DMA continuous request. 859 * @param _DMAContReq_MODE_ DMA continuous request mode. 860 * @retval None 861 */ 862 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) 863 864 /** 865 * @brief Return resolution bits in CR1 register. 866 * @param __HANDLE__ ADC handle 867 * @retval None 868 */ 869 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) 870 871 /** 872 * @} 873 */ 874 875 /* Private functions ---------------------------------------------------------*/ 876 /** @defgroup ADC_Private_Functions ADC Private Functions 877 * @{ 878 */ 879 880 /** 881 * @} 882 */ 883 884 /** 885 * @} 886 */ 887 888 /** 889 * @} 890 */ 891 892 #ifdef __cplusplus 893 } 894 #endif 895 896 #endif /*__STM32F4xx_ADC_H */ 897 898 899
