1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F3xx_LL_FMC_H 21 #define STM32F3xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f3xx_hal_def.h" 29 30 /** @addtogroup STM32F3xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FMC_BANK1) 42 43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FMC_NORSRAM_BANK4)) 47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 56 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 57 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 58 ((__MODE__) == FMC_ACCESS_MODE_D)) 59 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 60 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 61 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 62 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 63 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ 64 ((__MODE__) == FMC_WRAP_MODE_ENABLE)) 65 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 66 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 67 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 68 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 69 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 70 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 71 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 72 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 73 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 74 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 75 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 76 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 77 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 78 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 79 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 80 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 81 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 82 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 83 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 84 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 85 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 86 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 87 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 88 89 #endif /* FMC_BANK1 */ 90 #if defined(FMC_BANK3) 91 92 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 93 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ 94 ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) 95 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ 96 ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) 97 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 98 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 99 100 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 101 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 102 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 103 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 104 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 105 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 106 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 107 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 108 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 109 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 110 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 111 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 112 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 113 114 #endif /* FMC_BANK3 */ 115 #if defined(FMC_BANK4) 116 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) 117 118 #endif /* FMC_BANK4 */ 119 120 /** 121 * @} 122 */ 123 124 /* Exported typedef ----------------------------------------------------------*/ 125 126 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 127 * @{ 128 */ 129 130 #if defined(FMC_BANK1) 131 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 132 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 133 #endif /* FMC_BANK1 */ 134 #if defined(FMC_BANK3) 135 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef 136 #endif /* FMC_BANK3 */ 137 #if defined(FMC_BANK4) 138 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef 139 #endif /* FMC_BANK4 */ 140 141 #if defined(FMC_BANK1) 142 #define FMC_NORSRAM_DEVICE FMC_Bank1 143 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E 144 #endif /* FMC_BANK1 */ 145 #if defined(FMC_BANK3) 146 #define FMC_NAND_DEVICE FMC_Bank2_3 147 #endif /* FMC_BANK3 */ 148 #if defined(FMC_BANK4) 149 #define FMC_PCCARD_DEVICE FMC_Bank4 150 #endif /* FMC_BANK4 */ 151 152 #if defined(FMC_BANK1) 153 /** 154 * @brief FMC NORSRAM Configuration Structure definition 155 */ 156 typedef struct 157 { 158 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 159 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 160 161 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 162 multiplexed on the data bus or not. 163 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 164 165 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 166 the corresponding memory device. 167 This parameter can be a value of @ref FMC_Memory_Type */ 168 169 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 170 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 171 172 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 173 valid only with synchronous burst Flash memories. 174 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 175 176 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 177 the Flash memory in burst mode. 178 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 179 180 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 181 memory, valid only when accessing Flash memories in burst mode. 182 This parameter can be a value of @ref FMC_Wrap_Mode */ 183 184 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 185 clock cycle before the wait state or during the wait state, 186 valid only when accessing memories in burst mode. 187 This parameter can be a value of @ref FMC_Wait_Timing */ 188 189 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 190 This parameter can be a value of @ref FMC_Write_Operation */ 191 192 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 193 signal, valid for Flash memory access in burst mode. 194 This parameter can be a value of @ref FMC_Wait_Signal */ 195 196 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 197 This parameter can be a value of @ref FMC_Extended_Mode */ 198 199 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 200 valid only with asynchronous Flash memories. 201 This parameter can be a value of @ref FMC_AsynchronousWait */ 202 203 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 204 This parameter can be a value of @ref FMC_Write_Burst */ 205 206 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 207 This parameter is only enabled through the FMC_BCR1 register, 208 and don't care through FMC_BCR2..4 registers. 209 This parameter can be a value of @ref FMC_Continous_Clock */ 210 } FMC_NORSRAM_InitTypeDef; 211 212 /** 213 * @brief FMC NORSRAM Timing parameters structure definition 214 */ 215 typedef struct 216 { 217 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 218 the duration of the address setup time. 219 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 220 @note This parameter is not used with synchronous NOR Flash memories. */ 221 222 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 223 the duration of the address hold time. 224 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 225 @note This parameter is not used with synchronous NOR Flash memories. */ 226 227 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 228 the duration of the data setup time. 229 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 230 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 231 NOR Flash memories. */ 232 233 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 234 the duration of the bus turnaround. 235 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 236 @note This parameter is only used for multiplexed NOR Flash memories. */ 237 238 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 239 HCLK cycles. This parameter can be a value between Min_Data = 2 and 240 Max_Data = 16. 241 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 242 accesses. */ 243 244 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 245 to the memory before getting the first data. 246 The parameter value depends on the memory type as shown below: 247 - It must be set to 0 in case of a CRAM 248 - It is don't care in asynchronous NOR, SRAM or ROM accesses 249 - It may assume a value between Min_Data = 2 and Max_Data = 17 250 in NOR Flash memories with synchronous burst mode enable */ 251 252 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 253 This parameter can be a value of @ref FMC_Access_Mode */ 254 } FMC_NORSRAM_TimingTypeDef; 255 #endif /* FMC_BANK1 */ 256 257 #if defined(FMC_BANK3) 258 /** 259 * @brief FMC NAND Configuration Structure definition 260 */ 261 typedef struct 262 { 263 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 264 This parameter can be a value of @ref FMC_NAND_Bank */ 265 266 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 267 This parameter can be any value of @ref FMC_Wait_feature */ 268 269 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 270 This parameter can be any value of @ref FMC_NAND_Data_Width */ 271 272 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 273 This parameter can be any value of @ref FMC_ECC */ 274 275 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 276 This parameter can be any value of @ref FMC_ECC_Page_Size */ 277 278 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 279 delay between CLE low and RE low. 280 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 281 282 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 283 delay between ALE low and RE low. 284 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 285 } FMC_NAND_InitTypeDef; 286 #endif /* FMC_BANK3 */ 287 288 #if defined(FMC_BANK3) || defined(FMC_BANK4) 289 /** 290 * @brief FMC NAND Timing parameters structure definition 291 */ 292 typedef struct 293 { 294 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 295 the command assertion for NAND-Flash read or write access 296 to common/Attribute or I/O memory space (depending on 297 the memory space timing to be configured). 298 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 299 300 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 301 command for NAND-Flash read or write access to 302 common/Attribute or I/O memory space (depending on the 303 memory space timing to be configured). 304 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 305 306 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 307 (and data for write access) after the command de-assertion 308 for NAND-Flash read or write access to common/Attribute 309 or I/O memory space (depending on the memory space timing 310 to be configured). 311 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 312 313 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 314 data bus is kept in HiZ after the start of a NAND-Flash 315 write access to common/Attribute or I/O memory space (depending 316 on the memory space timing to be configured). 317 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 318 } FMC_NAND_PCC_TimingTypeDef; 319 #endif /* FMC_BANK3 */ 320 321 #if defined(FMC_BANK4) 322 /** 323 * @brief FMC PCCARD Configuration Structure definition 324 */ 325 typedef struct 326 { 327 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. 328 This parameter can be any value of @ref FMC_Wait_feature */ 329 330 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 331 delay between CLE low and RE low. 332 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 333 334 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 335 delay between ALE low and RE low. 336 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 337 }FMC_PCCARD_InitTypeDef; 338 #endif /* FMC_BANK4 */ 339 340 /** 341 * @} 342 */ 343 344 /* Exported constants --------------------------------------------------------*/ 345 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 346 * @{ 347 */ 348 #if defined(FMC_BANK1) 349 350 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 351 * @{ 352 */ 353 354 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 355 * @{ 356 */ 357 #define FMC_NORSRAM_BANK1 (0x00000000U) 358 #define FMC_NORSRAM_BANK2 (0x00000002U) 359 #define FMC_NORSRAM_BANK3 (0x00000004U) 360 #define FMC_NORSRAM_BANK4 (0x00000006U) 361 /** 362 * @} 363 */ 364 365 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 366 * @{ 367 */ 368 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 369 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 370 /** 371 * @} 372 */ 373 374 /** @defgroup FMC_Memory_Type FMC Memory Type 375 * @{ 376 */ 377 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 378 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 379 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 380 /** 381 * @} 382 */ 383 384 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 385 * @{ 386 */ 387 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 388 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 389 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 390 /** 391 * @} 392 */ 393 394 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 395 * @{ 396 */ 397 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 398 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 399 /** 400 * @} 401 */ 402 403 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 404 * @{ 405 */ 406 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 407 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 408 /** 409 * @} 410 */ 411 412 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 413 * @{ 414 */ 415 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 416 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 417 /** 418 * @} 419 */ 420 421 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode 422 * @{ 423 */ 424 #define FMC_WRAP_MODE_DISABLE (0x00000000U) 425 #define FMC_WRAP_MODE_ENABLE (0x00000400U) 426 /** 427 * @} 428 */ 429 430 /** @defgroup FMC_Wait_Timing FMC Wait Timing 431 * @{ 432 */ 433 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 434 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 435 /** 436 * @} 437 */ 438 439 /** @defgroup FMC_Write_Operation FMC Write Operation 440 * @{ 441 */ 442 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 443 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 444 /** 445 * @} 446 */ 447 448 /** @defgroup FMC_Wait_Signal FMC Wait Signal 449 * @{ 450 */ 451 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 452 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 453 /** 454 * @} 455 */ 456 457 /** @defgroup FMC_Extended_Mode FMC Extended Mode 458 * @{ 459 */ 460 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 461 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 462 /** 463 * @} 464 */ 465 466 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 467 * @{ 468 */ 469 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 470 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 471 /** 472 * @} 473 */ 474 475 /** @defgroup FMC_Write_Burst FMC Write Burst 476 * @{ 477 */ 478 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 479 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 480 /** 481 * @} 482 */ 483 484 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 485 * @{ 486 */ 487 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 488 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 489 /** 490 * @} 491 */ 492 493 /** @defgroup FMC_Access_Mode FMC Access Mode 494 * @{ 495 */ 496 #define FMC_ACCESS_MODE_A (0x00000000U) 497 #define FMC_ACCESS_MODE_B (0x10000000U) 498 #define FMC_ACCESS_MODE_C (0x20000000U) 499 #define FMC_ACCESS_MODE_D (0x30000000U) 500 /** 501 * @} 502 */ 503 504 /** 505 * @} 506 */ 507 #endif /* FMC_BANK1 */ 508 509 #if defined(FMC_BANK3) || defined(FMC_BANK4) 510 511 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 512 * @{ 513 */ 514 /** @defgroup FMC_NAND_Bank FMC NAND Bank 515 * @{ 516 */ 517 #define FMC_NAND_BANK2 (0x00000010U) 518 #define FMC_NAND_BANK3 (0x00000100U) 519 /** 520 * @} 521 */ 522 523 /** @defgroup FMC_Wait_feature FMC Wait feature 524 * @{ 525 */ 526 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) 527 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) 528 /** 529 * @} 530 */ 531 532 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 533 * @{ 534 */ 535 #if defined(FMC_BANK4) 536 #define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) 537 #endif /* FMC_BANK4 */ 538 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 539 /** 540 * @} 541 */ 542 543 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 544 * @{ 545 */ 546 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) 547 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) 548 /** 549 * @} 550 */ 551 552 /** @defgroup FMC_ECC FMC ECC 553 * @{ 554 */ 555 #define FMC_NAND_ECC_DISABLE (0x00000000U) 556 #define FMC_NAND_ECC_ENABLE (0x00000040U) 557 /** 558 * @} 559 */ 560 561 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 562 * @{ 563 */ 564 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 565 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 566 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 567 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 568 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 569 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 570 /** 571 * @} 572 */ 573 574 /** 575 * @} 576 */ 577 #endif /* FMC_BANK3 || FMC_BANK4 */ 578 579 580 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 581 * @{ 582 */ 583 #if defined(FMC_BANK3) || defined(FMC_BANK4) 584 #define FMC_IT_RISING_EDGE (0x00000008U) 585 #define FMC_IT_LEVEL (0x00000010U) 586 #define FMC_IT_FALLING_EDGE (0x00000020U) 587 #endif /* FMC_BANK3 || FMC_BANK4 */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 593 * @{ 594 */ 595 #if defined(FMC_BANK3) || defined(FMC_BANK4) 596 #define FMC_FLAG_RISING_EDGE (0x00000001U) 597 #define FMC_FLAG_LEVEL (0x00000002U) 598 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 599 #define FMC_FLAG_FEMPT (0x00000040U) 600 #endif /* FMC_BANK3 || FMC_BANK4 */ 601 /** 602 * @} 603 */ 604 605 /** 606 * @} 607 */ 608 609 /** 610 * @} 611 */ 612 613 /* Private macro -------------------------------------------------------------*/ 614 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 615 * @{ 616 */ 617 #if defined(FMC_BANK1) 618 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 619 * @brief macros to handle NOR device enable/disable and read/write operations 620 * @{ 621 */ 622 623 /** 624 * @brief Enable the NORSRAM device access. 625 * @param __INSTANCE__ FMC_NORSRAM Instance 626 * @param __BANK__ FMC_NORSRAM Bank 627 * @retval None 628 */ 629 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 630 |= FMC_BCRx_MBKEN) 631 632 /** 633 * @brief Disable the NORSRAM device access. 634 * @param __INSTANCE__ FMC_NORSRAM Instance 635 * @param __BANK__ FMC_NORSRAM Bank 636 * @retval None 637 */ 638 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 639 &= ~FMC_BCRx_MBKEN) 640 641 /** 642 * @} 643 */ 644 #endif /* FMC_BANK1 */ 645 646 #if defined(FMC_BANK3) 647 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 648 * @brief macros to handle NAND device enable/disable 649 * @{ 650 */ 651 652 /** 653 * @brief Enable the NAND device access. 654 * @param __INSTANCE__ FMC_NAND Instance 655 * @param __BANK__ FMC_NAND Bank 656 * @retval None 657 */ 658 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCRx_PBKEN): \ 659 ((__INSTANCE__)->PCR3 |= FMC_PCRx_PBKEN)) 660 661 /** 662 * @brief Disable the NAND device access. 663 * @param __INSTANCE__ FMC_NAND Instance 664 * @param __BANK__ FMC_NAND Bank 665 * @retval None 666 */ 667 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \ 668 CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN)) 669 670 /** 671 * @} 672 */ 673 #endif /* FMC_BANK3 */ 674 675 #if defined(FMC_BANK4) 676 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros 677 * @brief macros to handle PCCARD read/write operations 678 * @{ 679 */ 680 /** 681 * @brief Enable the PCCARD device access. 682 * @param __INSTANCE__ FMC_PCCARD Instance 683 * @retval None 684 */ 685 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN) 686 687 /** 688 * @brief Disable the PCCARD device access. 689 * @param __INSTANCE__ FMC_PCCARD Instance 690 * @retval None 691 */ 692 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN) 693 /** 694 * @} 695 */ 696 697 #endif 698 #if defined(FMC_BANK3) 699 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 700 * @brief macros to handle NAND interrupts 701 * @{ 702 */ 703 704 /** 705 * @brief Enable the NAND device interrupt. 706 * @param __INSTANCE__ FMC_NAND instance 707 * @param __BANK__ FMC_NAND Bank 708 * @param __INTERRUPT__ FMC_NAND interrupt 709 * This parameter can be any combination of the following values: 710 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 711 * @arg FMC_IT_LEVEL: Interrupt level. 712 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 713 * @retval None 714 */ 715 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ 716 ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) 717 718 /** 719 * @brief Disable the NAND device interrupt. 720 * @param __INSTANCE__ FMC_NAND Instance 721 * @param __BANK__ FMC_NAND Bank 722 * @param __INTERRUPT__ FMC_NAND interrupt 723 * This parameter can be any combination of the following values: 724 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 725 * @arg FMC_IT_LEVEL: Interrupt level. 726 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 727 * @retval None 728 */ 729 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ 730 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 731 732 /** 733 * @brief Get flag status of the NAND device. 734 * @param __INSTANCE__ FMC_NAND Instance 735 * @param __BANK__ FMC_NAND Bank 736 * @param __FLAG__ FMC_NAND flag 737 * This parameter can be any combination of the following values: 738 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 739 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 740 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 741 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 742 * @retval The state of FLAG (SET or RESET). 743 */ 744 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ 745 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) 746 747 /** 748 * @brief Clear flag status of the NAND device. 749 * @param __INSTANCE__ FMC_NAND Instance 750 * @param __BANK__ FMC_NAND Bank 751 * @param __FLAG__ FMC_NAND flag 752 * This parameter can be any combination of the following values: 753 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 754 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 755 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 756 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 757 * @retval None 758 */ 759 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ 760 ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 761 762 /** 763 * @} 764 */ 765 #endif /* FMC_BANK3 */ 766 767 #if defined(FMC_BANK4) 768 /** @defgroup FMC_LL_PCCARD_Interrupt FMC PCCARD Interrupt 769 * @brief macros to handle PCCARD interrupts 770 * @{ 771 */ 772 773 /** 774 * @brief Enable the PCCARD device interrupt. 775 * @param __INSTANCE__ FMC_PCCARD instance 776 * @param __INTERRUPT__ FMC_PCCARD interrupt 777 * This parameter can be any combination of the following values: 778 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 779 * @arg FMC_IT_LEVEL: Interrupt level. 780 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 781 * @retval None 782 */ 783 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) 784 785 /** 786 * @brief Disable the PCCARD device interrupt. 787 * @param __INSTANCE__ FMC_PCCARD instance 788 * @param __INTERRUPT__ FMC_PCCARD interrupt 789 * This parameter can be any combination of the following values: 790 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 791 * @arg FMC_IT_LEVEL: Interrupt level. 792 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 793 * @retval None 794 */ 795 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) 796 797 /** 798 * @brief Get flag status of the PCCARD device. 799 * @param __INSTANCE__ FMC_PCCARD instance 800 * @param __FLAG__ FMC_PCCARD flag 801 * This parameter can be any combination of the following values: 802 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 803 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 804 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 805 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 806 * @retval The state of FLAG (SET or RESET). 807 */ 808 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) 809 810 /** 811 * @brief Clear flag status of the PCCARD device. 812 * @param __INSTANCE__ FMC_PCCARD instance 813 * @param __FLAG__ FMC_PCCARD flag 814 * This parameter can be any combination of the following values: 815 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 816 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 817 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 818 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 819 * @retval None 820 */ 821 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) 822 823 /** 824 * @} 825 */ 826 #endif 827 828 /** 829 * @} 830 */ 831 832 /** 833 * @} 834 */ 835 836 /* Private functions ---------------------------------------------------------*/ 837 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 838 * @{ 839 */ 840 841 #if defined(FMC_BANK1) 842 /** @defgroup FMC_LL_NORSRAM NOR SRAM 843 * @{ 844 */ 845 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 846 * @{ 847 */ 848 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 849 FMC_NORSRAM_InitTypeDef *Init); 850 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 851 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 852 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 853 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 854 uint32_t ExtendedMode); 855 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 856 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 857 /** 858 * @} 859 */ 860 861 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 862 * @{ 863 */ 864 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 865 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 866 /** 867 * @} 868 */ 869 /** 870 * @} 871 */ 872 #endif /* FMC_BANK1 */ 873 874 #if defined(FMC_BANK3) 875 /** @defgroup FMC_LL_NAND NAND 876 * @{ 877 */ 878 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 879 * @{ 880 */ 881 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 882 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 883 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 884 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 885 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 886 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 887 /** 888 * @} 889 */ 890 891 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 892 * @{ 893 */ 894 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 895 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 896 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 897 uint32_t Timeout); 898 /** 899 * @} 900 */ 901 /** 902 * @} 903 */ 904 #endif /* FMC_BANK3 */ 905 906 #if defined(FMC_BANK4) 907 /** @defgroup FMC_LL_PCCARD PCCARD 908 * @{ 909 */ 910 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions 911 * @{ 912 */ 913 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init); 914 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, 915 FMC_NAND_PCC_TimingTypeDef *Timing); 916 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, 917 FMC_NAND_PCC_TimingTypeDef *Timing); 918 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, 919 FMC_NAND_PCC_TimingTypeDef *Timing); 920 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); 921 /** 922 * @} 923 */ 924 /** 925 * @} 926 */ 927 #endif /* FMC_BANK4 */ 928 929 930 /** 931 * @} 932 */ 933 934 /** 935 * @} 936 */ 937 938 /** 939 * @} 940 */ 941 942 #ifdef __cplusplus 943 } 944 #endif 945 946 #endif /* STM32F3xx_LL_FMC_H */ 947
