1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The SPI HAL driver can be used as follows:
29
30 (#) Declare a SPI_HandleTypeDef handle structure, for example:
31 SPI_HandleTypeDef hspi;
32
33 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
34 (##) Enable the SPIx interface clock
35 (##) SPI pins configuration
36 (+++) Enable the clock for the SPI GPIOs
37 (+++) Configure these SPI pins as alternate function push-pull
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the SPIx interrupt priority
40 (+++) Enable the NVIC SPI IRQ handle
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
43 (+++) Enable the DMAx clock
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx Stream/Channel
46 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
48
49 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
50 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
51
52 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
53 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
54 by calling the customized HAL_SPI_MspInit() API.
55 [..]
56 Circular mode restriction:
57 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
58 (##) Master 2Lines RxOnly
59 (##) Master 1Line Rx
60 (#) The CRC feature is not managed when the DMA circular mode is enabled
61 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
62 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
63 [..]
64 Master Receive mode restriction:
65 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
66 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
67 does not initiate a new transfer the following procedure has to be respected:
68 (##) HAL_SPI_DeInit()
69 (##) HAL_SPI_Init()
70 [..]
71 Callback registration:
72
73 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
74 allows the user to configure dynamically the driver callbacks.
75 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
76
77 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
78 (++) TxCpltCallback : SPI Tx Completed callback
79 (++) RxCpltCallback : SPI Rx Completed callback
80 (++) TxRxCpltCallback : SPI TxRx Completed callback
81 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
82 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
83 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
84 (++) ErrorCallback : SPI Error callback
85 (++) AbortCpltCallback : SPI Abort callback
86 (++) MspInitCallback : SPI Msp Init callback
87 (++) MspDeInitCallback : SPI Msp DeInit callback
88 This function takes as parameters the HAL peripheral handle, the Callback ID
89 and a pointer to the user callback function.
90
91
92 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
93 weak function.
94 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
95 and the Callback ID.
96 This function allows to reset following callbacks:
97 (++) TxCpltCallback : SPI Tx Completed callback
98 (++) RxCpltCallback : SPI Rx Completed callback
99 (++) TxRxCpltCallback : SPI TxRx Completed callback
100 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
101 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
102 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
103 (++) ErrorCallback : SPI Error callback
104 (++) AbortCpltCallback : SPI Abort callback
105 (++) MspInitCallback : SPI Msp Init callback
106 (++) MspDeInitCallback : SPI Msp DeInit callback
107
108 [..]
109 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
110 all callbacks are set to the corresponding weak functions:
111 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
112 Exception done for MspInit and MspDeInit functions that are
113 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
114 these callbacks are null (not registered beforehand).
115 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
116 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
117
118 [..]
119 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
120 Exception done MspInit/MspDeInit functions that can be registered/unregistered
121 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
122 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 Then, the user first registers the MspInit/MspDeInit user callbacks
124 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
125 or HAL_SPI_Init() function.
126
127 [..]
128 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
129 not defined, the callback registering feature is not available
130 and weak (surcharged) callbacks are used.
131
132 [..]
133 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
134 the following table resume the max SPI frequency reached with data size 8bits/16bits,
135 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
136
137 @endverbatim
138
139 Additional table :
140
141 DataSize = SPI_DATASIZE_8BIT:
142 +----------------------------------------------------------------------------------------------+
143 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
144 | Process | Transfer mode |---------------------|----------------------|----------------------|
145 | | | Master | Slave | Master | Slave | Master | Slave |
146 |==============================================================================================|
147 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
148 | X |----------------|----------|----------|-----------|----------|-----------|----------|
149 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
150 | R |----------------|----------|----------|-----------|----------|-----------|----------|
151 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
152 |=========|================|==========|==========|===========|==========|===========|==========|
153 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
154 | |----------------|----------|----------|-----------|----------|-----------|----------|
155 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
156 | X |----------------|----------|----------|-----------|----------|-----------|----------|
157 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
158 |=========|================|==========|==========|===========|==========|===========|==========|
159 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
160 | |----------------|----------|----------|-----------|----------|-----------|----------|
161 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
162 | X |----------------|----------|----------|-----------|----------|-----------|----------|
163 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
164 +----------------------------------------------------------------------------------------------+
165
166 DataSize = SPI_DATASIZE_16BIT:
167 +----------------------------------------------------------------------------------------------+
168 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
169 | Process | Transfer mode |---------------------|----------------------|----------------------|
170 | | | Master | Slave | Master | Slave | Master | Slave |
171 |==============================================================================================|
172 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
173 | X |----------------|----------|----------|-----------|----------|-----------|----------|
174 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
175 | R |----------------|----------|----------|-----------|----------|-----------|----------|
176 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
177 |=========|================|==========|==========|===========|==========|===========|==========|
178 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
179 | |----------------|----------|----------|-----------|----------|-----------|----------|
180 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
181 | X |----------------|----------|----------|-----------|----------|-----------|----------|
182 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
183 |=========|================|==========|==========|===========|==========|===========|==========|
184 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
185 | |----------------|----------|----------|-----------|----------|-----------|----------|
186 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
187 | X |----------------|----------|----------|-----------|----------|-----------|----------|
188 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
189 +----------------------------------------------------------------------------------------------+
190 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
191 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
192 @note
193 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
194 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
195 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
196
197 */
198
199 /* Includes ------------------------------------------------------------------*/
200 #include "stm32f3xx_hal.h"
201
202 /** @addtogroup STM32F3xx_HAL_Driver
203 * @{
204 */
205
206 /** @defgroup SPI SPI
207 * @brief SPI HAL module driver
208 * @{
209 */
210 #ifdef HAL_SPI_MODULE_ENABLED
211
212 /* Private typedef -----------------------------------------------------------*/
213 /* Private defines -----------------------------------------------------------*/
214 /** @defgroup SPI_Private_Constants SPI Private Constants
215 * @{
216 */
217 #define SPI_DEFAULT_TIMEOUT 100U
218 /**
219 * @}
220 */
221
222 /* Private macros ------------------------------------------------------------*/
223 /* Private variables ---------------------------------------------------------*/
224 /* Private function prototypes -----------------------------------------------*/
225 /** @defgroup SPI_Private_Functions SPI Private Functions
226 * @{
227 */
228 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
229 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
236 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
237 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
238 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
239 uint32_t Timeout, uint32_t Tickstart);
240 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
241 uint32_t Timeout, uint32_t Tickstart);
242 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
243 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
250 #if (USE_SPI_CRC != 0U)
251 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
252 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
255 #endif /* USE_SPI_CRC */
256 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
257 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
261 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
262 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
263 /**
264 * @}
265 */
266
267 /* Exported functions --------------------------------------------------------*/
268 /** @defgroup SPI_Exported_Functions SPI Exported Functions
269 * @{
270 */
271
272 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
273 * @brief Initialization and Configuration functions
274 *
275 @verbatim
276 ===============================================================================
277 ##### Initialization and de-initialization functions #####
278 ===============================================================================
279 [..] This subsection provides a set of functions allowing to initialize and
280 de-initialize the SPIx peripheral:
281
282 (+) User must implement HAL_SPI_MspInit() function in which he configures
283 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
284
285 (+) Call the function HAL_SPI_Init() to configure the selected device with
286 the selected configuration:
287 (++) Mode
288 (++) Direction
289 (++) Data Size
290 (++) Clock Polarity and Phase
291 (++) NSS Management
292 (++) BaudRate Prescaler
293 (++) FirstBit
294 (++) TIMode
295 (++) CRC Calculation
296 (++) CRC Polynomial if CRC enabled
297 (++) CRC Length, used only with Data8 and Data16
298 (++) FIFO reception threshold
299
300 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
301 of the selected SPIx peripheral.
302
303 @endverbatim
304 * @{
305 */
306
307 /**
308 * @brief Initialize the SPI according to the specified parameters
309 * in the SPI_InitTypeDef and initialize the associated handle.
310 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
311 * the configuration information for SPI module.
312 * @retval HAL status
313 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)314 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
315 {
316 uint32_t frxth;
317
318 /* Check the SPI handle allocation */
319 if (hspi == NULL)
320 {
321 return HAL_ERROR;
322 }
323
324 /* Check the parameters */
325 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
326 assert_param(IS_SPI_MODE(hspi->Init.Mode));
327 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
328 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
329 assert_param(IS_SPI_NSS(hspi->Init.NSS));
330 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
331 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
332 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
333 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
334 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
335 {
336 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
337 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
338
339 if (hspi->Init.Mode == SPI_MODE_MASTER)
340 {
341 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
342 }
343 else
344 {
345 /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
346 hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
347 }
348 }
349 else
350 {
351 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
352
353 /* Force polarity and phase to TI protocaol requirements */
354 hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
355 hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
356 }
357 #if (USE_SPI_CRC != 0U)
358 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
359 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
360 {
361 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
362 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
363 }
364 #else
365 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
366 #endif /* USE_SPI_CRC */
367
368 if (hspi->State == HAL_SPI_STATE_RESET)
369 {
370 /* Allocate lock resource and initialize it */
371 hspi->Lock = HAL_UNLOCKED;
372
373 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
374 /* Init the SPI Callback settings */
375 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
376 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
377 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
378 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
379 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
380 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
381 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
382 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
383
384 if (hspi->MspInitCallback == NULL)
385 {
386 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
387 }
388
389 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
390 hspi->MspInitCallback(hspi);
391 #else
392 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
393 HAL_SPI_MspInit(hspi);
394 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
395 }
396
397 hspi->State = HAL_SPI_STATE_BUSY;
398
399 /* Disable the selected SPI peripheral */
400 __HAL_SPI_DISABLE(hspi);
401
402 /* Align by default the rs fifo threshold on the data size */
403 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
404 {
405 frxth = SPI_RXFIFO_THRESHOLD_HF;
406 }
407 else
408 {
409 frxth = SPI_RXFIFO_THRESHOLD_QF;
410 }
411
412 /* CRC calculation is valid only for 16Bit and 8 Bit */
413 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
414 {
415 /* CRC must be disabled */
416 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
417 }
418
419 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
420 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
421 Communication speed, First bit and CRC calculation state */
422 WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
423 (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
424 (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
425 (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
426 (hspi->Init.NSS & SPI_CR1_SSM) |
427 (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
428 (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
429 (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
430 #if (USE_SPI_CRC != 0U)
431 /*---------------------------- SPIx CRCL Configuration -------------------*/
432 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
433 {
434 /* Align the CRC Length on the data size */
435 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
436 {
437 /* CRC Length aligned on the data size : value set by default */
438 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
439 {
440 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
441 }
442 else
443 {
444 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
445 }
446 }
447
448 /* Configure : CRC Length */
449 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
450 {
451 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
452 }
453 }
454 #endif /* USE_SPI_CRC */
455
456 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
457 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
458 (hspi->Init.TIMode & SPI_CR2_FRF) |
459 (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
460 (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
461 (frxth & SPI_CR2_FRXTH)));
462
463 #if (USE_SPI_CRC != 0U)
464 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
465 /* Configure : CRC Polynomial */
466 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
467 {
468 WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
469 }
470 #endif /* USE_SPI_CRC */
471
472 #if defined(SPI_I2SCFGR_I2SMOD)
473 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
474 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
475 #endif /* SPI_I2SCFGR_I2SMOD */
476
477 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
478 hspi->State = HAL_SPI_STATE_READY;
479
480 return HAL_OK;
481 }
482
483 /**
484 * @brief De-Initialize the SPI peripheral.
485 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
486 * the configuration information for SPI module.
487 * @retval HAL status
488 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)489 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
490 {
491 /* Check the SPI handle allocation */
492 if (hspi == NULL)
493 {
494 return HAL_ERROR;
495 }
496
497 /* Check SPI Instance parameter */
498 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
499
500 hspi->State = HAL_SPI_STATE_BUSY;
501
502 /* Disable the SPI Peripheral Clock */
503 __HAL_SPI_DISABLE(hspi);
504
505 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
506 if (hspi->MspDeInitCallback == NULL)
507 {
508 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
509 }
510
511 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
512 hspi->MspDeInitCallback(hspi);
513 #else
514 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
515 HAL_SPI_MspDeInit(hspi);
516 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
517
518 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
519 hspi->State = HAL_SPI_STATE_RESET;
520
521 /* Release Lock */
522 __HAL_UNLOCK(hspi);
523
524 return HAL_OK;
525 }
526
527 /**
528 * @brief Initialize the SPI MSP.
529 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
530 * the configuration information for SPI module.
531 * @retval None
532 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)533 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
534 {
535 /* Prevent unused argument(s) compilation warning */
536 UNUSED(hspi);
537
538 /* NOTE : This function should not be modified, when the callback is needed,
539 the HAL_SPI_MspInit should be implemented in the user file
540 */
541 }
542
543 /**
544 * @brief De-Initialize the SPI MSP.
545 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
546 * the configuration information for SPI module.
547 * @retval None
548 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)549 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
550 {
551 /* Prevent unused argument(s) compilation warning */
552 UNUSED(hspi);
553
554 /* NOTE : This function should not be modified, when the callback is needed,
555 the HAL_SPI_MspDeInit should be implemented in the user file
556 */
557 }
558
559 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
560 /**
561 * @brief Register a User SPI Callback
562 * To be used instead of the weak predefined callback
563 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
564 * the configuration information for the specified SPI.
565 * @param CallbackID ID of the callback to be registered
566 * @param pCallback pointer to the Callback function
567 * @retval HAL status
568 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)569 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
570 pSPI_CallbackTypeDef pCallback)
571 {
572 HAL_StatusTypeDef status = HAL_OK;
573
574 if (pCallback == NULL)
575 {
576 /* Update the error code */
577 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
578
579 return HAL_ERROR;
580 }
581 /* Process locked */
582 __HAL_LOCK(hspi);
583
584 if (HAL_SPI_STATE_READY == hspi->State)
585 {
586 switch (CallbackID)
587 {
588 case HAL_SPI_TX_COMPLETE_CB_ID :
589 hspi->TxCpltCallback = pCallback;
590 break;
591
592 case HAL_SPI_RX_COMPLETE_CB_ID :
593 hspi->RxCpltCallback = pCallback;
594 break;
595
596 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
597 hspi->TxRxCpltCallback = pCallback;
598 break;
599
600 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
601 hspi->TxHalfCpltCallback = pCallback;
602 break;
603
604 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
605 hspi->RxHalfCpltCallback = pCallback;
606 break;
607
608 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
609 hspi->TxRxHalfCpltCallback = pCallback;
610 break;
611
612 case HAL_SPI_ERROR_CB_ID :
613 hspi->ErrorCallback = pCallback;
614 break;
615
616 case HAL_SPI_ABORT_CB_ID :
617 hspi->AbortCpltCallback = pCallback;
618 break;
619
620 case HAL_SPI_MSPINIT_CB_ID :
621 hspi->MspInitCallback = pCallback;
622 break;
623
624 case HAL_SPI_MSPDEINIT_CB_ID :
625 hspi->MspDeInitCallback = pCallback;
626 break;
627
628 default :
629 /* Update the error code */
630 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
631
632 /* Return error status */
633 status = HAL_ERROR;
634 break;
635 }
636 }
637 else if (HAL_SPI_STATE_RESET == hspi->State)
638 {
639 switch (CallbackID)
640 {
641 case HAL_SPI_MSPINIT_CB_ID :
642 hspi->MspInitCallback = pCallback;
643 break;
644
645 case HAL_SPI_MSPDEINIT_CB_ID :
646 hspi->MspDeInitCallback = pCallback;
647 break;
648
649 default :
650 /* Update the error code */
651 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
652
653 /* Return error status */
654 status = HAL_ERROR;
655 break;
656 }
657 }
658 else
659 {
660 /* Update the error code */
661 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
662
663 /* Return error status */
664 status = HAL_ERROR;
665 }
666
667 /* Release Lock */
668 __HAL_UNLOCK(hspi);
669 return status;
670 }
671
672 /**
673 * @brief Unregister an SPI Callback
674 * SPI callback is redirected to the weak predefined callback
675 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
676 * the configuration information for the specified SPI.
677 * @param CallbackID ID of the callback to be unregistered
678 * @retval HAL status
679 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)680 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
681 {
682 HAL_StatusTypeDef status = HAL_OK;
683
684 /* Process locked */
685 __HAL_LOCK(hspi);
686
687 if (HAL_SPI_STATE_READY == hspi->State)
688 {
689 switch (CallbackID)
690 {
691 case HAL_SPI_TX_COMPLETE_CB_ID :
692 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
693 break;
694
695 case HAL_SPI_RX_COMPLETE_CB_ID :
696 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
697 break;
698
699 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
700 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
701 break;
702
703 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
704 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
705 break;
706
707 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
708 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
709 break;
710
711 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
712 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
713 break;
714
715 case HAL_SPI_ERROR_CB_ID :
716 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
717 break;
718
719 case HAL_SPI_ABORT_CB_ID :
720 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
721 break;
722
723 case HAL_SPI_MSPINIT_CB_ID :
724 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
725 break;
726
727 case HAL_SPI_MSPDEINIT_CB_ID :
728 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
729 break;
730
731 default :
732 /* Update the error code */
733 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
734
735 /* Return error status */
736 status = HAL_ERROR;
737 break;
738 }
739 }
740 else if (HAL_SPI_STATE_RESET == hspi->State)
741 {
742 switch (CallbackID)
743 {
744 case HAL_SPI_MSPINIT_CB_ID :
745 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
746 break;
747
748 case HAL_SPI_MSPDEINIT_CB_ID :
749 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
750 break;
751
752 default :
753 /* Update the error code */
754 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
755
756 /* Return error status */
757 status = HAL_ERROR;
758 break;
759 }
760 }
761 else
762 {
763 /* Update the error code */
764 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
765
766 /* Return error status */
767 status = HAL_ERROR;
768 }
769
770 /* Release Lock */
771 __HAL_UNLOCK(hspi);
772 return status;
773 }
774 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
775 /**
776 * @}
777 */
778
779 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
780 * @brief Data transfers functions
781 *
782 @verbatim
783 ==============================================================================
784 ##### IO operation functions #####
785 ===============================================================================
786 [..]
787 This subsection provides a set of functions allowing to manage the SPI
788 data transfers.
789
790 [..] The SPI supports master and slave mode :
791
792 (#) There are two modes of transfer:
793 (++) Blocking mode: The communication is performed in polling mode.
794 The HAL status of all data processing is returned by the same function
795 after finishing transfer.
796 (++) No-Blocking mode: The communication is performed using Interrupts
797 or DMA, These APIs return the HAL status.
798 The end of the data processing will be indicated through the
799 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
800 using DMA mode.
801 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
802 will be executed respectively at the end of the transmit or Receive process
803 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
804
805 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
806 exist for 1Line (simplex) and 2Lines (full duplex) modes.
807
808 @endverbatim
809 * @{
810 */
811
812 /**
813 * @brief Transmit an amount of data in blocking mode.
814 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
815 * the configuration information for SPI module.
816 * @param pData pointer to data buffer
817 * @param Size amount of data to be sent
818 * @param Timeout Timeout duration
819 * @retval HAL status
820 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)821 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
822 {
823 uint32_t tickstart;
824 HAL_StatusTypeDef errorcode = HAL_OK;
825 uint16_t initial_TxXferCount;
826
827 /* Check Direction parameter */
828 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
829
830 /* Process Locked */
831 __HAL_LOCK(hspi);
832
833 /* Init tickstart for timeout management*/
834 tickstart = HAL_GetTick();
835 initial_TxXferCount = Size;
836
837 if (hspi->State != HAL_SPI_STATE_READY)
838 {
839 errorcode = HAL_BUSY;
840 goto error;
841 }
842
843 if ((pData == NULL) || (Size == 0U))
844 {
845 errorcode = HAL_ERROR;
846 goto error;
847 }
848
849 /* Set the transaction information */
850 hspi->State = HAL_SPI_STATE_BUSY_TX;
851 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
852 hspi->pTxBuffPtr = (uint8_t *)pData;
853 hspi->TxXferSize = Size;
854 hspi->TxXferCount = Size;
855
856 /*Init field not used in handle to zero */
857 hspi->pRxBuffPtr = (uint8_t *)NULL;
858 hspi->RxXferSize = 0U;
859 hspi->RxXferCount = 0U;
860 hspi->TxISR = NULL;
861 hspi->RxISR = NULL;
862
863 /* Configure communication direction : 1Line */
864 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
865 {
866 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
867 __HAL_SPI_DISABLE(hspi);
868 SPI_1LINE_TX(hspi);
869 }
870
871 #if (USE_SPI_CRC != 0U)
872 /* Reset CRC Calculation */
873 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
874 {
875 SPI_RESET_CRC(hspi);
876 }
877 #endif /* USE_SPI_CRC */
878
879 /* Check if the SPI is already enabled */
880 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
881 {
882 /* Enable SPI peripheral */
883 __HAL_SPI_ENABLE(hspi);
884 }
885
886 /* Transmit data in 16 Bit mode */
887 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
888 {
889 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
890 {
891 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
892 hspi->pTxBuffPtr += sizeof(uint16_t);
893 hspi->TxXferCount--;
894 }
895 /* Transmit data in 16 Bit mode */
896 while (hspi->TxXferCount > 0U)
897 {
898 /* Wait until TXE flag is set to send data */
899 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
900 {
901 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
902 hspi->pTxBuffPtr += sizeof(uint16_t);
903 hspi->TxXferCount--;
904 }
905 else
906 {
907 /* Timeout management */
908 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
909 {
910 errorcode = HAL_TIMEOUT;
911 hspi->State = HAL_SPI_STATE_READY;
912 goto error;
913 }
914 }
915 }
916 }
917 /* Transmit data in 8 Bit mode */
918 else
919 {
920 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
921 {
922 if (hspi->TxXferCount > 1U)
923 {
924 /* write on the data register in packing mode */
925 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
926 hspi->pTxBuffPtr += sizeof(uint16_t);
927 hspi->TxXferCount -= 2U;
928 }
929 else
930 {
931 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
932 hspi->pTxBuffPtr ++;
933 hspi->TxXferCount--;
934 }
935 }
936 while (hspi->TxXferCount > 0U)
937 {
938 /* Wait until TXE flag is set to send data */
939 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
940 {
941 if (hspi->TxXferCount > 1U)
942 {
943 /* write on the data register in packing mode */
944 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
945 hspi->pTxBuffPtr += sizeof(uint16_t);
946 hspi->TxXferCount -= 2U;
947 }
948 else
949 {
950 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
951 hspi->pTxBuffPtr++;
952 hspi->TxXferCount--;
953 }
954 }
955 else
956 {
957 /* Timeout management */
958 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
959 {
960 errorcode = HAL_TIMEOUT;
961 hspi->State = HAL_SPI_STATE_READY;
962 goto error;
963 }
964 }
965 }
966 }
967 #if (USE_SPI_CRC != 0U)
968 /* Enable CRC Transmission */
969 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
970 {
971 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
972 }
973 #endif /* USE_SPI_CRC */
974
975 /* Check the end of the transaction */
976 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
977 {
978 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
979 }
980
981 /* Clear overrun flag in 2 Lines communication mode because received is not read */
982 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
983 {
984 __HAL_SPI_CLEAR_OVRFLAG(hspi);
985 }
986
987 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
988 {
989 errorcode = HAL_ERROR;
990 }
991 else
992 {
993 hspi->State = HAL_SPI_STATE_READY;
994 }
995
996 error:
997 /* Process Unlocked */
998 __HAL_UNLOCK(hspi);
999 return errorcode;
1000 }
1001
1002 /**
1003 * @brief Receive an amount of data in blocking mode.
1004 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1005 * the configuration information for SPI module.
1006 * @param pData pointer to data buffer
1007 * @param Size amount of data to be received
1008 * @param Timeout Timeout duration
1009 * @retval HAL status
1010 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)1011 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1012 {
1013 #if (USE_SPI_CRC != 0U)
1014 __IO uint32_t tmpreg = 0U;
1015 __IO uint8_t *ptmpreg8;
1016 __IO uint8_t tmpreg8 = 0;
1017 #endif /* USE_SPI_CRC */
1018 uint32_t tickstart;
1019 HAL_StatusTypeDef errorcode = HAL_OK;
1020
1021 if (hspi->State != HAL_SPI_STATE_READY)
1022 {
1023 errorcode = HAL_BUSY;
1024 goto error;
1025 }
1026
1027 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1028 {
1029 hspi->State = HAL_SPI_STATE_BUSY_RX;
1030 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1031 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1032 }
1033
1034 /* Process Locked */
1035 __HAL_LOCK(hspi);
1036
1037 /* Init tickstart for timeout management*/
1038 tickstart = HAL_GetTick();
1039
1040 if ((pData == NULL) || (Size == 0U))
1041 {
1042 errorcode = HAL_ERROR;
1043 goto error;
1044 }
1045
1046 /* Set the transaction information */
1047 hspi->State = HAL_SPI_STATE_BUSY_RX;
1048 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1049 hspi->pRxBuffPtr = (uint8_t *)pData;
1050 hspi->RxXferSize = Size;
1051 hspi->RxXferCount = Size;
1052
1053 /*Init field not used in handle to zero */
1054 hspi->pTxBuffPtr = (uint8_t *)NULL;
1055 hspi->TxXferSize = 0U;
1056 hspi->TxXferCount = 0U;
1057 hspi->RxISR = NULL;
1058 hspi->TxISR = NULL;
1059
1060 #if (USE_SPI_CRC != 0U)
1061 /* Reset CRC Calculation */
1062 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1063 {
1064 SPI_RESET_CRC(hspi);
1065 /* this is done to handle the CRCNEXT before the latest data */
1066 hspi->RxXferCount--;
1067 }
1068 #endif /* USE_SPI_CRC */
1069
1070 /* Set the Rx Fifo threshold */
1071 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1072 {
1073 /* Set RX Fifo threshold according the reception data length: 16bit */
1074 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1075 }
1076 else
1077 {
1078 /* Set RX Fifo threshold according the reception data length: 8bit */
1079 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1080 }
1081
1082 /* Configure communication direction: 1Line */
1083 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1084 {
1085 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1086 __HAL_SPI_DISABLE(hspi);
1087 SPI_1LINE_RX(hspi);
1088 }
1089
1090 /* Check if the SPI is already enabled */
1091 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1092 {
1093 /* Enable SPI peripheral */
1094 __HAL_SPI_ENABLE(hspi);
1095 }
1096
1097 /* Receive data in 8 Bit mode */
1098 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1099 {
1100 /* Transfer loop */
1101 while (hspi->RxXferCount > 0U)
1102 {
1103 /* Check the RXNE flag */
1104 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1105 {
1106 /* read the received data */
1107 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1108 hspi->pRxBuffPtr += sizeof(uint8_t);
1109 hspi->RxXferCount--;
1110 }
1111 else
1112 {
1113 /* Timeout management */
1114 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1115 {
1116 errorcode = HAL_TIMEOUT;
1117 hspi->State = HAL_SPI_STATE_READY;
1118 goto error;
1119 }
1120 }
1121 }
1122 }
1123 else
1124 {
1125 /* Transfer loop */
1126 while (hspi->RxXferCount > 0U)
1127 {
1128 /* Check the RXNE flag */
1129 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1130 {
1131 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1132 hspi->pRxBuffPtr += sizeof(uint16_t);
1133 hspi->RxXferCount--;
1134 }
1135 else
1136 {
1137 /* Timeout management */
1138 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1139 {
1140 errorcode = HAL_TIMEOUT;
1141 hspi->State = HAL_SPI_STATE_READY;
1142 goto error;
1143 }
1144 }
1145 }
1146 }
1147
1148 #if (USE_SPI_CRC != 0U)
1149 /* Handle the CRC Transmission */
1150 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1151 {
1152 /* freeze the CRC before the latest data */
1153 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1154
1155 /* Read the latest data */
1156 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1157 {
1158 /* the latest data has not been received */
1159 errorcode = HAL_TIMEOUT;
1160 goto error;
1161 }
1162
1163 /* Receive last data in 16 Bit mode */
1164 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1165 {
1166 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1167 }
1168 /* Receive last data in 8 Bit mode */
1169 else
1170 {
1171 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1172 }
1173
1174 /* Wait the CRC data */
1175 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1176 {
1177 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1178 errorcode = HAL_TIMEOUT;
1179 goto error;
1180 }
1181
1182 /* Read CRC to Flush DR and RXNE flag */
1183 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1184 {
1185 /* Read 16bit CRC */
1186 tmpreg = READ_REG(hspi->Instance->DR);
1187 /* To avoid GCC warning */
1188 UNUSED(tmpreg);
1189 }
1190 else
1191 {
1192 /* Initialize the 8bit temporary pointer */
1193 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1194 /* Read 8bit CRC */
1195 tmpreg8 = *ptmpreg8;
1196 /* To avoid GCC warning */
1197 UNUSED(tmpreg8);
1198
1199 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1200 {
1201 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1202 {
1203 /* Error on the CRC reception */
1204 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1205 errorcode = HAL_TIMEOUT;
1206 goto error;
1207 }
1208 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1209 tmpreg8 = *ptmpreg8;
1210 /* To avoid GCC warning */
1211 UNUSED(tmpreg8);
1212 }
1213 }
1214 }
1215 #endif /* USE_SPI_CRC */
1216
1217 /* Check the end of the transaction */
1218 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1219 {
1220 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1221 }
1222
1223 #if (USE_SPI_CRC != 0U)
1224 /* Check if CRC error occurred */
1225 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1226 {
1227 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1228 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1229 }
1230 #endif /* USE_SPI_CRC */
1231
1232 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1233 {
1234 errorcode = HAL_ERROR;
1235 }
1236 else
1237 {
1238 hspi->State = HAL_SPI_STATE_READY;
1239 }
1240
1241 error :
1242 __HAL_UNLOCK(hspi);
1243 return errorcode;
1244 }
1245
1246 /**
1247 * @brief Transmit and Receive an amount of data in blocking mode.
1248 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1249 * the configuration information for SPI module.
1250 * @param pTxData pointer to transmission data buffer
1251 * @param pRxData pointer to reception data buffer
1252 * @param Size amount of data to be sent and received
1253 * @param Timeout Timeout duration
1254 * @retval HAL status
1255 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1256 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1257 uint32_t Timeout)
1258 {
1259 uint16_t initial_TxXferCount;
1260 uint16_t initial_RxXferCount;
1261 uint32_t tmp_mode;
1262 HAL_SPI_StateTypeDef tmp_state;
1263 uint32_t tickstart;
1264 #if (USE_SPI_CRC != 0U)
1265 __IO uint32_t tmpreg = 0U;
1266 uint32_t spi_cr1;
1267 uint32_t spi_cr2;
1268 __IO uint8_t *ptmpreg8;
1269 __IO uint8_t tmpreg8 = 0;
1270 #endif /* USE_SPI_CRC */
1271
1272 /* Variable used to alternate Rx and Tx during transfer */
1273 uint32_t txallowed = 1U;
1274 HAL_StatusTypeDef errorcode = HAL_OK;
1275
1276 /* Check Direction parameter */
1277 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1278
1279 /* Process Locked */
1280 __HAL_LOCK(hspi);
1281
1282 /* Init tickstart for timeout management*/
1283 tickstart = HAL_GetTick();
1284
1285 /* Init temporary variables */
1286 tmp_state = hspi->State;
1287 tmp_mode = hspi->Init.Mode;
1288 initial_TxXferCount = Size;
1289 initial_RxXferCount = Size;
1290 #if (USE_SPI_CRC != 0U)
1291 spi_cr1 = READ_REG(hspi->Instance->CR1);
1292 spi_cr2 = READ_REG(hspi->Instance->CR2);
1293 #endif /* USE_SPI_CRC */
1294
1295 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1296 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1297 {
1298 errorcode = HAL_BUSY;
1299 goto error;
1300 }
1301
1302 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1303 {
1304 errorcode = HAL_ERROR;
1305 goto error;
1306 }
1307
1308 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1309 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1310 {
1311 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1312 }
1313
1314 /* Set the transaction information */
1315 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1316 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1317 hspi->RxXferCount = Size;
1318 hspi->RxXferSize = Size;
1319 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1320 hspi->TxXferCount = Size;
1321 hspi->TxXferSize = Size;
1322
1323 /*Init field not used in handle to zero */
1324 hspi->RxISR = NULL;
1325 hspi->TxISR = NULL;
1326
1327 #if (USE_SPI_CRC != 0U)
1328 /* Reset CRC Calculation */
1329 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1330 {
1331 SPI_RESET_CRC(hspi);
1332 }
1333 #endif /* USE_SPI_CRC */
1334
1335 /* Set the Rx Fifo threshold */
1336 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1337 {
1338 /* Set fiforxthreshold according the reception data length: 16bit */
1339 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1340 }
1341 else
1342 {
1343 /* Set fiforxthreshold according the reception data length: 8bit */
1344 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1345 }
1346
1347 /* Check if the SPI is already enabled */
1348 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1349 {
1350 /* Enable SPI peripheral */
1351 __HAL_SPI_ENABLE(hspi);
1352 }
1353
1354 /* Transmit and Receive data in 16 Bit mode */
1355 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1356 {
1357 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1358 {
1359 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1360 hspi->pTxBuffPtr += sizeof(uint16_t);
1361 hspi->TxXferCount--;
1362 }
1363 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1364 {
1365 /* Check TXE flag */
1366 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1367 {
1368 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1369 hspi->pTxBuffPtr += sizeof(uint16_t);
1370 hspi->TxXferCount--;
1371 /* Next Data is a reception (Rx). Tx not allowed */
1372 txallowed = 0U;
1373
1374 #if (USE_SPI_CRC != 0U)
1375 /* Enable CRC Transmission */
1376 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1377 {
1378 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1379 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1380 {
1381 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1382 }
1383 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1384 }
1385 #endif /* USE_SPI_CRC */
1386 }
1387
1388 /* Check RXNE flag */
1389 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1390 {
1391 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1392 hspi->pRxBuffPtr += sizeof(uint16_t);
1393 hspi->RxXferCount--;
1394 /* Next Data is a Transmission (Tx). Tx is allowed */
1395 txallowed = 1U;
1396 }
1397 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1398 {
1399 errorcode = HAL_TIMEOUT;
1400 hspi->State = HAL_SPI_STATE_READY;
1401 goto error;
1402 }
1403 }
1404 }
1405 /* Transmit and Receive data in 8 Bit mode */
1406 else
1407 {
1408 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1409 {
1410 if (hspi->TxXferCount > 1U)
1411 {
1412 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1413 hspi->pTxBuffPtr += sizeof(uint16_t);
1414 hspi->TxXferCount -= 2U;
1415 }
1416 else
1417 {
1418 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1419 hspi->pTxBuffPtr++;
1420 hspi->TxXferCount--;
1421 }
1422 }
1423 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1424 {
1425 /* Check TXE flag */
1426 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1427 {
1428 if (hspi->TxXferCount > 1U)
1429 {
1430 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1431 hspi->pTxBuffPtr += sizeof(uint16_t);
1432 hspi->TxXferCount -= 2U;
1433 }
1434 else
1435 {
1436 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1437 hspi->pTxBuffPtr++;
1438 hspi->TxXferCount--;
1439 }
1440 /* Next Data is a reception (Rx). Tx not allowed */
1441 txallowed = 0U;
1442
1443 #if (USE_SPI_CRC != 0U)
1444 /* Enable CRC Transmission */
1445 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1446 {
1447 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1448 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1449 {
1450 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1451 }
1452 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1453 }
1454 #endif /* USE_SPI_CRC */
1455 }
1456
1457 /* Wait until RXNE flag is reset */
1458 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1459 {
1460 if (hspi->RxXferCount > 1U)
1461 {
1462 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1463 hspi->pRxBuffPtr += sizeof(uint16_t);
1464 hspi->RxXferCount -= 2U;
1465 if (hspi->RxXferCount <= 1U)
1466 {
1467 /* Set RX Fifo threshold before to switch on 8 bit data size */
1468 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1469 }
1470 }
1471 else
1472 {
1473 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1474 hspi->pRxBuffPtr++;
1475 hspi->RxXferCount--;
1476 }
1477 /* Next Data is a Transmission (Tx). Tx is allowed */
1478 txallowed = 1U;
1479 }
1480 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1481 {
1482 errorcode = HAL_TIMEOUT;
1483 hspi->State = HAL_SPI_STATE_READY;
1484 goto error;
1485 }
1486 }
1487 }
1488
1489 #if (USE_SPI_CRC != 0U)
1490 /* Read CRC from DR to close CRC calculation process */
1491 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1492 {
1493 /* Wait until TXE flag */
1494 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1495 {
1496 /* Error on the CRC reception */
1497 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1498 errorcode = HAL_TIMEOUT;
1499 goto error;
1500 }
1501 /* Read CRC */
1502 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1503 {
1504 /* Read 16bit CRC */
1505 tmpreg = READ_REG(hspi->Instance->DR);
1506 /* To avoid GCC warning */
1507 UNUSED(tmpreg);
1508 }
1509 else
1510 {
1511 /* Initialize the 8bit temporary pointer */
1512 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1513 /* Read 8bit CRC */
1514 tmpreg8 = *ptmpreg8;
1515 /* To avoid GCC warning */
1516 UNUSED(tmpreg8);
1517
1518 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1519 {
1520 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1521 {
1522 /* Error on the CRC reception */
1523 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1524 errorcode = HAL_TIMEOUT;
1525 goto error;
1526 }
1527 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1528 tmpreg8 = *ptmpreg8;
1529 /* To avoid GCC warning */
1530 UNUSED(tmpreg8);
1531 }
1532 }
1533 }
1534
1535 /* Check if CRC error occurred */
1536 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1537 {
1538 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1539 /* Clear CRC Flag */
1540 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1541
1542 errorcode = HAL_ERROR;
1543 }
1544 #endif /* USE_SPI_CRC */
1545
1546 /* Check the end of the transaction */
1547 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1548 {
1549 errorcode = HAL_ERROR;
1550 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1551 }
1552
1553 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1554 {
1555 errorcode = HAL_ERROR;
1556 }
1557 else
1558 {
1559 hspi->State = HAL_SPI_STATE_READY;
1560 }
1561
1562 error :
1563 __HAL_UNLOCK(hspi);
1564 return errorcode;
1565 }
1566
1567 /**
1568 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1569 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1570 * the configuration information for SPI module.
1571 * @param pData pointer to data buffer
1572 * @param Size amount of data to be sent
1573 * @retval HAL status
1574 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1575 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1576 {
1577 HAL_StatusTypeDef errorcode = HAL_OK;
1578
1579 /* Check Direction parameter */
1580 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1581
1582 /* Process Locked */
1583 __HAL_LOCK(hspi);
1584
1585 if ((pData == NULL) || (Size == 0U))
1586 {
1587 errorcode = HAL_ERROR;
1588 goto error;
1589 }
1590
1591 if (hspi->State != HAL_SPI_STATE_READY)
1592 {
1593 errorcode = HAL_BUSY;
1594 goto error;
1595 }
1596
1597 /* Set the transaction information */
1598 hspi->State = HAL_SPI_STATE_BUSY_TX;
1599 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1600 hspi->pTxBuffPtr = (uint8_t *)pData;
1601 hspi->TxXferSize = Size;
1602 hspi->TxXferCount = Size;
1603
1604 /* Init field not used in handle to zero */
1605 hspi->pRxBuffPtr = (uint8_t *)NULL;
1606 hspi->RxXferSize = 0U;
1607 hspi->RxXferCount = 0U;
1608 hspi->RxISR = NULL;
1609
1610 /* Set the function for IT treatment */
1611 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1612 {
1613 hspi->TxISR = SPI_TxISR_16BIT;
1614 }
1615 else
1616 {
1617 hspi->TxISR = SPI_TxISR_8BIT;
1618 }
1619
1620 /* Configure communication direction : 1Line */
1621 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1622 {
1623 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1624 __HAL_SPI_DISABLE(hspi);
1625 SPI_1LINE_TX(hspi);
1626 }
1627
1628 #if (USE_SPI_CRC != 0U)
1629 /* Reset CRC Calculation */
1630 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1631 {
1632 SPI_RESET_CRC(hspi);
1633 }
1634 #endif /* USE_SPI_CRC */
1635
1636 /* Enable TXE and ERR interrupt */
1637 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1638
1639
1640 /* Check if the SPI is already enabled */
1641 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1642 {
1643 /* Enable SPI peripheral */
1644 __HAL_SPI_ENABLE(hspi);
1645 }
1646
1647 error :
1648 __HAL_UNLOCK(hspi);
1649 return errorcode;
1650 }
1651
1652 /**
1653 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1654 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1655 * the configuration information for SPI module.
1656 * @param pData pointer to data buffer
1657 * @param Size amount of data to be sent
1658 * @retval HAL status
1659 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1660 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1661 {
1662 HAL_StatusTypeDef errorcode = HAL_OK;
1663
1664
1665 if (hspi->State != HAL_SPI_STATE_READY)
1666 {
1667 errorcode = HAL_BUSY;
1668 goto error;
1669 }
1670
1671 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1672 {
1673 hspi->State = HAL_SPI_STATE_BUSY_RX;
1674 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1675 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1676 }
1677
1678 /* Process Locked */
1679 __HAL_LOCK(hspi);
1680
1681 if ((pData == NULL) || (Size == 0U))
1682 {
1683 errorcode = HAL_ERROR;
1684 goto error;
1685 }
1686
1687 /* Set the transaction information */
1688 hspi->State = HAL_SPI_STATE_BUSY_RX;
1689 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1690 hspi->pRxBuffPtr = (uint8_t *)pData;
1691 hspi->RxXferSize = Size;
1692 hspi->RxXferCount = Size;
1693
1694 /* Init field not used in handle to zero */
1695 hspi->pTxBuffPtr = (uint8_t *)NULL;
1696 hspi->TxXferSize = 0U;
1697 hspi->TxXferCount = 0U;
1698 hspi->TxISR = NULL;
1699
1700 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1701 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1702 {
1703 /* Set RX Fifo threshold according the reception data length: 16 bit */
1704 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1705 hspi->RxISR = SPI_RxISR_16BIT;
1706 }
1707 else
1708 {
1709 /* Set RX Fifo threshold according the reception data length: 8 bit */
1710 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1711 hspi->RxISR = SPI_RxISR_8BIT;
1712 }
1713
1714 /* Configure communication direction : 1Line */
1715 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1716 {
1717 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1718 __HAL_SPI_DISABLE(hspi);
1719 SPI_1LINE_RX(hspi);
1720 }
1721
1722 #if (USE_SPI_CRC != 0U)
1723 /* Reset CRC Calculation */
1724 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1725 {
1726 hspi->CRCSize = 1U;
1727 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1728 {
1729 hspi->CRCSize = 2U;
1730 }
1731 SPI_RESET_CRC(hspi);
1732 }
1733 else
1734 {
1735 hspi->CRCSize = 0U;
1736 }
1737 #endif /* USE_SPI_CRC */
1738
1739 /* Enable TXE and ERR interrupt */
1740 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1741
1742 /* Note : The SPI must be enabled after unlocking current process
1743 to avoid the risk of SPI interrupt handle execution before current
1744 process unlock */
1745
1746 /* Check if the SPI is already enabled */
1747 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1748 {
1749 /* Enable SPI peripheral */
1750 __HAL_SPI_ENABLE(hspi);
1751 }
1752
1753 error :
1754 /* Process Unlocked */
1755 __HAL_UNLOCK(hspi);
1756 return errorcode;
1757 }
1758
1759 /**
1760 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1761 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1762 * the configuration information for SPI module.
1763 * @param pTxData pointer to transmission data buffer
1764 * @param pRxData pointer to reception data buffer
1765 * @param Size amount of data to be sent and received
1766 * @retval HAL status
1767 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1768 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1769 {
1770 uint32_t tmp_mode;
1771 HAL_SPI_StateTypeDef tmp_state;
1772 HAL_StatusTypeDef errorcode = HAL_OK;
1773
1774 /* Check Direction parameter */
1775 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1776
1777 /* Process locked */
1778 __HAL_LOCK(hspi);
1779
1780 /* Init temporary variables */
1781 tmp_state = hspi->State;
1782 tmp_mode = hspi->Init.Mode;
1783
1784 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1785 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1786 {
1787 errorcode = HAL_BUSY;
1788 goto error;
1789 }
1790
1791 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1792 {
1793 errorcode = HAL_ERROR;
1794 goto error;
1795 }
1796
1797 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1798 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1799 {
1800 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1801 }
1802
1803 /* Set the transaction information */
1804 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1805 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1806 hspi->TxXferSize = Size;
1807 hspi->TxXferCount = Size;
1808 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1809 hspi->RxXferSize = Size;
1810 hspi->RxXferCount = Size;
1811
1812 /* Set the function for IT treatment */
1813 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1814 {
1815 hspi->RxISR = SPI_2linesRxISR_16BIT;
1816 hspi->TxISR = SPI_2linesTxISR_16BIT;
1817 }
1818 else
1819 {
1820 hspi->RxISR = SPI_2linesRxISR_8BIT;
1821 hspi->TxISR = SPI_2linesTxISR_8BIT;
1822 }
1823
1824 #if (USE_SPI_CRC != 0U)
1825 /* Reset CRC Calculation */
1826 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1827 {
1828 hspi->CRCSize = 1U;
1829 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1830 {
1831 hspi->CRCSize = 2U;
1832 }
1833 SPI_RESET_CRC(hspi);
1834 }
1835 else
1836 {
1837 hspi->CRCSize = 0U;
1838 }
1839 #endif /* USE_SPI_CRC */
1840
1841 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1842 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1843 {
1844 /* Set RX Fifo threshold according the reception data length: 16 bit */
1845 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1846 }
1847 else
1848 {
1849 /* Set RX Fifo threshold according the reception data length: 8 bit */
1850 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1851 }
1852
1853 /* Enable TXE, RXNE and ERR interrupt */
1854 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1855
1856 /* Check if the SPI is already enabled */
1857 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1858 {
1859 /* Enable SPI peripheral */
1860 __HAL_SPI_ENABLE(hspi);
1861 }
1862
1863 error :
1864 /* Process Unlocked */
1865 __HAL_UNLOCK(hspi);
1866 return errorcode;
1867 }
1868
1869 /**
1870 * @brief Transmit an amount of data in non-blocking mode with DMA.
1871 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1872 * the configuration information for SPI module.
1873 * @param pData pointer to data buffer
1874 * @param Size amount of data to be sent
1875 * @retval HAL status
1876 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1877 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1878 {
1879 HAL_StatusTypeDef errorcode = HAL_OK;
1880
1881 /* Check tx dma handle */
1882 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1883
1884 /* Check Direction parameter */
1885 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1886
1887 /* Process Locked */
1888 __HAL_LOCK(hspi);
1889
1890 if (hspi->State != HAL_SPI_STATE_READY)
1891 {
1892 errorcode = HAL_BUSY;
1893 goto error;
1894 }
1895
1896 if ((pData == NULL) || (Size == 0U))
1897 {
1898 errorcode = HAL_ERROR;
1899 goto error;
1900 }
1901
1902 /* Set the transaction information */
1903 hspi->State = HAL_SPI_STATE_BUSY_TX;
1904 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1905 hspi->pTxBuffPtr = (uint8_t *)pData;
1906 hspi->TxXferSize = Size;
1907 hspi->TxXferCount = Size;
1908
1909 /* Init field not used in handle to zero */
1910 hspi->pRxBuffPtr = (uint8_t *)NULL;
1911 hspi->TxISR = NULL;
1912 hspi->RxISR = NULL;
1913 hspi->RxXferSize = 0U;
1914 hspi->RxXferCount = 0U;
1915
1916 /* Configure communication direction : 1Line */
1917 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1918 {
1919 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1920 __HAL_SPI_DISABLE(hspi);
1921 SPI_1LINE_TX(hspi);
1922 }
1923
1924 #if (USE_SPI_CRC != 0U)
1925 /* Reset CRC Calculation */
1926 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1927 {
1928 SPI_RESET_CRC(hspi);
1929 }
1930 #endif /* USE_SPI_CRC */
1931
1932 /* Set the SPI TxDMA Half transfer complete callback */
1933 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1934
1935 /* Set the SPI TxDMA transfer complete callback */
1936 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1937
1938 /* Set the DMA error callback */
1939 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1940
1941 /* Set the DMA AbortCpltCallback */
1942 hspi->hdmatx->XferAbortCallback = NULL;
1943
1944 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1945 /* Packing mode is enabled only if the DMA setting is HALWORD */
1946 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1947 {
1948 /* Check the even/odd of the data size + crc if enabled */
1949 if ((hspi->TxXferCount & 0x1U) == 0U)
1950 {
1951 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1952 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1953 }
1954 else
1955 {
1956 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1957 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1958 }
1959 }
1960
1961 /* Enable the Tx DMA Stream/Channel */
1962 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1963 hspi->TxXferCount))
1964 {
1965 /* Update SPI error code */
1966 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1967 errorcode = HAL_ERROR;
1968
1969 goto error;
1970 }
1971
1972 /* Check if the SPI is already enabled */
1973 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1974 {
1975 /* Enable SPI peripheral */
1976 __HAL_SPI_ENABLE(hspi);
1977 }
1978
1979 /* Enable the SPI Error Interrupt Bit */
1980 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1981
1982 /* Enable Tx DMA Request */
1983 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1984
1985 error :
1986 /* Process Unlocked */
1987 __HAL_UNLOCK(hspi);
1988 return errorcode;
1989 }
1990
1991 /**
1992 * @brief Receive an amount of data in non-blocking mode with DMA.
1993 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1994 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1995 * the configuration information for SPI module.
1996 * @param pData pointer to data buffer
1997 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1998 * @param Size amount of data to be sent
1999 * @retval HAL status
2000 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)2001 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
2002 {
2003 HAL_StatusTypeDef errorcode = HAL_OK;
2004
2005 /* Check rx dma handle */
2006 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2007
2008 if (hspi->State != HAL_SPI_STATE_READY)
2009 {
2010 errorcode = HAL_BUSY;
2011 goto error;
2012 }
2013
2014 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
2015 {
2016 hspi->State = HAL_SPI_STATE_BUSY_RX;
2017
2018 /* Check tx dma handle */
2019 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2020
2021 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
2022 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
2023 }
2024
2025 /* Process Locked */
2026 __HAL_LOCK(hspi);
2027
2028 if ((pData == NULL) || (Size == 0U))
2029 {
2030 errorcode = HAL_ERROR;
2031 goto error;
2032 }
2033
2034 /* Set the transaction information */
2035 hspi->State = HAL_SPI_STATE_BUSY_RX;
2036 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2037 hspi->pRxBuffPtr = (uint8_t *)pData;
2038 hspi->RxXferSize = Size;
2039 hspi->RxXferCount = Size;
2040
2041 /*Init field not used in handle to zero */
2042 hspi->RxISR = NULL;
2043 hspi->TxISR = NULL;
2044 hspi->TxXferSize = 0U;
2045 hspi->TxXferCount = 0U;
2046
2047 /* Configure communication direction : 1Line */
2048 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2049 {
2050 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
2051 __HAL_SPI_DISABLE(hspi);
2052 SPI_1LINE_RX(hspi);
2053 }
2054
2055 #if (USE_SPI_CRC != 0U)
2056 /* Reset CRC Calculation */
2057 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2058 {
2059 SPI_RESET_CRC(hspi);
2060 }
2061 #endif /* USE_SPI_CRC */
2062
2063 #if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
2064 /* Packing mode management is enabled by the DMA settings */
2065 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
2066 {
2067 /* Restriction the DMA data received is not allowed in this mode */
2068 errorcode = HAL_ERROR;
2069 goto error;
2070 }
2071 #endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */
2072
2073 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2074 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2075 {
2076 /* Set RX Fifo threshold according the reception data length: 16bit */
2077 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2078 }
2079 else
2080 {
2081 /* Set RX Fifo threshold according the reception data length: 8bit */
2082 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2083
2084 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2085 {
2086 /* Set RX Fifo threshold according the reception data length: 16bit */
2087 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2088
2089 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2090 {
2091 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2092 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2093 }
2094 else
2095 {
2096 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2097 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2098 }
2099 }
2100 }
2101
2102 /* Set the SPI RxDMA Half transfer complete callback */
2103 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2104
2105 /* Set the SPI Rx DMA transfer complete callback */
2106 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2107
2108 /* Set the DMA error callback */
2109 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2110
2111 /* Set the DMA AbortCpltCallback */
2112 hspi->hdmarx->XferAbortCallback = NULL;
2113
2114 /* Enable the Rx DMA Stream/Channel */
2115 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2116 hspi->RxXferCount))
2117 {
2118 /* Update SPI error code */
2119 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2120 errorcode = HAL_ERROR;
2121
2122 goto error;
2123 }
2124
2125 /* Check if the SPI is already enabled */
2126 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2127 {
2128 /* Enable SPI peripheral */
2129 __HAL_SPI_ENABLE(hspi);
2130 }
2131
2132 /* Enable the SPI Error Interrupt Bit */
2133 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2134
2135 /* Enable Rx DMA Request */
2136 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2137
2138 error:
2139 /* Process Unlocked */
2140 __HAL_UNLOCK(hspi);
2141 return errorcode;
2142 }
2143
2144 /**
2145 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2146 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2147 * the configuration information for SPI module.
2148 * @param pTxData pointer to transmission data buffer
2149 * @param pRxData pointer to reception data buffer
2150 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2151 * @param Size amount of data to be sent
2152 * @retval HAL status
2153 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2154 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2155 uint16_t Size)
2156 {
2157 uint32_t tmp_mode;
2158 HAL_SPI_StateTypeDef tmp_state;
2159 HAL_StatusTypeDef errorcode = HAL_OK;
2160
2161 /* Check rx & tx dma handles */
2162 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2163 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2164
2165 /* Check Direction parameter */
2166 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2167
2168 /* Process locked */
2169 __HAL_LOCK(hspi);
2170
2171 /* Init temporary variables */
2172 tmp_state = hspi->State;
2173 tmp_mode = hspi->Init.Mode;
2174
2175 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2176 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2177 {
2178 errorcode = HAL_BUSY;
2179 goto error;
2180 }
2181
2182 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2183 {
2184 errorcode = HAL_ERROR;
2185 goto error;
2186 }
2187
2188 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2189 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2190 {
2191 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2192 }
2193
2194 /* Set the transaction information */
2195 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2196 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2197 hspi->TxXferSize = Size;
2198 hspi->TxXferCount = Size;
2199 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2200 hspi->RxXferSize = Size;
2201 hspi->RxXferCount = Size;
2202
2203 /* Init field not used in handle to zero */
2204 hspi->RxISR = NULL;
2205 hspi->TxISR = NULL;
2206
2207 #if (USE_SPI_CRC != 0U)
2208 /* Reset CRC Calculation */
2209 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2210 {
2211 SPI_RESET_CRC(hspi);
2212 }
2213 #endif /* USE_SPI_CRC */
2214
2215 #if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
2216 /* Packing mode management is enabled by the DMA settings */
2217 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
2218 {
2219 /* Restriction the DMA data received is not allowed in this mode */
2220 errorcode = HAL_ERROR;
2221 goto error;
2222 }
2223 #endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */
2224
2225 /* Reset the threshold bit */
2226 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2227
2228 /* The packing mode management is enabled by the DMA settings according the spi data size */
2229 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2230 {
2231 /* Set fiforxthreshold according the reception data length: 16bit */
2232 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2233 }
2234 else
2235 {
2236 /* Set RX Fifo threshold according the reception data length: 8bit */
2237 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2238
2239 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2240 {
2241 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2242 {
2243 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2244 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2245 }
2246 else
2247 {
2248 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2249 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2250 }
2251 }
2252
2253 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2254 {
2255 /* Set RX Fifo threshold according the reception data length: 16bit */
2256 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2257
2258 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2259 {
2260 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2261 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2262 }
2263 else
2264 {
2265 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2266 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2267 }
2268 }
2269 }
2270
2271 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2272 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2273 {
2274 /* Set the SPI Rx DMA Half transfer complete callback */
2275 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2276 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2277 }
2278 else
2279 {
2280 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2281 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2282 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2283 }
2284
2285 /* Set the DMA error callback */
2286 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2287
2288 /* Set the DMA AbortCpltCallback */
2289 hspi->hdmarx->XferAbortCallback = NULL;
2290
2291 /* Enable the Rx DMA Stream/Channel */
2292 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2293 hspi->RxXferCount))
2294 {
2295 /* Update SPI error code */
2296 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2297 errorcode = HAL_ERROR;
2298
2299 goto error;
2300 }
2301
2302 /* Enable Rx DMA Request */
2303 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2304
2305 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2306 is performed in DMA reception complete callback */
2307 hspi->hdmatx->XferHalfCpltCallback = NULL;
2308 hspi->hdmatx->XferCpltCallback = NULL;
2309 hspi->hdmatx->XferErrorCallback = NULL;
2310 hspi->hdmatx->XferAbortCallback = NULL;
2311
2312 /* Enable the Tx DMA Stream/Channel */
2313 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2314 hspi->TxXferCount))
2315 {
2316 /* Update SPI error code */
2317 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2318 errorcode = HAL_ERROR;
2319
2320 goto error;
2321 }
2322
2323 /* Check if the SPI is already enabled */
2324 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2325 {
2326 /* Enable SPI peripheral */
2327 __HAL_SPI_ENABLE(hspi);
2328 }
2329 /* Enable the SPI Error Interrupt Bit */
2330 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2331
2332 /* Enable Tx DMA Request */
2333 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2334
2335 error :
2336 /* Process Unlocked */
2337 __HAL_UNLOCK(hspi);
2338 return errorcode;
2339 }
2340
2341 /**
2342 * @brief Abort ongoing transfer (blocking mode).
2343 * @param hspi SPI handle.
2344 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2345 * started in Interrupt or DMA mode.
2346 * This procedure performs following operations :
2347 * - Disable SPI Interrupts (depending of transfer direction)
2348 * - Disable the DMA transfer in the peripheral register (if enabled)
2349 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2350 * - Set handle State to READY
2351 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2352 * @retval HAL status
2353 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2354 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2355 {
2356 HAL_StatusTypeDef errorcode;
2357 __IO uint32_t count;
2358 __IO uint32_t resetcount;
2359
2360 /* Initialized local variable */
2361 errorcode = HAL_OK;
2362 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2363 count = resetcount;
2364
2365 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2366 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2367
2368 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2369 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2370 {
2371 hspi->TxISR = SPI_AbortTx_ISR;
2372 /* Wait HAL_SPI_STATE_ABORT state */
2373 do
2374 {
2375 if (count == 0U)
2376 {
2377 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2378 break;
2379 }
2380 count--;
2381 } while (hspi->State != HAL_SPI_STATE_ABORT);
2382 /* Reset Timeout Counter */
2383 count = resetcount;
2384 }
2385
2386 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2387 {
2388 hspi->RxISR = SPI_AbortRx_ISR;
2389 /* Wait HAL_SPI_STATE_ABORT state */
2390 do
2391 {
2392 if (count == 0U)
2393 {
2394 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2395 break;
2396 }
2397 count--;
2398 } while (hspi->State != HAL_SPI_STATE_ABORT);
2399 /* Reset Timeout Counter */
2400 count = resetcount;
2401 }
2402
2403 /* Disable the SPI DMA Tx request if enabled */
2404 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2405 {
2406 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2407 if (hspi->hdmatx != NULL)
2408 {
2409 /* Set the SPI DMA Abort callback :
2410 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2411 hspi->hdmatx->XferAbortCallback = NULL;
2412
2413 /* Abort DMA Tx Handle linked to SPI Peripheral */
2414 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2415 {
2416 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2417 }
2418
2419 /* Disable Tx DMA Request */
2420 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2421
2422 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2423 {
2424 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2425 }
2426
2427 /* Disable SPI Peripheral */
2428 __HAL_SPI_DISABLE(hspi);
2429
2430 /* Empty the FRLVL fifo */
2431 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2432 {
2433 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2434 }
2435 }
2436 }
2437
2438 /* Disable the SPI DMA Rx request if enabled */
2439 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2440 {
2441 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2442 if (hspi->hdmarx != NULL)
2443 {
2444 /* Set the SPI DMA Abort callback :
2445 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2446 hspi->hdmarx->XferAbortCallback = NULL;
2447
2448 /* Abort DMA Rx Handle linked to SPI Peripheral */
2449 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2450 {
2451 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2452 }
2453
2454 /* Disable peripheral */
2455 __HAL_SPI_DISABLE(hspi);
2456
2457 /* Control the BSY flag */
2458 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2459 {
2460 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2461 }
2462
2463 /* Empty the FRLVL fifo */
2464 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2465 {
2466 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2467 }
2468
2469 /* Disable Rx DMA Request */
2470 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2471 }
2472 }
2473 /* Reset Tx and Rx transfer counters */
2474 hspi->RxXferCount = 0U;
2475 hspi->TxXferCount = 0U;
2476
2477 /* Check error during Abort procedure */
2478 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2479 {
2480 /* return HAL_Error in case of error during Abort procedure */
2481 errorcode = HAL_ERROR;
2482 }
2483 else
2484 {
2485 /* Reset errorCode */
2486 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2487 }
2488
2489 /* Clear the Error flags in the SR register */
2490 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2491 __HAL_SPI_CLEAR_FREFLAG(hspi);
2492
2493 /* Restore hspi->state to ready */
2494 hspi->State = HAL_SPI_STATE_READY;
2495
2496 return errorcode;
2497 }
2498
2499 /**
2500 * @brief Abort ongoing transfer (Interrupt mode).
2501 * @param hspi SPI handle.
2502 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2503 * started in Interrupt or DMA mode.
2504 * This procedure performs following operations :
2505 * - Disable SPI Interrupts (depending of transfer direction)
2506 * - Disable the DMA transfer in the peripheral register (if enabled)
2507 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2508 * - Set handle State to READY
2509 * - At abort completion, call user abort complete callback
2510 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2511 * considered as completed only when user abort complete callback is executed (not when exiting function).
2512 * @retval HAL status
2513 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2514 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2515 {
2516 HAL_StatusTypeDef errorcode;
2517 uint32_t abortcplt ;
2518 __IO uint32_t count;
2519 __IO uint32_t resetcount;
2520
2521 /* Initialized local variable */
2522 errorcode = HAL_OK;
2523 abortcplt = 1U;
2524 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2525 count = resetcount;
2526
2527 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2528 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2529
2530 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2531 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2532 {
2533 hspi->TxISR = SPI_AbortTx_ISR;
2534 /* Wait HAL_SPI_STATE_ABORT state */
2535 do
2536 {
2537 if (count == 0U)
2538 {
2539 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2540 break;
2541 }
2542 count--;
2543 } while (hspi->State != HAL_SPI_STATE_ABORT);
2544 /* Reset Timeout Counter */
2545 count = resetcount;
2546 }
2547
2548 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2549 {
2550 hspi->RxISR = SPI_AbortRx_ISR;
2551 /* Wait HAL_SPI_STATE_ABORT state */
2552 do
2553 {
2554 if (count == 0U)
2555 {
2556 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2557 break;
2558 }
2559 count--;
2560 } while (hspi->State != HAL_SPI_STATE_ABORT);
2561 /* Reset Timeout Counter */
2562 count = resetcount;
2563 }
2564
2565 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2566 before any call to DMA Abort functions */
2567 /* DMA Tx Handle is valid */
2568 if (hspi->hdmatx != NULL)
2569 {
2570 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2571 Otherwise, set it to NULL */
2572 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2573 {
2574 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2575 }
2576 else
2577 {
2578 hspi->hdmatx->XferAbortCallback = NULL;
2579 }
2580 }
2581 /* DMA Rx Handle is valid */
2582 if (hspi->hdmarx != NULL)
2583 {
2584 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2585 Otherwise, set it to NULL */
2586 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2587 {
2588 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2589 }
2590 else
2591 {
2592 hspi->hdmarx->XferAbortCallback = NULL;
2593 }
2594 }
2595
2596 /* Disable the SPI DMA Tx request if enabled */
2597 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2598 {
2599 /* Abort the SPI DMA Tx Stream/Channel */
2600 if (hspi->hdmatx != NULL)
2601 {
2602 /* Abort DMA Tx Handle linked to SPI Peripheral */
2603 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2604 {
2605 hspi->hdmatx->XferAbortCallback = NULL;
2606 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2607 }
2608 else
2609 {
2610 abortcplt = 0U;
2611 }
2612 }
2613 }
2614 /* Disable the SPI DMA Rx request if enabled */
2615 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2616 {
2617 /* Abort the SPI DMA Rx Stream/Channel */
2618 if (hspi->hdmarx != NULL)
2619 {
2620 /* Abort DMA Rx Handle linked to SPI Peripheral */
2621 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2622 {
2623 hspi->hdmarx->XferAbortCallback = NULL;
2624 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2625 }
2626 else
2627 {
2628 abortcplt = 0U;
2629 }
2630 }
2631 }
2632
2633 if (abortcplt == 1U)
2634 {
2635 /* Reset Tx and Rx transfer counters */
2636 hspi->RxXferCount = 0U;
2637 hspi->TxXferCount = 0U;
2638
2639 /* Check error during Abort procedure */
2640 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2641 {
2642 /* return HAL_Error in case of error during Abort procedure */
2643 errorcode = HAL_ERROR;
2644 }
2645 else
2646 {
2647 /* Reset errorCode */
2648 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2649 }
2650
2651 /* Clear the Error flags in the SR register */
2652 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2653 __HAL_SPI_CLEAR_FREFLAG(hspi);
2654
2655 /* Restore hspi->State to Ready */
2656 hspi->State = HAL_SPI_STATE_READY;
2657
2658 /* As no DMA to be aborted, call directly user Abort complete callback */
2659 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2660 hspi->AbortCpltCallback(hspi);
2661 #else
2662 HAL_SPI_AbortCpltCallback(hspi);
2663 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2664 }
2665
2666 return errorcode;
2667 }
2668
2669 /**
2670 * @brief Pause the DMA Transfer.
2671 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2672 * the configuration information for the specified SPI module.
2673 * @retval HAL status
2674 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2675 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2676 {
2677 /* Process Locked */
2678 __HAL_LOCK(hspi);
2679
2680 /* Disable the SPI DMA Tx & Rx requests */
2681 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2682
2683 /* Process Unlocked */
2684 __HAL_UNLOCK(hspi);
2685
2686 return HAL_OK;
2687 }
2688
2689 /**
2690 * @brief Resume the DMA Transfer.
2691 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2692 * the configuration information for the specified SPI module.
2693 * @retval HAL status
2694 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2695 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2696 {
2697 /* Process Locked */
2698 __HAL_LOCK(hspi);
2699
2700 /* Enable the SPI DMA Tx & Rx requests */
2701 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2702
2703 /* Process Unlocked */
2704 __HAL_UNLOCK(hspi);
2705
2706 return HAL_OK;
2707 }
2708
2709 /**
2710 * @brief Stop the DMA Transfer.
2711 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2712 * the configuration information for the specified SPI module.
2713 * @retval HAL status
2714 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2715 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2716 {
2717 HAL_StatusTypeDef errorcode = HAL_OK;
2718 /* The Lock is not implemented on this API to allow the user application
2719 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2720 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2721 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2722 */
2723
2724 /* Abort the SPI DMA tx Stream/Channel */
2725 if (hspi->hdmatx != NULL)
2726 {
2727 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2728 {
2729 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2730 errorcode = HAL_ERROR;
2731 }
2732 }
2733 /* Abort the SPI DMA rx Stream/Channel */
2734 if (hspi->hdmarx != NULL)
2735 {
2736 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2737 {
2738 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2739 errorcode = HAL_ERROR;
2740 }
2741 }
2742
2743 /* Disable the SPI DMA Tx & Rx requests */
2744 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2745 hspi->State = HAL_SPI_STATE_READY;
2746 return errorcode;
2747 }
2748
2749 /**
2750 * @brief Handle SPI interrupt request.
2751 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2752 * the configuration information for the specified SPI module.
2753 * @retval None
2754 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2755 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2756 {
2757 uint32_t itsource = hspi->Instance->CR2;
2758 uint32_t itflag = hspi->Instance->SR;
2759
2760 /* SPI in mode Receiver ----------------------------------------------------*/
2761 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2762 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2763 {
2764 hspi->RxISR(hspi);
2765 return;
2766 }
2767
2768 /* SPI in mode Transmitter -------------------------------------------------*/
2769 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2770 {
2771 hspi->TxISR(hspi);
2772 return;
2773 }
2774
2775 /* SPI in Error Treatment --------------------------------------------------*/
2776 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2777 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2778 {
2779 /* SPI Overrun error interrupt occurred ----------------------------------*/
2780 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2781 {
2782 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2783 {
2784 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2785 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2786 }
2787 else
2788 {
2789 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2790 return;
2791 }
2792 }
2793
2794 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2795 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2796 {
2797 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2798 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2799 }
2800
2801 /* SPI Frame error interrupt occurred ------------------------------------*/
2802 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2803 {
2804 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2805 __HAL_SPI_CLEAR_FREFLAG(hspi);
2806 }
2807
2808 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2809 {
2810 /* Disable all interrupts */
2811 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2812
2813 hspi->State = HAL_SPI_STATE_READY;
2814 /* Disable the SPI DMA requests if enabled */
2815 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2816 {
2817 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2818
2819 /* Abort the SPI DMA Rx channel */
2820 if (hspi->hdmarx != NULL)
2821 {
2822 /* Set the SPI DMA Abort callback :
2823 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2824 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2825 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2826 {
2827 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2828 }
2829 }
2830 /* Abort the SPI DMA Tx channel */
2831 if (hspi->hdmatx != NULL)
2832 {
2833 /* Set the SPI DMA Abort callback :
2834 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2835 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2836 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2837 {
2838 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2839 }
2840 }
2841 }
2842 else
2843 {
2844 /* Call user error callback */
2845 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2846 hspi->ErrorCallback(hspi);
2847 #else
2848 HAL_SPI_ErrorCallback(hspi);
2849 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2850 }
2851 }
2852 return;
2853 }
2854 }
2855
2856 /**
2857 * @brief Tx Transfer completed callback.
2858 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2859 * the configuration information for SPI module.
2860 * @retval None
2861 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2862 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2863 {
2864 /* Prevent unused argument(s) compilation warning */
2865 UNUSED(hspi);
2866
2867 /* NOTE : This function should not be modified, when the callback is needed,
2868 the HAL_SPI_TxCpltCallback should be implemented in the user file
2869 */
2870 }
2871
2872 /**
2873 * @brief Rx Transfer completed callback.
2874 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2875 * the configuration information for SPI module.
2876 * @retval None
2877 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2878 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2879 {
2880 /* Prevent unused argument(s) compilation warning */
2881 UNUSED(hspi);
2882
2883 /* NOTE : This function should not be modified, when the callback is needed,
2884 the HAL_SPI_RxCpltCallback should be implemented in the user file
2885 */
2886 }
2887
2888 /**
2889 * @brief Tx and Rx Transfer completed callback.
2890 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2891 * the configuration information for SPI module.
2892 * @retval None
2893 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2894 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2895 {
2896 /* Prevent unused argument(s) compilation warning */
2897 UNUSED(hspi);
2898
2899 /* NOTE : This function should not be modified, when the callback is needed,
2900 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2901 */
2902 }
2903
2904 /**
2905 * @brief Tx Half Transfer completed callback.
2906 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2907 * the configuration information for SPI module.
2908 * @retval None
2909 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2910 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2911 {
2912 /* Prevent unused argument(s) compilation warning */
2913 UNUSED(hspi);
2914
2915 /* NOTE : This function should not be modified, when the callback is needed,
2916 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2917 */
2918 }
2919
2920 /**
2921 * @brief Rx Half Transfer completed callback.
2922 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2923 * the configuration information for SPI module.
2924 * @retval None
2925 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2926 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2927 {
2928 /* Prevent unused argument(s) compilation warning */
2929 UNUSED(hspi);
2930
2931 /* NOTE : This function should not be modified, when the callback is needed,
2932 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2933 */
2934 }
2935
2936 /**
2937 * @brief Tx and Rx Half Transfer callback.
2938 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2939 * the configuration information for SPI module.
2940 * @retval None
2941 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2942 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2943 {
2944 /* Prevent unused argument(s) compilation warning */
2945 UNUSED(hspi);
2946
2947 /* NOTE : This function should not be modified, when the callback is needed,
2948 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2949 */
2950 }
2951
2952 /**
2953 * @brief SPI error callback.
2954 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2955 * the configuration information for SPI module.
2956 * @retval None
2957 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2958 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2959 {
2960 /* Prevent unused argument(s) compilation warning */
2961 UNUSED(hspi);
2962
2963 /* NOTE : This function should not be modified, when the callback is needed,
2964 the HAL_SPI_ErrorCallback should be implemented in the user file
2965 */
2966 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2967 and user can use HAL_SPI_GetError() API to check the latest error occurred
2968 */
2969 }
2970
2971 /**
2972 * @brief SPI Abort Complete callback.
2973 * @param hspi SPI handle.
2974 * @retval None
2975 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2976 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2977 {
2978 /* Prevent unused argument(s) compilation warning */
2979 UNUSED(hspi);
2980
2981 /* NOTE : This function should not be modified, when the callback is needed,
2982 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2983 */
2984 }
2985
2986 /**
2987 * @}
2988 */
2989
2990 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2991 * @brief SPI control functions
2992 *
2993 @verbatim
2994 ===============================================================================
2995 ##### Peripheral State and Errors functions #####
2996 ===============================================================================
2997 [..]
2998 This subsection provides a set of functions allowing to control the SPI.
2999 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
3000 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
3001 @endverbatim
3002 * @{
3003 */
3004
3005 /**
3006 * @brief Return the SPI handle state.
3007 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3008 * the configuration information for SPI module.
3009 * @retval SPI state
3010 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)3011 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
3012 {
3013 /* Return SPI handle state */
3014 return hspi->State;
3015 }
3016
3017 /**
3018 * @brief Return the SPI error code.
3019 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3020 * the configuration information for SPI module.
3021 * @retval SPI error code in bitmap format
3022 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)3023 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
3024 {
3025 /* Return SPI ErrorCode */
3026 return hspi->ErrorCode;
3027 }
3028
3029 /**
3030 * @}
3031 */
3032
3033 /**
3034 * @}
3035 */
3036
3037 /** @addtogroup SPI_Private_Functions
3038 * @brief Private functions
3039 * @{
3040 */
3041
3042 /**
3043 * @brief DMA SPI transmit process complete callback.
3044 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3045 * the configuration information for the specified DMA module.
3046 * @retval None
3047 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)3048 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
3049 {
3050 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3051 uint32_t tickstart;
3052
3053 /* Init tickstart for timeout management*/
3054 tickstart = HAL_GetTick();
3055
3056 /* DMA Normal Mode */
3057 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3058 {
3059 /* Disable ERR interrupt */
3060 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3061
3062 /* Disable Tx DMA Request */
3063 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3064
3065 /* Check the end of the transaction */
3066 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3067 {
3068 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3069 }
3070
3071 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
3072 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3073 {
3074 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3075 }
3076
3077 hspi->TxXferCount = 0U;
3078 hspi->State = HAL_SPI_STATE_READY;
3079
3080 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3081 {
3082 /* Call user error callback */
3083 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3084 hspi->ErrorCallback(hspi);
3085 #else
3086 HAL_SPI_ErrorCallback(hspi);
3087 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3088 return;
3089 }
3090 }
3091 /* Call user Tx complete callback */
3092 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3093 hspi->TxCpltCallback(hspi);
3094 #else
3095 HAL_SPI_TxCpltCallback(hspi);
3096 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3097 }
3098
3099 /**
3100 * @brief DMA SPI receive process complete callback.
3101 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3102 * the configuration information for the specified DMA module.
3103 * @retval None
3104 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3105 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3106 {
3107 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3108 uint32_t tickstart;
3109 #if (USE_SPI_CRC != 0U)
3110 __IO uint32_t tmpreg = 0U;
3111 __IO uint8_t *ptmpreg8;
3112 __IO uint8_t tmpreg8 = 0;
3113 #endif /* USE_SPI_CRC */
3114
3115 /* Init tickstart for timeout management*/
3116 tickstart = HAL_GetTick();
3117
3118 /* DMA Normal Mode */
3119 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3120 {
3121 /* Disable ERR interrupt */
3122 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3123
3124 #if (USE_SPI_CRC != 0U)
3125 /* CRC handling */
3126 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3127 {
3128 /* Wait until RXNE flag */
3129 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3130 {
3131 /* Error on the CRC reception */
3132 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3133 }
3134 /* Read CRC */
3135 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3136 {
3137 /* Read 16bit CRC */
3138 tmpreg = READ_REG(hspi->Instance->DR);
3139 /* To avoid GCC warning */
3140 UNUSED(tmpreg);
3141 }
3142 else
3143 {
3144 /* Initialize the 8bit temporary pointer */
3145 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3146 /* Read 8bit CRC */
3147 tmpreg8 = *ptmpreg8;
3148 /* To avoid GCC warning */
3149 UNUSED(tmpreg8);
3150
3151 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3152 {
3153 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3154 {
3155 /* Error on the CRC reception */
3156 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3157 }
3158 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3159 tmpreg8 = *ptmpreg8;
3160 /* To avoid GCC warning */
3161 UNUSED(tmpreg8);
3162 }
3163 }
3164 }
3165 #endif /* USE_SPI_CRC */
3166
3167 /* Check if we are in Master RX 2 line mode */
3168 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3169 {
3170 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3171 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3172 }
3173 else
3174 {
3175 /* Normal case */
3176 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3177 }
3178
3179 /* Check the end of the transaction */
3180 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3181 {
3182 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3183 }
3184
3185 hspi->RxXferCount = 0U;
3186 hspi->State = HAL_SPI_STATE_READY;
3187
3188 #if (USE_SPI_CRC != 0U)
3189 /* Check if CRC error occurred */
3190 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3191 {
3192 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3193 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3194 }
3195 #endif /* USE_SPI_CRC */
3196
3197 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3198 {
3199 /* Call user error callback */
3200 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3201 hspi->ErrorCallback(hspi);
3202 #else
3203 HAL_SPI_ErrorCallback(hspi);
3204 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3205 return;
3206 }
3207 }
3208 /* Call user Rx complete callback */
3209 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3210 hspi->RxCpltCallback(hspi);
3211 #else
3212 HAL_SPI_RxCpltCallback(hspi);
3213 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3214 }
3215
3216 /**
3217 * @brief DMA SPI transmit receive process complete callback.
3218 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3219 * the configuration information for the specified DMA module.
3220 * @retval None
3221 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3222 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3223 {
3224 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3225 uint32_t tickstart;
3226 #if (USE_SPI_CRC != 0U)
3227 __IO uint32_t tmpreg = 0U;
3228 __IO uint8_t *ptmpreg8;
3229 __IO uint8_t tmpreg8 = 0;
3230 #endif /* USE_SPI_CRC */
3231
3232 /* Init tickstart for timeout management*/
3233 tickstart = HAL_GetTick();
3234
3235 /* DMA Normal Mode */
3236 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3237 {
3238 /* Disable ERR interrupt */
3239 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3240
3241 #if (USE_SPI_CRC != 0U)
3242 /* CRC handling */
3243 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3244 {
3245 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3246 {
3247 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3248 tickstart) != HAL_OK)
3249 {
3250 /* Error on the CRC reception */
3251 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3252 }
3253 /* Initialize the 8bit temporary pointer */
3254 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3255 /* Read 8bit CRC */
3256 tmpreg8 = *ptmpreg8;
3257 /* To avoid GCC warning */
3258 UNUSED(tmpreg8);
3259 }
3260 else
3261 {
3262 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3263 {
3264 /* Error on the CRC reception */
3265 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3266 }
3267 /* Read CRC to Flush DR and RXNE flag */
3268 tmpreg = READ_REG(hspi->Instance->DR);
3269 /* To avoid GCC warning */
3270 UNUSED(tmpreg);
3271 }
3272 }
3273 #endif /* USE_SPI_CRC */
3274
3275 /* Check the end of the transaction */
3276 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3277 {
3278 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3279 }
3280
3281 /* Disable Rx/Tx DMA Request */
3282 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3283
3284 hspi->TxXferCount = 0U;
3285 hspi->RxXferCount = 0U;
3286 hspi->State = HAL_SPI_STATE_READY;
3287
3288 #if (USE_SPI_CRC != 0U)
3289 /* Check if CRC error occurred */
3290 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3291 {
3292 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3293 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3294 }
3295 #endif /* USE_SPI_CRC */
3296
3297 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3298 {
3299 /* Call user error callback */
3300 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3301 hspi->ErrorCallback(hspi);
3302 #else
3303 HAL_SPI_ErrorCallback(hspi);
3304 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3305 return;
3306 }
3307 }
3308 /* Call user TxRx complete callback */
3309 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3310 hspi->TxRxCpltCallback(hspi);
3311 #else
3312 HAL_SPI_TxRxCpltCallback(hspi);
3313 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3314 }
3315
3316 /**
3317 * @brief DMA SPI half transmit process complete callback.
3318 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3319 * the configuration information for the specified DMA module.
3320 * @retval None
3321 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3322 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3323 {
3324 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3325
3326 /* Call user Tx half complete callback */
3327 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3328 hspi->TxHalfCpltCallback(hspi);
3329 #else
3330 HAL_SPI_TxHalfCpltCallback(hspi);
3331 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3332 }
3333
3334 /**
3335 * @brief DMA SPI half receive process complete callback
3336 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3337 * the configuration information for the specified DMA module.
3338 * @retval None
3339 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3340 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3341 {
3342 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3343
3344 /* Call user Rx half complete callback */
3345 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3346 hspi->RxHalfCpltCallback(hspi);
3347 #else
3348 HAL_SPI_RxHalfCpltCallback(hspi);
3349 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3350 }
3351
3352 /**
3353 * @brief DMA SPI half transmit receive process complete callback.
3354 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3355 * the configuration information for the specified DMA module.
3356 * @retval None
3357 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3358 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3359 {
3360 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3361
3362 /* Call user TxRx half complete callback */
3363 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3364 hspi->TxRxHalfCpltCallback(hspi);
3365 #else
3366 HAL_SPI_TxRxHalfCpltCallback(hspi);
3367 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3368 }
3369
3370 /**
3371 * @brief DMA SPI communication error callback.
3372 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3373 * the configuration information for the specified DMA module.
3374 * @retval None
3375 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3376 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3377 {
3378 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3379
3380 /* Stop the disable DMA transfer on SPI side */
3381 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3382
3383 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3384 hspi->State = HAL_SPI_STATE_READY;
3385 /* Call user error callback */
3386 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3387 hspi->ErrorCallback(hspi);
3388 #else
3389 HAL_SPI_ErrorCallback(hspi);
3390 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3391 }
3392
3393 /**
3394 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3395 * (To be called at end of DMA Abort procedure following error occurrence).
3396 * @param hdma DMA handle.
3397 * @retval None
3398 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3399 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3400 {
3401 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3402 hspi->RxXferCount = 0U;
3403 hspi->TxXferCount = 0U;
3404
3405 /* Call user error callback */
3406 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3407 hspi->ErrorCallback(hspi);
3408 #else
3409 HAL_SPI_ErrorCallback(hspi);
3410 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3411 }
3412
3413 /**
3414 * @brief DMA SPI Tx communication abort callback, when initiated by user
3415 * (To be called at end of DMA Tx Abort procedure following user abort request).
3416 * @note When this callback is executed, User Abort complete call back is called only if no
3417 * Abort still ongoing for Rx DMA Handle.
3418 * @param hdma DMA handle.
3419 * @retval None
3420 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3421 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3422 {
3423 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3424
3425 hspi->hdmatx->XferAbortCallback = NULL;
3426
3427 /* Disable Tx DMA Request */
3428 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3429
3430 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3431 {
3432 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3433 }
3434
3435 /* Disable SPI Peripheral */
3436 __HAL_SPI_DISABLE(hspi);
3437
3438 /* Empty the FRLVL fifo */
3439 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3440 {
3441 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3442 }
3443
3444 /* Check if an Abort process is still ongoing */
3445 if (hspi->hdmarx != NULL)
3446 {
3447 if (hspi->hdmarx->XferAbortCallback != NULL)
3448 {
3449 return;
3450 }
3451 }
3452
3453 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3454 hspi->RxXferCount = 0U;
3455 hspi->TxXferCount = 0U;
3456
3457 /* Check no error during Abort procedure */
3458 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3459 {
3460 /* Reset errorCode */
3461 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3462 }
3463
3464 /* Clear the Error flags in the SR register */
3465 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3466 __HAL_SPI_CLEAR_FREFLAG(hspi);
3467
3468 /* Restore hspi->State to Ready */
3469 hspi->State = HAL_SPI_STATE_READY;
3470
3471 /* Call user Abort complete callback */
3472 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3473 hspi->AbortCpltCallback(hspi);
3474 #else
3475 HAL_SPI_AbortCpltCallback(hspi);
3476 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3477 }
3478
3479 /**
3480 * @brief DMA SPI Rx communication abort callback, when initiated by user
3481 * (To be called at end of DMA Rx Abort procedure following user abort request).
3482 * @note When this callback is executed, User Abort complete call back is called only if no
3483 * Abort still ongoing for Tx DMA Handle.
3484 * @param hdma DMA handle.
3485 * @retval None
3486 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3487 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3488 {
3489 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3490
3491 /* Disable SPI Peripheral */
3492 __HAL_SPI_DISABLE(hspi);
3493
3494 hspi->hdmarx->XferAbortCallback = NULL;
3495
3496 /* Disable Rx DMA Request */
3497 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3498
3499 /* Control the BSY flag */
3500 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3501 {
3502 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3503 }
3504
3505 /* Empty the FRLVL fifo */
3506 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3507 {
3508 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3509 }
3510
3511 /* Check if an Abort process is still ongoing */
3512 if (hspi->hdmatx != NULL)
3513 {
3514 if (hspi->hdmatx->XferAbortCallback != NULL)
3515 {
3516 return;
3517 }
3518 }
3519
3520 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3521 hspi->RxXferCount = 0U;
3522 hspi->TxXferCount = 0U;
3523
3524 /* Check no error during Abort procedure */
3525 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3526 {
3527 /* Reset errorCode */
3528 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3529 }
3530
3531 /* Clear the Error flags in the SR register */
3532 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3533 __HAL_SPI_CLEAR_FREFLAG(hspi);
3534
3535 /* Restore hspi->State to Ready */
3536 hspi->State = HAL_SPI_STATE_READY;
3537
3538 /* Call user Abort complete callback */
3539 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3540 hspi->AbortCpltCallback(hspi);
3541 #else
3542 HAL_SPI_AbortCpltCallback(hspi);
3543 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3544 }
3545
3546 /**
3547 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3548 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3549 * the configuration information for SPI module.
3550 * @retval None
3551 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3552 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3553 {
3554 /* Receive data in packing mode */
3555 if (hspi->RxXferCount > 1U)
3556 {
3557 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3558 hspi->pRxBuffPtr += sizeof(uint16_t);
3559 hspi->RxXferCount -= 2U;
3560 if (hspi->RxXferCount == 1U)
3561 {
3562 /* Set RX Fifo threshold according the reception data length: 8bit */
3563 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3564 }
3565 }
3566 /* Receive data in 8 Bit mode */
3567 else
3568 {
3569 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3570 hspi->pRxBuffPtr++;
3571 hspi->RxXferCount--;
3572 }
3573
3574 /* Check end of the reception */
3575 if (hspi->RxXferCount == 0U)
3576 {
3577 #if (USE_SPI_CRC != 0U)
3578 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3579 {
3580 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3581 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3582 return;
3583 }
3584 #endif /* USE_SPI_CRC */
3585
3586 /* Disable RXNE and ERR interrupt */
3587 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3588
3589 if (hspi->TxXferCount == 0U)
3590 {
3591 SPI_CloseRxTx_ISR(hspi);
3592 }
3593 }
3594 }
3595
3596 #if (USE_SPI_CRC != 0U)
3597 /**
3598 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3599 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3600 * the configuration information for SPI module.
3601 * @retval None
3602 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3603 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3604 {
3605 __IO uint8_t *ptmpreg8;
3606 __IO uint8_t tmpreg8 = 0;
3607
3608 /* Initialize the 8bit temporary pointer */
3609 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3610 /* Read 8bit CRC to flush Data Register */
3611 tmpreg8 = *ptmpreg8;
3612 /* To avoid GCC warning */
3613 UNUSED(tmpreg8);
3614
3615 hspi->CRCSize--;
3616
3617 /* Check end of the reception */
3618 if (hspi->CRCSize == 0U)
3619 {
3620 /* Disable RXNE and ERR interrupt */
3621 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3622
3623 if (hspi->TxXferCount == 0U)
3624 {
3625 SPI_CloseRxTx_ISR(hspi);
3626 }
3627 }
3628 }
3629 #endif /* USE_SPI_CRC */
3630
3631 /**
3632 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3633 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3634 * the configuration information for SPI module.
3635 * @retval None
3636 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3637 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3638 {
3639 /* Transmit data in packing Bit mode */
3640 if (hspi->TxXferCount >= 2U)
3641 {
3642 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3643 hspi->pTxBuffPtr += sizeof(uint16_t);
3644 hspi->TxXferCount -= 2U;
3645 }
3646 /* Transmit data in 8 Bit mode */
3647 else
3648 {
3649 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3650 hspi->pTxBuffPtr++;
3651 hspi->TxXferCount--;
3652 }
3653
3654 /* Check the end of the transmission */
3655 if (hspi->TxXferCount == 0U)
3656 {
3657 #if (USE_SPI_CRC != 0U)
3658 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3659 {
3660 /* Set CRC Next Bit to send CRC */
3661 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3662 /* Disable TXE interrupt */
3663 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3664 return;
3665 }
3666 #endif /* USE_SPI_CRC */
3667
3668 /* Disable TXE interrupt */
3669 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3670
3671 if (hspi->RxXferCount == 0U)
3672 {
3673 SPI_CloseRxTx_ISR(hspi);
3674 }
3675 }
3676 }
3677
3678 /**
3679 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3680 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3681 * the configuration information for SPI module.
3682 * @retval None
3683 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3684 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3685 {
3686 /* Receive data in 16 Bit mode */
3687 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3688 hspi->pRxBuffPtr += sizeof(uint16_t);
3689 hspi->RxXferCount--;
3690
3691 if (hspi->RxXferCount == 0U)
3692 {
3693 #if (USE_SPI_CRC != 0U)
3694 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3695 {
3696 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3697 return;
3698 }
3699 #endif /* USE_SPI_CRC */
3700
3701 /* Disable RXNE interrupt */
3702 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3703
3704 if (hspi->TxXferCount == 0U)
3705 {
3706 SPI_CloseRxTx_ISR(hspi);
3707 }
3708 }
3709 }
3710
3711 #if (USE_SPI_CRC != 0U)
3712 /**
3713 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3714 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3715 * the configuration information for SPI module.
3716 * @retval None
3717 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3718 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3719 {
3720 __IO uint32_t tmpreg = 0U;
3721
3722 /* Read 16bit CRC to flush Data Register */
3723 tmpreg = READ_REG(hspi->Instance->DR);
3724 /* To avoid GCC warning */
3725 UNUSED(tmpreg);
3726
3727 /* Disable RXNE interrupt */
3728 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3729
3730 SPI_CloseRxTx_ISR(hspi);
3731 }
3732 #endif /* USE_SPI_CRC */
3733
3734 /**
3735 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3736 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3737 * the configuration information for SPI module.
3738 * @retval None
3739 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3740 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3741 {
3742 /* Transmit data in 16 Bit mode */
3743 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3744 hspi->pTxBuffPtr += sizeof(uint16_t);
3745 hspi->TxXferCount--;
3746
3747 /* Enable CRC Transmission */
3748 if (hspi->TxXferCount == 0U)
3749 {
3750 #if (USE_SPI_CRC != 0U)
3751 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3752 {
3753 /* Set CRC Next Bit to send CRC */
3754 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3755 /* Disable TXE interrupt */
3756 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3757 return;
3758 }
3759 #endif /* USE_SPI_CRC */
3760
3761 /* Disable TXE interrupt */
3762 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3763
3764 if (hspi->RxXferCount == 0U)
3765 {
3766 SPI_CloseRxTx_ISR(hspi);
3767 }
3768 }
3769 }
3770
3771 #if (USE_SPI_CRC != 0U)
3772 /**
3773 * @brief Manage the CRC 8-bit receive in Interrupt context.
3774 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3775 * the configuration information for SPI module.
3776 * @retval None
3777 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3778 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3779 {
3780 __IO uint8_t *ptmpreg8;
3781 __IO uint8_t tmpreg8 = 0;
3782
3783 /* Initialize the 8bit temporary pointer */
3784 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3785 /* Read 8bit CRC to flush Data Register */
3786 tmpreg8 = *ptmpreg8;
3787 /* To avoid GCC warning */
3788 UNUSED(tmpreg8);
3789
3790 hspi->CRCSize--;
3791
3792 if (hspi->CRCSize == 0U)
3793 {
3794 SPI_CloseRx_ISR(hspi);
3795 }
3796 }
3797 #endif /* USE_SPI_CRC */
3798
3799 /**
3800 * @brief Manage the receive 8-bit in Interrupt context.
3801 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3802 * the configuration information for SPI module.
3803 * @retval None
3804 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3805 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3806 {
3807 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3808 hspi->pRxBuffPtr++;
3809 hspi->RxXferCount--;
3810
3811 #if (USE_SPI_CRC != 0U)
3812 /* Enable CRC Transmission */
3813 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3814 {
3815 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3816 }
3817 #endif /* USE_SPI_CRC */
3818
3819 if (hspi->RxXferCount == 0U)
3820 {
3821 #if (USE_SPI_CRC != 0U)
3822 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3823 {
3824 hspi->RxISR = SPI_RxISR_8BITCRC;
3825 return;
3826 }
3827 #endif /* USE_SPI_CRC */
3828 SPI_CloseRx_ISR(hspi);
3829 }
3830 }
3831
3832 #if (USE_SPI_CRC != 0U)
3833 /**
3834 * @brief Manage the CRC 16-bit receive in Interrupt context.
3835 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3836 * the configuration information for SPI module.
3837 * @retval None
3838 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3839 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3840 {
3841 __IO uint32_t tmpreg = 0U;
3842
3843 /* Read 16bit CRC to flush Data Register */
3844 tmpreg = READ_REG(hspi->Instance->DR);
3845 /* To avoid GCC warning */
3846 UNUSED(tmpreg);
3847
3848 /* Disable RXNE and ERR interrupt */
3849 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3850
3851 SPI_CloseRx_ISR(hspi);
3852 }
3853 #endif /* USE_SPI_CRC */
3854
3855 /**
3856 * @brief Manage the 16-bit receive in Interrupt context.
3857 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3858 * the configuration information for SPI module.
3859 * @retval None
3860 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3861 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3862 {
3863 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3864 hspi->pRxBuffPtr += sizeof(uint16_t);
3865 hspi->RxXferCount--;
3866
3867 #if (USE_SPI_CRC != 0U)
3868 /* Enable CRC Transmission */
3869 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3870 {
3871 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3872 }
3873 #endif /* USE_SPI_CRC */
3874
3875 if (hspi->RxXferCount == 0U)
3876 {
3877 #if (USE_SPI_CRC != 0U)
3878 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3879 {
3880 hspi->RxISR = SPI_RxISR_16BITCRC;
3881 return;
3882 }
3883 #endif /* USE_SPI_CRC */
3884 SPI_CloseRx_ISR(hspi);
3885 }
3886 }
3887
3888 /**
3889 * @brief Handle the data 8-bit transmit in Interrupt mode.
3890 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3891 * the configuration information for SPI module.
3892 * @retval None
3893 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3894 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3895 {
3896 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3897 hspi->pTxBuffPtr++;
3898 hspi->TxXferCount--;
3899
3900 if (hspi->TxXferCount == 0U)
3901 {
3902 #if (USE_SPI_CRC != 0U)
3903 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3904 {
3905 /* Enable CRC Transmission */
3906 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3907 }
3908 #endif /* USE_SPI_CRC */
3909 SPI_CloseTx_ISR(hspi);
3910 }
3911 }
3912
3913 /**
3914 * @brief Handle the data 16-bit transmit in Interrupt mode.
3915 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3916 * the configuration information for SPI module.
3917 * @retval None
3918 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3919 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3920 {
3921 /* Transmit data in 16 Bit mode */
3922 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3923 hspi->pTxBuffPtr += sizeof(uint16_t);
3924 hspi->TxXferCount--;
3925
3926 if (hspi->TxXferCount == 0U)
3927 {
3928 #if (USE_SPI_CRC != 0U)
3929 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3930 {
3931 /* Enable CRC Transmission */
3932 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3933 }
3934 #endif /* USE_SPI_CRC */
3935 SPI_CloseTx_ISR(hspi);
3936 }
3937 }
3938
3939 /**
3940 * @brief Handle SPI Communication Timeout.
3941 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3942 * the configuration information for SPI module.
3943 * @param Flag SPI flag to check
3944 * @param State flag state to check
3945 * @param Timeout Timeout duration
3946 * @param Tickstart tick start value
3947 * @retval HAL status
3948 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3949 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3950 uint32_t Timeout, uint32_t Tickstart)
3951 {
3952 __IO uint32_t count;
3953 uint32_t tmp_timeout;
3954 uint32_t tmp_tickstart;
3955
3956 /* Adjust Timeout value in case of end of transfer */
3957 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3958 tmp_tickstart = HAL_GetTick();
3959
3960 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3961 count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3962
3963 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3964 {
3965 if (Timeout != HAL_MAX_DELAY)
3966 {
3967 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3968 {
3969 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3970 on both master and slave sides in order to resynchronize the master
3971 and slave for their respective CRC calculation */
3972
3973 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3974 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3975
3976 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3977 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3978 {
3979 /* Disable SPI peripheral */
3980 __HAL_SPI_DISABLE(hspi);
3981 }
3982
3983 /* Reset CRC Calculation */
3984 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3985 {
3986 SPI_RESET_CRC(hspi);
3987 }
3988
3989 hspi->State = HAL_SPI_STATE_READY;
3990
3991 /* Process Unlocked */
3992 __HAL_UNLOCK(hspi);
3993
3994 return HAL_TIMEOUT;
3995 }
3996 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3997 if (count == 0U)
3998 {
3999 tmp_timeout = 0U;
4000 }
4001 count--;
4002 }
4003 }
4004
4005 return HAL_OK;
4006 }
4007
4008 /**
4009 * @brief Handle SPI FIFO Communication Timeout.
4010 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4011 * the configuration information for SPI module.
4012 * @param Fifo Fifo to check
4013 * @param State Fifo state to check
4014 * @param Timeout Timeout duration
4015 * @param Tickstart tick start value
4016 * @retval HAL status
4017 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)4018 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
4019 uint32_t Timeout, uint32_t Tickstart)
4020 {
4021 __IO uint32_t count;
4022 uint32_t tmp_timeout;
4023 uint32_t tmp_tickstart;
4024 __IO uint8_t *ptmpreg8;
4025 __IO uint8_t tmpreg8 = 0;
4026
4027 /* Adjust Timeout value in case of end of transfer */
4028 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
4029 tmp_tickstart = HAL_GetTick();
4030
4031 /* Initialize the 8bit temporary pointer */
4032 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
4033
4034 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
4035 count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
4036
4037 while ((hspi->Instance->SR & Fifo) != State)
4038 {
4039 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
4040 {
4041 /* Flush Data Register by a blank read */
4042 tmpreg8 = *ptmpreg8;
4043 /* To avoid GCC warning */
4044 UNUSED(tmpreg8);
4045 }
4046
4047 if (Timeout != HAL_MAX_DELAY)
4048 {
4049 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
4050 {
4051 /* Disable the SPI and reset the CRC: the CRC value should be cleared
4052 on both master and slave sides in order to resynchronize the master
4053 and slave for their respective CRC calculation */
4054
4055 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
4056 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
4057
4058 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4059 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4060 {
4061 /* Disable SPI peripheral */
4062 __HAL_SPI_DISABLE(hspi);
4063 }
4064
4065 /* Reset CRC Calculation */
4066 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
4067 {
4068 SPI_RESET_CRC(hspi);
4069 }
4070
4071 hspi->State = HAL_SPI_STATE_READY;
4072
4073 /* Process Unlocked */
4074 __HAL_UNLOCK(hspi);
4075
4076 return HAL_TIMEOUT;
4077 }
4078 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
4079 if (count == 0U)
4080 {
4081 tmp_timeout = 0U;
4082 }
4083 count--;
4084 }
4085 }
4086
4087 return HAL_OK;
4088 }
4089
4090 /**
4091 * @brief Handle the check of the RX transaction complete.
4092 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4093 * the configuration information for SPI module.
4094 * @param Timeout Timeout duration
4095 * @param Tickstart tick start value
4096 * @retval HAL status
4097 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4098 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4099 {
4100 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4101 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4102 {
4103 /* Disable SPI peripheral */
4104 __HAL_SPI_DISABLE(hspi);
4105 }
4106
4107 /* Control the BSY flag */
4108 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4109 {
4110 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4111 return HAL_TIMEOUT;
4112 }
4113
4114 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4115 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4116 {
4117 /* Empty the FRLVL fifo */
4118 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4119 {
4120 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4121 return HAL_TIMEOUT;
4122 }
4123 }
4124 return HAL_OK;
4125 }
4126
4127 /**
4128 * @brief Handle the check of the RXTX or TX transaction complete.
4129 * @param hspi SPI handle
4130 * @param Timeout Timeout duration
4131 * @param Tickstart tick start value
4132 * @retval HAL status
4133 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4134 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4135 {
4136 /* Control if the TX fifo is empty */
4137 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4138 {
4139 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4140 return HAL_TIMEOUT;
4141 }
4142
4143 /* Control the BSY flag */
4144 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4145 {
4146 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4147 return HAL_TIMEOUT;
4148 }
4149
4150 /* Control if the RX fifo is empty */
4151 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4152 {
4153 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4154 return HAL_TIMEOUT;
4155 }
4156
4157 return HAL_OK;
4158 }
4159
4160 /**
4161 * @brief Handle the end of the RXTX transaction.
4162 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4163 * the configuration information for SPI module.
4164 * @retval None
4165 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4166 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4167 {
4168 uint32_t tickstart;
4169
4170 /* Init tickstart for timeout management */
4171 tickstart = HAL_GetTick();
4172
4173 /* Disable ERR interrupt */
4174 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4175
4176 /* Check the end of the transaction */
4177 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4178 {
4179 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4180 }
4181
4182 #if (USE_SPI_CRC != 0U)
4183 /* Check if CRC error occurred */
4184 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4185 {
4186 hspi->State = HAL_SPI_STATE_READY;
4187 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4188 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4189 /* Call user error callback */
4190 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4191 hspi->ErrorCallback(hspi);
4192 #else
4193 HAL_SPI_ErrorCallback(hspi);
4194 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4195 }
4196 else
4197 {
4198 #endif /* USE_SPI_CRC */
4199 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4200 {
4201 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4202 {
4203 hspi->State = HAL_SPI_STATE_READY;
4204 /* Call user Rx complete callback */
4205 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4206 hspi->RxCpltCallback(hspi);
4207 #else
4208 HAL_SPI_RxCpltCallback(hspi);
4209 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4210 }
4211 else
4212 {
4213 hspi->State = HAL_SPI_STATE_READY;
4214 /* Call user TxRx complete callback */
4215 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4216 hspi->TxRxCpltCallback(hspi);
4217 #else
4218 HAL_SPI_TxRxCpltCallback(hspi);
4219 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4220 }
4221 }
4222 else
4223 {
4224 hspi->State = HAL_SPI_STATE_READY;
4225 /* Call user error callback */
4226 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4227 hspi->ErrorCallback(hspi);
4228 #else
4229 HAL_SPI_ErrorCallback(hspi);
4230 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4231 }
4232 #if (USE_SPI_CRC != 0U)
4233 }
4234 #endif /* USE_SPI_CRC */
4235 }
4236
4237 /**
4238 * @brief Handle the end of the RX transaction.
4239 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4240 * the configuration information for SPI module.
4241 * @retval None
4242 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4243 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4244 {
4245 /* Disable RXNE and ERR interrupt */
4246 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4247
4248 /* Check the end of the transaction */
4249 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4250 {
4251 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4252 }
4253 hspi->State = HAL_SPI_STATE_READY;
4254
4255 #if (USE_SPI_CRC != 0U)
4256 /* Check if CRC error occurred */
4257 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4258 {
4259 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4260 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4261 /* Call user error callback */
4262 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4263 hspi->ErrorCallback(hspi);
4264 #else
4265 HAL_SPI_ErrorCallback(hspi);
4266 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4267 }
4268 else
4269 {
4270 #endif /* USE_SPI_CRC */
4271 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4272 {
4273 /* Call user Rx complete callback */
4274 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4275 hspi->RxCpltCallback(hspi);
4276 #else
4277 HAL_SPI_RxCpltCallback(hspi);
4278 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4279 }
4280 else
4281 {
4282 /* Call user error callback */
4283 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4284 hspi->ErrorCallback(hspi);
4285 #else
4286 HAL_SPI_ErrorCallback(hspi);
4287 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4288 }
4289 #if (USE_SPI_CRC != 0U)
4290 }
4291 #endif /* USE_SPI_CRC */
4292 }
4293
4294 /**
4295 * @brief Handle the end of the TX transaction.
4296 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4297 * the configuration information for SPI module.
4298 * @retval None
4299 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4300 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4301 {
4302 uint32_t tickstart;
4303
4304 /* Init tickstart for timeout management*/
4305 tickstart = HAL_GetTick();
4306
4307 /* Disable TXE and ERR interrupt */
4308 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4309
4310 /* Check the end of the transaction */
4311 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4312 {
4313 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4314 }
4315
4316 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4317 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4318 {
4319 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4320 }
4321
4322 hspi->State = HAL_SPI_STATE_READY;
4323 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4324 {
4325 /* Call user error callback */
4326 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4327 hspi->ErrorCallback(hspi);
4328 #else
4329 HAL_SPI_ErrorCallback(hspi);
4330 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4331 }
4332 else
4333 {
4334 /* Call user Rx complete callback */
4335 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4336 hspi->TxCpltCallback(hspi);
4337 #else
4338 HAL_SPI_TxCpltCallback(hspi);
4339 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4340 }
4341 }
4342
4343 /**
4344 * @brief Handle abort a Rx transaction.
4345 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4346 * the configuration information for SPI module.
4347 * @retval None
4348 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4349 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4350 {
4351 __IO uint32_t count;
4352
4353 /* Disable SPI Peripheral */
4354 __HAL_SPI_DISABLE(hspi);
4355
4356 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4357
4358 /* Disable RXNEIE interrupt */
4359 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4360
4361 /* Check RXNEIE is disabled */
4362 do
4363 {
4364 if (count == 0U)
4365 {
4366 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4367 break;
4368 }
4369 count--;
4370 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4371
4372 /* Control the BSY flag */
4373 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4374 {
4375 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4376 }
4377
4378 /* Empty the FRLVL fifo */
4379 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4380 {
4381 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4382 }
4383
4384 hspi->State = HAL_SPI_STATE_ABORT;
4385 }
4386
4387 /**
4388 * @brief Handle abort a Tx or Rx/Tx transaction.
4389 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4390 * the configuration information for SPI module.
4391 * @retval None
4392 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4393 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4394 {
4395 __IO uint32_t count;
4396
4397 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4398
4399 /* Disable TXEIE interrupt */
4400 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4401
4402 /* Check TXEIE is disabled */
4403 do
4404 {
4405 if (count == 0U)
4406 {
4407 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4408 break;
4409 }
4410 count--;
4411 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4412
4413 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4414 {
4415 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4416 }
4417
4418 /* Disable SPI Peripheral */
4419 __HAL_SPI_DISABLE(hspi);
4420
4421 /* Empty the FRLVL fifo */
4422 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4423 {
4424 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4425 }
4426
4427 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4428 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4429 {
4430 /* Disable RXNEIE interrupt */
4431 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4432
4433 /* Check RXNEIE is disabled */
4434 do
4435 {
4436 if (count == 0U)
4437 {
4438 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4439 break;
4440 }
4441 count--;
4442 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4443
4444 /* Control the BSY flag */
4445 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4446 {
4447 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4448 }
4449
4450 /* Empty the FRLVL fifo */
4451 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4452 {
4453 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4454 }
4455 }
4456 hspi->State = HAL_SPI_STATE_ABORT;
4457 }
4458
4459 /**
4460 * @}
4461 */
4462
4463 #endif /* HAL_SPI_MODULE_ENABLED */
4464
4465 /**
4466 * @}
4467 */
4468
4469 /**
4470 * @}
4471 */
4472
4473
