1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + DLL Calibration Start
10 * + Timer Time Base Unit Configuration
11 * + Simple Time Base Start/Stop
12 * + Simple Time Base Start/Stop Interrupt
13 * + Simple Time Base Start/Stop DMA Request
14 * + Simple Output Compare/PWM Channel Configuration
15 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
16 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
17 * + Simple Input Capture Channel Configuration
18 * + Simple Input Capture Channel Start/Stop Interrupt
19 * + Simple Input Capture Channel Start/Stop DMA Request
20 * + Simple One Pulse Channel Configuration
21 * + Simple One Pulse Channel Start/Stop Interrupt
22 * + HRTIM External Synchronization Configuration
23 * + HRTIM Burst Mode Controller Configuration
24 * + HRTIM Burst Mode Controller Enabling
25 * + HRTIM External Events Conditioning Configuration
26 * + HRTIM Faults Conditioning Configuration
27 * + HRTIM Faults Enabling
28 * + HRTIM ADC trigger Configuration
29 * + Waveform Timer Configuration
30 * + Waveform Event Filtering Configuration
31 * + Waveform Dead Time Insertion Configuration
32 * + Waveform Chopper Mode Configuration
33 * + Waveform Compare Unit Configuration
34 * + Waveform Capture Unit Configuration
35 * + Waveform Output Configuration
36 * + Waveform Counter Start/Stop
37 * + Waveform Counter Start/Stop Interrupt
38 * + Waveform Counter Start/Stop DMA Request
39 * + Waveform Output Enabling
40 * + Waveform Output Level Set/Get
41 * + Waveform Output State Get
42 * + Waveform Burst DMA Operation Configuration
43 * + Waveform Burst DMA Operation Start
44 * + Waveform Timer Counter Software Reset
45 * + Waveform Capture Software Trigger
46 * + Waveform Burst Mode Controller Software Trigger
47 * + Waveform Timer Pre-loadable Registers Update Enabling
48 * + Waveform Timer Pre-loadable Registers Software Update
49 * + Waveform Timer Delayed Protection Status Get
50 * + Waveform Timer Burst Status Get
51 * + Waveform Timer Push-Pull Status Get
52 * + Peripheral State Get
53 *
54 ******************************************************************************
55 * @attention
56 *
57 * Copyright (c) 2016 STMicroelectronics.
58 * All rights reserved.
59 *
60 * This software is licensed under terms that can be found in the LICENSE file
61 * in the root directory of this software component.
62 * If no LICENSE file comes with this software, it is provided AS-IS.
63 *
64 ******************************************************************************
65 @verbatim
66 ==============================================================================
67 ##### Simple mode v.s. waveform mode #####
68 ==============================================================================
69 [..] The HRTIM HAL API is split into 2 categories:
70 (#)Simple functions: these functions allow for using a HRTIM timer as a
71 general purpose timer with high resolution capabilities.
72 HRTIM simple modes are managed through the set of functions named
73 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
74 to the one defined for the TIM peripheral. When a HRTIM timer operates in
75 simple mode, only a very limited set of HRTIM features are used.
76 Following simple modes are proposed:
77 (++)Output compare mode,
78 (++)PWM output mode,
79 (++)Input capture mode,
80 (++)One pulse mode.
81 (#)Waveform functions: These functions allow taking advantage of the HRTIM
82 flexibility to produce numerous types of control signal. When a HRTIM timer
83 operates in waveform mode, all the HRTIM features are accessible without
84 any restriction. HRTIM waveform modes are managed through the set of
85 functions named HAL_HRTIM_Waveform<Function>
86
87 ##### How to use this driver #####
88 ==============================================================================
89 [..]
90 (#)Initialize the HRTIM low level resources by implementing the
91 HAL_HRTIM_MspInit() function:
92 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
93 (##)Connect HRTIM pins to MCU I/Os
94 (+++) Enable the clock for the HRTIM GPIOs using the following
95 function: __HAL_RCC_GPIOx_CLK_ENABLE()
96 (+++) Configure these GPIO pins in Alternate Function mode using
97 HAL_GPIO_Init()
98 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
99 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
100 (+++)Initialize the DMA handle
101 (+++)Associate the initialized DMA handle to the appropriate DMA
102 handle of the HRTIM handle using __HAL_LINKDMA()
103 (+++)Initialize the DMA channel using HAL_DMA_Init()
104 (+++)Configure the priority and enable the NVIC for the transfer
105 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
106 and HAL_NVIC_EnableIRQ()
107 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
108 (+++)Configure the priority and enable the NVIC for the concerned
109 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
110
111 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
112 structure (field of the HRTIM handle) specifies which global interrupt of
113 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
114 It also contains the HRTIM external synchronization configuration. HRTIM
115 can act as a master (generating a synchronization signal) or as a slave
116 (waiting for a trigger to be synchronized).
117
118 (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
119 calibration is executed periodically and compensate for potential voltage
120 and temperature drifts. DLL calibration period is specified by the
121 CalibrationRate argument.
122
123 (#)HRTIM timers cannot be used until the high resolution unit is ready. This
124 can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
125 HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
126 is still going on when timeout given as argument expires. DLL calibration
127 can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
128 In that case an interrupt is generated when the DLL calibration is completed.
129 Note that as DLL calibration is executed on a periodic basis an interrupt
130 will be generated at the end of every DLL calibration operation
131 (worst case: one interrupt every 14 micro seconds !).
132
133 (#) Configure HRTIM resources shared by all HRTIM timers
134 (##)Burst Mode Controller:
135 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
136 controller: operating mode (continuous or one-shot mode), clock
137 (source, prescaler) , trigger(s), period, idle duration.
138 (##)External Events Conditioning:
139 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
140 external event channel: source, polarity, edge-sensitivity.
141 External event can be used as triggers (timer reset, input
142 capture, burst mode, ADC triggers, delayed protection)
143 They can also be used to set or reset timer outputs. Up to
144 10 event channels are available.
145 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
146 event sampling clock (used for digital filtering).
147 (##)Fault Conditioning:
148 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
149 fault channel: source, polarity, edge-sensitivity. Fault
150 channels are used to disable the outputs in case of an
151 abnormal operation. Up to 5 fault channels are available.
152 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
153 sampling clock (used for digital filtering).
154 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
155 circuitry. By default all fault inputs are disabled.
156 (##)ADC trigger:
157 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
158 the update of the ADC trigger register and the ADC trigger.
159 4 independent triggers are available to start both the regular
160 and the injected sequencers of the 2 ADCs
161
162 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
163 function must be called whatever the HRTIM timer operating mode is
164 (simple v.s. waveform). It configures mainly:
165 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
166 (##)The HRTIM timer clock prescaler
167 (##)The HRTIM timer period
168 (##)The HRTIM timer repetition counter
169
170 *** If the HRTIM timer operates in simple mode ***
171 ===================================================
172 [..]
173 (#) Start or Stop simple timers
174 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
175 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
176 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
177 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
178 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
179 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
180 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
181 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
182 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
183 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
184 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
185 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
186 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
187 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
188 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
189 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
190 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
191 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
192
193 *** If the HRTIM timer operates in waveform mode ***
194 ====================================================
195 [..]
196 (#) Completes waveform timer configuration
197 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
198 operating in wave form mode mainly consists in:
199 (+++)Enabling the HRTIM timer interrupts and DMA requests.
200 (+++)Enabling the half mode for the HRTIM timer.
201 (+++)Defining how the HRTIM timer reacts to external synchronization input.
202 (+++)Enabling the push-pull mode for the HRTIM timer.
203 (+++)Enabling the fault channels for the HRTIM timer.
204 (+++)Enabling the dead-time insertion for the HRTIM timer.
205 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
206 on which the delayed protection are applied).
207 (+++)Specifying the HRTIM timer update and reset triggers.
208 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
209 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
210 event blanking and windowing circuitry of a HRTIM timer:
211 (+++)Blanking: to mask external events during a defined time period a defined time period
212 (+++)Windowing, to enable external events only during a defined time period
213 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
214 unit for a HRTIM timer. Allows to generate a couple of
215 complementary signals from a single reference waveform,
216 with programmable delays between active state.
217 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
218 the high-frequency carrier signal added on top of the timing
219 unit output. Chopper mode can be enabled or disabled for each
220 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
221 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
222 controller. Allows having multiple HRTIM registers updated
223 with a single DMA request. The burst DMA operation is started
224 by calling HAL_HRTIM_BurstDMATransfer().
225 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
226 of a HRTIM timer. This operation consists in setting the
227 compare value and possibly specifying the auto delayed mode
228 for compare units 2 and 4 (allows to have compare events
229 generated relatively to capture events). Note that when auto
230 delayed mode is needed, the capture unit associated to the
231 compare unit must be configured separately.
232 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
233 of a HRTIM timer. This operation consists in specifying the
234 source(s) triggering the capture (timer register update event,
235 external event, timer output set/reset event, other HRTIM
236 timer related events).
237 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
238 output mainly consists in:
239 (+++)Setting the output polarity (active high or active low),
240 (+++)Defining the set/reset crossbar for the output,
241 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
242
243 (#) Set waveform timer output(s) level
244 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
245 active or inactive level. For example, when deadtime insertion
246 is enabled it is necessary to force the output level by software
247 to have the outputs in a complementary state as soon as the RUN mode is entered.
248
249 (#) Enable or Disable waveform timer output(s)
250 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
251
252 (#) Start or Stop waveform HRTIM timer(s).
253 (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
254 (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
255 (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
256 (#) Burst mode controller enabling:
257 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
258 burst mode controller.
259
260 (#) Some HRTIM operations can be triggered by software:
261 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
262 trigs the burst operation.
263 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
264 capture of the HRTIM timer counter.
265 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
266 update of the pre-loadable registers of the HRTIM timer
267 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
268 HRTIM timer counter.
269
270 (#) Some functions can be used any time to retrieve HRTIM timer related
271 information
272 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
273 capture register of the designated capture unit.
274 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
275 (ACTIVE/INACTIVE) of the designated timer output.
276 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
277 (IDLE/RUN/FAULT) of the designated timer output.
278 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
279 (ACTIVE/INACTIVE) of the designated output when the delayed
280 protection was triggered.
281 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
282 (ACTIVE/INACTIVE) of the burst mode controller.
283 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
284 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
285 the push-pull status indicates on which output the signal is currently
286 active (e.g signal applied on output 1 and output 2 forced
287 inactive or vice versa).
288 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
289 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
290 the idle push-pull status indicates during which period the
291 delayed protection request occurred (e.g. protection occurred
292 when the output 1 was active and output 2 forced inactive or
293 vice versa).
294
295 (#) Some functions can be used any time to retrieve actual HRTIM status
296 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
297
298 *** Callback registration ***
299 =============================
300 [..]
301 The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
302 allows the user to configure dynamically the driver callbacks.
303 Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
304 to register an interrupt callback.
305
306 [..]
307 Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
308 (+) Fault1Callback : Fault 1 interrupt callback function
309 (+) Fault2Callback : Fault 2 interrupt callback function
310 (+) Fault3Callback : Fault 3 interrupt callback function
311 (+) Fault4Callback : Fault 4 interrupt callback function
312 (+) Fault5Callback : Fault 5 interrupt callback function
313 (+) SystemFaultCallback : System fault interrupt callback function
314 (+) DLLCalibrationReadyCallback : DLL Ready interrupt callback function
315 (+) BurstModePeriodCallback : Burst mode period interrupt callback function
316 (+) SynchronizationEventCallback : Sync Input interrupt callback function
317 (+) ErrorCallback : DMA error callback function
318 (+) MspInitCallback : HRTIM MspInit callback function
319 (+) MspDeInitCallback : HRTIM MspInit callback function
320
321 [..]
322 Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
323 (+) RegistersUpdateCallback : Timer x Update interrupt callback function
324 (+) RepetitionEventCallback : Timer x Repetition interrupt callback function
325 (+) Compare1EventCallback : Timer x Compare 1 match interrupt callback function
326 (+) Compare2EventCallback : Timer x Compare 2 match interrupt callback function
327 (+) Compare3EventCallback : Timer x Compare 3 match interrupt callback function
328 (+) Compare4EventCallback : Timer x Compare 4 match interrupt callback function
329 (+) Capture1EventCallback : Timer x Capture 1 interrupts callback function
330 (+) Capture2EventCallback : Timer x Capture 2 interrupts callback function
331 (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
332 (+) CounterResetCallback : Timer x counter reset/roll-over interrupt callback function
333 (+) Output1SetCallback : Timer x output 1 set interrupt callback function
334 (+) Output1ResetCallback : Timer x output 1 reset interrupt callback function
335 (+) Output2SetCallback : Timer x output 2 set interrupt callback function
336 (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
337 (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
338
339 [..]
340 Both functions take as parameters the HAL peripheral handle, the Callback ID
341 and a pointer to the user callback function.
342
343 [..]
344 Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
345 to reset a callback to the default weak function. Both functions take as parameters
346 the HAL peripheral handle and the Callback ID.
347
348 [..]
349 By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
350 all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
351 Exception done for MspInit and MspDeInit functions that are reset to the legacy
352 weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
353 callbacks are null (not registered beforehand). If MspInit or MspDeInit are
354 not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
355 MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
356
357 [..]
358 Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
359 Exception done MspInit/MspDeInit functions that can be registered/unregistered
360 in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
361 (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
362 Then, the user first registers the MspInit/MspDeInit user callbacks
363 using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
364 or HAL_HRTIM_Init() function.
365
366 [..]
367 When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
368 not defined, the callback registration feature is not available and all
369 callbacks are set to the corresponding weak functions.
370
371 @endverbatim
372 ******************************************************************************
373 */
374
375 /* Includes ------------------------------------------------------------------*/
376 #include "stm32f3xx_hal.h"
377
378 /** @addtogroup STM32F3xx_HAL_Driver
379 * @{
380 */
381
382 #ifdef HAL_HRTIM_MODULE_ENABLED
383
384 #if defined(HRTIM1)
385
386 /** @defgroup HRTIM HRTIM
387 * @brief HRTIM HAL module driver
388 * @{
389 */
390
391 /* Private typedef -----------------------------------------------------------*/
392 /* Private define ------------------------------------------------------------*/
393 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
394 * @{
395 */
396 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
397 HRTIM_FLTR_FLT2EN |\
398 HRTIM_FLTR_FLT3EN |\
399 HRTIM_FLTR_FLT4EN | \
400 HRTIM_FLTR_FLT5EN)
401
402 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
403 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
404 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
405 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
406 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
407 HRTIM_TIMUPDATETRIGGER_TIMER_E)
408
409 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
410 (HRTIM_FAULTLOCK_READONLY << 8U) | \
411 (HRTIM_FAULTLOCK_READONLY << 16U) | \
412 (HRTIM_FAULTLOCK_READONLY << 24U))
413
414 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
415 (HRTIM_FAULTLOCK_READONLY << 8U))
416 /**
417 * @}
418 */
419
420 /* Private macro -------------------------------------------------------------*/
421 /* Private variables ---------------------------------------------------------*/
422 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
423 * @{
424 */
425 static uint32_t TimerIdxToTimerId[] =
426 {
427 HRTIM_TIMERID_TIMER_A,
428 HRTIM_TIMERID_TIMER_B,
429 HRTIM_TIMERID_TIMER_C,
430 HRTIM_TIMERID_TIMER_D,
431 HRTIM_TIMERID_TIMER_E,
432 HRTIM_TIMERID_MASTER,
433 };
434 /**
435 * @}
436 */
437
438 /* Private function prototypes -----------------------------------------------*/
439 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
440 * @{
441 */
442 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
443 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
444
445 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
446 uint32_t TimerIdx,
447 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
448
449 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
450 const HRTIM_TimerCfgTypeDef * pTimerCfg);
451
452 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
453 uint32_t TimerIdx,
454 const HRTIM_TimerCfgTypeDef * pTimerCfg);
455
456
457 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
458 uint32_t TimerIdx,
459 uint32_t CaptureUnit,
460 uint32_t Event);
461
462 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
463 uint32_t TimerIdx,
464 uint32_t Output,
465 const HRTIM_OutputCfgTypeDef * pOutputCfg);
466
467 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
468 uint32_t Event,
469 const HRTIM_EventCfgTypeDef * pEventCfg);
470
471 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
472 uint32_t TimerIdx,
473 uint32_t Event);
474
475 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
476 uint32_t TimerIdx,
477 uint32_t OCChannel);
478
479 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
480 uint32_t TimerIdx,
481 uint32_t OCChannel);
482
483 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
484 uint32_t TimerIdx);
485
486 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
487 const DMA_HandleTypeDef * hdma);
488
489 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
490 uint32_t TimerIdx);
491
492 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
493
494 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
495
496 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
497 uint32_t TimerIdx);
498
499 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
500
501 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
502
503 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
504
505 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
506 /**
507 * @}
508 */
509
510 /* Exported functions ---------------------------------------------------------*/
511 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
512 * @{
513 */
514
515 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
516 * @brief Initialization and Configuration functions
517 @verbatim
518 ===============================================================================
519 ##### Initialization and Time Base Configuration functions #####
520 ===============================================================================
521 [..] This section provides functions allowing to:
522 (+) Initialize a HRTIM instance
523 (+) De-initialize a HRTIM instance
524 (+) Initialize the HRTIM MSP
525 (+) De-initialize the HRTIM MSP
526 (+) Start the high-resolution unit (start DLL calibration)
527 (+) Check that the high resolution unit is ready (DLL calibration done)
528 (+) Configure the time base unit of a HRTIM timer
529
530 @endverbatim
531 * @{
532 */
533
534 /**
535 * @brief Initialize a HRTIM instance
536 * @param hhrtim pointer to HAL HRTIM handle
537 * @retval HAL status
538 */
HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)539 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
540 {
541 uint8_t timer_idx;
542 uint32_t hrtim_mcr;
543
544 /* Check the HRTIM handle allocation */
545 if(hhrtim == NULL)
546 {
547 return HAL_ERROR;
548 }
549
550 /* Check the parameters */
551 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
552 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
553
554 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
555 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
556 {
557 /* Initialize callback function pointers to their default values */
558 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
559 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
560 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
561 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
562 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
563 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
564 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
565 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
566 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
567 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
568 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
569 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
570 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
571 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
572 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
573 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
574 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
575 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
576 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
577 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
578 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
579 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
580 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
581 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
582 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
583
584 if (hhrtim->MspInitCallback == NULL)
585 {
586 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
587 }
588 }
589 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
590
591 /* Set the HRTIM state */
592 hhrtim->State = HAL_HRTIM_STATE_BUSY;
593
594 /* Initialize the DMA handles */
595 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
596 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
597 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
598 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
599 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
600 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
601
602 /* HRTIM output synchronization configuration (if required) */
603 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
604 {
605 /* Check parameters */
606 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
607 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
608
609 /* The synchronization output initialization procedure must be done prior
610 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
611 */
612 if (hhrtim->Instance == HRTIM1)
613 {
614 /* Enable the HRTIM peripheral clock */
615 __HAL_RCC_HRTIM1_CLK_ENABLE();
616 }
617
618 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
619
620 /* Set the event to be sent on the synchronization output */
621 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
622 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
623
624 /* Set the polarity of the synchronization output */
625 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
626 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
627
628 /* Update the HRTIM registers */
629 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
630 }
631
632 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
633 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
634 hhrtim->MspInitCallback(hhrtim);
635 #else
636 HAL_HRTIM_MspInit(hhrtim);
637 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
638
639 /* HRTIM input synchronization configuration (if required) */
640 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
641 {
642 /* Check parameters */
643 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
644
645 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
646
647 /* Set the synchronization input source */
648 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
649 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
650
651 /* Update the HRTIM registers */
652 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
653 }
654
655 /* Initialize the HRTIM state*/
656 hhrtim->State = HAL_HRTIM_STATE_READY;
657
658 /* Initialize the lock status of the HRTIM HAL API */
659 __HAL_UNLOCK(hhrtim);
660
661 /* Initialize timer related parameters */
662 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
663 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
664 timer_idx++)
665 {
666 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
667 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
668 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
669 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
670 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
671 hhrtim->TimerParam[timer_idx].DMASize = 0U;
672 }
673
674 return HAL_OK;
675 }
676
677 /**
678 * @brief De-initialize a HRTIM instance
679 * @param hhrtim pointer to HAL HRTIM handle
680 * @retval HAL status
681 */
HAL_HRTIM_DeInit(HRTIM_HandleTypeDef * hhrtim)682 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
683 {
684 /* Check the HRTIM handle allocation */
685 if(hhrtim == NULL)
686 {
687 return HAL_ERROR;
688 }
689
690 /* Check the parameters */
691 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
692
693 /* Set the HRTIM state */
694 hhrtim->State = HAL_HRTIM_STATE_BUSY;
695
696 /* DeInit the low level hardware */
697 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
698 if (hhrtim->MspDeInitCallback == NULL)
699 {
700 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
701 }
702
703 hhrtim->MspDeInitCallback(hhrtim);
704 #else
705 HAL_HRTIM_MspDeInit(hhrtim);
706 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
707
708 hhrtim->State = HAL_HRTIM_STATE_READY;
709
710 return HAL_OK;
711 }
712
713 /**
714 * @brief MSP initialization for a HRTIM instance
715 * @param hhrtim pointer to HAL HRTIM handle
716 * @retval None
717 */
HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)718 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
719 {
720 /* Prevent unused argument(s) compilation warning */
721 UNUSED(hhrtim);
722
723 /* NOTE: This function should not be modified, when the callback is needed,
724 the HAL_HRTIM_MspInit could be implemented in the user file
725 */
726 }
727
728 /**
729 * @brief MSP de-initialization of a HRTIM instance
730 * @param hhrtim pointer to HAL HRTIM handle
731 * @retval None
732 */
HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)733 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
734 {
735 /* Prevent unused argument(s) compilation warning */
736 UNUSED(hhrtim);
737
738 /* NOTE: This function should not be modified, when the callback is needed,
739 the HAL_HRTIM_MspDeInit could be implemented in the user file
740 */
741 }
742
743 /**
744 * @brief Start the DLL calibration
745 * @param hhrtim pointer to HAL HRTIM handle
746 * @param CalibrationRate DLL calibration period
747 * This parameter can be one of the following values:
748 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
749 * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.300 ms
750 * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=0.910 ms
751 * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=0.114 ms
752 * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=0.014 ms
753 * @retval HAL status
754 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
755 * within the HAL_HRTIM_PollForDLLCalibration function, just before
756 * exiting the function.
757 */
HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,uint32_t CalibrationRate)758 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
759 uint32_t CalibrationRate)
760 {
761 /* Check the parameters */
762 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
763
764 /* Process Locked */
765 __HAL_LOCK(hhrtim);
766
767 hhrtim->State = HAL_HRTIM_STATE_BUSY;
768
769 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
770 {
771 /* One shot DLL calibration */
772 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
773 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
774 }
775 else
776 {
777 /* Periodic DLL calibration */
778 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
779 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
780 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
781 }
782
783 /* Set HRTIM state */
784 hhrtim->State = HAL_HRTIM_STATE_READY;
785
786 return HAL_OK;
787 }
788
789 /**
790 * @brief Start the DLL calibration.
791 * DLL ready interrupt is enabled
792 * @param hhrtim pointer to HAL HRTIM handle
793 * @param CalibrationRate DLL calibration period
794 * This parameter can be one of the following values:
795 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
796 * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.300 ms
797 * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=0.910 ms
798 * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=0.114 ms
799 * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=0.014 ms
800 * @retval HAL status
801 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
802 * within the IRQ processing function when processing the DLL ready
803 * interrupt.
804 * @note If this function is called for periodic calibration, the DLLRDY
805 * interrupt is generated every time the calibration completes which
806 * will significantly increases the overall interrupt rate.
807 */
HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t CalibrationRate)808 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
809 uint32_t CalibrationRate)
810 {
811 /* Check the parameters */
812 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
813
814 /* Process Locked */
815 __HAL_LOCK(hhrtim);
816
817 hhrtim->State = HAL_HRTIM_STATE_BUSY;
818
819 /* Enable DLL Ready interrupt flag */
820 __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
821
822 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
823 {
824 /* One shot DLL calibration */
825 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
826 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
827 }
828 else
829 {
830 /* Periodic DLL calibration */
831 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
832 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
833 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
834 }
835
836 /* Set HRTIM state */
837 hhrtim->State = HAL_HRTIM_STATE_READY;
838
839 return HAL_OK;
840 }
841
842 /**
843 * @brief Poll the DLL calibration ready flag and returns when the flag is
844 * set (DLL calibration completed) or upon timeout expiration.
845 * @param hhrtim pointer to HAL HRTIM handle
846 * @param Timeout Timeout duration in millisecond
847 * @retval HAL status
848 */
HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,uint32_t Timeout)849 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
850 uint32_t Timeout)
851 {
852 uint32_t tickstart;
853
854 tickstart = HAL_GetTick();
855
856 /* Check End of conversion flag */
857 while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
858 {
859 if (Timeout != HAL_MAX_DELAY)
860 {
861 if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
862 {
863 hhrtim->State = HAL_HRTIM_STATE_ERROR;
864 return HAL_TIMEOUT;
865 }
866 }
867 }
868
869 /* Set HRTIM State */
870 hhrtim->State = HAL_HRTIM_STATE_READY;
871
872 /* Process unlocked */
873 __HAL_UNLOCK(hhrtim);
874
875 return HAL_OK;
876 }
877
878 /**
879 * @brief Configure the time base unit of a timer
880 * @param hhrtim pointer to HAL HRTIM handle
881 * @param TimerIdx Timer index
882 * This parameter can be one of the following values:
883 * @arg HRTIM_TIMERINDEX_MASTER for master timer
884 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
885 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
886 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
887 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
888 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
889 * @param pTimeBaseCfg pointer to the time base configuration structure
890 * @note This function must be called prior starting the timer
891 * @note The time-base unit initialization parameters specify:
892 * The timer counter operating mode (continuous, one shot),
893 * The timer clock prescaler,
894 * The timer period,
895 * The timer repetition counter.
896 * @retval HAL status
897 */
HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)898 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
899 uint32_t TimerIdx,
900 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
901 {
902 /* Check the parameters */
903 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
904 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
905 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
906
907 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
908 {
909 return HAL_BUSY;
910 }
911
912 /* Set the HRTIM state */
913 hhrtim->State = HAL_HRTIM_STATE_BUSY;
914
915 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
916 {
917 /* Configure master timer time base unit */
918 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
919 }
920 else
921 {
922 /* Configure timing unit time base unit */
923 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
924 }
925
926 /* Set HRTIM state */
927 hhrtim->State = HAL_HRTIM_STATE_READY;
928
929 return HAL_OK;
930 }
931
932 /**
933 * @}
934 */
935
936 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
937 * @brief Simple time base mode functions.
938 @verbatim
939 ===============================================================================
940 ##### Simple time base mode functions #####
941 ===============================================================================
942 [..] This section provides functions allowing to:
943 (+) Start simple time base
944 (+) Stop simple time base
945 (+) Start simple time base and enable interrupt
946 (+) Stop simple time base and disable interrupt
947 (+) Start simple time base and enable DMA transfer
948 (+) Stop simple time base and disable DMA transfer
949 -@- When a HRTIM timer operates in simple time base mode, the timer
950 counter counts from 0 to the period value.
951
952 @endverbatim
953 * @{
954 */
955
956 /**
957 * @brief Start the counter of a timer operating in simple time base mode.
958 * @param hhrtim pointer to HAL HRTIM handle
959 * @param TimerIdx Timer index.
960 * This parameter can be one of the following values:
961 * @arg HRTIM_TIMERINDEX_MASTER for master timer
962 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
963 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
964 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
965 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
966 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
967 * @retval HAL status
968 */
HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)969 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
970 uint32_t TimerIdx)
971 {
972 /* Check the parameters */
973 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
974
975 /* Process Locked */
976 __HAL_LOCK(hhrtim);
977
978 hhrtim->State = HAL_HRTIM_STATE_BUSY;
979
980 /* Enable the timer counter */
981 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
982
983 hhrtim->State = HAL_HRTIM_STATE_READY;
984
985 /* Process Unlocked */
986 __HAL_UNLOCK(hhrtim);
987
988 return HAL_OK;
989 }
990
991 /**
992 * @brief Stop the counter of a timer operating in simple time base mode.
993 * @param hhrtim pointer to HAL HRTIM handle
994 * @param TimerIdx Timer index.
995 * This parameter can be one of the following values:
996 * @arg HRTIM_TIMERINDEX_MASTER for master timer
997 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
998 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
999 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1000 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1001 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1002 * @retval HAL status
1003 */
HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1004 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
1005 uint32_t TimerIdx)
1006 {
1007 /* Check the parameters */
1008 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1009
1010 /* Process Locked */
1011 __HAL_LOCK(hhrtim);
1012
1013 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1014
1015 /* Disable the timer counter */
1016 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1017
1018 hhrtim->State = HAL_HRTIM_STATE_READY;
1019
1020 /* Process Unlocked */
1021 __HAL_UNLOCK(hhrtim);
1022
1023 return HAL_OK;
1024 }
1025
1026 /**
1027 * @brief Start the counter of a timer operating in simple time base mode
1028 * (Timer repetition interrupt is enabled).
1029 * @param hhrtim pointer to HAL HRTIM handle
1030 * @param TimerIdx Timer index.
1031 * This parameter can be one of the following values:
1032 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1033 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1034 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1035 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1036 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1037 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1038 * @retval HAL status
1039 */
HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1040 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
1041 uint32_t TimerIdx)
1042 {
1043 /* Check the parameters */
1044 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1045
1046 /* Process Locked */
1047 __HAL_LOCK(hhrtim);
1048
1049 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1050
1051 /* Enable the repetition interrupt */
1052 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1053 {
1054 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1055 }
1056 else
1057 {
1058 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1059 }
1060
1061 /* Enable the timer counter */
1062 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1063
1064 hhrtim->State = HAL_HRTIM_STATE_READY;
1065
1066 /* Process Unlocked */
1067 __HAL_UNLOCK(hhrtim);
1068
1069 return HAL_OK;
1070 }
1071
1072 /**
1073 * @brief Stop the counter of a timer operating in simple time base mode
1074 * (Timer repetition interrupt is disabled).
1075 * @param hhrtim pointer to HAL HRTIM handle
1076 * @param TimerIdx Timer index.
1077 * This parameter can be one of the following values:
1078 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1079 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1080 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1081 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1082 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1083 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1084 * @retval HAL status
1085 */
HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1086 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
1087 uint32_t TimerIdx)
1088 {
1089 /* Check the parameters */
1090 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1091
1092 /* Process Locked */
1093 __HAL_LOCK(hhrtim);
1094
1095 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1096
1097 /* Disable the repetition interrupt */
1098 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1099 {
1100 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1101 }
1102 else
1103 {
1104 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1105 }
1106
1107 /* Disable the timer counter */
1108 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1109
1110 hhrtim->State = HAL_HRTIM_STATE_READY;
1111
1112 /* Process Unlocked */
1113 __HAL_UNLOCK(hhrtim);
1114
1115 return HAL_OK;
1116 }
1117
1118 /**
1119 * @brief Start the counter of a timer operating in simple time base mode
1120 * (Timer repetition DMA request is enabled).
1121 * @param hhrtim pointer to HAL HRTIM handle
1122 * @param TimerIdx Timer index.
1123 * This parameter can be one of the following values:
1124 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1125 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1126 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1127 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1128 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1129 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1130 * @param SrcAddr DMA transfer source address
1131 * @param DestAddr DMA transfer destination address
1132 * @param Length The length of data items (data size) to be transferred
1133 * from source to destination
1134 */
HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1135 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1136 uint32_t TimerIdx,
1137 uint32_t SrcAddr,
1138 uint32_t DestAddr,
1139 uint32_t Length)
1140 {
1141 DMA_HandleTypeDef * hdma;
1142
1143 /* Check the parameters */
1144 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1145
1146 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1147 {
1148 return HAL_BUSY;
1149 }
1150 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1151 {
1152 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1153 {
1154 return HAL_ERROR;
1155 }
1156 else
1157 {
1158 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1159 }
1160 }
1161
1162 /* Process Locked */
1163 __HAL_LOCK(hhrtim);
1164
1165 /* Get the timer DMA handler */
1166 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1167
1168 if (hdma == NULL)
1169 {
1170 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1171
1172 /* Process Unlocked */
1173 __HAL_UNLOCK(hhrtim);
1174
1175 return HAL_ERROR;
1176 }
1177
1178 /* Set the DMA transfer completed callback */
1179 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1180 {
1181 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1182 }
1183 else
1184 {
1185 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1186 }
1187
1188 /* Set the DMA error callback */
1189 hdma->XferErrorCallback = HRTIM_DMAError ;
1190
1191 /* Enable the DMA channel */
1192 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1193 {
1194 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1195
1196 /* Process Unlocked */
1197 __HAL_UNLOCK(hhrtim);
1198
1199 return HAL_ERROR;
1200 }
1201
1202 /* Enable the timer repetition DMA request */
1203 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1204 {
1205 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1206 }
1207 else
1208 {
1209 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1210 }
1211
1212 /* Enable the timer counter */
1213 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1214
1215 hhrtim->State = HAL_HRTIM_STATE_READY;
1216
1217 /* Process Unlocked */
1218 __HAL_UNLOCK(hhrtim);
1219
1220 return HAL_OK;
1221 }
1222
1223 /**
1224 * @brief Stop the counter of a timer operating in simple time base mode
1225 * (Timer repetition DMA request is disabled).
1226 * @param hhrtim pointer to HAL HRTIM handle
1227 * @param TimerIdx Timer index.
1228 * This parameter can be one of the following values:
1229 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1230 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1231 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1232 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1233 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1234 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1235 * @retval HAL status
1236 */
HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1237 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1238 uint32_t TimerIdx)
1239 {
1240 DMA_HandleTypeDef * hdma;
1241
1242 /* Check the parameters */
1243 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1244
1245 /* Process Locked */
1246 __HAL_LOCK(hhrtim);
1247
1248 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1249 {
1250 hhrtim->State = HAL_HRTIM_STATE_READY;
1251
1252 /* Disable the DMA */
1253 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1254 {
1255 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1256 }
1257 /* Disable the timer repetition DMA request */
1258 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1259 }
1260 else
1261 {
1262 /* Get the timer DMA handler */
1263 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1264
1265 if (hdma == NULL)
1266 {
1267 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1268 }
1269 else
1270 {
1271 hhrtim->State = HAL_HRTIM_STATE_READY;
1272
1273 /* Disable the DMA */
1274 if (HAL_DMA_Abort(hdma) != HAL_OK)
1275 {
1276 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1277 }
1278
1279 /* Disable the timer repetition DMA request */
1280 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1281 }
1282 }
1283
1284 /* Disable the timer counter */
1285 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1286
1287 /* Process Unlocked */
1288 __HAL_UNLOCK(hhrtim);
1289
1290 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1291 {
1292 return HAL_ERROR;
1293 }
1294 else
1295 {
1296 return HAL_OK;
1297 }
1298 }
1299
1300 /**
1301 * @}
1302 */
1303
1304 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1305 * @brief Simple output compare functions
1306 @verbatim
1307 ===============================================================================
1308 ##### Simple output compare functions #####
1309 ===============================================================================
1310 [..] This section provides functions allowing to:
1311 (+) Configure simple output channel
1312 (+) Start simple output compare
1313 (+) Stop simple output compare
1314 (+) Start simple output compare and enable interrupt
1315 (+) Stop simple output compare and disable interrupt
1316 (+) Start simple output compare and enable DMA transfer
1317 (+) Stop simple output compare and disable DMA transfer
1318 -@- When a HRTIM timer operates in simple output compare mode
1319 the output level is set to a programmable value when a match
1320 is found between the compare register and the counter.
1321 Compare unit 1 is automatically associated to output 1
1322 Compare unit 2 is automatically associated to output 2
1323 @endverbatim
1324 * @{
1325 */
1326
1327 /**
1328 * @brief Configure an output in simple output compare mode
1329 * @param hhrtim pointer to HAL HRTIM handle
1330 * @param TimerIdx Timer index
1331 * This parameter can be one of the following values:
1332 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1333 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1334 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1335 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1336 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1337 * @param OCChannel Timer output
1338 * This parameter can be one of the following values:
1339 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1340 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1341 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1342 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1343 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1344 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1345 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1346 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1347 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1348 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1349 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1350 * @note When the timer operates in simple output compare mode:
1351 * Output 1 is implicitly controlled by the compare unit 1
1352 * Output 2 is implicitly controlled by the compare unit 2
1353 * Output Set/Reset crossbar is set according to the selected output compare mode:
1354 * Toggle: SETxyR = RSTxyR = CMPy
1355 * Active: SETxyR = CMPy, RSTxyR = 0
1356 * Inactive: SETxy =0, RSTxy = CMPy
1357 * @retval HAL status
1358 */
HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,const HRTIM_SimpleOCChannelCfgTypeDef * pSimpleOCChannelCfg)1359 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1360 uint32_t TimerIdx,
1361 uint32_t OCChannel,
1362 const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1363 {
1364 uint32_t CompareUnit = (uint32_t)RESET;
1365 HRTIM_OutputCfgTypeDef OutputCfg;
1366
1367 /* Check parameters */
1368 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1369 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1370 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1371 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1372 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1373
1374 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1375 {
1376 return HAL_BUSY;
1377 }
1378
1379 /* Process Locked */
1380 __HAL_LOCK(hhrtim);
1381
1382 /* Set HRTIM state */
1383 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1384
1385 /* Configure timer compare unit */
1386 switch (OCChannel)
1387 {
1388 case HRTIM_OUTPUT_TA1:
1389 case HRTIM_OUTPUT_TB1:
1390 case HRTIM_OUTPUT_TC1:
1391 case HRTIM_OUTPUT_TD1:
1392 case HRTIM_OUTPUT_TE1:
1393 {
1394 CompareUnit = HRTIM_COMPAREUNIT_1;
1395 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1396 break;
1397 }
1398 case HRTIM_OUTPUT_TA2:
1399 case HRTIM_OUTPUT_TB2:
1400 case HRTIM_OUTPUT_TC2:
1401 case HRTIM_OUTPUT_TD2:
1402 case HRTIM_OUTPUT_TE2:
1403 {
1404 CompareUnit = HRTIM_COMPAREUNIT_2;
1405 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1406 break;
1407 }
1408 default:
1409 {
1410 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1411
1412 /* Process Unlocked */
1413 __HAL_UNLOCK(hhrtim);
1414
1415 break;
1416 }
1417 }
1418
1419 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1420 {
1421 return HAL_ERROR;
1422 }
1423
1424 /* Configure timer output */
1425 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1426 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1427 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1428 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1429 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1430 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1431
1432 switch (pSimpleOCChannelCfg->Mode)
1433 {
1434 case HRTIM_BASICOCMODE_TOGGLE:
1435 {
1436 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1437 {
1438 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1439 }
1440 else
1441 {
1442 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1443 }
1444 OutputCfg.ResetSource = OutputCfg.SetSource;
1445 break;
1446 }
1447
1448 case HRTIM_BASICOCMODE_ACTIVE:
1449 {
1450 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1451 {
1452 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1453 }
1454 else
1455 {
1456 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1457 }
1458 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1459 break;
1460 }
1461
1462 case HRTIM_BASICOCMODE_INACTIVE:
1463 {
1464 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1465 {
1466 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1467 }
1468 else
1469 {
1470 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1471 }
1472 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1473 break;
1474 }
1475
1476 default:
1477 {
1478 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1479 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1480
1481 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1482
1483 /* Process Unlocked */
1484 __HAL_UNLOCK(hhrtim);
1485
1486 break;
1487 }
1488 }
1489
1490 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1491 {
1492 return HAL_ERROR;
1493 }
1494
1495 HRTIM_OutputConfig(hhrtim,
1496 TimerIdx,
1497 OCChannel,
1498 &OutputCfg);
1499
1500 /* Set HRTIM state */
1501 hhrtim->State = HAL_HRTIM_STATE_READY;
1502
1503 /* Process Unlocked */
1504 __HAL_UNLOCK(hhrtim);
1505
1506 return HAL_OK;
1507 }
1508
1509 /**
1510 * @brief Start the output compare signal generation on the designed timer output
1511 * @param hhrtim pointer to HAL HRTIM handle
1512 * @param TimerIdx Timer index
1513 * This parameter can be one of the following values:
1514 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1515 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1516 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1517 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1518 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1519 * @param OCChannel Timer output
1520 * This parameter can be one of the following values:
1521 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1522 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1523 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1524 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1525 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1526 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1527 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1528 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1529 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1530 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1531 * @retval HAL status
1532 */
HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1533 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1534 uint32_t TimerIdx,
1535 uint32_t OCChannel)
1536 {
1537 /* Check the parameters */
1538 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1539
1540 /* Process Locked */
1541 __HAL_LOCK(hhrtim);
1542
1543 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1544
1545 /* Enable the timer output */
1546 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1547
1548 /* Enable the timer counter */
1549 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1550
1551 hhrtim->State = HAL_HRTIM_STATE_READY;
1552
1553 /* Process Unlocked */
1554 __HAL_UNLOCK(hhrtim);
1555
1556 return HAL_OK;
1557 }
1558
1559 /**
1560 * @brief Stop the output compare signal generation on the designed timer output
1561 * @param hhrtim pointer to HAL HRTIM handle
1562 * @param TimerIdx Timer index
1563 * This parameter can be one of the following values:
1564 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1565 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1566 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1567 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1568 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1569 * @param OCChannel Timer output
1570 * This parameter can be one of the following values:
1571 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1572 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1573 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1574 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1575 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1576 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1577 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1578 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1579 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1580 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1581 * @retval HAL status
1582 */
HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1583 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1584 uint32_t TimerIdx,
1585 uint32_t OCChannel)
1586 {
1587 /* Check the parameters */
1588 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1589
1590 /* Process Locked */
1591 __HAL_LOCK(hhrtim);
1592
1593 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1594
1595 /* Disable the timer output */
1596 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1597
1598 /* Disable the timer counter */
1599 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1600
1601 hhrtim->State = HAL_HRTIM_STATE_READY;
1602
1603 /* Process Unlocked */
1604 __HAL_UNLOCK(hhrtim);
1605
1606 return HAL_OK;
1607 }
1608
1609 /**
1610 * @brief Start the output compare signal generation on the designed timer output
1611 * (Interrupt is enabled (see note note below)).
1612 * @param hhrtim pointer to HAL HRTIM handle
1613 * @param TimerIdx Timer index
1614 * This parameter can be one of the following values:
1615 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1616 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1617 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1618 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1619 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1620 * @param OCChannel Timer output
1621 * This parameter can be one of the following values:
1622 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1623 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1624 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1625 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1626 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1627 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1628 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1629 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1630 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1631 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1632 * @note Interrupt enabling depends on the chosen output compare mode
1633 * Output toggle: compare match interrupt is enabled
1634 * Output set active: output set interrupt is enabled
1635 * Output set inactive: output reset interrupt is enabled
1636 * @retval HAL status
1637 */
HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1638 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1639 uint32_t TimerIdx,
1640 uint32_t OCChannel)
1641 {
1642 uint32_t interrupt;
1643
1644 /* Check the parameters */
1645 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1646
1647 /* Process Locked */
1648 __HAL_LOCK(hhrtim);
1649
1650 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1651
1652 /* Get the interrupt to enable (depends on the output compare mode) */
1653 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1654
1655 /* Enable the timer output */
1656 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1657
1658 /* Enable the timer interrupt (depends on the output compare mode) */
1659 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1660
1661 /* Enable the timer counter */
1662 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1663
1664 hhrtim->State = HAL_HRTIM_STATE_READY;
1665
1666 /* Process Unlocked */
1667 __HAL_UNLOCK(hhrtim);
1668
1669 return HAL_OK;
1670 }
1671
1672 /**
1673 * @brief Stop the output compare signal generation on the designed timer output
1674 * (Interrupt is disabled).
1675 * @param hhrtim pointer to HAL HRTIM handle
1676 * @param TimerIdx Timer index
1677 * This parameter can be one of the following values:
1678 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1679 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1680 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1681 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1682 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1683 * @param OCChannel Timer output
1684 * This parameter can be one of the following values:
1685 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1686 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1687 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1688 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1689 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1690 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1691 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1692 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1693 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1694 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1695 * @retval HAL status
1696 */
HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1697 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1698 uint32_t TimerIdx,
1699 uint32_t OCChannel)
1700 {
1701 uint32_t interrupt;
1702
1703 /* Check the parameters */
1704 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1705
1706 /* Process Locked */
1707 __HAL_LOCK(hhrtim);
1708
1709 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1710
1711 /* Disable the timer output */
1712 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1713
1714 /* Get the interrupt to disable (depends on the output compare mode) */
1715 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1716
1717 /* Disable the timer interrupt */
1718 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1719
1720 /* Disable the timer counter */
1721 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1722
1723 hhrtim->State = HAL_HRTIM_STATE_READY;
1724
1725 /* Process Unlocked */
1726 __HAL_UNLOCK(hhrtim);
1727
1728 return HAL_OK;
1729 }
1730
1731 /**
1732 * @brief Start the output compare signal generation on the designed timer output
1733 * (DMA request is enabled (see note below)).
1734 * @param hhrtim pointer to HAL HRTIM handle
1735 * @param TimerIdx Timer index
1736 * This parameter can be one of the following values:
1737 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1738 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1739 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1740 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1741 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1742 * @param OCChannel Timer output
1743 * This parameter can be one of the following values:
1744 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1745 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1746 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1747 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1748 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1749 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1750 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1751 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1752 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1753 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1754 * @param SrcAddr DMA transfer source address
1755 * @param DestAddr DMA transfer destination address
1756 * @param Length The length of data items (data size) to be transferred
1757 * from source to destination
1758 * @note DMA request enabling depends on the chosen output compare mode
1759 * Output toggle: compare match DMA request is enabled
1760 * Output set active: output set DMA request is enabled
1761 * Output set inactive: output reset DMA request is enabled
1762 * @retval HAL status
1763 */
HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1764 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1765 uint32_t TimerIdx,
1766 uint32_t OCChannel,
1767 uint32_t SrcAddr,
1768 uint32_t DestAddr,
1769 uint32_t Length)
1770 {
1771 DMA_HandleTypeDef * hdma;
1772 uint32_t dma_request;
1773
1774 /* Check the parameters */
1775 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1776
1777 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1778 {
1779 return HAL_BUSY;
1780 }
1781 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1782 {
1783 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1784 {
1785 return HAL_ERROR;
1786 }
1787 else
1788 {
1789 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1790 }
1791 }
1792
1793 /* Process Locked */
1794 __HAL_LOCK(hhrtim);
1795
1796 /* Enable the timer output */
1797 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1798
1799 /* Get the DMA request to enable */
1800 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1801
1802 /* Get the timer DMA handler */
1803 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1804
1805 if (hdma == NULL)
1806 {
1807 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1808
1809 /* Process Unlocked */
1810 __HAL_UNLOCK(hhrtim);
1811
1812 return HAL_ERROR;
1813 }
1814
1815 /* Set the DMA error callback */
1816 hdma->XferErrorCallback = HRTIM_DMAError ;
1817
1818 /* Set the DMA transfer completed callback */
1819 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1820
1821 /* Enable the DMA channel */
1822 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1823 {
1824 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1825
1826 /* Process Unlocked */
1827 __HAL_UNLOCK(hhrtim);
1828
1829 return HAL_ERROR;
1830 }
1831
1832 /* Enable the timer DMA request */
1833 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1834
1835 /* Enable the timer counter */
1836 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1837
1838 hhrtim->State = HAL_HRTIM_STATE_READY;
1839
1840 /* Process Unlocked */
1841 __HAL_UNLOCK(hhrtim);
1842
1843 return HAL_OK;
1844 }
1845
1846 /**
1847 * @brief Stop the output compare signal generation on the designed timer output
1848 * (DMA request is disabled).
1849 * @param hhrtim pointer to HAL HRTIM handle
1850 * @param TimerIdx Timer index
1851 * This parameter can be one of the following values:
1852 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1853 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1854 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1855 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1856 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1857 * @param OCChannel Timer output
1858 * This parameter can be one of the following values:
1859 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1860 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1861 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1862 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1863 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1864 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1865 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1866 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1867 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1868 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1869 * @retval HAL status
1870 */
HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1871 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1872 uint32_t TimerIdx,
1873 uint32_t OCChannel)
1874 {
1875 uint32_t dma_request;
1876
1877 /* Check the parameters */
1878 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1879
1880 /* Process Locked */
1881 __HAL_LOCK(hhrtim);
1882
1883 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1884
1885 /* Disable the timer output */
1886 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1887
1888 /* Get the timer DMA handler */
1889 /* Disable the DMA */
1890 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1891 {
1892 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1893
1894 /* Process Unlocked */
1895 __HAL_UNLOCK(hhrtim);
1896
1897 return HAL_ERROR;
1898 }
1899
1900 /* Get the DMA request to disable */
1901 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1902
1903 /* Disable the timer DMA request */
1904 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1905
1906 /* Disable the timer counter */
1907 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1908
1909 hhrtim->State = HAL_HRTIM_STATE_READY;
1910
1911 /* Process Unlocked */
1912 __HAL_UNLOCK(hhrtim);
1913
1914 return HAL_OK;
1915 }
1916
1917 /**
1918 * @}
1919 */
1920
1921 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1922 * @brief Simple PWM output functions
1923 @verbatim
1924 ===============================================================================
1925 ##### Simple PWM output functions #####
1926 ===============================================================================
1927 [..] This section provides functions allowing to:
1928 (+) Configure simple PWM output channel
1929 (+) Start simple PWM output
1930 (+) Stop simple PWM output
1931 (+) Start simple PWM output and enable interrupt
1932 (+) Stop simple PWM output and disable interrupt
1933 (+) Start simple PWM output and enable DMA transfer
1934 (+) Stop simple PWM output and disable DMA transfer
1935 -@- When a HRTIM timer operates in simple PWM output mode
1936 the output level is set to a programmable value when a match is
1937 found between the compare register and the counter and reset when
1938 the timer period is reached. Duty cycle is determined by the
1939 comparison value.
1940 Compare unit 1 is automatically associated to output 1
1941 Compare unit 2 is automatically associated to output 2
1942 @endverbatim
1943 * @{
1944 */
1945
1946 /**
1947 * @brief Configure an output in simple PWM mode
1948 * @param hhrtim pointer to HAL HRTIM handle
1949 * @param TimerIdx Timer index
1950 * This parameter can be one of the following values:
1951 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1952 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1953 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1954 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1955 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1956 * @param PWMChannel Timer output
1957 * This parameter can be one of the following values:
1958 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1959 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1960 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1961 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1962 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1963 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1964 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1965 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1966 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1967 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1968 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
1969 * @note When the timer operates in simple PWM output mode:
1970 * Output 1 is implicitly controlled by the compare unit 1
1971 * Output 2 is implicitly controlled by the compare unit 2
1972 * Output Set/Reset crossbar is set as follows:
1973 * Output 1: SETx1R = CMP1, RSTx1R = PER
1974 * Output 2: SETx2R = CMP2, RST2R = PER
1975 * @note When Simple PWM mode is used the registers preload mechanism is
1976 * enabled (otherwise the behavior is not guaranteed).
1977 * @retval HAL status
1978 */
HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,const HRTIM_SimplePWMChannelCfgTypeDef * pSimplePWMChannelCfg)1979 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1980 uint32_t TimerIdx,
1981 uint32_t PWMChannel,
1982 const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
1983 {
1984 HRTIM_OutputCfgTypeDef OutputCfg;
1985 uint32_t hrtim_timcr;
1986
1987 /* Check parameters */
1988 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1989 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
1990 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
1991 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
1992
1993 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1994 {
1995 return HAL_BUSY;
1996 }
1997
1998 /* Process Locked */
1999 __HAL_LOCK(hhrtim);
2000
2001 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2002
2003 /* Configure timer compare unit */
2004 switch (PWMChannel)
2005 {
2006 case HRTIM_OUTPUT_TA1:
2007 case HRTIM_OUTPUT_TB1:
2008 case HRTIM_OUTPUT_TC1:
2009 case HRTIM_OUTPUT_TD1:
2010 case HRTIM_OUTPUT_TE1:
2011 {
2012 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
2013 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
2014 break;
2015 }
2016
2017 case HRTIM_OUTPUT_TA2:
2018 case HRTIM_OUTPUT_TB2:
2019 case HRTIM_OUTPUT_TC2:
2020 case HRTIM_OUTPUT_TD2:
2021 case HRTIM_OUTPUT_TE2:
2022 {
2023 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
2024 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
2025 break;
2026 }
2027 default:
2028 {
2029 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
2030 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
2031
2032 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2033
2034 /* Process Unlocked */
2035 __HAL_UNLOCK(hhrtim);
2036
2037 break;
2038 }
2039 }
2040
2041 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2042 {
2043 return HAL_ERROR;
2044 }
2045
2046 /* Configure timer output */
2047 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
2048 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
2049 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
2050 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
2051 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
2052 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
2053 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
2054
2055 HRTIM_OutputConfig(hhrtim,
2056 TimerIdx,
2057 PWMChannel,
2058 &OutputCfg);
2059
2060 /* Enable the registers preload mechanism */
2061 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
2062 hrtim_timcr |= HRTIM_TIMCR_PREEN;
2063 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
2064
2065 hhrtim->State = HAL_HRTIM_STATE_READY;
2066
2067 /* Process Unlocked */
2068 __HAL_UNLOCK(hhrtim);
2069
2070 return HAL_OK;
2071 }
2072
2073 /**
2074 * @brief Start the PWM output signal generation on the designed timer output
2075 * @param hhrtim pointer to HAL HRTIM handle
2076 * @param TimerIdx Timer index
2077 * This parameter can be one of the following values:
2078 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2079 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2080 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2081 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2082 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2083 * @param PWMChannel Timer output
2084 * This parameter can be one of the following values:
2085 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2086 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2087 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2088 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2089 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2090 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2091 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2092 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2093 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2094 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2095 * @retval HAL status
2096 */
HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2097 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
2098 uint32_t TimerIdx,
2099 uint32_t PWMChannel)
2100 {
2101 /* Check the parameters */
2102 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2103
2104 /* Process Locked */
2105 __HAL_LOCK(hhrtim);
2106
2107 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2108
2109 /* Enable the timer output */
2110 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2111
2112 /* Enable the timer counter */
2113 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2114
2115 hhrtim->State = HAL_HRTIM_STATE_READY;
2116
2117 /* Process Unlocked */
2118 __HAL_UNLOCK(hhrtim);
2119
2120 return HAL_OK;
2121 }
2122
2123 /**
2124 * @brief Stop the PWM output signal generation on the designed timer output
2125 * @param hhrtim pointer to HAL HRTIM handle
2126 * @param TimerIdx Timer index
2127 * This parameter can be one of the following values:
2128 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2129 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2130 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2131 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2132 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2133 * @param PWMChannel Timer output
2134 * This parameter can be one of the following values:
2135 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2136 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2137 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2138 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2139 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2140 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2141 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2142 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2143 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2144 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2145 * @retval HAL status
2146 */
HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2147 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
2148 uint32_t TimerIdx,
2149 uint32_t PWMChannel)
2150 {
2151 /* Check the parameters */
2152 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2153
2154 /* Process Locked */
2155 __HAL_LOCK(hhrtim);
2156
2157 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2158
2159 /* Disable the timer output */
2160 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2161
2162 /* Disable the timer counter */
2163 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2164
2165 hhrtim->State = HAL_HRTIM_STATE_READY;
2166
2167 /* Process Unlocked */
2168 __HAL_UNLOCK(hhrtim);
2169
2170 return HAL_OK;
2171 }
2172
2173 /**
2174 * @brief Start the PWM output signal generation on the designed timer output
2175 * (The compare interrupt is enabled).
2176 * @param hhrtim pointer to HAL HRTIM handle
2177 * @param TimerIdx Timer index
2178 * This parameter can be one of the following values:
2179 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2180 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2181 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2182 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2183 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2184 * @param PWMChannel Timer output
2185 * This parameter can be one of the following values:
2186 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2187 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2188 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2189 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2190 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2191 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2192 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2193 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2194 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2195 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2196 * @retval HAL status
2197 */
HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2198 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
2199 uint32_t TimerIdx,
2200 uint32_t PWMChannel)
2201 {
2202 /* Check the parameters */
2203 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2204
2205 /* Process Locked */
2206 __HAL_LOCK(hhrtim);
2207
2208 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2209
2210 /* Enable the timer output */
2211 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2212
2213 /* Enable the timer interrupt (depends on the PWM output) */
2214 switch (PWMChannel)
2215 {
2216 case HRTIM_OUTPUT_TA1:
2217 case HRTIM_OUTPUT_TB1:
2218 case HRTIM_OUTPUT_TC1:
2219 case HRTIM_OUTPUT_TD1:
2220 case HRTIM_OUTPUT_TE1:
2221 {
2222 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2223 break;
2224 }
2225
2226 case HRTIM_OUTPUT_TA2:
2227 case HRTIM_OUTPUT_TB2:
2228 case HRTIM_OUTPUT_TC2:
2229 case HRTIM_OUTPUT_TD2:
2230 case HRTIM_OUTPUT_TE2:
2231 {
2232 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2233 break;
2234 }
2235
2236 default:
2237 {
2238 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2239
2240 /* Process Unlocked */
2241 __HAL_UNLOCK(hhrtim);
2242
2243 break;
2244 }
2245 }
2246
2247 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2248 {
2249 return HAL_ERROR;
2250 }
2251
2252 /* Enable the timer counter */
2253 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2254
2255 hhrtim->State = HAL_HRTIM_STATE_READY;
2256
2257 /* Process Unlocked */
2258 __HAL_UNLOCK(hhrtim);
2259
2260 return HAL_OK;
2261 }
2262
2263 /**
2264 * @brief Stop the PWM output signal generation on the designed timer output
2265 * (The compare interrupt is disabled).
2266 * @param hhrtim pointer to HAL HRTIM handle
2267 * @param TimerIdx Timer index
2268 * This parameter can be one of the following values:
2269 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2270 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2271 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2272 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2273 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2274 * @param PWMChannel Timer output
2275 * This parameter can be one of the following values:
2276 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2277 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2278 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2279 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2280 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2281 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2282 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2283 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2284 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2285 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2286 * @retval HAL status
2287 */
HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2288 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2289 uint32_t TimerIdx,
2290 uint32_t PWMChannel)
2291 {
2292 /* Check the parameters */
2293 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2294
2295 /* Process Locked */
2296 __HAL_LOCK(hhrtim);
2297
2298 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2299
2300 /* Disable the timer output */
2301 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2302
2303 /* Disable the timer interrupt (depends on the PWM output) */
2304 switch (PWMChannel)
2305 {
2306 case HRTIM_OUTPUT_TA1:
2307 case HRTIM_OUTPUT_TB1:
2308 case HRTIM_OUTPUT_TC1:
2309 case HRTIM_OUTPUT_TD1:
2310 case HRTIM_OUTPUT_TE1:
2311 {
2312 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2313 break;
2314 }
2315
2316 case HRTIM_OUTPUT_TA2:
2317 case HRTIM_OUTPUT_TB2:
2318 case HRTIM_OUTPUT_TC2:
2319 case HRTIM_OUTPUT_TD2:
2320 case HRTIM_OUTPUT_TE2:
2321 {
2322 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2323 break;
2324 }
2325
2326 default:
2327 {
2328 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2329
2330 /* Process Unlocked */
2331 __HAL_UNLOCK(hhrtim);
2332
2333 break;
2334 }
2335 }
2336
2337 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2338 {
2339 return HAL_ERROR;
2340 }
2341
2342 /* Disable the timer counter */
2343 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2344
2345 hhrtim->State = HAL_HRTIM_STATE_READY;
2346
2347 /* Process Unlocked */
2348 __HAL_UNLOCK(hhrtim);
2349
2350 return HAL_OK;
2351 }
2352
2353 /**
2354 * @brief Start the PWM output signal generation on the designed timer output
2355 * (The compare DMA request is enabled).
2356 * @param hhrtim pointer to HAL HRTIM handle
2357 * @param TimerIdx Timer index
2358 * This parameter can be one of the following values:
2359 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2360 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2361 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2362 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2363 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2364 * @param PWMChannel Timer output
2365 * This parameter can be one of the following values:
2366 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2367 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2368 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2369 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2370 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2371 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2372 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2373 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2374 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2375 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2376 * @param SrcAddr DMA transfer source address
2377 * @param DestAddr DMA transfer destination address
2378 * @param Length The length of data items (data size) to be transferred
2379 * from source to destination
2380 * @retval HAL status
2381 */
HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)2382 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2383 uint32_t TimerIdx,
2384 uint32_t PWMChannel,
2385 uint32_t SrcAddr,
2386 uint32_t DestAddr,
2387 uint32_t Length)
2388 {
2389 DMA_HandleTypeDef * hdma;
2390
2391 /* Check the parameters */
2392 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2393
2394 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2395 {
2396 return HAL_BUSY;
2397 }
2398 if(hhrtim->State == HAL_HRTIM_STATE_READY)
2399 {
2400 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
2401 {
2402 return HAL_ERROR;
2403 }
2404 else
2405 {
2406 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2407 }
2408 }
2409
2410 /* Process Locked */
2411 __HAL_LOCK(hhrtim);
2412
2413 /* Enable the timer output */
2414 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2415
2416 /* Get the timer DMA handler */
2417 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2418
2419 if (hdma == NULL)
2420 {
2421 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2422
2423 /* Process Unlocked */
2424 __HAL_UNLOCK(hhrtim);
2425
2426 return HAL_ERROR;
2427 }
2428
2429 /* Set the DMA error callback */
2430 hdma->XferErrorCallback = HRTIM_DMAError ;
2431
2432 /* Set the DMA transfer completed callback */
2433 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2434
2435 /* Enable the DMA channel */
2436 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2437 {
2438 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2439
2440 /* Process Unlocked */
2441 __HAL_UNLOCK(hhrtim);
2442
2443 return HAL_ERROR;
2444 }
2445
2446 /* Enable the timer DMA request */
2447 switch (PWMChannel)
2448 {
2449 case HRTIM_OUTPUT_TA1:
2450 case HRTIM_OUTPUT_TB1:
2451 case HRTIM_OUTPUT_TC1:
2452 case HRTIM_OUTPUT_TD1:
2453 case HRTIM_OUTPUT_TE1:
2454 {
2455 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2456 break;
2457 }
2458
2459 case HRTIM_OUTPUT_TA2:
2460 case HRTIM_OUTPUT_TB2:
2461 case HRTIM_OUTPUT_TC2:
2462 case HRTIM_OUTPUT_TD2:
2463 case HRTIM_OUTPUT_TE2:
2464 {
2465 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2466 break;
2467 }
2468
2469 default:
2470 {
2471 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2472
2473 /* Process Unlocked */
2474 __HAL_UNLOCK(hhrtim);
2475
2476 break;
2477 }
2478 }
2479
2480 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2481 {
2482 return HAL_ERROR;
2483 }
2484
2485 /* Enable the timer counter */
2486 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2487
2488 hhrtim->State = HAL_HRTIM_STATE_READY;
2489
2490 /* Process Unlocked */
2491 __HAL_UNLOCK(hhrtim);
2492
2493 return HAL_OK;
2494 }
2495
2496 /**
2497 * @brief Stop the PWM output signal generation on the designed timer output
2498 * (The compare DMA request is disabled).
2499 * @param hhrtim pointer to HAL HRTIM handle
2500 * @param TimerIdx Timer index
2501 * This parameter can be one of the following values:
2502 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2503 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2504 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2505 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2506 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2507 * @param PWMChannel Timer output
2508 * This parameter can be one of the following values:
2509 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2510 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2511 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2512 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2513 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2514 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2515 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2516 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2517 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2518 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2519 * @retval HAL status
2520 */
HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2521 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2522 uint32_t TimerIdx,
2523 uint32_t PWMChannel)
2524 {
2525 /* Check the parameters */
2526 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2527
2528 /* Process Locked */
2529 __HAL_LOCK(hhrtim);
2530
2531 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2532
2533 /* Disable the timer output */
2534 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2535
2536 /* Get the timer DMA handler */
2537 /* Disable the DMA */
2538 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2539 {
2540 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2541
2542 /* Process Unlocked */
2543 __HAL_UNLOCK(hhrtim);
2544
2545 return HAL_ERROR;
2546 }
2547
2548 /* Disable the timer DMA request */
2549 switch (PWMChannel)
2550 {
2551 case HRTIM_OUTPUT_TA1:
2552 case HRTIM_OUTPUT_TB1:
2553 case HRTIM_OUTPUT_TC1:
2554 case HRTIM_OUTPUT_TD1:
2555 case HRTIM_OUTPUT_TE1:
2556 {
2557 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2558 break;
2559 }
2560
2561 case HRTIM_OUTPUT_TA2:
2562 case HRTIM_OUTPUT_TB2:
2563 case HRTIM_OUTPUT_TC2:
2564 case HRTIM_OUTPUT_TD2:
2565 case HRTIM_OUTPUT_TE2:
2566 {
2567 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2568 break;
2569 }
2570
2571 default:
2572 {
2573 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2574
2575 /* Process Unlocked */
2576 __HAL_UNLOCK(hhrtim);
2577
2578 break;
2579 }
2580 }
2581
2582 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2583 {
2584 return HAL_ERROR;
2585 }
2586
2587 /* Disable the timer counter */
2588 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2589
2590 hhrtim->State = HAL_HRTIM_STATE_READY;
2591
2592 /* Process Unlocked */
2593 __HAL_UNLOCK(hhrtim);
2594
2595 return HAL_OK;
2596 }
2597
2598 /**
2599 * @}
2600 */
2601
2602 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2603 * @brief Simple input capture functions
2604 @verbatim
2605 ===============================================================================
2606 ##### Simple input capture functions #####
2607 ===============================================================================
2608 [..] This section provides functions allowing to:
2609 (+) Configure simple input capture channel
2610 (+) Start simple input capture
2611 (+) Stop simple input capture
2612 (+) Start simple input capture and enable interrupt
2613 (+) Stop simple input capture and disable interrupt
2614 (+) Start simple input capture and enable DMA transfer
2615 (+) Stop simple input capture and disable DMA transfer
2616 -@- When a HRTIM timer operates in simple input capture mode
2617 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2618 value of the timer counter counter after a transition detected
2619 on a given external event input.
2620 @endverbatim
2621 * @{
2622 */
2623
2624 /**
2625 * @brief Configure a simple capture
2626 * @param hhrtim pointer to HAL HRTIM handle
2627 * @param TimerIdx Timer index
2628 * This parameter can be one of the following values:
2629 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2630 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2631 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2632 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2633 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2634 * @param CaptureChannel Capture unit
2635 * This parameter can be one of the following values:
2636 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2637 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2638 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2639 * @note When the timer operates in simple capture mode the capture is triggered
2640 * by the designated external event and GPIO input is implicitly used as event source.
2641 * The cature can be triggered by a rising edge, a falling edge or both
2642 * edges on event channel.
2643 * @retval HAL status
2644 */
HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,const HRTIM_SimpleCaptureChannelCfgTypeDef * pSimpleCaptureChannelCfg)2645 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2646 uint32_t TimerIdx,
2647 uint32_t CaptureChannel,
2648 const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2649 {
2650 HRTIM_EventCfgTypeDef EventCfg;
2651
2652 /* Check parameters */
2653 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2654 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2655 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2656 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2657 pSimpleCaptureChannelCfg->EventPolarity));
2658 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2659 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2660 pSimpleCaptureChannelCfg->EventFilter));
2661
2662 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2663 {
2664 return HAL_BUSY;
2665 }
2666
2667 /* Process Locked */
2668 __HAL_LOCK(hhrtim);
2669
2670 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2671
2672 /* Configure external event channel */
2673 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2674 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2675 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2676 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2677 EventCfg.Source = HRTIM_EVENTSRC_1;
2678
2679 HRTIM_EventConfig(hhrtim,
2680 pSimpleCaptureChannelCfg->Event,
2681 &EventCfg);
2682
2683 /* Memorize capture trigger (will be configured when the capture is started */
2684 HRTIM_CaptureUnitConfig(hhrtim,
2685 TimerIdx,
2686 CaptureChannel,
2687 pSimpleCaptureChannelCfg->Event);
2688
2689 hhrtim->State = HAL_HRTIM_STATE_READY;
2690
2691 /* Process Unlocked */
2692 __HAL_UNLOCK(hhrtim);
2693
2694 return HAL_OK;
2695 }
2696
2697 /**
2698 * @brief Enable a simple capture on the designed capture unit
2699 * @param hhrtim pointer to HAL HRTIM handle
2700 * @param TimerIdx Timer index
2701 * This parameter can be one of the following values:
2702 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2703 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2704 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2705 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2706 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2707 * @param CaptureChannel Timer output
2708 * This parameter can be one of the following values:
2709 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2710 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2711 * @retval HAL status
2712 * @note The external event triggering the capture is available for all timing
2713 * units. It can be used directly and is active as soon as the timing
2714 * unit counter is enabled.
2715 */
HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2716 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2717 uint32_t TimerIdx,
2718 uint32_t CaptureChannel)
2719 {
2720 /* Check the parameters */
2721 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2722 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2723
2724 /* Process Locked */
2725 __HAL_LOCK(hhrtim);
2726
2727 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2728
2729 /* Set the capture unit trigger */
2730 switch (CaptureChannel)
2731 {
2732 case HRTIM_CAPTUREUNIT_1:
2733 {
2734 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2735 break;
2736 }
2737
2738 case HRTIM_CAPTUREUNIT_2:
2739 {
2740 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2741 break;
2742 }
2743
2744 default:
2745 {
2746 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2747
2748 /* Process Unlocked */
2749 __HAL_UNLOCK(hhrtim);
2750
2751 break;
2752 }
2753 }
2754
2755 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2756 {
2757 return HAL_ERROR;
2758 }
2759
2760 /* Enable the timer counter */
2761 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2762
2763 hhrtim->State = HAL_HRTIM_STATE_READY;
2764
2765 /* Process Unlocked */
2766 __HAL_UNLOCK(hhrtim);
2767
2768 return HAL_OK;
2769 }
2770
2771 /**
2772 * @brief Disable a simple capture on the designed capture unit
2773 * @param hhrtim pointer to HAL HRTIM handle
2774 * @param TimerIdx Timer index
2775 * This parameter can be one of the following values:
2776 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2777 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2778 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2779 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2780 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2781 * @param CaptureChannel Timer output
2782 * This parameter can be one of the following values:
2783 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2784 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2785 * @retval HAL status
2786 */
HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2787 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2788 uint32_t TimerIdx,
2789 uint32_t CaptureChannel)
2790 {
2791 uint32_t hrtim_cpt1cr;
2792 uint32_t hrtim_cpt2cr;
2793
2794 /* Check the parameters */
2795 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2796 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2797
2798 /* Process Locked */
2799 __HAL_LOCK(hhrtim);
2800
2801 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2802
2803 /* Set the capture unit trigger */
2804 switch (CaptureChannel)
2805 {
2806 case HRTIM_CAPTUREUNIT_1:
2807 {
2808 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2809 break;
2810 }
2811
2812 case HRTIM_CAPTUREUNIT_2:
2813 {
2814 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2815 break;
2816 }
2817
2818 default:
2819 {
2820 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2821
2822 /* Process Unlocked */
2823 __HAL_UNLOCK(hhrtim);
2824
2825 break;
2826 }
2827 }
2828
2829 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2830 {
2831 return HAL_ERROR;
2832 }
2833
2834 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2835 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2836
2837 /* Disable the timer counter */
2838 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2839 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2840 {
2841 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2842 }
2843
2844 hhrtim->State = HAL_HRTIM_STATE_READY;
2845
2846 /* Process Unlocked */
2847 __HAL_UNLOCK(hhrtim);
2848
2849 return HAL_OK;
2850 }
2851
2852 /**
2853 * @brief Enable a simple capture on the designed capture unit
2854 * (Capture interrupt is enabled).
2855 * @param hhrtim pointer to HAL HRTIM handle
2856 * @param TimerIdx Timer index
2857 * This parameter can be one of the following values:
2858 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2859 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2860 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2861 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2862 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2863 * @param CaptureChannel Timer output
2864 * This parameter can be one of the following values:
2865 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2866 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2867 * @retval HAL status
2868 */
HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2869 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2870 uint32_t TimerIdx,
2871 uint32_t CaptureChannel)
2872 {
2873 /* Check the parameters */
2874 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2875 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2876
2877 /* Process Locked */
2878 __HAL_LOCK(hhrtim);
2879
2880 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2881
2882 /* Set the capture unit trigger */
2883 switch (CaptureChannel)
2884 {
2885 case HRTIM_CAPTUREUNIT_1:
2886 {
2887 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2888
2889 /* Enable the capture unit 1 interrupt */
2890 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2891 break;
2892 }
2893
2894 case HRTIM_CAPTUREUNIT_2:
2895 {
2896 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2897
2898 /* Enable the capture unit 2 interrupt */
2899 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2900 break;
2901 }
2902
2903 default:
2904 {
2905 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2906
2907 /* Process Unlocked */
2908 __HAL_UNLOCK(hhrtim);
2909
2910 break;
2911 }
2912 }
2913
2914 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2915 {
2916 return HAL_ERROR;
2917 }
2918
2919 /* Enable the timer counter */
2920 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2921
2922 hhrtim->State = HAL_HRTIM_STATE_READY;
2923
2924 /* Process Unlocked */
2925 __HAL_UNLOCK(hhrtim);
2926
2927 return HAL_OK;
2928 }
2929
2930 /**
2931 * @brief Disable a simple capture on the designed capture unit
2932 * (Capture interrupt is disabled).
2933 * @param hhrtim pointer to HAL HRTIM handle
2934 * @param TimerIdx Timer index
2935 * This parameter can be one of the following values:
2936 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2937 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2938 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2939 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2940 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2941 * @param CaptureChannel Timer output
2942 * This parameter can be one of the following values:
2943 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2944 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2945 * @retval HAL status
2946 */
HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2947 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
2948 uint32_t TimerIdx,
2949 uint32_t CaptureChannel)
2950 {
2951
2952 uint32_t hrtim_cpt1cr;
2953 uint32_t hrtim_cpt2cr;
2954
2955 /* Check the parameters */
2956 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2957 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2958
2959 /* Process Locked */
2960 __HAL_LOCK(hhrtim);
2961
2962 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2963
2964 /* Set the capture unit trigger */
2965 switch (CaptureChannel)
2966 {
2967 case HRTIM_CAPTUREUNIT_1:
2968 {
2969 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2970
2971 /* Disable the capture unit 1 interrupt */
2972 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2973 break;
2974 }
2975
2976 case HRTIM_CAPTUREUNIT_2:
2977 {
2978 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2979
2980 /* Disable the capture unit 2 interrupt */
2981 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2982 break;
2983 }
2984
2985 default:
2986 {
2987 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2988
2989 /* Process Unlocked */
2990 __HAL_UNLOCK(hhrtim);
2991
2992 break;
2993 }
2994 }
2995
2996 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2997 {
2998 return HAL_ERROR;
2999 }
3000
3001 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3002 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3003
3004 /* Disable the timer counter */
3005 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3006 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3007 {
3008 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3009 }
3010
3011 hhrtim->State = HAL_HRTIM_STATE_READY;
3012
3013 /* Process Unlocked */
3014 __HAL_UNLOCK(hhrtim);
3015
3016 return HAL_OK;
3017 }
3018
3019 /**
3020 * @brief Enable a simple capture on the designed capture unit
3021 * (Capture DMA request is enabled).
3022 * @param hhrtim pointer to HAL HRTIM handle
3023 * @param TimerIdx Timer index
3024 * This parameter can be one of the following values:
3025 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3026 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3027 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3028 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3029 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3030 * @param CaptureChannel Timer output
3031 * This parameter can be one of the following values:
3032 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3033 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3034 * @param SrcAddr DMA transfer source address
3035 * @param DestAddr DMA transfer destination address
3036 * @param Length The length of data items (data size) to be transferred
3037 * from source to destination
3038 * @retval HAL status
3039 */
HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)3040 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
3041 uint32_t TimerIdx,
3042 uint32_t CaptureChannel,
3043 uint32_t SrcAddr,
3044 uint32_t DestAddr,
3045 uint32_t Length)
3046 {
3047 DMA_HandleTypeDef * hdma;
3048
3049 /* Check the parameters */
3050 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3051 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3052
3053 /* Process Locked */
3054 __HAL_LOCK(hhrtim);
3055
3056 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3057
3058 /* Get the timer DMA handler */
3059 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
3060
3061 if (hdma == NULL)
3062 {
3063 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3064
3065 /* Process Unlocked */
3066 __HAL_UNLOCK(hhrtim);
3067
3068 return HAL_ERROR;
3069 }
3070
3071 /* Set the DMA error callback */
3072 hdma->XferErrorCallback = HRTIM_DMAError ;
3073
3074 /* Set the DMA transfer completed callback */
3075 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
3076
3077 /* Enable the DMA channel */
3078 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
3079 {
3080 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3081
3082 /* Process Unlocked */
3083 __HAL_UNLOCK(hhrtim);
3084
3085 return HAL_ERROR;
3086 }
3087
3088 switch (CaptureChannel)
3089 {
3090 case HRTIM_CAPTUREUNIT_1:
3091 {
3092 /* Set the capture unit trigger */
3093 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
3094
3095 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3096 break;
3097 }
3098
3099 case HRTIM_CAPTUREUNIT_2:
3100 {
3101 /* Set the capture unit trigger */
3102 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
3103
3104 /* Enable the timer DMA request */
3105 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3106 break;
3107 }
3108
3109 default:
3110 {
3111 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3112
3113 /* Process Unlocked */
3114 __HAL_UNLOCK(hhrtim);
3115
3116 break;
3117 }
3118 }
3119
3120 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3121 {
3122 return HAL_ERROR;
3123 }
3124
3125 /* Enable the timer counter */
3126 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3127
3128 hhrtim->State = HAL_HRTIM_STATE_READY;
3129
3130 /* Process Unlocked */
3131 __HAL_UNLOCK(hhrtim);
3132
3133 return HAL_OK;
3134 }
3135
3136 /**
3137 * @brief Disable a simple capture on the designed capture unit
3138 * (Capture DMA request is disabled).
3139 * @param hhrtim pointer to HAL HRTIM handle
3140 * @param TimerIdx Timer index
3141 * This parameter can be one of the following values:
3142 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3143 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3144 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3145 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3146 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3147 * @param CaptureChannel Timer output
3148 * This parameter can be one of the following values:
3149 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3150 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3151 * @retval HAL status
3152 */
HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)3153 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
3154 uint32_t TimerIdx,
3155 uint32_t CaptureChannel)
3156 {
3157
3158 uint32_t hrtim_cpt1cr;
3159 uint32_t hrtim_cpt2cr;
3160
3161 /* Check the parameters */
3162 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3163 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3164
3165 /* Process Locked */
3166 __HAL_LOCK(hhrtim);
3167
3168 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3169
3170 /* Get the timer DMA handler */
3171 /* Disable the DMA */
3172 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3173 {
3174 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3175
3176 /* Process Unlocked */
3177 __HAL_UNLOCK(hhrtim);
3178
3179 return HAL_ERROR;
3180 }
3181
3182 switch (CaptureChannel)
3183 {
3184 case HRTIM_CAPTUREUNIT_1:
3185 {
3186 /* Reset the capture unit trigger */
3187 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3188
3189 /* Disable the capture unit 1 DMA request */
3190 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3191 break;
3192 }
3193
3194 case HRTIM_CAPTUREUNIT_2:
3195 {
3196 /* Reset the capture unit trigger */
3197 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3198
3199 /* Disable the capture unit 2 DMA request */
3200 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3201 break;
3202 }
3203
3204 default:
3205 {
3206 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3207
3208 /* Process Unlocked */
3209 __HAL_UNLOCK(hhrtim);
3210
3211 break;
3212 }
3213 }
3214
3215 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3216 {
3217 return HAL_ERROR;
3218 }
3219
3220 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3221 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3222
3223 /* Disable the timer counter */
3224 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3225 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3226 {
3227 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3228 }
3229
3230 hhrtim->State = HAL_HRTIM_STATE_READY;
3231
3232 /* Process Unlocked */
3233 __HAL_UNLOCK(hhrtim);
3234
3235 return HAL_OK;
3236 }
3237
3238 /**
3239 * @}
3240 */
3241
3242 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3243 * @brief Simple one pulse functions
3244 @verbatim
3245 ===============================================================================
3246 ##### Simple one pulse functions #####
3247 ===============================================================================
3248 [..] This section provides functions allowing to:
3249 (+) Configure one pulse channel
3250 (+) Start one pulse generation
3251 (+) Stop one pulse generation
3252 (+) Start one pulse generation and enable interrupt
3253 (+) Stop one pulse generation and disable interrupt
3254 -@- When a HRTIM timer operates in simple one pulse mode
3255 the timer counter is started in response to transition detected
3256 on a given external event input to generate a pulse with a
3257 programmable length after a programmable delay.
3258 @endverbatim
3259 * @{
3260 */
3261
3262 /**
3263 * @brief Configure an output simple one pulse mode
3264 * @param hhrtim pointer to HAL HRTIM handle
3265 * @param TimerIdx Timer index
3266 * This parameter can be one of the following values:
3267 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3268 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3269 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3270 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3271 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3272 * @param OnePulseChannel Timer output
3273 * This parameter can be one of the following values:
3274 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3275 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3276 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3277 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3278 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3279 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3280 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3281 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3282 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3283 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3284 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
3285 * @note When the timer operates in simple one pulse mode:
3286 * the timer counter is implicitly started by the reset event,
3287 * the reset of the timer counter is triggered by the designated external event
3288 * GPIO input is implicitly used as event source,
3289 * Output 1 is implicitly controlled by the compare unit 1,
3290 * Output 2 is implicitly controlled by the compare unit 2.
3291 * Output Set/Reset crossbar is set as follows:
3292 * Output 1: SETx1R = CMP1, RSTx1R = PER
3293 * Output 2: SETx2R = CMP2, RST2R = PER
3294 * @retval HAL status
3295 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
3296 * outputs, the reset event related configuration data provided in the
3297 * second call will override the reset event related configuration data
3298 * provided in the first call.
3299 */
HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel,const HRTIM_SimpleOnePulseChannelCfgTypeDef * pSimpleOnePulseChannelCfg)3300 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
3301 uint32_t TimerIdx,
3302 uint32_t OnePulseChannel,
3303 const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
3304 {
3305 HRTIM_OutputCfgTypeDef OutputCfg;
3306 HRTIM_EventCfgTypeDef EventCfg;
3307
3308 /* Check parameters */
3309 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3310 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3311 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3312 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3313 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3314 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3315 pSimpleOnePulseChannelCfg->EventPolarity));
3316 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3317 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3318 pSimpleOnePulseChannelCfg->EventFilter));
3319
3320 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3321 {
3322 return HAL_BUSY;
3323 }
3324
3325 /* Process Locked */
3326 __HAL_LOCK(hhrtim);
3327
3328 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3329
3330 /* Configure timer compare unit */
3331 switch (OnePulseChannel)
3332 {
3333 case HRTIM_OUTPUT_TA1:
3334 case HRTIM_OUTPUT_TB1:
3335 case HRTIM_OUTPUT_TC1:
3336 case HRTIM_OUTPUT_TD1:
3337 case HRTIM_OUTPUT_TE1:
3338 {
3339 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3340 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3341 break;
3342 }
3343
3344 case HRTIM_OUTPUT_TA2:
3345 case HRTIM_OUTPUT_TB2:
3346 case HRTIM_OUTPUT_TC2:
3347 case HRTIM_OUTPUT_TD2:
3348 case HRTIM_OUTPUT_TE2:
3349 {
3350 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3351 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3352 break;
3353 }
3354
3355 default:
3356 {
3357 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
3358 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
3359
3360 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3361
3362 /* Process Unlocked */
3363 __HAL_UNLOCK(hhrtim);
3364
3365 break;
3366 }
3367 }
3368
3369 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3370 {
3371 return HAL_ERROR;
3372 }
3373
3374 /* Configure timer output */
3375 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3376 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3377 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3378 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3379 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3380 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3381 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3382
3383 HRTIM_OutputConfig(hhrtim,
3384 TimerIdx,
3385 OnePulseChannel,
3386 &OutputCfg);
3387
3388 /* Configure external event channel */
3389 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3390 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3391 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3392 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
3393 EventCfg.Source = HRTIM_EVENTSRC_1;
3394
3395 HRTIM_EventConfig(hhrtim,
3396 pSimpleOnePulseChannelCfg->Event,
3397 &EventCfg);
3398
3399 /* Configure the timer reset register */
3400 HRTIM_TIM_ResetConfig(hhrtim,
3401 TimerIdx,
3402 pSimpleOnePulseChannelCfg->Event);
3403
3404 hhrtim->State = HAL_HRTIM_STATE_READY;
3405
3406 /* Process Unlocked */
3407 __HAL_UNLOCK(hhrtim);
3408
3409 return HAL_OK;
3410 }
3411
3412 /**
3413 * @brief Enable the simple one pulse signal generation on the designed output
3414 * @param hhrtim pointer to HAL HRTIM handle
3415 * @param TimerIdx Timer index
3416 * This parameter can be one of the following values:
3417 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3418 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3419 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3420 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3421 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3422 * @param OnePulseChannel Timer output
3423 * This parameter can be one of the following values:
3424 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3425 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3426 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3427 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3428 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3429 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3430 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3431 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3432 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3433 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3434 * @retval HAL status
3435 */
HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3436 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3437 uint32_t TimerIdx,
3438 uint32_t OnePulseChannel)
3439 {
3440 /* Check the parameters */
3441 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3442
3443 /* Process Locked */
3444 __HAL_LOCK(hhrtim);
3445
3446 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3447
3448 /* Enable the timer output */
3449 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3450
3451 /* Enable the timer counter */
3452 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3453
3454 hhrtim->State = HAL_HRTIM_STATE_READY;
3455
3456 /* Process Unlocked */
3457 __HAL_UNLOCK(hhrtim);
3458
3459 return HAL_OK;
3460 }
3461
3462 /**
3463 * @brief Disable the simple one pulse signal generation on the designed output
3464 * @param hhrtim pointer to HAL HRTIM handle
3465 * @param TimerIdx Timer index
3466 * This parameter can be one of the following values:
3467 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3468 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3469 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3470 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3471 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3472 * @param OnePulseChannel Timer output
3473 * This parameter can be one of the following values:
3474 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3475 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3476 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3477 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3478 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3479 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3480 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3481 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3482 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3483 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3484 * @retval HAL status
3485 */
HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3486 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3487 uint32_t TimerIdx,
3488 uint32_t OnePulseChannel)
3489 {
3490 /* Check the parameters */
3491 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3492
3493 /* Process Locked */
3494 __HAL_LOCK(hhrtim);
3495
3496 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3497
3498 /* Disable the timer output */
3499 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3500
3501 /* Disable the timer counter */
3502 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3503
3504 hhrtim->State = HAL_HRTIM_STATE_READY;
3505
3506 /* Process Unlocked */
3507 __HAL_UNLOCK(hhrtim);
3508
3509 return HAL_OK;
3510 }
3511
3512 /**
3513 * @brief Enable the simple one pulse signal generation on the designed output
3514 * (The compare interrupt is enabled (pulse start)).
3515 * @param hhrtim pointer to HAL HRTIM handle
3516 * @param TimerIdx Timer index
3517 * This parameter can be one of the following values:
3518 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3519 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3520 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3521 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3522 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3523 * @param OnePulseChannel Timer output
3524 * This parameter can be one of the following values:
3525 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3526 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3527 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3528 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3529 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3530 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3531 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3532 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3533 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3534 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3535 * @retval HAL status
3536 */
HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3537 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3538 uint32_t TimerIdx,
3539 uint32_t OnePulseChannel)
3540 {
3541 /* Check the parameters */
3542 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3543
3544 /* Process Locked */
3545 __HAL_LOCK(hhrtim);
3546
3547 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3548
3549 /* Enable the timer output */
3550 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3551
3552 /* Enable the timer interrupt (depends on the OnePulse output) */
3553 switch (OnePulseChannel)
3554 {
3555 case HRTIM_OUTPUT_TA1:
3556 case HRTIM_OUTPUT_TB1:
3557 case HRTIM_OUTPUT_TC1:
3558 case HRTIM_OUTPUT_TD1:
3559 case HRTIM_OUTPUT_TE1:
3560 {
3561 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3562 break;
3563 }
3564
3565 case HRTIM_OUTPUT_TA2:
3566 case HRTIM_OUTPUT_TB2:
3567 case HRTIM_OUTPUT_TC2:
3568 case HRTIM_OUTPUT_TD2:
3569 case HRTIM_OUTPUT_TE2:
3570 {
3571 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3572 break;
3573 }
3574
3575 default:
3576 {
3577 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3578
3579 /* Process Unlocked */
3580 __HAL_UNLOCK(hhrtim);
3581
3582 break;
3583 }
3584 }
3585
3586 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3587 {
3588 return HAL_ERROR;
3589 }
3590
3591 /* Enable the timer counter */
3592 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3593
3594 hhrtim->State = HAL_HRTIM_STATE_READY;
3595
3596 /* Process Unlocked */
3597 __HAL_UNLOCK(hhrtim);
3598
3599 return HAL_OK;
3600 }
3601
3602 /**
3603 * @brief Disable the simple one pulse signal generation on the designed output
3604 * (The compare interrupt is disabled).
3605 * @param hhrtim pointer to HAL HRTIM handle
3606 * @param TimerIdx Timer index
3607 * This parameter can be one of the following values:
3608 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3609 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3610 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3611 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3612 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3613 * @param OnePulseChannel Timer output
3614 * This parameter can be one of the following values:
3615 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3616 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3617 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3618 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3619 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3620 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3621 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3622 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3623 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3624 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3625 * @retval HAL status
3626 */
HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3627 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3628 uint32_t TimerIdx,
3629 uint32_t OnePulseChannel)
3630 {
3631 /* Check the parameters */
3632 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3633
3634 /* Process Locked */
3635 __HAL_LOCK(hhrtim);
3636
3637 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3638
3639 /* Disable the timer output */
3640 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3641
3642 /* Disable the timer interrupt (depends on the OnePulse output) */
3643 switch (OnePulseChannel)
3644 {
3645 case HRTIM_OUTPUT_TA1:
3646 case HRTIM_OUTPUT_TB1:
3647 case HRTIM_OUTPUT_TC1:
3648 case HRTIM_OUTPUT_TD1:
3649 case HRTIM_OUTPUT_TE1:
3650 {
3651 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3652 break;
3653 }
3654
3655 case HRTIM_OUTPUT_TA2:
3656 case HRTIM_OUTPUT_TB2:
3657 case HRTIM_OUTPUT_TC2:
3658 case HRTIM_OUTPUT_TD2:
3659 case HRTIM_OUTPUT_TE2:
3660 {
3661 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3662 break;
3663 }
3664
3665 default:
3666 {
3667 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3668
3669 /* Process Unlocked */
3670 __HAL_UNLOCK(hhrtim);
3671
3672 break;
3673 }
3674 }
3675
3676 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3677 {
3678 return HAL_ERROR;
3679 }
3680
3681 /* Disable the timer counter */
3682 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3683
3684 hhrtim->State = HAL_HRTIM_STATE_READY;
3685
3686 /* Process Unlocked */
3687 __HAL_UNLOCK(hhrtim);
3688
3689 return HAL_OK;
3690 }
3691
3692 /**
3693 * @}
3694 */
3695
3696 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3697 * @brief HRTIM configuration functions
3698 @verbatim
3699 ===============================================================================
3700 ##### HRTIM configuration functions #####
3701 ===============================================================================
3702 [..] This section provides functions allowing to configure the HRTIM
3703 resources shared by all the HRTIM timers operating in waveform mode:
3704 (+) Configure the burst mode controller
3705 (+) Configure an external event conditioning
3706 (+) Configure the external events sampling clock
3707 (+) Configure a fault conditioning
3708 (+) Enable or disable fault inputs
3709 (+) Configure the faults sampling clock
3710 (+) Configure an ADC trigger
3711
3712 @endverbatim
3713 * @{
3714 */
3715
3716 /**
3717 * @brief Configure the burst mode feature of the HRTIM
3718 * @param hhrtim pointer to HAL HRTIM handle
3719 * @param pBurstModeCfg pointer to the burst mode configuration structure
3720 * @retval HAL status
3721 * @note This function must be called before starting the burst mode
3722 * controller
3723 */
HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,const HRTIM_BurstModeCfgTypeDef * pBurstModeCfg)3724 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3725 const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3726 {
3727 uint32_t hrtim_bmcr;
3728
3729 /* Check parameters */
3730 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3731 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3732 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3733 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3734 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3735
3736 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3737 {
3738 return HAL_BUSY;
3739 }
3740
3741 /* Process Locked */
3742 __HAL_LOCK(hhrtim);
3743
3744 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3745
3746 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3747
3748 /* Set the burst mode operating mode */
3749 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3750 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3751
3752 /* Set the burst mode clock source */
3753 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3754 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3755
3756 /* Set the burst mode prescaler */
3757 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3758 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3759
3760 /* Enable/disable burst mode registers preload */
3761 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3762 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3763
3764 /* Set the burst mode trigger */
3765 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3766
3767 /* Set the burst mode compare value */
3768 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3769
3770 /* Set the burst mode period */
3771 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3772
3773 /* Update the HRTIM registers */
3774 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3775
3776 hhrtim->State = HAL_HRTIM_STATE_READY;
3777
3778 /* Process Unlocked */
3779 __HAL_UNLOCK(hhrtim);
3780
3781 return HAL_OK;
3782 }
3783
3784 /**
3785 * @brief Configure the conditioning of an external event
3786 * @param hhrtim pointer to HAL HRTIM handle
3787 * @param Event external event to configure
3788 * This parameter can be one of the following values:
3789 * @arg HRTIM_EVENT_NONE: no external Event
3790 * @arg HRTIM_EVENT_1: External event 1
3791 * @arg HRTIM_EVENT_2: External event 2
3792 * @arg HRTIM_EVENT_3: External event 3
3793 * @arg HRTIM_EVENT_4: External event 4
3794 * @arg HRTIM_EVENT_5: External event 5
3795 * @arg HRTIM_EVENT_6: External event 6
3796 * @arg HRTIM_EVENT_7: External event 7
3797 * @arg HRTIM_EVENT_8: External event 8
3798 * @arg HRTIM_EVENT_9: External event 9
3799 * @arg HRTIM_EVENT_10: External event 10
3800 * @param pEventCfg pointer to the event conditioning configuration structure
3801 * @note This function must be called before starting the timer
3802 * @retval HAL status
3803 */
HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)3804 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3805 uint32_t Event,
3806 const HRTIM_EventCfgTypeDef* pEventCfg)
3807 {
3808 /* Check parameters */
3809 assert_param(IS_HRTIM_EVENT(Event));
3810 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
3811 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3812 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3813 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3814 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3815
3816 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3817 {
3818 return HAL_BUSY;
3819 }
3820
3821 /* Process Locked */
3822 __HAL_LOCK(hhrtim);
3823
3824 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3825
3826 /* Configure the event channel */
3827 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3828
3829 hhrtim->State = HAL_HRTIM_STATE_READY;
3830
3831 /* Process Unlocked */
3832 __HAL_UNLOCK(hhrtim);
3833
3834 return HAL_OK;
3835 }
3836
3837 /**
3838 * @brief Configure the external event conditioning block prescaler
3839 * @param hhrtim pointer to HAL HRTIM handle
3840 * @param Prescaler Prescaler value
3841 * This parameter can be one of the following values:
3842 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3843 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3844 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3845 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3846 * @note This function must be called before starting the timer
3847 * @retval HAL status
3848 */
HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)3849 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3850 uint32_t Prescaler)
3851 {
3852 /* Check parameters */
3853 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3854
3855 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3856 {
3857 return HAL_BUSY;
3858 }
3859
3860 /* Process Locked */
3861 __HAL_LOCK(hhrtim);
3862
3863 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3864
3865 /* Set the external event prescaler */
3866 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3867
3868 hhrtim->State = HAL_HRTIM_STATE_READY;
3869
3870 /* Process Unlocked */
3871 __HAL_UNLOCK(hhrtim);
3872
3873 return HAL_OK;
3874 }
3875
3876 /**
3877 * @brief Configure the conditioning of fault input
3878 * @param hhrtim pointer to HAL HRTIM handle
3879 * @param Fault fault input to configure
3880 * This parameter can be one of the following values:
3881 * @arg HRTIM_FAULT_1: Fault input 1
3882 * @arg HRTIM_FAULT_2: Fault input 2
3883 * @arg HRTIM_FAULT_3: Fault input 3
3884 * @arg HRTIM_FAULT_4: Fault input 4
3885 * @arg HRTIM_FAULT_5: Fault input 5
3886 * @param pFaultCfg pointer to the fault conditioning configuration structure
3887 * @note This function must be called before starting the timer and before
3888 * enabling faults inputs
3889 * @retval HAL status
3890 */
HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,const HRTIM_FaultCfgTypeDef * pFaultCfg)3891 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3892 uint32_t Fault,
3893 const HRTIM_FaultCfgTypeDef* pFaultCfg)
3894 {
3895 uint32_t hrtim_fltinr1;
3896 uint32_t hrtim_fltinr2;
3897
3898 /* Check parameters */
3899 assert_param(IS_HRTIM_FAULT(Fault));
3900 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3901 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3902 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3903 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3904
3905 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3906 {
3907 return HAL_BUSY;
3908 }
3909
3910 /* Process Locked */
3911 __HAL_LOCK(hhrtim);
3912
3913 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3914
3915 /* Configure fault channel */
3916 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3917 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3918
3919 switch (Fault)
3920 {
3921 case HRTIM_FAULT_1:
3922 {
3923 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
3924 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
3925 hrtim_fltinr1 |= (pFaultCfg->Source & HRTIM_FLTINR1_FLT1SRC);
3926 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
3927 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
3928 break;
3929 }
3930
3931 case HRTIM_FAULT_2:
3932 {
3933 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
3934 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
3935 hrtim_fltinr1 |= ((pFaultCfg->Source << 8U) & HRTIM_FLTINR1_FLT2SRC);
3936 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
3937 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
3938 break;
3939 }
3940
3941 case HRTIM_FAULT_3:
3942 {
3943 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
3944 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
3945 hrtim_fltinr1 |= ((pFaultCfg->Source << 16U) & HRTIM_FLTINR1_FLT3SRC);
3946 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
3947 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
3948 break;
3949 }
3950
3951 case HRTIM_FAULT_4:
3952 {
3953 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
3954 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
3955 hrtim_fltinr1 |= ((pFaultCfg->Source << 24U) & HRTIM_FLTINR1_FLT4SRC);
3956 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
3957 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
3958 break;
3959 }
3960
3961 case HRTIM_FAULT_5:
3962 {
3963 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
3964 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
3965 hrtim_fltinr2 |= (pFaultCfg->Source & HRTIM_FLTINR2_FLT5SRC);
3966 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
3967 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
3968 break;
3969 }
3970
3971 default:
3972 {
3973 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3974
3975 /* Process Unlocked */
3976 __HAL_UNLOCK(hhrtim);
3977
3978 break;
3979 }
3980 }
3981
3982 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3983 {
3984 return HAL_ERROR;
3985 }
3986
3987 /* Update the HRTIM registers except LOCK bit */
3988 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
3989 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
3990
3991 /* Update the HRTIM registers LOCK bit */
3992 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
3993 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
3994
3995 hhrtim->State = HAL_HRTIM_STATE_READY;
3996
3997 /* Process Unlocked */
3998 __HAL_UNLOCK(hhrtim);
3999
4000 return HAL_OK;
4001 }
4002
4003 /**
4004 * @brief Configure the fault conditioning block prescaler
4005 * @param hhrtim pointer to HAL HRTIM handle
4006 * @param Prescaler Prescaler value
4007 * This parameter can be one of the following values:
4008 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
4009 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
4010 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
4011 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
4012 * @retval HAL status
4013 * @note This function must be called before starting the timer and before
4014 * enabling faults inputs
4015 */
HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)4016 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
4017 uint32_t Prescaler)
4018 {
4019 /* Check parameters */
4020 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
4021
4022 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4023 {
4024 return HAL_BUSY;
4025 }
4026
4027 /* Process Locked */
4028 __HAL_LOCK(hhrtim);
4029
4030 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4031
4032 /* Set the external event prescaler */
4033 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
4034
4035 hhrtim->State = HAL_HRTIM_STATE_READY;
4036
4037 /* Process Unlocked */
4038 __HAL_UNLOCK(hhrtim);
4039
4040 return HAL_OK;
4041 }
4042
4043 /**
4044 * @brief Enable or disables the HRTIMx Fault mode.
4045 * @param hhrtim pointer to HAL HRTIM handle
4046 * @param Faults fault input(s) to enable or disable
4047 * This parameter can be any combination of the following values:
4048 * @arg HRTIM_FAULT_1: Fault input 1
4049 * @arg HRTIM_FAULT_2: Fault input 2
4050 * @arg HRTIM_FAULT_3: Fault input 3
4051 * @arg HRTIM_FAULT_4: Fault input 4
4052 * @arg HRTIM_FAULT_5: Fault input 5
4053 * @param Enable Fault(s) enabling
4054 * This parameter can be one of the following values:
4055 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
4056 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
4057 * @retval None
4058 */
HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Faults,uint32_t Enable)4059 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
4060 uint32_t Faults,
4061 uint32_t Enable)
4062 {
4063 /* Check parameters */
4064 assert_param(IS_HRTIM_FAULT(Faults));
4065 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
4066
4067 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
4068 {
4069 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
4070 }
4071 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
4072 {
4073 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
4074 }
4075 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
4076 {
4077 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
4078 }
4079 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
4080 {
4081 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
4082 }
4083 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
4084 {
4085 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
4086 }
4087 }
4088
4089 /**
4090 * @brief Configure both the ADC trigger register update source and the ADC
4091 * trigger source.
4092 * @param hhrtim pointer to HAL HRTIM handle
4093 * @param ADCTrigger ADC trigger to configure
4094 * This parameter can be one of the following values:
4095 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
4096 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
4097 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
4098 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
4099 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
4100 * @retval HAL status
4101 * @note This function must be called before starting the timer
4102 */
HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t ADCTrigger,const HRTIM_ADCTriggerCfgTypeDef * pADCTriggerCfg)4103 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
4104 uint32_t ADCTrigger,
4105 const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
4106 {
4107 uint32_t hrtim_cr1;
4108
4109 /* Check parameters */
4110 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
4111 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
4112
4113 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4114 {
4115 return HAL_BUSY;
4116 }
4117
4118 /* Process Locked */
4119 __HAL_LOCK(hhrtim);
4120
4121 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4122
4123 /* Set the ADC trigger update source */
4124 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
4125
4126 switch (ADCTrigger)
4127 {
4128 case HRTIM_ADCTRIGGER_1:
4129 {
4130 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
4131 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
4132
4133 /* Set the ADC trigger 1 source */
4134 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
4135 break;
4136 }
4137
4138 case HRTIM_ADCTRIGGER_2:
4139 {
4140 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
4141 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
4142
4143 /* Set the ADC trigger 2 source */
4144 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
4145 break;
4146 }
4147
4148 case HRTIM_ADCTRIGGER_3:
4149 {
4150 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
4151 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
4152
4153 /* Set the ADC trigger 3 source */
4154 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
4155 break;
4156 }
4157
4158 case HRTIM_ADCTRIGGER_4:
4159 {
4160 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
4161 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4162
4163 /* Set the ADC trigger 4 source */
4164 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4165 break;
4166 }
4167
4168 default:
4169 {
4170 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4171
4172 /* Process Unlocked */
4173 __HAL_UNLOCK(hhrtim);
4174
4175 break;
4176 }
4177 }
4178
4179 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4180 {
4181 return HAL_ERROR;
4182 }
4183
4184 /* Update the HRTIM registers */
4185 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4186
4187 hhrtim->State = HAL_HRTIM_STATE_READY;
4188
4189 /* Process Unlocked */
4190 __HAL_UNLOCK(hhrtim);
4191
4192 return HAL_OK;
4193 }
4194
4195
4196 /**
4197 * @}
4198 */
4199
4200 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
4201 * @brief HRTIM timer configuration and control functions
4202 @verbatim
4203 ===============================================================================
4204 ##### HRTIM timer configuration and control functions #####
4205 ===============================================================================
4206 [..] This section provides functions used to configure and control a
4207 HRTIM timer operating in waveform mode:
4208 (+) Configure HRTIM timer general behavior
4209 (+) Configure HRTIM timer event filtering
4210 (+) Configure HRTIM timer deadtime insertion
4211 (+) Configure HRTIM timer chopper mode
4212 (+) Configure HRTIM timer burst DMA
4213 (+) Configure HRTIM timer compare unit
4214 (+) Configure HRTIM timer capture unit
4215 (+) Configure HRTIM timer output
4216 (+) Set HRTIM timer output level
4217 (+) Enable HRTIM timer output
4218 (+) Disable HRTIM timer output
4219 (+) Start HRTIM timer
4220 (+) Stop HRTIM timer
4221 (+) Start HRTIM timer and enable interrupt
4222 (+) Stop HRTIM timer and disable interrupt
4223 (+) Start HRTIM timer and enable DMA transfer
4224 (+) Stop HRTIM timer and disable DMA transfer
4225 (+) Enable or disable the burst mode controller
4226 (+) Start the burst mode controller (by software)
4227 (+) Trigger a Capture (by software)
4228 (+) Update the HRTIM timer preloadable registers (by software)
4229 (+) Reset the HRTIM timer counter (by software)
4230 (+) Start a burst DMA transfer
4231 (+) Enable timer register update
4232 (+) Disable timer register update
4233
4234 @endverbatim
4235 * @{
4236 */
4237
4238 /**
4239 * @brief Configure the general behavior of a timer operating in waveform mode
4240 * @param hhrtim pointer to HAL HRTIM handle
4241 * @param TimerIdx Timer index
4242 * This parameter can be one of the following values:
4243 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4244 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4245 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4246 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4247 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4248 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4249 * @param pTimerCfg pointer to the timer configuration structure
4250 * @note When the timer operates in waveform mode, all the features supported by
4251 * the HRTIM are available without any limitation.
4252 * @retval HAL status
4253 * @note This function must be called before starting the timer
4254 */
HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)4255 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
4256 uint32_t TimerIdx,
4257 const HRTIM_TimerCfgTypeDef * pTimerCfg)
4258 {
4259 /* Check parameters */
4260 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4261
4262 /* Relevant for all HRTIM timers, including the master */
4263 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4264 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4265 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4266 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4267 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4268 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4269 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4270
4271 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4272 {
4273 return HAL_BUSY;
4274 }
4275
4276 /* Process Locked */
4277 __HAL_LOCK(hhrtim);
4278
4279 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4280
4281 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4282 {
4283 /* Check parameters */
4284 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4285 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4286 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4287
4288 /* Configure master timer */
4289 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4290 }
4291 else
4292 {
4293 /* Check parameters */
4294 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
4295 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
4296 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
4297 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
4298 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
4299 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
4300 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
4301 pTimerCfg->DeadTimeInsertion));
4302 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
4303 pTimerCfg->DelayedProtectionMode));
4304 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
4305 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
4306 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
4307
4308 /* Configure timing unit */
4309 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
4310 }
4311
4312 /* Update timer parameters */
4313 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
4314 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
4315 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
4316 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
4317 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
4318
4319 /* Force a software update */
4320 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
4321
4322 hhrtim->State = HAL_HRTIM_STATE_READY;
4323
4324 /* Process Unlocked */
4325 __HAL_UNLOCK(hhrtim);
4326
4327 return HAL_OK;
4328 }
4329
4330 /**
4331 * @brief Configure the event filtering capabilities of a timer (blanking, windowing)
4332 * @param hhrtim pointer to HAL HRTIM handle
4333 * @param TimerIdx Timer index
4334 * This parameter can be one of the following values:
4335 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4336 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4337 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4338 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4339 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4340 * @param Event external event for which timer event filtering must be configured
4341 * This parameter can be one of the following values:
4342 * @arg HRTIM_EVENT_1: External event 1
4343 * @arg HRTIM_EVENT_2: External event 2
4344 * @arg HRTIM_EVENT_3: External event 3
4345 * @arg HRTIM_EVENT_4: External event 4
4346 * @arg HRTIM_EVENT_5: External event 5
4347 * @arg HRTIM_EVENT_6: External event 6
4348 * @arg HRTIM_EVENT_7: External event 7
4349 * @arg HRTIM_EVENT_8: External event 8
4350 * @arg HRTIM_EVENT_9: External event 9
4351 * @arg HRTIM_EVENT_10: External event 10
4352 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
4353 * @note This function must be called before starting the timer
4354 * @retval HAL status
4355 */
HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event,const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg)4356 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
4357 uint32_t TimerIdx,
4358 uint32_t Event,
4359 const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
4360 {
4361 /* Check parameters */
4362 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4363 assert_param(IS_HRTIM_EVENT(Event));
4364 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
4365
4366 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
4367
4368 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4369 {
4370 return HAL_BUSY;
4371 }
4372
4373 /* Process Locked */
4374 __HAL_LOCK(hhrtim);
4375
4376 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4377
4378 /* Configure timer event filtering capabilities */
4379 switch (Event)
4380 {
4381 case HRTIM_EVENT_NONE:
4382 {
4383 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
4384 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
4385 break;
4386 }
4387
4388 case HRTIM_EVENT_1:
4389 {
4390 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
4391 break;
4392 }
4393
4394 case HRTIM_EVENT_2:
4395 {
4396 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4397 break;
4398 }
4399
4400 case HRTIM_EVENT_3:
4401 {
4402 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4403 break;
4404 }
4405
4406 case HRTIM_EVENT_4:
4407 {
4408 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4409 break;
4410 }
4411
4412 case HRTIM_EVENT_5:
4413 {
4414 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4415 break;
4416 }
4417
4418 case HRTIM_EVENT_6:
4419 {
4420 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
4421 break;
4422 }
4423
4424 case HRTIM_EVENT_7:
4425 {
4426 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4427 break;
4428 }
4429
4430 case HRTIM_EVENT_8:
4431 {
4432 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4433 break;
4434 }
4435
4436 case HRTIM_EVENT_9:
4437 {
4438 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4439 break;
4440 }
4441
4442 case HRTIM_EVENT_10:
4443 {
4444 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4445 break;
4446 }
4447
4448 default:
4449 {
4450 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4451
4452 /* Process Unlocked */
4453 __HAL_UNLOCK(hhrtim);
4454
4455 break;
4456 }
4457 }
4458
4459 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4460 {
4461 return HAL_ERROR;
4462 }
4463
4464 hhrtim->State = HAL_HRTIM_STATE_READY;
4465
4466 /* Process Unlocked */
4467 __HAL_UNLOCK(hhrtim);
4468
4469 return HAL_OK;
4470 }
4471
4472 /**
4473 * @brief Configure the dead-time insertion feature for a timer
4474 * @param hhrtim pointer to HAL HRTIM handle
4475 * @param TimerIdx Timer index
4476 * This parameter can be one of the following values:
4477 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4478 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4479 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4480 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4481 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4482 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
4483 * @retval HAL status
4484 * @note This function must be called before starting the timer
4485 */
HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_DeadTimeCfgTypeDef * pDeadTimeCfg)4486 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
4487 uint32_t TimerIdx,
4488 const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
4489 {
4490 uint32_t hrtim_dtr;
4491
4492 /* Check parameters */
4493 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4494 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
4495 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
4496 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
4497 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
4498 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
4499 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
4500 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
4501
4502 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4503 {
4504 return HAL_BUSY;
4505 }
4506
4507 /* Process Locked */
4508 __HAL_LOCK(hhrtim);
4509
4510 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4511
4512 /* Set timer deadtime configuration */
4513 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
4514 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
4515 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
4516 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
4517 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
4518 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
4519 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
4520 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
4521 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
4522
4523 /* Update the HRTIM registers */
4524 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
4525 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
4526 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
4527 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
4528
4529 hhrtim->State = HAL_HRTIM_STATE_READY;
4530
4531 /* Process Unlocked */
4532 __HAL_UNLOCK(hhrtim);
4533
4534 return HAL_OK;
4535 }
4536
4537 /**
4538 * @brief Configure the chopper mode feature for a timer
4539 * @param hhrtim pointer to HAL HRTIM handle
4540 * @param TimerIdx Timer index
4541 * This parameter can be one of the following values:
4542 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4543 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4544 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4545 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4546 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4547 * @param pChopperModeCfg pointer to the chopper mode configuration structure
4548 * @retval HAL status
4549 * @note This function must be called before configuring the timer output(s)
4550 */
HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_ChopperModeCfgTypeDef * pChopperModeCfg)4551 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
4552 uint32_t TimerIdx,
4553 const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
4554 {
4555 uint32_t hrtim_chpr;
4556
4557 /* Check parameters */
4558 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4559 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
4560 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
4561 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
4562
4563 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4564 {
4565 return HAL_BUSY;
4566 }
4567
4568 /* Process Locked */
4569 __HAL_LOCK(hhrtim);
4570
4571 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4572
4573 /* Set timer choppe mode configuration */
4574 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
4575 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
4576 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
4577
4578 /* Update the HRTIM registers */
4579 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
4580 (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
4581 hrtim_chpr);
4582
4583 hhrtim->State = HAL_HRTIM_STATE_READY;
4584
4585 /* Process Unlocked */
4586 __HAL_UNLOCK(hhrtim);
4587
4588 return HAL_OK;
4589 }
4590
4591 /**
4592 * @brief Configure the burst DMA controller for a timer
4593 * @param hhrtim pointer to HAL HRTIM handle
4594 * @param TimerIdx Timer index
4595 * This parameter can be one of the following values:
4596 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4597 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4598 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4599 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4600 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4601 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4602 * @param RegistersToUpdate registers to be written by DMA
4603 * This parameter can be any combination of the following values:
4604 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
4605 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
4606 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
4607 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
4608 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
4609 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
4610 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
4611 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
4612 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
4613 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
4614 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
4615 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
4616 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
4617 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
4618 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
4619 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
4620 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
4621 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
4622 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
4623 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
4624 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
4625 * @retval HAL status
4626 * @note This function must be called before starting the timer
4627 */
HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t RegistersToUpdate)4628 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
4629 uint32_t TimerIdx,
4630 uint32_t RegistersToUpdate)
4631 {
4632 /* Check parameters */
4633 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
4634
4635 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4636 {
4637 return HAL_BUSY;
4638 }
4639
4640 /* Process Locked */
4641 __HAL_LOCK(hhrtim);
4642
4643 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4644
4645 /* Set the burst DMA timer update register */
4646 switch (TimerIdx)
4647 {
4648 case HRTIM_TIMERINDEX_TIMER_A:
4649 {
4650 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
4651 break;
4652 }
4653
4654 case HRTIM_TIMERINDEX_TIMER_B:
4655 {
4656 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
4657 break;
4658 }
4659
4660 case HRTIM_TIMERINDEX_TIMER_C:
4661 {
4662 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
4663 break;
4664 }
4665
4666 case HRTIM_TIMERINDEX_TIMER_D:
4667 {
4668 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
4669 break;
4670 }
4671
4672 case HRTIM_TIMERINDEX_TIMER_E:
4673 {
4674 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
4675 break;
4676 }
4677
4678 case HRTIM_TIMERINDEX_MASTER:
4679 {
4680 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
4681 break;
4682 }
4683
4684 default:
4685 {
4686 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4687
4688 /* Process Unlocked */
4689 __HAL_UNLOCK(hhrtim);
4690
4691 break;
4692 }
4693 }
4694
4695 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4696 {
4697 return HAL_ERROR;
4698 }
4699
4700 hhrtim->State = HAL_HRTIM_STATE_READY;
4701
4702 /* Process Unlocked */
4703 __HAL_UNLOCK(hhrtim);
4704
4705 return HAL_OK;
4706 }
4707
4708 /**
4709 * @brief Configure the compare unit of a timer operating in waveform mode
4710 * @param hhrtim pointer to HAL HRTIM handle
4711 * @param TimerIdx Timer index
4712 * This parameter can be one of the following values:
4713 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4714 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4715 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4716 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4717 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4718 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4719 * @param CompareUnit Compare unit to configure
4720 * This parameter can be one of the following values:
4721 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
4722 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
4723 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
4724 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
4725 * @param pCompareCfg pointer to the compare unit configuration structure
4726 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
4727 * application has to configure separately the capture unit. Capture unit
4728 * to configure in that case depends on the compare unit auto delayed mode
4729 * is applied to (see below):
4730 * Auto delayed on output compare 2: capture unit 1 must be configured
4731 * Auto delayed on output compare 4: capture unit 2 must be configured
4732 * @retval HAL status
4733 * @note This function must be called before starting the timer
4734 */
HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CompareUnit,const HRTIM_CompareCfgTypeDef * pCompareCfg)4735 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
4736 uint32_t TimerIdx,
4737 uint32_t CompareUnit,
4738 const HRTIM_CompareCfgTypeDef* pCompareCfg)
4739 {
4740 /* Check parameters */
4741 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4742
4743 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4744 {
4745 return HAL_BUSY;
4746 }
4747
4748 /* Process Locked */
4749 __HAL_LOCK(hhrtim);
4750
4751 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4752
4753 /* Configure the compare unit */
4754 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4755 {
4756 switch (CompareUnit)
4757 {
4758 case HRTIM_COMPAREUNIT_1:
4759 {
4760 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
4761 break;
4762 }
4763
4764 case HRTIM_COMPAREUNIT_2:
4765 {
4766 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
4767 break;
4768 }
4769
4770 case HRTIM_COMPAREUNIT_3:
4771 {
4772 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
4773 break;
4774 }
4775
4776 case HRTIM_COMPAREUNIT_4:
4777 {
4778 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
4779 break;
4780 }
4781
4782 default:
4783 {
4784 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4785
4786 /* Process Unlocked */
4787 __HAL_UNLOCK(hhrtim);
4788
4789 break;
4790 }
4791 }
4792
4793 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4794 {
4795 return HAL_ERROR;
4796 }
4797
4798 }
4799 else
4800 {
4801 switch (CompareUnit)
4802 {
4803 case HRTIM_COMPAREUNIT_1:
4804 {
4805 /* Set the compare value */
4806 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
4807 break;
4808 }
4809
4810 case HRTIM_COMPAREUNIT_2:
4811 {
4812 /* Check parameters */
4813 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4814
4815 /* Set the compare value */
4816 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
4817
4818 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4819 {
4820 /* Configure auto-delayed mode */
4821 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
4822 /* to the other to reinitialize properly the auto-delayed mechanism */
4823 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
4824 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
4825
4826 /* Set the compare value for timeout compare unit (if any) */
4827 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4828 {
4829 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4830 }
4831 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4832 {
4833 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4834 }
4835 else
4836 {
4837 /* nothing to do */
4838 }
4839 }
4840 else
4841 {
4842 /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
4843 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
4844 }
4845 break;
4846 }
4847
4848 case HRTIM_COMPAREUNIT_3:
4849 {
4850 /* Set the compare value */
4851 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
4852 break;
4853 }
4854
4855 case HRTIM_COMPAREUNIT_4:
4856 {
4857 /* Check parameters */
4858 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4859
4860 /* Set the compare value */
4861 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
4862
4863 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4864 {
4865 /* Configure auto-delayed mode */
4866 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
4867 /* to the other to reinitialize properly the auto-delayed mechanism */
4868 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
4869 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
4870
4871 /* Set the compare value for timeout compare unit (if any) */
4872 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4873 {
4874 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4875 }
4876 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4877 {
4878 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4879 }
4880 else
4881 {
4882 /* nothing to do */
4883 }
4884 }
4885 else
4886 {
4887 /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
4888 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
4889 }
4890 break;
4891 }
4892
4893 default:
4894 {
4895 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4896
4897 /* Process Unlocked */
4898 __HAL_UNLOCK(hhrtim);
4899
4900 break;
4901 }
4902 }
4903
4904 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4905 {
4906 return HAL_ERROR;
4907 }
4908
4909 }
4910 hhrtim->State = HAL_HRTIM_STATE_READY;
4911
4912 /* Process Unlocked */
4913 __HAL_UNLOCK(hhrtim);
4914
4915 return HAL_OK;
4916 }
4917
4918 /**
4919 * @brief Configure the capture unit of a timer operating in waveform mode
4920 * @param hhrtim pointer to HAL HRTIM handle
4921 * @param TimerIdx Timer index
4922 * This parameter can be one of the following values:
4923 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4924 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4925 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4926 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4927 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4928 * @param CaptureUnit Capture unit to configure
4929 * This parameter can be one of the following values:
4930 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
4931 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
4932 * @param pCaptureCfg pointer to the compare unit configuration structure
4933 * @retval HAL status
4934 * @note This function must be called before starting the timer
4935 */
HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,const HRTIM_CaptureCfgTypeDef * pCaptureCfg)4936 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
4937 uint32_t TimerIdx,
4938 uint32_t CaptureUnit,
4939 const HRTIM_CaptureCfgTypeDef* pCaptureCfg)
4940 {
4941 /* Check parameters */
4942 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
4943
4944
4945 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4946 {
4947 return HAL_BUSY;
4948 }
4949
4950 /* Process Locked */
4951 __HAL_LOCK(hhrtim);
4952
4953 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4954
4955 /* Configure the capture unit */
4956 switch (CaptureUnit)
4957 {
4958 case HRTIM_CAPTUREUNIT_1:
4959 {
4960 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger);
4961 break;
4962 }
4963
4964 case HRTIM_CAPTUREUNIT_2:
4965 {
4966 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger);
4967 break;
4968 }
4969
4970 default:
4971 {
4972 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4973
4974 /* Process Unlocked */
4975 __HAL_UNLOCK(hhrtim);
4976
4977 break;
4978 }
4979 }
4980
4981 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4982 {
4983 return HAL_ERROR;
4984 }
4985
4986
4987 hhrtim->State = HAL_HRTIM_STATE_READY;
4988
4989 /* Process Unlocked */
4990 __HAL_UNLOCK(hhrtim);
4991
4992 return HAL_OK;
4993 }
4994
4995 /**
4996 * @brief Configure the output of a timer operating in waveform mode
4997 * @param hhrtim pointer to HAL HRTIM handle
4998 * @param TimerIdx Timer index
4999 * This parameter can be one of the following values:
5000 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5001 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5002 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5003 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5004 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5005 * @param Output Timer output
5006 * This parameter can be one of the following values:
5007 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5008 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5009 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5010 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5011 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5012 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5013 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5014 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5015 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5016 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5017 * @param pOutputCfg pointer to the timer output configuration structure
5018 * @retval HAL status
5019 * @note This function must be called before configuring the timer and after
5020 * configuring the deadtime insertion feature (if required).
5021 */
HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)5022 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
5023 uint32_t TimerIdx,
5024 uint32_t Output,
5025 const HRTIM_OutputCfgTypeDef * pOutputCfg)
5026 {
5027 /* Check parameters */
5028 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5029 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
5030 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
5031 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
5032 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
5033 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
5034 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
5035
5036 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5037 {
5038 return HAL_BUSY;
5039 }
5040
5041 /* Process Locked */
5042 __HAL_LOCK(hhrtim);
5043
5044 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5045
5046 /* Configure the timer output */
5047 HRTIM_OutputConfig(hhrtim,
5048 TimerIdx,
5049 Output,
5050 pOutputCfg);
5051
5052 hhrtim->State = HAL_HRTIM_STATE_READY;
5053
5054 /* Process Unlocked */
5055 __HAL_UNLOCK(hhrtim);
5056
5057 return HAL_OK;
5058 }
5059
5060 /**
5061 * @brief Force the timer output to its active or inactive state
5062 * @param hhrtim pointer to HAL HRTIM handle
5063 * @param TimerIdx Timer index
5064 * This parameter can be one of the following values:
5065 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5066 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5067 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5068 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5069 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5070 * @param Output Timer output
5071 * This parameter can be one of the following values:
5072 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5073 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5074 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5075 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5076 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5077 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5078 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5079 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5080 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5081 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5082 * @param OutputLevel indicates whether the output is forced to its active or inactive level
5083 * This parameter can be one of the following values:
5084 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
5085 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
5086 * @retval HAL status
5087 * @note The 'software set/reset trigger' bit in the output set/reset registers
5088 * is automatically reset by hardware
5089 */
HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,uint32_t OutputLevel)5090 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
5091 uint32_t TimerIdx,
5092 uint32_t Output,
5093 uint32_t OutputLevel)
5094 {
5095 /* Check parameters */
5096 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5097 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
5098
5099 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5100 {
5101 return HAL_BUSY;
5102 }
5103
5104 /* Process Locked */
5105 __HAL_LOCK(hhrtim);
5106
5107 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5108
5109 /* Force timer output level */
5110 switch (Output)
5111 {
5112 case HRTIM_OUTPUT_TA1:
5113 case HRTIM_OUTPUT_TB1:
5114 case HRTIM_OUTPUT_TC1:
5115 case HRTIM_OUTPUT_TD1:
5116 case HRTIM_OUTPUT_TE1:
5117 {
5118 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
5119 {
5120 /* Force output to its active state */
5121 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
5122 }
5123 else
5124 {
5125 /* Force output to its inactive state */
5126 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
5127 }
5128 break;
5129 }
5130
5131 case HRTIM_OUTPUT_TA2:
5132 case HRTIM_OUTPUT_TB2:
5133 case HRTIM_OUTPUT_TC2:
5134 case HRTIM_OUTPUT_TD2:
5135 case HRTIM_OUTPUT_TE2:
5136 {
5137 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
5138 {
5139 /* Force output to its active state */
5140 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
5141 }
5142 else
5143 {
5144 /* Force output to its inactive state */
5145 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
5146 }
5147 break;
5148 }
5149
5150 default:
5151 {
5152 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5153
5154 /* Process Unlocked */
5155 __HAL_UNLOCK(hhrtim);
5156
5157 break;
5158 }
5159 }
5160
5161 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5162 {
5163 return HAL_ERROR;
5164 }
5165
5166 hhrtim->State = HAL_HRTIM_STATE_READY;
5167
5168 /* Process Unlocked */
5169 __HAL_UNLOCK(hhrtim);
5170
5171 return HAL_OK;
5172 }
5173
5174 /**
5175 * @brief Enable the generation of the waveform signal on the designated output(s)
5176 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
5177 * @param hhrtim pointer to HAL HRTIM handle
5178 * @param OutputsToStart Timer output(s) to enable
5179 * This parameter can be any combination of the following values:
5180 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5181 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5182 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5183 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5184 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5185 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5186 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5187 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5188 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5189 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5190 * @retval HAL status
5191 */
HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStart)5192 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
5193 uint32_t OutputsToStart)
5194 {
5195 /* Check the parameters */
5196 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
5197
5198 /* Process Locked */
5199 __HAL_LOCK(hhrtim);
5200
5201 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5202
5203 /* Enable the HRTIM outputs */
5204 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
5205
5206 hhrtim->State = HAL_HRTIM_STATE_READY;
5207
5208 /* Process Unlocked */
5209 __HAL_UNLOCK(hhrtim);
5210
5211 return HAL_OK;
5212 }
5213
5214 /**
5215 * @brief Disable the generation of the waveform signal on the designated output(s)
5216 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
5217 * @param hhrtim pointer to HAL HRTIM handle
5218 * @param OutputsToStop Timer output(s) to disable
5219 * This parameter can be any combination of the following values:
5220 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5221 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5222 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5223 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5224 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5225 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5226 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5227 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5228 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5229 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5230 * @retval HAL status
5231 */
HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStop)5232 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
5233 uint32_t OutputsToStop)
5234 {
5235 /* Check the parameters */
5236 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
5237
5238 /* Process Locked */
5239 __HAL_LOCK(hhrtim);
5240
5241 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5242
5243 /* Enable the HRTIM outputs */
5244 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
5245
5246 hhrtim->State = HAL_HRTIM_STATE_READY;
5247
5248 /* Process Unlocked */
5249 __HAL_UNLOCK(hhrtim);
5250
5251 return HAL_OK;
5252 }
5253
5254 /**
5255 * @brief Start the counter of the designated timer(s) operating in waveform mode
5256 * Timers can be combined (ORed) to allow for simultaneous counter start.
5257 * @param hhrtim pointer to HAL HRTIM handle
5258 * @param Timers Timer counter(s) to start
5259 * This parameter can be any combination of the following values:
5260 * @arg HRTIM_TIMERID_MASTER
5261 * @arg HRTIM_TIMERID_TIMER_A
5262 * @arg HRTIM_TIMERID_TIMER_B
5263 * @arg HRTIM_TIMERID_TIMER_C
5264 * @arg HRTIM_TIMERID_TIMER_D
5265 * @arg HRTIM_TIMERID_TIMER_E
5266 * @retval HAL status
5267 */
HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5268 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
5269 uint32_t Timers)
5270 {
5271 /* Check the parameters */
5272 assert_param(IS_HRTIM_TIMERID(Timers));
5273
5274 /* Process Locked */
5275 __HAL_LOCK(hhrtim);
5276
5277 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5278
5279 /* Enable timer(s) counter */
5280 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5281
5282 hhrtim->State = HAL_HRTIM_STATE_READY;
5283
5284 /* Process Unlocked */
5285 __HAL_UNLOCK(hhrtim);
5286
5287 return HAL_OK;
5288 }
5289
5290 /**
5291 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5292 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5293 * @param hhrtim pointer to HAL HRTIM handle
5294 * @param Timers Timer counter(s) to stop
5295 * This parameter can be any combination of the following values:
5296 * @arg HRTIM_TIMERID_MASTER
5297 * @arg HRTIM_TIMERID_TIMER_A
5298 * @arg HRTIM_TIMERID_TIMER_B
5299 * @arg HRTIM_TIMERID_TIMER_C
5300 * @arg HRTIM_TIMERID_TIMER_D
5301 * @arg HRTIM_TIMERID_TIMER_E
5302 * @retval HAL status
5303 * @note The counter of a timer is stopped only if all timer outputs are disabled
5304 */
HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5305 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
5306 uint32_t Timers)
5307 {
5308 /* Check the parameters */
5309 assert_param(IS_HRTIM_TIMERID(Timers));
5310
5311 /* Process Locked */
5312 __HAL_LOCK(hhrtim);
5313
5314 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5315
5316 /* Disable timer(s) counter */
5317 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5318
5319 hhrtim->State = HAL_HRTIM_STATE_READY;
5320
5321 /* Process Unlocked */
5322 __HAL_UNLOCK(hhrtim);
5323
5324 return HAL_OK;
5325 }
5326
5327 /**
5328 * @brief Start the counter of the designated timer(s) operating in waveform mode
5329 * Timers can be combined (ORed) to allow for simultaneous counter start.
5330 * @param hhrtim pointer to HAL HRTIM handle
5331 * @param Timers Timer counter(s) to start
5332 * This parameter can be any combination of the following values:
5333 * @arg HRTIM_TIMERID_MASTER
5334 * @arg HRTIM_TIMERID_TIMER_A
5335 * @arg HRTIM_TIMERID_TIMER_B
5336 * @arg HRTIM_TIMERID_TIMER_C
5337 * @arg HRTIM_TIMERID_TIMER_D
5338 * @arg HRTIM_TIMERID_TIMER_E
5339 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
5340 * to the timers to start are enabled within this function.
5341 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
5342 * function.
5343 * @retval HAL status
5344 */
HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5345 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
5346 uint32_t Timers)
5347 {
5348 uint8_t timer_idx;
5349
5350 /* Check the parameters */
5351 assert_param(IS_HRTIM_TIMERID(Timers));
5352
5353 /* Process Locked */
5354 __HAL_LOCK(hhrtim);
5355
5356 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5357
5358 /* Enable HRTIM interrupts (if required) */
5359 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5360
5361 /* Enable master timer related interrupts (if required) */
5362 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5363 {
5364 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
5365 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5366 }
5367
5368 /* Enable timing unit related interrupts (if required) */
5369 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5370 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5371 timer_idx++)
5372 {
5373 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5374 {
5375 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
5376 timer_idx,
5377 hhrtim->TimerParam[timer_idx].InterruptRequests);
5378 }
5379 }
5380
5381 /* Enable timer(s) counter */
5382 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5383
5384 hhrtim->State = HAL_HRTIM_STATE_READY;
5385
5386 /* Process Unlocked */
5387 __HAL_UNLOCK(hhrtim);
5388
5389 return HAL_OK;}
5390
5391 /**
5392 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5393 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5394 * @param hhrtim pointer to HAL HRTIM handle
5395 * @param Timers Timer counter(s) to stop
5396 * This parameter can be any combination of the following values:
5397 * @arg HRTIM_TIMERID_MASTER
5398 * @arg HRTIM_TIMERID_TIMER_A
5399 * @arg HRTIM_TIMERID_TIMER_B
5400 * @arg HRTIM_TIMERID_TIMER_C
5401 * @arg HRTIM_TIMERID_TIMER_D
5402 * @arg HRTIM_TIMERID_TIMER_E
5403 * @retval HAL status
5404 * @note The counter of a timer is stopped only if all timer outputs are disabled
5405 * @note All enabled timer related interrupts are disabled.
5406 */
HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5407 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
5408 uint32_t Timers)
5409 {
5410 /* ++ WA */
5411 __IO uint32_t delai = (uint32_t)(0x17FU);
5412 /* -- WA */
5413
5414 uint8_t timer_idx;
5415
5416 /* Check the parameters */
5417 assert_param(IS_HRTIM_TIMERID(Timers));
5418
5419 /* Process Locked */
5420 __HAL_LOCK(hhrtim);
5421
5422 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5423
5424 /* Disable HRTIM interrupts (if required) */
5425 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5426
5427 /* Disable master timer related interrupts (if required) */
5428 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5429 {
5430 /* Interrupts enable flag must be cleared one by one */
5431 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5432 }
5433
5434 /* Disable timing unit related interrupts (if required) */
5435 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5436 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5437 timer_idx++)
5438 {
5439 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5440 {
5441 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
5442 }
5443 }
5444
5445 /* ++ WA */
5446 do { delai--; } while (delai != 0U);
5447 /* -- WA */
5448
5449 /* Disable timer(s) counter */
5450 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5451
5452 hhrtim->State = HAL_HRTIM_STATE_READY;
5453
5454 /* Process Unlocked */
5455 __HAL_UNLOCK(hhrtim);
5456
5457 return HAL_OK;
5458 }
5459
5460 /**
5461 * @brief Start the counter of the designated timer(s) operating in waveform mode
5462 * Timers can be combined (ORed) to allow for simultaneous counter start.
5463 * @param hhrtim pointer to HAL HRTIM handle
5464 * @param Timers Timer counter(s) to start
5465 * This parameter can be any combination of the following values:
5466 * @arg HRTIM_TIMERID_MASTER
5467 * @arg HRTIM_TIMERID_TIMER_A
5468 * @arg HRTIM_TIMERID_TIMER_B
5469 * @arg HRTIM_TIMERID_TIMER_C
5470 * @arg HRTIM_TIMERID_TIMER_D
5471 * @arg HRTIM_TIMERID_TIMER_E
5472 * @retval HAL status
5473 * @note This function enables the dma request(s) mentioned in the timer
5474 * configuration data structure for every timers to start.
5475 * @note The source memory address, the destination memory address and the
5476 * size of each DMA transfer are specified at timer configuration time
5477 * (see HAL_HRTIM_WaveformTimerConfig)
5478 */
HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5479 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
5480 uint32_t Timers)
5481 {
5482 uint8_t timer_idx;
5483 DMA_HandleTypeDef * hdma;
5484
5485 /* Check the parameters */
5486 assert_param(IS_HRTIM_TIMERID(Timers));
5487
5488 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5489 {
5490 return HAL_BUSY;
5491 }
5492
5493 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5494
5495 /* Process Locked */
5496 __HAL_LOCK(hhrtim);
5497
5498 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
5499 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5500 {
5501 /* Set the DMA error callback */
5502 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
5503
5504 /* Set the DMA transfer completed callback */
5505 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
5506
5507 /* Enable the DMA channel */
5508 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
5509 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
5510 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
5511 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
5512 {
5513 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5514
5515 /* Process Unlocked */
5516 __HAL_UNLOCK(hhrtim);
5517
5518 return HAL_ERROR;
5519 }
5520
5521 /* Enable the timer DMA request */
5522 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
5523 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5524 }
5525
5526 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5527 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5528 timer_idx++)
5529 {
5530 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
5531 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5532 {
5533 /* Get the timer DMA handler */
5534 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5535
5536 if (hdma == NULL)
5537 {
5538 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5539
5540 /* Process Unlocked */
5541 __HAL_UNLOCK(hhrtim);
5542
5543 return HAL_ERROR;
5544 }
5545
5546 /* Set the DMA error callback */
5547 hdma->XferErrorCallback = HRTIM_DMAError ;
5548
5549 /* Set the DMA transfer completed callback */
5550 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
5551
5552 /* Enable the DMA channel */
5553 if (HAL_DMA_Start_IT(hdma,
5554 hhrtim->TimerParam[timer_idx].DMASrcAddress,
5555 hhrtim->TimerParam[timer_idx].DMADstAddress,
5556 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
5557 {
5558 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5559
5560 /* Process Unlocked */
5561 __HAL_UNLOCK(hhrtim);
5562
5563 return HAL_ERROR;
5564 }
5565
5566 /* Enable the timer DMA request */
5567 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
5568 timer_idx,
5569 hhrtim->TimerParam[timer_idx].DMARequests);
5570 }
5571 }
5572
5573 /* Enable the timer counter */
5574 __HAL_HRTIM_ENABLE(hhrtim, Timers);
5575
5576 hhrtim->State = HAL_HRTIM_STATE_READY;
5577
5578 /* Process Unlocked */
5579 __HAL_UNLOCK(hhrtim);
5580
5581 return HAL_OK;
5582 }
5583
5584 /**
5585 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5586 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5587 * @param hhrtim pointer to HAL HRTIM handle
5588 * @param Timers Timer counter(s) to stop
5589 * This parameter can be any combination of the following values:
5590 * @arg HRTIM_TIMERID_MASTER
5591 * @arg HRTIM_TIMERID_TIMER_A
5592 * @arg HRTIM_TIMERID_TIMER_B
5593 * @arg HRTIM_TIMERID_TIMER_C
5594 * @arg HRTIM_TIMERID_TIMER_D
5595 * @arg HRTIM_TIMERID_TIMER_E
5596 * @retval HAL status
5597 * @note The counter of a timer is stopped only if all timer outputs are disabled
5598 * @note All enabled timer related DMA requests are disabled.
5599 */
HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5600 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
5601 uint32_t Timers)
5602 {
5603 uint8_t timer_idx;
5604
5605 /* Check the parameters */
5606 assert_param(IS_HRTIM_TIMERID(Timers));
5607
5608 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5609
5610 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
5611 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5612 {
5613 /* Disable the DMA */
5614 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
5615 {
5616 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5617 }
5618 else
5619 {
5620 hhrtim->State = HAL_HRTIM_STATE_READY;
5621 /* Disable the DMA request(s) */
5622 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
5623 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5624 }
5625 }
5626
5627 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5628 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5629 timer_idx++)
5630 {
5631 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
5632 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5633 {
5634 /* Get the timer DMA handler */
5635 /* Disable the DMA */
5636 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
5637 {
5638 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5639 }
5640 else
5641 {
5642 hhrtim->State = HAL_HRTIM_STATE_READY;
5643
5644 /* Disable the DMA request(s) */
5645 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5646 timer_idx,
5647 hhrtim->TimerParam[timer_idx].DMARequests);
5648 }
5649 }
5650 }
5651
5652 /* Disable the timer counter */
5653 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5654
5655 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5656 {
5657 return HAL_ERROR;
5658 }
5659 else
5660 {
5661 return HAL_OK;
5662 }
5663 }
5664
5665 /**
5666 * @brief Enable or disables the HRTIM burst mode controller.
5667 * @param hhrtim pointer to HAL HRTIM handle
5668 * @param Enable Burst mode controller enabling
5669 * This parameter can be one of the following values:
5670 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
5671 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
5672 * @retval HAL status
5673 * @note This function must be called after starting the timer(s)
5674 */
HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Enable)5675 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
5676 uint32_t Enable)
5677 {
5678 /* Check parameters */
5679 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
5680
5681 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5682 {
5683 return HAL_BUSY;
5684 }
5685
5686 /* Process Locked */
5687 __HAL_LOCK(hhrtim);
5688
5689 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5690
5691 /* Enable/Disable the burst mode controller */
5692 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
5693
5694 hhrtim->State = HAL_HRTIM_STATE_READY;
5695
5696 /* Process Unlocked */
5697 __HAL_UNLOCK(hhrtim);
5698
5699 return HAL_OK;
5700 }
5701
5702 /**
5703 * @brief Trig the burst mode operation.
5704 * @param hhrtim pointer to HAL HRTIM handle
5705 * @retval HAL status
5706 */
HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef * hhrtim)5707 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
5708 {
5709 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5710 {
5711 return HAL_BUSY;
5712 }
5713
5714 /* Process Locked */
5715 __HAL_LOCK(hhrtim);
5716
5717 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5718
5719 /* Software trigger of the burst mode controller */
5720 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
5721
5722 hhrtim->State = HAL_HRTIM_STATE_READY;
5723
5724 /* Process Unlocked */
5725 __HAL_UNLOCK(hhrtim);
5726
5727 return HAL_OK;
5728 }
5729
5730 /**
5731 * @brief Trig a software capture on the designed capture unit
5732 * @param hhrtim pointer to HAL HRTIM handle
5733 * @param TimerIdx Timer index
5734 * This parameter can be one of the following values:
5735 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5736 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5737 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5738 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5739 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5740 * @param CaptureUnit Capture unit to trig
5741 * This parameter can be one of the following values:
5742 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5743 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5744 * @retval HAL status
5745 * @note The 'software capture' bit in the capure configuration register is
5746 * automatically reset by hardware
5747 */
HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)5748 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
5749 uint32_t TimerIdx,
5750 uint32_t CaptureUnit)
5751 {
5752 /* Check parameters */
5753 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5754 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5755
5756 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5757 {
5758 return HAL_BUSY;
5759 }
5760
5761 /* Process Locked */
5762 __HAL_LOCK(hhrtim);
5763
5764 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5765
5766 /* Force a software capture on concerned capture unit */
5767 switch (CaptureUnit)
5768 {
5769 case HRTIM_CAPTUREUNIT_1:
5770 {
5771 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
5772 break;
5773 }
5774
5775 case HRTIM_CAPTUREUNIT_2:
5776 {
5777 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
5778 break;
5779 }
5780
5781 default:
5782 {
5783 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5784
5785 /* Process Unlocked */
5786 __HAL_UNLOCK(hhrtim);
5787
5788 break;
5789 }
5790 }
5791
5792 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5793 {
5794 return HAL_ERROR;
5795 }
5796
5797 hhrtim->State = HAL_HRTIM_STATE_READY;
5798
5799 /* Process Unlocked */
5800 __HAL_UNLOCK(hhrtim);
5801
5802 return HAL_OK;
5803 }
5804
5805 /**
5806 * @brief Trig the update of the registers of one or several timers
5807 * @param hhrtim pointer to HAL HRTIM handle
5808 * @param Timers timers concerned with the software register update
5809 * This parameter can be any combination of the following values:
5810 * @arg HRTIM_TIMERUPDATE_MASTER
5811 * @arg HRTIM_TIMERUPDATE_A
5812 * @arg HRTIM_TIMERUPDATE_B
5813 * @arg HRTIM_TIMERUPDATE_C
5814 * @arg HRTIM_TIMERUPDATE_D
5815 * @arg HRTIM_TIMERUPDATE_E
5816 * @retval HAL status
5817 * @note The 'software update' bits in the HRTIM control register 2 register are
5818 * automatically reset by hardware
5819 */
HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5820 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
5821 uint32_t Timers)
5822 {
5823 /* Check parameters */
5824 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5825
5826 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5827 {
5828 return HAL_BUSY;
5829 }
5830
5831 /* Process Locked */
5832 __HAL_LOCK(hhrtim);
5833
5834 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5835
5836 /* Force timer(s) registers update */
5837 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
5838
5839 hhrtim->State = HAL_HRTIM_STATE_READY;
5840
5841 /* Process Unlocked */
5842 __HAL_UNLOCK(hhrtim);
5843
5844 return HAL_OK;
5845 }
5846
5847 /**
5848 * @brief Trig the reset of one or several timers
5849 * @param hhrtim pointer to HAL HRTIM handle
5850 * @param Timers timers concerned with the software counter reset
5851 * This parameter can be any combination of the following values:
5852 * @arg HRTIM_TIMERRESET_MASTER
5853 * @arg HRTIM_TIMERRESET_TIMER_A
5854 * @arg HRTIM_TIMERRESET_TIMER_B
5855 * @arg HRTIM_TIMERRESET_TIMER_C
5856 * @arg HRTIM_TIMERRESET_TIMER_D
5857 * @arg HRTIM_TIMERRESET_TIMER_E
5858 * @retval HAL status
5859 * @note The 'software reset' bits in the HRTIM control register 2 are
5860 * automatically reset by hardware
5861 */
HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5862 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
5863 uint32_t Timers)
5864 {
5865 /* Check parameters */
5866 assert_param(IS_HRTIM_TIMERRESET(Timers));
5867
5868 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5869 {
5870 return HAL_BUSY;
5871 }
5872
5873 /* Process Locked */
5874 __HAL_LOCK(hhrtim);
5875
5876 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5877
5878 /* Force timer(s) registers reset */
5879 hhrtim->Instance->sCommonRegs.CR2 = Timers;
5880
5881 hhrtim->State = HAL_HRTIM_STATE_READY;
5882
5883 /* Process Unlocked */
5884 __HAL_UNLOCK(hhrtim);
5885
5886 return HAL_OK;
5887 }
5888
5889 /**
5890 * @brief Start a burst DMA operation to update HRTIM control registers content
5891 * @param hhrtim pointer to HAL HRTIM handle
5892 * @param TimerIdx Timer index
5893 * This parameter can be one of the following values:
5894 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5895 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5896 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5897 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5898 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5899 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5900 * @param BurstBufferAddress address of the buffer the HRTIM control registers
5901 * content will be updated from.
5902 * @param BurstBufferLength size (in WORDS) of the burst buffer.
5903 * @retval HAL status
5904 * @note The TimerIdx parameter determines the dma channel to be used by the
5905 * DMA burst controller (see below)
5906 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
5907 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
5908 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
5909 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
5910 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
5911 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
5912 */
HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t BurstBufferAddress,uint32_t BurstBufferLength)5913 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
5914 uint32_t TimerIdx,
5915 uint32_t BurstBufferAddress,
5916 uint32_t BurstBufferLength)
5917 {
5918 DMA_HandleTypeDef * hdma;
5919
5920 /* Check the parameters */
5921 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5922
5923 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5924 {
5925 return HAL_BUSY;
5926 }
5927 if(hhrtim->State == HAL_HRTIM_STATE_READY)
5928 {
5929 if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
5930 {
5931 return HAL_ERROR;
5932 }
5933 else
5934 {
5935 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5936 }
5937 }
5938
5939 /* Process Locked */
5940 __HAL_LOCK(hhrtim);
5941
5942 /* Get the timer DMA handler */
5943 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
5944
5945 if (hdma == NULL)
5946 {
5947 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5948
5949 /* Process Unlocked */
5950 __HAL_UNLOCK(hhrtim);
5951
5952 return HAL_ERROR;
5953 }
5954
5955 /* Set the DMA transfer completed callback */
5956 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
5957
5958 /* Set the DMA error callback */
5959 hdma->XferErrorCallback = HRTIM_DMAError ;
5960
5961 /* Enable the DMA channel */
5962 if (HAL_DMA_Start_IT(hdma,
5963 BurstBufferAddress,
5964 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
5965 BurstBufferLength) != HAL_OK)
5966 {
5967 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5968
5969 /* Process Unlocked */
5970 __HAL_UNLOCK(hhrtim);
5971
5972 return HAL_ERROR;
5973 }
5974
5975 hhrtim->State = HAL_HRTIM_STATE_READY;
5976
5977 /* Process Unlocked */
5978 __HAL_UNLOCK(hhrtim);
5979
5980 return HAL_OK;
5981 }
5982
5983 /**
5984 * @brief Enable the transfer from preload to active registers for one
5985 * or several timing units (including master timer).
5986 * @param hhrtim pointer to HAL HRTIM handle
5987 * @param Timers Timer(s) concerned by the register preload enabling command
5988 * This parameter can be any combination of the following values:
5989 * @arg HRTIM_TIMERUPDATE_MASTER
5990 * @arg HRTIM_TIMERUPDATE_A
5991 * @arg HRTIM_TIMERUPDATE_B
5992 * @arg HRTIM_TIMERUPDATE_C
5993 * @arg HRTIM_TIMERUPDATE_D
5994 * @arg HRTIM_TIMERUPDATE_E
5995 * @retval HAL status
5996 */
HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5997 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
5998 uint32_t Timers)
5999 {
6000 /* Check the parameters */
6001 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
6002
6003 /* Process Locked */
6004 __HAL_LOCK(hhrtim);
6005
6006 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6007
6008 /* Enable timer(s) registers update */
6009 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
6010
6011 hhrtim->State = HAL_HRTIM_STATE_READY;
6012
6013 /* Process Unlocked */
6014 __HAL_UNLOCK(hhrtim);
6015
6016 return HAL_OK;
6017 }
6018
6019 /**
6020 * @brief Disable the transfer from preload to active registers for one
6021 * or several timing units (including master timer).
6022 * @param hhrtim pointer to HAL HRTIM handle
6023 * @param Timers Timer(s) concerned by the register preload disabling command
6024 * This parameter can be any combination of the following values:
6025 * @arg HRTIM_TIMERUPDATE_MASTER
6026 * @arg HRTIM_TIMERUPDATE_A
6027 * @arg HRTIM_TIMERUPDATE_B
6028 * @arg HRTIM_TIMERUPDATE_C
6029 * @arg HRTIM_TIMERUPDATE_D
6030 * @arg HRTIM_TIMERUPDATE_E
6031 * @retval HAL status
6032 */
HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6033 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
6034 uint32_t Timers)
6035 {
6036 /* Check the parameters */
6037 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
6038
6039 /* Process Locked */
6040 __HAL_LOCK(hhrtim);
6041
6042 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6043
6044 /* Enable timer(s) registers update */
6045 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
6046
6047 hhrtim->State = HAL_HRTIM_STATE_READY;
6048
6049 /* Process Unlocked */
6050 __HAL_UNLOCK(hhrtim);
6051
6052 return HAL_OK;
6053 }
6054
6055 /**
6056 * @}
6057 */
6058
6059 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
6060 * @brief Peripheral State functions
6061 @verbatim
6062 ===============================================================================
6063 ##### Peripheral State functions #####
6064 ===============================================================================
6065 [..] This section provides functions used to get HRTIM or HRTIM timer
6066 specific information:
6067 (+) Get HRTIM HAL state
6068 (+) Get captured value
6069 (+) Get HRTIM timer output level
6070 (+) Get HRTIM timer output state
6071 (+) Get delayed protection status
6072 (+) Get burst status
6073 (+) Get current push-pull status
6074 (+) Get idle push-pull status
6075
6076 @endverbatim
6077 * @{
6078 */
6079
6080 /**
6081 * @brief Return the HRTIM HAL state
6082 * @param hhrtim pointer to HAL HRTIM handle
6083 * @retval HAL state
6084 */
HAL_HRTIM_GetState(const HRTIM_HandleTypeDef * hhrtim)6085 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim)
6086 {
6087 /* Return HRTIM state */
6088 return hhrtim->State;
6089 }
6090
6091 /**
6092 * @brief Return actual value of the capture register of the designated capture unit
6093 * @param hhrtim pointer to HAL HRTIM handle
6094 * @param TimerIdx Timer index
6095 * This parameter can be one of the following values:
6096 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6097 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6098 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6099 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6100 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6101 * @param CaptureUnit Capture unit to trig
6102 * This parameter can be one of the following values:
6103 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
6104 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
6105 * @retval Captured value
6106 */
HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)6107 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
6108 uint32_t TimerIdx,
6109 uint32_t CaptureUnit)
6110 {
6111 uint32_t captured_value;
6112
6113 /* Check parameters */
6114 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6115 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
6116
6117 /* Read captured value */
6118 switch (CaptureUnit)
6119 {
6120 case HRTIM_CAPTUREUNIT_1:
6121 {
6122 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
6123 break;
6124 }
6125
6126 case HRTIM_CAPTUREUNIT_2:
6127 {
6128 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
6129 break;
6130 }
6131
6132 default:
6133 {
6134 captured_value = 0xFFFFFFFFUL;
6135 break;
6136 }
6137
6138 }
6139
6140 return captured_value;
6141 }
6142
6143
6144 /**
6145 * @brief Return actual level (active or inactive) of the designated output
6146 * @param hhrtim pointer to HAL HRTIM handle
6147 * @param TimerIdx Timer index
6148 * This parameter can be one of the following values:
6149 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6150 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6151 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6152 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6153 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6154 * @param Output Timer output
6155 * This parameter can be one of the following values:
6156 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6157 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6158 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6159 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6160 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6161 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6162 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6163 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6164 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6165 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6166 * @retval Output level
6167 * @note Returned output level is taken before the output stage (chopper,
6168 * polarity).
6169 */
HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6170 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,
6171 uint32_t TimerIdx,
6172 uint32_t Output)
6173 {
6174 uint32_t output_level;
6175
6176 /* Check parameters */
6177 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6178
6179 /* Read the output level */
6180 switch (Output)
6181 {
6182 case HRTIM_OUTPUT_TA1:
6183 case HRTIM_OUTPUT_TB1:
6184 case HRTIM_OUTPUT_TC1:
6185 case HRTIM_OUTPUT_TD1:
6186 case HRTIM_OUTPUT_TE1:
6187 {
6188 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
6189 {
6190 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6191 }
6192 else
6193 {
6194 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6195 }
6196 break;
6197 }
6198
6199 case HRTIM_OUTPUT_TA2:
6200 case HRTIM_OUTPUT_TB2:
6201 case HRTIM_OUTPUT_TC2:
6202 case HRTIM_OUTPUT_TD2:
6203 case HRTIM_OUTPUT_TE2:
6204 {
6205 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
6206 {
6207 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6208 }
6209 else
6210 {
6211 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6212 }
6213 break;
6214 }
6215
6216 default:
6217 {
6218 output_level = 0xFFFFFFFFUL;
6219 break;
6220 }
6221 }
6222
6223 return output_level;
6224 }
6225
6226 /**
6227 * @brief Return actual state (RUN, IDLE, FAULT) of the designated output
6228 * @param hhrtim pointer to HAL HRTIM handle
6229 * @param TimerIdx Timer index
6230 * This parameter can be one of the following values:
6231 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6232 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6233 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6234 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6235 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6236 * @param Output Timer output
6237 * This parameter can be one of the following values:
6238 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6239 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6240 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6241 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6242 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6243 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6244 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6245 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6246 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6247 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6248 * @retval Output state
6249 */
HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6250 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
6251 uint32_t TimerIdx,
6252 uint32_t Output)
6253 {
6254 uint32_t output_bit;
6255 uint32_t output_state;
6256
6257 /* Check parameters */
6258 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6259
6260 /* Prevent unused argument(s) compilation warning */
6261 UNUSED(TimerIdx);
6262
6263 /* Set output state according to output control status and output disable status */
6264 switch (Output)
6265 {
6266 case HRTIM_OUTPUT_TA1:
6267 {
6268 output_bit = HRTIM_OENR_TA1OEN;
6269 break;
6270 }
6271
6272 case HRTIM_OUTPUT_TA2:
6273 {
6274 output_bit = HRTIM_OENR_TA2OEN;
6275 break;
6276 }
6277
6278 case HRTIM_OUTPUT_TB1:
6279 {
6280 output_bit = HRTIM_OENR_TB1OEN;
6281 break;
6282 }
6283
6284 case HRTIM_OUTPUT_TB2:
6285 {
6286 output_bit = HRTIM_OENR_TB2OEN;
6287 break;
6288 }
6289
6290 case HRTIM_OUTPUT_TC1:
6291 {
6292 output_bit = HRTIM_OENR_TC1OEN;
6293 break;
6294 }
6295
6296 case HRTIM_OUTPUT_TC2:
6297 {
6298 output_bit = HRTIM_OENR_TC2OEN;
6299 break;
6300 }
6301
6302 case HRTIM_OUTPUT_TD1:
6303 {
6304 output_bit = HRTIM_OENR_TD1OEN;
6305 break;
6306 }
6307
6308 case HRTIM_OUTPUT_TD2:
6309 {
6310 output_bit = HRTIM_OENR_TD2OEN;
6311 break;
6312 }
6313
6314 case HRTIM_OUTPUT_TE1:
6315 {
6316 output_bit = HRTIM_OENR_TE1OEN;
6317 break;
6318 }
6319
6320 case HRTIM_OUTPUT_TE2:
6321 {
6322 output_bit = HRTIM_OENR_TE2OEN;
6323 break;
6324 }
6325
6326 default:
6327 {
6328 output_bit = 0UL;
6329 break;
6330 }
6331 }
6332
6333 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
6334 {
6335 /* Output is enabled: output in RUN state (whatever output disable status is)*/
6336 output_state = HRTIM_OUTPUTSTATE_RUN;
6337 }
6338 else
6339 {
6340 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
6341 {
6342 /* Output is disabled: output in FAULT state */
6343 output_state = HRTIM_OUTPUTSTATE_FAULT;
6344 }
6345 else
6346 {
6347 /* Output is disabled: output in IDLE state */
6348 output_state = HRTIM_OUTPUTSTATE_IDLE;
6349 }
6350 }
6351
6352 return(output_state);
6353 }
6354
6355 /**
6356 * @brief Return the level (active or inactive) of the designated output
6357 * when the delayed protection was triggered.
6358 * @param hhrtim pointer to HAL HRTIM handle
6359 * @param TimerIdx Timer index
6360 * This parameter can be one of the following values:
6361 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6362 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6363 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6364 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6365 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6366 * @param Output Timer output
6367 * This parameter can be one of the following values:
6368 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6369 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6370 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6371 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6372 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6373 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6374 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6375 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6376 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6377 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6378 * @retval Delayed protection status
6379 */
HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6380 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,
6381 uint32_t TimerIdx,
6382 uint32_t Output)
6383 {
6384 uint32_t delayed_protection_status;
6385
6386 /* Check parameters */
6387 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6388
6389 /* Read the delayed protection status */
6390 switch (Output)
6391 {
6392 case HRTIM_OUTPUT_TA1:
6393 case HRTIM_OUTPUT_TB1:
6394 case HRTIM_OUTPUT_TC1:
6395 case HRTIM_OUTPUT_TD1:
6396 case HRTIM_OUTPUT_TE1:
6397 {
6398 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
6399 {
6400 /* Output 1 was active when the delayed idle protection was triggered */
6401 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6402 }
6403 else
6404 {
6405 /* Output 1 was inactive when the delayed idle protection was triggered */
6406 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6407 }
6408 break;
6409 }
6410
6411 case HRTIM_OUTPUT_TA2:
6412 case HRTIM_OUTPUT_TB2:
6413 case HRTIM_OUTPUT_TC2:
6414 case HRTIM_OUTPUT_TD2:
6415 case HRTIM_OUTPUT_TE2:
6416 {
6417 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
6418 {
6419 /* Output 2 was active when the delayed idle protection was triggered */
6420 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6421 }
6422 else
6423 {
6424 /* Output 2 was inactive when the delayed idle protection was triggered */
6425 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6426 }
6427 break;
6428 }
6429
6430 default:
6431 {
6432 delayed_protection_status = 0xFFFFFFFFUL;
6433 break;
6434 }
6435 }
6436
6437 return delayed_protection_status;
6438 }
6439
6440 /**
6441 * @brief Return the actual status (active or inactive) of the burst mode controller
6442 * @param hhrtim pointer to HAL HRTIM handle
6443 * @retval Burst mode controller status
6444 */
HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)6445 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)
6446 {
6447 uint32_t burst_mode_status;
6448
6449 /* Read burst mode status */
6450 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
6451
6452 return burst_mode_status;
6453 }
6454
6455 /**
6456 * @brief Indicate on which output the signal is currently active (when the
6457 * push pull mode is enabled).
6458 * @param hhrtim pointer to HAL HRTIM handle
6459 * @param TimerIdx Timer index
6460 * This parameter can be one of the following values:
6461 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6462 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6463 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6464 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6465 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6466 * @retval Burst mode controller status
6467 */
HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6468 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
6469 uint32_t TimerIdx)
6470 {
6471 uint32_t current_pushpull_status;
6472
6473 /* Check the parameters */
6474 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6475
6476 /* Read current push pull status */
6477 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
6478
6479 return current_pushpull_status;
6480 }
6481
6482
6483 /**
6484 * @brief Indicate on which output the signal was applied, in push-pull mode,
6485 balanced fault mode or delayed idle mode, when the protection was triggered.
6486 * @param hhrtim pointer to HAL HRTIM handle
6487 * @param TimerIdx Timer index
6488 * This parameter can be one of the following values:
6489 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6490 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6491 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6492 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6493 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6494 * @retval Idle Push Pull Status
6495 */
HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6496 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
6497 uint32_t TimerIdx)
6498 {
6499 uint32_t idle_pushpull_status;
6500
6501 /* Check the parameters */
6502 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6503
6504 /* Read current push pull status */
6505 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
6506
6507 return idle_pushpull_status;
6508 }
6509
6510 /**
6511 * @}
6512 */
6513
6514 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
6515 * @brief Functions called when HRTIM generates an interrupt
6516 * 7 interrupts can be generated by the master timer:
6517 * - Master timer registers update
6518 * - Synchronization event received
6519 * - Master timer repetition event
6520 * - Master Compare 1 to 4 event
6521 * 14 interrupts can be generated by each timing unit:
6522 * - Delayed protection triggered
6523 * - Counter reset or roll-over event
6524 * - Output 1 and output 2 reset (transition active to inactive)
6525 * - Output 1 and output 2 set (transition inactive to active)
6526 * - Capture 1 and 2 events
6527 * - Timing unit registers update
6528 * - Repetition event
6529 * - Compare 1 to 4 event
6530 * 8 global interrupts are generated for the whole HRTIM:
6531 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
6532 * - DLL calibration done
6533 * - Burst mode period completed
6534 @verbatim
6535 ===============================================================================
6536 ##### HRTIM interrupts handling #####
6537 ===============================================================================
6538 [..]
6539 This subsection provides a set of functions allowing to manage the HRTIM
6540 interrupts:
6541 (+) HRTIM interrupt handler
6542 (+) Callback function called when Fault1 interrupt occurs
6543 (+) Callback function called when Fault2 interrupt occurs
6544 (+) Callback function called when Fault3 interrupt occurs
6545 (+) Callback function called when Fault4 interrupt occurs
6546 (+) Callback function called when Fault5 interrupt occurs
6547 (+) Callback function called when system Fault interrupt occurs
6548 (+) Callback function called when DLL ready interrupt occurs
6549 (+) Callback function called when burst mode period interrupt occurs
6550 (+) Callback function called when synchronization input interrupt occurs
6551 (+) Callback function called when a timer register update interrupt occurs
6552 (+) Callback function called when a timer repetition interrupt occurs
6553 (+) Callback function called when a compare 1 match interrupt occurs
6554 (+) Callback function called when a compare 2 match interrupt occurs
6555 (+) Callback function called when a compare 3 match interrupt occurs
6556 (+) Callback function called when a compare 4 match interrupt occurs
6557 (+) Callback function called when a capture 1 interrupt occurs
6558 (+) Callback function called when a capture 2 interrupt occurs
6559 (+) Callback function called when a delayed protection interrupt occurs
6560 (+) Callback function called when a timer counter reset interrupt occurs
6561 (+) Callback function called when a timer output 1 set interrupt occurs
6562 (+) Callback function called when a timer output 1 reset interrupt occurs
6563 (+) Callback function called when a timer output 2 set interrupt occurs
6564 (+) Callback function called when a timer output 2 reset interrupt occurs
6565 (+) Callback function called when a timer output 2 reset interrupt occurs
6566 (+) Callback function called upon completion of a burst DMA transfer
6567 (+) HRTIM callback function registration
6568 (+) HRTIM callback function unregistration
6569 (+) HRTIM Timer x callback function registration
6570 (+) HRTIM Timer x callback function unregistration
6571
6572 @endverbatim
6573 * @{
6574 */
6575
6576 /**
6577 * @brief This function handles HRTIM interrupt request.
6578 * @param hhrtim pointer to HAL HRTIM handle
6579 * @param TimerIdx Timer index
6580 * This parameter can be any value of HRTIM_Timer_Index
6581 * @retval None
6582 */
HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6583 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
6584 uint32_t TimerIdx)
6585 {
6586 /* HRTIM interrupts handling */
6587 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
6588 {
6589 HRTIM_HRTIM_ISR(hhrtim);
6590 }
6591 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6592 {
6593 /* Master related interrupts handling */
6594 HRTIM_Master_ISR(hhrtim);
6595 }
6596 else
6597 {
6598 /* Timing unit related interrupts handling */
6599 HRTIM_Timer_ISR(hhrtim, TimerIdx);
6600 }
6601
6602 }
6603
6604 /**
6605 * @brief Callback function invoked when a fault 1 interrupt occurred
6606 * @param hhrtim pointer to HAL HRTIM handle * @retval None
6607 * @retval None
6608 */
HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)6609 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
6610 {
6611 /* Prevent unused argument(s) compilation warning */
6612 UNUSED(hhrtim);
6613
6614 /* NOTE : This function should not be modified, when the callback is needed,
6615 the HAL_HRTIM_Fault1Callback could be implemented in the user file
6616 */
6617 }
6618
6619 /**
6620 * @brief Callback function invoked when a fault 2 interrupt occurred
6621 * @param hhrtim pointer to HAL HRTIM handle
6622 * @retval None
6623 */
HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)6624 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
6625 {
6626 /* Prevent unused argument(s) compilation warning */
6627 UNUSED(hhrtim);
6628
6629 /* NOTE : This function should not be modified, when the callback is needed,
6630 the HAL_HRTIM_Fault2Callback could be implemented in the user file
6631 */
6632 }
6633
6634 /**
6635 * @brief Callback function invoked when a fault 3 interrupt occurred
6636 * @param hhrtim pointer to HAL HRTIM handle
6637 * @retval None
6638 */
HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)6639 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
6640 {
6641 /* Prevent unused argument(s) compilation warning */
6642 UNUSED(hhrtim);
6643
6644 /* NOTE : This function should not be modified, when the callback is needed,
6645 the HAL_HRTIM_Fault3Callback could be implemented in the user file
6646 */
6647 }
6648
6649 /**
6650 * @brief Callback function invoked when a fault 4 interrupt occurred
6651 * @param hhrtim pointer to HAL HRTIM handle
6652 * @retval None
6653 */
HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)6654 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
6655 {
6656 /* Prevent unused argument(s) compilation warning */
6657 UNUSED(hhrtim);
6658
6659 /* NOTE : This function should not be modified, when the callback is needed,
6660 the HAL_HRTIM_Fault4Callback could be implemented in the user file
6661 */
6662 }
6663
6664 /**
6665 * @brief Callback function invoked when a fault 5 interrupt occurred
6666 * @param hhrtim pointer to HAL HRTIM handle
6667 * @retval None
6668 */
HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)6669 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
6670 {
6671 /* Prevent unused argument(s) compilation warning */
6672 UNUSED(hhrtim);
6673
6674 /* NOTE : This function should not be modified, when the callback is needed,
6675 the HAL_HRTIM_Fault5Callback could be implemented in the user file
6676 */
6677 }
6678
6679 /**
6680 * @brief Callback function invoked when a system fault interrupt occurred
6681 * @param hhrtim pointer to HAL HRTIM handle
6682 * @retval None
6683 */
HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)6684 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
6685 {
6686 /* Prevent unused argument(s) compilation warning */
6687 UNUSED(hhrtim);
6688
6689 /* NOTE : This function should not be modified, when the callback is needed,
6690 the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
6691 */
6692 }
6693
6694 /**
6695 * @brief Callback function invoked when the DLL calibration is completed
6696 * @param hhrtim pointer to HAL HRTIM handle
6697 * @retval None
6698 */
HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)6699 __weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
6700 {
6701 /* Prevent unused argument(s) compilation warning */
6702 UNUSED(hhrtim);
6703
6704 /* NOTE : This function should not be modified, when the callback is needed,
6705 the HAL_HRTIM_DLLCalibrationCallback could be implemented in the user file
6706 */
6707 }
6708
6709 /**
6710 * @brief Callback function invoked when the end of the burst mode period is reached
6711 * @param hhrtim pointer to HAL HRTIM handle
6712 * @retval None
6713 */
HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)6714 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
6715 {
6716 /* Prevent unused argument(s) compilation warning */
6717 UNUSED(hhrtim);
6718
6719 /* NOTE : This function should not be modified, when the callback is needed,
6720 the HAL_HRTIM_BurstModeCallback could be implemented in the user file
6721 */
6722 }
6723
6724 /**
6725 * @brief Callback function invoked when a synchronization input event is received
6726 * @param hhrtim pointer to HAL HRTIM handle
6727 * @retval None
6728 */
HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)6729 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
6730 {
6731 /* Prevent unused argument(s) compilation warning */
6732 UNUSED(hhrtim);
6733
6734 /* NOTE : This function should not be modified, when the callback is needed,
6735 the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
6736 */
6737 }
6738
6739 /**
6740 * @brief Callback function invoked when timer registers are updated
6741 * @param hhrtim pointer to HAL HRTIM handle
6742 * @param TimerIdx Timer index
6743 * This parameter can be one of the following values:
6744 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6745 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6746 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6747 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6748 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6749 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6750 * @retval None
6751 */
HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6752 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
6753 uint32_t TimerIdx)
6754 {
6755 /* Prevent unused argument(s) compilation warning */
6756 UNUSED(hhrtim);
6757 UNUSED(TimerIdx);
6758
6759 /* NOTE : This function should not be modified, when the callback is needed,
6760 the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
6761 */
6762 }
6763
6764 /**
6765 * @brief Callback function invoked when timer repetition period has elapsed
6766 * @param hhrtim pointer to HAL HRTIM handle
6767 * @param TimerIdx Timer index
6768 * This parameter can be one of the following values:
6769 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6770 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6771 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6772 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6773 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6774 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6775 * @retval None
6776 */
HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6777 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
6778 uint32_t TimerIdx)
6779 {
6780 /* Prevent unused argument(s) compilation warning */
6781 UNUSED(hhrtim);
6782 UNUSED(TimerIdx);
6783
6784 /* NOTE : This function should not be modified, when the callback is needed,
6785 the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
6786 */
6787 }
6788
6789 /**
6790 * @brief Callback function invoked when the timer counter matches the value
6791 * programmed in the compare 1 register
6792 * @param hhrtim pointer to HAL HRTIM handle
6793 * @param TimerIdx Timer index
6794 * This parameter can be one of the following values:
6795 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6796 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6797 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6798 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6799 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6800 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6801 * @retval None
6802 */
HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6803 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6804 uint32_t TimerIdx)
6805 {
6806 /* Prevent unused argument(s) compilation warning */
6807 UNUSED(hhrtim);
6808 UNUSED(TimerIdx);
6809
6810 /* NOTE : This function should not be modified, when the callback is needed,
6811 the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
6812 */
6813 }
6814
6815 /**
6816 * @brief Callback function invoked when the timer counter matches the value
6817 * programmed in the compare 2 register
6818 * @param hhrtim pointer to HAL HRTIM handle
6819 * @retval None
6820 * @param TimerIdx Timer index
6821 * This parameter can be one of the following values:
6822 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6823 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6824 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6825 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6826 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6827 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6828 */
HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6829 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6830 uint32_t TimerIdx)
6831 {
6832 /* Prevent unused argument(s) compilation warning */
6833 UNUSED(hhrtim);
6834 UNUSED(TimerIdx);
6835
6836 /* NOTE : This function should not be modified, when the callback is needed,
6837 the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
6838 */
6839 }
6840
6841 /**
6842 * @brief Callback function invoked when the timer counter matches the value
6843 * programmed in the compare 3 register
6844 * @param hhrtim pointer to HAL HRTIM handle
6845 * @param TimerIdx Timer index
6846 * This parameter can be one of the following values:
6847 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6848 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6849 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6850 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6851 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6852 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6853 * @retval None
6854 */
HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6855 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
6856 uint32_t TimerIdx)
6857 {
6858 /* Prevent unused argument(s) compilation warning */
6859 UNUSED(hhrtim);
6860 UNUSED(TimerIdx);
6861
6862 /* NOTE : This function should not be modified, when the callback is needed,
6863 the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
6864 */
6865 }
6866
6867 /**
6868 * @brief Callback function invoked when the timer counter matches the value
6869 * programmed in the compare 4 register.
6870 * @param hhrtim pointer to HAL HRTIM handle
6871 * @param TimerIdx Timer index
6872 * This parameter can be one of the following values:
6873 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6874 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6875 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6876 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6877 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6878 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6879 * @retval None
6880 */
HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6881 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
6882 uint32_t TimerIdx)
6883 {
6884 /* Prevent unused argument(s) compilation warning */
6885 UNUSED(hhrtim);
6886 UNUSED(TimerIdx);
6887
6888 /* NOTE : This function should not be modified, when the callback is needed,
6889 the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
6890 */
6891 }
6892
6893 /**
6894 * @brief Callback function invoked when the timer x capture 1 event occurs
6895 * @param hhrtim pointer to HAL HRTIM handle
6896 * @param TimerIdx Timer index
6897 * This parameter can be one of the following values:
6898 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6899 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6900 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6901 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6902 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6903 * @retval None
6904 */
HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6905 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6906 uint32_t TimerIdx)
6907 {
6908 /* Prevent unused argument(s) compilation warning */
6909 UNUSED(hhrtim);
6910 UNUSED(TimerIdx);
6911
6912 /* NOTE : This function should not be modified, when the callback is needed,
6913 the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
6914 */
6915 }
6916
6917 /**
6918 * @brief Callback function invoked when the timer x capture 2 event occurs
6919 * @param hhrtim pointer to HAL HRTIM handle
6920 * @param TimerIdx Timer index
6921 * This parameter can be one of the following values:
6922 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6923 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6924 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6925 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6926 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6927 * @retval None
6928 */
HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6929 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6930 uint32_t TimerIdx)
6931 {
6932 /* Prevent unused argument(s) compilation warning */
6933 UNUSED(hhrtim);
6934 UNUSED(TimerIdx);
6935
6936 /* NOTE : This function should not be modified, when the callback is needed,
6937 the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
6938 */
6939 }
6940
6941 /**
6942 * @brief Callback function invoked when the delayed idle or balanced idle mode is
6943 * entered.
6944 * @param hhrtim pointer to HAL HRTIM handle
6945 * @param TimerIdx Timer index
6946 * This parameter can be one of the following values:
6947 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6948 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6949 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6950 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6951 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6952 * @retval None
6953 */
HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6954 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
6955 uint32_t TimerIdx)
6956 {
6957 /* Prevent unused argument(s) compilation warning */
6958 UNUSED(hhrtim);
6959 UNUSED(TimerIdx);
6960
6961 /* NOTE : This function should not be modified, when the callback is needed,
6962 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
6963 */
6964 }
6965
6966 /**
6967 * @brief Callback function invoked when the timer x counter reset/roll-over
6968 * event occurs.
6969 * @param hhrtim pointer to HAL HRTIM handle
6970 * @param TimerIdx Timer index
6971 * This parameter can be one of the following values:
6972 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6973 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6974 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6975 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6976 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6977 * @retval None
6978 */
HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6979 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
6980 uint32_t TimerIdx)
6981 {
6982 /* Prevent unused argument(s) compilation warning */
6983 UNUSED(hhrtim);
6984 UNUSED(TimerIdx);
6985
6986 /* NOTE : This function should not be modified, when the callback is needed,
6987 the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
6988 */
6989 }
6990
6991 /**
6992 * @brief Callback function invoked when the timer x output 1 is set
6993 * @param hhrtim pointer to HAL HRTIM handle
6994 * @param TimerIdx Timer index
6995 * This parameter can be one of the following values:
6996 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6997 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6998 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6999 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7000 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7001 * @retval None
7002 */
HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7003 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
7004 uint32_t TimerIdx)
7005 {
7006 /* Prevent unused argument(s) compilation warning */
7007 UNUSED(hhrtim);
7008 UNUSED(TimerIdx);
7009
7010 /* NOTE : This function should not be modified, when the callback is needed,
7011 the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
7012 */
7013 }
7014
7015 /**
7016 * @brief Callback function invoked when the timer x output 1 is reset
7017 * @param hhrtim pointer to HAL HRTIM handle
7018 * @param TimerIdx Timer index
7019 * This parameter can be one of the following values:
7020 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7021 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7022 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7023 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7024 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7025 * @retval None
7026 */
HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7027 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
7028 uint32_t TimerIdx)
7029 {
7030 /* Prevent unused argument(s) compilation warning */
7031 UNUSED(hhrtim);
7032 UNUSED(TimerIdx);
7033
7034 /* NOTE : This function should not be modified, when the callback is needed,
7035 the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
7036 */
7037 }
7038
7039 /**
7040 * @brief Callback function invoked when the timer x output 2 is set
7041 * @param hhrtim pointer to HAL HRTIM handle
7042 * @param TimerIdx Timer index
7043 * This parameter can be one of the following values:
7044 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7045 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7046 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7047 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7048 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7049 * @retval None
7050 */
HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7051 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
7052 uint32_t TimerIdx)
7053 {
7054 /* Prevent unused argument(s) compilation warning */
7055 UNUSED(hhrtim);
7056 UNUSED(TimerIdx);
7057
7058 /* NOTE : This function should not be modified, when the callback is needed,
7059 the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
7060 */
7061 }
7062
7063 /**
7064 * @brief Callback function invoked when the timer x output 2 is reset
7065 * @param hhrtim pointer to HAL HRTIM handle
7066 * @param TimerIdx Timer index
7067 * This parameter can be one of the following values:
7068 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7069 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7070 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7071 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7072 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7073 * @retval None
7074 */
HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7075 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
7076 uint32_t TimerIdx)
7077 {
7078 /* Prevent unused argument(s) compilation warning */
7079 UNUSED(hhrtim);
7080 UNUSED(TimerIdx);
7081
7082 /* NOTE : This function should not be modified, when the callback is needed,
7083 the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
7084 */
7085 }
7086
7087 /**
7088 * @brief Callback function invoked when a DMA burst transfer is completed
7089 * @param hhrtim pointer to HAL HRTIM handle
7090 * @param TimerIdx Timer index
7091 * This parameter can be one of the following values:
7092 * @arg HRTIM_TIMERINDEX_MASTER for master timer
7093 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7094 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7095 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7096 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7097 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7098 * @retval None
7099 */
HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7100 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
7101 uint32_t TimerIdx)
7102 {
7103 /* Prevent unused argument(s) compilation warning */
7104 UNUSED(hhrtim);
7105 UNUSED(TimerIdx);
7106
7107 /* NOTE : This function should not be modified, when the callback is needed,
7108 the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
7109 */
7110 }
7111
7112 /**
7113 * @brief Callback function invoked when a DMA error occurs
7114 * @param hhrtim pointer to HAL HRTIM handle
7115 * @retval None
7116 */
HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef * hhrtim)7117 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
7118 {
7119 /* Prevent unused argument(s) compilation warning */
7120 UNUSED(hhrtim);
7121
7122 /* NOTE : This function should not be modified, when the callback is needed,
7123 the HAL_HRTIM_ErrorCallback could be implemented in the user file
7124 */
7125 }
7126
7127 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
7128 /**
7129 * @brief HRTIM callback function registration
7130 * @param hhrtim pointer to HAL HRTIM handle
7131 * @param CallbackID ID of the HRTIM callback function to register
7132 * This parameter can be one of the following values:
7133 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
7134 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
7135 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
7136 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
7137 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
7138 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
7139 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
7140 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
7141 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
7142 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
7143 * @arg HAL_HRTIM_MSPINIT_CB_ID
7144 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
7145 * @param pCallback Callback function pointer
7146 * @retval HAL status
7147 */
HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_CallbackTypeDef pCallback)7148 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7149 HAL_HRTIM_CallbackIDTypeDef CallbackID,
7150 pHRTIM_CallbackTypeDef pCallback)
7151 {
7152 HAL_StatusTypeDef status = HAL_OK;
7153
7154 if (pCallback == NULL)
7155 {
7156 /* Update the state */
7157 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7158
7159 return HAL_ERROR;
7160 }
7161
7162 /* Process locked */
7163 __HAL_LOCK(hhrtim);
7164
7165 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7166 {
7167 switch (CallbackID)
7168 {
7169 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7170 hhrtim->Fault1Callback = pCallback;
7171 break;
7172
7173 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7174 hhrtim->Fault2Callback = pCallback;
7175 break;
7176
7177 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7178 hhrtim->Fault3Callback = pCallback;
7179 break;
7180
7181 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7182 hhrtim->Fault4Callback = pCallback;
7183 break;
7184
7185 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7186 hhrtim->Fault5Callback = pCallback;
7187 break;
7188
7189 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7190 hhrtim->SystemFaultCallback = pCallback;
7191 break;
7192
7193 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
7194 hhrtim->DLLCalibrationReadyCallback = pCallback;
7195 break;
7196
7197 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7198 hhrtim->BurstModePeriodCallback = pCallback;
7199 break;
7200
7201 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7202 hhrtim->SynchronizationEventCallback = pCallback;
7203 break;
7204
7205 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7206 hhrtim->ErrorCallback = pCallback;
7207 break;
7208
7209 case HAL_HRTIM_MSPINIT_CB_ID :
7210 hhrtim->MspInitCallback = pCallback;
7211 break;
7212
7213 case HAL_HRTIM_MSPDEINIT_CB_ID :
7214 hhrtim->MspDeInitCallback = pCallback;
7215 break;
7216
7217 default :
7218 /* Update the state */
7219 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7220
7221 /* Return error status */
7222 status = HAL_ERROR;
7223 break;
7224 }
7225 }
7226 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7227 {
7228 switch (CallbackID)
7229 {
7230 case HAL_HRTIM_MSPINIT_CB_ID :
7231 hhrtim->MspInitCallback = pCallback;
7232 break;
7233
7234 case HAL_HRTIM_MSPDEINIT_CB_ID :
7235 hhrtim->MspDeInitCallback = pCallback;
7236 break;
7237
7238 default :
7239 /* Update the state */
7240 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7241
7242 /* Return error status */
7243 status = HAL_ERROR;
7244 break;
7245 }
7246 }
7247 else
7248 {
7249 /* Update the state */
7250 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7251
7252 /* Return error status */
7253 status = HAL_ERROR;
7254 }
7255
7256 /* Release Lock */
7257 __HAL_UNLOCK(hhrtim);
7258
7259 return status;
7260 }
7261
7262 /**
7263 * @brief HRTIM callback function un-registration
7264 * @param hhrtim pointer to HAL HRTIM handle
7265 * @param CallbackID ID of the HRTIM callback function to unregister
7266 * This parameter can be one of the following values:
7267 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
7268 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
7269 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
7270 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
7271 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
7272 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
7273 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
7274 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
7275 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
7276 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
7277 * @arg HAL_HRTIM_MSPINIT_CB_ID
7278 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
7279 * @retval HAL status
7280 */
HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)7281 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7282 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7283 {
7284 HAL_StatusTypeDef status = HAL_OK;
7285
7286 /* Process locked */
7287 __HAL_LOCK(hhrtim);
7288
7289 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7290 {
7291 switch (CallbackID)
7292 {
7293 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7294 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
7295 break;
7296
7297 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7298 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
7299 break;
7300
7301 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7302 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
7303 break;
7304
7305 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7306 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
7307 break;
7308
7309 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7310 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
7311 break;
7312
7313 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7314 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
7315 break;
7316
7317 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
7318 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
7319 break;
7320
7321 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7322 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
7323 break;
7324
7325 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7326 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
7327 break;
7328
7329 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7330 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
7331 break;
7332
7333 case HAL_HRTIM_MSPINIT_CB_ID :
7334 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7335 break;
7336
7337 case HAL_HRTIM_MSPDEINIT_CB_ID :
7338 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7339 break;
7340
7341 default :
7342 /* Update the state */
7343 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7344
7345 /* Return error status */
7346 status = HAL_ERROR;
7347 break;
7348 }
7349 }
7350 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7351 {
7352 switch (CallbackID)
7353 {
7354 case HAL_HRTIM_MSPINIT_CB_ID :
7355 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7356 break;
7357
7358 case HAL_HRTIM_MSPDEINIT_CB_ID :
7359 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7360 break;
7361
7362 default :
7363 /* Update the state */
7364 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7365
7366 /* Return error status */
7367 status = HAL_ERROR;
7368 break;
7369 }
7370 }
7371 else
7372 {
7373 /* Update the state */
7374 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7375
7376 /* Return error status */
7377 status = HAL_ERROR;
7378 }
7379
7380 /* Release Lock */
7381 __HAL_UNLOCK(hhrtim);
7382
7383 return status;
7384 }
7385
7386 /**
7387 * @brief HRTIM Timer x callback function registration
7388 * @param hhrtim pointer to HAL HRTIM handle
7389 * @param CallbackID ID of the HRTIM Timer x callback function to register
7390 * This parameter can be one of the following values:
7391 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7392 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7393 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7394 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7395 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7396 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7397 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7398 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7399 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7400 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7401 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7402 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7403 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7404 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7405 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7406 * @param pCallback Callback function pointer
7407 * @retval HAL status
7408 */
HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_TIMxCallbackTypeDef pCallback)7409 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7410 HAL_HRTIM_CallbackIDTypeDef CallbackID,
7411 pHRTIM_TIMxCallbackTypeDef pCallback)
7412 {
7413 HAL_StatusTypeDef status = HAL_OK;
7414
7415 if (pCallback == NULL)
7416 {
7417 /* Update the state */
7418 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7419
7420 return HAL_ERROR;
7421 }
7422
7423 /* Process locked */
7424 __HAL_LOCK(hhrtim);
7425
7426 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7427 {
7428 switch (CallbackID)
7429 {
7430 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7431 hhrtim->RegistersUpdateCallback = pCallback;
7432 break;
7433
7434 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7435 hhrtim->RepetitionEventCallback = pCallback;
7436 break;
7437
7438 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7439 hhrtim->Compare1EventCallback = pCallback;
7440 break;
7441
7442 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7443 hhrtim->Compare2EventCallback = pCallback;
7444 break;
7445
7446 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7447 hhrtim->Compare3EventCallback = pCallback;
7448 break;
7449
7450 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7451 hhrtim->Compare4EventCallback = pCallback;
7452 break;
7453
7454 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7455 hhrtim->Capture1EventCallback = pCallback;
7456 break;
7457
7458 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7459 hhrtim->Capture2EventCallback = pCallback;
7460 break;
7461
7462 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7463 hhrtim->DelayedProtectionCallback = pCallback;
7464 break;
7465
7466 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7467 hhrtim->CounterResetCallback = pCallback;
7468 break;
7469
7470 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7471 hhrtim->Output1SetCallback = pCallback;
7472 break;
7473
7474 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7475 hhrtim->Output1ResetCallback = pCallback;
7476 break;
7477
7478 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7479 hhrtim->Output2SetCallback = pCallback;
7480 break;
7481
7482 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7483 hhrtim->Output2ResetCallback = pCallback;
7484 break;
7485
7486 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7487 hhrtim->BurstDMATransferCallback = pCallback;
7488 break;
7489
7490 default :
7491 /* Update the state */
7492 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7493
7494 /* Return error status */
7495 status = HAL_ERROR;
7496 break;
7497 }
7498 }
7499 else
7500 {
7501 /* Update the state */
7502 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7503
7504 /* Return error status */
7505 status = HAL_ERROR;
7506 }
7507
7508 /* Release Lock */
7509 __HAL_UNLOCK(hhrtim);
7510
7511 return status;
7512 }
7513
7514 /**
7515 * @brief HRTIM Timer x callback function un-registration
7516 * @param hhrtim pointer to HAL HRTIM handle
7517 * @param CallbackID ID of the HRTIM callback Timer x function to unregister
7518 * This parameter can be one of the following values:
7519 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7520 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7521 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7522 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7523 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7524 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7525 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7526 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7527 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7528 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7529 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7530 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7531 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7532 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7533 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7534 * @retval HAL status
7535 */
HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)7536 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7537 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7538 {
7539 HAL_StatusTypeDef status = HAL_OK;
7540
7541 /* Process locked */
7542 __HAL_LOCK(hhrtim);
7543
7544 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7545 {
7546 switch (CallbackID)
7547 {
7548 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7549 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
7550 break;
7551
7552 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7553 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
7554 break;
7555
7556 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7557 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
7558 break;
7559
7560 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7561 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
7562 break;
7563
7564 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7565 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
7566 break;
7567
7568 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7569 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
7570 break;
7571
7572 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7573 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
7574 break;
7575
7576 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7577 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
7578 break;
7579
7580 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7581 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
7582 break;
7583
7584 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7585 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
7586 break;
7587
7588 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7589 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
7590 break;
7591
7592 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7593 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
7594 break;
7595
7596 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7597 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
7598 break;
7599
7600 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7601 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
7602 break;
7603
7604 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7605 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
7606 break;
7607
7608 default :
7609 /* Update the state */
7610 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7611
7612 /* Return error status */
7613 status = HAL_ERROR;
7614 break;
7615 }
7616 }
7617 else
7618 {
7619 /* Update the state */
7620 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7621
7622 /* Return error status */
7623 status = HAL_ERROR;
7624 }
7625
7626 /* Release Lock */
7627 __HAL_UNLOCK(hhrtim);
7628
7629 return status;
7630 }
7631 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
7632 /**
7633 * @}
7634 */
7635
7636 /**
7637 * @}
7638 */
7639
7640 /** @addtogroup HRTIM_Private_Functions
7641 * @{
7642 */
7643
7644 /**
7645 * @brief Configure the master timer time base
7646 * @param hhrtim pointer to HAL HRTIM handle
7647 * @param pTimeBaseCfg pointer to the time base configuration structure
7648 * @retval None
7649 */
HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)7650 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
7651 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7652 {
7653 uint32_t hrtim_mcr;
7654
7655 /* Configure master timer */
7656 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7657
7658 /* Set the prescaler ratio */
7659 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
7660 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7661
7662 /* Set the operating mode */
7663 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
7664 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
7665
7666 /* Update the HRTIM registers */
7667 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7668 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
7669 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
7670 }
7671
7672 /**
7673 * @brief Configure timing unit (Timer A to Timer E) time base
7674 * @param hhrtim pointer to HAL HRTIM handle
7675 * @param TimerIdx Timer index
7676 * @param pTimeBaseCfg pointer to the time base configuration structure
7677 * @retval None
7678 */
HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)7679 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
7680 uint32_t TimerIdx ,
7681 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7682 {
7683 uint32_t hrtim_timcr;
7684
7685 /* Configure master timing unit */
7686 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7687
7688 /* Set the prescaler ratio */
7689 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
7690 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7691
7692 /* Set the operating mode */
7693 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
7694 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
7695
7696 /* Update the HRTIM registers */
7697 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7698 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
7699 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
7700 }
7701
7702 /**
7703 * @brief Configure the master timer in waveform mode
7704 * @param hhrtim pointer to HAL HRTIM handle
7705 * @param pTimerCfg pointer to the timer configuration data structure
7706 * @retval None
7707 */
HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimerCfgTypeDef * pTimerCfg)7708 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7709 const HRTIM_TimerCfgTypeDef * pTimerCfg)
7710 {
7711 uint32_t hrtim_mcr;
7712 uint32_t hrtim_bmcr;
7713
7714 /* Configure master timer */
7715 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7716 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7717
7718 /* Enable/Disable the half mode */
7719 hrtim_mcr &= ~(HRTIM_MCR_HALF);
7720 hrtim_mcr |= pTimerCfg->HalfModeEnable;
7721
7722 /* Enable/Disable the timer start upon synchronization event reception */
7723 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
7724 hrtim_mcr |= pTimerCfg->StartOnSync;
7725
7726 /* Enable/Disable the timer reset upon synchronization event reception */
7727 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
7728 hrtim_mcr |= pTimerCfg->ResetOnSync;
7729
7730 /* Enable/Disable the DAC synchronization event generation */
7731 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
7732 hrtim_mcr |= pTimerCfg->DACSynchro;
7733
7734 /* Enable/Disable preload mechanism for timer registers */
7735 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
7736 hrtim_mcr |= pTimerCfg->PreloadEnable;
7737
7738 /* Master timer registers update handling */
7739 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
7740 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
7741
7742 /* Enable/Disable registers update on repetition */
7743 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
7744 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
7745
7746 /* Set the timer burst mode */
7747 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
7748 hrtim_bmcr |= pTimerCfg->BurstMode;
7749
7750 /* Update the HRTIM registers */
7751 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7752 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7753 }
7754
7755 /**
7756 * @brief Configure timing unit (Timer A to Timer E) in waveform mode
7757 * @param hhrtim pointer to HAL HRTIM handle
7758 * @param TimerIdx Timer index
7759 * @param pTimerCfg pointer to the timer configuration data structure
7760 * @retval None
7761 */
HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)7762 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7763 uint32_t TimerIdx,
7764 const HRTIM_TimerCfgTypeDef * pTimerCfg)
7765 {
7766 uint32_t hrtim_timcr;
7767 uint32_t hrtim_timfltr;
7768 uint32_t hrtim_timoutr;
7769 uint32_t hrtim_timrstr;
7770 uint32_t hrtim_bmcr;
7771
7772 /* UPDGAT bitfield must be reset before programming a new value */
7773 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
7774
7775 /* Configure timing unit (Timer A to Timer E) */
7776 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7777 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
7778 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7779 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7780
7781 /* Enable/Disable the half mode */
7782 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
7783 hrtim_timcr |= pTimerCfg->HalfModeEnable;
7784
7785 /* Enable/Disable the timer start upon synchronization event reception */
7786 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
7787 hrtim_timcr |= pTimerCfg->StartOnSync;
7788
7789 /* Enable/Disable the timer reset upon synchronization event reception */
7790 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
7791 hrtim_timcr |= pTimerCfg->ResetOnSync;
7792
7793 /* Enable/Disable the DAC synchronization event generation */
7794 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
7795 hrtim_timcr |= pTimerCfg->DACSynchro;
7796
7797 /* Enable/Disable preload mechanism for timer registers */
7798 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
7799 hrtim_timcr |= pTimerCfg->PreloadEnable;
7800
7801 /* Timing unit registers update handling */
7802 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
7803 hrtim_timcr |= pTimerCfg->UpdateGating;
7804
7805 /* Enable/Disable registers update on repetition */
7806 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
7807 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
7808 {
7809 hrtim_timcr |= HRTIM_TIMCR_TREPU;
7810 }
7811
7812 /* Set the push-pull mode */
7813 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
7814 hrtim_timcr |= pTimerCfg->PushPull;
7815
7816 /* Enable/Disable registers update on timer counter reset */
7817 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
7818 hrtim_timcr |= pTimerCfg->ResetUpdate;
7819
7820 /* Set the timer update trigger */
7821 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
7822 hrtim_timcr |= pTimerCfg->UpdateTrigger;
7823
7824 /* Enable/Disable the fault channel at timer level */
7825 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
7826 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
7827
7828 /* Lock/Unlock fault sources at timer level */
7829 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
7830 hrtim_timfltr |= pTimerCfg->FaultLock;
7831
7832 /* The deadtime cannot be used simultaneously with the push-pull mode */
7833 if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
7834 {
7835 /* Enable/Disable dead time insertion at timer level */
7836 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
7837 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
7838 }
7839
7840 /* Enable/Disable delayed protection at timer level
7841 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
7842 Balanced Idle is only available in push-pull mode
7843 */
7844 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
7845 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
7846 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
7847 {
7848 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
7849 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
7850 }
7851
7852 /* Set the timer counter reset trigger */
7853 hrtim_timrstr = pTimerCfg->ResetTrigger;
7854
7855 /* Set the timer burst mode */
7856 switch (TimerIdx)
7857 {
7858 case HRTIM_TIMERINDEX_TIMER_A:
7859 {
7860 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
7861 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
7862 break;
7863 }
7864
7865 case HRTIM_TIMERINDEX_TIMER_B:
7866 {
7867 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
7868 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
7869 break;
7870 }
7871
7872 case HRTIM_TIMERINDEX_TIMER_C:
7873 {
7874 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
7875 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
7876 break;
7877 }
7878
7879 case HRTIM_TIMERINDEX_TIMER_D:
7880 {
7881 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
7882 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
7883 break;
7884 }
7885
7886 case HRTIM_TIMERINDEX_TIMER_E:
7887 {
7888 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
7889 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
7890 break;
7891 }
7892
7893 default:
7894 break;
7895 }
7896
7897 /* Update the HRTIM registers */
7898 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7899 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
7900 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
7901 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
7902 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7903 }
7904
7905 /**
7906 * @brief Configure a capture unit
7907 * @param hhrtim pointer to HAL HRTIM handle
7908 * @param TimerIdx Timer index
7909 * @param CaptureUnit Capture unit identifier
7910 * @param Event Event reference
7911 * @retval None
7912 */
HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,uint32_t Event)7913 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
7914 uint32_t TimerIdx,
7915 uint32_t CaptureUnit,
7916 uint32_t Event)
7917 {
7918 uint32_t CaptureTrigger = 0xFFFFFFFFU;
7919
7920 switch (Event)
7921 {
7922 case HRTIM_EVENT_1:
7923 {
7924 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
7925 break;
7926 }
7927
7928 case HRTIM_EVENT_2:
7929 {
7930 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
7931 break;
7932 }
7933
7934 case HRTIM_EVENT_3:
7935 {
7936 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
7937 break;
7938 }
7939
7940 case HRTIM_EVENT_4:
7941 {
7942 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
7943 break;
7944 }
7945
7946 case HRTIM_EVENT_5:
7947 {
7948 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
7949 break;
7950 }
7951
7952 case HRTIM_EVENT_6:
7953 {
7954 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
7955 break;
7956 }
7957
7958 case HRTIM_EVENT_7:
7959 {
7960 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
7961 break;
7962 }
7963
7964 case HRTIM_EVENT_8:
7965 {
7966 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
7967 break;
7968 }
7969
7970 case HRTIM_EVENT_9:
7971 {
7972 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
7973 break;
7974 }
7975
7976 case HRTIM_EVENT_10:
7977 {
7978 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
7979 break;
7980 }
7981
7982 default:
7983 break;
7984 }
7985
7986 switch (CaptureUnit)
7987 {
7988 case HRTIM_CAPTUREUNIT_1:
7989 {
7990 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
7991 break;
7992 }
7993
7994 case HRTIM_CAPTUREUNIT_2:
7995 {
7996 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
7997 break;
7998 }
7999
8000 default:
8001 break;
8002 }
8003 }
8004
8005 /**
8006 * @brief Configure the output of a timing unit
8007 * @param hhrtim pointer to HAL HRTIM handle
8008 * @param TimerIdx Timer index
8009 * @param Output timing unit output identifier
8010 * @param pOutputCfg pointer to the output configuration data structure
8011 * @retval None
8012 */
HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)8013 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
8014 uint32_t TimerIdx,
8015 uint32_t Output,
8016 const HRTIM_OutputCfgTypeDef * pOutputCfg)
8017 {
8018 uint32_t hrtim_outr;
8019 uint32_t hrtim_dtr;
8020
8021 uint32_t shift = 0U;
8022
8023 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
8024 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
8025
8026 switch (Output)
8027 {
8028 case HRTIM_OUTPUT_TA1:
8029 case HRTIM_OUTPUT_TB1:
8030 case HRTIM_OUTPUT_TC1:
8031 case HRTIM_OUTPUT_TD1:
8032 case HRTIM_OUTPUT_TE1:
8033 {
8034 /* Set the output set/reset crossbar */
8035 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
8036 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
8037 break;
8038 }
8039
8040 case HRTIM_OUTPUT_TA2:
8041 case HRTIM_OUTPUT_TB2:
8042 case HRTIM_OUTPUT_TC2:
8043 case HRTIM_OUTPUT_TD2:
8044 case HRTIM_OUTPUT_TE2:
8045 {
8046 /* Set the output set/reset crossbar */
8047 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
8048 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
8049 shift = 16U;
8050 break;
8051 }
8052
8053 default:
8054 break;
8055 }
8056
8057 /* Clear output config */
8058 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
8059 HRTIM_OUTR_IDLM1 |
8060 HRTIM_OUTR_IDLES1|
8061 HRTIM_OUTR_FAULT1|
8062 HRTIM_OUTR_CHP1 |
8063 HRTIM_OUTR_DIDL1) << shift);
8064
8065 /* Set the polarity */
8066 hrtim_outr |= (pOutputCfg->Polarity << shift);
8067
8068 /* Set the IDLE mode */
8069 hrtim_outr |= (pOutputCfg->IdleMode << shift);
8070
8071 /* Set the IDLE state */
8072 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
8073
8074 /* Set the FAULT state */
8075 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
8076
8077 /* Set the chopper mode */
8078 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
8079
8080 /* Set the burst mode entry mode : deadtime insertion when entering the idle
8081 state during a burst mode operation is allowed only under the following
8082 conditions:
8083 - the outputs is active during the burst mode (IDLES=1U)
8084 - positive deadtimes (SDTR/SDTF set to 0U)
8085 */
8086 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
8087 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
8088 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
8089 {
8090 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
8091 }
8092
8093 /* Update HRTIM register */
8094 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
8095 }
8096
8097 /**
8098 * @brief Configure an external event channel
8099 * @param hhrtim pointer to HAL HRTIM handle
8100 * @param Event Event channel identifier
8101 * @param pEventCfg pointer to the event channel configuration data structure
8102 * @retval None
8103 */
HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)8104 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
8105 uint32_t Event,
8106 const HRTIM_EventCfgTypeDef *pEventCfg)
8107 {
8108 uint32_t hrtim_eecr1;
8109 uint32_t hrtim_eecr2;
8110 uint32_t hrtim_eecr3;
8111
8112 /* Configure external event channel */
8113 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
8114 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
8115 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
8116
8117 switch (Event)
8118 {
8119 case HRTIM_EVENT_NONE:
8120 {
8121 /* Update the HRTIM registers */
8122 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
8123 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
8124 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
8125 break;
8126 }
8127
8128 case HRTIM_EVENT_1:
8129 {
8130 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
8131 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
8132 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
8133 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
8134 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
8135 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8136 /* Update the HRTIM registers (EE1FAST bit) */
8137 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
8138 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8139 break;
8140 }
8141
8142 case HRTIM_EVENT_2:
8143 {
8144 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
8145 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
8146 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
8147 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
8148 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
8149 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8150 /* Update the HRTIM registers (EE2FAST bit) */
8151 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
8152 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8153 break;
8154 }
8155
8156 case HRTIM_EVENT_3:
8157 {
8158 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
8159 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
8160 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
8161 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
8162 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
8163 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8164 /* Update the HRTIM registers (EE3FAST bit) */
8165 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
8166 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8167 break;
8168 }
8169
8170 case HRTIM_EVENT_4:
8171 {
8172 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
8173 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
8174 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
8175 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
8176 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
8177 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8178 /* Update the HRTIM registers (EE4FAST bit) */
8179 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
8180 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8181 break;
8182 }
8183
8184 case HRTIM_EVENT_5:
8185 {
8186 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
8187 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
8188 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
8189 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
8190 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
8191 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8192 /* Update the HRTIM registers (EE5FAST bit) */
8193 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
8194 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8195 break;
8196 }
8197
8198 case HRTIM_EVENT_6:
8199 {
8200 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
8201 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
8202 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
8203 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
8204 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
8205 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
8206 /* Update the HRTIM registers */
8207 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8208 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8209 break;
8210 }
8211
8212 case HRTIM_EVENT_7:
8213 {
8214 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
8215 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
8216 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
8217 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
8218 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
8219 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
8220 /* Update the HRTIM registers */
8221 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8222 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8223 break;
8224 }
8225
8226 case HRTIM_EVENT_8:
8227 {
8228 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
8229 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
8230 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
8231 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
8232 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
8233 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
8234 /* Update the HRTIM registers */
8235 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8236 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8237 break;
8238 }
8239
8240 case HRTIM_EVENT_9:
8241 {
8242 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
8243 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
8244 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
8245 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
8246 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
8247 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
8248 /* Update the HRTIM registers */
8249 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8250 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8251 break;
8252 }
8253
8254 case HRTIM_EVENT_10:
8255 {
8256 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
8257 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
8258 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
8259 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
8260 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
8261 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
8262 /* Update the HRTIM registers */
8263 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8264 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8265 break;
8266 }
8267
8268 default:
8269 break;
8270 }
8271 }
8272
8273 /**
8274 * @brief Configure the timer counter reset
8275 * @param hhrtim pointer to HAL HRTIM handle
8276 * @param TimerIdx Timer index
8277 * @param Event Event channel identifier
8278 * @retval None
8279 */
HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event)8280 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
8281 uint32_t TimerIdx,
8282 uint32_t Event)
8283 {
8284 switch (Event)
8285 {
8286 case HRTIM_EVENT_1:
8287 {
8288 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
8289 break;
8290 }
8291
8292 case HRTIM_EVENT_2:
8293 {
8294 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
8295 break;
8296 }
8297
8298 case HRTIM_EVENT_3:
8299 {
8300 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
8301 break;
8302 }
8303
8304 case HRTIM_EVENT_4:
8305 {
8306 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
8307 break;
8308 }
8309
8310 case HRTIM_EVENT_5:
8311 {
8312 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
8313 break;
8314 }
8315
8316 case HRTIM_EVENT_6:
8317 {
8318 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
8319 break;
8320 }
8321
8322 case HRTIM_EVENT_7:
8323 {
8324 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
8325 break;
8326 }
8327
8328 case HRTIM_EVENT_8:
8329 {
8330 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
8331 break;
8332 }
8333
8334 case HRTIM_EVENT_9:
8335 {
8336 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
8337 break;
8338 }
8339
8340 case HRTIM_EVENT_10:
8341 {
8342 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
8343 break;
8344 }
8345
8346 default:
8347 break;
8348 }
8349 }
8350
8351 /**
8352 * @brief Return the interrupt to enable or disable according to the
8353 * OC mode.
8354 * @param hhrtim pointer to HAL HRTIM handle
8355 * @param TimerIdx Timer index
8356 * @param OCChannel Timer output
8357 * This parameter can be one of the following values:
8358 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8359 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8360 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8361 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8362 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8363 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8364 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8365 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8366 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8367 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8368 * @retval Interrupt to enable or disable
8369 */
HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)8370 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
8371 uint32_t TimerIdx,
8372 uint32_t OCChannel)
8373 {
8374 uint32_t hrtim_set;
8375 uint32_t hrtim_reset;
8376 uint32_t interrupt = 0U;
8377
8378 switch (OCChannel)
8379 {
8380 case HRTIM_OUTPUT_TA1:
8381 case HRTIM_OUTPUT_TB1:
8382 case HRTIM_OUTPUT_TC1:
8383 case HRTIM_OUTPUT_TD1:
8384 case HRTIM_OUTPUT_TE1:
8385 {
8386 /* Retreives actual OC mode and set interrupt accordingly */
8387 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8388 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8389
8390 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8391 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8392 {
8393 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8394 interrupt = HRTIM_TIM_IT_CMP1;
8395 }
8396 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8397 (hrtim_reset == 0U))
8398 {
8399 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8400 interrupt = HRTIM_TIM_IT_SET1;
8401 }
8402 else if ((hrtim_set == 0U) &&
8403 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8404 {
8405 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8406 interrupt = HRTIM_TIM_IT_RST1;
8407 }
8408 else
8409 {
8410 /* nothing to do */
8411 }
8412 break;
8413 }
8414
8415 case HRTIM_OUTPUT_TA2:
8416 case HRTIM_OUTPUT_TB2:
8417 case HRTIM_OUTPUT_TC2:
8418 case HRTIM_OUTPUT_TD2:
8419 case HRTIM_OUTPUT_TE2:
8420 {
8421 /* Retreives actual OC mode and set interrupt accordingly */
8422 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8423 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8424
8425 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8426 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8427 {
8428 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8429 interrupt = HRTIM_TIM_IT_CMP2;
8430 }
8431 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8432 (hrtim_reset == 0U))
8433 {
8434 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8435 interrupt = HRTIM_TIM_IT_SET2;
8436 }
8437 else if ((hrtim_set == 0U) &&
8438 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8439 {
8440 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8441 interrupt = HRTIM_TIM_IT_RST2;
8442 }
8443 else
8444 {
8445 /* nothing to do */
8446 }
8447 break;
8448 }
8449
8450 default:
8451 break;
8452 }
8453
8454 return interrupt;
8455 }
8456
8457 /**
8458 * @brief Return the DMA request to enable or disable according to the
8459 * OC mode.
8460 * @param hhrtim pointer to HAL HRTIM handle
8461 * @param TimerIdx Timer index
8462 * @param OCChannel Timer output
8463 * This parameter can be one of the following values:
8464 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8465 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8466 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8467 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8468 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8469 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8470 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8471 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8472 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8473 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8474 * @retval DMA request to enable or disable
8475 */
HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)8476 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
8477 uint32_t TimerIdx,
8478 uint32_t OCChannel)
8479 {
8480 uint32_t hrtim_set;
8481 uint32_t hrtim_reset;
8482 uint32_t dma_request = 0U;
8483
8484 switch (OCChannel)
8485 {
8486 case HRTIM_OUTPUT_TA1:
8487 case HRTIM_OUTPUT_TB1:
8488 case HRTIM_OUTPUT_TC1:
8489 case HRTIM_OUTPUT_TD1:
8490 case HRTIM_OUTPUT_TE1:
8491 {
8492 /* Retreives actual OC mode and set dma_request accordingly */
8493 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8494 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8495
8496 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8497 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8498 {
8499 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8500 dma_request = HRTIM_TIM_DMA_CMP1;
8501 }
8502 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8503 (hrtim_reset == 0U))
8504 {
8505 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8506 dma_request = HRTIM_TIM_DMA_SET1;
8507 }
8508 else if ((hrtim_set == 0U) &&
8509 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8510 {
8511 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8512 dma_request = HRTIM_TIM_DMA_RST1;
8513 }
8514 else
8515 {
8516 /* nothing to do */
8517 }
8518 break;
8519 }
8520
8521 case HRTIM_OUTPUT_TA2:
8522 case HRTIM_OUTPUT_TB2:
8523 case HRTIM_OUTPUT_TC2:
8524 case HRTIM_OUTPUT_TD2:
8525 case HRTIM_OUTPUT_TE2:
8526 {
8527 /* Retreives actual OC mode and set dma_request accordingly */
8528 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8529 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8530
8531 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8532 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8533 {
8534 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8535 dma_request = HRTIM_TIM_DMA_CMP2;
8536 }
8537 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8538 (hrtim_reset == 0U))
8539 {
8540 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8541 dma_request = HRTIM_TIM_DMA_SET2;
8542 }
8543 else if ((hrtim_set == 0U) &&
8544 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8545 {
8546 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8547 dma_request = HRTIM_TIM_DMA_RST2;
8548 }
8549 else
8550 {
8551 /* nothing to do */
8552 }
8553 break;
8554 }
8555
8556 default:
8557 break;
8558 }
8559
8560 return dma_request;
8561 }
8562
HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8563 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
8564 uint32_t TimerIdx)
8565 {
8566 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
8567
8568 switch (TimerIdx)
8569 {
8570 case HRTIM_TIMERINDEX_MASTER:
8571 {
8572 hdma = hhrtim->hdmaMaster;
8573 break;
8574 }
8575
8576 case HRTIM_TIMERINDEX_TIMER_A:
8577 {
8578 hdma = hhrtim->hdmaTimerA;
8579 break;
8580 }
8581
8582 case HRTIM_TIMERINDEX_TIMER_B:
8583 {
8584 hdma = hhrtim->hdmaTimerB;
8585 break;
8586 }
8587
8588 case HRTIM_TIMERINDEX_TIMER_C:
8589 {
8590 hdma = hhrtim->hdmaTimerC;
8591 break;
8592 }
8593
8594 case HRTIM_TIMERINDEX_TIMER_D:
8595 {
8596 hdma = hhrtim->hdmaTimerD;
8597 break;
8598 }
8599
8600 case HRTIM_TIMERINDEX_TIMER_E:
8601 {
8602 hdma = hhrtim->hdmaTimerE;
8603 break;
8604 }
8605
8606 default:
8607 break;
8608 }
8609
8610 return hdma;
8611 }
8612
GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,const DMA_HandleTypeDef * hdma)8613 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
8614 const DMA_HandleTypeDef * hdma)
8615 {
8616 uint32_t timed_idx = 0xFFFFFFFFU;
8617
8618 if (hdma == hhrtim->hdmaMaster)
8619 {
8620 timed_idx = HRTIM_TIMERINDEX_MASTER;
8621 }
8622 else if (hdma == hhrtim->hdmaTimerA)
8623 {
8624 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
8625 }
8626 else if (hdma == hhrtim->hdmaTimerB)
8627 {
8628 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
8629 }
8630 else if (hdma == hhrtim->hdmaTimerC)
8631 {
8632 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
8633 }
8634 else if (hdma == hhrtim->hdmaTimerD)
8635 {
8636 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
8637 }
8638 else if (hdma == hhrtim->hdmaTimerE)
8639 {
8640 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
8641 }
8642 else
8643 {
8644 /* nothing to do */
8645 }
8646 return timed_idx;
8647 }
8648
8649 /**
8650 * @brief Force an immediate transfer from the preload to the active
8651 * registers.
8652 * @param hhrtim pointer to HAL HRTIM handle
8653 * @param TimerIdx Timer index
8654 * @retval None
8655 */
HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8656 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
8657 uint32_t TimerIdx)
8658 {
8659 switch (TimerIdx)
8660 {
8661 case HRTIM_TIMERINDEX_MASTER:
8662 {
8663 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
8664 break;
8665 }
8666
8667 case HRTIM_TIMERINDEX_TIMER_A:
8668 {
8669 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
8670 break;
8671 }
8672
8673 case HRTIM_TIMERINDEX_TIMER_B:
8674 {
8675 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
8676 break;
8677 }
8678
8679 case HRTIM_TIMERINDEX_TIMER_C:
8680 {
8681 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
8682 break;
8683 }
8684
8685 case HRTIM_TIMERINDEX_TIMER_D:
8686 {
8687 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
8688 break;
8689 }
8690
8691 case HRTIM_TIMERINDEX_TIMER_E:
8692 {
8693 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
8694 break;
8695 }
8696
8697 default:
8698 break;
8699 }
8700 }
8701
8702
8703 /**
8704 * @brief HRTIM interrupts service routine
8705 * @param hhrtim pointer to HAL HRTIM handle
8706 * @retval None
8707 */
HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)8708 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
8709 {
8710 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8711 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8712
8713 /* Fault 1 event */
8714 if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
8715 {
8716 if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
8717 {
8718 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
8719
8720 /* Invoke Fault 1 event callback */
8721 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8722 hhrtim->Fault1Callback(hhrtim);
8723 #else
8724 HAL_HRTIM_Fault1Callback(hhrtim);
8725 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8726 }
8727 }
8728
8729 /* Fault 2 event */
8730 if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
8731 {
8732 if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
8733 {
8734 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
8735
8736 /* Invoke Fault 2 event callback */
8737 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8738 hhrtim->Fault2Callback(hhrtim);
8739 #else
8740 HAL_HRTIM_Fault2Callback(hhrtim);
8741 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8742 }
8743 }
8744
8745 /* Fault 3 event */
8746 if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
8747 {
8748 if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
8749 {
8750 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
8751
8752 /* Invoke Fault 3 event callback */
8753 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8754 hhrtim->Fault3Callback(hhrtim);
8755 #else
8756 HAL_HRTIM_Fault3Callback(hhrtim);
8757 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8758 }
8759 }
8760
8761 /* Fault 4 event */
8762 if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
8763 {
8764 if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
8765 {
8766 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
8767
8768 /* Invoke Fault 4 event callback */
8769 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8770 hhrtim->Fault4Callback(hhrtim);
8771 #else
8772 HAL_HRTIM_Fault4Callback(hhrtim);
8773 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8774 }
8775 }
8776
8777 /* Fault 5 event */
8778 if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
8779 {
8780 if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
8781 {
8782 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
8783
8784 /* Invoke Fault 5 event callback */
8785 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8786 hhrtim->Fault5Callback(hhrtim);
8787 #else
8788 HAL_HRTIM_Fault5Callback(hhrtim);
8789 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8790 }
8791 }
8792
8793 /* System fault event */
8794 if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
8795 {
8796 if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
8797 {
8798 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
8799
8800 /* Invoke System fault event callback */
8801 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8802 hhrtim->SystemFaultCallback(hhrtim);
8803 #else
8804 HAL_HRTIM_SystemFaultCallback(hhrtim);
8805 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8806 }
8807 }
8808 }
8809
8810 /**
8811 * @brief Master timer interrupts service routine
8812 * @param hhrtim pointer to HAL HRTIM handle
8813 * @retval None
8814 */
HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)8815 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
8816 {
8817 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8818 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8819 uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
8820 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
8821
8822 /* DLL calibration ready event */
8823 if((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
8824 {
8825 if((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET)
8826 {
8827 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
8828
8829 /* Set HRTIM State */
8830 hhrtim->State = HAL_HRTIM_STATE_READY;
8831
8832 /* Process unlocked */
8833 __HAL_UNLOCK(hhrtim);
8834
8835 /* Invoke System fault event callback */
8836 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8837 hhrtim->DLLCalibrationReadyCallback(hhrtim);
8838 #else
8839 HAL_HRTIM_DLLCalibrationReadyCallback(hhrtim);
8840 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8841 }
8842 }
8843
8844 /* Burst mode period event */
8845 if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
8846 {
8847 if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
8848 {
8849 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
8850
8851 /* Invoke Burst mode period event callback */
8852 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8853 hhrtim->BurstModePeriodCallback(hhrtim);
8854 #else
8855 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
8856 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8857 }
8858 }
8859
8860 /* Master timer compare 1 event */
8861 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
8862 {
8863 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
8864 {
8865 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
8866
8867 /* Invoke compare 1 event callback */
8868 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8869 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8870 #else
8871 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8872 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8873 }
8874 }
8875
8876 /* Master timer compare 2 event */
8877 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
8878 {
8879 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
8880 {
8881 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
8882
8883 /* Invoke compare 2 event callback */
8884 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8885 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8886 #else
8887 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8888 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8889 }
8890 }
8891
8892 /* Master timer compare 3 event */
8893 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
8894 {
8895 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
8896 {
8897 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
8898
8899 /* Invoke compare 3 event callback */
8900 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8901 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8902 #else
8903 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8904 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8905 }
8906 }
8907
8908 /* Master timer compare 4 event */
8909 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
8910 {
8911 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
8912 {
8913 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
8914
8915 /* Invoke compare 4 event callback */
8916 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8917 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8918 #else
8919 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8920 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8921 }
8922 }
8923
8924 /* Master timer repetition event */
8925 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
8926 {
8927 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
8928 {
8929 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
8930
8931 /* Invoke repetition event callback */
8932 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8933 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8934 #else
8935 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8936 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8937 }
8938 }
8939
8940 /* Synchronization input event */
8941 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
8942 {
8943 if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
8944 {
8945 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
8946
8947 /* Invoke synchronization event callback */
8948 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8949 hhrtim->SynchronizationEventCallback(hhrtim);
8950 #else
8951 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
8952 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8953 }
8954 }
8955
8956 /* Master timer registers update event */
8957 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
8958 {
8959 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
8960 {
8961 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
8962
8963 /* Invoke registers update event callback */
8964 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8965 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8966 #else
8967 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8968 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8969 }
8970 }
8971 }
8972
8973 /**
8974 * @brief Timer interrupts service routine
8975 * @param hhrtim pointer to HAL HRTIM handle
8976 * @param TimerIdx Timer index
8977 * This parameter can be one of the following values:
8978 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8979 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8980 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8981 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8982 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8983 * @retval None
8984 */
HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8985 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
8986 uint32_t TimerIdx)
8987 {
8988 uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
8989 uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
8990
8991 /* Timer compare 1 event */
8992 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
8993 {
8994 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
8995 {
8996 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
8997
8998 /* Invoke compare 1 event callback */
8999 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9000 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
9001 #else
9002 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
9003 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9004 }
9005 }
9006
9007 /* Timer compare 2 event */
9008 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
9009 {
9010 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
9011 {
9012 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
9013
9014 /* Invoke compare 2 event callback */
9015 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9016 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
9017 #else
9018 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
9019 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9020 }
9021 }
9022
9023 /* Timer compare 3 event */
9024 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
9025 {
9026 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
9027 {
9028 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
9029
9030 /* Invoke compare 3 event callback */
9031 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9032 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
9033 #else
9034 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
9035 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9036 }
9037 }
9038
9039 /* Timer compare 4 event */
9040 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
9041 {
9042 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
9043 {
9044 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
9045
9046 /* Invoke compare 4 event callback */
9047 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9048 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
9049 #else
9050 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
9051 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9052 }
9053 }
9054
9055 /* Timer repetition event */
9056 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
9057 {
9058 if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
9059 {
9060 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
9061
9062 /* Invoke repetition event callback */
9063 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9064 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
9065 #else
9066 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
9067 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9068 }
9069 }
9070
9071 /* Timer registers update event */
9072 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
9073 {
9074 if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
9075 {
9076 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
9077
9078 /* Invoke registers update event callback */
9079 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9080 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
9081 #else
9082 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
9083 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9084 }
9085 }
9086
9087 /* Timer capture 1 event */
9088 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
9089 {
9090 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
9091 {
9092 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
9093
9094 /* Invoke capture 1 event callback */
9095 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9096 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
9097 #else
9098 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
9099 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9100 }
9101 }
9102
9103 /* Timer capture 2 event */
9104 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
9105 {
9106 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
9107 {
9108 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
9109
9110 /* Invoke capture 2 event callback */
9111 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9112 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
9113 #else
9114 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
9115 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9116 }
9117 }
9118
9119 /* Timer output 1 set event */
9120 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
9121 {
9122 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
9123 {
9124 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
9125
9126 /* Invoke output 1 set event callback */
9127 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9128 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
9129 #else
9130 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
9131 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9132 }
9133 }
9134
9135 /* Timer output 1 reset event */
9136 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
9137 {
9138 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
9139 {
9140 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
9141
9142 /* Invoke output 1 reset event callback */
9143 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9144 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
9145 #else
9146 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
9147 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9148 }
9149 }
9150
9151 /* Timer output 2 set event */
9152 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
9153 {
9154 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
9155 {
9156 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
9157
9158 /* Invoke output 2 set event callback */
9159 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9160 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
9161 #else
9162 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
9163 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9164 }
9165 }
9166
9167 /* Timer output 2 reset event */
9168 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
9169 {
9170 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
9171 {
9172 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
9173
9174 /* Invoke output 2 reset event callback */
9175 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9176 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
9177 #else
9178 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
9179 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9180 }
9181 }
9182
9183 /* Timer reset event */
9184 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
9185 {
9186 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
9187 {
9188 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
9189
9190 /* Invoke timer reset callback */
9191 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9192 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
9193 #else
9194 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
9195 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9196 }
9197 }
9198
9199 /* Delayed protection event */
9200 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
9201 {
9202 if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
9203 {
9204 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
9205
9206 /* Invoke delayed protection callback */
9207 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9208 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
9209 #else
9210 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
9211 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9212 }
9213 }
9214 }
9215
9216 /**
9217 * @brief DMA callback invoked upon master timer related DMA request completion
9218 * @param hdma pointer to DMA handle.
9219 * @retval None
9220 */
HRTIM_DMAMasterCplt(DMA_HandleTypeDef * hdma)9221 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
9222 {
9223 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9224
9225 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
9226 {
9227 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9228 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9229 #else
9230 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9231 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9232 }
9233 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
9234 {
9235 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9236 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9237 #else
9238 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9239 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9240 }
9241 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
9242 {
9243 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9244 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9245 #else
9246 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9247 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9248 }
9249 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
9250 {
9251 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9252 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9253 #else
9254 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9255 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9256 }
9257 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
9258 {
9259 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9260 hrtim->SynchronizationEventCallback(hrtim);
9261 #else
9262 HAL_HRTIM_SynchronizationEventCallback(hrtim);
9263 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9264 }
9265 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
9266 {
9267 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9268 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9269 #else
9270 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9271 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9272 }
9273 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
9274 {
9275 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9276 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9277 #else
9278 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9279 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9280 }
9281 else
9282 {
9283 /* nothing to do */
9284 }
9285 }
9286
9287 /**
9288 * @brief DMA callback invoked upon timer A..E related DMA request completion
9289 * @param hdma pointer to DMA handle.
9290 * @retval None
9291 */
HRTIM_DMATimerxCplt(DMA_HandleTypeDef * hdma)9292 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
9293 {
9294 uint8_t timer_idx;
9295
9296 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9297
9298 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
9299
9300 if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
9301
9302 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
9303 {
9304 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9305 hrtim->Compare1EventCallback(hrtim, timer_idx);
9306 #else
9307 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
9308 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9309 }
9310 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
9311 {
9312 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9313 hrtim->Compare2EventCallback(hrtim, timer_idx);
9314 #else
9315 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
9316 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9317 }
9318 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
9319 {
9320 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9321 hrtim->Compare3EventCallback(hrtim, timer_idx);
9322 #else
9323 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
9324 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9325 }
9326 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
9327 {
9328 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9329 hrtim->Compare4EventCallback(hrtim, timer_idx);
9330 #else
9331 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
9332 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9333 }
9334 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
9335 {
9336 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9337 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
9338 #else
9339 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
9340 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9341 }
9342 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
9343 {
9344 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9345 hrtim->Capture1EventCallback(hrtim, timer_idx);
9346 #else
9347 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
9348 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9349 }
9350 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
9351 {
9352 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9353 hrtim->Capture2EventCallback(hrtim, timer_idx);
9354 #else
9355 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
9356 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9357 }
9358 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
9359 {
9360 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9361 hrtim->Output1SetCallback(hrtim, timer_idx);
9362 #else
9363 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
9364 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9365 }
9366 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
9367 {
9368 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9369 hrtim->Output1ResetCallback(hrtim, timer_idx);
9370 #else
9371 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
9372 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9373 }
9374 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
9375 {
9376 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9377 hrtim->Output2SetCallback(hrtim, timer_idx);
9378 #else
9379 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
9380 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9381 }
9382 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
9383 {
9384 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9385 hrtim->Output2ResetCallback(hrtim, timer_idx);
9386 #else
9387 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
9388 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9389 }
9390 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
9391 {
9392 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9393 hrtim->CounterResetCallback(hrtim, timer_idx);
9394 #else
9395 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
9396 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9397 }
9398 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
9399 {
9400 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9401 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
9402 #else
9403 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
9404 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9405 }
9406 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
9407 {
9408 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9409 hrtim->RepetitionEventCallback(hrtim, timer_idx);
9410 #else
9411 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
9412 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9413 }
9414 else
9415 {
9416 /* nothing to do */
9417 }
9418 }
9419
9420 /**
9421 * @brief DMA error callback
9422 * @param hdma pointer to DMA handle.
9423 * @retval None
9424 */
HRTIM_DMAError(DMA_HandleTypeDef * hdma)9425 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
9426 {
9427 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9428
9429 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9430 hrtim->ErrorCallback(hrtim);
9431 #else
9432 HAL_HRTIM_ErrorCallback(hrtim);
9433 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9434 }
9435
9436 /**
9437 * @brief DMA callback invoked upon burst DMA transfer completion
9438 * @param hdma pointer to DMA handle.
9439 * @retval None
9440 */
HRTIM_BurstDMACplt(DMA_HandleTypeDef * hdma)9441 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
9442 {
9443 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9444
9445 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9446 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9447 #else
9448 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9449 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9450 }
9451
9452 /**
9453 * @}
9454 */
9455
9456 /**
9457 * @}
9458 */
9459
9460 #endif /* HRTIM1 */
9461
9462 #endif /* HAL_HRTIM_MODULE_ENABLED */
9463
9464 /**
9465 * @}
9466 */
9467
