1 /**
2   ******************************************************************************
3   * @file    stm32f3xx_hal_cortex.h
4   * @author  MCD Application Team
5   * @brief   Header file of CORTEX HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2016 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file in
13   * the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F3xx_HAL_CORTEX_H
21 #define __STM32F3xx_HAL_CORTEX_H
22 
23 #ifdef __cplusplus
24  extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f3xx_hal_def.h"
29 
30 /** @addtogroup STM32F3xx_HAL_Driver
31   * @{
32   */
33 
34 /** @addtogroup CORTEX
35   * @{
36   */
37 /* Exported types ------------------------------------------------------------*/
38 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
39   * @{
40   */
41 
42 #if (__MPU_PRESENT == 1U)
43 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
44   * @brief  MPU Region initialization structure
45   * @{
46   */
47 typedef struct
48 {
49   uint8_t                Enable;                /*!< Specifies the status of the region.
50                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
51   uint8_t                Number;                /*!< Specifies the number of the region to protect.
52                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
53   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
54   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
55                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
56   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
57                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
58   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
59                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
60   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
61                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
62   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
63                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
64   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
65                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
66   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
67                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
68   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
69                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
70 }MPU_Region_InitTypeDef;
71 /**
72   * @}
73   */
74 #endif /* __MPU_PRESENT */
75 
76 /**
77   * @}
78   */
79 
80 /* Exported constants --------------------------------------------------------*/
81 
82 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
83   * @{
84   */
85 
86 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
87   * @{
88   */
89 #define NVIC_PRIORITYGROUP_0         (0x00000007U) /*!< 0 bits for pre-emption priority
90                                                                  4 bits for subpriority */
91 #define NVIC_PRIORITYGROUP_1         (0x00000006U) /*!< 1 bits for pre-emption priority
92                                                                  3 bits for subpriority */
93 #define NVIC_PRIORITYGROUP_2         (0x00000005U) /*!< 2 bits for pre-emption priority
94                                                                  2 bits for subpriority */
95 #define NVIC_PRIORITYGROUP_3         (0x00000004U) /*!< 3 bits for pre-emption priority
96                                                                  1 bits for subpriority */
97 #define NVIC_PRIORITYGROUP_4         (0x00000003U) /*!< 4 bits for pre-emption priority
98                                                                  0 bits for subpriority */
99 /**
100   * @}
101   */
102 
103 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
104   * @{
105   */
106 #define SYSTICK_CLKSOURCE_HCLK_DIV8    (0x00000000U)
107 #define SYSTICK_CLKSOURCE_HCLK         (0x00000004U)
108 /**
109   * @}
110   */
111 
112 #if (__MPU_PRESENT == 1U)
113 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
114   * @{
115   */
116 #define  MPU_HFNMI_PRIVDEF_NONE      (0x00000000U)
117 #define  MPU_HARDFAULT_NMI           (0x00000002U)
118 #define  MPU_PRIVILEGED_DEFAULT      (0x00000004U)
119 #define  MPU_HFNMI_PRIVDEF           (0x00000006U)
120 /**
121   * @}
122   */
123 
124 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
125   * @{
126   */
127 #define  MPU_REGION_ENABLE     ((uint8_t)0x01U)
128 #define  MPU_REGION_DISABLE    ((uint8_t)0x00U)
129 /**
130   * @}
131   */
132 
133 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
134   * @{
135   */
136 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)
137 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)
138 /**
139   * @}
140   */
141 
142 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
143   * @{
144   */
145 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)
146 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)
147 /**
148   * @}
149   */
150 
151 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
152   * @{
153   */
154 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01U)
155 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00U)
156 /**
157   * @}
158   */
159 
160 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
161   * @{
162   */
163 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01U)
164 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00U)
165 /**
166   * @}
167   */
168 
169 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
170   * @{
171   */
172 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00U)
173 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01U)
174 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02U)
175 /**
176   * @}
177   */
178 
179 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
180   * @{
181   */
182 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
183 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
184 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
185 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
186 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
187 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
188 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
189 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
190 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
191 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
192 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
193 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
194 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
195 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
196 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
197 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
198 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
199 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
200 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
201 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
202 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
203 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
204 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
205 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
206 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
207 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
208 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
209 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
210 /**
211   * @}
212   */
213 
214 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
215   * @{
216   */
217 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)
218 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U)
219 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)
220 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)
221 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U)
222 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)
223 /**
224   * @}
225   */
226 
227 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
228   * @{
229   */
230 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)
231 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01U)
232 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)
233 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)
234 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04U)
235 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)
236 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)
237 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)
238 /**
239   * @}
240   */
241 #endif /* __MPU_PRESENT */
242 
243 /**
244   * @}
245   */
246 
247 /* Exported Macros -----------------------------------------------------------*/
248 
249 
250 /* Exported functions --------------------------------------------------------*/
251 /** @addtogroup CORTEX_Exported_Functions
252   * @{
253   */
254 
255 /** @addtogroup CORTEX_Exported_Functions_Group1
256  * @{
257  */
258 /* Initialization and de-initialization functions *****************************/
259 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
260 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
261 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
262 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
263 void HAL_NVIC_SystemReset(void);
264 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
265 /**
266   * @}
267   */
268 
269 /** @addtogroup CORTEX_Exported_Functions_Group2
270  * @{
271  */
272 /* Peripheral Control functions ***********************************************/
273 #if (__MPU_PRESENT == 1U)
274 void HAL_MPU_EnableRegion(uint32_t RegionNumber);
275 void HAL_MPU_DisableRegion(uint32_t RegionNumber);
276 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
277 #endif /* __MPU_PRESENT */
278 uint32_t HAL_NVIC_GetPriorityGrouping(void);
279 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
280 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
281 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
282 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
283 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
284 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
285 void HAL_SYSTICK_IRQHandler(void);
286 void HAL_SYSTICK_Callback(void);
287 /**
288   * @}
289   */
290 
291 /**
292   * @}
293   */
294 
295 /* Private types -------------------------------------------------------------*/
296 /* Private variables ---------------------------------------------------------*/
297 /* Private constants ---------------------------------------------------------*/
298 /* Private macros ------------------------------------------------------------*/
299 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
300   * @{
301   */
302 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
303                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
304                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
305                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
306                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
307 
308 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
309 
310 #define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
311 
312 #define IS_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
313 
314 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
315   * @{
316   */
317 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
318                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
319 /**
320   * @}
321   */
322 
323 #if (__MPU_PRESENT == 1U)
324 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
325                                      ((STATE) == MPU_REGION_DISABLE))
326 
327 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
328                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
329 
330 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
331                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
332 
333 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
334                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
335 
336 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
337                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
338 
339 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
340                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
341                                 ((TYPE) == MPU_TEX_LEVEL2))
342 
343 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
344                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
345                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
346                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
347                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
348                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
349 
350 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
351                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
352                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
353                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
354                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
355                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
356                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
357                                          ((NUMBER) == MPU_REGION_NUMBER7))
358 
359 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
360                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
361                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
362                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
363                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
364                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
365                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
366                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
367                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
368                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
369                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
370                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
371                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
372                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
373                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
374                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
375                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
376                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
377                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
378                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
379                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
380                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
381                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
382                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
383                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
384                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
385                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
386                                      ((SIZE) == MPU_REGION_SIZE_4GB))
387 
388 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)
389 #endif /* __MPU_PRESENT */
390 
391 /**
392   * @}
393   */
394 
395 /* Private functions ---------------------------------------------------------*/
396 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
397   * @brief    CORTEX private  functions
398   * @{
399   */
400 
401 #if (__MPU_PRESENT == 1U)
402 
403 void HAL_MPU_Disable(void);
404 void HAL_MPU_Enable(uint32_t MPU_Control);
405 
406 #endif /* __MPU_PRESENT */
407 
408 /**
409   * @}
410   */
411 
412 /**
413   * @}
414   */
415 
416 /**
417   * @}
418   */
419 
420 #ifdef __cplusplus
421 }
422 #endif
423 
424 #endif /* __STM32F3xx_HAL_CORTEX_H */
425 
426