1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F2xx_LL_TIM_H
21 #define __STM32F2xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f2xx.h"
29
30 /** @addtogroup STM32F2xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U /* 6: TIMx_CH4 */
54 };
55
56 static const uint8_t SHIFT_TAB_OCxx[] =
57 {
58 0U, /* 0: OC1M, OC1FE, OC1PE */
59 0U, /* 1: - NA */
60 8U, /* 2: OC2M, OC2FE, OC2PE */
61 0U, /* 3: - NA */
62 0U, /* 4: OC3M, OC3FE, OC3PE */
63 0U, /* 5: - NA */
64 8U /* 6: OC4M, OC4FE, OC4PE */
65 };
66
67 static const uint8_t SHIFT_TAB_ICxx[] =
68 {
69 0U, /* 0: CC1S, IC1PSC, IC1F */
70 0U, /* 1: - NA */
71 8U, /* 2: CC2S, IC2PSC, IC2F */
72 0U, /* 3: - NA */
73 0U, /* 4: CC3S, IC3PSC, IC3F */
74 0U, /* 5: - NA */
75 8U /* 6: CC4S, IC4PSC, IC4F */
76 };
77
78 static const uint8_t SHIFT_TAB_CCxP[] =
79 {
80 0U, /* 0: CC1P */
81 2U, /* 1: CC1NP */
82 4U, /* 2: CC2P */
83 6U, /* 3: CC2NP */
84 8U, /* 4: CC3P */
85 10U, /* 5: CC3NP */
86 12U /* 6: CC4P */
87 };
88
89 static const uint8_t SHIFT_TAB_OISx[] =
90 {
91 0U, /* 0: OIS1 */
92 1U, /* 1: OIS1N */
93 2U, /* 2: OIS2 */
94 3U, /* 3: OIS2N */
95 4U, /* 4: OIS3 */
96 5U, /* 5: OIS3N */
97 6U /* 6: OIS4 */
98 };
99 /**
100 * @}
101 */
102
103 /* Private constants ---------------------------------------------------------*/
104 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
105 * @{
106 */
107
108
109 /* Remap mask definitions */
110 #define TIMx_OR_RMP_SHIFT 16U
111 #define TIMx_OR_RMP_MASK 0x0000FFFFU
112 #define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
113 #define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
114 #define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
115
116 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
117 #define DT_DELAY_1 ((uint8_t)0x7F)
118 #define DT_DELAY_2 ((uint8_t)0x3F)
119 #define DT_DELAY_3 ((uint8_t)0x1F)
120 #define DT_DELAY_4 ((uint8_t)0x1F)
121
122 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
123 #define DT_RANGE_1 ((uint8_t)0x00)
124 #define DT_RANGE_2 ((uint8_t)0x80)
125 #define DT_RANGE_3 ((uint8_t)0xC0)
126 #define DT_RANGE_4 ((uint8_t)0xE0)
127
128
129 /**
130 * @}
131 */
132
133 /* Private macros ------------------------------------------------------------*/
134 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
135 * @{
136 */
137 /** @brief Convert channel id into channel index.
138 * @param __CHANNEL__ This parameter can be one of the following values:
139 * @arg @ref LL_TIM_CHANNEL_CH1
140 * @arg @ref LL_TIM_CHANNEL_CH1N
141 * @arg @ref LL_TIM_CHANNEL_CH2
142 * @arg @ref LL_TIM_CHANNEL_CH2N
143 * @arg @ref LL_TIM_CHANNEL_CH3
144 * @arg @ref LL_TIM_CHANNEL_CH3N
145 * @arg @ref LL_TIM_CHANNEL_CH4
146 * @retval none
147 */
148 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
149 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
150 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
151 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
152 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
153 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
154 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
155
156 /** @brief Calculate the deadtime sampling period(in ps).
157 * @param __TIMCLK__ timer input clock frequency (in Hz).
158 * @param __CKD__ This parameter can be one of the following values:
159 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
160 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
161 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
162 * @retval none
163 */
164 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
165 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
166 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
167 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
168 /**
169 * @}
170 */
171
172
173 /* Exported types ------------------------------------------------------------*/
174 #if defined(USE_FULL_LL_DRIVER)
175 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
176 * @{
177 */
178
179 /**
180 * @brief TIM Time Base configuration structure definition.
181 */
182 typedef struct
183 {
184 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
185 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
186
187 This feature can be modified afterwards using unitary function
188 @ref LL_TIM_SetPrescaler().*/
189
190 uint32_t CounterMode; /*!< Specifies the counter mode.
191 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
192
193 This feature can be modified afterwards using unitary function
194 @ref LL_TIM_SetCounterMode().*/
195
196 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
197 Auto-Reload Register at the next update event.
198 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
199 Some timer instances may support 32 bits counters. In that case this parameter must
200 be a number between 0x0000 and 0xFFFFFFFF.
201
202 This feature can be modified afterwards using unitary function
203 @ref LL_TIM_SetAutoReload().*/
204
205 uint32_t ClockDivision; /*!< Specifies the clock division.
206 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
207
208 This feature can be modified afterwards using unitary function
209 @ref LL_TIM_SetClockDivision().*/
210
211 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
212 reaches zero, an update event is generated and counting restarts
213 from the RCR value (N).
214 This means in PWM mode that (N+1) corresponds to:
215 - the number of PWM periods in edge-aligned mode
216 - the number of half PWM period in center-aligned mode
217 GP timers: this parameter must be a number between Min_Data = 0x00 and
218 Max_Data = 0xFF.
219 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
220 Max_Data = 0xFFFF.
221
222 This feature can be modified afterwards using unitary function
223 @ref LL_TIM_SetRepetitionCounter().*/
224 } LL_TIM_InitTypeDef;
225
226 /**
227 * @brief TIM Output Compare configuration structure definition.
228 */
229 typedef struct
230 {
231 uint32_t OCMode; /*!< Specifies the output mode.
232 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
233
234 This feature can be modified afterwards using unitary function
235 @ref LL_TIM_OC_SetMode().*/
236
237 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
238 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
239
240 This feature can be modified afterwards using unitary functions
241 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
242
243 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
244 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
245
246 This feature can be modified afterwards using unitary functions
247 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
248
249 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
250 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
251
252 This feature can be modified afterwards using unitary function
253 LL_TIM_OC_SetCompareCHx (x=1..6).*/
254
255 uint32_t OCPolarity; /*!< Specifies the output polarity.
256 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
257
258 This feature can be modified afterwards using unitary function
259 @ref LL_TIM_OC_SetPolarity().*/
260
261 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
262 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_OC_SetPolarity().*/
266
267
268 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
269 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
270
271 This feature can be modified afterwards using unitary function
272 @ref LL_TIM_OC_SetIdleState().*/
273
274 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
275 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
276
277 This feature can be modified afterwards using unitary function
278 @ref LL_TIM_OC_SetIdleState().*/
279 } LL_TIM_OC_InitTypeDef;
280
281 /**
282 * @brief TIM Input Capture configuration structure definition.
283 */
284
285 typedef struct
286 {
287
288 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
289 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
290
291 This feature can be modified afterwards using unitary function
292 @ref LL_TIM_IC_SetPolarity().*/
293
294 uint32_t ICActiveInput; /*!< Specifies the input.
295 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
296
297 This feature can be modified afterwards using unitary function
298 @ref LL_TIM_IC_SetActiveInput().*/
299
300 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
301 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
302
303 This feature can be modified afterwards using unitary function
304 @ref LL_TIM_IC_SetPrescaler().*/
305
306 uint32_t ICFilter; /*!< Specifies the input capture filter.
307 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
308
309 This feature can be modified afterwards using unitary function
310 @ref LL_TIM_IC_SetFilter().*/
311 } LL_TIM_IC_InitTypeDef;
312
313
314 /**
315 * @brief TIM Encoder interface configuration structure definition.
316 */
317 typedef struct
318 {
319 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
320 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
321
322 This feature can be modified afterwards using unitary function
323 @ref LL_TIM_SetEncoderMode().*/
324
325 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
326 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
327
328 This feature can be modified afterwards using unitary function
329 @ref LL_TIM_IC_SetPolarity().*/
330
331 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
332 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
333
334 This feature can be modified afterwards using unitary function
335 @ref LL_TIM_IC_SetActiveInput().*/
336
337 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
338 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
339
340 This feature can be modified afterwards using unitary function
341 @ref LL_TIM_IC_SetPrescaler().*/
342
343 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
344 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
345
346 This feature can be modified afterwards using unitary function
347 @ref LL_TIM_IC_SetFilter().*/
348
349 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
350 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_IC_SetPolarity().*/
354
355 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
356 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_IC_SetActiveInput().*/
360
361 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
362 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetPrescaler().*/
366
367 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
368 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetFilter().*/
372
373 } LL_TIM_ENCODER_InitTypeDef;
374
375 /**
376 * @brief TIM Hall sensor interface configuration structure definition.
377 */
378 typedef struct
379 {
380
381 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
382 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
383
384 This feature can be modified afterwards using unitary function
385 @ref LL_TIM_IC_SetPolarity().*/
386
387 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
388 Prescaler must be set to get a maximum counter period longer than the
389 time interval between 2 consecutive changes on the Hall inputs.
390 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
391
392 This feature can be modified afterwards using unitary function
393 @ref LL_TIM_IC_SetPrescaler().*/
394
395 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
396 This parameter can be a value of
397 @ref TIM_LL_EC_IC_FILTER.
398
399 This feature can be modified afterwards using unitary function
400 @ref LL_TIM_IC_SetFilter().*/
401
402 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
403 A positive pulse (TRGO event) is generated with a programmable delay every time
404 a change occurs on the Hall inputs.
405 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
406
407 This feature can be modified afterwards using unitary function
408 @ref LL_TIM_OC_SetCompareCH2().*/
409 } LL_TIM_HALLSENSOR_InitTypeDef;
410
411 /**
412 * @brief BDTR (Break and Dead Time) structure definition
413 */
414 typedef struct
415 {
416 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
417 This parameter can be a value of @ref TIM_LL_EC_OSSR
418
419 This feature can be modified afterwards using unitary function
420 @ref LL_TIM_SetOffStates()
421
422 @note This bit-field cannot be modified as long as LOCK level 2 has been
423 programmed. */
424
425 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
426 This parameter can be a value of @ref TIM_LL_EC_OSSI
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_SetOffStates()
430
431 @note This bit-field cannot be modified as long as LOCK level 2 has been
432 programmed. */
433
434 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
435 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
436
437 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
438 register has been written, their content is frozen until the next reset.*/
439
440 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
441 switching-on of the outputs.
442 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
443
444 This feature can be modified afterwards using unitary function
445 @ref LL_TIM_OC_SetDeadTime()
446
447 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
448 programmed. */
449
450 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
451 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
452
453 This feature can be modified afterwards using unitary functions
454 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
455
456 @note This bit-field can not be modified as long as LOCK level 1 has been
457 programmed. */
458
459 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
460 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
461
462 This feature can be modified afterwards using unitary function
463 @ref LL_TIM_ConfigBRK()
464
465 @note This bit-field can not be modified as long as LOCK level 1 has been
466 programmed. */
467
468 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
469 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
470
471 This feature can be modified afterwards using unitary functions
472 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
473
474 @note This bit-field can not be modified as long as LOCK level 1 has been
475 programmed. */
476 } LL_TIM_BDTR_InitTypeDef;
477
478 /**
479 * @}
480 */
481 #endif /* USE_FULL_LL_DRIVER */
482
483 /* Exported constants --------------------------------------------------------*/
484 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
485 * @{
486 */
487
488 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
489 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
490 * @{
491 */
492 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
493 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
494 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
495 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
496 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
497 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
498 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
499 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
500 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
501 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
502 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
503 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
504 /**
505 * @}
506 */
507
508 #if defined(USE_FULL_LL_DRIVER)
509 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
510 * @{
511 */
512 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
513 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
514 /**
515 * @}
516 */
517
518 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
519 * @{
520 */
521 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
522 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
523 /**
524 * @}
525 */
526 #endif /* USE_FULL_LL_DRIVER */
527
528 /** @defgroup TIM_LL_EC_IT IT Defines
529 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
530 * @{
531 */
532 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
533 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
534 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
535 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
536 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
537 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
538 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
539 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
540 /**
541 * @}
542 */
543
544 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
545 * @{
546 */
547 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
548 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
549 /**
550 * @}
551 */
552
553 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
554 * @{
555 */
556 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
557 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
558 /**
559 * @}
560 */
561
562 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
563 * @{
564 */
565 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
566 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
567 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
568 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
569 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
570 /**
571 * @}
572 */
573
574 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
575 * @{
576 */
577 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
578 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
579 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
580 /**
581 * @}
582 */
583
584 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
585 * @{
586 */
587 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
588 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
589 /**
590 * @}
591 */
592
593 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
594 * @{
595 */
596 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
597 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
598 /**
599 * @}
600 */
601
602 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
603 * @{
604 */
605 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
606 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
612 * @{
613 */
614 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
615 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
616 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
617 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
618 /**
619 * @}
620 */
621
622 /** @defgroup TIM_LL_EC_CHANNEL Channel
623 * @{
624 */
625 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
626 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
627 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
628 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
629 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
630 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
631 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
632 /**
633 * @}
634 */
635
636 #if defined(USE_FULL_LL_DRIVER)
637 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
638 * @{
639 */
640 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
641 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
642 /**
643 * @}
644 */
645 #endif /* USE_FULL_LL_DRIVER */
646
647 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
648 * @{
649 */
650 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
651 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
652 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
653 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
654 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
655 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
656 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
657 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
663 * @{
664 */
665 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
666 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
672 * @{
673 */
674 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
675 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
676 /**
677 * @}
678 */
679
680
681 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
682 * @{
683 */
684 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
685 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
686 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
692 * @{
693 */
694 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
695 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
696 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
697 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
703 * @{
704 */
705 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
706 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
707 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
708 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
709 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
710 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
711 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
712 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
713 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
714 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
715 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
716 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
717 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
718 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
719 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
720 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
721 /**
722 * @}
723 */
724
725 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
726 * @{
727 */
728 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
729 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
730 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
731 /**
732 * @}
733 */
734
735 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
736 * @{
737 */
738 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
739 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
740 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
741 /**
742 * @}
743 */
744
745 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
746 * @{
747 */
748 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
749 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
750 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
751 /**
752 * @}
753 */
754
755 /** @defgroup TIM_LL_EC_TRGO Trigger Output
756 * @{
757 */
758 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
759 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
760 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
761 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
762 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
763 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
764 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
765 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
766 /**
767 * @}
768 */
769
770
771 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
772 * @{
773 */
774 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
775 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
776 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
777 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
778 /**
779 * @}
780 */
781
782 /** @defgroup TIM_LL_EC_TS Trigger Selection
783 * @{
784 */
785 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
786 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
787 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
788 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
789 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
790 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
791 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
792 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
793 /**
794 * @}
795 */
796
797 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
798 * @{
799 */
800 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
801 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
802 /**
803 * @}
804 */
805
806 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
807 * @{
808 */
809 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
810 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
811 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
812 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
813 /**
814 * @}
815 */
816
817 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
818 * @{
819 */
820 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
821 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
822 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
823 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
824 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
825 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
826 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
827 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
828 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
829 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
830 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
831 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
832 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
833 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
834 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
835 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
836 /**
837 * @}
838 */
839
840
841 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
842 * @{
843 */
844 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
845 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
846 /**
847 * @}
848 */
849
850
851
852
853 /** @defgroup TIM_LL_EC_OSSI OSSI
854 * @{
855 */
856 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
857 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
858 /**
859 * @}
860 */
861
862 /** @defgroup TIM_LL_EC_OSSR OSSR
863 * @{
864 */
865 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
866 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
867 /**
868 * @}
869 */
870
871
872 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
873 * @{
874 */
875 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
876 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
877 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
878 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
879 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
880 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
881 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
882 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
883 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
884 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
885 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
886 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
887 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
888 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
889 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
890 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
891 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
892 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
893 /**
894 * @}
895 */
896
897 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
898 * @{
899 */
900 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
901 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
902 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
903 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
904 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
905 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
906 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
907 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
908 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
909 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
910 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
911 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
912 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
913 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
914 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
915 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
916 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
917 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
918 /**
919 * @}
920 */
921
922
923 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
924 * @{
925 */
926 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
927 #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
928 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
929 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
930 /**
931 * @}
932 */
933
934 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
935 * @{
936 */
937 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
938 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
939 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
940 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
941 /**
942 * @}
943 */
944
945 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
946 * @{
947 */
948 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
949 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
950 #define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
951 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */
952 /**
953 * @}
954 */
955
956
957 /**
958 * @}
959 */
960
961 /* Exported macro ------------------------------------------------------------*/
962 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
963 * @{
964 */
965
966 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
967 * @{
968 */
969 /**
970 * @brief Write a value in TIM register.
971 * @param __INSTANCE__ TIM Instance
972 * @param __REG__ Register to be written
973 * @param __VALUE__ Value to be written in the register
974 * @retval None
975 */
976 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
977
978 /**
979 * @brief Read a value in TIM register.
980 * @param __INSTANCE__ TIM Instance
981 * @param __REG__ Register to be read
982 * @retval Register value
983 */
984 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
985 /**
986 * @}
987 */
988
989 /**
990 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
991 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
992 * @param __TIMCLK__ timer input clock frequency (in Hz)
993 * @param __CKD__ This parameter can be one of the following values:
994 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
995 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
996 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
997 * @param __DT__ deadtime duration (in ns)
998 * @retval DTG[0:7]
999 */
1000 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1001 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1002 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1003 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1004 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1005 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1006 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1007 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1008 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1009 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1010 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1011 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1012 0U)
1013
1014 /**
1015 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1016 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1017 * @param __TIMCLK__ timer input clock frequency (in Hz)
1018 * @param __CNTCLK__ counter clock frequency (in Hz)
1019 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1020 */
1021 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1022 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1023
1024 /**
1025 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1026 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1027 * @param __TIMCLK__ timer input clock frequency (in Hz)
1028 * @param __PSC__ prescaler
1029 * @param __FREQ__ output signal frequency (in Hz)
1030 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1031 */
1032 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1033 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1034
1035 /**
1036 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1037 * active/inactive delay.
1038 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1039 * @param __TIMCLK__ timer input clock frequency (in Hz)
1040 * @param __PSC__ prescaler
1041 * @param __DELAY__ timer output compare active/inactive delay (in us)
1042 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1043 */
1044 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1045 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1046 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1047
1048 /**
1049 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1050 * (when the timer operates in one pulse mode).
1051 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1052 * @param __TIMCLK__ timer input clock frequency (in Hz)
1053 * @param __PSC__ prescaler
1054 * @param __DELAY__ timer output compare active/inactive delay (in us)
1055 * @param __PULSE__ pulse duration (in us)
1056 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1057 */
1058 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1059 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1060 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1061
1062 /**
1063 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1064 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1065 * @param __ICPSC__ This parameter can be one of the following values:
1066 * @arg @ref LL_TIM_ICPSC_DIV1
1067 * @arg @ref LL_TIM_ICPSC_DIV2
1068 * @arg @ref LL_TIM_ICPSC_DIV4
1069 * @arg @ref LL_TIM_ICPSC_DIV8
1070 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1071 */
1072 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1073 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1074
1075
1076 /**
1077 * @}
1078 */
1079
1080 /* Exported functions --------------------------------------------------------*/
1081 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1082 * @{
1083 */
1084
1085 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1086 * @{
1087 */
1088 /**
1089 * @brief Enable timer counter.
1090 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1091 * @param TIMx Timer instance
1092 * @retval None
1093 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1094 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1095 {
1096 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1097 }
1098
1099 /**
1100 * @brief Disable timer counter.
1101 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1102 * @param TIMx Timer instance
1103 * @retval None
1104 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1105 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1106 {
1107 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1108 }
1109
1110 /**
1111 * @brief Indicates whether the timer counter is enabled.
1112 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1113 * @param TIMx Timer instance
1114 * @retval State of bit (1 or 0).
1115 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1116 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1117 {
1118 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1119 }
1120
1121 /**
1122 * @brief Enable update event generation.
1123 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1124 * @param TIMx Timer instance
1125 * @retval None
1126 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1127 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1128 {
1129 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1130 }
1131
1132 /**
1133 * @brief Disable update event generation.
1134 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1135 * @param TIMx Timer instance
1136 * @retval None
1137 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1138 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1139 {
1140 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1141 }
1142
1143 /**
1144 * @brief Indicates whether update event generation is enabled.
1145 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1146 * @param TIMx Timer instance
1147 * @retval Inverted state of bit (0 or 1).
1148 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1149 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1150 {
1151 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1152 }
1153
1154 /**
1155 * @brief Set update event source
1156 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1157 * generate an update interrupt or DMA request if enabled:
1158 * - Counter overflow/underflow
1159 * - Setting the UG bit
1160 * - Update generation through the slave mode controller
1161 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1162 * overflow/underflow generates an update interrupt or DMA request if enabled.
1163 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1164 * @param TIMx Timer instance
1165 * @param UpdateSource This parameter can be one of the following values:
1166 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1167 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1168 * @retval None
1169 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1170 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1171 {
1172 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1173 }
1174
1175 /**
1176 * @brief Get actual event update source
1177 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1178 * @param TIMx Timer instance
1179 * @retval Returned value can be one of the following values:
1180 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1181 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1182 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1183 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1184 {
1185 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1186 }
1187
1188 /**
1189 * @brief Set one pulse mode (one shot v.s. repetitive).
1190 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1191 * @param TIMx Timer instance
1192 * @param OnePulseMode This parameter can be one of the following values:
1193 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1194 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1195 * @retval None
1196 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1197 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1198 {
1199 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1200 }
1201
1202 /**
1203 * @brief Get actual one pulse mode.
1204 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1205 * @param TIMx Timer instance
1206 * @retval Returned value can be one of the following values:
1207 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1208 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1209 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1210 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1211 {
1212 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1213 }
1214
1215 /**
1216 * @brief Set the timer counter counting mode.
1217 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1218 * check whether or not the counter mode selection feature is supported
1219 * by a timer instance.
1220 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1221 * requires a timer reset to avoid unexpected direction
1222 * due to DIR bit readonly in center aligned mode.
1223 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1224 * CR1 CMS LL_TIM_SetCounterMode
1225 * @param TIMx Timer instance
1226 * @param CounterMode This parameter can be one of the following values:
1227 * @arg @ref LL_TIM_COUNTERMODE_UP
1228 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1229 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1230 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1231 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1232 * @retval None
1233 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1234 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1235 {
1236 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1237 }
1238
1239 /**
1240 * @brief Get actual counter mode.
1241 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1242 * check whether or not the counter mode selection feature is supported
1243 * by a timer instance.
1244 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1245 * CR1 CMS LL_TIM_GetCounterMode
1246 * @param TIMx Timer instance
1247 * @retval Returned value can be one of the following values:
1248 * @arg @ref LL_TIM_COUNTERMODE_UP
1249 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1250 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1251 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1252 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1253 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1254 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1255 {
1256 uint32_t counter_mode;
1257
1258 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1259
1260 if (counter_mode == 0U)
1261 {
1262 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1263 }
1264
1265 return counter_mode;
1266 }
1267
1268 /**
1269 * @brief Enable auto-reload (ARR) preload.
1270 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1271 * @param TIMx Timer instance
1272 * @retval None
1273 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1274 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1275 {
1276 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1277 }
1278
1279 /**
1280 * @brief Disable auto-reload (ARR) preload.
1281 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1282 * @param TIMx Timer instance
1283 * @retval None
1284 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1285 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1286 {
1287 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1288 }
1289
1290 /**
1291 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1292 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1293 * @param TIMx Timer instance
1294 * @retval State of bit (1 or 0).
1295 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1296 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1297 {
1298 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1299 }
1300
1301 /**
1302 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1303 * (when supported) and the digital filters.
1304 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1305 * whether or not the clock division feature is supported by the timer
1306 * instance.
1307 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1308 * @param TIMx Timer instance
1309 * @param ClockDivision This parameter can be one of the following values:
1310 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1311 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1312 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1313 * @retval None
1314 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1315 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1316 {
1317 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1318 }
1319
1320 /**
1321 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1322 * generators (when supported) and the digital filters.
1323 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1324 * whether or not the clock division feature is supported by the timer
1325 * instance.
1326 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1327 * @param TIMx Timer instance
1328 * @retval Returned value can be one of the following values:
1329 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1330 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1331 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1332 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1333 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1334 {
1335 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1336 }
1337
1338 /**
1339 * @brief Set the counter value.
1340 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1341 * whether or not a timer instance supports a 32 bits counter.
1342 * @rmtoll CNT CNT LL_TIM_SetCounter
1343 * @param TIMx Timer instance
1344 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1345 * @retval None
1346 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1347 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1348 {
1349 WRITE_REG(TIMx->CNT, Counter);
1350 }
1351
1352 /**
1353 * @brief Get the counter value.
1354 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1355 * whether or not a timer instance supports a 32 bits counter.
1356 * @rmtoll CNT CNT LL_TIM_GetCounter
1357 * @param TIMx Timer instance
1358 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1359 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1360 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1361 {
1362 return (uint32_t)(READ_REG(TIMx->CNT));
1363 }
1364
1365 /**
1366 * @brief Get the current direction of the counter
1367 * @rmtoll CR1 DIR LL_TIM_GetDirection
1368 * @param TIMx Timer instance
1369 * @retval Returned value can be one of the following values:
1370 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1371 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1372 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1373 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1374 {
1375 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1376 }
1377
1378 /**
1379 * @brief Set the prescaler value.
1380 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1381 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1382 * prescaler ratio is taken into account at the next update event.
1383 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1384 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1385 * @param TIMx Timer instance
1386 * @param Prescaler between Min_Data=0 and Max_Data=65535
1387 * @retval None
1388 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1389 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1390 {
1391 WRITE_REG(TIMx->PSC, Prescaler);
1392 }
1393
1394 /**
1395 * @brief Get the prescaler value.
1396 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1397 * @param TIMx Timer instance
1398 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1399 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1400 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1401 {
1402 return (uint32_t)(READ_REG(TIMx->PSC));
1403 }
1404
1405 /**
1406 * @brief Set the auto-reload value.
1407 * @note The counter is blocked while the auto-reload value is null.
1408 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1409 * whether or not a timer instance supports a 32 bits counter.
1410 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1411 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1412 * @param TIMx Timer instance
1413 * @param AutoReload between Min_Data=0 and Max_Data=65535
1414 * @retval None
1415 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1416 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1417 {
1418 WRITE_REG(TIMx->ARR, AutoReload);
1419 }
1420
1421 /**
1422 * @brief Get the auto-reload value.
1423 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1424 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1425 * whether or not a timer instance supports a 32 bits counter.
1426 * @param TIMx Timer instance
1427 * @retval Auto-reload value
1428 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1429 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1430 {
1431 return (uint32_t)(READ_REG(TIMx->ARR));
1432 }
1433
1434 /**
1435 * @brief Set the repetition counter value.
1436 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1437 * whether or not a timer instance supports a repetition counter.
1438 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1439 * @param TIMx Timer instance
1440 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1441 * @retval None
1442 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1443 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1444 {
1445 WRITE_REG(TIMx->RCR, RepetitionCounter);
1446 }
1447
1448 /**
1449 * @brief Get the repetition counter value.
1450 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1451 * whether or not a timer instance supports a repetition counter.
1452 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1453 * @param TIMx Timer instance
1454 * @retval Repetition counter value
1455 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1456 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1457 {
1458 return (uint32_t)(READ_REG(TIMx->RCR));
1459 }
1460
1461 /**
1462 * @}
1463 */
1464
1465 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1466 * @{
1467 */
1468 /**
1469 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1470 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1471 * they are updated only when a commutation event (COM) occurs.
1472 * @note Only on channels that have a complementary output.
1473 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1474 * whether or not a timer instance is able to generate a commutation event.
1475 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1476 * @param TIMx Timer instance
1477 * @retval None
1478 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1479 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1480 {
1481 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1482 }
1483
1484 /**
1485 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1486 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1487 * whether or not a timer instance is able to generate a commutation event.
1488 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1489 * @param TIMx Timer instance
1490 * @retval None
1491 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1492 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1493 {
1494 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1495 }
1496
1497 /**
1498 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1499 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1500 * @param TIMx Timer instance
1501 * @retval State of bit (1 or 0).
1502 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1503 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1504 {
1505 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1506 }
1507
1508 /**
1509 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1510 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1511 * whether or not a timer instance is able to generate a commutation event.
1512 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1513 * @param TIMx Timer instance
1514 * @param CCUpdateSource This parameter can be one of the following values:
1515 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1516 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1517 * @retval None
1518 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1519 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1520 {
1521 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1522 }
1523
1524 /**
1525 * @brief Set the trigger of the capture/compare DMA request.
1526 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1527 * @param TIMx Timer instance
1528 * @param DMAReqTrigger This parameter can be one of the following values:
1529 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1530 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1531 * @retval None
1532 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1533 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1534 {
1535 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1536 }
1537
1538 /**
1539 * @brief Get actual trigger of the capture/compare DMA request.
1540 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1541 * @param TIMx Timer instance
1542 * @retval Returned value can be one of the following values:
1543 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1544 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1545 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1546 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1547 {
1548 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1549 }
1550
1551 /**
1552 * @brief Set the lock level to freeze the
1553 * configuration of several capture/compare parameters.
1554 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1555 * the lock mechanism is supported by a timer instance.
1556 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1557 * @param TIMx Timer instance
1558 * @param LockLevel This parameter can be one of the following values:
1559 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1560 * @arg @ref LL_TIM_LOCKLEVEL_1
1561 * @arg @ref LL_TIM_LOCKLEVEL_2
1562 * @arg @ref LL_TIM_LOCKLEVEL_3
1563 * @retval None
1564 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1565 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1566 {
1567 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1568 }
1569
1570 /**
1571 * @brief Enable capture/compare channels.
1572 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1573 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1574 * CCER CC2E LL_TIM_CC_EnableChannel\n
1575 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1576 * CCER CC3E LL_TIM_CC_EnableChannel\n
1577 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1578 * CCER CC4E LL_TIM_CC_EnableChannel
1579 * @param TIMx Timer instance
1580 * @param Channels This parameter can be a combination of the following values:
1581 * @arg @ref LL_TIM_CHANNEL_CH1
1582 * @arg @ref LL_TIM_CHANNEL_CH1N
1583 * @arg @ref LL_TIM_CHANNEL_CH2
1584 * @arg @ref LL_TIM_CHANNEL_CH2N
1585 * @arg @ref LL_TIM_CHANNEL_CH3
1586 * @arg @ref LL_TIM_CHANNEL_CH3N
1587 * @arg @ref LL_TIM_CHANNEL_CH4
1588 * @retval None
1589 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1590 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1591 {
1592 SET_BIT(TIMx->CCER, Channels);
1593 }
1594
1595 /**
1596 * @brief Disable capture/compare channels.
1597 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1598 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1599 * CCER CC2E LL_TIM_CC_DisableChannel\n
1600 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1601 * CCER CC3E LL_TIM_CC_DisableChannel\n
1602 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1603 * CCER CC4E LL_TIM_CC_DisableChannel
1604 * @param TIMx Timer instance
1605 * @param Channels This parameter can be a combination of the following values:
1606 * @arg @ref LL_TIM_CHANNEL_CH1
1607 * @arg @ref LL_TIM_CHANNEL_CH1N
1608 * @arg @ref LL_TIM_CHANNEL_CH2
1609 * @arg @ref LL_TIM_CHANNEL_CH2N
1610 * @arg @ref LL_TIM_CHANNEL_CH3
1611 * @arg @ref LL_TIM_CHANNEL_CH3N
1612 * @arg @ref LL_TIM_CHANNEL_CH4
1613 * @retval None
1614 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1615 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1616 {
1617 CLEAR_BIT(TIMx->CCER, Channels);
1618 }
1619
1620 /**
1621 * @brief Indicate whether channel(s) is(are) enabled.
1622 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1623 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1624 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1625 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1626 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1627 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1628 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1629 * @param TIMx Timer instance
1630 * @param Channels This parameter can be a combination of the following values:
1631 * @arg @ref LL_TIM_CHANNEL_CH1
1632 * @arg @ref LL_TIM_CHANNEL_CH1N
1633 * @arg @ref LL_TIM_CHANNEL_CH2
1634 * @arg @ref LL_TIM_CHANNEL_CH2N
1635 * @arg @ref LL_TIM_CHANNEL_CH3
1636 * @arg @ref LL_TIM_CHANNEL_CH3N
1637 * @arg @ref LL_TIM_CHANNEL_CH4
1638 * @retval State of bit (1 or 0).
1639 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1640 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1641 {
1642 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1643 }
1644
1645 /**
1646 * @}
1647 */
1648
1649 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1650 * @{
1651 */
1652 /**
1653 * @brief Configure an output channel.
1654 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1655 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1656 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1657 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1658 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1659 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1660 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1661 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1662 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1663 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1664 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1665 * CR2 OIS4 LL_TIM_OC_ConfigOutput
1666 * @param TIMx Timer instance
1667 * @param Channel This parameter can be one of the following values:
1668 * @arg @ref LL_TIM_CHANNEL_CH1
1669 * @arg @ref LL_TIM_CHANNEL_CH2
1670 * @arg @ref LL_TIM_CHANNEL_CH3
1671 * @arg @ref LL_TIM_CHANNEL_CH4
1672 * @param Configuration This parameter must be a combination of all the following values:
1673 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1674 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1675 * @retval None
1676 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1677 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1678 {
1679 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1680 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1681 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1682 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1683 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1684 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1685 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1686 }
1687
1688 /**
1689 * @brief Define the behavior of the output reference signal OCxREF from which
1690 * OCx and OCxN (when relevant) are derived.
1691 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1692 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1693 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1694 * CCMR2 OC4M LL_TIM_OC_SetMode
1695 * @param TIMx Timer instance
1696 * @param Channel This parameter can be one of the following values:
1697 * @arg @ref LL_TIM_CHANNEL_CH1
1698 * @arg @ref LL_TIM_CHANNEL_CH2
1699 * @arg @ref LL_TIM_CHANNEL_CH3
1700 * @arg @ref LL_TIM_CHANNEL_CH4
1701 * @param Mode This parameter can be one of the following values:
1702 * @arg @ref LL_TIM_OCMODE_FROZEN
1703 * @arg @ref LL_TIM_OCMODE_ACTIVE
1704 * @arg @ref LL_TIM_OCMODE_INACTIVE
1705 * @arg @ref LL_TIM_OCMODE_TOGGLE
1706 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1707 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1708 * @arg @ref LL_TIM_OCMODE_PWM1
1709 * @arg @ref LL_TIM_OCMODE_PWM2
1710 * @retval None
1711 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1712 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1713 {
1714 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1715 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1716 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1717 }
1718
1719 /**
1720 * @brief Get the output compare mode of an output channel.
1721 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1722 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1723 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1724 * CCMR2 OC4M LL_TIM_OC_GetMode
1725 * @param TIMx Timer instance
1726 * @param Channel This parameter can be one of the following values:
1727 * @arg @ref LL_TIM_CHANNEL_CH1
1728 * @arg @ref LL_TIM_CHANNEL_CH2
1729 * @arg @ref LL_TIM_CHANNEL_CH3
1730 * @arg @ref LL_TIM_CHANNEL_CH4
1731 * @retval Returned value can be one of the following values:
1732 * @arg @ref LL_TIM_OCMODE_FROZEN
1733 * @arg @ref LL_TIM_OCMODE_ACTIVE
1734 * @arg @ref LL_TIM_OCMODE_INACTIVE
1735 * @arg @ref LL_TIM_OCMODE_TOGGLE
1736 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1737 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1738 * @arg @ref LL_TIM_OCMODE_PWM1
1739 * @arg @ref LL_TIM_OCMODE_PWM2
1740 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)1741 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
1742 {
1743 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1744 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1745 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1746 }
1747
1748 /**
1749 * @brief Set the polarity of an output channel.
1750 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1751 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1752 * CCER CC2P LL_TIM_OC_SetPolarity\n
1753 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1754 * CCER CC3P LL_TIM_OC_SetPolarity\n
1755 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1756 * CCER CC4P LL_TIM_OC_SetPolarity
1757 * @param TIMx Timer instance
1758 * @param Channel This parameter can be one of the following values:
1759 * @arg @ref LL_TIM_CHANNEL_CH1
1760 * @arg @ref LL_TIM_CHANNEL_CH1N
1761 * @arg @ref LL_TIM_CHANNEL_CH2
1762 * @arg @ref LL_TIM_CHANNEL_CH2N
1763 * @arg @ref LL_TIM_CHANNEL_CH3
1764 * @arg @ref LL_TIM_CHANNEL_CH3N
1765 * @arg @ref LL_TIM_CHANNEL_CH4
1766 * @param Polarity This parameter can be one of the following values:
1767 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1768 * @arg @ref LL_TIM_OCPOLARITY_LOW
1769 * @retval None
1770 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1771 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1772 {
1773 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1774 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1775 }
1776
1777 /**
1778 * @brief Get the polarity of an output channel.
1779 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1780 * CCER CC1NP LL_TIM_OC_GetPolarity\n
1781 * CCER CC2P LL_TIM_OC_GetPolarity\n
1782 * CCER CC2NP LL_TIM_OC_GetPolarity\n
1783 * CCER CC3P LL_TIM_OC_GetPolarity\n
1784 * CCER CC3NP LL_TIM_OC_GetPolarity\n
1785 * CCER CC4P LL_TIM_OC_GetPolarity
1786 * @param TIMx Timer instance
1787 * @param Channel This parameter can be one of the following values:
1788 * @arg @ref LL_TIM_CHANNEL_CH1
1789 * @arg @ref LL_TIM_CHANNEL_CH1N
1790 * @arg @ref LL_TIM_CHANNEL_CH2
1791 * @arg @ref LL_TIM_CHANNEL_CH2N
1792 * @arg @ref LL_TIM_CHANNEL_CH3
1793 * @arg @ref LL_TIM_CHANNEL_CH3N
1794 * @arg @ref LL_TIM_CHANNEL_CH4
1795 * @retval Returned value can be one of the following values:
1796 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1797 * @arg @ref LL_TIM_OCPOLARITY_LOW
1798 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)1799 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
1800 {
1801 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1802 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1803 }
1804
1805 /**
1806 * @brief Set the IDLE state of an output channel
1807 * @note This function is significant only for the timer instances
1808 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
1809 * can be used to check whether or not a timer instance provides
1810 * a break input.
1811 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1812 * CR2 OIS1N LL_TIM_OC_SetIdleState\n
1813 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
1814 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
1815 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
1816 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
1817 * CR2 OIS4 LL_TIM_OC_SetIdleState
1818 * @param TIMx Timer instance
1819 * @param Channel This parameter can be one of the following values:
1820 * @arg @ref LL_TIM_CHANNEL_CH1
1821 * @arg @ref LL_TIM_CHANNEL_CH1N
1822 * @arg @ref LL_TIM_CHANNEL_CH2
1823 * @arg @ref LL_TIM_CHANNEL_CH2N
1824 * @arg @ref LL_TIM_CHANNEL_CH3
1825 * @arg @ref LL_TIM_CHANNEL_CH3N
1826 * @arg @ref LL_TIM_CHANNEL_CH4
1827 * @param IdleState This parameter can be one of the following values:
1828 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1829 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1830 * @retval None
1831 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)1832 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1833 {
1834 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1835 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1836 }
1837
1838 /**
1839 * @brief Get the IDLE state of an output channel
1840 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1841 * CR2 OIS1N LL_TIM_OC_GetIdleState\n
1842 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
1843 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
1844 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
1845 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
1846 * CR2 OIS4 LL_TIM_OC_GetIdleState
1847 * @param TIMx Timer instance
1848 * @param Channel This parameter can be one of the following values:
1849 * @arg @ref LL_TIM_CHANNEL_CH1
1850 * @arg @ref LL_TIM_CHANNEL_CH1N
1851 * @arg @ref LL_TIM_CHANNEL_CH2
1852 * @arg @ref LL_TIM_CHANNEL_CH2N
1853 * @arg @ref LL_TIM_CHANNEL_CH3
1854 * @arg @ref LL_TIM_CHANNEL_CH3N
1855 * @arg @ref LL_TIM_CHANNEL_CH4
1856 * @retval Returned value can be one of the following values:
1857 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1858 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1859 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)1860 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
1861 {
1862 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1863 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1864 }
1865
1866 /**
1867 * @brief Enable fast mode for the output channel.
1868 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1869 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1870 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1871 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1872 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1873 * @param TIMx Timer instance
1874 * @param Channel This parameter can be one of the following values:
1875 * @arg @ref LL_TIM_CHANNEL_CH1
1876 * @arg @ref LL_TIM_CHANNEL_CH2
1877 * @arg @ref LL_TIM_CHANNEL_CH3
1878 * @arg @ref LL_TIM_CHANNEL_CH4
1879 * @retval None
1880 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1881 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1882 {
1883 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1884 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1885 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1886
1887 }
1888
1889 /**
1890 * @brief Disable fast mode for the output channel.
1891 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1892 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1893 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1894 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1895 * @param TIMx Timer instance
1896 * @param Channel This parameter can be one of the following values:
1897 * @arg @ref LL_TIM_CHANNEL_CH1
1898 * @arg @ref LL_TIM_CHANNEL_CH2
1899 * @arg @ref LL_TIM_CHANNEL_CH3
1900 * @arg @ref LL_TIM_CHANNEL_CH4
1901 * @retval None
1902 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1903 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1904 {
1905 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1906 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1907 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1908
1909 }
1910
1911 /**
1912 * @brief Indicates whether fast mode is enabled for the output channel.
1913 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1914 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1915 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1916 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1917 * @param TIMx Timer instance
1918 * @param Channel This parameter can be one of the following values:
1919 * @arg @ref LL_TIM_CHANNEL_CH1
1920 * @arg @ref LL_TIM_CHANNEL_CH2
1921 * @arg @ref LL_TIM_CHANNEL_CH3
1922 * @arg @ref LL_TIM_CHANNEL_CH4
1923 * @retval State of bit (1 or 0).
1924 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)1925 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
1926 {
1927 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1928 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1929 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1930 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1931 }
1932
1933 /**
1934 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1935 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1936 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1937 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1938 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1939 * @param TIMx Timer instance
1940 * @param Channel This parameter can be one of the following values:
1941 * @arg @ref LL_TIM_CHANNEL_CH1
1942 * @arg @ref LL_TIM_CHANNEL_CH2
1943 * @arg @ref LL_TIM_CHANNEL_CH3
1944 * @arg @ref LL_TIM_CHANNEL_CH4
1945 * @retval None
1946 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1947 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1948 {
1949 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1950 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1951 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1952 }
1953
1954 /**
1955 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1956 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1957 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1958 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1959 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1960 * @param TIMx Timer instance
1961 * @param Channel This parameter can be one of the following values:
1962 * @arg @ref LL_TIM_CHANNEL_CH1
1963 * @arg @ref LL_TIM_CHANNEL_CH2
1964 * @arg @ref LL_TIM_CHANNEL_CH3
1965 * @arg @ref LL_TIM_CHANNEL_CH4
1966 * @retval None
1967 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1968 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1969 {
1970 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1971 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1972 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1973 }
1974
1975 /**
1976 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1977 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1978 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1979 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1980 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
1981 * @param TIMx Timer instance
1982 * @param Channel This parameter can be one of the following values:
1983 * @arg @ref LL_TIM_CHANNEL_CH1
1984 * @arg @ref LL_TIM_CHANNEL_CH2
1985 * @arg @ref LL_TIM_CHANNEL_CH3
1986 * @arg @ref LL_TIM_CHANNEL_CH4
1987 * @retval State of bit (1 or 0).
1988 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)1989 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
1990 {
1991 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1992 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1993 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
1994 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1995 }
1996
1997 /**
1998 * @brief Enable clearing the output channel on an external event.
1999 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2000 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2001 * or not a timer instance can clear the OCxREF signal on an external event.
2002 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2003 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2004 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2005 * CCMR2 OC4CE LL_TIM_OC_EnableClear
2006 * @param TIMx Timer instance
2007 * @param Channel This parameter can be one of the following values:
2008 * @arg @ref LL_TIM_CHANNEL_CH1
2009 * @arg @ref LL_TIM_CHANNEL_CH2
2010 * @arg @ref LL_TIM_CHANNEL_CH3
2011 * @arg @ref LL_TIM_CHANNEL_CH4
2012 * @retval None
2013 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2014 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2015 {
2016 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2017 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2018 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2019 }
2020
2021 /**
2022 * @brief Disable clearing the output channel on an external event.
2023 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2024 * or not a timer instance can clear the OCxREF signal on an external event.
2025 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2026 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2027 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2028 * CCMR2 OC4CE LL_TIM_OC_DisableClear
2029 * @param TIMx Timer instance
2030 * @param Channel This parameter can be one of the following values:
2031 * @arg @ref LL_TIM_CHANNEL_CH1
2032 * @arg @ref LL_TIM_CHANNEL_CH2
2033 * @arg @ref LL_TIM_CHANNEL_CH3
2034 * @arg @ref LL_TIM_CHANNEL_CH4
2035 * @retval None
2036 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2037 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2038 {
2039 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2040 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2041 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2042 }
2043
2044 /**
2045 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2046 * @note This function enables clearing the output channel on an external event.
2047 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2048 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2049 * or not a timer instance can clear the OCxREF signal on an external event.
2050 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2051 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2052 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2053 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2054 * @param TIMx Timer instance
2055 * @param Channel This parameter can be one of the following values:
2056 * @arg @ref LL_TIM_CHANNEL_CH1
2057 * @arg @ref LL_TIM_CHANNEL_CH2
2058 * @arg @ref LL_TIM_CHANNEL_CH3
2059 * @arg @ref LL_TIM_CHANNEL_CH4
2060 * @retval State of bit (1 or 0).
2061 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2062 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2063 {
2064 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2065 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2066 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2067 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2068 }
2069
2070 /**
2071 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2072 * the Ocx and OCxN signals).
2073 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2074 * dead-time insertion feature is supported by a timer instance.
2075 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2076 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2077 * @param TIMx Timer instance
2078 * @param DeadTime between Min_Data=0 and Max_Data=255
2079 * @retval None
2080 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2081 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2082 {
2083 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2084 }
2085
2086 /**
2087 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2088 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2089 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2090 * whether or not a timer instance supports a 32 bits counter.
2091 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2092 * output channel 1 is supported by a timer instance.
2093 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2094 * @param TIMx Timer instance
2095 * @param CompareValue between Min_Data=0 and Max_Data=65535
2096 * @retval None
2097 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2098 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2099 {
2100 WRITE_REG(TIMx->CCR1, CompareValue);
2101 }
2102
2103 /**
2104 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2105 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2106 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2107 * whether or not a timer instance supports a 32 bits counter.
2108 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2109 * output channel 2 is supported by a timer instance.
2110 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2111 * @param TIMx Timer instance
2112 * @param CompareValue between Min_Data=0 and Max_Data=65535
2113 * @retval None
2114 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2115 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2116 {
2117 WRITE_REG(TIMx->CCR2, CompareValue);
2118 }
2119
2120 /**
2121 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2122 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2123 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2124 * whether or not a timer instance supports a 32 bits counter.
2125 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2126 * output channel is supported by a timer instance.
2127 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2128 * @param TIMx Timer instance
2129 * @param CompareValue between Min_Data=0 and Max_Data=65535
2130 * @retval None
2131 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2132 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2133 {
2134 WRITE_REG(TIMx->CCR3, CompareValue);
2135 }
2136
2137 /**
2138 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2139 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2140 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2141 * whether or not a timer instance supports a 32 bits counter.
2142 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2143 * output channel 4 is supported by a timer instance.
2144 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2145 * @param TIMx Timer instance
2146 * @param CompareValue between Min_Data=0 and Max_Data=65535
2147 * @retval None
2148 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2149 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2150 {
2151 WRITE_REG(TIMx->CCR4, CompareValue);
2152 }
2153
2154 /**
2155 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2156 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2157 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2158 * whether or not a timer instance supports a 32 bits counter.
2159 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2160 * output channel 1 is supported by a timer instance.
2161 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2162 * @param TIMx Timer instance
2163 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2164 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2165 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2166 {
2167 return (uint32_t)(READ_REG(TIMx->CCR1));
2168 }
2169
2170 /**
2171 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2172 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2173 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2174 * whether or not a timer instance supports a 32 bits counter.
2175 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2176 * output channel 2 is supported by a timer instance.
2177 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2178 * @param TIMx Timer instance
2179 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2180 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2181 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2182 {
2183 return (uint32_t)(READ_REG(TIMx->CCR2));
2184 }
2185
2186 /**
2187 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2188 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2189 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2190 * whether or not a timer instance supports a 32 bits counter.
2191 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2192 * output channel 3 is supported by a timer instance.
2193 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2194 * @param TIMx Timer instance
2195 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2196 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2197 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2198 {
2199 return (uint32_t)(READ_REG(TIMx->CCR3));
2200 }
2201
2202 /**
2203 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2204 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2205 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2206 * whether or not a timer instance supports a 32 bits counter.
2207 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2208 * output channel 4 is supported by a timer instance.
2209 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2210 * @param TIMx Timer instance
2211 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2212 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2213 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2214 {
2215 return (uint32_t)(READ_REG(TIMx->CCR4));
2216 }
2217
2218 /**
2219 * @}
2220 */
2221
2222 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2223 * @{
2224 */
2225 /**
2226 * @brief Configure input channel.
2227 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2228 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2229 * CCMR1 IC1F LL_TIM_IC_Config\n
2230 * CCMR1 CC2S LL_TIM_IC_Config\n
2231 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2232 * CCMR1 IC2F LL_TIM_IC_Config\n
2233 * CCMR2 CC3S LL_TIM_IC_Config\n
2234 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2235 * CCMR2 IC3F LL_TIM_IC_Config\n
2236 * CCMR2 CC4S LL_TIM_IC_Config\n
2237 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2238 * CCMR2 IC4F LL_TIM_IC_Config\n
2239 * CCER CC1P LL_TIM_IC_Config\n
2240 * CCER CC1NP LL_TIM_IC_Config\n
2241 * CCER CC2P LL_TIM_IC_Config\n
2242 * CCER CC2NP LL_TIM_IC_Config\n
2243 * CCER CC3P LL_TIM_IC_Config\n
2244 * CCER CC3NP LL_TIM_IC_Config\n
2245 * CCER CC4P LL_TIM_IC_Config\n
2246 * CCER CC4NP LL_TIM_IC_Config
2247 * @param TIMx Timer instance
2248 * @param Channel This parameter can be one of the following values:
2249 * @arg @ref LL_TIM_CHANNEL_CH1
2250 * @arg @ref LL_TIM_CHANNEL_CH2
2251 * @arg @ref LL_TIM_CHANNEL_CH3
2252 * @arg @ref LL_TIM_CHANNEL_CH4
2253 * @param Configuration This parameter must be a combination of all the following values:
2254 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2255 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2256 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2257 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2258 * @retval None
2259 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2260 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2261 {
2262 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2263 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2264 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2265 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2266 << SHIFT_TAB_ICxx[iChannel]);
2267 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2268 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2269 }
2270
2271 /**
2272 * @brief Set the active input.
2273 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2274 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2275 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2276 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2277 * @param TIMx Timer instance
2278 * @param Channel This parameter can be one of the following values:
2279 * @arg @ref LL_TIM_CHANNEL_CH1
2280 * @arg @ref LL_TIM_CHANNEL_CH2
2281 * @arg @ref LL_TIM_CHANNEL_CH3
2282 * @arg @ref LL_TIM_CHANNEL_CH4
2283 * @param ICActiveInput This parameter can be one of the following values:
2284 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2285 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2286 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2287 * @retval None
2288 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2289 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2290 {
2291 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2292 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2293 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2294 }
2295
2296 /**
2297 * @brief Get the current active input.
2298 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2299 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2300 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2301 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2302 * @param TIMx Timer instance
2303 * @param Channel This parameter can be one of the following values:
2304 * @arg @ref LL_TIM_CHANNEL_CH1
2305 * @arg @ref LL_TIM_CHANNEL_CH2
2306 * @arg @ref LL_TIM_CHANNEL_CH3
2307 * @arg @ref LL_TIM_CHANNEL_CH4
2308 * @retval Returned value can be one of the following values:
2309 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2310 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2311 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2312 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2313 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2314 {
2315 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2316 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2317 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2318 }
2319
2320 /**
2321 * @brief Set the prescaler of input channel.
2322 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2323 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2324 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2325 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2326 * @param TIMx Timer instance
2327 * @param Channel This parameter can be one of the following values:
2328 * @arg @ref LL_TIM_CHANNEL_CH1
2329 * @arg @ref LL_TIM_CHANNEL_CH2
2330 * @arg @ref LL_TIM_CHANNEL_CH3
2331 * @arg @ref LL_TIM_CHANNEL_CH4
2332 * @param ICPrescaler This parameter can be one of the following values:
2333 * @arg @ref LL_TIM_ICPSC_DIV1
2334 * @arg @ref LL_TIM_ICPSC_DIV2
2335 * @arg @ref LL_TIM_ICPSC_DIV4
2336 * @arg @ref LL_TIM_ICPSC_DIV8
2337 * @retval None
2338 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2339 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2340 {
2341 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2342 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2343 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2344 }
2345
2346 /**
2347 * @brief Get the current prescaler value acting on an input channel.
2348 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2349 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2350 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2351 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2352 * @param TIMx Timer instance
2353 * @param Channel This parameter can be one of the following values:
2354 * @arg @ref LL_TIM_CHANNEL_CH1
2355 * @arg @ref LL_TIM_CHANNEL_CH2
2356 * @arg @ref LL_TIM_CHANNEL_CH3
2357 * @arg @ref LL_TIM_CHANNEL_CH4
2358 * @retval Returned value can be one of the following values:
2359 * @arg @ref LL_TIM_ICPSC_DIV1
2360 * @arg @ref LL_TIM_ICPSC_DIV2
2361 * @arg @ref LL_TIM_ICPSC_DIV4
2362 * @arg @ref LL_TIM_ICPSC_DIV8
2363 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2364 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2365 {
2366 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2367 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2368 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2369 }
2370
2371 /**
2372 * @brief Set the input filter duration.
2373 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2374 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2375 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2376 * CCMR2 IC4F LL_TIM_IC_SetFilter
2377 * @param TIMx Timer instance
2378 * @param Channel This parameter can be one of the following values:
2379 * @arg @ref LL_TIM_CHANNEL_CH1
2380 * @arg @ref LL_TIM_CHANNEL_CH2
2381 * @arg @ref LL_TIM_CHANNEL_CH3
2382 * @arg @ref LL_TIM_CHANNEL_CH4
2383 * @param ICFilter This parameter can be one of the following values:
2384 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2385 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2386 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2387 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2388 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2389 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2390 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2391 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2392 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2393 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2394 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2395 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2396 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2397 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2398 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2399 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2400 * @retval None
2401 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2402 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2403 {
2404 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2405 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2406 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2407 }
2408
2409 /**
2410 * @brief Get the input filter duration.
2411 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2412 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2413 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2414 * CCMR2 IC4F LL_TIM_IC_GetFilter
2415 * @param TIMx Timer instance
2416 * @param Channel This parameter can be one of the following values:
2417 * @arg @ref LL_TIM_CHANNEL_CH1
2418 * @arg @ref LL_TIM_CHANNEL_CH2
2419 * @arg @ref LL_TIM_CHANNEL_CH3
2420 * @arg @ref LL_TIM_CHANNEL_CH4
2421 * @retval Returned value can be one of the following values:
2422 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2423 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2424 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2425 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2426 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2427 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2428 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2429 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2430 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2431 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2432 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2433 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2434 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2435 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2436 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2437 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2438 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2439 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2440 {
2441 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2442 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2443 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2444 }
2445
2446 /**
2447 * @brief Set the input channel polarity.
2448 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2449 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2450 * CCER CC2P LL_TIM_IC_SetPolarity\n
2451 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2452 * CCER CC3P LL_TIM_IC_SetPolarity\n
2453 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2454 * CCER CC4P LL_TIM_IC_SetPolarity\n
2455 * CCER CC4NP LL_TIM_IC_SetPolarity
2456 * @param TIMx Timer instance
2457 * @param Channel This parameter can be one of the following values:
2458 * @arg @ref LL_TIM_CHANNEL_CH1
2459 * @arg @ref LL_TIM_CHANNEL_CH2
2460 * @arg @ref LL_TIM_CHANNEL_CH3
2461 * @arg @ref LL_TIM_CHANNEL_CH4
2462 * @param ICPolarity This parameter can be one of the following values:
2463 * @arg @ref LL_TIM_IC_POLARITY_RISING
2464 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2465 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2466 * @retval None
2467 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2468 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2469 {
2470 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2471 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2472 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2473 }
2474
2475 /**
2476 * @brief Get the current input channel polarity.
2477 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2478 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2479 * CCER CC2P LL_TIM_IC_GetPolarity\n
2480 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2481 * CCER CC3P LL_TIM_IC_GetPolarity\n
2482 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2483 * CCER CC4P LL_TIM_IC_GetPolarity\n
2484 * CCER CC4NP LL_TIM_IC_GetPolarity
2485 * @param TIMx Timer instance
2486 * @param Channel This parameter can be one of the following values:
2487 * @arg @ref LL_TIM_CHANNEL_CH1
2488 * @arg @ref LL_TIM_CHANNEL_CH2
2489 * @arg @ref LL_TIM_CHANNEL_CH3
2490 * @arg @ref LL_TIM_CHANNEL_CH4
2491 * @retval Returned value can be one of the following values:
2492 * @arg @ref LL_TIM_IC_POLARITY_RISING
2493 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2494 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2495 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2496 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2497 {
2498 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2499 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2500 SHIFT_TAB_CCxP[iChannel]);
2501 }
2502
2503 /**
2504 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2505 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2506 * a timer instance provides an XOR input.
2507 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2508 * @param TIMx Timer instance
2509 * @retval None
2510 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2511 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2512 {
2513 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2514 }
2515
2516 /**
2517 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2518 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2519 * a timer instance provides an XOR input.
2520 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2521 * @param TIMx Timer instance
2522 * @retval None
2523 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2524 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2525 {
2526 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2527 }
2528
2529 /**
2530 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2531 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2532 * a timer instance provides an XOR input.
2533 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2534 * @param TIMx Timer instance
2535 * @retval State of bit (1 or 0).
2536 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)2537 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
2538 {
2539 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2540 }
2541
2542 /**
2543 * @brief Get captured value for input channel 1.
2544 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2545 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2546 * whether or not a timer instance supports a 32 bits counter.
2547 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2548 * input channel 1 is supported by a timer instance.
2549 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2550 * @param TIMx Timer instance
2551 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2552 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)2553 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
2554 {
2555 return (uint32_t)(READ_REG(TIMx->CCR1));
2556 }
2557
2558 /**
2559 * @brief Get captured value for input channel 2.
2560 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2561 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2562 * whether or not a timer instance supports a 32 bits counter.
2563 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2564 * input channel 2 is supported by a timer instance.
2565 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2566 * @param TIMx Timer instance
2567 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2568 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)2569 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
2570 {
2571 return (uint32_t)(READ_REG(TIMx->CCR2));
2572 }
2573
2574 /**
2575 * @brief Get captured value for input channel 3.
2576 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2577 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2578 * whether or not a timer instance supports a 32 bits counter.
2579 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2580 * input channel 3 is supported by a timer instance.
2581 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2582 * @param TIMx Timer instance
2583 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2584 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)2585 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
2586 {
2587 return (uint32_t)(READ_REG(TIMx->CCR3));
2588 }
2589
2590 /**
2591 * @brief Get captured value for input channel 4.
2592 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2593 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2594 * whether or not a timer instance supports a 32 bits counter.
2595 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2596 * input channel 4 is supported by a timer instance.
2597 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2598 * @param TIMx Timer instance
2599 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2600 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)2601 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
2602 {
2603 return (uint32_t)(READ_REG(TIMx->CCR4));
2604 }
2605
2606 /**
2607 * @}
2608 */
2609
2610 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2611 * @{
2612 */
2613 /**
2614 * @brief Enable external clock mode 2.
2615 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2616 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2617 * whether or not a timer instance supports external clock mode2.
2618 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2619 * @param TIMx Timer instance
2620 * @retval None
2621 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2622 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2623 {
2624 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2625 }
2626
2627 /**
2628 * @brief Disable external clock mode 2.
2629 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2630 * whether or not a timer instance supports external clock mode2.
2631 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2632 * @param TIMx Timer instance
2633 * @retval None
2634 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2635 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2636 {
2637 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2638 }
2639
2640 /**
2641 * @brief Indicate whether external clock mode 2 is enabled.
2642 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2643 * whether or not a timer instance supports external clock mode2.
2644 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2645 * @param TIMx Timer instance
2646 * @retval State of bit (1 or 0).
2647 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)2648 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
2649 {
2650 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2651 }
2652
2653 /**
2654 * @brief Set the clock source of the counter clock.
2655 * @note when selected clock source is external clock mode 1, the timer input
2656 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2657 * function. This timer input must be configured by calling
2658 * the @ref LL_TIM_IC_Config() function.
2659 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2660 * whether or not a timer instance supports external clock mode1.
2661 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2662 * whether or not a timer instance supports external clock mode2.
2663 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2664 * SMCR ECE LL_TIM_SetClockSource
2665 * @param TIMx Timer instance
2666 * @param ClockSource This parameter can be one of the following values:
2667 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2668 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2669 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2670 * @retval None
2671 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2672 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2673 {
2674 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2675 }
2676
2677 /**
2678 * @brief Set the encoder interface mode.
2679 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2680 * whether or not a timer instance supports the encoder mode.
2681 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2682 * @param TIMx Timer instance
2683 * @param EncoderMode This parameter can be one of the following values:
2684 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2685 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2686 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2687 * @retval None
2688 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2689 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2690 {
2691 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2692 }
2693
2694 /**
2695 * @}
2696 */
2697
2698 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2699 * @{
2700 */
2701 /**
2702 * @brief Set the trigger output (TRGO) used for timer synchronization .
2703 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2704 * whether or not a timer instance can operate as a master timer.
2705 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2706 * @param TIMx Timer instance
2707 * @param TimerSynchronization This parameter can be one of the following values:
2708 * @arg @ref LL_TIM_TRGO_RESET
2709 * @arg @ref LL_TIM_TRGO_ENABLE
2710 * @arg @ref LL_TIM_TRGO_UPDATE
2711 * @arg @ref LL_TIM_TRGO_CC1IF
2712 * @arg @ref LL_TIM_TRGO_OC1REF
2713 * @arg @ref LL_TIM_TRGO_OC2REF
2714 * @arg @ref LL_TIM_TRGO_OC3REF
2715 * @arg @ref LL_TIM_TRGO_OC4REF
2716 * @retval None
2717 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2718 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2719 {
2720 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2721 }
2722
2723 /**
2724 * @brief Set the synchronization mode of a slave timer.
2725 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2726 * a timer instance can operate as a slave timer.
2727 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2728 * @param TIMx Timer instance
2729 * @param SlaveMode This parameter can be one of the following values:
2730 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2731 * @arg @ref LL_TIM_SLAVEMODE_RESET
2732 * @arg @ref LL_TIM_SLAVEMODE_GATED
2733 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2734 * @retval None
2735 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2736 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2737 {
2738 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2739 }
2740
2741 /**
2742 * @brief Set the selects the trigger input to be used to synchronize the counter.
2743 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2744 * a timer instance can operate as a slave timer.
2745 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2746 * @param TIMx Timer instance
2747 * @param TriggerInput This parameter can be one of the following values:
2748 * @arg @ref LL_TIM_TS_ITR0
2749 * @arg @ref LL_TIM_TS_ITR1
2750 * @arg @ref LL_TIM_TS_ITR2
2751 * @arg @ref LL_TIM_TS_ITR3
2752 * @arg @ref LL_TIM_TS_TI1F_ED
2753 * @arg @ref LL_TIM_TS_TI1FP1
2754 * @arg @ref LL_TIM_TS_TI2FP2
2755 * @arg @ref LL_TIM_TS_ETRF
2756 * @retval None
2757 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2758 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2759 {
2760 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2761 }
2762
2763 /**
2764 * @brief Enable the Master/Slave mode.
2765 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2766 * a timer instance can operate as a slave timer.
2767 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2768 * @param TIMx Timer instance
2769 * @retval None
2770 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2771 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2772 {
2773 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2774 }
2775
2776 /**
2777 * @brief Disable the Master/Slave mode.
2778 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2779 * a timer instance can operate as a slave timer.
2780 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2781 * @param TIMx Timer instance
2782 * @retval None
2783 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2784 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2785 {
2786 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2787 }
2788
2789 /**
2790 * @brief Indicates whether the Master/Slave mode is enabled.
2791 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2792 * a timer instance can operate as a slave timer.
2793 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2794 * @param TIMx Timer instance
2795 * @retval State of bit (1 or 0).
2796 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)2797 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
2798 {
2799 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2800 }
2801
2802 /**
2803 * @brief Configure the external trigger (ETR) input.
2804 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2805 * a timer instance provides an external trigger input.
2806 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2807 * SMCR ETPS LL_TIM_ConfigETR\n
2808 * SMCR ETF LL_TIM_ConfigETR
2809 * @param TIMx Timer instance
2810 * @param ETRPolarity This parameter can be one of the following values:
2811 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2812 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2813 * @param ETRPrescaler This parameter can be one of the following values:
2814 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2815 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2816 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2817 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2818 * @param ETRFilter This parameter can be one of the following values:
2819 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2820 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2821 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2822 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2823 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2824 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2825 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2826 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2827 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2828 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2829 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2830 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2831 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2832 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2833 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2834 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2835 * @retval None
2836 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2837 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2838 uint32_t ETRFilter)
2839 {
2840 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2841 }
2842
2843 /**
2844 * @}
2845 */
2846
2847 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
2848 * @{
2849 */
2850 /**
2851 * @brief Enable the break function.
2852 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2853 * a timer instance provides a break input.
2854 * @rmtoll BDTR BKE LL_TIM_EnableBRK
2855 * @param TIMx Timer instance
2856 * @retval None
2857 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)2858 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2859 {
2860 __IO uint32_t tmpreg;
2861 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2862 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2863 tmpreg = READ_REG(TIMx->BDTR);
2864 (void)(tmpreg);
2865 }
2866
2867 /**
2868 * @brief Disable the break function.
2869 * @rmtoll BDTR BKE LL_TIM_DisableBRK
2870 * @param TIMx Timer instance
2871 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2872 * a timer instance provides a break input.
2873 * @retval None
2874 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)2875 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2876 {
2877 __IO uint32_t tmpreg;
2878 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2879 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2880 tmpreg = READ_REG(TIMx->BDTR);
2881 (void)(tmpreg);
2882 }
2883
2884 /**
2885 * @brief Configure the break input.
2886 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2887 * a timer instance provides a break input.
2888 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
2889 * @param TIMx Timer instance
2890 * @param BreakPolarity This parameter can be one of the following values:
2891 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
2892 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2893 * @retval None
2894 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)2895 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2896 {
2897 __IO uint32_t tmpreg;
2898 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2899 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
2900 tmpreg = READ_REG(TIMx->BDTR);
2901 (void)(tmpreg);
2902 }
2903
2904 /**
2905 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2906 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2907 * a timer instance provides a break input.
2908 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2909 * BDTR OSSR LL_TIM_SetOffStates
2910 * @param TIMx Timer instance
2911 * @param OffStateIdle This parameter can be one of the following values:
2912 * @arg @ref LL_TIM_OSSI_DISABLE
2913 * @arg @ref LL_TIM_OSSI_ENABLE
2914 * @param OffStateRun This parameter can be one of the following values:
2915 * @arg @ref LL_TIM_OSSR_DISABLE
2916 * @arg @ref LL_TIM_OSSR_ENABLE
2917 * @retval None
2918 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)2919 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2920 {
2921 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
2922 }
2923
2924 /**
2925 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2926 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2927 * a timer instance provides a break input.
2928 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2929 * @param TIMx Timer instance
2930 * @retval None
2931 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)2932 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2933 {
2934 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2935 }
2936
2937 /**
2938 * @brief Disable automatic output (MOE can be set only by software).
2939 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2940 * a timer instance provides a break input.
2941 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2942 * @param TIMx Timer instance
2943 * @retval None
2944 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)2945 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2946 {
2947 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2948 }
2949
2950 /**
2951 * @brief Indicate whether automatic output is enabled.
2952 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2953 * a timer instance provides a break input.
2954 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2955 * @param TIMx Timer instance
2956 * @retval State of bit (1 or 0).
2957 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)2958 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
2959 {
2960 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2961 }
2962
2963 /**
2964 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2965 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2966 * software and is reset in case of break or break2 event
2967 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2968 * a timer instance provides a break input.
2969 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2970 * @param TIMx Timer instance
2971 * @retval None
2972 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)2973 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2974 {
2975 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2976 }
2977
2978 /**
2979 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
2980 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2981 * software and is reset in case of break or break2 event.
2982 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2983 * a timer instance provides a break input.
2984 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
2985 * @param TIMx Timer instance
2986 * @retval None
2987 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)2988 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
2989 {
2990 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2991 }
2992
2993 /**
2994 * @brief Indicates whether outputs are enabled.
2995 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2996 * a timer instance provides a break input.
2997 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
2998 * @param TIMx Timer instance
2999 * @retval State of bit (1 or 0).
3000 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3001 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3002 {
3003 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3004 }
3005
3006 /**
3007 * @}
3008 */
3009
3010 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3011 * @{
3012 */
3013 /**
3014 * @brief Configures the timer DMA burst feature.
3015 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3016 * not a timer instance supports the DMA burst mode.
3017 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3018 * DCR DBA LL_TIM_ConfigDMABurst
3019 * @param TIMx Timer instance
3020 * @param DMABurstBaseAddress This parameter can be one of the following values:
3021 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3022 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3023 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3024 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3025 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3026 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3027 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3028 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3029 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3030 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3031 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3032 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3033 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3034 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3035 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3036 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3037 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3038 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3039 * @param DMABurstLength This parameter can be one of the following values:
3040 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3041 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3042 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3043 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3044 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3045 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3046 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3047 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3048 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3049 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3050 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3051 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3052 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3053 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3054 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3055 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3056 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3057 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3058 * @retval None
3059 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3060 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3061 {
3062 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3063 }
3064
3065 /**
3066 * @}
3067 */
3068
3069 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3070 * @{
3071 */
3072 /**
3073 * @brief Remap TIM inputs (input channel, internal/external triggers).
3074 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3075 * a some timer inputs can be remapped.
3076 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3077 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3078 * TIM11_OR TI1_RMP LL_TIM_SetRemap
3079 * @param TIMx Timer instance
3080 * @param Remap Remap param depends on the TIMx. Description available only
3081 * in CHM version of the User Manual (not in .pdf).
3082 * Otherwise see Reference Manual description of OR registers.
3083 *
3084 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3085 *
3086 * TIM2: one of the following values
3087 *
3088 * ITR1_RMP can be one of the following values
3089 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3090 * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
3091 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3092 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3093 *
3094 * TIM5: one of the following values
3095 *
3096 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3097 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3098 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3099 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3100 *
3101 * TIM11: one of the following values
3102 *
3103 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3104 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1
3105 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
3106 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
3107 *
3108 * @retval None
3109 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3110 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3111 {
3112 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3113 }
3114
3115 /**
3116 * @}
3117 */
3118
3119 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3120 * @{
3121 */
3122 /**
3123 * @brief Clear the update interrupt flag (UIF).
3124 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3125 * @param TIMx Timer instance
3126 * @retval None
3127 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3128 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3129 {
3130 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3131 }
3132
3133 /**
3134 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3135 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3136 * @param TIMx Timer instance
3137 * @retval State of bit (1 or 0).
3138 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3139 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3140 {
3141 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3142 }
3143
3144 /**
3145 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3146 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3147 * @param TIMx Timer instance
3148 * @retval None
3149 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3150 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3151 {
3152 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3153 }
3154
3155 /**
3156 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3157 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3158 * @param TIMx Timer instance
3159 * @retval State of bit (1 or 0).
3160 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3161 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3162 {
3163 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3164 }
3165
3166 /**
3167 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3168 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3169 * @param TIMx Timer instance
3170 * @retval None
3171 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3172 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3173 {
3174 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3175 }
3176
3177 /**
3178 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3179 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3180 * @param TIMx Timer instance
3181 * @retval State of bit (1 or 0).
3182 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3183 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3184 {
3185 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3186 }
3187
3188 /**
3189 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3190 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3191 * @param TIMx Timer instance
3192 * @retval None
3193 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3194 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3195 {
3196 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3197 }
3198
3199 /**
3200 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3201 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3202 * @param TIMx Timer instance
3203 * @retval State of bit (1 or 0).
3204 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3205 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3206 {
3207 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3208 }
3209
3210 /**
3211 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3212 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3213 * @param TIMx Timer instance
3214 * @retval None
3215 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3216 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3217 {
3218 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3219 }
3220
3221 /**
3222 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3223 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3224 * @param TIMx Timer instance
3225 * @retval State of bit (1 or 0).
3226 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)3227 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
3228 {
3229 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3230 }
3231
3232 /**
3233 * @brief Clear the commutation interrupt flag (COMIF).
3234 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3235 * @param TIMx Timer instance
3236 * @retval None
3237 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3238 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3239 {
3240 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3241 }
3242
3243 /**
3244 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3245 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3246 * @param TIMx Timer instance
3247 * @retval State of bit (1 or 0).
3248 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)3249 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
3250 {
3251 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3252 }
3253
3254 /**
3255 * @brief Clear the trigger interrupt flag (TIF).
3256 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3257 * @param TIMx Timer instance
3258 * @retval None
3259 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3260 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3261 {
3262 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3263 }
3264
3265 /**
3266 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3267 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3268 * @param TIMx Timer instance
3269 * @retval State of bit (1 or 0).
3270 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)3271 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
3272 {
3273 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3274 }
3275
3276 /**
3277 * @brief Clear the break interrupt flag (BIF).
3278 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3279 * @param TIMx Timer instance
3280 * @retval None
3281 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3282 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3283 {
3284 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3285 }
3286
3287 /**
3288 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3289 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3290 * @param TIMx Timer instance
3291 * @retval State of bit (1 or 0).
3292 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)3293 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
3294 {
3295 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3296 }
3297
3298 /**
3299 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3300 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3301 * @param TIMx Timer instance
3302 * @retval None
3303 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3304 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3305 {
3306 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3307 }
3308
3309 /**
3310 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3311 * (Capture/Compare 1 interrupt is pending).
3312 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3313 * @param TIMx Timer instance
3314 * @retval State of bit (1 or 0).
3315 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)3316 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
3317 {
3318 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3319 }
3320
3321 /**
3322 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3323 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3324 * @param TIMx Timer instance
3325 * @retval None
3326 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3327 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3328 {
3329 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3330 }
3331
3332 /**
3333 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3334 * (Capture/Compare 2 over-capture interrupt is pending).
3335 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3336 * @param TIMx Timer instance
3337 * @retval State of bit (1 or 0).
3338 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)3339 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
3340 {
3341 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3342 }
3343
3344 /**
3345 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3346 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3347 * @param TIMx Timer instance
3348 * @retval None
3349 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3350 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3351 {
3352 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3353 }
3354
3355 /**
3356 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
3357 * (Capture/Compare 3 over-capture interrupt is pending).
3358 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3359 * @param TIMx Timer instance
3360 * @retval State of bit (1 or 0).
3361 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)3362 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
3363 {
3364 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3365 }
3366
3367 /**
3368 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3369 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3370 * @param TIMx Timer instance
3371 * @retval None
3372 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3373 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3374 {
3375 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3376 }
3377
3378 /**
3379 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
3380 * (Capture/Compare 4 over-capture interrupt is pending).
3381 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3382 * @param TIMx Timer instance
3383 * @retval State of bit (1 or 0).
3384 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)3385 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
3386 {
3387 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3388 }
3389
3390 /**
3391 * @}
3392 */
3393
3394 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3395 * @{
3396 */
3397 /**
3398 * @brief Enable update interrupt (UIE).
3399 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3400 * @param TIMx Timer instance
3401 * @retval None
3402 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3403 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3404 {
3405 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3406 }
3407
3408 /**
3409 * @brief Disable update interrupt (UIE).
3410 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3411 * @param TIMx Timer instance
3412 * @retval None
3413 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3414 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3415 {
3416 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3417 }
3418
3419 /**
3420 * @brief Indicates whether the update interrupt (UIE) is enabled.
3421 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3422 * @param TIMx Timer instance
3423 * @retval State of bit (1 or 0).
3424 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)3425 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
3426 {
3427 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
3428 }
3429
3430 /**
3431 * @brief Enable capture/compare 1 interrupt (CC1IE).
3432 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3433 * @param TIMx Timer instance
3434 * @retval None
3435 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)3436 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3437 {
3438 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3439 }
3440
3441 /**
3442 * @brief Disable capture/compare 1 interrupt (CC1IE).
3443 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3444 * @param TIMx Timer instance
3445 * @retval None
3446 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)3447 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3448 {
3449 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3450 }
3451
3452 /**
3453 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3454 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3455 * @param TIMx Timer instance
3456 * @retval State of bit (1 or 0).
3457 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)3458 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
3459 {
3460 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
3461 }
3462
3463 /**
3464 * @brief Enable capture/compare 2 interrupt (CC2IE).
3465 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3466 * @param TIMx Timer instance
3467 * @retval None
3468 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)3469 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3470 {
3471 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3472 }
3473
3474 /**
3475 * @brief Disable capture/compare 2 interrupt (CC2IE).
3476 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3477 * @param TIMx Timer instance
3478 * @retval None
3479 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)3480 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3481 {
3482 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3483 }
3484
3485 /**
3486 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3487 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3488 * @param TIMx Timer instance
3489 * @retval State of bit (1 or 0).
3490 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)3491 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
3492 {
3493 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
3494 }
3495
3496 /**
3497 * @brief Enable capture/compare 3 interrupt (CC3IE).
3498 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3499 * @param TIMx Timer instance
3500 * @retval None
3501 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)3502 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3503 {
3504 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3505 }
3506
3507 /**
3508 * @brief Disable capture/compare 3 interrupt (CC3IE).
3509 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3510 * @param TIMx Timer instance
3511 * @retval None
3512 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)3513 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3514 {
3515 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3516 }
3517
3518 /**
3519 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3520 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3521 * @param TIMx Timer instance
3522 * @retval State of bit (1 or 0).
3523 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)3524 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
3525 {
3526 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
3527 }
3528
3529 /**
3530 * @brief Enable capture/compare 4 interrupt (CC4IE).
3531 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3532 * @param TIMx Timer instance
3533 * @retval None
3534 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)3535 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3536 {
3537 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3538 }
3539
3540 /**
3541 * @brief Disable capture/compare 4 interrupt (CC4IE).
3542 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3543 * @param TIMx Timer instance
3544 * @retval None
3545 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)3546 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3547 {
3548 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3549 }
3550
3551 /**
3552 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3553 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3554 * @param TIMx Timer instance
3555 * @retval State of bit (1 or 0).
3556 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)3557 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
3558 {
3559 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
3560 }
3561
3562 /**
3563 * @brief Enable commutation interrupt (COMIE).
3564 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3565 * @param TIMx Timer instance
3566 * @retval None
3567 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)3568 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3569 {
3570 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3571 }
3572
3573 /**
3574 * @brief Disable commutation interrupt (COMIE).
3575 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3576 * @param TIMx Timer instance
3577 * @retval None
3578 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)3579 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3580 {
3581 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3582 }
3583
3584 /**
3585 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3586 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3587 * @param TIMx Timer instance
3588 * @retval State of bit (1 or 0).
3589 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)3590 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
3591 {
3592 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
3593 }
3594
3595 /**
3596 * @brief Enable trigger interrupt (TIE).
3597 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3598 * @param TIMx Timer instance
3599 * @retval None
3600 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)3601 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3602 {
3603 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3604 }
3605
3606 /**
3607 * @brief Disable trigger interrupt (TIE).
3608 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3609 * @param TIMx Timer instance
3610 * @retval None
3611 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)3612 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3613 {
3614 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3615 }
3616
3617 /**
3618 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3619 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3620 * @param TIMx Timer instance
3621 * @retval State of bit (1 or 0).
3622 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)3623 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
3624 {
3625 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
3626 }
3627
3628 /**
3629 * @brief Enable break interrupt (BIE).
3630 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3631 * @param TIMx Timer instance
3632 * @retval None
3633 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)3634 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3635 {
3636 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3637 }
3638
3639 /**
3640 * @brief Disable break interrupt (BIE).
3641 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3642 * @param TIMx Timer instance
3643 * @retval None
3644 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)3645 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3646 {
3647 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3648 }
3649
3650 /**
3651 * @brief Indicates whether the break interrupt (BIE) is enabled.
3652 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3653 * @param TIMx Timer instance
3654 * @retval State of bit (1 or 0).
3655 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)3656 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
3657 {
3658 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
3659 }
3660
3661 /**
3662 * @}
3663 */
3664
3665 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
3666 * @{
3667 */
3668 /**
3669 * @brief Enable update DMA request (UDE).
3670 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3671 * @param TIMx Timer instance
3672 * @retval None
3673 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3674 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3675 {
3676 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3677 }
3678
3679 /**
3680 * @brief Disable update DMA request (UDE).
3681 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3682 * @param TIMx Timer instance
3683 * @retval None
3684 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3685 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3686 {
3687 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3688 }
3689
3690 /**
3691 * @brief Indicates whether the update DMA request (UDE) is enabled.
3692 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3693 * @param TIMx Timer instance
3694 * @retval State of bit (1 or 0).
3695 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)3696 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
3697 {
3698 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3699 }
3700
3701 /**
3702 * @brief Enable capture/compare 1 DMA request (CC1DE).
3703 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3704 * @param TIMx Timer instance
3705 * @retval None
3706 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3707 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3708 {
3709 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3710 }
3711
3712 /**
3713 * @brief Disable capture/compare 1 DMA request (CC1DE).
3714 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3715 * @param TIMx Timer instance
3716 * @retval None
3717 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3718 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3719 {
3720 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3721 }
3722
3723 /**
3724 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3725 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3726 * @param TIMx Timer instance
3727 * @retval State of bit (1 or 0).
3728 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)3729 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
3730 {
3731 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3732 }
3733
3734 /**
3735 * @brief Enable capture/compare 2 DMA request (CC2DE).
3736 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3737 * @param TIMx Timer instance
3738 * @retval None
3739 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3740 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3741 {
3742 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3743 }
3744
3745 /**
3746 * @brief Disable capture/compare 2 DMA request (CC2DE).
3747 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3748 * @param TIMx Timer instance
3749 * @retval None
3750 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3751 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3752 {
3753 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3754 }
3755
3756 /**
3757 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3758 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3759 * @param TIMx Timer instance
3760 * @retval State of bit (1 or 0).
3761 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)3762 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
3763 {
3764 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3765 }
3766
3767 /**
3768 * @brief Enable capture/compare 3 DMA request (CC3DE).
3769 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3770 * @param TIMx Timer instance
3771 * @retval None
3772 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3773 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3774 {
3775 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3776 }
3777
3778 /**
3779 * @brief Disable capture/compare 3 DMA request (CC3DE).
3780 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3781 * @param TIMx Timer instance
3782 * @retval None
3783 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3784 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3785 {
3786 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3787 }
3788
3789 /**
3790 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3791 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3792 * @param TIMx Timer instance
3793 * @retval State of bit (1 or 0).
3794 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)3795 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
3796 {
3797 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3798 }
3799
3800 /**
3801 * @brief Enable capture/compare 4 DMA request (CC4DE).
3802 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3803 * @param TIMx Timer instance
3804 * @retval None
3805 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3806 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3807 {
3808 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3809 }
3810
3811 /**
3812 * @brief Disable capture/compare 4 DMA request (CC4DE).
3813 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3814 * @param TIMx Timer instance
3815 * @retval None
3816 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3817 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3818 {
3819 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3820 }
3821
3822 /**
3823 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3824 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3825 * @param TIMx Timer instance
3826 * @retval State of bit (1 or 0).
3827 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)3828 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
3829 {
3830 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3831 }
3832
3833 /**
3834 * @brief Enable commutation DMA request (COMDE).
3835 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3836 * @param TIMx Timer instance
3837 * @retval None
3838 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)3839 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3840 {
3841 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3842 }
3843
3844 /**
3845 * @brief Disable commutation DMA request (COMDE).
3846 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3847 * @param TIMx Timer instance
3848 * @retval None
3849 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)3850 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3851 {
3852 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3853 }
3854
3855 /**
3856 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3857 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3858 * @param TIMx Timer instance
3859 * @retval State of bit (1 or 0).
3860 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)3861 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
3862 {
3863 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
3864 }
3865
3866 /**
3867 * @brief Enable trigger interrupt (TDE).
3868 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3869 * @param TIMx Timer instance
3870 * @retval None
3871 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3872 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3873 {
3874 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3875 }
3876
3877 /**
3878 * @brief Disable trigger interrupt (TDE).
3879 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3880 * @param TIMx Timer instance
3881 * @retval None
3882 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3883 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3884 {
3885 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3886 }
3887
3888 /**
3889 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3890 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3891 * @param TIMx Timer instance
3892 * @retval State of bit (1 or 0).
3893 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)3894 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
3895 {
3896 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3897 }
3898
3899 /**
3900 * @}
3901 */
3902
3903 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3904 * @{
3905 */
3906 /**
3907 * @brief Generate an update event.
3908 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3909 * @param TIMx Timer instance
3910 * @retval None
3911 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3912 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3913 {
3914 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3915 }
3916
3917 /**
3918 * @brief Generate Capture/Compare 1 event.
3919 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3920 * @param TIMx Timer instance
3921 * @retval None
3922 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3923 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3924 {
3925 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3926 }
3927
3928 /**
3929 * @brief Generate Capture/Compare 2 event.
3930 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3931 * @param TIMx Timer instance
3932 * @retval None
3933 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3934 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3935 {
3936 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3937 }
3938
3939 /**
3940 * @brief Generate Capture/Compare 3 event.
3941 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3942 * @param TIMx Timer instance
3943 * @retval None
3944 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)3945 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
3946 {
3947 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
3948 }
3949
3950 /**
3951 * @brief Generate Capture/Compare 4 event.
3952 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
3953 * @param TIMx Timer instance
3954 * @retval None
3955 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)3956 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
3957 {
3958 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
3959 }
3960
3961 /**
3962 * @brief Generate commutation event.
3963 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
3964 * @param TIMx Timer instance
3965 * @retval None
3966 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)3967 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
3968 {
3969 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
3970 }
3971
3972 /**
3973 * @brief Generate trigger event.
3974 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
3975 * @param TIMx Timer instance
3976 * @retval None
3977 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)3978 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
3979 {
3980 SET_BIT(TIMx->EGR, TIM_EGR_TG);
3981 }
3982
3983 /**
3984 * @brief Generate break event.
3985 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
3986 * @param TIMx Timer instance
3987 * @retval None
3988 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)3989 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
3990 {
3991 SET_BIT(TIMx->EGR, TIM_EGR_BG);
3992 }
3993
3994 /**
3995 * @}
3996 */
3997
3998 #if defined(USE_FULL_LL_DRIVER)
3999 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4000 * @{
4001 */
4002
4003 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4004 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4005 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4006 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4007 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4008 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4009 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4010 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4011 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4012 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4013 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4014 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4015 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4016 /**
4017 * @}
4018 */
4019 #endif /* USE_FULL_LL_DRIVER */
4020
4021 /**
4022 * @}
4023 */
4024
4025 /**
4026 * @}
4027 */
4028
4029 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
4030
4031 /**
4032 * @}
4033 */
4034
4035 #ifdef __cplusplus
4036 }
4037 #endif
4038
4039 #endif /* __STM32F2xx_LL_TIM_H */
4040
